Diagrama Xbox360

SCHEMATIC K7

PAGE [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32]

RULES: 1.) 2.) 3.) 4.) 5.) 6.) 7.) 8.) 9.) 10.) 12.) 13.) 14.) 15.)

CONTENTS

PAGE

COVER PAGE CLOCK DIAGRAM RESET/ENABLE DIAGRAM CPU, CLOCKS + EEPROM + STRAPPING CPU, FSB CPU, FSB POWER + PLL POWER CPU, CORE POWER CPU, POWER CPU, DECOUPLING CPU, DECOUPLING CPU, DECOUPLING GPU, FSB GPU, VIDEO + PCIEX + EEPROM GPU, MEMORY CONTROLLER A + B GPU, MEMORY CONTROLLER C + D GPU, PLL POWER + FSB POWER GPU, CORE POWER + MEM POWER GPU, DECOUPLING DUAL ETHERNET PHY MEMORY, A (TOP) MEMORY, A MIRRORED (BOTTOM) MEMORY, B (TOP) MEMORY, B MIRRORED (BOTTOM) MEMORY, C (TOP) MEMORY, C MIRRORED (BOTTOM) MEMORY, D (TOP) MEMORY, D MIRRORED (BOTTOM) ANA, CLOCKS + STRAPPING ANA, VIDEO + FAN + JTAG ANA, POWER + DECOUPLING DEBUG MAPPING, WN DBG VS WN XDK POWER TRACE EMI CAPS

(APPLIED

[33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64]

REV

PB NUMBER X803600-011

XENON RETAIL REV K7 FAB K

XENON

WHEN POSSIBLE)

PLEASE

BOM RELEASE

DATE

SIGNATURE

XENON_FABK

Wed Aug

24

09:41:55

2005

REFER

XX/XX/XX

DATE

TO THE

PB NUMBER

XENON DESIGN

SPEC

X803600-011

DRN BY

MICROSOFT

CHK BY

TITLE

ENGR APVD

DRAWING

PAGE]

BOM RELEASE DATE XX/XX/XX

CONTENTS SB, PCIEX + SMM GPIO + JTAG SB, SMC SB, FLASH + USB + SPI SB, ETHERNET + AUDIO + SATA SB, STANDBY POWER + DECOUPLE SB, MAIN POWER + DECOUPLE SB OUT, ETHERNET SB OUT, AUDIO SB OUT, FLASH SB OUT, FAN + INFRARED + BUTTONS CONN, AVIP CONN, RJ45 + USB COMBO CONN, GAME PORTS + MEMORY PORTS BACKUP CLOCK + V_5P0 DUAL CONN, ODD AND HDD CONN, ARGON + POWER VREGS, INPUT + OUTPUT FILTERS VREGS, CPU CONTROLLER VREGS, GPU OUTPUT PHASE 1,2,3 VREGS, GPU CONTROLLER VREGS, GPU OUTPUT PHASE 1,2 VREGS, SWITCHED 1.8, 5.0V VREGS, LINEAR REGULATORS XDK, DEBUG CONN DEBUG BOARD, CPU + GPU BREAKOUT DEBUG BOARD, CPU CONN DEBUG BOARD, CPU CONN + TERM DEBUG BOARD, CPU TERM DEBUG BOARD, TITAN + YETI CONN DEBUG BOARD, GPU CONN + TERM XDK, LEDS LABELS AND MOUNTING

MSB TO LSB IS TOP TO BOTTOM WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS LANED SIGNALS ARE GROUPED ON SYMBOLS TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE SUFFIX _N FOR ACTIVE LOW OR N JUNCTION SUFFIX _P FOR P JUNCTION SUFFIX _EN FOR ENABLE 'CLK' FOR CLOCKS, 'RST' FOR RESETS PWRGD FOR POWER GOOD

[PAGE_TITLE=COVER

VER RETAIL

SCH,

APVD

MICROSOFT

APVD

CONFIDENTIAL

PBA,

XBOX XENON

PROJECT NAME XENON_RETAIL

PAGE 1/73

REV K7

RJ45/USB CONN

AVIP CONN

POWER CONN

FAN CONN

CLOCK DIAGRAM

ENET_CLK(25MHZ)

ENET PHY

I2S_MCLK(12.288MHZ) I2S_BCLK(3.072MHZ)

ANA_XTAL_IN(27MHZ)

AUDIO DAC

GPU VR

DEBUG CONN ANA BCKUP

SB DVD SATA CONN

ANA GPU VR CNTL

STBY_CLK(48MHZ) SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) PCIEX_CLK_DP/DN(100MHZ) AUD_CLK(24.576MHZ) CPU_CLK_DP/DN(100MHZ) GPU_CLK_DP/DN

DVD PWR CONN ANA BCKUP

VR FLSH

HDD CONN

3P3

CPU

GPU MA_CLK1_DP/DN(800MHZ) MA_CLK0_DP/DN(800MHZ) MB_CLK1_DP/DN(800MHZ) MB_CLK0_DP/DN(800MHZ)

1P8

MEM CLAM C+D

MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ) MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ)

RISCWATCH CONN

PIX_CLK_OUT_DP/DN(100MHZ) (100MHZ)

TITAN CONN

VR VMEM VR 5P0

MPORT VR

MEM CLAM A+B

EFUSE

CPU VR

JTAG

VR

CPU VR CNTL

VR

GAME CONN IR

MEM CONN

EJECT SW


DIAGRAM>

MEM CONN

BIND SW

ARGON CONN

DRAWING XENON_FABK Wed Jul 27 21:53:30

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 2/73

REV K7

RJ45/USB CONN

AVIP CONN

POWER CONN

FAN CONN

ENET PHY

ENET_RST_N

EXT_PWR_ON_N

RESET/ENABLE AUD_CLAMP AUD_RST_N

DIAGRAM

AUDIO DAC

PSU_V12P0_EN

GPU VR ANA_CLK_OE ANA_RST_N

ANA

VREG_GPU_EN_N

GPU VR CNTL

SB_RST_N

SMC_RST_N DVD SATA CONN

SB

VREG_GPU_PWRGD EXT_PWR_ON_N CPU_CHECKSTOP_N CPU_RST_N CPU_PWRGD GPU_RST_N

RISCWATCH CONN

VREG_CPU_PWRGD

HDD CONN

MEM CLAM C+D

MEM_RST MEM_SCAN_EN MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN

3P3 VR

DEBUG CONN

CPU VR

GPU

CPU

MEM_RST MEM_SCAN_EN MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN

SMC_DBG_EN

GPU_RST_DONE

VREG_3P3_EN

DVD PWR CONN

VREG_1P8_EN_N VREG_5P0_EN_N

CPU_PWRGD TITAN CONN

MEM CLAM A+B VMEM VR 5P0

EFUSE

JTAG

VR

CPU VR CNTL

VR VREG_EFUSE_EN VREG_CPU_EN

GAME CONN IR

EJECT SW

[PAGE_TITLE=RESET/ENABLE

MEM CONN

MEM CONN

DIAGRAM]

BIND SW

ARGON CONN

DRAWING XENON_FABK Wed Jul 27 21:53:44

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 3/73

REV K7

56 34

34

CPU_RST_V1P1_N

OUT

FT2P11

FTP

FT2P12

FTP

3.92K 402

1

R7R10

1

V_GPUCORE

2

R6R4

2

R6R6

R6R9

2

1K 402

10K 5% CH 402

2

IN

46

IN

CPU_CLK_DN

1% CH

1

CPU VERSION

2

2

10K 5% CH 402

R7R17

2

10K 5% CH 402

1

1

R7D1

2

AJ25 AH25

CORE_CLK_DP CORE_CLK_DN

AJ2 AF16

HARD_RESET_B POWER_GOOD

AK23 AK22

FSB_CLK_DP FSB_CLK_DN

CPU_FSB_CLK_SEL

AG18

FSB_CLK_SEL

FSB_CLK_DP FSB_CLK_DN

1

R6R7

10K 5% CH 402

CPU_EXT_CLK_EN

AF18

EXT_CLK_EN

CPU_PLL_BYPASS

AH16

PLL_BYPASS

CPU_PULSE_LIMIT_BYPASS

AJ16

PULSE_LIMIT_BYPASS

R7R24 2

AG16

TRIGGER_IN

10K 402

V_GPUCORE

CPU_TRIGGER_IN

CPU_SYS_CONFIG0 CPU_SYS_CONFIG1

2

LAYOUT:

R7R8

10K 5% EMPTY 402

10K 5% EMPTY 402

2

TP6R1 PROBE 1

4

1 1 1

R7R6

2

10K 5% CH 402

2

R7R7

2

CPU_ANL_1

2 SMT

MUST BE ACCESSIBLE

10K 5% CH 402

AK17

CPU_CORE_IF_BGR_PLL

C6

VREG_EFUSE_EN

FSB_HF_CLKOUT_DP FSB_HF_CLKOUT_DN

AH22 AJ22

CPU_FSB_HF_CLKOUT_DP CPU_FSB_HF_CLKOUT_DN

FSB_IMPED_CAL_DP FSB_IMPED_CAL_DN

AK25 AK24

CPU_FSB_IMPED_CAL_DP CPU_FSB_IMPED_CAL_DN

AK14 AK15

CPU_RES0_DP CPU_RES0_DN

VDDS0_DP VDDS0_DN

AH13 AK12

CPU_VDDS0_DP CPU_VDDS0_DN

VDDS1_DP VDDS1_DN

AJ4 AK5

CPU_VDDS1_DP CPU_VDDS1_DN

AK16

CPU_PSRO0_OUT

CORE_IF_BGR_PLL

EFU_POWERON

2

C6R46

10UF 10% 6.3V EMPTY 1206

R6R10

5.11K 402

2

CPU_TEST_EN

TEMP_P TEMP_N

ANL_1 ANL_2 SPARE0 SPARE1

AH4

TE

VID0 VID1 VID2 VID3 VID4 VID5

SMT

2

1

1

1

1

R7R12

R7R13

R7R22

R7R23

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

2

0

1

2

1

R7R21

2

1

2

2

1

1

2

3

2

1

2

2

1

R7R3

R7R19

R7R18

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

2

FT7R4 FT7R6 FT7R2 FT7R1 FT7R5

IN

CPU_TEMP_P CPU_TEMP_N

C4 B5 A4 B4 A5 C5

CPU_VREG_APS0 CPU_VREG_APS1 CPU_VREG_APS2 CPU_VREG_APS3 CPU_VREG_APS4 CPU_VREG_APS5

FTP FTP FTP FTP FTP

1 1 1 1 1

J7F1 2X3HDR 1 3 5

R6E2

CPU_SPI_CLK

IN

V_MEM

1K 402

FTP FTP FTP

CPU_SPI_SI CPU_SPI_WP_N

2 4 6

PROBE

DB7R1 TP

5% CH

CPU_SPI_CLK_R CPU_SPI_SO_R

CPU_SPI_EN_R

OUT OUT

4 4

IN OUT

29 29

1 1 1

FT7T2 FT7T1 FT7T7

OUT OUT

4 4

2

SCK SDI HOLD_N* CS_N* WP_N*

VCC

8

SDO

2

R6E1

OUT OUT OUT OUT OUT OUT

49 49 49 49 49 49

FTP FTP FTP

FT7T5 FT7T4 FT7T3

10K 5% CH 402

1

C6F1

1

.1UF 10% 6.3V X5R 402

R7F3 10K 5% EMPTY 402

2

2

CPU_SPI_SI_R

X800552-001

1

10K 402

R7U3

IN

CPU_SPI_EN

2

10K 5% CH 402

2

R7F2

+ EEPROM + STRAPPING]

10K 402

1 2

5% CH

R7F1

R7F7

1

CPU_SPI_SI

OUT

4

5% CH

R7F4

V_MEM R7E8

1K 402

1

4

GND

2

10K 5% CH 402

V_MEM

1

7 1 3

2

V_MEM

IC

6 5

4

OUT

AT25020A

2

1K 402

CLOCKS

5% CH

R7E7

CPU_SPI_SO

4 3 2 1 0

4

[PAGE_TITLE=CPU,

1 1 1

X02046-002

10K 5% CH 402

1K 402 4

TP7R2 1 2

1

EMPTY

4

PROBE

SMT

AK20 AK21

U7E1

R7R5

2

0 5% EMPTY 402

TP7R4 1 2

V_MEM

10K 5% EMPTY 402

2

R7R2

0 5% EMPTY 402

2

PROBE

CPU_SPI_CLK CPU_SPI_EN CPU_SPI_SO

4

R7R20

2

1

R7R1

1.07K 1% CH 402

1 2

A2 B2 A3

1

1

1

OUT OUT

R6D2

931 1% CH 402

R7R9 SPI_CLK SPI_EN SPI_SO

AK1 AJ1

R7R14

1

R6D1

1

SPI_SI

AG24 AF24

CPU_SPARE0 CPU_SPARE1

PROBE 1

B3

PSRO0_OUT

1

CPU_ANL_2

2 SMT

55

OUT

SMT POST_IN0 POST_IN1 POST_IN2 POST_IN3 POST_IN4

CPU_ANL_1_R

1% EMPTY

PROBE 1 2

TP7R3 RESISTOR0_DP RESISTOR0_DN

SYS_CONFIG0 SYS_CONFIG1

AH10 AJ10 AK9 AK10 AK11

CPU_SPI_SI

IN

TP6R2

V_GPUCORE

TP7R1

SMT

AK3 AH1 0 1 2 3 4

OUT

1

R7R15

IC 20

5% CH

CPU_POST_IN<0..4>

1

1 OF 10

U7D1

1

10K 5% EMPTY 402

WITH ZERO OHM R'S FOR WN WITH .01UF CAPS FOR SHIVA

V_GPUCORE

360PF 10% 50V NPO 603

2

PROBE

SMT

STUFF C?,C? STUFF C?,C?

C7R113

1

R6R8

N: N:

TP6D1 1 2

5% CH

1K 402

1

1

5% CH

R6R5

2

10K 5% EMPTY 402

C7R112

CPU_CLK_DP

360PF 10% 50V NPO 603

2

R7R11 2

1

6.19K 402

1

1

1% CH

CLOCKS + EEPROM + STRAPPING

46

CPU_PWRGD_V1P1_N

1% CH

V_GPUCORE

1

R7R16 2

1

6.19K 402

3.92K 402

CPU,

2

1% CH

1

CPU_PWRGD

IN

R7R4

1

CPU_RST_N

IN

100 5% CH 402

1

5% EMPTY

CPU_SPI_WP_N

IN

4

5% CH

DRAWING XENON_FABK Wed Aug 24 09:27:00

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 4/73

REV K7

CPU,

U7D1

FSB

2 OF 10 CPU VERSION

12 12

IN IN

12 12

IN IN

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

12 12

IN IN

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

FSB_GP_CP0_CLK_DP FSB_GP_CP0_CLK_DN

Y30 Y29 AD29 AD30

GP_CP0_FLAG_DP GP_CP0_FLAG_DN

FSB_GP_CP0_DATA0_DP FSB_GP_CP0_DATA0_DN FSB_GP_CP0_DATA1_DP FSB_GP_CP0_DATA1_DN FSB_GP_CP0_DATA2_DP FSB_GP_CP0_DATA2_DN FSB_GP_CP0_DATA3_DP FSB_GP_CP0_DATA3_DN FSB_GP_CP0_DATA4_DP FSB_GP_CP0_DATA4_DN FSB_GP_CP0_DATA5_DP FSB_GP_CP0_DATA5_DN FSB_GP_CP0_DATA6_DP FSB_GP_CP0_DATA6_DN FSB_GP_CP0_DATA7_DP FSB_GP_CP0_DATA7_DN

V28 V27 V30 V29 W29 W30 Y28 Y27 AA29 AA30 AB28 AB27 AB30 AB29 AC29 AC30

GP_CP0_DATA0_DP GP_CP0_DATA0_DN GP_CP0_DATA1_DP GP_CP0_DATA1_DN GP_CP0_DATA2_DP GP_CP0_DATA2_DN GP_CP0_DATA3_DP GP_CP0_DATA3_DN GP_CP0_DATA4_DP GP_CP0_DATA4_DN GP_CP0_DATA5_DP GP_CP0_DATA5_DN GP_CP0_DATA6_DP GP_CP0_DATA6_DN GP_CP0_DATA7_DP GP_CP0_DATA7_DN

FSB_GP_CP1_CLK_DP FSB_GP_CP1_CLK_DN

CP_GP0_CLK_DP CP_GP0_CLK_DN

AG29 AG30

FSB_CP_GP0_CLK_DP FSB_CP_GP0_CLK_DN

CP_GP0_FLAG_DP CP_GP0_FLAG_DN

AK27 AK28

FSB_CP_GP0_FLAG_DP FSB_CP_GP0_FLAG_DN

CP_GP0_DATA0_DP CP_GP0_DATA0_DN CP_GP0_DATA1_DP CP_GP0_DATA1_DN CP_GP0_DATA2_DP CP_GP0_DATA2_DN CP_GP0_DATA3_DP CP_GP0_DATA3_DN CP_GP0_DATA4_DP CP_GP0_DATA4_DN CP_GP0_DATA5_DP CP_GP0_DATA5_DN CP_GP0_DATA6_DP CP_GP0_DATA6_DN CP_GP0_DATA7_DP CP_GP0_DATA7_DN

AD28 AD27 AE29 AE30 AF30 AF29 AF27 AF28 AH30 AH29 AH27 AH28 AJ29 AJ30 AK30 AK29

CP_GP1_CLK_DP CP_GP1_CLK_DN

GP_CP0_CLK_DP GP_CP0_CLK_DN

FSB_GP_CP0_FLAG_DP FSB_GP_CP0_FLAG_DN

G30 G29

GP_CP1_CLK_DP GP_CP1_CLK_DN

FSB_GP_CP1_FLAG_DP FSB_GP_CP1_FLAG_DN

L28 L27

GP_CP1_FLAG_DP GP_CP1_FLAG_DN

FSB_GP_CP1_DATA0_DP FSB_GP_CP1_DATA0_DN FSB_GP_CP1_DATA1_DP FSB_GP_CP1_DATA1_DN FSB_GP_CP1_DATA2_DP FSB_GP_CP1_DATA2_DN FSB_GP_CP1_DATA3_DP FSB_GP_CP1_DATA3_DN FSB_GP_CP1_DATA4_DP FSB_GP_CP1_DATA4_DN FSB_GP_CP1_DATA5_DP FSB_GP_CP1_DATA5_DN FSB_GP_CP1_DATA6_DP FSB_GP_CP1_DATA6_DN FSB_GP_CP1_DATA7_DP FSB_GP_CP1_DATA7_DN

E28 E27 E30 E29 F29 F30 G28 G27 H29 H30 J28 J27 J30 J29 K29 K30

GP_CP1_DATA0_DP GP_CP1_DATA0_DN GP_CP1_DATA1_DP GP_CP1_DATA1_DN GP_CP1_DATA2_DP GP_CP1_DATA2_DN GP_CP1_DATA3_DP GP_CP1_DATA3_DN GP_CP1_DATA4_DP GP_CP1_DATA4_DN GP_CP1_DATA5_DP GP_CP1_DATA5_DN GP_CP1_DATA6_DP GP_CP1_DATA6_DN GP_CP1_DATA7_DP GP_CP1_DATA7_DN

IC 20

OUT OUT

12 12

OUT OUT

12 12

FSB_CP_GP0_DATA0_DP FSB_CP_GP0_DATA0_DN FSB_CP_GP0_DATA1_DP FSB_CP_GP0_DATA1_DN FSB_CP_GP0_DATA2_DP FSB_CP_GP0_DATA2_DN FSB_CP_GP0_DATA3_DP FSB_CP_GP0_DATA3_DN FSB_CP_GP0_DATA4_DP FSB_CP_GP0_DATA4_DN FSB_CP_GP0_DATA5_DP FSB_CP_GP0_DATA5_DN FSB_CP_GP0_DATA6_DP FSB_CP_GP0_DATA6_DN FSB_CP_GP0_DATA7_DP FSB_CP_GP0_DATA7_DN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

P30 P29

FSB_CP_GP1_CLK_DP FSB_CP_GP1_CLK_DN

OUT OUT

12 12

CP_GP1_FLAG_DP CP_GP1_FLAG_DN

U30 U29

FSB_CP_GP1_FLAG_DP FSB_CP_GP1_FLAG_DN

OUT OUT

12 12

CP_GP1_DATA0_DP CP_GP1_DATA0_DN CP_GP1_DATA1_DP CP_GP1_DATA1_DN CP_GP1_DATA2_DP CP_GP1_DATA2_DN CP_GP1_DATA3_DP CP_GP1_DATA3_DN CP_GP1_DATA4_DP CP_GP1_DATA4_DN CP_GP1_DATA5_DP CP_GP1_DATA5_DN CP_GP1_DATA6_DP CP_GP1_DATA6_DN CP_GP1_DATA7_DP CP_GP1_DATA7_DN

L30 L29 M30 M29 N27 N28 N30 N29 R27 R28 R30 R29 T30 T29 U27 U28

FSB_CP_GP1_DATA0_DP FSB_CP_GP1_DATA0_DN FSB_CP_GP1_DATA1_DP FSB_CP_GP1_DATA1_DN FSB_CP_GP1_DATA2_DP FSB_CP_GP1_DATA2_DN FSB_CP_GP1_DATA3_DP FSB_CP_GP1_DATA3_DN FSB_CP_GP1_DATA4_DP FSB_CP_GP1_DATA4_DN FSB_CP_GP1_DATA5_DP FSB_CP_GP1_DATA5_DN FSB_CP_GP1_DATA6_DP FSB_CP_GP1_DATA6_DN FSB_CP_GP1_DATA7_DP FSB_CP_GP1_DATA7_DN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

X02046-002

V_GPUCORE

1 2

[PAGE_TITLE=CPU,

FSB]

C6R14 .1UF 10% 6.3V X5R 402

1 2

C6R25 .1UF 10% 6.3V X5R 402

1 2

C6R37

.1UF 10% 6.3V X5R 402

1 2

C6T19

.1UF 10% 6.3V X5R 402

1 2

C6T7

.1UF 10% 6.3V X5R 402

1 2

C6T27 .1UF 10% 6.3V X5R 402

1 2

C6T33

.1UF 10% 6.3V X5R 402

1 2

C6T32 .1UF 10% 6.3V X5R 402

1 2

C6R6 .1UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:01

MICROSOFT 2005

CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 5/73

REV K7

CPU,

FSB POWER + PLL

POWER

V_1P8 V_GPUCORE

V_CPUPLL

U7D1

FB7R1 1

1 2

C7R1

1 2

FB 603

1K 0.2A 0.7DCR

2

1

.1UF 10% 6.3V X5R 402

C7R7

2

C7R116

.1UF 10% 6.3V X5R 402

1

4 of

ST7R1 2

V_EFUSE

SHORT

2

FB6D1 1

1 2

C6D1

10K 402

2

R7T2

1

CPU_VDDE

5% CH

FB 603

1K 0.2A 0.7DCR

1

.1UF 10% 6.3V X5R 402

2.2UF 10% 6.3V X5R 603

2

V_CPU_CORE_HF_VDDA_PLL V_CPU_CORE_HF_GNDA_PLL

ST6D1 2

1

V_CPU_CORE_IF_VDDA_PLL V_CPU_CORE_IF_GNDA_PLL

SHORT

V_CPU_FSB_HF_VDDA_PLL V_CPU_FSB_HF_GNDA_PLL

FB6R1 1

1 2

C6R2

V_CPU_FSB_IF_VDDA_PLL

2

V_CPU_FSB_IF_GNDA_PLL

FB 603

1K 0.2A 0.7DCR

V_CPU_VDDA_RNG

1

.1UF 10% 6.3V X5R 402

V_CPU_GNDA_RNG

C6R4

VDD_IO VDDE VDDE_SEC

AJ19 AH19

CORE_HF_VDDA_PLL CORE_HF_GNDA_PLL

AK19 AK18

CORE_IF_VDDA_PLL CORE_IF_GNDA_PLL

AF22 AG22

FSB_HF_VDDA_PLL FSB_HF_GNDA_PLL

AF20 AG20

FSB_IF_VDDA_PLL FSB_IF_GNDA_PLL

AK13 AJ13

VDDA_RNG GNDA_RNG

2.2UF 10% 6.3V X5R 603

2 ST6R1 2

1

AK6 A6 B6

C6D4

SHORT

FB6R2 1

1 2

C6R3

2 FB 603

1K 0.2A 0.7DCR

1

.1UF 10% 6.3V X5R 402

2 1

ST6R2 2

10

CPU VERSION

C7R114

.1UF 10% 6.3V X5R 402

2

2.2UF 10% 6.3V X5R 603

2 1

C7R115

.1UF 10% 6.3V X5R 402

1

IC 20 VDD_FSB0 VDD_FSB1 VDD_FSB2 VDD_FSB3 VDD_FSB4 VDD_FSB5 VDD_FSB6 VDD_FSB7 VDD_FSB8 VDD_FSB9 VDD_FSB10 VDD_FSB11 VDD_FSB12 VDD_FSB13 VDD_FSB14 VDD_FSB15 VDD_FSB16 VDD_FSB17 VDD_FSB18 VDD_FSB19 VDD_FSB20 VDD_FSB21 VDD_FSB22 VDD_FSB23 VDD_FSB24 VDD_FSB25 VDD_FSB26 VDD_FSB27 VDD_FSB28 VDD_FSB29 VDD_FSB30 VDD_FSB31 VDD_FSB32 VDD_FSB33 VDD_FSB34 VDD_FSB35 VDD_FSB36 VDD_FSB37 VDD_FSB38 VDD_FSB39 VDD_FSB40 VDD_FSB41 VDD_FSB42 VDD_FSB43 VDD_FSB44 VDD_FSB45 VDD_FSB46

AA27 AB26 AC27 AD26 AE27 AF26 AG27 AH26 AJ27 AK26 B9 B12 B15 B18 B21 B24 B27 C8 C11 C14 C17 C20 C23 C26 D10 D13 D17 D21 D25 D27 D29 E26 F27 G26 H27 J26 K27 L26 M27 N26 P27 R26 T27 U26 V26 W27 Y26

C6R5 2.2UF 10% 6.3V X5R 603

X02046-002

SHORT

FB7D1 1

1 2

C7D1

2

1K 0.2A 0.7DCR

FB 603

1

1UF 10% 50V EMPTY 603

2 1

ST7D1 2

C7D2 2.2UF 10% 6.3V X5R 603

SHORT

[PAGE_TITLE=CPU,

FSB

POWER + PLL

POWER]

DRAWING XENON_FABK Wed Aug 24 09:27:01

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 6/73

REV K7

CPU, V_CPUCORE

U7D1

AA2 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA24 AB1 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC2 AC4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AD1 AD3 AD5 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD21

V_CPUCORE

IC 5 of

VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47

V_CPUCORE

V_CPUCORE U7D1

10

CPU VERSION

6 of

AD23 AD25 AE2 AE4 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE22 AE24 AF1 AF3 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF23 AF25 AG2 AG4 AG6 AG8 AG10 AG12 AG14 AH3 AH6 AH9 AH12 AH15 AJ5 AJ8 AJ11 AJ14 B1 C2 D1 D3 D5

D7 D9 E2 E4 E6 E8 E10 F1 F3 F5 F7 F9 F11 G2 G4 G6 G8 G10 G12 G14 G16 G18 G20 G22 G24 H1 H3 H5 H7 H9 H11 H13 H15 H17 H19 H21 H23 H25 J2 J4 J6 J8 J10 J12 J14 J16 J18

VDD96 VDD97 VDD98 VDD99 VDD100 VDD101 VDD102 VDD103 VDD104 VDD105 VDD106 VDD107 VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130 VDD131 VDD132 VDD133 VDD134 VDD135 VDD136 VDD137 VDD138 VDD139 VDD140 VDD141 VDD142 X02046-002

V_CPUCORE

U7D1

IC

10

CPU VERSION

20 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82 VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90 VDD91 VDD92 VDD93 VDD94 VDD95

CORE POWER

VDD143 VDD144 VDD145 VDD146 VDD147 VDD148 VDD149 VDD150 VDD151 VDD152 VDD153 VDD154 VDD155 VDD156 VDD157 VDD158 VDD159 VDD160 VDD161 VDD162 VDD163 VDD164 VDD165 VDD166 VDD167 VDD168 VDD169 VDD170 VDD171 VDD172 VDD173 VDD174 VDD175 VDD176 VDD177 VDD178 VDD179 VDD180 VDD181 VDD182 VDD183 VDD184 VDD185 VDD186 VDD187 VDD188 VDD189

10

CPU VERSION J20 J22 J24 K1 K3 K5 K7 K9 K11 K13 K15 K17 K19 K21 K23 K25 L2 L4 L6 L8 L10 L12 L14 L16 L18 L20 L22 L24 M1 M3 M5 M7 M9 M11 M13 M15 M17 M19 M21 M23 M25 N2 N4 N6 N8 N10 N12

N14 N16 N18 N20 N22 N24 P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 T1 T3 T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 U2 U4 U6

V_CPUCORE

IC 7 of

20

VDD190 VDD191 VDD192 VDD193 VDD194 VDD195 VDD196 VDD197 VDD198 VDD199 VDD200 VDD201 VDD202 VDD203 VDD204 VDD205 VDD206 VDD207 VDD208 VDD209 VDD210 VDD211 VDD212 VDD213 VDD214 VDD215 VDD216 VDD217 VDD218 VDD219 VDD220 VDD221 VDD222 VDD223 VDD224 VDD225 VDD226 VDD227 VDD228 VDD229 VDD230 VDD231 VDD232 VDD233 VDD234 VDD235 VDD236

20 VDD237 VDD238 VDD239 VDD240 VDD241 VDD242 VDD243 VDD244 VDD245 VDD246 VDD247 VDD248 VDD249 VDD250 VDD251 VDD252 VDD253 VDD254 VDD255 VDD256 VDD257 VDD258 VDD259 VDD260 VDD261 VDD262 VDD263 VDD264 VDD265 VDD266 VDD267 VDD268 VDD269 VDD270 VDD271 VDD272 VDD273 VDD274 VDD275 VDD276 VDD277 VDD278 VDD279 VDD280 VDD281 VDD282 VDD283

U8 U10 U12 U14 U16 U18 U20 U22 U24 V1 V3 V5 V7 V9 V11 V13 V15 V17 V19 V21 V23 V25 W2 W4 W6 W8 W10 W12 W14 W16 W18 W20 W22 W24 Y1 Y3 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25

X02046-002

X02046-002

[PAGE_TITLE=CPU,

CORE POWER]

DRAWING XENON_FABK Wed Aug 24 09:27:01

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 7/73

REV K7

CPU,

U7D1

U7D1

IC 8 of

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

AE9 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE26 AE28 AF2 AF4 AF6 AF8 AF10 AF12 AF14 AG1 AG3 AG5 AG7 AG9 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG26 AG28 AH2 AH5 AH8 AH11 AH14 AH17 AH18 AH20 AH21 AH23 AH24 AJ3 AJ6 AJ9 AJ12 AJ15 AJ17 AJ18 AJ20 AJ21 AJ23 AJ24 AJ26 AJ28 B8 B11

B14 B17 B20 B23 B26 B29 C1 C3 C9 C12 C15 C18 C21 C24 C27 D2 D4 D6 D8 D11 D15 D19 D23 D26 D28 D30 E1 E3 E5 E7 E9 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25

VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 X02046-002

U7D1

10

CPU VERSION

20

VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116

IC 9 of

10

CPU VERSION AA1 AA3 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA26 AA28 AB2 AB4 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC1 AC3 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC25 AC26 AC28 AD2 AD4 AD6 AD8 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AE1 AE3 AE5 AE7

POWER

IC 10

20

VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232

of

10

CPU VERSION H2 H4 H6 H8 H10 H12 H14 H16 H18 H20 H22 H24 H26 H28 J1 J3 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 J25 K2 K4 K6 K8 K10 K12 K14 K16 K18 K20 K22 K24 K26 K28 L1 L3 L5 L7 L9 L11 L13 L15 L17 L19 L21 L23 L25 M2 M4 M6 M8

M10 M12 M14 M16 M18 M20 M22 M24 M26 M28 N1 N3 N5 N7 N9 N11 N13 N15 N17 N19 N21 N23 N25 P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 R1 R3 R5 R7 R9 R11 R13 R15 R17 R19 R21 R23 R25 T2 T4 T6 T8 T10 T12 T14 T16

20

VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348

VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290

T18 T20 T22 T24 T26 T28 U1 U3 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 U25 V2 V4 V6 V8 V10 V12 V14 V16 V18 V20 V22 V24 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 W21 W23 W25 W26 W28 Y2 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24

X02046-002

X02046-002

[PAGE_TITLE=CPU,

POWER]

DRAWING XENON_FABK Wed Aug 24 09:27:02

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 8/73

REV K7

V_CPUCORE

V_CPUCORE

CPU,

1

C7D21

2

4.7UF 10% 6.3V X5R 805

1

C7T94

2

4.7UF 10% 6.3V X5R 805

1

C7T101

2

4.7UF 10% 6.3V X5R 805

1

C7T87

2

4.7UF 10% 6.3V X5R 805

1

C7R2

2

4.7UF 10% 6.3V X5R 805

1

C7E3

2

4.7UF 10% 6.3V X5R 805

1

C7T32

2

4.7UF 10% 6.3V X5R 805

1

C7R28

2

4.7UF 10% 6.3V X5R 805

1

C7D20

2

4.7UF 10% 6.3V X5R 805

C7R122

1

2

4.7UF 10% 6.3V X5R 805

1

C7E8

2

4.7UF 10% 6.3V X5R 805

1

C7E14

2

4.7UF 10% 6.3V X5R 805

1

C7T93

2

4.7UF 10% 6.3V X5R 805

1

C7D16

2

4.7UF 10% 6.3V X5R 805

1

C7E12

2

4.7UF 10% 6.3V X5R 805

1

C7E10

2

4.7UF 10% 6.3V X5R 805

1

C7E11

2

4.7UF 10% 6.3V X5R 805

1

C7T33

2

4.7UF 10% 6.3V X5R 805

[PAGE_TITLE=CPU,

1

C7T85

2

4.7UF 10% 6.3V X5R 805

1

C7E6

2

4.7UF 10% 6.3V X5R 805

1

C7D12

2

4.7UF 10% 6.3V X5R 805

1

C7D19

C7T36

2

4.7UF 10% 6.3V X5R 805

1

C7R118

2

4.7UF 10% 6.3V X5R 805

1

C7E5

2

4.7UF 10% 6.3V X5R 805

1

C7D14

2

4.7UF 10% 6.3V X5R 805

1

C7R121

C7R6

2

4.7UF 10% 6.3V X5R 805

DECOUPLING]

2

1

C7R94

2

4.7UF 10% 6.3V X5R 805

1

C7E1

2

4.7UF 10% 6.3V X5R 805 C7R119

2

4.7UF 10% 6.3V X5R 805

1

1

4.7UF 10% 6.3V X5R 805

1

2

4.7UF 10% 6.3V X5R 805

1

C7E7

2

4.7UF 10% 6.3V X5R 805

1

C7D13

2

4.7UF 10% 6.3V X5R 805

1

C7T83

2

4.7UF 10% 6.3V X5R 805

1

C7D11

2

4.7UF 10% 6.3V X5R 805

1

C7T84

2

4.7UF 10% 6.3V X5R 805

DECOUPLING

1

C7D9

2

4.7UF 10% 6.3V X5R 805

1

C7R5

2

4.7UF 10% 6.3V X5R 805

1

C7T34

2

4.7UF 10% 6.3V X5R 805

1

C7R26

2

4.7UF 10% 6.3V X5R 805

1

C7R117

2

4.7UF 10% 6.3V X5R 805

1

C7T96

2

4.7UF 10% 6.3V X5R 805

1

C7R92

2

4.7UF 10% 6.3V X5R 805

1

C7D6

2

4.7UF 10% 6.3V X5R 805

1

C7D17

2

4.7UF 10% 6.3V X5R 805

1

C7R27

2

4.7UF 10% 6.3V X5R 805

1

C7D8

2

4.7UF 10% 6.3V X5R 805

1

C7D4

2

4.7UF 10% 6.3V X5R 805

1

C7D18

2

4.7UF 10% 6.3V X5R 805

1

C7D7

2

4.7UF 10% 6.3V X5R 805

1

C7E16

2

4.7UF 10% 6.3V X5R 805

1

C7R91

2

4.7UF 10% 6.3V X5R 805

1

C7R29

2

4.7UF 10% 6.3V X5R 805

1

C7E4

2

4.7UF 10% 6.3V X5R 805

1

C7D10

2

4.7UF 10% 6.3V X5R 805

1

C7R4

2

4.7UF 10% 6.3V X5R 805

1

C7T35

2

4.7UF 10% 6.3V X5R 805

1

C7D5

2

4.7UF 10% 6.3V X5R 805

1

C7R93

2

4.7UF 10% 6.3V X5R 805

1

C7T95

2

4.7UF 10% 6.3V X5R 805

1

C7D3

2

4.7UF 10% 6.3V X5R 805

1

C7R120

2

4.7UF 10% 6.3V X5R 805

1

C7D15

2

4.7UF 10% 6.3V X5R 805

1

C7R3

2

1

4.7UF 10% 6.3V X5R 805

1

C7R30

2

1

4.7UF 10% 6.3V X5R 805

1

C7R90

C7E2

2

1

2 1

C7E15

C7E9

2

C7T86

1

2

C7T97

1

2

C7D22

1

2

C7T45

2

1

C7R16

2

.1UF 10% 6.3V X5R 402

2

C7T88

2

C7R12

2

C7R10

2

1

C7R11

2

.1UF 10% 6.3V X5R 402

2

1

4.7UF 10% 6.3V X5R 805

DRAWING XENON_FABK Wed Aug 24 09:27:03

C7T76

1

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

4.7UF 10% 6.3V X5R 805

1

2

2

.1UF 10% 6.3V X5R 402

4.7UF 10% 6.3V X5R 805

1

C7T77

C7T1

.1UF 10% 6.3V X5R 402

4.7UF 10% 6.3V X5R 805

1

2

1

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

4.7UF 10% 6.3V X5R 805

1

C7T78

.1UF 10% 6.3V X5R 402

4.7UF 10% 6.3V X5R 805

1

2

.1UF 10% 6.3V X5R 402

4.7UF 10% 6.3V X5R 805

1

C7T79

.1UF 10% 6.3V X5R 402

C7R13

2

.1UF 10% 6.3V X5R 402

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 9/73

REV K7

V_CPUCORE

CPU,

1

C7R36

2

.1UF 10% 6.3V X5R 402

1

C7R22

2

.1UF 10% 6.3V X5R 402

1

C7R23

2

.1UF 10% 6.3V X5R 402

1

C7R24

2

.1UF 10% 6.3V X5R 402

1

C7R25

2

.1UF 10% 6.3V X5R 402

1

C7R38

2

.1UF 10% 6.3V X5R 402

1

C7R37

2

.1UF 10% 6.3V X5R 402

1

C7R44

2

.1UF 10% 6.3V X5R 402

1

C6R11

2

.1UF 10% 6.3V X5R 402

1

C7R46

2

.1UF 10% 6.3V X5R 402

1

C7R62

2

.1UF 10% 6.3V X5R 402

1

C7R78

2

.1UF 10% 6.3V X5R 402

1

C7R70

2

.1UF 10% 6.3V X5R 402

1

C7R53

2

.1UF 10% 6.3V X5R 402

1

C7R47

2

.1UF 10% 6.3V X5R 402

1

C7R63

2

.1UF 10% 6.3V X5R 402

1

C7R79

2

.1UF 10% 6.3V X5R 402

1

C7R77

2

.1UF 10% 6.3V X5R 402

1

C6R17

2

.1UF 10% 6.3V X5R 402

1

C7R45

2

.1UF 10% 6.3V X5R 402

1

C7R49

2

.1UF 10% 6.3V X5R 402

1

C7R72

2

.1UF 10% 6.3V X5R 402

1

C6R29

2

.1UF 10% 6.3V X5R 402

1

C6R28

2

.1UF 10% 6.3V X5R 402

1

C6R27

2

.1UF 10% 6.3V X5R 402

1

C7R76

2

.1UF 10% 6.3V X5R 402

1

C7T15

2

.1UF 10% 6.3V X5R 402

1

C7R64

2

.1UF 10% 6.3V X5R 402

1

C7R71

2

.1UF 10% 6.3V X5R 402

1

C7R84

2

.1UF 10% 6.3V X5R 402

1

C7T9

2

.1UF 10% 6.3V X5R 402

1

C7R55

2

.1UF 10% 6.3V X5R 402

1

C7R35

2

.1UF 10% 6.3V X5R 402

1

C7R34

2

.1UF 10% 6.3V X5R 402

1

C7R19

2

.1UF 10% 6.3V X5R 402

1

C7R43

2

.1UF 10% 6.3V X5R 402

1

C6R16

2

.1UF 10% 6.3V X5R 402

1

C6R19

2

.1UF 10% 6.3V X5R 402

1

C7R61

2

.1UF 10% 6.3V X5R 402

1

C7R54

2

.1UF 10% 6.3V X5R 402

1

C7R80

2

.1UF 10% 6.3V X5R 402

1

C6R32

2

.1UF 10% 6.3V X5R 402

1

C6R31

2

.1UF 10% 6.3V X5R 402

1

C6T5

2

.1UF 10% 6.3V X5R 402

1

C7R68

2

.1UF 10% 6.3V X5R 402

1

C7R69

2

.1UF 10% 6.3V X5R 402

1

C7R57

2

.1UF 10% 6.3V X5R 402

1

C6R20

2

.1UF 10% 6.3V X5R 402

1

C6R21

2

.1UF 10% 6.3V X5R 402

1

C6T26

2

.1UF 10% 6.3V X5R 402

DECOUPLING

1

C7R52

2

.1UF 10% 6.3V X5R 402

1

C7R51

2

.1UF 10% 6.3V X5R 402

1

C7R50

2

.1UF 10% 6.3V X5R 402

1

C6T6

2

.1UF 10% 6.3V X5R 402

1

C6R22

2

.1UF 10% 6.3V X5R 402

1

C6R23

2

.1UF 10% 6.3V X5R 402

1

C7R58

2

.1UF 10% 6.3V X5R 402

1

C7R59

2

.1UF 10% 6.3V X5R 402

1

C7R60

2

.1UF 10% 6.3V X5R 402

1

C6R30

2

.1UF 10% 6.3V X5R 402

1

C7T20

2

.1UF 10% 6.3V X5R 402

1

C7T22

2

.1UF 10% 6.3V X5R 402

1

C7T27

2

.1UF 10% 6.3V X5R 402

1

C7R48

2

.1UF 10% 6.3V X5R 402

1

C6T4

2

.1UF 10% 6.3V X5R 402

1

C7T37

2

.1UF 10% 6.3V X5R 402

1

C7R89

2

.1UF 10% 6.3V X5R 402

1

C6T25

2

.1UF 10% 6.3V X5R 402

1

C7R99

2

.1UF 10% 6.3V X5R 402

1

C6T23

2

.1UF 10% 6.3V X5R 402

1

C6R44

2

.1UF 10% 6.3V X5R 402

1

C6T2

2

.1UF 10% 6.3V X5R 402

1

C6T1

2

.1UF 10% 6.3V X5R 402

1

C6R43

2

.1UF 10% 6.3V X5R 402

1

C7R102

2

.1UF 10% 6.3V X5R 402

1

C7R81

2

.1UF 10% 6.3V X5R 402

1

C6R36

2

.1UF 10% 6.3V X5R 402

1

C7T81

2

.1UF 10% 6.3V X5R 402

1

C7R100

2

.1UF 10% 6.3V X5R 402

1

C7R74

2

.1UF 10% 6.3V X5R 402

1

C6T10

2

.1UF 10% 6.3V X5R 402

1

C7T19

2

.1UF 10% 6.3V X5R 402

1

C7R66

2

.1UF 10% 6.3V X5R 402

1

C7R111

2

.1UF 10% 6.3V X5R 402

1

C7R110

2

.1UF 10% 6.3V X5R 402

1

C7T2

2

.1UF 10% 6.3V X5R 402

1

C6R35

2

.1UF 10% 6.3V X5R 402

1

C7T10

2

.1UF 10% 6.3V X5R 402

1

C6R39

2

.1UF 10% 6.3V X5R 402

1

C6R18

2

.1UF 10% 6.3V X5R 402

1

C7T21

2

1

1

C7T71

2

1

.1UF 10% 6.3V X5R 402

1

C6R42

C7R67

2

C7T3

1

2

C7T5

1

2

C7T82

1

2

C6R40

1

2

C6R38

1

2

C6R34

1

2

DECOUPLING]

DRAWING XENON_FABK Wed Aug 24 09:27:03

2005

1

2

MICROSOFT

C7T72

C6R33

C7R88

C6R45

1

.1UF 10% 6.3V X5R 402

CONFIDENTIAL

C7T73

2

2

2

2

2

.1UF 10% 6.3V X5R 402

C7T8

2

.1UF 10% 6.3V X5R 402

N:

[PAGE_TITLE=CPU,

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

C7T74

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

C7T75

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

C7T70

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

C7T69

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

EMPTY FOR CPU SOCKET

PROJECT NAME XENON_RETAIL

PAGE 10/73

REV K7

CPU,

V_CPUCORE

1

C7R31

2

.1UF 10% 6.3V X5R 402

1

C7T12

2

.1UF 10% 6.3V X5R 402

1

C7R82

2

.1UF 10% 6.3V X5R 402

1

C7R56

2

.1UF 10% 6.3V X5R 402

1

C6R26

2

.1UF 10% 6.3V X5R 402

1

C6T9

2

.1UF 10% 6.3V X5R 402

1

C6T3

2

.1UF 10% 6.3V X5R 402

1

C7R21

2

.1UF 10% 6.3V X5R 402

1

C7R107

2

.1UF 10% 6.3V X5R 402

1

C6R13

2

.1UF 10% 6.3V X5R 402

1

C6T11

2

.1UF 10% 6.3V X5R 402

1

C7R17

2

.1UF 10% 6.3V X5R 402

1

C7R18

2

.1UF 10% 6.3V X5R 402

1

C7R20

2

.1UF 10% 6.3V X5R 402

1

C7R42

2

.1UF 10% 6.3V X5R 402

1

C7R41

2

.1UF 10% 6.3V X5R 402

1

C7R40

2

.1UF 10% 6.3V X5R 402

1

C7R39

2

.1UF 10% 6.3V X5R 402

1

C6T21

2

.1UF 10% 6.3V X5R 402

1

C6R12

2

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=CPU,

1

C7T38

2

.1UF 10% 6.3V X5R 402

1

C7R65

2

.1UF 10% 6.3V X5R 402

1

C6T14

2

.1UF 10% 6.3V X5R 402

1

C7T28

2

.1UF 10% 6.3V X5R 402

1

C7T31

2

.1UF 10% 6.3V X5R 402

1

C6R10

2

.1UF 10% 6.3V X5R 402

1

C7R8

2

.1UF 10% 6.3V X5R 402

1

C7R15

2

.1UF 10% 6.3V X5R 402

1

C7R33

2

.1UF 10% 6.3V X5R 402

1

C7R32

2

.1UF 10% 6.3V X5R 402

DECOUPLING]

1

C7T58

2

.1UF 10% 6.3V X5R 402

1

C6R24

2

.1UF 10% 6.3V X5R 402

1

C7T56

2

.1UF 10% 6.3V X5R 402

1

C7R98

2

.1UF 10% 6.3V X5R 402

1

C6T8

2

.1UF 10% 6.3V X5R 402

1

C7T17

2

.1UF 10% 6.3V X5R 402

1

C7T41

2

.1UF 10% 6.3V X5R 402

1

C6T12

2

.1UF 10% 6.3V X5R 402

1

C6R15

2

.1UF 10% 6.3V X5R 402

1

C6R41

2

.1UF 10% 6.3V X5R 402

1

C7T30

2

.1UF 10% 6.3V X5R 402

1

C7T29

2

.1UF 10% 6.3V X5R 402

1

C7T50

2

.1UF 10% 6.3V X5R 402

1

C7R106

2

.1UF 10% 6.3V X5R 402

1

C6T20

2

.1UF 10% 6.3V X5R 402

1

C7T49

2

.1UF 10% 6.3V X5R 402

1

C6T22

2

.1UF 10% 6.3V X5R 402

1

C7T13

2

.1UF 10% 6.3V X5R 402

1

C7R14

2

.1UF 10% 6.3V X5R 402

1

C7R9

2

.1UF 10% 6.3V X5R 402

DECOUPLING

1

C7T54

2

.1UF 10% 6.3V X5R 402

1

C6T24

2

.1UF 10% 6.3V X5R 402

1

C7T53

2

.1UF 10% 6.3V X5R 402

1

C7T52

2

.1UF 10% 6.3V X5R 402

1

C6R9

2

.1UF 10% 6.3V X5R 402

1

C6R7

2

.1UF 10% 6.3V X5R 402

1

C7T61

2

.1UF 10% 6.3V X5R 402

1

C7T60

2

.1UF 10% 6.3V X5R 402

1

C7T59

2

.1UF 10% 6.3V X5R 402

1

C7R86

2

.1UF 10% 6.3V X5R 402

1

C6T13

2

.1UF 10% 6.3V X5R 402

1

C7T14

2

.1UF 10% 6.3V X5R 402

1

C7T80

2

.1UF 10% 6.3V X5R 402

1

C7T11

2

.1UF 10% 6.3V X5R 402

1

C7T40

2

.1UF 10% 6.3V X5R 402

1

C7R75

2

.1UF 10% 6.3V X5R 402

1

C7R85

2

.1UF 10% 6.3V X5R 402

C7R101

1

2

.1UF 10% 6.3V X5R 402

1

C6R8

2

.1UF 10% 6.3V X5R 402

1

C7R73

2

.1UF 10% 6.3V X5R 402

1

C7R95

2

.1UF 10% 6.3V X5R 402

1

C7R103

2

.1UF 10% 6.3V X5R 402

1

C7R104

2

.1UF 10% 6.3V X5R 402

1

C7R96

2

.1UF 10% 6.3V X5R 402

1

C7R108

2

.1UF 10% 6.3V X5R 402

1

C7R109

2

.1UF 10% 6.3V X5R 402

1

C7R105

2

.1UF 10% 6.3V X5R 402

1

C7T4

2

.1UF 10% 6.3V X5R 402

1

C6T18

2

.1UF 10% 6.3V X5R 402

1

C7T16

2

.1UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:05

1

C7T51

2

.1UF 10% 6.3V X5R 402

1

C7T47

2

.1UF 10% 6.3V X5R 402

1

C7T46

2

.1UF 10% 6.3V X5R 402

1

C7R97

2

.1UF 10% 6.3V X5R 402

1

C7T57

2

.1UF 10% 6.3V X5R 402

1

C7T55

2

.1UF 10% 6.3V X5R 402

1

C7T18

2

.1UF 10% 6.3V X5R 402

1

C7T39

2

.1UF 10% 6.3V X5R 402

1

C7T26

2

.1UF 10% 6.3V X5R 402

1

C7T48

2

.1UF 10% 6.3V X5R 402

2005

1

C6T15

2

.1UF 10% 6.3V X5R 402

1

C6T16

2

.1UF 10% 6.3V X5R 402

1

C7T43

2

.1UF 10% 6.3V X5R 402

1

C7T44

2

.1UF 10% 6.3V X5R 402

1

C7T42

2

.1UF 10% 6.3V X5R 402

1

C7R83

2

.1UF 10% 6.3V X5R 402

1

C7T24

2

.1UF 10% 6.3V X5R 402

1

C7T25

2

.1UF 10% 6.3V X5R 402

1

C6T17

2

.1UF 10% 6.3V X5R 402

1

C7T23

2

.1UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

1

C6T28

2

.1UF 10% 6.3V X5R 402

1

C6T29

2

.1UF 10% 6.3V X5R 402

1

C6T30

2

.1UF 10% 6.3V X5R 402

1

C7T62

2

.1UF 10% 6.3V X5R 402

1

C7T63

2

.1UF 10% 6.3V X5R 402

1

C7T64

2

.1UF 10% 6.3V X5R 402

1

C7T65

2

.1UF 10% 6.3V X5R 402

1

C7T66

2

.1UF 10% 6.3V X5R 402

1

C7T67

2

.1UF 10% 6.3V X5R 402

1

C7T68

2

.1UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

PAGE 11/73

REV K7

GPU,

V_GPUCORE

2 1K 402

1

R5R1

2 1

R5R2

2

2

1K 5% EMPTY 402

1K 5% CH 402

1K 402

5 5 5 5

IN IN IN IN

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

R5C12

V_MEM

FSB

1

V_MEM

5% CH

R5C11

1 OF 8

U4D1

1

GPU VERSION

5% CH

FSB_BYPCLK_DP FSB_BYPCLK_DN FSB_BYPCLK_SEL

B29 A29 D25

FSB_BYPCLK_DP FSB_BYPCLK_DN FSB_BYPCLK_SEL

FSB_CP_GP0_CLK_DP FSB_CP_GP0_CLK_DN FSB_CP_GP0_FLAG_DP FSB_CP_GP0_FLAG_DN

J34 J33 J30 J29

CP_GP0_CLK_DP CP_GP0_CLK_DN CP_GP0_FLAG_DP CP_GP0_FLAG_DN

FSB_CP_GP0_DATA0_DP FSB_CP_GP0_DATA0_DN FSB_CP_GP0_DATA1_DP FSB_CP_GP0_DATA1_DN FSB_CP_GP0_DATA2_DP FSB_CP_GP0_DATA2_DN FSB_CP_GP0_DATA3_DP FSB_CP_GP0_DATA3_DN FSB_CP_GP0_DATA4_DP FSB_CP_GP0_DATA4_DN FSB_CP_GP0_DATA5_DP FSB_CP_GP0_DATA5_DN FSB_CP_GP0_DATA6_DP FSB_CP_GP0_DATA6_DN FSB_CP_GP0_DATA7_DP FSB_CP_GP0_DATA7_DN

M29 M30 L32 L31 K33 K34 L30 L29 J31 J32 K30 K29 H34 H33 H31 H32

CP_GP0_DATA0_DP CP_GP0_DATA0_DN CP_GP0_DATA1_DP CP_GP0_DATA1_DN CP_GP0_DATA2_DP CP_GP0_DATA2_DN CP_GP0_DATA3_DP CP_GP0_DATA3_DN CP_GP0_DATA4_DP CP_GP0_DATA4_DN CP_GP0_DATA5_DP CP_GP0_DATA5_DN CP_GP0_DATA6_DP CP_GP0_DATA6_DN CP_GP0_DATA7_DP CP_GP0_DATA7_DN

V33 V34 T33 T34

CP_GP1_CLK_DP CP_GP1_CLK_DN CP_GP1_FLAG_DP CP_GP1_FLAG_DN

5 5 5 5

IN IN IN IN

FSB_CP_GP1_CLK_DP FSB_CP_GP1_CLK_DN FSB_CP_GP1_FLAG_DP FSB_CP_GP1_FLAG_DN

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

FSB_CP_GP1_DATA0_DP FSB_CP_GP1_DATA0_DN FSB_CP_GP1_DATA1_DP FSB_CP_GP1_DATA1_DN FSB_CP_GP1_DATA2_DP FSB_CP_GP1_DATA2_DN FSB_CP_GP1_DATA3_DP FSB_CP_GP1_DATA3_DN FSB_CP_GP1_DATA4_DP FSB_CP_GP1_DATA4_DN FSB_CP_GP1_DATA5_DP FSB_CP_GP1_DATA5_DN FSB_CP_GP1_DATA6_DP FSB_CP_GP1_DATA6_DN FSB_CP_GP1_DATA7_DP FSB_CP_GP1_DATA7_DN FSB_IMPED_CAL FSB_IMPED_NCAL

1

R5R3

2

AA31 AA32 Y33 Y34 W30 W29 W33 W34 V29 V28 V31 V32 U33 U34 U30 U29

CP_GP1_DATA0_DP CP_GP1_DATA0_DN CP_GP1_DATA1_DP CP_GP1_DATA1_DN CP_GP1_DATA2_DP CP_GP1_DATA2_DN CP_GP1_DATA3_DP CP_GP1_DATA3_DN CP_GP1_DATA4_DP CP_GP1_DATA4_DN CP_GP1_DATA5_DP CP_GP1_DATA5_DN CP_GP1_DATA6_DP CP_GP1_DATA6_DN CP_GP1_DATA7_DP CP_GP1_DATA7_DN

T28 AA28

FSB_IMPED_PCAL FSB_IMPED_NCAL

IC 1

57

1

GP_CP0_CLK_DP GP_CP0_CLK_DN GP_CP0_FLAG_DP GP_CP0_FLAG_DN GP_CP0_DATA0_DP GP_CP0_DATA0_DN GP_CP0_DATA1_DP GP_CP0_DATA1_DN GP_CP0_DATA2_DP GP_CP0_DATA2_DN GP_CP0_DATA3_DP GP_CP0_DATA3_DN GP_CP0_DATA4_DP GP_CP0_DATA4_DN GP_CP0_DATA5_DP GP_CP0_DATA5_DN GP_CP0_DATA6_DP GP_CP0_DATA6_DN GP_CP0_DATA7_DP GP_CP0_DATA7_DN GP_CP1_CLK_DP GP_CP1_CLK_DN GP_CP1_FLAG_DP GP_CP1_FLAG_DN GP_CP1_DATA0_DP GP_CP1_DATA0_DN GP_CP1_DATA1_DP GP_CP1_DATA1_DN GP_CP1_DATA2_DP GP_CP1_DATA2_DN GP_CP1_DATA3_DP GP_CP1_DATA3_DN GP_CP1_DATA4_DP GP_CP1_DATA4_DN GP_CP1_DATA5_DP GP_CP1_DATA5_DN GP_CP1_DATA6_DP GP_CP1_DATA6_DN GP_CP1_DATA7_DP GP_CP1_DATA7_DN

P33 P34 L34 L33

FSB_GP_CP0_CLK_DP FSB_GP_CP0_CLK_DN FSB_GP_CP0_FLAG_DP FSB_GP_CP0_FLAG_DN

T29 T30 T31 T32 R34 R33 R29 R30 N34 N33 P29 P30 N31 N32 M34 M33

FSB_GP_CP0_DATA0_DP FSB_GP_CP0_DATA0_DN FSB_GP_CP0_DATA1_DP FSB_GP_CP0_DATA1_DN FSB_GP_CP0_DATA2_DP FSB_GP_CP0_DATA2_DN FSB_GP_CP0_DATA3_DP FSB_GP_CP0_DATA3_DN FSB_GP_CP0_DATA4_DP FSB_GP_CP0_DATA4_DN FSB_GP_CP0_DATA5_DP FSB_GP_CP0_DATA5_DN FSB_GP_CP0_DATA6_DP FSB_GP_CP0_DATA6_DN FSB_GP_CP0_DATA7_DP FSB_GP_CP0_DATA7_DN

AC33 AC34 Y29 Y30 AC28 AC29 AD29 AD30 AD34 AD33 AB29 AB30 AC32 AC31 AA29 AA30 AB33 AB34 AA34 AA33

OUT OUT OUT OUT

5 5 5 5

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

FSB_GP_CP1_CLK_DP FSB_GP_CP1_CLK_DN FSB_GP_CP1_FLAG_DP FSB_GP_CP1_FLAG_DN

OUT OUT OUT OUT

5 5 5 5

FSB_GP_CP1_DATA0_DP FSB_GP_CP1_DATA0_DN FSB_GP_CP1_DATA1_DP FSB_GP_CP1_DATA1_DN FSB_GP_CP1_DATA2_DP FSB_GP_CP1_DATA2_DN FSB_GP_CP1_DATA3_DP FSB_GP_CP1_DATA3_DN FSB_GP_CP1_DATA4_DP FSB_GP_CP1_DATA4_DN FSB_GP_CP1_DATA5_DP FSB_GP_CP1_DATA5_DN FSB_GP_CP1_DATA6_DP FSB_GP_CP1_DATA6_DN FSB_GP_CP1_DATA7_DP FSB_GP_CP1_DATA7_DN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

13

IN

R2E5

0 402

2

1

5% CH

R2R5

2

.1UF 10% 6.3V X5R 402

U2E2

EMPTY

2

SN74LVC1G125

5 2 3

MEM_SCAN_EN_BUFF

VCC IN GND

OUT OE_N

4 1

V_MEM

1

C2R12

1

2

.1UF 10% 6.3V X5R 402 13

IN

R2D12

0 402

R4F8

R2D11

1K 5% CH 402

1K 5% CH 402

2

2

EMPTY

MEM_SCAN_TOP_EN_BUFF

VCC IN GND

OUT OE_N

4 1

MEM_SCAN_TOP_EN 1

2

13

FSB]

22 25

1

X801565-001

FSB DECOUPLING

C4R33

27 21 24

SN74LVC1G125

C2D5

1

C4R45

.1UF 10% 6.3V X5R 402

C4T22

.1UF 10% 6.3V X5R 402

C5R18

.1UF 10% 6.3V X5R 402

C4R65

.1UF 10% 6.3V X5R 402

C4R60

.1UF 10% 6.3V X5R 402

IN

OUT

20 26

22

24

OUT

21 27

23

25

1

R4F7

R2T2

1K 5% CH 402

1K 5% CH 402

2

2

5% CH

U2R1

1

EMPTY

SN74LVC1G125

MEM_SCAN_BOT_EN_BUFF

5 2 3

VCC IN GND

OUT OE_N

2

4 1

1

R4U6

R2T1

1K 5% CH 402

1K 5% CH 402

2

MEM_SCAN_BOT_EN

X801565-001

C4T13

.1UF 10% 6.3V X5R 402

R2R6

0 402

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

26 20 23

V_MEM

V_GPUCORE

.1UF 10% 6.3V X5R 402

OUT

5% CH

U2D1

5 2 3

V_MEM

C4R27

MEM_SCAN_EN

2

X02056-010

4.87K 1% CH 402

0 5% CH 402

1

X801565-001

1

[PAGE_TITLE=GPU,

C2E4

13

IN

DRAWING XENON_FABK Wed Aug 24 09:27:06

GPU_SCAN_BUFF_EN_N

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 12/73

REV K7

R4D3

1 49.9 402

R4D4

1 49.9 402 FT2P14 34

R5D1

562 402

46 46

GPU, U4D1

1% EMPTY

PEX_SB_GPU_L1_DP PEX_SB_GPU_L1_DN PEX_SB_GPU_L0_DP PEX_SB_GPU_L0_DN

IN IN IN IN

2

PEX_PCAL

1% CH

R5D2

1

V_GPUPCIE

2K 402

R4R3

1 1.47K 402

2

2

PEX_NCAL

1% CH

28 28 29 29 29 29

R3C28

1

ANA_PIX_CLK_2X_DP ANA_PIX_CLK_2X_DN GPU_TEMP_P GPU_TEMP_N EDRAM_TEMP_P EDRAM_TEMP_N

IN IN IN OUT IN OUT

1.27K 402

2

DBG_LED3

A25 A24

NB_CLK_DP NB_CLK_DN

E11

RST_IN_N*

B22 A22 B26 A26

PEX_RX1_DP PEX_RX1_DN PEX_RX0_DP PEX_RX0_DN

A28 B28 B21

PEX_PCAL PEX_NCAL PEX_ICAL

D10 C10

PIX_CLK_IN_DP PIX_CLK_IN_DN

C22 C23 G14 G15

IN

IC

RST_DONE

34

R4T1

1 40.2 402

2

R4R8

1 40.2 402

V_MEM

1.5K 1% CH 402

J2D2 2X4HDR

2

29

OUT OUT V_MEM

PEX_GPU_SB_L1_DN

2

OUT

33

C4D3

C5D1

1

OUT

33

PEX_GPU_SB_L0_DN

2

OUT

33

.1UF 10% 6.3V X5R 402

R4D1

2

PEX_GPU_SB_L0_DP

2

.1UF 10% 6.3V X5R 402

29

1 1K 5% EMPTY 402 DB4D1

1

TP

1

R4D2

29 OUT 29 OUT GPU_SROM_EN_PSRO_OUT GPU_SPI_SO GPU_SPI_CLK GPU_SPI_CS_N

2

1K 5% CH 402

13 13 13

OUT OUT OUT

GPU_TCLK GPU_TDO GPU_TDI GPU_TMS GPU_TRST GPU_TRST_ED

E13 D12 E12 G12 G11 G13

TCLK TDO TDI TMS TRST TRST_ED

MEM_RST MEM_SCAN_EN_BUFF MEM_SCAN_TOP_EN_BUFF MEM_SCAN_BOT_EN_BUFF

AG11 AN13 G9 G10

OUT OUT OUT OUT 2

1

X02056-010 1.5K 1% CH 402

21

20 12 12 12

22

23

24

25

26

27

2

R2E1

R4F6

1K 5% CH 402

1K 5% CH 402

1

J5C2

EMPTY

2X3HDR

V_1P8 1 3 5

2 4 6

GPU_SPI_SI GPU_SPI_WP_N

13 13

OUT OUT

V_1P8

1 1

1.5K 1% CH 402

GPU_SCAN_BUFF_EN_N

GPU_PIX_CLK_1X PIX_DATA<14..0>

GPU_VSYNC_OUT GPU_HSYNC_OUT

G17 E16 E15 E14

MEM_RST MEM_SCAN_EN MEM_SCAN_OEN_A MEM_SCAN_OEN_B

MEM_CALA MEM_CALB

2 4 6 8

1

R2D10

C4D2

1

.1UF 10% 6.3V X5R 402

PEX_GPU_SB_L0_DN_C

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

33

R2E4

1 3 5 7

2

AG16 V8

1

R2E2

OUT

MEM_CALB

1% CH

V_MEM

1

2

2

34

OUT

PEX_GPU_SB_L1_DP

2

.1UF 10% 6.3V X5R 402

PEX_GPU_SB_L0_DP_C

A11 B11

SROM_EN_PSRO_OUT SROM_SI SROM_SCLK SROM_CS

SROM_SO

MEM_CALA

1% CH

FT2P13

PEX_GPU_SB_L1_DN_C

B17 A17 D16 B16 A16 D15 B15 A15 A14 D13 B13 A13 B12 A12 D11

PIX_DATA14 PIX_DATA13 PIX_DATA12 PIX_DATA11 PIX_DATA10 PIX_DATA9 PIX_DATA8 PIX_DATA7 PIX_DATA6 PIX_DATA5 PIX_DATA4 PIX_DATA3 PIX_DATA2 PIX_DATA1 PIX_DATA0

NB_THERMD_P NB_THERMD_N ED_THERMD_P ED_THERMD_N

G16

PEX_GPU_SB_L1_DP_C

FTP

1

56

GPU_SPI_SI

GPU_RST_DONE

B23 A23 B27 A27

B14

VSYNC_OUT HSYNC_OUT

IN

D14

C4D1

1

1

PEX_TX1_DP PEX_TX1_DN PEX_TX0_DP PEX_TX0_DN

1% CH

13

+ EEPROM + JTAG

57

PIX_CLK_OUT

PEX_ICAL

1% CH

+ PCIEX

2 OF 12 GPU VERSION

GPU_CLK_DP GPU_CLK_DN

IN IN

VIDEO

2

GPU_RST_N

IN 33 33 33 33

1

1

FTP

2

1% EMPTY

2

R4C7

1

R2D9

R2E3

1.5K 1% CH 402

1.5K 1% CH 402

2

2

10K 5% CH 402

1 V_1P8 U4C1

13

IN

R5C5

GPU_SPI_CLK 1K 402

13

IN

IN

12

2

[PAGE_TITLE=GPU,

VIDEO

1K 402

1 R5C10

R5P3

10K 5% CH 402

10K 5% CH 402

2

+ PCIEX

5% CH

5% CH

2

EMPTY AT25020A

GPU_SPI_CLK_R GPU_SPI_SO_R

GPU_SPI_CS_N_R

6 5

SCK SDI

7 1 3

HOLD_N* CS_N* WP_N*

VCC

8

SDO

2

GND

4

C5C3

V_MEM

.1UF 10% 6.3V X5R 402

VIDEO

GPU_SPI_SI

OUT 2

V_1P8

R4C6

R4C3

GPU_SPI_CS_N 1

5% CH

R5C8

GPU_SPI_SO 1K 402

13

OUT

EMPTY

X800552-001

2 10K 402

2 10K 402

R4C4

1

5% CH

R4C5

1 1

GPU_SPI_WP_N

IN

13

C3C2

10UF 20% 6.3V X5R 805

DECOUPLING

C4R2

.1UF 10% 6.3V X5R 402

C4R26

.1UF 10% 6.3V X5R 402

C4R1

.1UF 10% 6.3V X5R 402

10K 5% CH 402

13

5% EMPTY

+ EEPROM + JTAG]

DRAWING XENON_FABK Wed Aug 24 09:27:07

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 13/73

REV K7

GPU, U4D1

21 21 21 21 21 21 21 21 21

20 20 20 20 20 20 20 20 20 21 21

21 21 21 21 21 21 21 21 21

20 20 20 20 20 20 20 20 20 20 20

21 21 21 21 21 21 21 21 21 21 21

20 20 20 20 20 20 20 20 20 20 20

21 21 21 21 21 21 21 21 21 21 21

20 20 20 20 20 20 20 20 20 20 20

21 21

20 20

BI BI BI BI BI BI BI BI OUT IN OUT BI BI BI BI BI BI BI BI OUT IN OUT BI BI BI BI BI BI BI BI OUT IN OUT BI BI BI BI BI BI BI BI OUT IN OUT

MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3

AP19 AN19 AL18 AN20 AN18 AM20 AN17 AL20 AP20 AM18 AP18

MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3

MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2

AP15 AN15 AM15 AN14 AN16 AL13 AP17 AM13 AP14 AL15 AP16

MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2

MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1

AH16 AK20 AK16 AH20 AH17 AJ19 AJ18 AH18 AK19 AK17 AM17

MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1

MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0

AK15 AH11 AH15 AK11 AH13 AK12 AJ13 AH12 AM12 AJ14 AK14

MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0

AK6 AP13

MA_VREF1 MA_VREF0

V_MEM 1

R4T4

2

1 2

.1UF 10% 6.3V X5R 402

MA_CLK1_DP MA_CLK1_DN MA_CLK0_DP MA_CLK0_DN

AH10 AK10 AN12 AP12

MA_A12 MA_A11 MA_A10 MA_A9 MA_A8 MA_A7 MA_A6 MA_A5 MA_A4 MA_A3 MA_A2 MA_A1 MA_A0

AN4 AP7 AP4 AP8 AN11 AP9 AN10 AP11 AN9 AN8 AN7 AN5 AP6

MA_BA2 MA_BA1 MA_BA0

AP10 AM10 AP5

MA_CKE MA_WE_N* MA_CAS_N* MA_RAS_N* MA_CS1_N* MA_CS0_N*

AN6 AJ9 AK8 AK7 AK9 AL10

MA_CLK1_DP MA_CLK1_DN MA_CLK0_DP MA_CLK0_DN MA_A<12..0>

OUT OUT OUT OUT OUT

12 11 10 9 8 7 6 5 4 3 2 1 0

MA_BA<2..0>

2 1 0

MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS1_N MA_CS0_N

OUT

20 20 20 20 21 20

OUT OUT OUT OUT OUT OUT

21 21 20 20 20

20

21

21

21 21 21 21

23 23 23 23 23 23 23 23 23 23 23

22 22 22 22 22 22 22 22 22 22 22

BI BI BI BI BI BI BI BI OUT IN OUT

23 23 23 23 23 23 23 23 23 23 23

22 22 22 22 22 22 22 22 22 22 22

BI BI BI BI BI BI BI BI OUT IN OUT

23 23 23 23 23 23 23 23 23 23 23

22 22 22 22 22 22 22 22 22 22 22

BI BI BI BI BI BI BI BI OUT IN OUT

23 23 23 23 23 23 23 23 23 23 23

22 22 22 22 22 22 22 22 22 22 22

BI BI BI BI BI BI BI BI OUT IN OUT

MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3

AN27 AP28 AP27 AP29 AL25 AP31 AM25 AP32 AP30 AN26 AP26

MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3

MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2

AM23 AP23 AL23 AN23 AN25 AP22 AP25 AN21 AN22 AP24 AN24

MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2

MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1

AH26 AN32 AK26 AN31 AN29 AN30 AK28 AK29 AK30 AN28 AK27

MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1

MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0

AK25 AH21 AH25 AK21 AH23 AK22 AJ23 AH22 AM22 AJ24 AK24

MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0

AG33 AP21

MB_VREF1 MB_VREF0

V_MEM

IC 57

MB_CLK1_DP MB_CLK1_DN MB_CLK0_DP MB_CLK0_DN

1

2

2

1 MEMORY CONTROLLER A,

2

1 2

C4R3

C4T45 .1UF 10% 6.3V X5R 402

10UF 10% 6.3V X5R 1206

AH30 AH33 AG30

MB_CKE MB_WE_N* MB_CAS_N* MB_RAS_N* MB_CS1_N* MB_CS0_N*

AG34 AF33 AF32 AF31 AH34 AF34

C4T29

.22UF 10% 6.3V X5R 402

C4T32

C4T42

.22UF 10% 6.3V X5R 402

.22UF 10% 6.3V X5R 402

C4T44

1

R5E1

C5E1 .1UF 10% 6.3V X5R 402

2

C4T35

MEMORY CONTROLLER

C4T27

.22UF 10% 6.3V X5R 402

C4T41

.22UF 10% 6.3V X5R 402

12 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0

MB_BA<2..0>

MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS1_N MB_CS0_N

OUT OUT OUT OUT OUT

23 23 22 22

22

23

OUT

OUT OUT OUT OUT OUT OUT

22 22 22 22 23 22

22

23

23 23 23 23

MEMORY CONTROLLER B,

1.27K 1% CH 402

DECOUPLING

1

2

C4T47

549 1% CH 402

10UF 10% 6.3V X5R 1206

C4T31

.22UF 10% 6.3V X5R 402

C4T34 .22UF 10% 6.3V X5R 402

C5T2

.22UF 10% 6.3V X5R 402

C4T39

.22UF 10% 6.3V X5R 402

MB_VREF0

1

.22UF 10% 6.3V X5R 402

R4T5

2

.22UF 10% 6.3V X5R 402

[PAGE_TITLE=GPU,

DECOUPLING 2

1.27K 1% CH 402

MB_BA2 MB_BA1 MB_BA0

R4T8 V_MEM

MA_VREF0

R4T6

AK32 AE29 AE34 AJ30 AK33 AJ33 AK34 AM32 AJ34 AE30 AF28 AE33 AF29

V_MEM MB_VREF1

549 1% CH 402

1

MB_A12 MB_A11 MB_A10 MB_A9 MB_A8 MB_A7 MB_A6 MB_A5 MB_A4 MB_A3 MB_A2 MB_A1 MB_A0

MB_CLK1_DP MB_CLK1_DN MB_CLK0_DP MB_CLK0_DN MB_A<12..0>

V_MEM

549 1% CH 402

R4T7 1.27K 1% CH 402

AM33 AM34 AL33 AL34

X02056-010

1

V_MEM MA_VREF1

R4T3

2

4 OF 8 GPU VERSION

R5E2

1

C4T40

U4D1

57

X02056-010

549 1% CH 402

A & B

IC

3 OF 8 GPU VERSION

MEMORY CONTROLLER 0 PARTITION

1.27K 1% CH 402

1 2

C4T46 .1UF 10% 6.3V X5R 402

C4T33

.22UF 10% 6.3V X5R 402

C5T3

.22UF 10% 6.3V X5R 402

C5T4

.22UF 10% 6.3V X5R 402

C5T1

.22UF 10% 6.3V X5R 402

C4T43

.22UF 10% 6.3V X5R 402

A + B]

DRAWING XENON_FABK Wed Aug 24 09:27:08

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 14/73

REV K7

GPU, U4D1

5 OF 8 GPU VERSION

BI BI BI BI BI BI BI BI OUT IN OUT

MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3

R1 R3 R2 R4 N4 T2 N3 U1 T1 P2 P1

MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3

24 24 24 24 24 24 24 24 24 24 24

BI BI BI BI BI BI BI BI OUT IN OUT

MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2

L1 K4 L2 K3 N2 K2 N1 J2 K1 M1 M2

MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2

25 25 25 25 25 25 25 25 25 25 25

24 24 24 24 24 24 24 24 24 24 24

BI BI BI BI BI BI BI BI OUT IN OUT

MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1

J6 N6 J5 N7 L5 M5 L7 M3 M7 K5 K7

MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1

25 25 25 25 25 25 25 25 25 25 25

24 24 24 24 24 24 24 24 24 24 24

BI BI BI BI BI BI BI BI OUT IN OUT

MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0

H2 B2 H5 C2 F2 E5 F5 E2 D2 G5 G2

MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0

25 25 25 25 25 25 25 25 25 25 25

24 24 24 24 24 24 24 24 24 24 24

25 25 25 25 25 25 25 25 25 25 25

G1 E10

V_MEM 2

R4R4

1

MEMORY CONTROLLER 1 PARTITION

U4D1

GPU VERSION

MC_CLK1_DP MC_CLK1_DN MC_CLK0_DP MC_CLK0_DN

MC_CLK1_DP MC_CLK1_DN MC_CLK0_DP MC_CLK0_DN MC_A<12..0>

J1 H1 F1 E1

MC_A12 MC_A11 MC_A10 MC_A9 MC_A8 MC_A7 MC_A6 MC_A5 MC_A4 MC_A3 MC_A2 MC_A1 MC_A0

A10 A7 B10 B6 D1 A5 A4 C1 B5 A6 B7 A9 B8

MC_BA2 MC_BA1 MC_BA0

B4 A3 B9

MC_CKE MC_WE_N* MC_CAS_N* MC_RAS_N* MC_CS1_N* MC_CS0_N*

A8 E7 E8 E9 E6 B3

12 11 10 9 8 7 6 5 4 3 2 1 0

MC_BA<2..0>

2 1 0

MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS1_N MC_CS0_N

25 25 24 24

OUT OUT OUT OUT OUT

24

OUT

24 24 24 24 25 24

OUT OUT OUT OUT OUT OUT

24

25

25

25 25 25 25

BI BI BI BI BI BI BI BI OUT IN OUT

MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3

AC3 AC4 AC1 AD1 AB1 AE2 AA2 AE1 AD2 AC2 AB2

MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3

26 26 26 26 26 26 26 26 26 26 26

BI BI BI BI BI BI BI BI OUT IN OUT

MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2

W2 W1 Y2 V4 Y4 V1 AA1 V2 V3 Y1 Y3

MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2

27 27 27 27 27 27 27 27 27 27 27

26 26 26 26 26 26 26 26 26 26 26

BI BI BI BI BI BI BI BI OUT IN OUT

MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1

W6 AC7 W5 AC6 AA5 AB5 AA7 AB3 AB7 Y5 Y7

MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1

27 27 27 27 27 27 27 27 27 27 27

26 26 26 26 26 26 26 26 26 26 26

BI BI BI BI BI BI BI BI OUT IN OUT

MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0

V7 P6 V6 P5 U3 R5 T5 T7 R7 U5 U7

MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0

27 27 27 27 27 27 27 27 27 27 27

26 26 26 26 26 26 26 26 26 26 26

27 27 27 27 27 27 27 27 27 27 27

1

2

2

2

R4R5

2

1.27K 1% CH 402

1

V_MEM

1 MEMORY CONTROLLER C,

DECOUPLING 2

MC_VREF0

1

1

R4R2

2

1.27K 1% CH 402

1 2

C3R5

10UF 10% 6.3V X5R 1206

C4R10

.1UF 10% 6.3V X5R 402

1

2

2

C4R38

.22UF 10% 6.3V X5R 402

1

2

C4R51 .22UF 10% 6.3V X5R 402

1

2

1

C4T14 .22UF 10% 6.3V X5R 402

2

.1UF 10% 6.3V X5R 402

2

PAGE_TITLE=[GPU,

C4R23

.22UF 10% 6.3V X5R 402

1

2

C4R66 .22UF 10% 6.3V X5R 402

1

2

C4T12 .22UF 10% 6.3V X5R 402

MEMORY CONTROLLER C + D]

1 2

MD_BA2 MD_BA1 MD_BA0

AG5 AH2 AJ5

MD_CKE MD_WE_N* MD_CAS_N* MD_RAS_N* MD_CS1_N* MD_CS0_N*

AK1 AH1 AJ1 AL1 AH5 AG1

12 11 10 9 8 7 6 5 4 3 2 1 0

MD_BA<2..0>

2 1 0

MD_CKE MD_WE_N MD_CAS_N MD_RAS_N MD_CS1_N MD_CS0_N

OUT

OUT OUT OUT OUT OUT OUT

26 26 26 26 27 26

26

26

27

27

27 27 27 27

V_MEM MEMORY CONTROLLER D, R4R6

1.27K 1% CH 402

DECOUPLING

1

2

1

549 1% CH 402

1

C4T28

10UF 10% 6.3V X5R 1206

2

2

C4R15

.22UF 10% 6.3V X5R 402

1

C4R61

.22UF 10% 6.3V X5R 402

2

1

2

C4T38

.22UF 10% 6.3V X5R 402

1 2

C4R50

.22UF 10% 6.3V X5R 402

MD_VREF0

C4R48

.22UF 10% 6.3V X5R 402

1

R4R7

2

1

AK5 AL2 AM2 AF5 AE5 AF2 AF7 AE7 AG2 AM1 AJ2 AM3 AK2

V_MEM

R4T2

2

MD_A12 MD_A11 MD_A10 MD_A9 MD_A8 MD_A7 MD_A6 MD_A5 MD_A4 MD_A3 MD_A2 MD_A1 MD_A0

27 27 26 26

OUT OUT OUT OUT OUT

X02056-010 549 1% CH 402

1

C4T36

MD_CLK1_DP MD_CLK1_DN MD_CLK0_DP MD_CLK0_DN MD_A<12..0>

AD6 AD5 AE4 AE3

MD_VREF1 MD_VREF0

MD_VREF1

549 1% CH 402

IC 57

MD_CLK1_DP MD_CLK1_DN MD_CLK0_DP MD_CLK0_DN

R3T2 V_MEM

R4R1 .1UF 10% 6.3V X5R 402

AF1 U2

V_MEM

X02056-010

549 1% CH 402

1

C4R25

6 OF 8

57

MC_VREF1 MC_VREF0

MC_VREF1

1

C & D

IC

1.27K 1% CH 402

1 2

C4R64

1

.1UF 10% 6.3V X5R 402

2

C4T7

.22UF 10% 6.3V X5R 402

1 2

1 C4R31

.22UF 10% 6.3V X5R 402

2

C4R12

.22UF 10% 6.3V X5R 402

1

2

C4R19

.22UF 10% 6.3V X5R 402

C4R32 .22UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:10

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 15/73

REV K7

GPU,

PLL POWER + FSB POWER

V_GPUCORE FB4D1 1

0.5

2

120 0.2A DCR

FB 603

1

C4D6 2.2UF 10% 6.3V X5R 603

2

1 2

C4D5

.1UF 10% 6.3V X5R 402

1 2

C4D4

0.01UF 10% 16V X7R 402

V_GPUCORE V_GPUPCIE

U4D1

GPU VERSION

FB4T1 1

0.5

2

120 0.2A DCR

V_PVDDA

FB 603

1

C4T48 2.2UF 10% 6.3V X5R 603

2

1 2

1 C4T30

.1UF 10% 6.3V X5R 402

C4T37 0.01UF 10% 16V X7R 402

2

C5R7 .1UF 10% 6.3V X5R 402

V_PVDDA_MEM

FB4R1

0.5

1 120 0.2A DCR

8 OF 12

2 FB 603

V_PVDDA_ED

1 2

C4R68 2.2UF 10% 6.3V X5R 603

1 2

C4R4 .1UF 10% 6.3V X5R 402

C4R6

0.01UF 10% 16V X7R 402

V_PVDDA_FSB

1 2

C4R8 .1UF 10% 6.3V X5R 402

A20 A21

PVDDA PVSSA

C27 C26

VDD_BSB1 VSS_BSB1

C25 C24

VDD_BSB0 VSS_BSB0

AG10 AG9

PVDDA_MEM PVSSA_MEM

A18 A19

PVDDA_ED PVSSA_ED

B25 B24

PVDDA_PEX PVSSA_PEX

G34 F34

PVDDA_FSB PVSSA_FSB

V_GPUPCIE

IC 57 VDD_FSB24 VDD_FSB23 VDD_FSB22 VDD_FSB21 VDD_FSB20 VDD_FSB19 VDD_FSB18 VDD_FSB17 VDD_FSB16 VDD_FSB15 VDD_FSB14 VDD_FSB13 VDD_FSB12 VDD_FSB11 VDD_FSB10 VDD_FSB9 VDD_FSB8 VDD_FSB7 VDD_FSB6 VDD_FSB5 VDD_FSB4 VDD_FSB3 VDD_FSB2 VDD_FSB1 VDD_FSB0

AA27 AB28 AB32 AC27 AD28 AD31 K28 K31 L27 M28 M32 N27 P28 P31 R28 R32 T27 U28 U31 V27 V30 W28 W32 Y28 Y31

X02056-010

1 2

C4R5

.1UF 10% 6.3V X5R 402

C4R7

0.01UF 10% 16V X7R 402

FB5R1 1

0.5

120 0.2A DCR

2 FB 603

1 2

[PAGE_TITLE=GPU,

C5R19 2.2UF 10% 6.3V X5R 603

PLL

1 2

C5R13

.1UF 10% 6.3V X5R 402

C5R15

0.01UF 10% 16V X7R 402

POWER + FSB

POWER]

DRAWING XENON_FABK Wed Aug 24 09:27:10

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 16/73

REV K7

GPU,

V_GPUCORE

CORE POWER + MEM POWER

V_GPUCORE U4D1 U4D1

AA14 AA15 AA16 AA19 AA20 AA21 AB11 AB12 AB13 AB17 AB18 AB22 AB23 AB24 AC11 AC12 AC13 AC17 AC18 AC22 AC23 AC24 AD11 AD12 AD13 AD17 AD18 AD22 AD23 AD24 B18 B20 C19 C21 C29 C31 C33 C34 D17 D18 D20 D22 D30 D32 D34 E17 E19 E21 E31 F17 F18 F20 F23 F25 F27 F29 F30 G19 G28 G32 H12 H14 H16 H18 H20 H22 H24 H26 H27 J27

9 OF 12

GPU VERSION 57 VDD_CORE139 VDD_CORE69 VDD_CORE138 VDD_CORE68 VDD_CORE137 VDD_CORE67 VDD_CORE136 VDD_CORE66 VDD_CORE135 VDD_CORE65 VDD_CORE134 VDD_CORE64 VDD_CORE133 VDD_CORE63 VDD_CORE132 VDD_CORE62 VDD_CORE131 VDD_CORE61 VDD_CORE130 VDD_CORE60 VDD_CORE129 VDD_CORE59 VDD_CORE128 VDD_CORE58 VDD_CORE127 VDD_CORE57 VDD_CORE126 VDD_CORE56 VDD_CORE125 VDD_CORE55 VDD_CORE124 VDD_CORE54 VDD_CORE123 VDD_CORE53 VDD_CORE122 VDD_CORE52 VDD_CORE121 VDD_CORE51 VDD_CORE120 VDD_CORE50 VDD_CORE119 VDD_CORE49 VDD_CORE118 VDD_CORE48 VDD_CORE117 VDD_CORE47 VDD_CORE116 VDD_CORE46 VDD_CORE115 VDD_CORE45 VDD_CORE114 VDD_CORE44 VDD_CORE113 VDD_CORE43 VDD_CORE112 VDD_CORE42 VDD_CORE111 VDD_CORE41 VDD_CORE110 VDD_CORE40 VDD_CORE109 VDD_CORE39 VDD_CORE108 VDD_CORE38 VDD_CORE107 VDD_CORE37 VDD_CORE106 VDD_CORE36 VDD_CORE105 VDD_CORE35 VDD_CORE104 VDD_CORE34 VDD_CORE33 VDD_CORE103 VDD_CORE32 VDD_CORE102 VDD_CORE31 VDD_CORE101 VDD_CORE30 VDD_CORE100 VDD_CORE29 VDD_CORE99 VDD_CORE28 VDD_CORE98 VDD_CORE27 VDD_CORE97 VDD_CORE26 VDD_CORE96 VDD_CORE25 VDD_CORE95 VDD_CORE24 VDD_CORE94 VDD_CORE23 VDD_CORE93 VDD_CORE22 VDD_CORE92 VDD_CORE21 VDD_CORE91 VDD_CORE20 VDD_CORE90 VDD_CORE19 VDD_CORE89 VDD_CORE18 VDD_CORE88 VDD_CORE17 VDD_CORE87 VDD_CORE16 VDD_CORE86 VDD_CORE15 VDD_CORE85 VDD_CORE14 VDD_CORE84 VDD_CORE13 VDD_CORE83 VDD_CORE12 VDD_CORE82 VDD_CORE11 VDD_CORE81 VDD_CORE10 VDD_CORE80 VDD_CORE9 VDD_CORE79 VDD_CORE8 VDD_CORE78 VDD_CORE7 VDD_CORE77 VDD_CORE6 VDD_CORE76 VDD_CORE5 VDD_CORE75 VDD_CORE4 VDD_CORE74 VDD_CORE3 VDD_CORE73 VDD_CORE2 VDD_CORE72 VDD_CORE1 VDD_CORE71 VDD_CORE0 VDD_CORE70 X02056-010

[PAGE_TITLE=GPU,

U4D1

IC

IC 11

L11 L12 L13 L17 L18 L22 L23 L24 M11 M12 M13 M17 M18 M22 M23 M24 N11 N12 N13 N17 N18 N22 N23 N24 P14 P15 P16 P19 P20 P21 R14 R15 R16 R19 R20 R21 T14 T15 T16 T19 T20 T21 U11 U12 U13 U17 U18 U22 U23 U24 V11 V12 V13 V17 V18 V22 V23 V24 W14 W15 W16 W19 W20 W21 Y14 Y15 Y16 Y19 Y20 Y21

V_MEM

V_MEM U4D1 AA4 AA6 AB6 AC5 AC8 AD4 AD7 AE8 AE28 AE31 AF3 AF6 AF27 AF30 AG4 AG7 AG13 AG15 AG17 AG20 AG23 AG25 AG28 AG32 AH3 AH6 AH8 AH9 AH14 AH19 AH24 AH27 AH29 AH31 AJ4 AJ7 AJ11 AJ12 AJ16 AJ21 AJ22 AJ26 AJ28 AJ32 AK3 AK13 AK23 AK31 AL4 AL6 AL8 AL11 AL14 AL17 AL21 AL24

10

OF 12

GPU VERSION VDD_MEM111 VDD_MEM110 VDD_MEM109 VDD_MEM108 VDD_MEM107 VDD_MEM106 VDD_MEM105 VDD_MEM104 VDD_MEM103 VDD_MEM102 VDD_MEM101 VDD_MEM100 VDD_MEM99 VDD_MEM98 VDD_MEM97 VDD_MEM96 VDD_MEM95 VDD_MEM94 VDD_MEM93 VDD_MEM92 VDD_MEM91 VDD_MEM90 VDD_MEM89 VDD_MEM88 VDD_MEM87 VDD_MEM86 VDD_MEM85 VDD_MEM84 VDD_MEM83 VDD_MEM82 VDD_MEM81 VDD_MEM80 VDD_MEM79 VDD_MEM78 VDD_MEM77 VDD_MEM76 VDD_MEM75 VDD_MEM74 VDD_MEM73 VDD_MEM72 VDD_MEM71 VDD_MEM70 VDD_MEM69 VDD_MEM68 VDD_MEM67 VDD_MEM66 VDD_MEM65 VDD_MEM64 VDD_MEM63 VDD_MEM62 VDD_MEM61 VDD_MEM60 VDD_MEM59 VDD_MEM58 VDD_MEM57 VDD_MEM56 X02056-010

IC

57 VDD_MEM55 VDD_MEM54 VDD_MEM53 VDD_MEM52 VDD_MEM51 VDD_MEM50 VDD_MEM49 VDD_MEM48 VDD_MEM47 VDD_MEM46 VDD_MEM45 VDD_MEM44 VDD_MEM43 VDD_MEM42 VDD_MEM41 VDD_MEM40 VDD_MEM39 VDD_MEM38 VDD_MEM37 VDD_MEM36 VDD_MEM35 VDD_MEM34 VDD_MEM33 VDD_MEM32 VDD_MEM31 VDD_MEM30 VDD_MEM29 VDD_MEM28 VDD_MEM27 VDD_MEM26 VDD_MEM25 VDD_MEM24 VDD_MEM23 VDD_MEM22 VDD_MEM21 VDD_MEM20 VDD_MEM19 VDD_MEM18 VDD_MEM17 VDD_MEM16 VDD_MEM15 VDD_MEM14 VDD_MEM13 VDD_MEM12 VDD_MEM11 VDD_MEM10 VDD_MEM9 VDD_MEM8 VDD_MEM7 VDD_MEM6 VDD_MEM5 VDD_MEM4 VDD_MEM3 VDD_MEM2 VDD_MEM1 VDD_MEM0 BGA

AL28 AL30 AL32 AM5 AM7 AM9 AM16 AM19 AM26 AM27 AM29 AM31 AN2 AP3 C3 C5 C7 C9 C12 C14 C16 C18 D4 D6 D8 E3 F4 F7 F9 F11 F13 F15 G3 G6 G8 H4 H7 H10 J3 J7 K8 L4 L6 M6 N5 N8 P4 P7 R8 T3 T6 U4 U8 W3 W7 Y8

GPU VERSION A1 AA3 AA8 AA11 AA12 AA13 AA17 AA18 AA22 AA23 AA24 AB4 AB8 AB14 AB15 AB16 AB19 AB20 AB21 AB27 AB31 AC14 AC15 AC16 AC19 AC20 AC21 AC30 AD3 AD8 AD14 AD15 AD16 AD19 AD20 AD21 AD27 AD32 AE6 AE27 AE32 AF4 AF8 AG3 AG6 AG8 AG12 AG14 AG18 AG19 AG21 AG22 AG24 AG26 AG27 AG29 AG31 AH4 AH7 AH28 AH32 AJ3 AJ6 AJ8 AJ10

VSS260 VSS259 VSS258 VSS257 VSS256 VSS255 VSS254 VSS253 VSS252 VSS251 VSS250 VSS249 VSS248 VSS247 VSS246 VSS245 VSS244 VSS243 VSS242 VSS241 VSS240 VSS239 VSS238 VSS237 VSS236 VSS235 VSS234 VSS233 VSS232 VSS231 VSS230 VSS229 VSS228 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS220 VSS219 VSS218 VSS217 VSS216 VSS215 VSS214 VSS213 VSS212 VSS211 VSS210 VSS209 VSS208 VSS207 VSS206 VSS205 VSS204 VSS203 VSS202 VSS201 VSS200 VSS199 VSS198 VSS197 VSS196 X02056-010

IC 12

OF 12

OF 12

GPU VERSION 51

VSS195 VSS194 VSS193 VSS192 VSS191 VSS190 VSS189 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131

F21 F24 F26 F28 F31 G4 G7 G18 G20 G27 G29 G33 H3 H6 H8 H9 H11 H13 H15 H17 H19 H21 H23 H25 H28 J4 J8 J28 K6 K27 K32 L3 L8 L14 L15 L16 L19 L20 L21 L28 M4 M8 M14 M15 M16 M19 M20 M21 M27 M31 N14 N15 N16 N19 N20 N21 N28 N29 N30 P3 P8 P11 P12 P13 P17

AJ15 AJ17 AJ20 AJ25 AJ27 AJ29 AJ31 AK4 AK18 AL3 AL5 AL7 AL9 AL12 AL16 AL19 AL22 AL26 AL27 AL29 AL31 AM4 AM6 AM8 AM11 AM14 AM21 AM24 AM28 AM30 AN3 AN33 B19 B33 C4 C6 C8 C11 C13 C15 C17 C20 C28 C32 D3 D5 D7 D9 D19 D21 D31 E4 E18 E20 E22 E30 E32 F3 F6 F8 F10 F12 F14 F16 F19

VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66

X02056-010

BGA

51 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS20 VSS21 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0

P18 P22 P23 P24 P27 P32 R6 R11 R12 R13 R17 R18 R22 R23 R24 R27 R31 T4 T8 T11 T12 T13 T17 T18 T22 T23 T24 U6 U14 U15 U16 U19 U20 U21 U27 U32 V5 V14 V15 V16 V19 V20 V21 W4 W11 W8 W12 W13 W17 W18 W22 W23 W24 W27 W31 Y6 Y11 Y12 Y13 Y17 Y18 Y22 Y23 Y24 Y27 Y32

BGA

BGA

CORE POWER + MEM POWER]

DRAWING XENON_FABK Wed Aug 24 09:27:11

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 17/73

REV K7

GPU,

DECOUPLING

V_GPUCORE

V_GPUCORE

1

C4R20

2

.1UF 10% 6.3V X5R 402

1

C4R37

2

.1UF 10% 6.3V X5R 402

1

C4R59

2

.1UF 10% 6.3V X5R 402

1

C4T6

2

.1UF 10% 6.3V X5R 402

1

C4T9

2

.1UF 10% 6.3V X5R 402

1

C4R57

2

.1UF 10% 6.3V X5R 402

1

C4T11

2

.1UF 10% 6.3V X5R 402

1

C4T3

2

.1UF 10% 6.3V X5R 402

1

C4R52

2

.1UF 10% 6.3V X5R 402

1

C4R18

2

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=GPU,

1

C4R11

2

.1UF 10% 6.3V X5R 402

1

C4R17

2

.1UF 10% 6.3V X5R 402

1

C4R55

2

.1UF 10% 6.3V X5R 402

1

C4R47

2

.1UF 10% 6.3V X5R 402

1

C4T20

2

.1UF 10% 6.3V X5R 402

1

C4R36

2

.1UF 10% 6.3V X5R 402

1

C4R34

2

.1UF 10% 6.3V X5R 402

1

C4R42

2

.1UF 10% 6.3V X5R 402

1

C4T16

2

.1UF 10% 6.3V X5R 402

1

C4T1

2

.1UF 10% 6.3V X5R 402

1

C4R16

2

.1UF 10% 6.3V X5R 402

1

C4R21

2

.1UF 10% 6.3V X5R 402

1

C4T5

2

.1UF 10% 6.3V X5R 402

1

C4T21

2

.1UF 10% 6.3V X5R 402

1

C4R46

2

.1UF 10% 6.3V X5R 402

1

C4T8

2

.1UF 10% 6.3V X5R 402

1

C4R35

2

.1UF 10% 6.3V X5R 402

1

C4R54

2

.1UF 10% 6.3V X5R 402

1

C4R63

2

.1UF 10% 6.3V X5R 402

1

C4T2

2

.1UF 10% 6.3V X5R 402

DECOUPLING]

1

C4R28

2

.1UF 10% 6.3V X5R 402

1

C4R22

2

.1UF 10% 6.3V X5R 402

1

C4T23

2

.1UF 10% 6.3V X5R 402

1

C4R44

2

.1UF 10% 6.3V X5R 402

1

C4T24

2

.1UF 10% 6.3V X5R 402

1

C4T19

2

.1UF 10% 6.3V X5R 402

1

C4T18

2

.1UF 10% 6.3V X5R 402

1

C4R62

2

.1UF 10% 6.3V X5R 402

1

C4R43

2

.1UF 10% 6.3V X5R 402

1

C4R56

2

.1UF 10% 6.3V X5R 402

1

C4R13

2

.1UF 10% 6.3V X5R 402

1

C5R17

2

.1UF 10% 6.3V X5R 402

1

C4R53

2

.1UF 10% 6.3V X5R 402

1

C4R41

2

.1UF 10% 6.3V X5R 402

1

C4T26

2

.1UF 10% 6.3V X5R 402

1

C4T25

2

.1UF 10% 6.3V X5R 402

1

C4T4

2

.1UF 10% 6.3V X5R 402

1

C4R58

2

.1UF 10% 6.3V X5R 402

1

C4T10

2

.1UF 10% 6.3V X5R 402

1

C4T15

2

.1UF 10% 6.3V X5R 402

1

C5R9

2

.1UF 10% 6.3V X5R 402

1

C5R16

2

.1UF 10% 6.3V X5R 402

2

C5R10

1

.1UF 10% 6.3V X5R 402

1

C5R12

1

C4R39

2

.1UF 10% 6.3V X5R 402

1

C4R49

2

.1UF 10% 6.3V X5R 402

2

C4R67

1

.1UF 10% 6.3V X5R 402

2

C4R24

C4R40

2

C5R8

C4R9

2

C5R14

C4R14

2

1

C5R5

2

2

1

C5R4

C5R2

2

2

2

1

2

2

2

2

2

1

C5R11

2

2

C5R6

2

1

2005

1

C6R47

1

C4R69

1

C5D3

1

C5D4

1

2

C5D6

1

4.7UF 10% 6.3V X5R 805

1

2

10% 4.7UF 6.3V X5R 805

DRAWING XENON_FABK Wed Aug 24 09:27:12

C6E1

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

.1UF 10% 6.3V X5R 402

1

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

2

C6E2

4.7UF 10% 6.3V X5R 805

1

C5R3

1

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

2

C4T17

4.7UF 10% 6.3V X5R 805

2

C5R1

1

4.7UF 10% 6.3V X5R 805

1

C5R20

C4R29

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

1

.1UF 10% 6.3V X5R 402

1

C4R30

10% 4.7UF 6.3V X5R 805

.1UF 10% 6.3V X5R 402

1

2

2

.1UF 10% 6.3V X5R 402

1

2

4.7UF 10% 6.3V X5R 805

4.7UF 10% 6.3V X5R 805

.1UF 10% 6.3V X5R 402

1

1

4.7UF 10% 6.3V X5R 805

.1UF 10% 6.3V X5R 402

1

C5D2

4.7UF 10% 6.3V X5R 805

2

.1UF 10% 6.3V X5R 402

1

2

4.7UF 10% 6.3V X5R 805

C5D5

1

4.7UF 10% 6.3V X5R 805

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 18/73

REV K7

V_1P8 FB1N1 2

2

39

46

C1N8

10UF 10% 6.3V EMPTY 1206

1 2

DB1N1

1

TP

44

19

39

V_ENET

IN

R1B12

2 36

39

OUT

4.7K 5% EMPTY 402

MII_RXD0

ENET_RST_N

10

RESET_N

MII_RX_CLK MII_RXDV MII_RXER

20 19 21

RXC RX_DV/TEST0 RX_ER/TEST1

36 36 36

39 39 39

OUT OUT OUT

MII_RXD3 MII_RXD2 MII_RXD1

15 16 17 18

RXD3/ISOLATE RXD2/F100 RXD1/ANEN RXD0/PHYAD0

36 39

39 36

OUT IN

MII_TX_CLK MII_TXEN

23 24

TXC TX_EN

28 27 26 25

TXD3 TXD2 TXD1 TXD0

14 13

MDC_CLK_OUT MDIO

29 30

COL/ENERGYDET CRS/LOWPWR0

31 32

REGVDDIN REGVDDOUT

39 39 39 39 39 39

36 36

IN

36 36 36 36

IN BI 36 36

19

ENET_REF_CLK2_OUT

OUT OUT OUT

39 39

IN

MII_TXD3 IN MII_TXD2 IN MII_TXD1 IN MII_TXD0 IN MII_MDC_CLK_OUT MII_MDIO

OUT OUT

MII_COL MII_CRS

ENET_AVDD 1 2

[PAGE_TITLE=DUAL

ETHERNET

PHY]

C1N6

.1UF 10% 6.3V EMPTY 402

OUT

2

19

C1N14 .1UF 10% 6.3V EMPTY 402

EMPTY BCM5241

39 39 39

33

C1N7

10UF 20% 6.3V EMPTY 805

1

XTALI2 XTALO2

36 36 36

39

1

2

U1B1

ENET_CLK

IN

1

X801554-001

OVDD2 OVDD1 AVDD

22 9

V_ENET

7

ENET_AVDD

IN

39

IN

19

12 11

ENET_LINK_N ENET_ACT_N

OUT OUT

39 39

44 44

TDP TDN

3 4

ENET_RX_DP ENET_RX_DN

OUT OUT

39 39

44 44

RDP RDN

6 5

ENET_TX_DP ENET_TX_DN

OUT OUT

39 39

44 44

RDAC

8

LINK# ACT#

GND

33

19

44

ENET_RDAC

1

ENET_AVDD

1 EMPTY 603

60 0.5A 0.1DCR

1

R1N8 LCC32

2

1.27K 1% EMPTY 402

DRAWING XENON_FABK Wed Aug 24 09:27:13

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 19/73

REV K7

MEMORY PARTITION CHIP

V_MEM

1

2 14

14 27

26

25

24

23

22

21

13

21

14

21

27

26

25

24

R4F4

60.4 1% CH 402

60.4 1% CH 402

2

U4F1

J11 J10

MEM_RST MA_A<11..0>

IN IN

14

MA_BA<2..0>

IN

CLK_DP CLK_DN

V9

RESET

11 10 9 8 7 6 5 4 3 2 1 0

L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4

A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4

2 1 0

H10 G9 G4

BA2/RAS_N BA1/BA0 BA0/BA1

H4 H9 F4 H3 F9

21 21 21 21

14 14 14 14 14

IN IN IN IN IN

MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS0_N

12

IN

MEM_SCAN_TOP_EN A9

MF

MEM_SCAN_EN

SCAN_EN

26

24

22

23

22

21

12

IN

21

20 21

IN IN

TOP

= 0

IC GDDR136 MF=0

MA_CLK0_DN

IN

A,

MIRROR FUNCTION

1

R4F3

MA_CLK0_DP

IN

SELECT = 0,

V4

MEM_A_VREF1 MEM_A_VREF0

H1 H12

CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N

VREF1 VREF0

V_MEM

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3

BI BI BI BI BI BI BI BI

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2

BI BI BI BI BI BI BI BI

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1

BI BI BI BI BI BI BI BI

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0

BI BI BI BI BI BI BI BI

ZQ

A4

14 14 14 14 14 14 14 14

IN OUT IN 14 14 14 14 14 14 14 14

IN OUT IN 14 14 14 14 14 14 14 14

IN OUT IN 14 14 14 14 14 14 14 14

IN OUT IN

U4F1

21 21 21 21 21 21 21 21 14 21 14

21 14 21

21 21 21 21 21 21 21 21 14 21 14

21 14 21

21 21 21 21 21 21 21 21 14 21 14 21 21 21 21 21 21 21 21 14 21 14

21 14 21

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=0 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

X801995-006 21 14 21

MA_ZQ_TOP

1

R3F1

X801995-006

1

R4U4

2

549 1% CH 402

2

MEM_A_VREF1

OUT

20

PARTITION

A DECOUPLING V_MEM

1 R4U5 1.27K 1% CH 402

C4U9

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

V_MEM MEMORY A,

TOP,

DECOUPLING

21

1

2

243 1% CH 402

2

PARTITION

A,

TOP]

C4F12

10UF 10% 6.3V X5R 1206

C3F3

.22UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:13

C4F9

.22UF 10% 6.3V X5R 402

2005

C4F11

.22UF 10% 6.3V X5R 402

C4F7

.22UF 10% 6.3V X5R 402

C3F1 .22UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

C4F1

.22UF 10% 6.3V X5R 402

C4F6

.22UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

C4F3

.22UF 10% 6.3V X5R 402

PAGE 20/73

REV K7

MEMORY PARTITION

V_MEM

CHIP

1

2 14

24

23

22 27

20 26 20

IN

MA_CLK1_DN

13 25 14

IN IN

MEM_RST MA_A<11..0>

20

27 26

25

24

23

R4U3

60.4 1% CH 402

60.4 1% CH 402

2

U4U1

IC GDDR136 MF=1

14

25 22

14

J11 J10

11 10 9 8 7 6 5 4 3 2 1 0

MA_BA<2..0>

IN

20 20 20 20

14 14 14 14 14

IN IN IN IN IN

23

12

IN

2 1 0

MA_CKE MA_WE_N MA_CAS_N MA_RAS_N MA_CS1_N

CLK_DP CLK_DN

V9

RESET

L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9

A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0

H3 G4 G9

RAS_N/BA2 BA0/BA1 BA1/BA0

H9 H4 F9 H10 F4

MEM_SCAN_BOT_EN

20

12 27

IN

MEM_SCAN_EN

20

21 20

IN IN

MEM_A_VREF0 MEM_A_VREF1

WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N

A9

MF

V4

SCAN_EN

H1 H12

VREF1 VREF0

V_MEM

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_WDQS2 MA_RDQS2 MA_DM2

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_WDQS0 MA_RDQS0 MA_DM0

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1

ZQ

A4

= 1

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

U4U1

20 20 20 20 20 20 20 20 14 20 14

20 14 20

20 20 20 20 20 20 20 20 14 20 14

20 14 20

20 20 20 20 20 20 20 20 14 20 14 20 20 20 20 20 20 20 20 14 20 14

20 14 20

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=1 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3 J3 J2

NC<1> NC<0>

X801995-006 20 14 20

R3U1

549 1% CH 402

2

MEM_A_VREF0

243 1% CH 402

V_MEM MEMORY A,

OUT

20

C3U2

.22UF 10% 6.3V X5R 402

C4F2 .1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

BOTTOM,

DECOUPLING

21

1 1.27K 1% CH 402

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

1

R4F1

R4F2

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

MA_ZQ_BOT

1

2

BOTTOM

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

X801995-006

2

A,

MIRROR FUNCTION

1

R4U2

MA_CLK1_DP

IN

SELECT = 1,

PARITION

A,

BOTTOM]

DRAWING XENON_FABK Wed Aug 24 09:27:14

C4U8

.22UF 10% 6.3V X5R 402

2005

C4U11

.22UF 10% 6.3V X5R 402

C4U6

.22UF 10% 6.3V X5R 402

C3U1 .22UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

C4U1 .22UF 10% 6.3V X5R 402

C4U5

.22UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

C4U2

.22UF 10% 6.3V X5R 402

PAGE 21/73

REV K7

MEMORY PARTITION CHIP

V_MEM

1 60.4 1% CH 402

60.4 1% CH 402

2

14 25

24

23

21

20 27 23

26 26

25

24

23

24 21

MEM_RST MB_A<11..0>

IN IN

23

20

14

IN

23 23 23 23

14 14 14 14 14

12

J11 J10

MB_CLK0_DN

IN

13 26 14

IN

20

12 27

IN

23

22 23

IN IN

MB_BA<2..0>

CLK_DP CLK_DN

V9

RESET

11 10 9 8 7 6 5 4 3 2 1 0

L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4

A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4

2 1 0

H10 G9 G4

BA2/RAS_N BA1/BA0 BA0/BA1

MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS0_N

IN IN IN IN IN

MEM_SCAN_TOP_EN MEM_SCAN_EN MEM_B_VREF1 MEM_B_VREF0

H4 H9 F4 H3 F9

CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N

A9

MF

V4 H1 H12

V_MEM

IC GDDR136 MF=0

MB_CLK0_DP

IN

TOP

= 0

R5F4

U5F1 14

B,

MIRROR FUNCTION

1

R5F3

2

SELECT = 0,

SCAN_EN VREF1 VREF0

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0

ZQ

A4

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

U5F1

23 23 23 23 23 23 23 23 14 23 14

23 14 23

23 23 23 23 23 23 23 23 14 23 14

23 14 23

23 23 23 23 23 23 23 23 14 23 14 23 23 23 23 23 23 23 23 14 23 14

23 14 23

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=1 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

X801995-006 23 14 23

MB_ZQ_TOP

1 1

2

R4F5

X801995-006

R5U4 549 1% CH 402

2

MEM_B_VREF1

OUT

22

V_MEM MEMORY B,

C4F10

1 R5U3 1.27K 1% CH 402

C5U5 .1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

2

PARITION

B,

TOP]

TOP,

DECOUPLING

PARTITION B DECOUPLING V_MEM

23

1

2

243 1% CH 402

C5F6 10UF 10% 6.3V X5R 1206

.22UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:14

C5F5

.22UF 10% 6.3V X5R 402

2005

C4F8

.22UF 10% 6.3V X5R 402

C4F5 .22UF 10% 6.3V X5R 402

C4F4

.22UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

C5F2

.22UF 10% 6.3V X5R 402

C5F3

.22UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

C5F4

.22UF 10% 6.3V X5R 402

PAGE 22/73

REV K7

MEMORY PARTITION CHIP

SELECT = 1,

B,

MIRROR FUNCTION

BOTTOM = 1

V_MEM

1

1

2 14

24

21 27

20 26 22

14

IN

13 25 14

IN IN

22

27 26

25

24

22

R5U1

60.4 1% CH 402

60.4 1% CH 402

2

U5U1

IC GDDR136 MF=1

MB_CLK1_DP

IN

22

R5U2

25 21

14

J11 J10

MB_CLK1_DN MEM_RST MB_A<11..0>

IN

22 22 22 22

14 14 14 14 14

IN IN IN IN IN

21

12

IN

20

12 27

IN

22

23 22

IN IN

11 10 9 8 7 6 5 4 3 2 1 0

MB_BA<2..0>

V9

RESET

L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9

A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0

H3 G4 G9

2 1 0

MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS1_N

H9 H4 F9 H10 F4

MEM_SCAN_BOT_EN MEM_SCAN_EN

A9 V4

MEM_B_VREF0 MEM_B_VREF1

CLK_DP CLK_DN

H1 H12

RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N MF SCAN_EN VREF1 VREF0

V_MEM

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2

BI BI BI BI BI BI BI BI

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3

BI BI BI BI BI BI BI BI

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0

BI BI BI BI BI BI BI BI

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1

ZQ

A4

14 14 14 14 14 14 14 14

IN OUT IN 14 14 14 14 14 14 14 14

IN OUT IN 14 14 14 14 14 14 14 14

IN OUT IN 14 14 14 14 14 14 14 14

BI BI BI BI BI BI BI BI IN OUT IN

U5U1

22 22 22 22 22 22 22 22 14 22 14

22 14 22

22 22 22 22 22 22 22 22 14 22 14

22 14 22

22 22 22 22 22 22 22 22 14 22 14 22 22 22 22 22 22 22 22 14 22 14

22 14 22

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=1 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

X801995-006 22 14 22

MB_ZQ_BOT

1 1

2

R4U1

X801995-006

R5F1 549 1% CH 402

2

MEM_B_VREF0

OUT

22

2

1.27K 1% CH 402

V_MEM MEMORY B,

23

1

R5F2

243 1% CH 402

C4U10

.22UF 10% 6.3V X5R 402

C5F1

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

PARTITION

B,

BOTTOM]

DRAWING XENON_FABK Wed Aug 24 09:27:15

C5U4

.22UF 10% 6.3V X5R 402

2005

C4U7

.22UF 10% 6.3V X5R 402

BOTTOM,

C4U4 .22UF 10% 6.3V X5R 402

DECOUPLING

C4U3

.22UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

C5U1 .22UF 10% 6.3V X5R 402

C5U2

.22UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

C5U3

.22UF 10% 6.3V X5R 402

PAGE 23/73

REV K7

MEMORY PARTITION CHIP

C,

SELECT = 0,

MIRROR FUNCTION

BI BI BI BI BI BI BI BI

TOP

= 0

V_MEM

1

2 15

27

26

25

23

22

26 27

26

25

23

22

21

22 21

R3D4

60.4 1% CH 402

60.4 1% CH 402

2

U3D1

IC GDDR136 MF=0

MC_CLK0_DP

IN

15

IN

20

13

25

15

IN IN

25

15

25 25 25 25

15 15 15 15 15

IN IN IN IN IN

20

12

IN

20

1

R3D5

12

IN

25

24 25

J11 J10

MC_CLK0_DN MEM_RST MC_A<11..0>

IN

MC_BA<2..0>

V9

RESET

11 10 9 8 7 6 5 4 3 2 1 0

L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4

A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4

2 1 0

H10 G9 G4

BA2/RAS_N BA1/BA0 BA0/BA1

MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS0_N

H4 H9 F4 H3 F9

CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N

MEM_SCAN_TOP_EN

A9

MF

MEM_SCAN_EN IN IN

CLK_DP CLK_DN

V4

MEM_C_VREF1 MEM_C_VREF0

H1 H12

SCAN_EN VREF1 VREF0

V_MEM

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0

ZQ

A4

IN OUT IN 15 15 15 15 15 15 15 15

BI BI BI BI BI BI BI BI IN OUT IN

15 15 15 15 15 15 15 15

BI BI BI BI BI BI BI BI IN OUT IN

15 15 15 15 15 15 15 15

BI BI BI BI BI BI BI BI IN OUT IN

U3D1

25 25 25 25 25 25 25 25 15 25 15

25 15 25

25 25 25 25 25 25 25 25 15 25 15

25 15 25

25 25 25 25 25 25 25 25 15 25 15 25 25 25 25 25 25 25 25 15 25 15

25 15 25

2

549 1% CH 402

MEM_C_VREF1

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

X801995-006 25 15 25

243 1% CH 402

V_MEM MEMORY C,

C2E1

OUT

24

25

1 C2R9

2

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

PARITION

C,

TOP]

TOP,

DECOUPLING

PARTITION C DECOUPLING V_MEM

1

2

V2 M12 M1 V11 F12 F1 A11 A2

GDDR136 MF=0

R3D1

R2R1

1.27K 1% CH 402

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

1

1

R2R2

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

MC_ZQ_TOP

X801995-006

2

15 15 15 15 15 15 15 15

C2D3

10UF 20% 6.3V X5R 805

1 2

C3C5

10UF 20% 6.3V X5R 805

1 2

C2E8

.22UF 10% 6.3V X5R 402

C3E2

.22UF 10% 6.3V X5R 402

C3E1

.22UF 10% 6.3V X5R 402

C3E3

.22UF 10% 6.3V X5R 402

C3E5

.22UF 10% 6.3V X5R 402

C3E7

.22UF 10% 6.3V X5R 402

C3E6

.22UF 10% 6.3V X5R 402

C2E3

.22UF 10% 6.3V X5R 402

10UF 20% 6.3V X5R 805

DRAWING XENON_FABK Wed Aug 24 09:27:15

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 24/73

REV K7

MEMORY PARTITION CHIP

SELECT = 1,

C,

MIRROR FUNCTION

BOTTOM = 1

V_MEM

1

2 15

26

24

23

22

21

20

13

27

26

24

23

22

23 21

60.4 1% CH 402

2

U3R1

24

15

IN IN

15

J11 J10

MEM_RST MC_A<11..0>

11 10 9 8 7 6 5 4 3 2 1 0

MC_BA<2..0>

IN

2 1 0

24 24 24 24

15 15 15 15 15

IN IN IN IN IN

MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS1_N

21

12

IN

MEM_SCAN_BOT_EN

20

12

25 24

L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9

A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0

A9 V4

MEM_C_VREF0 MEM_C_VREF1

IN IN

RESET

H9 H4 F9 H10 F4

MEM_SCAN_EN

IN 24

CLK_DP CLK_DN

V9

H3 G4 G9

H1 H12

V_MEM

IC GDDR136 MF=1

MC_CLK1_DN

IN

24

27

R2R3

60.4 1% CH 402

MC_CLK1_DP

IN

15 27

1

R2R4

RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N MF SCAN_EN VREF1 VREF0

V_MEM

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3

BI BI BI BI BI BI BI BI

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0

BI BI BI BI BI BI BI BI

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1

BI BI BI BI BI BI BI BI

ZQ

A4

V_MEM

15 15 15 15 15 15 15 15

BI BI BI BI BI BI BI BI IN OUT IN

15 15 15 15 15 15 15 15

IN OUT IN 15 15 15 15 15 15 15 15

IN OUT IN 15 15 15 15 15 15 15 15

IN OUT IN

U3R1

24 24 24 24 24 24 24 24 15 24 15

24 15 24

24 24 24 24 24 24 24 24 15 24 15

24 15 24

24 24 24 24 24 24 24 24 15 24 15 24 24 24 24 24 24 24 24 15 24 15

1 2

C3T4

.1UF 10% 6.3V X5R 402

24 15 24

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=1 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

X801995-006

24 15 24

MC_ZQ_BOT

1 1

R3R1

X801995-006

R3D3

2

549 1% CH 402

2

MEM_C_VREF0

OUT

24

243 1% CH 402

V_MEM MEMORY C,

C2T1

.22UF 10% 6.3V X5R 402

1

R3D2

2

1.27K 1% CH 402

C3D3

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

BOTTOM,

DECOUPLING

25

PARTITION

C,

BOTTOM]

C3T1

.22UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:16

C3T2

.22UF 10% 6.3V X5R 402

2005

C3T3

.22UF 10% 6.3V X5R 402

C3T5

.22UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

C3T7

.22UF 10% 6.3V X5R 402

C3T6

.22UF 10% 6.3V X5R 402

C2T3

.22UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

PAGE 25/73

REV K7

MEMORY PARTITION

V_MEM

CHIP 1

15 25

24

23

22

21

20

23

2

15 15 15 15 15

U3E1

J11 J10

RESET

11 10 9 8 7 6 5 4 3 2 1 0

L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4

A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4

2 1 0

H10 G9 G4

BA2/RAS_N BA1/BA0 BA0/BA1

MD_CKE MD_WE_N MD_CAS_N MD_RAS_N MD_CS0_N MEM_SCAN_TOP_EN

A9

MF

MEM_SCAN_EN

V4

SCAN_EN

22

20

12

IN

22

21

20

12

IN

27

CLK_DP CLK_DN

V9

26 27

MEM_D_VREF1 MEM_D_VREF0

IN IN

H4 H9 F4 H3 F9

CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N

H1 H12

VREF1 VREF0

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3

BI BI BI BI BI BI BI BI

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2

BI BI BI BI BI BI BI BI

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1

BI BI BI BI BI BI BI BI

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

ZQ

A4

V_MEM

MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0

2

549 1% CH 402

15 15 15 15 15 15 15 15

IN OUT IN 15 15 15 15 15 15 15 15

IN OUT IN 15 15 15 15 15 15 15 15

BI BI BI BI BI BI BI BI IN OUT IN

27 15 27

27 27 27 27 27 27 27 27 15 27 15

27 15 27

27 27 27 27 27 27 27 27 15 27 15 27 27 27 27 27 27 27 27 15 27 15

1 2

U3E1

C3R3 .1UF 10% 6.3V X5R 402

27 15 27

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=0 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

X801995-006

27 15 27

243 1% CH 402

V_MEM MEMORY D, PARTITION

OUT

26

27

1

1

2

C2T2

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

PARTITION

D,

TOP]

TOP,

DECOUPLING

D DECOUPLING V_MEM C2D2

MEM_D_VREF1

2

IN OUT IN

27 27 27 27 27 27 27 27 15 27 15

R3E1

R2T4

1.27K 1% CH 402

15 15 15 15 15 15 15 15

1

1

R2T3

V_MEM

MD_ZQ_TOP

X801995-006

2

CAP

V_MEM

IC

IN IN IN IN IN

24

TOP

= 0

MD_CLK0 STITCHING

GDDR136 MF=0

MD_BA<2..0>

IN

27 27 27 27

24

60.4 1% CH 402

MEM_RST MD_A<11..0>

IN IN

15

27

25

R3E4

60.4 1% CH 402

MD_CLK0_DN

IN

13 27 15

27

27

R3E5

MD_CLK0_DP

IN

D,

MIRROR FUNCTION

1

2 15

SELECT = 0,

C2E2 10UF 20% 6.3V X5R 805

.22UF 10% 6.3V X5R 402

C2D1

.22UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:16

C3D1

.22UF 10% 6.3V X5R 402

2005

C3D2

.22UF 10% 6.3V X5R 402

C3D4

.22UF 10% 6.3V X5R 402

MICROSOFT CONFIDENTIAL

C3D6

.22UF 10% 6.3V X5R 402

C3D5

.22UF 10% 6.3V X5R 402

C2D4

.22UF 10% 6.3V X5R 402

PROJECT NAME XENON_RETAIL

PAGE 26/73

REV K7

MEMORY PARTITION V_MEM

1

CHIP

R2T5

R2T6

60.4 1% CH 402

60.4 1% CH 402

2

U3T1

15 23

22

21 26

20 25 26

26

25

24

23

MEM_RST MD_A<11..0>

IN IN

15

J11 J10

MD_CLK1_DN

IN

13 24 15

11 10 9 8 7 6 5 4 3 2 1 0

MD_BA<2..0>

IN

2 1 0

RESET

L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9

A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0

H3 G4 G9

RAS_N/BA2 BA0/BA1 BA1/BA0

15 15 15 15 15

IN IN IN IN IN

MD_CKE MD_WE_N MD_CAS_N MD_RAS_N MD_CS1_N MEM_SCAN_BOT_EN

A9

MF

MEM_SCAN_EN

V4

SCAN_EN

23

21

12

IN

22

21

20

12 26

IN

26

27 26

H9 H4 F9 H10 F4

MEM_D_VREF0 MEM_D_VREF1

IN IN

= 1

V_MEM

CLK_DP CLK_DN

V9

26 26 26 26

25

BOTTOM

IC GDDR136 MF=1

MD_CLK1_DP

IN

D,

MIRROR FUNCTION

1

2

15

SELECT = 1,

H1 H12

WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N

VREF1 VREF0

DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3

T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3

MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2

DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2

T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10

MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3

BI BI BI BI BI BI BI BI

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1

G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10

MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0

BI BI BI BI BI BI BI BI

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0

G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3

MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1

BI BI BI BI BI BI BI BI

ZQ

A4

V_MEM

15 15 15 15 15 15 15 15

BI BI BI BI BI BI BI BI IN OUT IN

15 15 15 15 15 15 15 15

IN OUT IN 15 15 15 15 15 15 15 15

IN OUT IN

U3T1

26 26 26 26 26 26 26 26 15 26 15

26 15 26

26 26 26 26 26 26 26 26 15 26 15

26 15 26

26 26 26 26 26 26 26 26 15 26 15

26 15 26

V_MEM 15 15 15 15 15 15 15 15

IN OUT IN

26 26 26 26 26 26 26 26 15 26 15

1 2 26 15 26

IC

V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1

VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

V2 M12 M1 V11 F12 F1 A11 A2

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

K12 K1

VDDA<1> VDDA<0>

J12 J1

VSSA<1> VSSA<0>

GDDR136 MF=1 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>

T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1

VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

V3 L12 L1 G12 G1 A10 V10 A3

NC<1> NC<0>

J3 J2

C2T7

10UF 10% 6.3V X5R 1206

X801995-006

MD_ZQ_BOT

1 1

R3T1

X801995-006

R3E3

2

549 1% CH 402

2

MEM_D_VREF0

OUT

26

27

243 1% CH 402

V_MEM MEMORY D,

MEMORY D, R3E2

2

C2R7

V_MEM

1 1.27K 1% CH 402

BOTTOM,

.22UF 10% 6.3V X5R 402

DECOUPLING

C3R1

.22UF 10% 6.3V X5R 402

C3R2 .22UF 10% 6.3V X5R 402

BOTTOM,

C3R4

.22UF 10% 6.3V X5R 402

DECOUPLING

C3R7

.22UF 10% 6.3V X5R 402

C3R6

.22UF 10% 6.3V X5R 402

C2R10

.22UF 10% 6.3V X5R 402

C2R8

.22UF 10% 6.3V X5R 402

C3E4

.1UF 10% 6.3V X5R 402

[PAGE_TITLE=MEMORY

C2R13 .22UF 10% 6.3V X5R 402

PARITION

D,

BOTTOM]

C2T6 .22UF 10% 6.3V X5R 402

C3E8 .22UF 10% 6.3V X5R 402

C3F5

.22UF 10% 6.3V X5R 402

C3U4

.22UF 10% 6.3V X5R 402

C4F14

.22UF 10% 6.3V X5R 402

C4F15

.22UF 10% 6.3V X5R 402

C4U12

.22UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:17

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 27/73

REV K7

ANA,

V_12P0

CLOCKS + STRAPPING

ANA_V_12P0_DET_R

V_3P3STBY

R4B9

1

1% CH

1

FTP

FT2P7

2

1

2

R4B3 1K 5% CH 402

1

R3B1

1

5% CH

C4N28

2

2

2

R4B2

1

75 402

1% CH

FT3N1

FTP

2 68.1 402

1 of

U4B1

3

ANA VERSION

1

112 138 16

ANA_POR_BYPASS

ANA_VRST_OK ANA_V12P0_PWRGD SMC_RST_N

1

R2P3

1 1

1

10K 402

ANA_RST_N

IN

1% CH

470PF 5% 50V EMPTY 402

ANA_V_12P0_DET

34

R4B8

1

1K 402

IC

1K 5% CH 402

95

V_12P0_DET CORE_RST_N* POR_BYPASS

V_RST_OK V_12P0_OK SMC_RST_N*

120 122 140

2

R2P1

2

SMC_RST_N_R

10K 402

46

1 46

34

IN

FTP

IN

ANA_XTAL_IN

FT2P4

R4B17

1K 402

2

1

XTAL_IN XTAL_OUT

CPU_CLK_DP CPU_CLK_DN

30 29

ANA_CPU_CLK_DP

132

XTAL_VSS

NB_CLK_DP NB_CLK_DN

27 26

ANA_GPU_CLK_DP

22 21

ANA_PCIEX_CLK_DP

126

ANA_XTAL_BYPASS

2

ANA_CLK_OE

130 131

ANA_CLK_OE_R

5% CH

139

ANA_CLK_OE

R4B16 10K 5% CH 402

36

ANA_PLL_BYP_VID_VREF

24

ANA_CLK_DRV_RSET

VREFGEN_18S1 CLK_DRV_RSET

1

SATA_CLK_DP SATA_CLK_DN

19 18

SATA_CLK_REF

13

R4P1 V_1P8STBY 2

475 1% CH 402

46 56 46 56

34 34

BI IN

SMB_DATA SMB_CLK

SMB_DATA SMB_CLK

72 69 71 70

ANA_TCLK ANA_TDO ANA_TDI ANA_TMS

R4P3

2

FT2N3

FTP

FT3P4

1 1

ANA_PCIEX_CLK_DN

1 1

ANA_SATA_CLK_DP ANA_SATA_CLK_DN

1

TP

DB3C3

TP

DB3C4

TP

DB3C1

TP

DB3C2

TP

DB3B4

TP

DB3B3

TP

DB3B2

TP

1 2

11

DB3B1

ANA_ENET_CLK

1

STBY_CLK

136

ANA_STBY_CLK

1

14

AUD_CLK_R

ANA_PIX_CLK_2X_DN_R DB3N2 TP DB4N4 TP

35

1

127

R3C14

33 402

PLL_BYP_VID

1

AV_CLK

TCK TDO TDI TMS

FTP

2

R3C20 2

1 49.9 402

5% CH

1% CH

ANA_PIX_CLK_2X_DP ANA_PIX_CLK_2X_DN

FT4N5

R3C13

R3C19 2

1

5% CH

33 402

1

2

49.9 402

1 1

1% CH

10K 5% CH 402

QFP144

2

.1UF 10% 6.3V X5R 402

1 1

R3B15

33 402 FT4P1

FTP

2

AUD_CLK

2

1

R5C1

1.5K 1% CH 402

1.5K 1% CH 402

J5C1

1

R5C3

2

[PAGE_TITLE=ANA,

CLOCKS

2

2X3HDR 2 4 6

2

1

R5C2

1 3 5

FTP FTP

FT4P2 FT4P3

FTP

FT2P2

OUT

36

1

V_1P8STBY

1

13 13

5% CH

1 V_1P8STBY

OUT OUT

R4B7

X02014-005

C4P6

56

DB3N3

1

332 1% CH 402

332 1% CH 402

ANA_GPU_CLK_DN

ENET_CLK

AV_CLK

R4P4

1

1 1

ANA_PIX_CLK_2X_DP_R

PLL_BYP_VID

1

2

1 1

33 32

AUD_CLK 8 9

FTP

48 46

TP

PIX_CLK_OUT_DP PIX_CLK_OUT_DN

1

34 34

1

ANA_CPU_CLK_DN

ANA_SATA_CLK_REF

FT4N2

5% CH

XTAL_BYPASS PCIEX_CLK_DP PCIEX_CLK_DN

FTP

OUT OUT

C3B12 10PF 5% 50V EMPTY 402

R4P5 10K 5% CH 402

ENET_CLK

2

SATA_CLK_REF

V_3P3

STITCH

V_3P3

STITCH

EMPTY

1.5K 1% CH 402

+ STRAPPING

1 2

C1B4 .1UF 10% 6.3V X5R 402

1 2

1 C2B14

.1UF 10% 6.3V X5R 402

2

C2B17

.1UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:18

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 28/73

REV K7

ANA,

VIDEO + FAN + JTAG U4B1

13

V_1P8STBY

13

IN IN

1

2

13 13

IN IN

33

OUT

43

DAC_B_OUT_DP DAC_B_OUT_DN

95 94

VID_DACB_DP VID_DACB_DN

OUT

43

DAC_C_OUT_DP DAC_C_OUT_DN

99 100

VID_DACC_DP VID_DACC_DN

OUT

43

DAC_D_OUT_DP DAC_D_OUT_DN

102 103

VID_DACD_DP VID_DACD_DN

OUT

43

115 116

VID_HSYNC_OUT_R VID_VSYNC_OUT_R

OUT OUT

43 43

GPU_VSYNC_OUT GPU_HSYNC_OUT

42 41

HSYNC_IN VSYNC_IN

ANA_VID_VREF

54

VREFGEN_18S0

97

DAC_RSET

86 87

FAN_OP2_DP FAN_OP2_DN

FAN_OUT2

88

FAN2_OUT

FAN2_FDBK

82 83

FAN_OP1_DP FAN_OP1_DN

FAN_OUT1

84

FAN1_OUT

FAN1_FDBK

76

TEMP_N

C4P12 .1UF 10% 6.3V X5R 402

OUT

VID_DACA_DP VID_DACA_DN

PIX_DATA14 PIX_DATA13 PIX_DATA12 PIX_DATA11 PIX_DATA10 PIX_DATA9 PIX_DATA8 PIX_DATA7 PIX_DATA6 PIX_DATA5 PIX_DATA4 PIX_DATA3 PIX_DATA2 PIX_DATA1 PIX_DATA0

1

2

ANA_VID_INT

92 91

67 66 64 63 61 60 58 57 53 52 49 48 47 46 44

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

332 1% CH 402

332 1% CH 402

128

DAC_A_OUT_DP DAC_A_OUT_DN

PIX_CLK_IN

R4P7

R4P6

IC 95

55

1

2

2 OF 3 ANA VERSION

GPU_PIX_CLK_1X PIX_DATA<14..0>

R4B12

2 806 402

VID_INT

1 HSYNC_OUT VSYNC_OUT

2

1

ANA_DAC_RSET

1

IN

2

SMC_PWM1

R4B15

205K 402

1

R4B13

R4B14

37.4 1% CH 402

37.4 1% CH 402

37.4 1% CH 402

2

1% CH

1 2

IN

42

IN

C4N24 .22UF 10% 6.3V X5R 402

1 34

IN

SMC_PWM0

2 205K 402

R4C1

1

1% CH

FTP

FAN_OP1_DP

1 2

FT4N4

111

BND_GAP_CAP

C4P2

78

TEMP_RSET

.22UF 10% 6.3V X5R 402

BND_GAP_CAP TEMP_RSET X02014-005

OUT

42

OUT

42

DB4P2

2

ST4C1

2

CPU_TEMP_N

1 SHORT ST4C2

13

IN

GPU_TEMP_N

2

1 1

SHORT

FT4N1

C4B3

0.01UF 10% 16V X7R 402

IN

EDRAM_TEMP_N

2

FTP

BRD_TEMP_N

2

TP

TEMP3_P TEMP2_P TEMP1_P TEMP0_P TEMPCAL_P

75 77 79 80 73

1

CAL_TEMP_P

CAL_TEMP_N CPU_TEMP_P GPU_TEMP_P EDRAM_TEMP_P BRD_TEMP_P

OUT OUT OUT OUT OUT

2

SATA_CLK_REF

C5C6

1000PF 10% 50V EMPTY 402

STITCH

V_3P3

1

C1P13

R4C2

2

29 4 13 13 29

QFP144

1

1

ST4C5 13

DB5P2

TP

1 1

TP

1

1

TP

IN

2

CUSTOM THERMAL CALIBRATION PADS LOCATION MUST REMAIN LOCKED

DB5P1

TP

1

DB4P3

4

2

1% CH

FAN_OP2_DP

42

1

R4B11

37.4 1% CH 402

DB4P1

34

1

R4B10

11K 1% CH 402

.1UF 10% 6.3V X5R 402

2

V_1P8

1 SHORT

STBY_CLK

STITCH

ST4C4 29

IN

1 SHORT

IN

2

CAL_TEMP_N

V_3P3STBY

V_1P8STBY

1

1

1

V_3P3STBY

Q1G3

ST4C3 29

V_1P8STBY MMBT3906 XSTR 1

2

1 SHORT

2

3

C2R2 .1UF 10% 6.3V X5R 402

29

[PAGE_TITLE=ANA,

IN OUT

BRD_TEMP_P BRD_TEMP_N

.1UF 10% 6.3V X5R 402

2

V_1P8STBY

3 29

2

C2R1

C3N10

.1UF 10% 6.3V X5R 402

1 2

C2P50 .1UF 10% 6.3V X5R 402

Q1G1

1

MMBT2222 EMPTY 2

VIDEO + FAN + JTAG]

DRAWING XENON_FABK Wed Aug 24 09:27:19

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 29/73

REV K7

ANA,

V_1P8STBY

POWER + DECOUPLING

FB3B2 1

1

V_1P8STBY 1

0.5

1

ANA_VDD_DAC18S

2

OUT

FB 603

120 0.2A DCR

1

C4N13

10UF 10% 6.3V X5R 1206

2

2

C4N26 2.2UF 10% 6.3V X5R 603

1 2

C4B6 .1UF 10% 6.3V X5R 402

1

V_1P8STBY

30

.1UF 10% 6.3V X5R 402

ANA VERSION 104 90 105

FB4N4 2

ANA_VDD_I18S

FB 603

1 2

C4P4

10UF 20% 6.3V X5R 805

C4N21

C4P7

.1UF 10% 6.3V X5R 402

C4P3

.1UF 10% 6.3V X5R 402

C4P11

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

C4P9

.1UF 10% 6.3V X5R 402

V_1P8STBY

FB4N3 1 60 0.5A 0.1DCR

C4N14 10UF 10% 6.3V X5R 1206

ANA_VDD_C18S

2 FB 603

1 2

C4N15 C4N19 10UF 20% 6.3V X5R 805

.1UF 10% 6.3V X5R 402

C4P10

C4P8

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

C4P1

.1UF 10% 6.3V X5R 402

C4N11

.1UF 10% 6.3V X5R 402

C4N7

.1UF 10% 6.3V X5R 402

V_3P3STBY

C4N5 .1UF 10% 6.3V X5R 402

C4N6

.1UF 10% 6.3V X5R 402

C4N8

.1UF 10% 6.3V X5R 402

2

C4N10 3 of

V_1P8STBY

60 0.5A 0.1DCR

.22UF 10% 6.3V X5R 402

C3B3

0.5

10UF 20% 6.3V X5R 805

120 0.2A DCR

FB 603

C4B7

2

U4B1

1

1

C4B4

2

VDD_I18S4 VDD_I18S3 VDD_I18S2 VDD_I18S1 VDD_I18S0

17 28 34 56 62

VSS_I18S4 VSS_I18S3 VSS_I18S2 VSS_I18S1 VSS_I18S0

121 134 10 25 45 59

VDD_C18S5 VDD_C18S4 VDD_C18S3 VDD_C18S2 VDD_C18S1 VDD_C18S0

119 133

VSS_C18S5 VSS_C18S4 VSS_C18S3 VSS_C18S2 VSS_C18S1 VSS_C18S0

7 23 50 68 117 125 123 124 135 12

VDD_I33S3 VDD_I33S2<2> VDD_I33S2<1> VDD_I33S2<0> VDD_I33S1 VDD_I33S0

118 137 15

VSS_I33S2 VSS_I33S1 VSS_I33S0

2

95

VAA_PLL18S6 AVSS_PLL18S6

142 141

VAA_PLL18S5 AVSS_PLL18S5

144 143

VAA_PLL18S4 AVSS_PLL18S4

2 1

VAA_PLL18S3 AVSS_PLL18S3

4 3

VAA_PLL18S2 AVSS_PLL18S2

6 5 38 37

VAA_PLL18S0 AVSS_PLL18S0

40 39

VAA_XTAL33S

129

VAA_FAN33S AVSS_FAN33S

85 89

VAA_POR33S AVSS_POR33S

114 110

VAA_RTS33S AVSS_RTS33S

74 81

AVSS_DAC33M1 AVSS_DAC33M0 NC<1> NC<0>

X02014-005

1 2

ANA_VAA_PLL18S0

V_3P3STBY

100 402

1 2

96 101 106

C4N22 .1UF 10% 6.3V X5R 402

1

2

1

C4N9

.1UF 10% 6.3V X5R 402

2

1

2

2

5% CH

93 98 107 108

ANA_VAA_DAC33M

2

.22UF 10% 6.3V X5R 402

C3B8 .22UF 10% 6.3V X5R 402

C3B9 .22UF 10% 6.3V X5R 402

V_1P8STBY

.1UF 10% 6.3V X5R 402

FB4C2 1

2

C4C4 .22UF 10% 6.3V X5R 402

1 2

C4C5

0.5

10UF 20% 6.3V X5R 805

120 0.2A DCR

2 FB 603

V_3P3STBY FB4P1

ANA_VDD_DAC18S 1

C4B9

C4N4

1

1

IN

R4N1

1

ANA_VAA_XTAL33S

QFP144

30

.22UF 10% 6.3V X5R 402

ANA_VAA_PLL18S1

1

VAA_PLL18S1 AVSS_PLL18S1

VAA_DAC33M2 VAA_DAC33M1 VAA_DAC33M0

C4B5

113 109

2

C4N17

.1UF 10% 6.3V X5R 402

1

.1UF 10% 6.3V X5R 402

IC VAA_POR18S AVSS_POR18S

VDD_DAC18S1 VDD_DAC18S0 VSS_DAC18S

20 31 43 51 65

3

ANA_VAA_RTS33S

FB4N2

2

C4P5 .1UF 10% 6.3V X5R 402

0.5

1

120 0.2A DCR

FB 603

1

C4P13

2.2UF 10% 6.3V X5R 603

2

1

2

2

2 C4N23

C4C3

.22UF 10% 6.3V X5R 402

10UF 10% 6.3V X5R 1206

V_3P3 FB4N1 1

1 2

[PAGE_TITLE=ANA,

POWER + DECOUPLING]

C4N18

.1UF 10% 6.3V X5R 402

1 2

C4N16

.1UF 10% 6.3V X5R 402

1 2

C4N12 .1UF 10% 6.3V X5R 402

1 2

DRAWING XENON_FABK Wed Aug 24 09:27:20

C4N2

10UF 20% 6.3V X5R 805

2005

2

60 0.5A 0.1DCR

FB 603

1 2

C4N3 10UF 10% 6.3V X5R 1206

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 30/73

REV K7

DEBUG BOARD MAPPING

IN

CPU_DBGSEL_DEBUG<0..69> N:CONNECT TO CPU DEBUG OUT

[PAGE_TITLE=DEBUG

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

XDK BOARD MAPPING

CPU_DBG_TERM<0..69>

MAPPING,

57

OUT

IN

CPU_DBGSEL_XDK<0..69> N:CONNECT TO CPU DEBUG OUT

1 1 1

FTP FTP FTP

1 1 1

52 53 54

56 57 58 59 60 61 62 63

WN DEBUG VS WN XDK]

DRAWING XENON_FABK Wed Aug 24 09:27:21

FT6U11 FT6U9 FT6U10

DBG_WN_POST_OUT0 DBG_WN_POST_OUT1 DBG_WN_POST_OUT2 DBG_WN_POST_OUT3 DBG_WN_POST_OUT4 DBG_WN_POST_OUT5 DBG_WN_POST_OUT6 DBG_WN_POST_OUT7

2005

MICROSOFT CONFIDENTIAL

1 1 1 1 1 1 1 1

DB6E1 DB6E2 DB6E3

FTP FTP FTP FTP FTP FTP FTP FTP

FT6U8 FT6U2 FT6U3 FT6U4 FT6U5 FT6U6 FT6U7 FT6U1

PROJECT NAME XENON_RETAIL

PAGE 31/73

REV K7

POWER TRACE DECOUPLING V_12P0

V_12P0

1

C7G2

0.01UF

2

10%

16V X7R 402

1

C4N27

2

0.01UF

10% 16V X7R 402

1

C9F2

0.01UF

2

10%

16V X7R 402

1

C9E2

0.01UF

V_5P0STBY

1

C3N2

1

C1N12

1

C1C7

2

2

0.01UF

10% 16V X7R 402

1

C1C15

0.01UF

2

10%

16V X7R 402

1

C7N1

0.01UF

2

10%

16V X7R 402

1

C6N1

2

0.01UF

10% 16V X7R 402

1

C5N1

2

.1UF 10% 6.3V X5R 402

10%

C9C7

2

.1UF 10% 6.3V X5R 402

16V X7R 402

1

2

.1UF 10% 6.3V X5R 402

V_5P0

1

C7B1

2

.1UF 10% 6.3V X5R 402

1

C6B1

2

.1UF 10% 6.3V X5R 402

1

C4B8

2

.1UF 10% 6.3V X5R 402

1

C1D8

V_3P3STBY

1

C5V1

2

.1UF 10% 6.3V X5R 402

1

C3U3

2

.1UF 10% 6.3V X5R 402

1

C2T4

2

.1UF 10% 6.3V X5R 402

2

C1B2

C1C1

2

C1D10

C1B3

1

C2G1

2

1

C3G3

2

.1UF 10% 6.3V X5R 402

1

2

C5G3

2

C1C12

1

C1C8

2

.1UF 10% 6.3V X5R 402

1

C8G2

2

.1UF 10% 6.3V X5R 402

1

C1F1

2

.1UF 10% 6.3V X5R 402

1

C5G5

2

.1UF 10% 6.3V X5R 402

54

1

C9N1

IN

V_VREG_V1P8V5P0

2

1

1

C5N2

1

2

C3N1

2

C5G1

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

C4F13

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

2

.1UF 10% 6.3V X5R 402

1

C7N2

2

.1UF 10% 6.3V X5R 402

2

1

C1N13

2

.1UF 10% 6.3V X5R 402

2

1

C1G1

2

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

2

V_1P8

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

C2F2

.1UF 10% 6.3V X5R 402

1

.1UF 10% 6.3V X5R 402

1

1

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

1

V_5P0DUAL

2

1

.1UF 10% 6.3V X5R 402

C1F2

2

.1UF 10% 6.3V X5R 402

2

0.01UF

10% 16V X7R 402

1

C4N1

2

0.01UF

10% 16V X7R 402

[PAGE_TITLE=POWER

TRACE

EMI

CAPS]

DRAWING XENON_FABK Wed Aug 24 09:27:22

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 32/73

REV K7

ADB:ADD

SB,

CONFIG TABLE

PCIEX

+ SMM GPIO + JTAG] 1 of

U2C1

SB VERSION

R2P9

2 1K 402

V_3P3

1

46 46

5% EMPTY

46

IN IN IN

DB1N5

R2P5

2

V_1P8 R2P16

2 1K 402

1K 402

1

5% EMPTY

1

TP

1

5% EMPTY

DB2P15

R2P2

1K 402

13 13 13 13

1

5% EMPTY

K1 J1

SATA_CLK_REF

H3

SATA_CLK_REF

SATA_CLK_SEL

H4

SATA_CLK_SEL

ECB_CLK_BYP ECB_CLK_SEL

A6 B6

ECB_CLK_BYP ECB_CLK_SEL

TP

U20 V20

HBEDB_CLK_BYP HBEDB_CLK_SEL

TP

1

XUSB_CLK_BYP XUSB_CLK_SEL

B15 C15

XUSB_CLK_BYP XUSB_CLK_SEL

PCIEX_CLK_DP IN PCIEX_CLK_DN IN PEX_GPU_SB_L1_DP PEX_GPU_SB_L1_DN

IN IN

PEX_GPU_SB_L0_DP PEX_GPU_SB_L0_DN

IN IN

PEX_RBIAS1 PEX_RBIAS0

1 2

1

R2P11

C2P25

.1UF 10% 6.3V X5R 402

1

124 1% CH 402

2

56

1

2

IN

KER_DBG_RXD

L22 L21

PEX_CLK_DP PEX_CLK_DN

P22 N22

PEX_RX1_DP PEX_RX1_DN

T21 R21

PEX_RX0_DP PEX_RX0_DN

K20 K19

PEX_RBIAS1 PEX_RBIAS0

D15

UART0_RXD

R2P8

C2P18 .1UF 10% 6.3V X5R 402

2

2

1

1

1

1

1

1

R1P2

R1P3

R1P5

R1P1

R2N6

R2N4

R2N5

10K 5% CH 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

2

0

1

2

1

R1P6

2

1

1

2

2

1

2

3

1

2

5

1

2

2

14

11

1

1

15

SB_GPIO<0..15>

R1C4

R1C5

R1C6

R1C2

R2B10

R2B8

R2B9

1K 5% EMPTY 402

1K 5% CH 402

1K 5% CH 402

1K 5% CH 402

1K 5% CH 402

1K 5% CH 402

1K 5% CH 402

1K 5% CH 402

2

2

2

2

2

33

1

R1C7

2

BI

2

SB_TCLK SB_TDO SB_TDI SB_TMS SB_TRST

W20 V22 V21 W22 W21

C2C2

1

TCK TDO TDI TMS TRST

PEX_SB_GPU_L1_DP

2

OUT

13

OUT

13

OUT

13

OUT

13

.1UF 10% 6.3V X5R 402 C2C1

PEX_SB_GPU_L1_DN

2

.1UF 10% 6.3V X5R 402 C2C4

1

PEX_SB_GPU_L0_DP

2

.1UF 10% 6.3V X5R 402 PEX_TX1_DP PEX_TX1_DN

N20 M20

PEX_SB_GPU_L1_DP_C

R19 P19

PEX_SB_GPU_L0_DP_C

UART0_TXD

D14

KER_DBG_TXD_R

PEX_SB_GPU_L0_DN

2

.1UF 10% 6.3V X5R 402

PEX_SB_GPU_L0_DN_C

R2N8

2

D10 D11 D12 D13 C8 D9 C9 B9 A9 C10 B10 A10 C11 B11 A11 C12 B12 A12 C13 B13 A13 C14 B14 A14 E3 F1 F2 F3 G1 G2 G3 G4

C2C3

1

PEX_SB_GPU_L1_DN_C

PEX_TX0_DP PEX_TX0_DN

GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

499 1% CH 402

V_3P3

1

EMPTY 106

1

HBEDB_CLK_BYP HBEDB_CLK_SEL

46 46

6

SATA_CLK_DP SATA_CLK_DN

1

DB2N8

2

SATA_CLK_DP SATA_CLK_DN

47 402

SB_GPIO_RESERVED31 SB_GPIO_RESERVED30 SB_GPIO_RESERVED29 SB_GPIO_RESERVED28 SB_GPIO_RESERVED27 SB_GPIO_RESERVED26 SB_GPIO_RESERVED25 SB_GPIO_RESERVED24 SB_GPIO_RESERVED23 SB_GPIO_RESERVED22 SB_GPIO_RESERVED21 SB_GPIO_RESERVED20 SB_GPIO_RESERVED19 SB_GPIO_RESERVED18 SB_GPIO_RESERVED17 SB_GPIO_RESERVED16 SCART_RGB AUD_RST_N

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

KER_DBG_TXD

OUT

56

DB2P1 DB2P2 DB2P3 DB2P4 DB2P5 DB2P6 DB2P7 DB2N6 DB2N5 DB2N4 DB2N3 DB2N11 DB2N12 DB2N10 DB2N9 DB2N7

15 14

SB_GPIO<0..15>

BI

33

43 40

OUT OUT

11

ANA_VID_INT IN WSS_CNTL0 OUT WSS_CNTL1 OUT PCIEX_INT SB_GPIO_RESERVED6

29 43 43

DB1P1 TP

DB1P2

1

TP

1 5

ENET_RST_N

OUT

1 SATA_CLK

1

5% CH

V_3P3

FTP

19

39

3 2 1 0

FT1N1

STITCH

V_3P3

J2D1 2X3HDR 1 3 5

X02047-012 2 4 6

2 1

EMPTY

[PAGE_TITLE=SB,

PCIEX

+ SMM GPIO + JTAG]

C1C2 .1UF 10% 6.3V X5R 402

2 1

C2B16

.1UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:23

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 33/73

REV K7

SB,

SMC V_12P0

46 56

46

28

STBY_CLK SMC_RST_N

IN

IN

2

R8N17 1

47

2

TRAY_OPEN

OUT

R2N15

33 402

C2P51

1

5% CH

1

1UF 10% 50V X7R 603

2

VREG_GPU_PWRGD 2 of

U2C1 56

43

IN

R2M1

2

EXT_PWR_ON_N

10K 402

1

SB VERSION

5% CH

V_3P3STBY 35 35

DDC_DATA_OUT DDC_CLK_OUT

BI BI

V_3P3STBY

1

FT2P24 FT2P15 46 46

56 28

28 56

BI BI

1 1

FTP FTP

2

IN

34

IN

56

1

R2P6

R2P4

2.2K 5% CH 402

2.2K 5% CH 402

2

1

SMC_RST_N*

G20

SB_RST_N*

SB_MAIN_PWRGD

G19

MAIN_PWR_OK

TRAY_OPEN_R

47 40

TRAY_STATUS

IN

EXT_PWR_ON_R

AUD_CLAMP

OUT

SMB_DATA SMB_CLK AV_MODE2_R

43

IN

AV_MODE2

R2M3

2

43

IN

43

IN

AV_MODE0

2

2

56

13 56 56

35

IN BI BI BI

1

5% CH

R2A2

10K 402

DDC_CLK

5% CH

R2M5

10K 402

43

AV_MODE1_R AV_MODE0_R

10K 402

AV_MODE1

1

SMC_UART1_RXD

C16

SMC_DBG

DBG_LED3 DBG_LED2 DBG_LED1

42

2

2

R2B16

R2B19

R2B18

2K 1% EMPTY 402

2K 1% EMPTY 402

2K 1% EMPTY 402

1

IN

1

TP DB2P8 TP DB2P9

1 1

6

SMC_DBG_TXD

106

SMC_UART1_TXD

B16

SMC_DBG_TXD_R

1 47 402

E22 E21 E20 E19 F22 F21 F20 F19

PWRSW_N VREG_3P3_EN_N ANA_V12P0_PWRGD

B20 B21 C20 C22 C21 D22 D21 D20

SMC_P3_GPIO7 SMC_P3_GPIO6 SMC_P3_GPIO5 SMC_P3_GPIO4 SMC_P3_GPIO3 SMC_P3_GPIO2 SMC_P3_GPIO1 SMC_P3_GPIO0

SMC_P1_GPIO7 SMC_P1_GPIO6 SMC_P1_GPIO5 SMC_P1_GPIO4 SMC_P1_GPIO3 SMC_P1_GPIO2 SMC_P1_GPIO1 SMC_P1_GPIO0

Y21 Y22 AA20 AA21 AB20 Y20 AA19 AB19

VREG_CPU_EN

SMC_P0_GPIO7 SMC_P0_GPIO6 SMC_P0_GPIO5 SMC_P0_GPIO4 SMC_P0_GPIO3 SMC_P0_GPIO2 SMC_P0_GPIO1 SMC_P0_GPIO0

J20 H21 H19 H20 J19 J22 J21 H22

GPU_RST_DONE_R

A17 B17

SMC_PWM1 SMC_PWM0

SMC_IR_IN

EN_TEST1_N EN_TEST0_N

G22 G21

ENTEST1_N* ENTEST0_N*

SMC_PWM1 SMC_PWM0

ANA_RST_N VREG_GPU_EN_N PSU_V12P0_EN ANA_CLK_OE

VREG_V5P0_EN_N VREG_V5P0_SEL VREG_V1P8_EN_N BINDSW_N TILTSW_N EJECTSW_N CPU_RST_N SB_MAIN_PWRGD_R SB_RST_N GPU_RST_N CPU_PWRGD

R7V4

1

R2N9

SMC_P2_GPIO7 SMC_P2_GPIO6 SMC_P2_GPIO5 SMC_P2_GPIO4 SMC_P2_GPIO3 SMC_P2_GPIO2 SMC_P2_GPIO1 SMC_P2_GPIO0

A16

1% CH

1.82K 402

N: TIED TO V_MEMPORT FOR BETTER ROUTING

SMC_P4_GPIO7 SMC_P4_GPIO6 SMC_P4_GPIO5 SMC_P4_GPIO4 SMC_P4_GPIO3 SMC_P4_GPIO2 SMC_P4_GPIO1 SMC_P4_GPIO0

IR_DATA

56

OUT

2

10K 402

5% CH

V_5P0

2

5% CH

VREG_CPU_PWRGD

28

OUT OUT OUT OUT

28 52 48 28

OUT

50

OUT OUT OUT IN IN IN

54 46 54 42 42 42

OUT

4

OUT

34

50

IN

48 55

OUT OUT IN

52

IN

R8N18 2

1

EMPTY

A18 B18 C18 D18 A19 B19 C19 A20

5% CH

1

BI

D16

1

2

56

STBY_CLK

C17

FTP

SMC_DBG_EN

IN

Y12

SB_RST_N

FT2P10

34

4.7K 5% CH 402

48

R3P7

2 1K 402

46

1

5% CH

GPU_RST_DONE

IN

13

2

R3P6

1

10K 5% CH 402

47

1 2

R2P15

1K 402

1

FTP

SB_MAIN_PWRGD

FT2P5 34

OUT

5% CH

2

OUT OUT

13 4

OUT OUT

29 29

R2P10 10K 5% CH 402

1

X02047-012

V_1P8STBY

DBG_LED0 FT3P3 FT2R1 FT2P25 FT1U2

FTP FTP FTP FTP

1 1 1 1

N: DBG_LED0 STUFFED = ICS CLOCK DBG_LED0 EMPTY = ANA CLOCK

1

1

R2P12

2

10K 5% CH 402

R2P13

2

10K 5% CH 402

ARGON_DATA ARGON_CLK

[PAGE_TITLE=SB,

SMC]

DRAWING XENON_FABK Wed Aug 24 09:27:24

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

BI BI

48 48

PAGE 34/73

REV K7

FLSH_DATA<7..0>

BI

7 6 5 4 3 2 1 0

FLSH_WP_N

OUT V_3P3STBY 2

41

IN

2.2K 402

FLSH_READY

FT2P22 FT2P23 FT2P20 FT2P21

FTP FTP FTP FTP 45 45 45 45

BI BI BI BI

R1P7

1

5% CH

SPI_CLK SPI_MOSI SPI_SS_N*

Y2 AA2 Y3 AA3 AB3 Y4 AA4 AB4

FLSH_DATA7 FLSH_DATA6 FLSH_DATA5 FLSH_DATA4 FLSH_DATA3 FLSH_DATA2 FLSH_DATA1 FLSH_DATA0

Y1 V1

1 1

USBPORTA3_DP USBPORTA3_DN

1 1

USBPORTA2_DP USBPORTA2_DN GAMEPORT2_DP GAMEPORT2_DN

W18 Y18 AA17 AB17 W16 Y16

GAMEPORT1_DP GAMEPORT1_DN

AA15 AB15 W12

3 of SB VERSION

U3 Y5 AA5

6

EMPTY 106

AB5

SPI_MISO

SPI_MISO_R

R1R1

2 33 402

W1

FLSH_CLE

FLSH_CE_N*

V3

FLSH_CE_N

FLSH_RE_N*

V2

FLSH_RE_N

FLSH_WE_N*

W3

FLSH_WE_N

FLSH_ALE

W2

FLSH_ALE

Y10 W10

USBPORTB4_DP USBPORTB4_DN

FLSH_CLE

FLSH_WP_N* FLSH_READY

USBA_D3_DP USBA_D3_DN

USBB_D4_DP USBB_D4_DN

USBA_D2_DP USBA_D2_DN

USBB_D3_DP USBB_D3_DN

Y8 W8

MEMPORT1_DP MEMPORT1_DN

USBA_D1_DP USBA_D1_DN

USBB_D2_DP USBB_D2_DN

AB7 AA7

EXPPORT_DP EXPPORT_DN

USBA_D0_DP USBA_D0_DN

USBB_D1_DP USBB_D1_DN

AB9 AA9

USB_RBIAS

USBB_D0_DP USBB_D0_DN

AB11 AA11

1 1

1

SPI_MISO

56

OUT

5% CH

OUT

41

OUT

41

OUT

41

OUT

41

OUT

41

FTP FTP

FT2P8 FT2P9

BI BI

45 45

BI BI

44 44

MEMPORT2_DP MEMPORT2_DN

BI BI

45 45

ARGONPORT_DP ARGONPORT_DN

BI BI

48 48

V_5P0STBY

X02047-012

SB_USB_RBIAS

1

2

R2N10

2

DDC_DATA_OUT

49.9 402

R2P14

C2P40 .1UF 10% 6.3V EMPTY 402

BI

113 1% CH 402

2

FB2N1

1

1

DDC_DATA_OUT_R

1% CH

1

62PF 5% 50V NPO 402

2

DDC_DATA

2

1K 0.2A 0.7DCR

C2N2

2

2.2K 5% CH 402

FB 603

V_5P0STBY

2

R3N1

0 402

1

5% EMPTY

DDC_CLK

2 2.2K 402

1

DDC_CLK_OUT_R

5% CH

2 2.2K 402

1 2

R3N3

1

Q2N2

1

MMBT2222 XSTR

5% CH

2

2

C3N4 470PF 5% 50V X7R 402

R2N11

DDC_CLK_OUT_E

1

[PAGE_TITLE=SB,

FLASH

+ USB + SPI]

3

R2N12

2

DDC_CLK_OUT

D2M3

BI

43

BI

43

34

DDC_CLK_OUT_B

3 34

BI

1

2

2

34

1

R2M8

2.2K 5% CH 402

3

1

1

R2M7

BAV99 SOT23S DIO

41 41

SPI_CLK SPI_MOSI SPI_SS_N

IN IN IN

BAV99 SOT23S DIO

U2C1 56 56 56

+ USB + SPI

1

FLASH

D2M2

SB,

49.9 1% CH 402

DRAWING XENON_FABK Wed Aug 24 09:27:24

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 35/73

REV K7

SB,

39

19

IN

R1B9

MII_TX_CLK 33 402

ETHERNET + AUDIO + SATA

MII_TX_CLK_R

5% CH

R1C3

MII_MDC_CLK_OUT_R

U2C1 39

19

IN

R1B10

MII_RX_CLK

MII_TX_CLK MII_RX_CLK

19 19 19 19

IN IN IN IN

MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0

D1 D2 D3 C1

MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0

39 39

19 19

IN IN

MII_RXDV MII_RXER

C2 B2

MII_RXDV MII_RXER

19 19

IN IN BI

MII_COL MII_CRS MII_MDIO

B5 A5 E1

MII_COL MII_CRS MII_MDIO

19

28

AUD_CLK

IN

47 47

IN IN

47 47

IN IN

6

EMPTY

33 402

106 MII_MDC_CLK_OUT

A8

1 2

AUD_CLK

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

C5 A4 B4 C4

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

MII_TXEN

A3

MII_TXEN

OUT OUT OUT OUT

19 19 19 19

C7 B8 A7 B7 C6

OUT

19

I2S_SD_R

R2B12

I2S_WS_R SPDIF_R

47 402

SATA1_TX_DP SATA1_TX_DN

R2 P2

HDD_TX_DP HDD_TX_DN

ODD_RX_DP ODD_RX_DN

L3 M3

SATA0_RX_DP SATA0_RX_DN

SATA0_TX_DP SATA0_TX_DN

N1 M1

ODD_TX_DP ODD_TX_DN

U2

SATA_RBIAS

R1C8

2

47 402

I2S_MCLK

5% CH

I2S_BCLK

R2B13

I2S_SD

I2S_BCLK_R

SATA1_RX_DP SATA1_RX_DN

1

39

39

5% CH

47 402

I2S_MCLK_R

N4 P4

.1UF 10% 6.3V X5R 402

19

39 39 39 39

R2B11

I2S_MCLK_OUT I2S_BCLK_OUT I2S_SD I2S_WS SPDIF

OUT

E2

HDD_RX_DP HDD_RX_DN

C1C9

MII_MDC_CLK_OUT

5% CH

R2B14

SATA_RBIAS

[PAGE_TITLE=SB,

B3 C3

39 39 39 39

39 39

4 of SB VERSION

5% CH

33 402

39

MII_RX_CLK_R

5% CH

47 402

1 47 402

OUT OUT

47 47

OUT OUT

47 47

5% CH

R2A10

I2S_WS 2

SPDIF

OUT

40

OUT

40

OUT

40

OUT

40

OUT

43

5% CH

X02047-012

374 1% CH 402

ETHERNET + AUDIO + SATA]

DRAWING XENON_FABK Wed Aug 24 09:27:25

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 36/73

REV K7

SB,

STANDBY POWER + DECOUPLING 5 of

U2C1

SB VERSION

V_1P8STBY

FB2P4 1 120 0.2A DCR

0.5

C2R5

10UF 10% 6.3V X5R 1206

2

V_AVDD_USB

FB 603

V_AVSS_USB

1

C2P47

2.2UF 10% 6.3V X5R 603

2 1

ST2P3

2

1 2

C2P43

V_CMPAVDD18_USB

.1UF 10% 6.3V X5R 402

V_CMPAVSS18_USB V_VDD18_USB

SHORT

FB2P3 1

0.5

2

120 0.2A DCR

FB 603

1 2

ST2P2

1

2

1

C2P46

2.2UF 10% 6.3V X5R 603

2

C2P42

.1UF 10% 6.3V X5R 402

V_CMPAVSS33_USB V_VDD33_USB

SHORT

AB13 AA13

AVDD_USB AVSS_USB

Y13 W13

CMPAVDD18_USB CMPAVSS18_USB

V13 V12 V11 V10 V9 V8 V7 Y6 W6 V6

VDD18_USB<9> VDD18_USB<8> VDD18_USB<7> VDD18_USB<6> VDD18_USB<5> VDD18_USB<4> VDD18_USB<3> VDD18_USB<2> VDD18_USB<1> VDD18_USB<0>

Y14 W14

CMPAVDD33_USB CMPAVSS33_USB

V17 V16 V15 V14

VDD33_USB<3> VDD33_USB<2> VDD33_USB<1> VDD33_USB<0>

FB2R1 1

1 2

C2R3

2

120 0.5A 0.2DCR

FB 603

1

10UF 10% 6.3V X5R 1206

C2P45 10UF 20% 6.3V X5R 805

2

1 2

C2P41 .1UF 10% 6.3V X5R 402

1 2

C2P2 .1UF 10% 6.3V X5R 402

1 2

C2P3 .1UF 10% 6.3V X5R 402

V_3P3STBY 37

FB2P5 1

C2R6

FB 603

1 2

1

V_1P8STBY

EMPTY 106 VDD18_AUX<9> VDD18_AUX<8> VDD18_AUX<7> VDD18_AUX<6> VDD18_AUX<5> VDD18_AUX<4> VDD18_AUX<3> VDD18_AUX<2> VDD18_AUX<1> VDD18_AUX<0>

J18 H18 G18 J15 H15 R14 H14 R12 P12 R9

VDD33_AUX<14> VDD33_AUX<13> VDD33_AUX<12> VDD33_AUX<11> VDD33_AUX<10> VDD33_AUX<9> VDD33_AUX<8> VDD33_AUX<7> VDD33_AUX<6> VDD33_AUX<5> VDD33_AUX<4> VDD33_AUX<3> VDD33_AUX<2> VDD33_AUX<1> VDD33_AUX<0>

V19 D19 V18 F18 E18 E17 D17 E16 E15 W5 V5 U5 W4 V4 U4

VSS_USB<25> VSS_USB<24> VSS_USB<23> VSS_USB<22> VSS_USB<21> VSS_USB<20> VSS_USB<19> VSS_USB<18> VSS_USB<17> VSS_USB<16> VSS_USB<15> VSS_USB<14> VSS_USB<13> VSS_USB<12> VSS_USB<11> VSS_USB<10> VSS_USB<9> VSS_USB<8> VSS_USB<7> VSS_USB<6> VSS_USB<5> VSS_USB<4> VSS_USB<3> VSS_USB<2> VSS_USB<1> VSS_USB<0>

SB BALLS V18 AND V19 ARE IN THE LOWER RIGHT HAND OF THE CHIP THEY HAVE BEEN ISOLATED FOR BETTER POWER ROUTING V_CMPAVDD33_USB

37

IN

V_3P3STBY

Y19 W19 AB18 AA18 Y17 W17 AB16 AA16 Y15 W15 AB14 AA14 AB12 AA12 Y11 W11 AB10 AA10 Y9 W9 AB8 AA8 Y7 W7 AB6 AA6

V_1P8STBY

1 2

C2P38 .1UF 10% 6.3V X5R 402

C2P37

.1UF 10% 6.3V X5R 402

X02047-012

C2P23

.1UF 10% 6.3V X5R 402

C2P24

.1UF 10% 6.3V X5R 402

V_3P3STBY

2

120 0.2A DCR

0.5

10UF 10% 6.3V X5R 1206

V_CMPAVDD33_USB

OUT

6

ST2P4

2

C2P48 2.2UF 10% 6.3V X5R 603

1 2

C2P44 .1UF 10% 6.3V X5R 402

1 2

C2P6

C2N1

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

C2P5

.1UF 10% 6.3V X5R 402

SHORT

FB2P1 1

C2P8

0.5

120 0.2A DCR

10UF 10% 6.3V X5R 1206

[PAGE_TITLE=SB,

2 FB 603

1 2

C2P34 2.2UF 10% 6.3V X5R 603

1 2

C2P35 .1UF 10% 6.3V X5R 402

STANDBY POWER + DECOUPLING]

DRAWING XENON_FABK Wed Aug 24 09:27:26

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 37/73

REV K7

V_1P8 6 of

U2C1

SB VERSION

V_SBPCIE FB2P2 1

1 2

C2P19

0.5

2

V_AVSS_PEX

FB 603

120 0.2A DCR

10UF 10% 6.3V X5R 1206

V_AVDD_PEX

1 2

ST2P1

1

1

C2P27

2.2UF 10% 6.3V X5R 603

2

2

C2P26

V_VDD_PEX_FB

0.01UF 10% 16V X7R 402

SHORT

R2P17 0 603

5% CH

1

1

C2P10

4.7UF 10% 6.3V X5R 805

2

2

1

C2P32 .1UF 10% 6.3V X5R 402

2

C2P31 0.01UF 10% 16V X7R 402

V_1P8 FB1P2 1

1 2

C1P2 10UF 10% 6.3V X5R 1206

1 2

C1P7

0.5

10UF 10% 6.3V X5R 1206

2

120 0.2A DCR

V_AVDD1_SATA

FB 603

V_AVSS1_SATA

1

C1P5 2.2UF 10% 6.3V X5R 603

2 ST1P2

1

1

2

C1P6

V_AVDD0_SATA

.1UF 10% 6.3V X5R 402

2

V_AVSS0_SATA V_CMPAVDD_SATA V_CMPAVSS_SATA V_VDD_SATA

SHORT

FB1P1 1 0.5

2

120 0.2A DCR

FB 603

1 2

ST1P1

1

2

1

C1P3 2.2UF 10% 6.3V X5R 603

2

C1P4

.1UF 10% 6.3V X5R 402

SHORT

FB1P4 1

0.5

2

120 0.2A DCR

FB 603

1 2

ST1P3

1

2

1

C1P10 2.2UF 10% 6.3V X5R 603

2

C1P11 .1UF 10% 6.3V X5R 402

L19 L20

AVDD_PEX AVSS_PEX

T18 R18 P18 N18 M18

VDD_PEX<4> VDD_PEX<3> VDD_PEX<2> VDD_PEX<1> VDD_PEX<0>

U22 T22 R22 M22 K22 U21 P21 N21 M21 K21 T20 R20 P20 T19 N19 M19

VSS_PEX<15> VSS_PEX<14> VSS_PEX<13> VSS_PEX<12> VSS_PEX<11> VSS_PEX<10> VSS_PEX<9> VSS_PEX<8> VSS_PEX<7> VSS_PEX<6> VSS_PEX<5> VSS_PEX<4> VSS_PEX<3> VSS_PEX<2> VSS_PEX<1> VSS_PEX<0>

J3 J2

AVDD1_SATA AVSS1_SATA

H1 H2

AVDD0_SATA AVSS0_SATA

U1 T1

CMPAVDD_SATA CMPAVSS_SATA

T5 R5 P5 N5 M5 L5

VDD_SATA<5> VDD_SATA<4> VDD_SATA<3> VDD_SATA<2> VDD_SATA<1> VDD_SATA<0>

T4 R4 M4 L4 K4 J4 T3 R3 P3 N3 K3 T2 N2 M2 L2 K2 R1 P1 L1

VSS_SATA<18> VSS_SATA<17> VSS_SATA<16> VSS_SATA<15> VSS_SATA<14> VSS_SATA<13> VSS_SATA<12> VSS_SATA<11> VSS_SATA<10> VSS_SATA<9> VSS_SATA<8> VSS_SATA<7> VSS_SATA<6> VSS_SATA<5> VSS_SATA<4> VSS_SATA<3> VSS_SATA<2> VSS_SATA<1> VSS_SATA<0>

SHORT

FB1P3 1 120 0.5A 0.2DCR

2 FB 603

1 2

[PAGE_TITLE=SB,

C1P8 10UF 20% 6.3V X5R 805

MAIN

1 2

C2P52

.1UF 10% 6.3V X5R 402

1 2

6

EMPTY 106 VDD18<17> VDD18<16> VDD18<15> VDD18<14> VDD18<13> VDD18<12> VDD18<11> VDD18<10> VDD18<9> VDD18<8> VDD18<7> VDD18<6> VDD18<5> VDD18<4> VDD18<3> VDD18<2> VDD18<1> VDD18<0>

U19 U18 R15 P15 M15 M14 J12 H12 R11 J11 H11 M9 H9 R8 P8 M8 J8 H8

VDD33<13> VDD33<12> VDD33<11> VDD33<10> VDD33<9> VDD33<8> VDD33<7> VDD33<6> VDD33<5> VDD33<4> VDD33<3> VDD33<2> VDD33<1> VDD33<0>

E14 E13 E12 E11 E10 E9 D8 D7 D6 G5 D5 F4 E4 D4

VSS<41> VSS<40> VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

N15 L15 K15 P14 N14 L14 K14 J14 R13 P13 N13 M13 L13 K13 J13 H13 N12 M12 L12 K12 P11 N11 M11 L11 K11 R10 P10 N10 M10 L10 K10 J10 H10 P9 N9 L9 K9 J9 N8 L8 K8 A15

V_1P8

1 2

C2P22

.1UF 10% 6.3V X5R 402

1 2

C2P21 .1UF 10% 6.3V X5R 402

1

C2P16 .1UF 10% 6.3V X5R 402

2

1

1

C2P28 .1UF 10% 6.3V X5R 402

2

1

C2P30

.1UF 10% 6.3V X5R 402

2

1

C2P17 .1UF 10% 6.3V X5R 402

2

2

C2P15 .1UF 10% 6.3V X5R 402

1 2

C2P33

.1UF 10% 6.3V X5R 402

1 2

C2P29

.1UF 10% 6.3V X5R 402

V_3P3 V_1P8

1 2

1

C2P39 1UF 10% 50V X7R 603

1

C2P20 1UF 10% 50V X7R 603

2

C1D2

10UF 10% 6.3V X5R 1206

2

V_3P3

1 2

C2P13 .1UF 10% 6.3V X5R 402

1 2

1

C2P12 .1UF 10% 6.3V X5R 402

2

C2P14 .1UF 10% 6.3V X5R 402

1 2

C2P11 .1UF 10% 6.3V X5R 402

1 2

C2P9

.1UF 10% 6.3V X5R 402

V_3P3

1 2

C2P4 1UF 10% 50V X7R 603

1 2

C2P1

10UF 10% 6.3V X5R 1206

C1P1

.1UF 10% 6.3V X5R 402

X02047-012

POWER + DECOUPLING]

DRAWING XENON_FABK Wed Aug 24 09:27:27

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 38/73

REV K7

N: N:

123.8 OHM TERMINATION REQUIRED FOR ICS 100 OHM TERMINATION REQUIRED FOR BROADCOM ENET_RX_DP

19

BI

44

1 44

19

39

R1A4

V_ENET

IN

1

ENET_CLK

IN

2 IC ICS1893BF

1

ENET_RST_N 2

R1C1 10K 5% CH 402

1

44

19

36

19

39

MII_MDC_CLK_OUT

IN

2

V_ENET

IN

1.5K 402 36

19

ENET_REF_CLK_OUT

R1B11

1

1% CH

MII_RX_CLK MII_RXDV MII_RXER

34 32 35

RXCLK RXDV RXER

36 36 36 36

19 19 19 19

OUT OUT OUT OUT

MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0

28 29 30 31

RXD<3> RXD<2> RXD<1> RXD<0>

MII_TX_CLK MII_TXEN

37 38

TXCLK TXEN

MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0

42 41 40 39

TXD<3> TXD<2> TXD<1> TXD<0>

27 26

MDC MDIO

43 44

COL CRS

10

AMDIX_EN

19 36

OUT IN

19 19 19 19

36 36 36 36

IN IN IN IN

19 19

MII_COL MII_CRS

OUT OUT

ENET_AMDIX_EN

R1N4

100 402 19

39

IN

2

V_ENET

R1N1

9.53K 402

RESET_N*

OUT OUT OUT

2

44

23 19 19 19

36 19

36 36

REF_IN REF_OUT

36 36 36

MII_MDIO

BI

47 46

1

20 19

5% EMPTY

1

ENET_100BIAS

48 45 33 14 7 24 22 18

10K 5% CH 402

330 1% EMPTY 402

TP_AP TP_AN

12 13

TP_BP TP_BN

16 15

2

10/100

9 36 25 21 17 11 5 2

1

R1N2

R1N3

1.58K 1% CH 402

2K 1% CH 402

1

44

44

OUT

1

BI

19

44

ENET_TX_DP

BI

19

44

1

2

R1N6 1

2

10K 5% CH 402

2

10K 5% CH 402

2 10K 5% CH 402

ENET_TX_DP_R

1

R1M2 ENET_LINK_N

1

2

61.9 1% CH 402

R1B4

OUT

19

44

1

R1N5

R1B5

2

10K 5% CH 402

1K 5% CH 402

1

2

ENET_10_100_OUT

0 5% CH 603 ENET_TX_DN_R

R1A2

EMPTY FOR BROADCOM STUFF FOR ICS

AMDIX_EN HAS INTERNAL PULLUP AUTO MDIX IS ON BY DEFAULT

ETHERNET

ENET_RX_DN

R1A1 ENET_P2LI_R

DB1N3

10/100 PIN INDICATION

61.9 1% CH 402

1

R1N7

1

ENET_RX_DN_R

1

2

X800188-002

2

19

OUT

8 6 4 3 1

VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

2

0 5% CH 603

R1A3

TP

2

2 ENET_ACT_N

100TCSR 10TCSR

ENET_10BIAS

1% CH

VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>

P4RD P3TD P2LI P1CL P0AC

R1B6

STUFF FOR BROADCOM EMPTY FOR ICS R1B13

1

ENET_P1CL

TP

IN

R1M1 44

OUT

1

DB1N4

33

ENET_RX_DP_R

ENET_POAC_R U1B2

19

1

ENET_P4RD

46

2

ENET_P3TD

19

R1B7 1K 5% CH 402

61.9 1% CH 402

2

IS FOR OUTPUT OF CONNECTION SPEED

61.9 1% CH 402

ENET_TX_DN

BI

19

44

ADDRESS="00001"

V_3P3 FB1B1 1 60 0.5A

2 0.1DCR 603

1 C1A5

100UF 20% 16V

2 ELEC RDL

[PAGE_TITLE=SB

OUT,

ETHERNET]

V_ENET

2 1

C1B1 10UF 20% 6.3V X5R 805

C1N1 .1UF 10% 6.3V X5R 402

C1N4 .1UF 10% 6.3V X5R 402

C1N5

.1UF 10% 6.3V X5R 402

C1N3

.1UF 10% 6.3V X5R 402

C1N9

.1UF 10% 6.3V X5R 402

C1N11

.1UF 10% 6.3V X5R 402

C1N2

.1UF 10% 6.3V X5R 402

OUT

19

39

44

C1N10

.1UF 10% 6.3V X5R 402

DRAWING XENON_FABK Wed Aug 24 09:27:28

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 39/73

REV K7

V_12P0 2

1

V_3P3 R2B1

1

1 R2B6

0 603

0 603

FT2N1

2

4.7UF 10% 16V X5R 1206

AUD_VDD

1 2

C2B11 4.7UF 10% 6.3V X5R 805

1

2

2

1K 402

AUD_AC_R

1

FB2A2 1

AUD_CLAMP_R

2 0.7DCR 603

1K 0.2A

5% CH

2

C2B7

0.1UF 10% 25V X7R 603

1

R2B3

10UF 20% 16V X5R 1206

AUD_VAA

5% CH

C2A7

2

5% CH

C2B10

FT2M1

R2B5

C2B5

.1UF 10% 6.3V X5R 402

EG2B2

1

1

FTP

FTP

PGB0010603

1

10K 5% CH 402

2

C2B3 470PF 5% 50V X7R 402

X801161-001

603 U2B1

1

EMPTY

IC

2

XDAC

IN

FTP

1

IN IN IN IN

I2S_MCLK I2S_BCLK I2S_SD I2S_WS

AUD_RST_N AUD_DCAP

1

2

1K 5% CH 402

C2B1

10UF 10% 6.3V X5R 1206

C2B6

.1UF 10% 6.3V X5R 402

DVDD

13 4 3 2

MCLK BCLK SD WS

5 12 11

NC PDN DVREF

1

AUDIO AVDD

AUD_R_OUT

9

VOUTR VOUTL

6 10

AVREF

8

AGND

7

AUD_L_OUT

C2B4

.1UF 10% 6.3V X5R 402

X02238-002

C2B8

10UF 10% 6.3V X5R 1206

EG2B1

PGB0010603

10K 5% CH 402

2

C2B2 470PF 5% 50V X7R 402

1

1

C2B9

2

AUD_AC_L

10UF 20% 16V X5R 1206

2 1K 402

1

R2B2

1

FB2A1

2

3

AUD_CLAMP_C

Q2N1 1

V_3P3STBY 1 4.7K 402

5% CH

2 0.7DCR 603

1K 0.2A

CR2N1

AUD_CLAMP

R2M12 2

1

AUD_CLAMP_L

5% CH

MBT3904

IN

43

R2B4

1

34

OUT

2

X801161-001

603 EMPTY

FTP

43

AUD_ACAP

DGND

FT2P1

OUT

AUD_VOUTR AUD_VOUTL

2

R2N3

14

1

FT2N2 33

36 36 36 36

MMBT3906 XSTR

2 1K 402

R2N2

1

AUD_CLAMP_B2

3

6 2

5

5% CH

4

1

AUD_CLAMP_B3

XSTR

2

R2N1

1K 402

1

5% CH

AUD_CLAMP_B1

1

R2M13

2

[PAGE_TITLE=SB

OUT,

AUDIO]

1K 5% CH 402

DRAWING XENON_FABK Wed Aug 24 09:27:29

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 40/73

REV K7

FLSH_DATA1

N: N:

FLSH_DATA0 0 1 0

8MB

16MB

1

32MB

64MB

RETAIL=16MB XDK=64MB

V_3P3STBY

1

FT1R3 FT1R4 FT1R5 FT2R3 FT2R4 FT2R5 FT2R6 FT2R7

FTP FTP FTP FTP FTP FTP FTP FTP

1 1 1 1 1 1 1 1

2

1

1

R2D7

R2D6

R1E2

10K 5% CH 402

10K 5% EMPTY 402

10K 5% CH 402

2

2

1 2

1

C2E6

10UF 10% 6.3V X5R 1206

2

1

C2E5 .1UF 10% 6.3V X5R 402

2

IN

FLSH_DATA<7..0>

.1UF 10% 6.3V X5R 402

STUFFED AT CONFIG LEVEL UPDATE TO RECENT PART NO#

U2E1

IC NAND FLASH RDY

1 35

N: N:

C2R11

FTP

FT1T1

7 6 5 4 3 2 1 0

1

2

1

1

1

1

1

1

1

R2D8

R2D5

R2D4

R2D3

R2D1

R1D4

R1D3

R1D2

10K 5% EMPTY 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

2

2

2

2

2

2

2

35 35 35 35 35 35

IN IN IN IN IN IN

FLSH_CE_N FLSH_RE_N FLSH_WE_N FLSH_WP_N FLSH_ALE FLSH_CLE

37 12

VCC1 VCC0

44 43 42 41 32 31 30 29

DATA<7> DATA<6> DATA<5> DATA<4> DATA<3> DATA<2> DATA<1> DATA<0>

9 8 18 19 17 16

CE_N* RE_N* WE_N* WP_N* ALE CLE

6 36 13

VSS/NC VSS1 VSS0

NC<27> NC<26> NC<25> NC<24> NC<23> NC<22> NC<21> NC<20> NC<19> NC<18> NC<17> NC<16> NC<15> NC<14> NC<13> NC<12> NC<11> NC<10> NC<9> NC<8> NC<7> NC<6> NC<5> NC<4> NC<3> NC<2> NC<1> NC<0>

X803471-003

[PAGE_TITLE=SB

OUT,

FLASH]

FLSH_READY

7 38 48 47 46 45 40 39 35 34 33 28 27 26 25 24 23 22 21 20 15 14 11 10 5 4 3 2 1

FLSH_NC38

2

R2D2

0 402

OUT

35

1

5% EMPTY

TSOP

DRAWING XENON_FABK Wed Aug 24 09:27:30

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 41/73

REV K7

V_3P3STBY BINDING

V_12P0

BUTTON

FAN CONTROL 1

1

R5V3

SWITCH TH SW5G1 THR

2

4 3

1 2

5.11K 402

10K 5% CH 402

3

R5V2

10K 402

1

BINDSW_N

OUT

29

34

IN

FAN1_OUT

C4N25 2700PF 10% 50V X7R 402

1

2

V_FAN1

1

R3A1 249 1% CH 402

R1G4 10K 5% CH 402

R1G3

2

EJECTSW_N_R

1

EJECTSW_N

OUT

34

FAN1_FDBK_R

2 1 2

D3A1 1N4148 SOT23 DIO

1

FAN1_Q1_E

2

4 3

3

MMBT2222 XSTR 2

V_3P3STBY

SW1G1 THR

BCP51 XSTR 2 4

Q3A1

1

5% CH

X02246-002

TH

Q3M1

1

3

2

SWITCH

1

1% CH

FAN1_Q1_C

BINDSW_N_R

ODD EJECT BUTTON

R3A8

2

47

5% CH

10K 402

1

R4P2

5.11K 402

V_3P3STBY

C3M1 1UF 10% 50V X7R 603

2 R3A7

2

X02246-002

1 1 30K 1% CH 402

2

1

FAN1_FDBK

1% CH

29

OUT

J3A1

1

2X2HDR

R3A2 TILT SM

R2G2

SW2G1 SM

2

4 3

1 2

11K 1% CH 402

1

SWITCH

10K 5% CH 402

2

R2G3

2

TILTSW_N_R

10K 402

X800550-001

1

TILTSW_N

OUT

2 4

HDR

V_12P0

FAN CONTROL 2

34

5% CH

R3B16

2

5.11K 402

1

1% CH

FAN2_Q1_C

3

Q3A2

1

SWITCH

29

IN

FAN2_OUT

Q3M4

1

3

BCP51 XSTR 2 4

3

TILT SM

1 3

MMBT2222 XSTR

1

D3B1 1N4148 SOT23 DIO

2

4 3

1 2

2

FAN2_Q1_E

SW2G2 SM

C4N20

1

R3M4 249 1% CH 402

V_3P3STBY

V_IR 1 C2V1

U1G1

4.7UF 10% 6.3V X5R 805

IC IR

VCC DATA GND ME2 ME1

2

49.9 402

R2V1 1% CH

FAN2_FDBK_R

1 1

2 2

C2V2

R2N7

.1UF 10% 6.3V X5R 402

1

3 1 2 5 4

1

2

2700PF 10% 50V X7R 402

X800550-001

V_FAN2

10K 5% CH 402

1

R3A5

2

2 5.11K 402

R4N8

2

C3A7

1UF 10% 50V X7R 603

30K 1% CH 402

FAN2_FDBK

OUT

29

1

1% CH

1

R3M5 IR_DATA

OUT

34

2

11K 1% CH 402

X803473-002

[PAGE_TITLE=CONN,

FAN + INFRARED

+ SWITCHES]

DRAWING XENON_FABK Wed Aug 24 09:27:30

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 42/73

REV K7

AARON:

THIS

PAGE HAS TOO MUCH ON IT.

L3A3 1

D3A4 2

2

1

2

1

OUT

IND 1210

1 1

C3A6 62PF 5% 50V NPO 402

2

75PF 5% 50V NPO 402

36

2

DIO SOT23S BAV99

3

R3A3 D3A3

75 1% CH 402

V_3P3

2

1

2

2

1

43

OUT

IND 1210

.27UH 0.45A NA

1

VID_DACB_OUT

C2A6

2

IN

2

62PF 5% 50V NPO 402

1

C2M5

C2A1

4.7UF 10% 6.3V X5R 805

470PF 5% 50V X7R 402

2

75PF 5% 50V NPO 402

43

IN

62PF 5% 50V NPO 402

2

75PF 5% 50V NPO 402

1

WSS_CNTL1

IN

R2A6

43

2

WSS_CNTL0

1% CH

3

2

62PF 5% 50V NPO 402

1

43

IN

40

IN

40

4

C2A2 75PF 5% 50V NPO 402

2

WSS_CNTL_OUT_R

1% CH

IN

XSTR

1

WSS_CNTL_E

43

R2A5

1K 402

VID_VSYNC_OUT

OUT

33

43

R2M11 1

PB

PB

B

B

D

CVBS(COMP)

CVBS(COMP)

CVBS

N/A

CVBS

CVBS

VID_DACD_OUT VID_DACD_RET

VID_VSYNC_OUT

12 10

VID_VSYNC_OUT VID_VSYNC_RET

25

SPDIF

AUD_R_OUT

15 13

AUD_R_OUT AUD_R_RET

AUD_L_OUT

16 14

AUD_L_OUT AUD_L_RET

1

17 19

WSS_CNTL SCART_RGB

WSS_CNTL_OUT

C2A8 75PF 5% 50V NPO 402

3

1% CH

2

VID_HSYNC_OUT

OUT

43

R2M9 5% CH

DDC_CLK DDC_DATA

AV_MODE2 AV_MODE1 AV_MODE0

28 24 20

AV_MODE2 AV_MODE1 AV_MODE0

OUT OUT OUT

34

34

34 34 34

43 43 43

34 33 32 31

MTGB<8-1> MTGA<8-1>

TH

1

56 34 34 34

43 43 43 43

IN IN IN IN

EXT_PWR_ON_N AV_MODE2 AV_MODE1 AV_MODE0

2

1

2

35 35

26 22 18

GND<2> GND<1> GND<0> SHIELD<3> SHIELD<2> SHIELD<1> SHIELD<0>

2

1

56

OUT

BI BI

V_3P3STBY

3

33 402

EXT_PWR_ON_N

21 23

X800055-001

34

1

30

DDC_CLK DDC_DATA

2

C2M4 0.01UF 10% 16V X7R 402

1

1

1

R2A1

R2M6

R2M4

R2M2

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

C2A3 470PF 5% 50V X7R 402

2

1 2

LAYOUT:PLACE

C2M3 470PF 5% 50V X7R 402

2

1 2

C2M2 470PF 5% 50V X7R 402

2

1 2

C2M1

470PF 5% 50V X7R 402

CLOSE TO CONNECTOR EMI CAPS

1

D3M2 2

V_3P3STBY

R3M2

CONNECTOR

EXT_PWR_ON

VID_HSYNC_OUT VID_HSYNC_RET

MMBT3906 XSTR

5% CH

CONN

XENON AVIP V_AVIP V_AVIP_RET

7 5

Q2M1

1

5% CH

1

VID_HSYNC_OUT_R

AVIP]

N/A

11 9

2 SCART_RGB_R

R2M10 1

IN

N/A

VID_HSYNC_OUT

5% CH

SCART_RGB_OUT_R

1

2

2 10K 402

49.9 402

[PAGE_TITLE=[CONN,

SCART_RGB

IN

1% CH

29

C

VID_DACC_OUT VID_DACC_RET

1

10K 402

3 D3M3

V_3P3STBY

2

BAV99 SOT23S DIO

49.9 402

R3M3

R

VID_DACB_OUT VID_DACB_RET

2

2

1

VID_VSYNC_OUT_R

BAV99 SOT23S DIO

IN

G

R

8 6

V_3P3

29

G

PR

VID_DACC_OUT

5% CH

OUT

IN

6

R2A4 2

VID_DACD_OUT

C2A5

Y

PR

VID_DACA_OUT VID_DACA_RET

10K 402

1

2

43

2

R2A9 2

2

Y

C(CHROMA)

3 1

VID_DACD_OUT

IN

2

1% CH

IND 1210

1

2

2

75 1% CH 402

R2A7

301 402

D2A2

3

DIO SOT23S BAV99

R2A3

V_3P3

1 4.75K 402

1

1 .27UH 0.45A NA

Y(LUMA)

N/A

4 2

CR2A1 MBT3904

1

IN

L2A1 1

VGA

N/A

VID_DACB_OUT

WSS_CNTL_B

5 33

VID_DACD_DP

IN

C3A1

5.36K 402

IN

SCART

B

VID_DACA_OUT

SCART_RGB_OUT

C3A4

33

29

IN

43

1

1% CH

2

43

V_12P0

IND 1210

2

1

2

2

43

OUT

R2A8 1

D3A2

75 1% CH 402

1

VID_DACC_OUT

1.82K 402

3

DIO SOT23S BAV99

R3A6

V_3P3

2

.27UH 0.45A NA

1

HDTV

A

J2A1

L3A1 1

VID_DACC_DP

IN

SDTV

C3A2

29 27

29

ADVANCED

V_3P3 1

C3A5

THRMSTR 1206

2 22PF 5% 50V NPO 402

STANDARD

V_AVIP

2

SPDIF

IN

L3A2 1

VID_DACB_DP

RT2M1

1.1A 0.21DCR

C3A3

1

29

DAC

43

D2A1

3

R3A4 75 1% CH 402

V_5P0

VID_DACA_OUT

3

DIO SOT23S BAV99

.27UH 0.45A NA

1

V_3P3

2

1

VID_DACA_DP

IN

DIO SOT23S BAV99

29

DRAWING XENON_FABK Wed Aug 24 09:27:31

MICROSOFT 2005

CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 43/73

REV K7

43

V_5P0DUAL RT1B1 44

2

V_EXPPORT

IN

V_EXPPORT

1

1.1A 0.21DCR

D1A2

THRMSTR 1206

L1B1

35

BI

EXPPORT_DN

1

BI

EXPPORT_DP

4

5% CH

1

470PF 5% 50V X7R 402

2 1

1

FTP

FT1N2

C1M2

4.7UF 10% 6.3V X5R 805

1

NA SM

BAV99 SOT23S DIO

EMPTY

CMCHOKE

2

EXPPORT_DN_CM

3

EXPPORT_DP_CM

D1A1

X801560-001

1

2 3

R1B1

EG1A2 PGB0010603 X801161-001 EMPTY 603

1

5% CH

BAV99 SOT23S DIO

2

0 603

2 ELEC RDL

C1A3

EG1A1 PGB0010603 X801161-001 EMPTY 603

2

35

3

1

0 603

2

220UF 20% 10V

2

R1B2

1 C2A4

J1A1 XENON RJ45/USB

48

IN

ARGON_NTX D1B1

44

IN

V_EXPPORT

2

2 3

1

470PF 5% 50V X7R 402

IN

16

OMNI

V_ENET

1 0 402

1 0 402

IN IN

ENET_P2LI_R ENET_LINK_N

1 2

LED_LEFT_A LED_LEFT_C

3 4

LED_RIGHT_A LED_RIGHT_C

39

39 19

39

39 19

IN IN

ENET_POAC_R ENET_ACT_N

2

39

19

IN

ENET_TX_DP

5% EMPTY

39

19

IN

ENET_TX_DN

2

39

19

IN

ENET_RX_DP

5% EMPTY

39

19

IN

ENET_RX_DN

BAV99 SOT23S DIO 39

VBUS DD+ GND

C1A4

1

19

12 13 14 15

R1M3

R1A5

ENET_TX_CT

ENET_RX_CT

C1M1

.1UF 10% 6.3V X5R 402

11 10 7

XFMER2_P XFMER2_C XFMER2_N

9 6 5

XFMER1_P XFMER1_C XFMER1_N

8

CAP

20 19 18 17

EMI4 EMI3 EMI2 EMI1

C1A2 .1UF 10% 6.3V X5R 402

21

CONN COMBO

ME1 X806148-001

[PAGE_TITLE=CONN,

ETHERNET]

DRAWING XENON_FABK Wed Aug 24 09:27:32

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 44/73

REV K7

V_MEMPORT1

OUT

V_MPORT V_5P0DUAL RT2G1 RT8G1 1

C8V14

4.7UF 10% 6.3V X5R 805

2

1 C9G2 2

220UF 20% 10V ELEC RDL

1

470PF 5% 50V X7R 402

35

BI

2

35

BI

MEMPORT2_DP

4

CMCHOKE

2

MEMPORT2_DN_CM

2

1

GAMEPORT2_DP_CM

BAV99 SOT23S DIO

GAMEPORT1_DN_CM GAMEPORT1_DP_CM

V_5P0DUAL RT8G2 V_GAMEPORT1

THRMSTR 1206 2

1

C9V3

4.7UF 10% 6.3V X5R 805

2

1 C9G3 220UF 20% 10V ELEC RDL

2

1

1

EG4G1 PGB0010603 X801161-001 603 DIO

XENON MU

5% CH

CONN

C9G4

1 2 3 4

VBUS DD+ GND

5 6 7 8

VBUS DD+ GND

9 10

EMI1 EMI2

11 12

ME1 ME2

470PF 5% 50V X7R 402

1

X800245-003

2

1 C2G2 2 R3G4 0 603

220UF 20% 10V ELEC RDL

1

C3V5

470PF 5% 50V X7R 402

2 1

C2G3

4.7UF 10% 6.3V X5R 805

5% CH

NA SM L2G1 35

BI

MEMPORT1_DN

1

35

BI

MEMPORT1_DP

4

EMPTY

CMCHOKE

2

MEMPORT1_DN_CM

3

MEMPORT1_DP_CM

1 2 3 4 5

GND VBUS DD+ GND

6 7 8 9 10

GND VBUS DD+ GND

14 13 12 11

EMI4 EMI3 EMI2 EMI1

15 16 17 18

ME4 ME3 ME2 ME1 MTGA<8-1> MTGB<8-1> MTGC<8-1> X800059-001

R2G5

D9V2

1 3

5% CH 1

NA SM L9V1

35

BI

GAMEPORT1_DN

4

BI

GAMEPORT1_DP

1

BAV99 SOT23S DIO

EMPTY

CMCHOKE

3

EG9V1 PGB0010603 X801161-001 603 EMPTY

2 D9V1

X801560-001

2

2

3

R9V1 0 603

[PAGE_TITLE=CONN,

5% CH

1

2

2

5% CH

V_MPORT

V_5P0

U1F2

C1U2 1.0UF 10% 16V X7R 805

IC NCP1117

1

35

EG9V2 PGB0010603 X801161-001 603 EMPTY

2

0 603

0 603

2

EG2G1 PGB0010603 X801161-001 603 DIO

2

EG3G1 PGB0010603 X801161-001 603 DIO

V_5P0DUAL

TH

1

1

X801560-001

R9V2

CONN

J3G1

XENON GAME CONN GAMEPORT2_DN_CM

5% CH

1

MEMPORT2_DP_CM

EG4G2 PGB0010603 X801161-001 603 DIO

R4G4

J9G1

3

R9G1

3

0 603

TH

2

1.1A 0.21DCR

1

1

D9G1

X801560-001

2

MEMPORT2_DN

EG9G1 PGB0010603 X801161-001 603 EMPTY

2

0 603

BI

X801560-001

BAV99 SOT23S DIO

3

1

1

35

2

GAMEPORT2_DP

NA SM

1

EMPTY

CMCHOKE

4

C5G6

4.7UF 10% 6.3V X5R 805

1

EMPTY

2

GAMEPORT2_DN

470PF 5% 50V X7R 402

5% CH

L4G1

2

BI

2

2

C4V6

3

NA SM 35

0 603

2

5% CH

L9G1

220UF 20% 10V ELEC RDL

R4G5

EG9G2 PGB0010603 X801161-001 603 EMPTY

2

1

1 C5G4 2

D9G2

R9G2

V_MEMPORT2

1 FB 603

C9G1

V_5P0DUAL

0 603

2 120 0.5A 0.2DCR

THRMSTR 1206

1.1A 0.21DCR

1

1

1

1

V_GAMEPORT2

THRMSTR 2 1206

1.1A 0.21DCR

FB5G1

2

2

3

IN

1

ADJUST/GND

OUT

2

1 1

X800499-001

2

C1F6 0.1UF 10% 25V X7R 603

FTP

FT1V1

1 C1F4

100UF 20% 16V

2 ELEC RDL

1 BAV99 SOT23S DIO

MEMORY PORTS

+ GAME PORTS]

DRAWING XENON_FABK Wed Aug 24 09:27:33

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 45/73

REV K7

V_3P3STBY

V_5P0DUAL

FB3P2 1

V_3P3STBY

.1UF 10% 6.3V X5R 402

2

C3N8

.1UF 10% 6.3V X5R 402

1

V_3P3

1

R1G2

R1G1

R1V2

1K 5% CH 402

20 1% CH 1206

20 1% CH 1206

2

2

2 0.1DCR 603 EMPTY

N:

ONE CAP PER POWER PIN STBY_CLK

FB3P1 1

2

ANA_XTAL_BACKUP

2 1

2

C3P6 4.7UF 10% 6.3V X5R 805

1

2

C3P4

.1UF 10% 6.3V X5R 402

C3P8

.1UF 10% 6.3V X5R 402

1

2

C3P2 .1UF 10% 6.3V X5R 402

1

2

.1UF 10% 6.3V X5R 402

1

Q1G2

MMBT2222 XSTR

SMC_RST_N

IN

1M 402

MMBT2222 XSTR

2 1

C3N3

ANA_CLK_OE

2 1K 402

2

C3B13 22PF 5% 50V NPO 402

22 23 17 5 1

C3B14 22PF 5% 50V NPO 402

1

R3P3

1 28 56

56 34

34 28

SMB_CLK SMB_DATA

IN IN

BCKUP_X1 BCKUP_X2

28

CPU_CLK_DP_R CPU_CLK_DN_R

15 16

GPU_CLK_DP_R GPU_CLK_DN_R

18 19

SMB_CLK SMB_DATA

14 13

20

BCKUP_RSET

21 25 12 9 4

GND_5 GND_4 GND_3 GND_2 GND_1

11 10

SATA_CLK_DP_R SATA_CLK_DN_R

33 402

GPU_CLK_DN_R

33 402

1

R1R3

10K 5% CH 402

10K 5% CH 402

R1R5

2 1

33 402

2

VREG_V5P0_SEL FT1R1

FTP

1

1 4.7K 402

R1D6

2

VREG_V5P0_SEL_B1

5% CH

1

VREG_V5P0_SEL_B2

XSTR

CLOCK

+ V_5P0

DUAL]

49.9 402

2

1 1

1

1% CH

R3C3

49.9 402

5% CH

R3C2

1

5% CH

R3B8

33 402

2

2

1

33 33

OUT OUT

2

FTP FTP

FT3P2 FT3P1

OUT OUT

33 33

2

1% CH

R3C1

49.9 402

2

1 1

1% CH

ENET_CLK

5% CH

OUT 1 2

ANA_BCKUP_F25MB

SI4501DY S2 G2

1

R3C27 2

19

FTP FTP

FT1P2 FT1P1

39

C3B4

10PF 5% 50V EMPTY 402

5 8 7 6

1

FTP

SATA_CLK_REF

5% CH

33 402 D<3> D<2> D<1> D<0>

2 1

OUT 1

FT1R2

2

G1 S1 ANA_BCKUP_F48M

1

R3B7

33 402

X801132-001

R1D5

1

[PAGE_TITLE=[BACKUP

.1UF 10% 6.3V X5R 402

R3C5

IC

C1R3

2 4.7K 5% CH 402

5% CH

R3C4

1

V_5P0DUAL

V_5P0

CR1D1

1

SATA_CLK_DP SATA_CLK_DN

VREG_V5P0_SEL_NGATE

5% CH

2

SATA_CLK_DN_R

TSSOP28

U1R1

3 4

2

1% CH

PCIEX_CLK_DP PCIEX_CLK_DN R3C6

1

SATA_CLK_DP_R

33 402

220UF 20% 10V ELEC RDL

VREG_V5P0_SEL_PGATE

R3C9

49.9 402

PCIEX_CLK_DN_R

33 402

2

1

5% CH

PCIEX_CLK_DP_R

1 C1D11

R1R2

1% CH

49.9 402

R3C10

GPU_CLK_DP_R

24

BCKUP_F48M

5% CH

13 13

R3C15 2

CPU_CLK_DN_R

1

MBT3904

IN

1% CH

CPU_CLK_DP_R

6 7

BCKUP_F25MA BCKUP_F25MB

X803897-001

V_12P0

1

34

R3C16 2

49.9 402

1

4 4

1% CH

GPU_CLK_DP OUT GPU_CLK_DN OUT

ANA_BCKUP_F25MA

V_5P0STBY

10K 402

1

5% CH

OUT OUT

R3C17 2

49.9 402

R3C7

V_5P0STBY

2

1

5% CH

33 402

GEN

PCIEX_CLK_DP_R PCIEX_CLK_DN_R

BCKUP_OE

475 1% CH 402

CLK

X1_BCKUP

8

R3P2

1

VCC3_5 VCC3_4 VCC3_3 VCC3_2 VCC3_1

27 26

ANA_BCKUP_OE

5% CH

2

VREG_V5P0_SEL_C

1% CH

IC BACKUP

ANA_BCKUP_RSET

2

R3C18 2

2

2 3 IN

1 49.9 402

5% CH

R3C8 NOTE: SWAP POLARITY FOR ROUTING

V_3P3STBY

34

28

OUT

CPU_CLK_DP CPU_CLK_DN

5% CH

SM XTAL

V_1P8STBY

28

R3C12

33 402

U3B4

.1UF 10% 6.3V X5R 402

.1UF 10% 6.3V X5R 402

ANA_BCKUP_X2

2

2

1

1

ANA_XTAL_IN

R3C11

Y3B1 27MHZ

2

1

5% CH

ANA_BCKUP_X1

R3B4

1

Q1V1

1

BLEEDER_B

5% CH

10K 402

2

R3B5

33 402

V_3P3STBY

2

1

.1UF 10% 6.3V X5R 402

2

C3P5

V_1P8STBY

3

R1V1

1

1

C3P7

33 402

1

2

2

C3P1

3

56 28 34

STITCH

V_CLKGEN

0.1DCR 603

60 0.5A

BLEEDER_C2

1

C3N9

2

1

BLEEDER_C1

2

1

60 0.5A

VREG_5P0_SEL

VREG_5P0_SEL NGATE/PGATE

V_5P0DUAL

HIGH

LOW

V_5P0STBY

LOW

HIGH

V_5P0

2

2005

FTP

OUT 1

MICROSOFT CONFIDENTIAL

33

FT2N4

10PF 5% 50V EMPTY 402

STBY_CLK

5% CH

2

DRAWING XENON_FABK Wed Aug 24 09:27:34

1 C3C3

C3C4

1

FTP

34

FT2R2

10PF 5% 50V EMPTY 402

PROJECT NAME XENON_RETAIL

PAGE 46/73

REV K7

V_5P0 D1E4 2 3 36

HDD_TX_DP

IN

C1E4

1

2

1

0.01UF

10% 16V X7R 402

BAV99 SOT23S DIO

HDD_TX_DP_C

HDD SATA AND POWER

HDD_TX_DN_C

36

HDD_TX_DN

IN

D1E3

C1E3

1

0.01UF

2

J1E1

10%

1 2 3 4 5 6 7

3

16V X7R 402

1 BAV99 SOT23S DIO

V_5P0

1

C1E2

2

1

10% 16V X7R 402 HDD_RX_DN_C

2

BAV99 SOT23S DIO

1

1 EG1E2 PGB0010603 X801161-001 603 EMPTY

2

0.01UF

EG1E3 PGB0010603 X801161-001 603 EMPTY

EG1E1 PGB0010603 X801161-001 603 EMPTY

36

OUT

1

C1E1

V_5P0

D1E1 2

RT1U1

2 2

0.01UF

10% 16V X7R 402

3

1 C1E5

1

2 ELEC RDL

2

100UF 20% 16V

C1T5 1UF 10% 50V X7R 603

1

C1T4

V_5P0DUAL

IN

1

C1C6

2

10% 16V X7R 402

36

IN

ODD_TX_DN

1

C1C5

2

V_12P0

10% 16V X7R 402

36

OUT

ODD_RX_DN

1

C1C4

2

ODD_RX_DN_C

0.01UF

10% 16V X7R 402

36

OUT

ODD_RX_DP

1

C1C3

2

1 2 3 4 5 6 7

1 C1C10 100UF 20% 16V ELEC RDL

2

C1C14 1UF 10% 50V X7R 603

2

1 C1C11

C1C13

0.1UF 10% 25V X7R 603

2

34

100UF 20% 16V ELEC RDL

OUT

1 2

C1D6

10% 16V X7R 402

C1T1

1 C1D9 2

ODD POWER AND CONTROL CR1D2

CR1D3

1UF 10% 50V X7R 603

.1UF 10% 6.3V X5R 402

TRAY_STATUS

100UF 20% 16V ELEC RDL

1 2

C1D4

1UF 10% 50V X7R 603

1 2

C1D1

1UF 10% 50V X7R 603

C1D3

2

3

3 1

TRAY_STATUS_R

1

R1R4

2

V_3P3

1 3 5 7 9 11

4 6 8 10 12

V_12P0

.1UF 10% 6.3V X5R 402

BAV99 SOT23S EMPTY

J1D1

V_5P0

5% CH

1

BAV99 SOT23S EMPTY

EJECTSW_N TRAY_OPEN

CONN

ODD + HDD]

V_3P3

C1T2

470PF 5% 50V X7R 402

1UF 10% 50V X7R 603

C1R1

100 402

0.01UF

[PAGE_TITLE=CONN,

1

V_5P0

CONN

1 2

8

ODD_RX_DP_C

V_XPOD

V_3P3

9

0.01UF

1 THRMSTR 1206

1.1A 0.21DCR

2

J1C1 SATA

ODD_TX_DN_C

C1T3

V_3P3

ODD POWER DECOUPLING

0.01UF

TH

RT1R1 2

ODD_TX_DP_C

ME1 ME2

470PF 5% 50V X7R 402

1UF 10% 50V X7R 603

2

ODD SATA ODD_TX_DP

EMI1 EMI2

17 18

V_HDD

THRMSTR 1812

BAV99 SOT23S DIO

36

15 16

X800351-002

1

1.5A 0.11DCR

1

GND GND GND V_HDD V_HDD V_HDD V_XPOD

MTGA<8-1> MTGB<8-1>

HDD_RX_DP_C

HDD_RX_DP

XENON HDD CONN

GND D+ DGND DD+ GND

8 9 10 11 12 13 14

2

EG1E4 X801161-001 PGB0010603 603 EMPTY

3

HDD_RX_DN

OUT

2

1

2

1

D1E2

36

CONN

2

DRAWING XENON_FABK Wed Aug 24 09:27:35

2005

MICROSOFT CONFIDENTIAL

1 2

IN IN

42 34

34

C1R4

75PF 5% 50V NPO 402

PROJECT NAME XENON_RETAIL

PAGE 47/73

REV K7

DB8M1 TP

1 DB8M2 TP

1

V_12P0

V_3P3STBY

FTP

1

FT9N1

DB8M3 TP

1

2

1 C6G5 2

100UF 20% 16V ELEC RDL

1

0 603

1

ALUM 2 RDL

2

1500UF 20% 16V

C6G2 470PF 5% 50V X7R 402

34

R6G7

1

1 C9B1

IN

L6G1

R8A1

5% CH

ARGONPORT_DP

X801560-001

1 2

R6G8

2

C6G3

470PF 5% 50V EMPTY 402

1 2

C6G4

470PF 5% 50V EMPTY 402

ARGON_DN_CM ARGON_DP_CM

5% CH

USE LC NETWORK FOR USB 1.1 USE USB CHOKE FOR USB 2.0

V_3P3STBY 1

R3N7 10K 5% CH 402

2 34

IN

PWRSW_N

2 10K 402

R3N6 5% CH

1

TH CONN

J6G1

2

0 603

1

J9A1

PSU_V12P0_EN_R

1

10K 5% CH 402

2

1

C8A1 .1UF 10% 6.3V X5R 402

2

C8A2

470PF 5% 50V EMPTY 402

VCC DD+ GND

5 6 7 8 9

SPARE C_DATA C_CLK GND NTX EMI1 EMI2

12 13

ME1 ME2

4 5 6

V12P0 V12P0 V12P0

7

PSU_EN

8

VSB5P0

9 10 13 14

EMI1 EMI2 EMI3 EMI4

11 12

ME1 ME2 MTGA<8-1> MTGB<8-1>

1

1 C5B7

10 11

GND GND GND

V_5P0STBY

XENON RF CONN

1 2 3 4

CONN XENON PWR

1 2 3

2

FTP

1 C8B1

100UF 20% 16V ELEC RDL

2

100UF 20% 16V ELEC RDL

V_5P0STBY

V_12P0

1

1

FT8N1

1

TH

X02285-004

C9A4

470PF 5% 50V X7R 402

2

V_12P0

X800095-001

R8B5

2

BI BI

ARGON_DATA ARGON_CLK 2

C6V11

470PF 5% 50V X7R 402

1

2 1

C6V10

470PF 5% 50V X7R 402

R7B2

2.2K 5% CH 402

C6V15 470PF 5% 50V X7R 402

34 34

2 44

OUT

2.2K 402

ARGON_NTX 2 1

ARGON + POWER]

R8A4

1

5% CH

BLEEDER_V12P0_B1

2.2K 5% CH 402

2

2 549 402

R8N1

Q8B4

MMBT2222 XSTR 2

2

Q8B5

3 1

BLEEDER_V12P0_B2

1 3

1

1

1% CH

Q8N1

BCP51 XSTR 2 4

BLEEDER_V12P0_LOAD

1 3

[PAGE_TITLE=CONN,

0.1UF 10% 25V X7R 603

1

5% CH

PWRSW_N_R

2

C9A2

2

3

1

1

R8A2

C9A6

0.1UF 10% 25V X7R 603

2

BLEEDER_V12P0_C2

BI

0.1UF 10% 25V X7R 603

1

EMPTY

CMCHOKE

4

2

C9A5

2

1

BLEEDER_V12P0_C1

35

ARGONPORT_DN

BI

0.1UF 10% 25V X7R 603

100 402

1

NA SM

35

C9A1

2

PSU_V12P0_EN

2

1

1

1

1

R7N3

R7N1

R7N4

R7N2

10 1% CH 805

10 1% CH 805

10 1% CH 805

10 1% CH 805

2

2

2

MMBT2222 XSTR 2

C6V12 470PF 5% 50V X7R 402

34

28

IN

ANA_V12P0_PWRGD

2 2.2K 402

R8A3

1

5% CH

DRAWING XENON_FABK Wed Aug 24 09:27:35

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 48/73

REV K7

4 4 4

4

IN

0 402

CPU_VREG_APS2

0 402

CPU_VREG_APS0

IN

0 402

V_GPUCORE

R7E1 0 402

5% CH

R7E2

CPU_VREG_APS1

5

5% CH

R7E5

CPU_VREG_APS3

IN IN

4

CPU_VREG_APS4

IN

4

R7E3

CPU_VREG_APS5

IN

4

5% CH

3

1

R7E4 0 402

5% CH

5% CH

R7E6 1K 402

1

1

1

1

N: N: N:

1

2

R7T6

R7T4

R7T8

R7T7

R7T5

R7T9

1

10K 5% EMPTY 402

10K 5% CH 402

10K 5% CH 402

10K 5% CH 402

10K 5% EMPTY 402

10K 5% EMPTY 402

2

0

5% CH

2

5

1

2

2

4

2

3

1

2

2

1

1

2

1

0

1

VREG_CPU_VID<5..0>

1

R7T13

R7T11

R7T15

R7T14

R7T12

R7T16

10K 5% CH 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% CH 402

10K 5% CH 402

2

2

2

2

2

1

N:CPU

INPUT

1

1 2

C9B2 4.7UF 10% 16V X5R 1206

1.6UH 10A NA

2

V_VREG_CPU

IND TH

C9C4

C9C1

1500UF 20% 16V ALUM RDL

1500UF 20% 16V ALUM RDL

C9E3

1500UF 20% 16V ALUM RDL

C9D2

1500UF 20% 16V ALUM RDL

1 2

C9B4

10UF 20% 16V EMPTY 1206

1 2

V_CPUCORE

1 C8F3

2200UF 20% 6.3V

C8F1

2200UF 20% 6.3V ALUM RDL

[PAGE_TITLE=VREGS,

1

OUTPUT FILTER

C8E3

2200UF 20% 6.3V ALUM RDL

INPUT

C8F2

2200UF 20% 6.3V ALUM RDL

C8E8

2200UF 20% 6.3V ALUM RDL

C8D1

2200UF 20% 6.3V ALUM RDL

+ OUTPUT FILTERS]

50

51

1 2

10UF 20% 16V EMPTY 1206

C8B2

2

1.6UH 10A NA

IND TH

V_VREG_GPU 1 C6B3

1 C7B3

1

2 ALUM RDL

2 ALUM RDL

2

1500UF 20% 16V

4.7UF 10% 16V X5R 1206

1500UF 20% 16V

C8B4

10UF 20% 16V X5R 1206

1 2

C6B5 10UF 20% 16V X5R 1206

1

OUT 1

C6N2 10UF 20% 16V X5R 1206

2

2

C7B4 10UF 20% 16V X5R 1206

1 2

52

53

C7N3

10UF 20% 16V X5R 1206

DB8P1

1

2 ALUM RDL

OUT

C9C3

1

N:CPU

FILTER

L8B1

L9B1 1

50

C7E13

N:GPU INPUT

FILTER

OUT

220PF 5% 50V NPO 402

2

V_12P0 V_12P0

WATERNOSE=011100=1.1625V DD1.0 REQUIRES VID0 RC DD2.0 NO STUFF RC

DB8P2 FTP

C8C1

2200UF 20% 6.3V ALUM RDL

V_GPUCORE

FT7U1

1

N:GPU OUTPUT FILTER

C8D4

2200UF 20% 6.3V ALUM RDL

FTP

FT5R2

1 C7C2

1 C7C1

1 C6C3

1 C6C2

1 C6C1

1 C5C4

2 ALUM RDL

2 ALUM RDL

ALUM 2 RDL

2 ALUM RDL

2 POLY RDL

2 POLY RDL

2200UF 20% 6.3V

2200UF 20% 6.3V

2200UF 20% 6.3V

DRAWING XENON_FABK Wed Aug 24 09:27:36

2200UF 20% 6.3V

2005

820UF 20% 4V

MICROSOFT CONFIDENTIAL

820UF 20% 4V

PROJECT NAME XENON_RETAIL

PAGE 49/73

REV K7

51 34

49

V_VREG_CPU

IN

10 805

VREG_CPU_EN

IN FT2P17

FTP

R7V5

2

1

VREG_CPU_VCC

1% CH

1

1

C7V1 1UF 10% 50V X7R 603

1

1

R7F5

2

2

10K 5% CH 402

1 C7G1

R8U3

2

294K 1% CH 402

100UF 20% 16V ELEC RDL

2

1

U7U1 51

IN

IN

0 603 51

IN

5% CH

0 603

DB7U3

1

2

R8V1

R8V2

R8V4

47.5K 1% CH 603

47.5K 1% CH 603

47.5K 1% CH 603

1

VREG_CPU_CSCOMP_R

2

1

RAMPADJ

11

EN

VREG_CPU_PHASE1_R

20 21 22 23

SW4 SW3 SW2 SW1

VREG_CPU_CSCOMP

18

CSCOMP

17

CSSUM

16

CSREF

VREG_CPU_SW4

1

TP

VREG_CPU_PHASE3_R VREG_CPU_PHASE2_R

5% CH

1

2

VCC

14

VREG_CPU_RAMPADJ

R7V3

VREG_CPU_PHASE1

RT8F1

2

TEMP SENSOR

THRMSTR 603

NA 100K

8

R8V3

1

2

1% CH

35.7K 603

2

1

R8V5 76.8K 1% CH 603

1

34

ADP3188 28

5% CH

R7V2

VREG_CPU_PHASE2

FT2P16

OUT

IC

R7V1

VREG_CPU_PHASE3 0 603

51

FTP

VREG_CPU_PWRGD

2

1

C8V1

360PF 10% 50V NPO 603

10

VID5 VID4 VID3 VID2 VID1 VID0

6 1 2 3 4 5

PWM4 PWM3 PWM2 PWM1

24 25 26 27

VREG_CPU_PWM3 VREG_CPU_PWM2 VREG_CPU_PWM1

8200PF 10% 16V CH 603

12

VREG_CPU_DELAY VREG_CPU_RT

COMP

RT

13

7

FBRTN

GND

19

1 2

R8U2 ST7T1

2

51 51 51

VREG_CPU_DRV_EN

DELAY

9

VREG_CPU_FBRTN

OUT OUT OUT

49

IN

15

ILIMIT

FB

VREG_CPU_VID<5..0>

5 4 3 2 1 0

X803045-001

C8U3

2

PWRGD

1

1

294K 1% CH 402

2

2

C8U1

.047UF 10% 16V X7R 603

1

2

R8U1

R8U4

324K 1% CH 603

205K 1% CH 402

1

2 1

OUT

51

C8U2

1000PF 10% 50V EMPTY 402

SHORT

2

VREG_CPU_CSSUM

V_CPUCORE

1 LAYOUT:ATTACH TO CLOSEST INDUCTOR 1

ST8F1 2

1

VREG_CPU_CSREF

10 402

SHORT

R8G3

2

1% CH

C7U2

1

R7U1

[PAGE_TITLE=VREGS,

1% CH

2

TARGET FSW=233KHZ

1000PF 10% 50V X7R 402

VREG_CPU_FB

2 1

1

N:

C8G1

0.1UF 10% 25V EMPTY 603

1.33K 603

1000PF 10% 50V X7R 402

VREG_CPU_CSREF_R

2 1

2

C7U4

1

C7U1

2

VREG_CPU_COMP_R

3000PF 10% 50V X7R 603

CPU CONTROLLER]

1 4.02K 402

R7U2

2

C7U3

360PF 10% 50V NPO 603

VREG_CPU_COMP

1% CH

DRAWING XENON_FABK Wed Aug 24 09:27:36

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 50/73

REV K7

50

51

50

49

IN

R9P2

1

V_VREG_CPU

2.2 805

2

1% CH

1 2

50

IN

50

VREG_CPU_DRV_EN

V_VREG_CPU

IN

3 VREG_CPU_BST3

1

1.0UF 10% 16V X7R 805

R9P1

1 U9P1 4 2 3 6

C9P3

2

D

0.01UF 10% 50V X7R 805

SOT23 DIO

C9P4

VREG_CPU_PWM3

IN

1

VREG_CPU3_VCC

49

2.2 805

IC

MOS DRIVER BST VCC DRVH IN OD_N* SW PGND DRVL

1 8 7 5

2

VREG_CPU_BST3_R

1% CH

C9P2

1

0.015UF

G

2

X801233-001

S

Q9D1

D

Q9D2 NTD60N02R DPAK

1

NTD60N02R DPAK

1 S

G

FET

2

FET

2

C9D3

10UF 20% 16V X5R 1206

1 2

C9D1

4.7UF 10% 16V X5R 1206

VREG_CPU_PHASE3

5% 16V X7R 805

V_CPUCORE 1

VREG_CPU_DRVH3

1 D

Q9C1

S

FET

D

Q8C1

S

FET

NTD85N02R DPAK

1 2

2

0.6UH 30A NA

IND TH

R9C1

3

G

NTD85N02R DPAK G

2

2.2 1% EMPTY 805

VREG_CPU_SW3_R

1

2.2 805

2

1

VREG_CPU2_VCC

1% CH

1 2

C9T3 1.0UF 10% 16V X7R 805

1

U9T1

3 6

C9T2

3

2

D

0.01UF 10% 50V X7R 805

R9T1

1

VREG_CPU_PWM2 2

IN

VREG_CPU_BST2

SOT23 DIO

4 50

2

2.2 805

IC

MOS DRIVER BST VCC DRVH IN OD_N* SW DRVL PGND

1 8 7 5

2

VREG_CPU_BST2_R

1% CH

C9T1

1

0.015UF

1

2

X801233-001

3 Q9E1 NTD60N02R DPAK

G

S

2

5% 16V X7R 805

Q9D4

D

NTD60N02R DPAK

1 S

G

FET

1 2

FET

2

C9D4 10UF 20% 16V X5R 1206

1 2

VREG_CPU_PHASE2

1

D

Q9E3

D

Q9D3

S

FET

NTD85N02R DPAK S

2

NTD85N02R DPAK G

FET

2

0.6UH 30A NA R9E1 2.2 1% EMPTY 805

IND TH

VREG_CPU_SW2_R

1% CH

2.2 805

2

1

VREG_CPU1_VCC

1 2

1.0UF 10% 16V X7R 805

R9U1

1

4

IN

1

SOT23 DIO

C9U3

U9U1

50

VREG_CPU_BST1

VREG_CPU_PWM1 2 3 6

MOS DRIVER BST VCC DRVH IN OD_N* SW PGND DRVL X801233-001

2.2 805

IC 1 8 7 5

1% CH

C9U2

2 2

3 D

0.01UF 10% 50V X7R 805

2

VREG_CPU_BST1_R

1

C9U1

0.015UF

2

5% 16V X7R 805

Q9F1 NTD60N02R DPAK

G

S

FET

Q9F4

D

NTD60N02R DPAK

1 S

G

FET

2

1 2

C9F4

10UF 20% 16V X5R 1206

1 2

4.7UF 10% 16V X5R 1206

VREG_CPU_PHASE1

1

2 IND TH

R9F1 D

Q9F2

D

Q8F1 NTD85N02R DPAK

NTD85N02R DPAK

2

2.2 1% EMPTY 805 VREG_CPU_SW1_R

S

FET

G

S

FET 1

PHASE

50

L8F1 0.6UH 30A NA

2

CPU OUTPUT

4700PF 10% 50V EMPTY 603

OUT

1

G

[PAGE_TITLE=VREGS,

C9E4

C9F1

VREG_CPU_DRVH1

VREG_CPU_BG1

R9U2

50

L8E1

1

1

4700PF 10% 50V EMPTY 603

OUT

1

G

D9F1 1N4148 3

C9C5

C9E1

4.7UF 10% 16V X5R 1206

VREG_CPU_DRVH2

VREG_CPU_BG2

R9T2

1

D9E1 1N4148 3

50

OUT

L8D1

VREG_CPU_BG3

51

D9C1 1N4148 3

1,2,3]

DRAWING XENON_FABK Wed Aug 24 09:27:37

2005

MICROSOFT CONFIDENTIAL

C9F3

4700PF 10% 50V EMPTY 603

PROJECT NAME XENON_RETAIL

PAGE 51/73

REV K7

53

52

49

V_VREG_GPU

IN

V_GPUCORE

53

52

49

IN

V_VREG_GPU

1

ST5R2 2

1

2

VREG_GPU_VID4

0 402 VREG_GPU_VID3

10000=1.150V

VREG_GPU_VID2

1 2

1

NA 10K

VREG_GPU_VFB_R

2

R8P7

1.1K 402

R8P9

2 1.21K 402

THRMSTR 603

1

2

1% CH

R8P4

2 5.11K 402

1

1.0UF 10% 16V X7R 805

C8P2

2

1 52

C8P1

4.02K 402

6800PF 10% 50V X7R 603

1

7.5K 603

C9P1

2

.047UF 10% 16V X7R 603

C8N5

1

2

V_GPUCORE

VFB

2

VDRP

32

COMP

CBOUT

21

VREG_GPU_SEN

10

NSEN

PGD

29

VREG_GPU_CS2

CS2 CS1

GH2 GL2

19 17

1

CSREF

GH1 GL1

22 24

VREG_GPU_ROSC

9

ROSC

28

CPGD

R8P5

VREG_GPU_CPGD

1

R8P6

2

42.2K 1% CH 603

27

1 2

1

1% CH

VREG_GPU_PHASE1

IN

VREG_GPU_COMP

5

2

52

VREG_GPU_5VREF

1

VREG_GPU_VDRP

6 4

1

7.5K 603

VREG_GPU_ILIM

VREG_GPU_VFB

VREG_GPU_CSREF

ST5R1 2

VREG_GPU_PHASE2

31 8

VCCH

VREG_GPU_CS1

SHORT

IN

ILIM 5VREF

VFFB

R8P2

2

VREG_GPU_VCCH

5VSB

7

2

7.5K 603

C8N4

0.01UF 10% 16V X7R 402

R8N10

1

COVC

LGND

3

GND2 GND1

18 23

R8N11

1

VREG_GPU_VID0

2 3

0 402

2

2

1

R8B2

2 2K 402

SHORT

2 1

1

C8B7

1

1

V_5P0STBY

1

R5N1

2

10K 5% CH 402

1

VREG_GPU_EN_N 1

IN

R9B1

10K 402

FTP

FT2P6

0.1UF 10% 25V X7R 603

Q8B3

FET 2N7002 2 SOT23

2

5% CH

VREG_GPU_PWRGD 1 VREG_GPU_GH2_R

1

R8N5

2

1A CH

2

1

750K 1% CH 603

1

R8N3

0 805 VREG_GPU_GL1_R

1A CH

FTP

1

2

34

VREG_GPU_GL2

OUT

53

OUT

53

OUT

53

OUT

53

1A CH

2

VREG_GPU_GH1 R8N4

1

OUT

FT2P3

VREG_GPU_GH2 R8N6

0 805 VREG_GPU_GH1_R

2

470PF 5% 50V

3 6.19K 1% CH 402

X800631-001

34

R8B3 1

D8B1 MMSZ18 SOD123 DIO

2

R8C1

0.1UF 10% 25V X7R 603

C8P4

C8B8 0.1UF 10% 25V X7R 603

52

C9B3

2

C9C2

1

1% CH

53

2

1% CH

VREG_GPU_GL2_R VREG_GPU_CSREF_R

0.1UF 10% 25V X7R 603

2

R8B4

7.5K 603

0.1UF 10% 25V X7R 603

OUT

1

C8N1

52

0 805

2

VREG_GPU_PHASE1

0.1UF 10% 25V X7R 603

1

C8P3

2

ST5D1

2 330 5% CH 805

2

1

1

VREG_GPU_NPNC

R8N2

OUT

1

C8B3

0.1UF 10% 25V BAV99 X7R 603 SOT23S DIO

1

5% CH

2

2

3 2

1

1% CH

V_GPUCORE

1

VREG_GPU_PHASE1_C

2

5% CH

R8N12

1

D8B2 1N4148 SOT23 DIO

5% CH

0 402

20

30

1% CH

10% 6800PF 50V X7R 603 1

VREG_GPU_VID1

15 14 13 12 11

VCCL

VREG_GPU_VFFB

1% CH

R8P1

1

VREG_GPU_COMP_C

2

R8P3

2

VREG_GPU_COMP_R

2

IC NCP5331

VCCL2 VCCL1

26

VREG_GPU_5VREF

IN

U8N1 16 25

VID4 VID3 VID2 VID1 VID0

1% CH

1000PF 10% 50V EMPTY 402 1

53

2

1.0UF 10% 16V X7R 805

D8B3 1

1

5% CH

0 402

C8N2

VREG_GPU_VCCL

1

1% CH

53

1

C8N3

R8N9

1

2

5% EMPTY

0 402

SHORT

RT7C1

R8N8

1

VREG_GPU_EN_N_R

R8N7 2.2 1% CH 805

0 805

2

VREG_GPU_GL1

1A CH

NPO 603

[PAGE_TITLE=VREGS,

GPU CONTROLLER]

DRAWING XENON_FABK Wed Aug 24 09:27:38

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 52/73

REV K7

52

49

V_VREG_GPU

IN

3 D

52

4.7UF 10% 16V X5R 1206

NTD60N02R DPAK

1

VREG_GPU_GH2

IN

C6B2 Q6B1

G

S

2

V_GPUCORE VREG_GPU_PHASE2

FET

OUT

52

L6C1 1 3

52

IN

3 Q6B2

D

NTD85N02R DPAK

1

VREG_GPU_GL2

G

S

2

1

R6B3

Q6C1 NTD85N02R DPAK

1 S

G

FET

2

2

2.2 1% CH 805

FET VREG_GPU_PH2_R

D

2 3

52

D

S

FET

4.7UF 10% 16V X5R 1206

NTD60N02R DPAK

1

VREG_GPU_GH1

IN

G

2

C6B4

4700PF 10% 50V X7R 603

C7B2

Q7B1

2 IND TH

0.6UH 30A NA

1

L7C1 1 3

52

IN

D

NTD85N02R DPAK

1

VREG_GPU_GL1

Q7B2

G

S

2

R7B6

Q7C1 NTD85N02R DPAK

1 G

FET

S

2

2

U1E1

IC

[PAGE_TITLE=VREGS,

3

IN

C8B6

4700PF 10% 50V X7R 603

1

ADJUST/GND X800499-001 DPAK 3.3V

V_1P8

IC

U2T1

NCP1117

1.0UF 10% 16V X7R 805

52

V_1P8

V_5P0

C1T6

OUT

FET

1

2

VREG_GPU_PHASE1

2.2 1% CH 805

2

1

IND TH

VREG_GPU_PH1_R

D

1

3

2

0.6UH 30A NA

NCP1117 OUT

2

V_V3P3TOV1P8

1 2

C2T5 0.1UF 10% 25V X7R 603

GPU OUTPUT PHASE 1,2]

3

IN

1

ADJUST/GND

1 C2E7

100UF 20% 16V

2 ELEC RDL

X800500-001 DPAK 1.8V

OUT

1

2

1 2

C2R4

0.1UF 10% 25V X7R 603

FTP

FT2R8

V_MEM R2T8

1 0 805

1 C2D6

100UF 20% 16V

R2T7

1

2 ELEC RDL

0 805

DRAWING XENON_FABK Wed Aug 24 09:27:39

2

1A EMPTY

2005

2

1A EMPTY

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 53/73

REV K7

R3V1

1

V_VREG_V1P8V5P0

IN

54

R3V7

1 54

IN

IN

2

C3V1

54 54

1

2

2

R2U1

1

2

1 VREG_5P0_PHASE_C

402 402

V_MEM

3

1% CH

R3V8

2

BAV99 SOT23S DIO

10 402

1

1.47K 402

2

1

2

330 5% CH 805

C4V2 1

R3V2

1

C4V3 0.1UF 10% 25V X7R 603

2

2

R4V3

54

2 1

V_5P0 R6U1

2 402 402

2

R6V3

1

2 10.7K 402

1

VREG_5P0_VFB1_C

1% CH

R6V1 1% CH

2

1

1% CH

C4V5

R3V5

2K 1% CH 402

10K 5% CH 402

ROSC

4

VREG_5P0_BST

GATEH2 GATEL2

20 19

GATEH1 GATEL1

1 2

NC<1> NC<0>

5 6

9

VFB1

13

VREF2

16

MODE

S

54 32

VREG_5P0_GATEL1

FET

1 2 R5F5 2.2 1% CH 805

1

NA TH

1 S

2 OUT OUT

1

VREG_V5P0_EN_N FTP

1

0.1UF 10% 25V X7R 603

AND V5P0]

54

C6U1 4.7UF 10% 16V X5R 1206

1 2

10K 402

R4G6 5% CH

2

3

3

2

2

1

Q4G1

1

1 10K

Q3G1 402

R3G5 5% CH

2

1

1 C2F3

1 C5F8

2 POLY RDL

2 ELEC RDL

820UF 20% 4V

820UF 20% 4V

VREG_5P0_PHASE VREG_5P0_IS1P R4G1

1 12.1K 402

1

2

0 1A CH 805

C4G1

220UF 20% 10V

R4G2

16.9K 402

Q6F2 NTD60N02R DPAK

1 G

S

2

1

FET

10K 5% CH 402

VREG_V1P8_EN_N 1

IN

34

2

FT2P19

FET SOT23 2N7002

1

DRAWING XENON_FABK Wed Aug 24 09:27:39

2

FTP

FT6V1

V_5P0

1% CH

DB6G1 TP

1

NA TH

R6G1 3 D

1

2

4.0UH 12A

54 54

OUT OUT

1

0.1UF 10% 25V X7R 603

1

2

VREG_5P0_GATEL1_R

FTP

2

1% CH

FET 1

R3G1

1

1 C3F2 POLY 2 RDL

C6F7

4.7UF 10% 16V X5R 1206

Q6F1

R5F6

2

VREG_V1P8_EN_N_R

C3U6

C3V7

2

54

V_3P3STBY

VREG_V5P0_EN_N_R

TP

10UF 10% 6.3V X5R 1206

2

L6F1

10K 5% CH 402

1

NTD60N02R DPAK G

VREG_V1P8_EN

DB3F1

4700PF 10% 50V X7R 603

3 D

VREG_5P0_GATEH1_R

VREG_V5P0_EN

V_MEM

2

1% CH

V_VREG_V1P8V5P0

IN

2

51.1K 1% EMPTY 402

FT2U1

VREG_1P8_GATEL2 VREG_5P0_GATEH1

X800762-001

R4V2

1

FTP

1

2.2 1% CH 805

2

GND

FET 2N7002 SOT23

V1P8

NTD60N02R DPAK

1

1

VREG_1P8_GATEH2

2

FT2P18

C3V3

Q2G1

D

COMP1 IS+1 IS-1

2

4.0UH 12A

1

BST

7 8

54

OUT

1

R3V6

15.4K 402

R2V2 3

0 1A CH 805

1

R4G3

IN

1

2

2

34

[PAGE_TITLE=VREGS,

VFB2

17

VREG_5P0_VREF2

2

C3V2

0.1UF 10% 25V X7R 603

1

R3V9

V_3P3STBY

R6V2

2

12

VREG_1P8_ROSC

VREG_5P0_VFB1

2

1

VREG_1P8_VFB2

VREG_5P0_IS1M

220NF 10% 10V X7R 603

2

1% CH

FET

2

2.2 1% CH 805

IS+2 IS-2

3

1

2

1

COMP2

VREG_5P0_IS1P

IN

4700PF 10% 50V X7R 603

1

11

1

V_5P0

5.36K 402

VCC

10

2

1% CH

VREG_V5P0_EN_R

D4V1 MMSZ18 SOD123 DIO

C6V1

1% CH

13.3K 402

VREG_1P8_OUT

IC

18

VREG_1P8_IS2M

VREG_V5P0_EN 1

1

1

R3V4

1

R3U2

14 15

VREG_1P8_IS2P

22.1K 402

43.2 402

S

2

VREG_1P8_GATEL2_R

1.07K 1% CH 402

VREG_1P8_IS2P

L2F1

G

2

IN

G

NCP5425

1

54

1

VREG_1P8_GATEH2_R

18.7K 1% EMPTY 402

R3G7

C3F6

4.7UF 10% 16V X5R 1206

2

NTD60N02R DPAK

2

R4V1 0.1UF 10% 25V X7R 603

2

1500UF 20% 16V ALUM RDL

1

2

1

Q3F1

D

1 C7F2

2

U4V1

1% CH

54

C3U5

4.7UF 10% 16V X5R 1206

3 1500UF 20% 16V ALUM RDL

1

2

1

32

OUT

R3V3

4700PF 10% 50V X7R 603

R3G6

2

VREG_5P0_BST_R

C3V6

1

1% CH

V_VREG_V1P8V5P0

2

VREG_1P8_VFB2_C

2

2 NA TH

VREG_1P8_IS2P

IN

V_MEM D4V2

1 1.6UH 10A

C6F3

C4V4 0.1UF 10% 25V X7R 603

2

L7F1

1.0UF 10% 16V X7R 805

470NF 10% 10V X7R 603

VREG_5P0_PHASE

2

C3V4

1

VREG_V1P8_EN_R

1% CH

V_VREG_V1P8V5P0

IN

1 1

V_VREG_V1P8V5P0_R

54

10 603

V_VREG_V1P8V5P0

54

32

V_12P0

VREG_V1P8_EN

IN 32

2

1% CH

2.2 805

VREG_1P8_OUT_R

54

1

2.2 1% CH 805

2

C7V2

10UF 10% 6.3V EMPTY 1206

C6G1

10UF 10% 6.3V X5R 1206

1 C7F1

2200UF 20% 6.3V

ALUM 2 RDL

VREG_5P0_OUT_R

32

2005

C5G2

4700PF 10% 50V X7R 603

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 54/73

REV K7

V_5P0

IN

1K 5% CH 402

3

ENABLE

1

R1F8

1K 402

2

1 VREG_3P3_EN_N_R

5% CH

2

1

V_3P3

Q2F2

U1F1

VREG_V3P3_IN

1

VREG_3P3_EN_N

VIN

3

2 SOT23 NTR2101P FET

1

R1F7

34

2

C1U1

IC NCP1086

3

IN

TAB

4

1

GND

OUT

2

1.0UF 10% 16V X7R 805

1 1

X800498-001 3.3V

2

FTP

2

FT1U1

1 C1F3

C1F5

100UF 20% 16V

0.1UF 10% 25V X7R 603

R7T10

R6T3

10K 5% CH 402

10K 5% CH 402

2

2 ELEC RDL

C7T100

VOUT

5

GND

2

NC

4

X803461-001 SOT23_5 3.5V

1UF 10% 50V X7R 603

V_EFUSE

U6T1

IC NCP502D

VREG_EFUSE_EN_C2

1

VIN

3

ENABLE

VOUT

5

GND

2

NC

4

1

C7T98

3

4

IN

FT7T8

U5B1

IC

1

IN

1

ADJUST/GND

C5B3

1

2

OUT

1

X800499-001 DPAK 3.3V

1.0UF 10% 16V X7R 805

2

1

FTP

2

0.1UF 10% 25V X7R 603

2

1

4

FTP

1

FT5N1

2

3

IN

1

ADJUST/GND

C5B5

1.0UF 10% 16V X7R 805

1

2

OUT

3

1

X800500-001 DPAK 1.8V

2

FTP

FT5N2

1 C5B4

C5B6 0.1UF 10% 25V X7R 603

1

2

BAV99 SOT23S EMPTY

3

IN

1

ADJUST/GND

C4C6

2

1 3

1

2

C2C5 1.0UF 10% 16V X7R 805

IN ADJUST/GND

4

1 1

X800501-001 SOT223 1.2V

2

1

R3C22

R3C21

499 1% CH 402

1 1% CH 0402

2

VREG_VDD_PEX_ADJ

1

1 2

R2C3

C2C6 .1UF 10% 6.3V X5R 402

2

243 1% CH 402

1 2

[PAGE_TITLE=[VREGS,

LINEAR

VREGS]

2

FTP

FT2P26

R6C1

0 805

1A EMPTY

V_1P8

2

OUT OUT/TAB

R5C6

1K 1% CH 402

1 1% CH 0402

2

2

0 5% CH 402

1

2

1A CH

1 0 805

R5C4

2

VREG_CPUPLL_IN

1A CH

1 2

C6P1 1.0UF 10% 16V X7R 805

FTP

FT5R1

C5C5 4.7UF 10% 6.3V X5R 805

V_CPUPLL EMPTY

U6R1

N:

NCP1117 3

IN

1

ADJUST/GND

TARGET IS

1 1

4

X800501-001 SOT223 1.8V

2

R6R3

R6R1

499 1% EMPTY 402

1 1% CH 0402

C3C1

2

4.7UF 10% 6.3V X5R 805

1

R6R2

C6R1

.1UF 10% 6.3V EMPTY 402

2

374 1% EMPTY 402

2

1 2

DRAWING XENON_FABK Wed Aug 24 09:27:40

2005

FTP

FT7R3

1

VREG_CPUPLL_ADJUST

1

2.20V

2

OUT OUT/TAB

VREG_VDD_PEX_R

1

3

R5C9

2

0 805

1.87V

NCP1117 1

R5P2

BAV99 SOT23S EMPTY

V_SBPCIE TARGET IS

.1UF 10% 6.3V X5R 402

2

1 1

R5P1

C5P1

2

V_3P3 N:

1.25V

1

CR4P2 1

1

IC

TARGET IS 1

4

X800501-001 SOT223 1.2V

1.0UF 10% 16V X7R 805

2

V_3P3

U3P1

N: 2

OUT OUT/TAB

VREG_PCIEX_ADJUST

V_1P8STBY

100UF 20% 16V ELEC RDL

IC NCP1117

1

V3P3STBY_V1P8STBY_D

1

V_GPUPCIE U5C1

CR4N1

100UF 20% 16V ELEC RDL

IC NCP1117

XSTR

V_3P3

V_3P3STBY

V_1P8STBY U5B2

1

10K 5% CH 402

2

V_5P0STBY

X800489-002 SC70 3.5V

2

5

VREG_EFUSE_EN_R

5% CH

R6T1

1 C5B2

C5B1

R6T4

2

V_3P3STBY

NCP1117 3

1K 402

1UF 10% 50V EMPTY 603

VREG_PCIEX_R

V_5P0STBY

2

VREG_EFUSE_EN

6

FT7T6

C7T99

1UF 10% 50V X7R 603

CR6T1 MBT3904

FTP

VREG_CPUPLL_R

1

LP2980

1A EMPTY

VREG_EFUSE_EN_C1

0 805

V_5P0 1

R2F2

1

V_5P0

2

EMPTY

U6T2

V_5P0

MICROSOFT CONFIDENTIAL

C7P1 4.7UF 10% 6.3V X5R 805

PROJECT NAME XENON_RETAIL

PAGE 55/73

REV K7

XDK,

DEBUG CONNECTORS V_5P0DUAL

OUT IN

SPI_SS_N SPI_MISO

KER_DBG_RXD SPI_MOSI SPI_CLK

1 3 5 7 9

35 35

OUT OUT

J1F1 1X6HDR

1

C1D7

EMPTY

34

2

KER_DBG_TXD SMC_DBG_TXD SMC_DBG_EN

IN IN OUT

J2B1 2X7HDR_14 2 4 6 8 10 12

C1R2

1 3 5 7 9 11 13

C3B5

28

34

BI

28

IN

34

46

34 34 34 34

13

IN IN IN IN

DBG_LED0 DBG_LED1 DBG_LED2 DBG_LED3

SMB_CLK

1

100 402

2

SMB_DATA

28

BI

34

46

V_12P0

5% CH

R2B7

1

EXT_PWR_ON_DBG

1K 402

5% CH

1UF 10% 50V X7R 603

R2N14

1

SMB_DATA_R

R2N13 2

100 402

C2B15

.1UF 10% 6.3V X5R 402

EMPTY 46

SMC_RST_N

1 2 3 4 5 6 EMPTY TH

SMB_CLK_R

.1UF 10% 6.3V X5R 402

2

5% CH

V_3P3STBY

V_3P3 33 34

R2P18

100 402

.1UF 10% 6.3V X5R 402

1

33

OUT

V_5P0STBY

SMC_RST_XDK_N

35 35

J1D2 2X5HDR_10 2 4 6 8

2

EXT_PWR_ON_N

43

OUT

56

34

5% CH 1

V_5P0STBY

D8B4 GREEN SM EMPTY

2

1 2 V_12P0

1

C2B12

C2B13

.1UF 10% 6.3V X5R 402

R8B6

1UF 10% 50V X7R 603

2

V_5P0STBY R7V7

0 805

R7V6

1

2

0 805

3

1

J9A2 1X2HDR

1A EMPTY

2

1A EMPTY

1K 402

1 2 V_GPUFAN

1

V_5P0

SM EMPTY

2

4.7UF 10% 16V EMPTY 805

1 2

C7G4

1

EMPTY

0.01UF 10% 16V EMPTY 402

Q8B6

1

MMBT2222 EMPTY

2

2

2

2

R8C3

R8C4

R8C5

R8C6

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

10K 5% EMPTY 402

1

1

1

1 2

2

R8P8

C8P5

.1UF 10% 6.3V X5R 402

1

10K 5% CH 402

J8C1 2X5HDR 4

CPU_RST_V1P1_N

IN 57 57 57 57

OUT OUT IN OUT

CPU_TMS CPU_TRST_N CPU_TDO CPU_TDI FT7R7

FTP

1

R8C2

2 1K 402

DEBUG CONN]

1

5% CH

CPU_RST_N_2_R

2 4 6 8 10

CPU_CHECKSTOP_N

1 3 5 7 9

CPU_TCLK EXT_PWR_ON_N

57

IN OUT OUT

57 43

56

34

EMPTY 1 2

[PAGE_TITLE=XDK.

2

5% EMPTY

V_1P8

2

C7G3

R8A5

V_1P8

C9A3

.1UF 10% 6.3V X5R 402

J7G1 1X3HDR 1 2 3

1

2K 1% EMPTY 402

C7D23

.1UF 10% 6.3V EMPTY 402

DRAWING XENON_FABK Wed Aug 24 09:26:59

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 56/73

REV K7

V_GPUCORE U4D1

7 OF 8 GPU VERSION

DEBUG BOARD,

CPU + GPU DEBUG BREAKOUT]

IC

U7D1

57 E25 D29 G30 F32

TBCLK3 TBCLK2 TBCLK1 TBCLK0

56 56 56 56

G21 G22 F22 G23 D23 G24 E23 E24 D24 G25 G26 E26 D26 E27 D27 E28 D28 H29 E29 H30 C30 B30 A30 G31 B31 A31 B32 A32 F33 E33 D33 E34

TB31 TB30 TB29 TB28 TB27 TB26 TB25 TB24 TB23 TB22 TB21 TB20 TB19 TB18 TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

IN IN IN IN

CPU_TCLK CPU_TDI CPU_TMS CPU_TRST_N

AH7 AK8 AK4 AK7

2

C6T35

.1UF 10% 6.3V X5R 402

1 2

C7T90 .1UF 10% 6.3V X5R 402

1 2

C6T36

.1UF 10% 6.3V X5R 402

1 2

C7T91

.1UF 10% 6.3V X5R 402

V_GPUCORE

1 2

C7T89 .1UF 10% 6.3V X5R 402

1 2

C6T34 .1UF 10% 6.3V X5R 402

1 2

C7T92 .1UF 10% 6.3V X5R 402

1 2

C6T31 .1UF 10% 6.3V X5R 402

X02056-010

TP7A1 EMPTY TDRX4

TP7M2 EMPTY TDRX2 1 2

TDR_SINGLE_XDK2

TDR_DIFF_XDK2_DP

SIG GND

TDR_DIFF_XDK2_DN

1 2 3 4

SIG GND

TP8A2 EMPTY TDRX2 1 2

TDR_SINGLE_XDK1

SIG GND

1 2 3 4

TP8A1 EMPTY TDRX2

[PAGE_TITLE=DEBUG

SIG GND

BOARD,

DP GND DN GND

TP8M1 EMPTY TDRX4 TDR_DIFF_XDK1_DP TDR_DIFF_XDK1_DN

1 2

DP GND DN GND

TP7A2 EMPTY TDRX4

TP7M1 EMPTY TDRX2 1 2

1 2 3 4

DP GND DN GND

TP8M2 EMPTY TDRX4 1 2 3 4

IC 20 TDO CHECKSTOP_B

CPU_TDO CPU_CHECKSTOP_N

AJ7 AK2 E25 F25

DEBUG_CLKOUT_DP DEBUG_CLKOUT_DN

C7 F13 B7 A7 A8 A9 C10 B10 A10 E11 E12 E13 A11 F15 E14 D12 A12 D14 E15 C13 B13 E16 A13 A14 A15 D16 C16 B16 E17 F17 A17 A16 A18 E18 A19 D18 B19 A20 C19 A21 E19 D20 F19 A22 B22 E20 A23 C22 A24 A25 E21 D22 A26 B25 F21 E22 A27 A28 C25 D24 A29 E23 A30 B28 C29 F23 B30 E24 C28 C30

DEBUG_OUT0 DEBUG_OUT1 DEBUG_OUT2 DEBUG_OUT3 DEBUG_OUT4 DEBUG_OUT5 DEBUG_OUT6 DEBUG_OUT7 DEBUG_OUT8 DEBUG_OUT9 DEBUG_OUT10 DEBUG_OUT11 DEBUG_OUT12 DEBUG_OUT13 DEBUG_OUT14 DEBUG_OUT15 DEBUG_OUT16 DEBUG_OUT17 DEBUG_OUT18 DEBUG_OUT19 DEBUG_OUT20 DEBUG_OUT21 DEBUG_OUT22 DEBUG_OUT23 DEBUG_OUT24 DEBUG_OUT25 DEBUG_OUT26 DEBUG_OUT27 DEBUG_OUT28 DEBUG_OUT29 DEBUG_OUT30 DEBUG_OUT31 DEBUG_OUT32 DEBUG_OUT33 DEBUG_OUT34 DEBUG_OUT35 DEBUG_OUT36 DEBUG_OUT37 DEBUG_OUT38 DEBUG_OUT39 DEBUG_OUT40 DEBUG_OUT41 DEBUG_OUT42 DEBUG_OUT43 DEBUG_OUT44 DEBUG_OUT45 DEBUG_OUT46 DEBUG_OUT47 DEBUG_OUT48 DEBUG_OUT49 DEBUG_OUT50 DEBUG_OUT51 DEBUG_OUT52 DEBUG_OUT53 DEBUG_OUT54 DEBUG_OUT55 DEBUG_OUT56 DEBUG_OUT57 DEBUG_OUT58 DEBUG_OUT59 DEBUG_OUT60 DEBUG_OUT61 DEBUG_OUT62 DEBUG_OUT63 DEBUG_OUT64 DEBUG_OUT65 DEBUG_OUT66 DEBUG_OUT67 DEBUG_OUT68 DEBUG_OUT69

V_GPUCORE

1

3 OF 10 CPU VERSION

TCLK TDI TMS TRST_B

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

OUT OUT CPU_DBG_CLK_DP OUT CPU_DBG_CLK_DN OUT CPU_DBGSEL_XDK<0..69>

56 56

OUT

31

N:CPU_DBGSEL_DEBUG<0..69> N:CPU_DBGSEL_XDK<0..69>

X02046-002

DP GND DN GND

CPU + GPU DEBUG BREAKOUT]

DRAWING XENON_FABK Wed Aug 24 09:27:41

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 57/73

REV K7

INTELLIGENT

SERIAL

NUMBER TARGET.

LB7G1

1

LABEL

1375X250_TARGET X801181-001

WEST PCB MOUNTING HOLES

MIDDLE

EAST PCB MOUNTING HOLES EDGE MTG9G1 MTG_HOLE 9 NC9

EMPTY GND=1,2,3,4,5,6,7,8 EDGE MTG1G1 MTG_HOLE 9 NC9

EMPTY GND=1,2,3,4,5,6,7,8 CTR MTG5B1 MTG_HOLE 9 NC9

EMPTY GND=1,2,3,4,5,6,7,8 EDGE MTG9B1 MTG_HOLE 9 NC9

EMPTY GND=1,2,3,4,5,6,7,8

EMPTY GND=1,2,3,4,5,6,7,8

EMPTY GND=1,2,3,4,5,6,7,8

HEAT SINK STD MTG8C1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8 STD MTG3C1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8 STD MTG6C1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8

STD MTG5C1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8

[PAGE_TITLE=LABELS

PCB MOUNTING HOLES CTR MTG5G1 MTG_HOLE 9 NC9

EDGE MTG1B1 MTG_HOLE 9 NC9

AND MOUNTING]

MOUNTING HOLES STD MTG6E1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8 STD MTG3E1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8 STD MTG8E1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8

STD MTG5E1 MTG_HOLE 9 NC9 EMPTY GND=1,2,3,4,5,6,7,8

DRAWING XENON_FABK Wed Aug 24 09:27:41

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 64/73

REV K7

***

Signal

Cross-Reference

ANA_CLK_OE

for

34B3>

28C8<

the 46B7<

entire

design

***

ENET_RX_DP

19B3>

39D1<>

44B5<

FSB_GP_CP0_FLAG_DP

MA_DQ11

14C8<>

20B5<>

21B5<>

ENET_TX_DN

19B3>

39A1<>

44B5<

FSB_GP_CP1_CLK_DN

12C4>

5C7<

MA_DQ12

14C8<>

20B5<>

21B5<>

ENET_TX_DP

19B3>

39C1<>

44B5<

FSB_GP_CP1_CLK_DP

12C4>

5C7<

MA_DQ13

14C8<>

20B5<>

21B5<>

12C4>

5C7<

ANA_PIX_CLK_2X_DN

28B1>

13C8<

EXPPORT_DN

35B4<>

44C8<>

FSB_GP_CP1_DATA0_DN

12B4>

5B7<

MA_DQ14

14C8<>

20B5<>

21B5<>

ANA_PIX_CLK_2X_DP

28B1>

13C8<

EXPPORT_DP

35B4<>

44C8<>

FSB_GP_CP1_DATA0_DP

12B4>

5B7<

MA_DQ15

14C8<>

20C5<>

21B5<>

EXT_PWR_ON_N

43C1>

56A1>

FSB_GP_CP1_DATA1_DN

12B4>

5B7<

MA_DQ16

14C8<>

20C5<>

21C5<>

FAN1_FDBK

42C2>

29C6<

FSB_GP_CP1_DATA1_DP

12B4>

5B7<

MA_DQ17

14C8<>

20C5<>

21C5<>

ANA_RST_N

34C3>

28D7<

ANA_V12P0_PWRGD

28D3>

34C3<

ANA_VDD_DAC18S

30D5>

30A5<

FAN1_OUT

29C3>

42D5<

FSB_GP_CP1_DATA2_DN

12B4>

5B7<

MA_DQ18

14C8<>

20C5<>

21C5<>

ANA_VID_INT

29D3>

33B2<

FAN2_FDBK

42A2>

29C6<

FSB_GP_CP1_DATA2_DP

12B4>

5B7<

MA_DQ19

14C8<>

20C5<>

21C5<>

ANA_XTAL_IN

46D2>

28C7<

FAN2_OUT

29C3>

42B4<

FSB_GP_CP1_DATA3_DN

12B4>

5B7<

MA_DQ20

14C8<>

20C5<>

21C5<>

ARGONPORT_DN

35B4<>

48C8<>

FLSH_ALE

35C4>

41B5<

FSB_GP_CP1_DATA3_DP

12B4>

5B7<

MA_DQ21

14C8<>

20C5<>

21C5<>

ARGONPORT_DP

35B4<>

48C8<>

FLSH_CE_N

35C4>

41B5<

FSB_GP_CP1_DATA4_DN

12B4>

5B7<

MA_DQ22

14C8<>

20C5<>

21D5<>

ARGON_CLK

34A1<>

48A7<>

FLSH_CLE

35C4>

41B5<

FSB_GP_CP1_DATA4_DP

12B4>

5B7<

MA_DQ23

14C8<>

20C5<>

21D5<>

ARGON_DATA

34A1<>

48A7<>

FLSH_DATA<7..0>

35C8<>

FSB_GP_CP1_DATA5_DN

12B4>

5B7<

MA_DQ24

14D8<>

20C5<>

21C5<>

ARGON_NTX

48A6>

44B7<

FLSH_READY

41C1>

35C8<

FSB_GP_CP1_DATA5_DP

12B4>

5B7<

MA_DQ25

14D8<>

20C5<>

21C5<>

AUD_CLAMP

34C6>

40A6<

FLSH_RE_N

35C4>

41B5<

FSB_GP_CP1_DATA6_DN

12B4>

5B7<

MA_DQ26

14D8<>

20C5<>

21C5<>

AUD_CLK

28B1>

36C6<

FLSH_WE_N

35C4>

41B5<

FSB_GP_CP1_DATA6_DP

12B4>

5B7<

MA_DQ27

14D8<>

20C5<>

21C5<>

AUD_L_OUT

40C1>

43B4<

FLSH_WP_N

35C8>

41B5<

FSB_GP_CP1_DATA7_DN

12B4>

5B7<

MA_DQ28

14D8<>

20C5<>

21C5<>

AUD_RST_N

33B2>

40C8<

FSB_CP_GP0_CLK_DN

5D3>

12D8<

FSB_GP_CP1_DATA7_DP

12B4>

5B7<

MA_DQ29

14D8<>

20C5<>

21C5<>

AUD_R_OUT

40C1>

43B4<

FSB_CP_GP0_CLK_DP

5D3>

12D8<

FSB_GP_CP1_FLAG_DN

12B4>

5B7<

MA_DQ30

14D8<>

20D5<>

AV_MODE0

43B1>

34B8<

43A3<

FSB_CP_GP0_DATA0_DN

5C3>

12C8<

FSB_GP_CP1_FLAG_DP

12C4>

5B7<

MA_DQ31

14D8<>

20D5<>

AV_MODE1

43B1>

34B8<

43A3<

FSB_CP_GP0_DATA0_DP

5C3>

12C8<

GAMEPORT1_DN

35B7<>

45A8<>

MA_RAS_N

14B5>

20B8<

21B8<

AV_MODE2

43B1>

34B8<

43A3<

FSB_CP_GP0_DATA1_DN

5C3>

12C8<

GAMEPORT1_DP

35B7<>

45A8<>

MA_RDQS0

20B5>

21B5>

14B8<

BINDSW_N

42D6>

34B3<

FSB_CP_GP0_DATA1_DP

5C3>

12C8<

GAMEPORT2_DN

35B7<>

45C8<>

MA_RDQS1

20B5>

21B5>

14C8<

BRD_TEMP_N

29A7>

29A8<

FSB_CP_GP0_DATA2_DN

5C3>

12C8<

GAMEPORT2_DP

35B7<>

45C8<>

MA_RDQS2

20C5>

21C5>

BRD_TEMP_P

29B1>

29A7<

FSB_CP_GP0_DATA2_DP

5C3>

12C8<

GPU_CLK_DN

46C1>

13D7<

MA_RDQS3

20C5>

21C5>

14D8<

CAL_TEMP_N

29B1>

29A8<

FSB_CP_GP0_DATA3_DN

5C3>

12C8<

GPU_CLK_DP

46C1>

13D7<

MA_WDQS0

14B8>

20B5<

21B5<

CPU_ANL_1

4C5>

FSB_CP_GP0_DATA3_DP

5C3>

12C8<

GPU_HSYNC_OUT

13C4>

29C6<

MA_WDQS1

14C8>

20B5<

21B5<

CPU_CHECKSTOP_N

57D1>

56A1<

FSB_CP_GP0_DATA4_DN

5C3>

12C8<

GPU_PIX_CLK_1X

13C3>

29D6<

MA_WDQS2

14C8>

20C5<

21C5<

CPU_CLK_DN

46D1>

4D6<

FSB_CP_GP0_DATA4_DP

5C3>

12C8<

GPU_RST_DONE

13D3>

34C1<

MA_WDQS3

14D8>

20C5<

21C5<

CPU_CLK_DP

46D1>

4D6<

FSB_CP_GP0_DATA5_DN

5C3>

12C8<

GPU_RST_N

34B3>

13D8<

MA_WE_N

14B5>

20B8<

21B8<

FSB_CP_GP0_DATA5_DP

5C3>

12C8<

GPU_SCAN_BUFF_EN_N

MB_A<11..0>

22C8<

23C8<

FSB_CP_GP0_DATA6_DN

5C3>

12C8<

GPU_SPI_CLK

13B3>

13A7<

MB_A<12..0>

14C1>

FSB_CP_GP0_DATA6_DP

13B3>

13A7<

CPU_DBGSEL_DEBUG<0..69> CPU_DBGSEL_XDK<0..69>

48A5<

31D8< 57D1>

CPU_DBG_CLK_DN

57D1>

CPU_DBG_CLK_DP

57D1>

31D4<

56C3>

41C8<

34C8<

43A3<

13A7>

12A3<

5C3>

12C8<

GPU_SPI_CS_N

FSB_CP_GP0_DATA7_DN

5C3>

12C8<

GPU_SPI_SI

13A2>

13B4>

CPU_FSB_HF_CLKOUT_DN

4C2>

FSB_CP_GP0_DATA7_DP

5C3>

12C8<

GPU_SPI_SO

13C3>

13A7<

CPU_FSB_HF_CLKOUT_DP

4C2>

FSB_CP_GP0_FLAG_DN

12C8<

GPU_SPI_WP_N

12C8<

5C3>

13C7<

21C5<> 21C5<>

14C8<

MB_BA<2..0>

14C1>

22B8<

23B8<

MB_CAS_N

14B1>

22B8<

23B8<

MB_CKE

14B1>

22B8<

23B8<

13B4>

13A4<

MB_CLK0_DN

14C1>

22C8<

CPU_PWRGD

34B3>

4D8<

FSB_CP_GP0_FLAG_DP

GPU_TEMP_N

13C8>

29B8<

MB_CLK0_DP

14C1>

22D8<

CPU_RST_N

34B3>

4D8<

FSB_CP_GP1_CLK_DN

5C3>

12C8<

GPU_TEMP_P

29B1>

13C8<

MB_CLK1_DN

14C1>

CPU_RST_V1P1_N

4D7>

56A5<

FSB_CP_GP1_CLK_DP

5C3>

12C8<

GPU_VSYNC_OUT

13C4>

29C6<

MB_CLK1_DP

14C1>

23D8<

CPU_SPI_CLK

4B1>

4A5<

FSB_CP_GP1_DATA0_DN

5B3>

12B8<

HDD_RX_DN

47C8>

36B6<

MB_CS0_N

14B1>

22B8<

CPU_SPI_EN

4B2>

4A6<

FSB_CP_GP1_DATA0_DP

5B3>

12B8<

HDD_RX_DP

47B8>

36B6<

MB_CS1_N

14B1>

23B8<

CPU_SPI_SI

4A1>

4B3>

FSB_CP_GP1_DATA1_DN

5B3>

12B8<

HDD_TX_DN

36B3>

47D8<

MB_DM0

14B4>

22B5<

23B5<

CPU_SPI_SO

4B2>

4A5<

FSB_CP_GP1_DATA1_DP

5B3>

12B8<

HDD_TX_DP

36B3>

47D8<

MB_DM1

14C4>

22B5<

23B5<

CPU_SPI_WP_N

4A3>

4A2<

FSB_CP_GP1_DATA2_DN

5B3>

12B8<

I2S_BCLK

36C1>

40C7<

MB_DM2

14C4>

22C5<

23C5<

CPU_TCLK

56A1>

57D5<

FSB_CP_GP1_DATA2_DP

5B3>

12B8<

I2S_MCLK

36C1>

40C7<

MB_DM3

14D4>

22C5<

23C5<

CPU_TDI

56A5>

57D5<

FSB_CP_GP1_DATA3_DN

5B3>

12B8<

I2S_SD

36C1>

40C7<

MB_DQ0

14B4<>

22B5<>

23B5<>

CPU_TDO

57D1>

56A5<

FSB_CP_GP1_DATA3_DP

5B3>

12B8<

I2S_WS

36C1>

40C7<

MB_DQ1

14B4<>

22B5<>

23B5<>

CPU_TEMP_N

4B2>

29B8<

FSB_CP_GP1_DATA4_DN

5B3>

12B8<

IR_DATA

42A5>

34B6<

MB_DQ2

14B4<>

22B5<>

23B5<>

CPU_TEMP_P

29B1>

4B2<

FSB_CP_GP1_DATA4_DP

5B3>

12B8<

KER_DBG_RXD

56D4>

33C6<

MB_DQ3

14B4<>

22B5<>

23B5<>

CPU_TMS

56A5>

57D5<

FSB_CP_GP1_DATA5_DN

5B3>

12B8<

KER_DBG_TXD

33C1>

56C6<

MB_DQ4

14B4<>

22B5<>

23B5<>

CPU_TRST_N

56A5>

57D5<

FSB_CP_GP1_DATA5_DP

5B3>

12B8<

MA_A<11..0>

20C8<

21C8<

MB_DQ5

14B4<>

22B5<>

23B5<>

CPU_VREG_APS0

4B2>

49C7<

FSB_CP_GP1_DATA6_DN

5B3>

12B8<

MA_A<12..0>

14C5>

MB_DQ6

14B4<>

22B5<>

23B5<>

CPU_VREG_APS1

4B2>

49D7<

FSB_CP_GP1_DATA6_DP

5B3>

12B8<

MA_BA<2..0>

14C5>

20B8<

21B8<

MB_DQ7

14B4<>

22B5<>

23B5<>

CPU_VREG_APS2

4B2>

49D7<

FSB_CP_GP1_DATA7_DN

5B3>

12B8<

MA_CAS_N

14B5>

20B8<

21B8<

MB_DQ8

14C4<>

22B5<>

23B5<>

CPU_VREG_APS3

4B2>

49D7<

FSB_CP_GP1_DATA7_DP

5B3>

12B8<

MA_CKE

14B5>

20B8<

21B8<

MB_DQ9

14C4<>

22B5<>

23B5<>

CPU_VREG_APS4

4B2>

49D7<

FSB_CP_GP1_FLAG_DN

5B3>

12B8<

MA_CLK0_DN

14C5>

20C8<

MB_DQ10

14C4<>

22B5<>

23B5<>

CPU_VREG_APS5

4B2>

49D7<

FSB_CP_GP1_FLAG_DP

5B3>

12C8<

MA_CLK0_DP

14C5>

20D8<

MB_DQ11

14C4<>

22B5<>

23B5<>

DBG_LED0

34A8<>

56D3<

FSB_GP_CP0_CLK_DN

12D4>

5D7<

MA_CLK1_DN

14C5>

21C8<

MB_DQ12

14C4<>

22B5<>

23B5<>

DBG_LED1

34B8<>

56D3<

FSB_GP_CP0_CLK_DP

12D4>

5D7<

MA_CLK1_DP

14C5>

21D8<

MB_DQ13

14C4<>

22B5<>

23B5<>

DBG_LED2

34B8<>

56D3<

FSB_GP_CP0_DATA0_DN

12C4>

5C7<

MA_CS0_N

14B5>

20B8<

MB_DQ14

14C4<>

22B5<>

23B5<>

DBG_LED3

34B8<>

13C7<

FSB_GP_CP0_DATA0_DP

12C4>

5C7<

MA_CS1_N

14B5>

21B8<

MB_DQ15

14C4<>

22B5<>

23B5<>

DDC_CLK

35A1<>

43C1<>

FSB_GP_CP0_DATA1_DN

12C4>

5C7<

MA_DM0

14B8>

20B5<

21B5<

MB_DQ16

14C4<>

22C5<>

23C5<>

DDC_CLK_OUT

34C8<>

35A5<>

FSB_GP_CP0_DATA1_DP

12C4>

5C7<

MA_DM1

14C8>

20B5<

21B5<

MB_DQ17

14C4<>

22C5<>

23C5<>

DDC_DATA

35B1<>

43C1<>

FSB_GP_CP0_DATA2_DN

12C4>

5C7<

MA_DM2

14C8>

20C5<

21C5<

MB_DQ18

14C4<>

22C5<>

23C5<>

DDC_DATA_OUT

34C8<>

35B5<>

FSB_GP_CP0_DATA2_DP

12C4>

5C7<

MA_DM3

14D8>

20C5<

21C5<

MB_DQ19

14C4<>

22C5<>

23C5<>

EDRAM_TEMP_N

13C8>

29A8<

FSB_GP_CP0_DATA3_DN

12C4>

5C7<

MA_DQ0

14B8<>

20B5<>

21B5<>

MB_DQ20

14C4<>

22C5<>

23C5<>

EDRAM_TEMP_P

29B1>

13C8<

FSB_GP_CP0_DATA3_DP

12C4>

5C7<

MA_DQ1

14B8<>

20B5<>

21B5<>

MB_DQ21

14C4<>

22C5<>

23C5<>

EJECTSW_N

42C6>

34B3<

47A1<

FSB_GP_CP0_DATA4_DN

12C4>

5C7<

MA_DQ2

14B8<>

20B5<>

21B5<>

MB_DQ22

14C4<>

22C5<>

23C5<>

ENET_ACT_N

19B3>

39C3>

44B5<

FSB_GP_CP0_DATA4_DP

12C4>

5C7<

MA_DQ3

14B8<>

20B5<>

21B5<>

MB_DQ23

14C4<>

22C5<>

23D5<>

ENET_AVDD

19D4>

19B3<

19B6<

FSB_GP_CP0_DATA5_DN

12C4>

5C7<

MA_DQ4

14B8<>

20B5<>

21B5<>

MB_DQ24

14D4<>

22C5<>

23C5<>

ENET_CLK

46B1>

19C6<

39C7<

FSB_GP_CP0_DATA5_DP

12C4>

5C7<

MA_DQ5

14B8<>

20B5<>

21B5<>

MB_DQ25

14D4<>

22C5<>

23C5<>

ENET_LINK_N

19B3>

39B2>

44B5<

FSB_GP_CP0_DATA6_DN

12C4>

5C7<

MA_DQ6

14B8<>

20B5<>

21B5<>

MB_DQ26

14D4<>

22C5<>

23C5<>

ENET_P2LI_R

39B2>

44B5<

FSB_GP_CP0_DATA6_DP

12C4>

5C7<

MA_DQ7

14B8<>

20B5<>

21C5<>

MB_DQ27

14D4<>

22C5<>

23C5<>

ENET_POAC_R

39C3>

44B5<

FSB_GP_CP0_DATA7_DN

12C4>

5C7<

MA_DQ8

14C8<>

20B5<>

21B5<>

MB_DQ28

14D4<>

22C5<>

23C5<>

ENET_RST_N

33A2>

19C6<

FSB_GP_CP0_DATA7_DP

12C4>

5C7<

MA_DQ9

14C8<>

20B5<>

21B5<>

MB_DQ29

14D4<>

22C5<>

23C5<>

ENET_RX_DN

19B3>

39C1<>

MA_DQ10

14C8<>

20B5<>

21B5<>

MB_DQ30

14D4<>

22C5<>

23C5<>

4B6<

56D3< 34B8<

39C8< 44B5<

FSB_GP_CP0_FLAG_DN

5C3>

12C4>

5C7<

23C8<

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 65/73

REV K7

MB_DQ31

14D4<>

MD_CS0_N

15B1>

26B8<

MB_RAS_N

14B1>

22B8<

23B8<

MD_CS1_N

15B1>

27B8<

MB_RDQS0

22B5>

23B5>

22D5<>

14B4<

23C5<>

MD_DM0

15B4>

26B5<

27B5<

MB_RDQS1

22B5>

23B5>

14C4<

MD_DM1

15C4>

26B5<

MB_RDQS2

22C5>

23C5>

14C4<

MD_DM2

15C4>

26C5<

MB_RDQS3

22C5>

23C5>

14D4<

MD_DM3

15D4>

26C5<

MB_WDQS0

14B4>

22B5<

23B5<

MD_DQ0

15B4<>

26B5<>

MB_WDQS1

14C4>

22B5<

23B5<

MD_DQ1

15B4<>

MB_WDQS2

14C4>

22C5<

23C5<

MD_DQ2

MB_WDQS3

14D4>

22C5<

23C5<

MD_DQ3

MB_WE_N

14B1>

22B8<

23B8<

MD_DQ4

MC_A<11..0>

24C8<

25C8<

MII_RXDV

19C6>

39C7>

36C6<

VREG_GPU_EN_N

34C3>

52B3<

MII_RXER

19C6>

39C7>

36C6<

VREG_GPU_GH1

52A1>

53C7<

MII_RX_CLK

19C6>

39C7>

36D7<

VREG_GPU_GH2

52A1>

53D7<

27B5<

MII_TXD0

36C3>

19B6<

39B7<

VREG_GPU_GL1

27C5<

MII_TXD1

36C3>

19B6<

39B7<

VREG_GPU_GL2

52A1>

53C7<

27C5<

MII_TXD2

36C3>

19B6<

39B7<

VREG_GPU_PHASE1

52D1>

53B2>

27B5<>

MII_TXD3

36C3>

19B6<

39C7<

VREG_GPU_PHASE2

53D2>

52B8<

26B5<>

27B5<>

MII_TXEN

36C3>

19B6<

39C7<

VREG_GPU_PWRGD

52A1>

34D1<

15B4<>

26B5<>

27B5<>

MII_TX_CLK

19B6>

39C7>

36D7<

VREG_V1P8_EN

54A4>

54D8<

15B4<>

26B5<>

27B5<>

ODD_RX_DN

47A8>

36B6<

VREG_V1P8_EN_N

34B3>

54A3<

15B4<>

26B5<>

27B5<>

ODD_RX_DP

47A8>

36B6<

VREG_V5P0_EN

54A4>

54B7<

MD_DQ5

15B4<>

26B5<>

27B5<>

ODD_TX_DN

36B3>

47A8<

VREG_V5P0_EN_N

34B3>

54A7< 46A8<

52A1>

MC_A<12..0>

15C5>

MD_DQ6

15B4<>

26B5<>

27C5<>

ODD_TX_DP

36B3>

47B8<

VREG_V5P0_SEL

34B3>

MC_BA<2..0>

15C5>

24C8<

25B8<

MD_DQ7

15B4<>

26B5<>

27C5<>

PCIEX_CLK_DN

46B1>

33C6<

V_CMPAVDD33_USB

37A7>

MC_CAS_N

15B5>

24B8<

25B8<

MD_DQ8

15C4<>

26B5<>

27B5<>

PCIEX_CLK_DP

46B1>

33C6<

V_ENET

MC_CKE

15C5>

24B8<

25B8<

MD_DQ9

15C4<>

26B5<>

27B5<>

PEX_GPU_SB_L0_DN

13C1>

33C7<

MC_CLK0_DN

15C5>

24C8<

MD_DQ10

15C4<>

26B5<>

27B5<>

PEX_GPU_SB_L0_DP

13D1>

33C7<

V_EXPPORT

39A3> 39D5< 44B7<

53B7< 52B8<

37C2< 19C3<

19C7<

39B8<

44D4

44D7<

MC_CLK0_DP

15C5>

24D8<

MD_DQ11

15C4<>

26B5<>

27B5<>

PEX_GPU_SB_L1_DN

13D1>

33C7<

V_MEMPORT1

MC_CLK1_DN

15C5>

25C8<

MD_DQ12

15C4<>

26C5<>

27B5<>

PEX_GPU_SB_L1_DP

13D1>

33C7<

V_VREG_CPU

49B4>

MC_CLK1_DP

15D5>

25D8<

MD_DQ13

15C4<>

26C5<>

27B5<>

PEX_SB_GPU_L0_DN

33C1>

13D8<

V_VREG_GPU

49B1>

52D4<

52D7<

53D7<

MC_CS0_N

15B5>

24B8<

MD_DQ14

15C4<>

26C5<>

27B5<>

PEX_SB_GPU_L0_DP

33C1>

13D8<

V_VREG_V1P8V5P0

54D4>

32D4<

54B4<

54D4<

MC_CS1_N

15B5>

25B8<

MD_DQ15

15C4<>

26C5<>

27B5<>

PEX_SB_GPU_L1_DN

33D1>

13D8<

MC_DM0

15B8>

24B4<

25B4<

MD_DQ16

15C4<>

26C5<>

27C5<>

PEX_SB_GPU_L1_DP

33D1>

13D8<

MC_DM1

15C8>

24B4<

25B4<

MD_DQ17

15C4<>

26C5<>

27C5<>

PIX_DATA<14..0>

13C3>

29D6<

MC_DM2

15C8>

24C4<

25C4<

MD_DQ18

15C4<>

26C5<>

27C5<>

PSU_V12P0_EN

34B3>

48C5<

MC_DM3

15D8>

24C4<

25C4<

MD_DQ19

15C4<>

26C5<>

27C5<>

PWRSW_N

34C3>

48B8<

MC_DQ0

15B8<>

24B5<>

25B4<>

MD_DQ20

15C4<>

26C5<>

27C5<>

SATA_CLK_DN

46B1>

33D6<

MC_DQ1

15B8<>

24B5<>

25B4<>

MD_DQ21

15C4<>

26C5<>

27D5<>

SATA_CLK_DP

46B1>

33D6<

MC_DQ2

15B8<>

24B5<>

25B4<>

MD_DQ22

15C4<>

26C5<>

27D5<>

SATA_CLK_REF

46A1>

33D6<

MC_DQ3

15B8<>

24B5<>

25B4<>

MD_DQ23

15D4<>

26C5<>

27D5<>

SB_GPIO<0..15>

33B1<>

MC_DQ4

15B8<>

24B5<>

25B4<>

MD_DQ24

15D4<>

26C5<>

27C5<>

SB_MAIN_PWRGD

34B1>

34C6<

MC_DQ5

15B8<>

24B5<>

25B4<>

MD_DQ25

15D4<>

26C5<>

27C5<>

SB_RST_N

34B3>

34C6<

MC_DQ6

15B8<>

24B5<>

25C4<>

MD_DQ26

15D4<>

26C5<>

27C5<>

SCART_RGB

33B2>

43A6<

MC_DQ7

15B8<>

24B5<>

25C4<>

MD_DQ27

15D4<>

26D5<>

27C5<>

SMB_CLK

34B8<>

MC_DQ8

15C8<>

24B5<>

25B4<>

MD_DQ28

15D4<>

26D5<>

27C5<>

SMB_DATA

28B7<>

MC_DQ9

15C8<>

24B5<>

25B4<>

MD_DQ29

15D4<>

26D5<>

27C5<>

SMC_DBG_EN

56C6>

34C6<

MC_DQ10

15C8<>

24B5<>

25B4<>

MD_DQ30

15D4<>

26D5<>

27C5<>

SMC_DBG_TXD

34C3>

56C6<

MC_DQ11

15C8<>

24B5<>

25B4<>

MD_DQ31

27C5<>

SMC_PWM0

MC_DQ12

15C8<>

24B5<>

25B4<>

MD_RAS_N

15B1>

26B8<

27B8<

SMC_PWM1

34B3>

29C8<

MC_DQ13

15C8<>

24B5<>

25B4<>

MD_RDQS0

26B5>

27B5>

15B4<

SMC_RST_N

28D3>

34D6<

MC_DQ14

15C8<>

24C5<>

25B4<>

MD_RDQS1

26B5>

27B5>

15C4<

SPDIF

36C1>

43D6<

MC_DQ15

15C8<>

24C5<>

25B4<>

MD_RDQS2

26C5>

27C5>

15C4<

SPI_CLK

56D6>

35D7<

MC_DQ16

15C8<>

24C5<>

25C4<>

MD_RDQS3

26C5>

27C5>

15D4<

SPI_MISO

35D3>

56D8<

MC_DQ17

15C8<>

24C5<>

25C4<>

MD_WDQS0

15B4>

26B5<

27B5<

SPI_MOSI

56D6>

35D7<

MC_DQ18

15C8<>

24C5<>

25C4<>

MD_WDQS1

15C4>

26B5<

27B5<

SPI_SS_N

56D8>

35D7<

MC_DQ19

15C8<>

24C5<>

25C4<>

MD_WDQS2

15C4>

26C5<

27C5<

STBY_CLK

46A1>

34D6<

MC_DQ20

15C8<>

24C5<>

25C4<>

MD_WDQS3

15D4>

26C5<

27C5<

TILTSW_N

42B6>

MC_DQ21

15C8<>

24C5<>

25D4<>

MD_WE_N

15B1>

26B8<

27B8<

TRAY_OPEN

34D8>

47A1<

MC_DQ22

15C8<>

24C5<>

25D4<>

MEMPORT1_DN

35C4<>

45B4<>

TRAY_STATUS

47A4>

34C6<

MC_DQ23

15D8<>

24C5<>

25D4<>

MEMPORT1_DP

35C4<>

45B4<>

VID_DACA_DP

29D3>

43D8<

MC_DQ24

15D8<>

24C5<>

25C4<>

MEMPORT2_DN

35B4<>

45C4<>

VID_DACA_OUT

43D5>

43C4<

MC_DQ25

15D8<>

24C5<>

25C4<>

MEMPORT2_DP

35B4<>

45C4<>

VID_DACB_DP

29D3>

43C8<

MC_DQ26

15D8<>

24C5<>

25C4<>

MEM_A_VREF0

21A6>

20B8<

21B8<

VID_DACB_OUT

43C6>

43C4<

MC_DQ27

15D8<>

24C5<>

25C4<>

MEM_A_VREF1

20A6>

20B8<

21B8<

VID_DACC_DP

29D3>

43C8<

MC_DQ28

15D8<>

24C5<>

25C4<>

MEM_B_VREF0

23A6>

22B8<

23B8<

VID_DACC_OUT

43C6>

43C4<

MC_DQ29

15D8<>

24D5<>

25C4<>

MEM_B_VREF1

22A6>

22B8<

23B8<

VID_DACD_DP

29D3>

43B8<

MC_DQ30

15D8<>

24D5<>

25C4<>

MEM_C_VREF0

25A6>

24B8<

25B8<

VID_DACD_OUT

43B6>

43B4<

25C4<>

15D4<>

26D5<>

34B3>

28B6<

34B8<>

56C3<>

MEM_C_VREF1

24A6>

24B8<

25B8<

VID_HSYNC_OUT

43A4>

43B4<

24B8<

25B8<

MEM_D_VREF0

27A7>

26B8<

27B8<

VID_HSYNC_OUT_R

29C3>

43A7<

MC_RDQS0

24B4>

25B4>

15B8<

MEM_D_VREF1

VID_VSYNC_OUT

43A6>

43B4<

MC_RDQS1

24B4>

25B4>

15C8<

MEM_RST

VID_VSYNC_OUT_R

29C3>

43A8<

MC_RDQS2

24C4>

25C4>

15C8<

VREG_1P8_IS2P

54D1>

54D7<

MC_RDQS3

24C4>

25C4>

15D8<

MEM_SCAN_BOT_EN

VREG_3P3_EN_N

34C3>

55D8<

MC_WDQS0

15B8>

24B4<

25B4<

MEM_SCAN_BOT_EN_BUFF

VREG_5P0_IS1P

54B1>

54B6<

MC_WDQS1

15C8>

24B4<

25B4<

MEM_SCAN_EN

MC_WDQS2

15C8>

24C4<

25C4<

MC_WDQS3

15D8>

24C4<

25C4<

MEM_SCAN_EN_BUFF

MC_WE_N

15B5>

24B8<

25B8<

MEM_SCAN_TOP_EN

MD_A<11..0>

26C8<

27C8<

MD_A<12..0>

15C1>

26B8<

27B8<

20C8< 25C8<

12A1>

21C8< 26C8<

21B8<

23B8<

13B3>

12D1> 24B8< 12B1>

23C8<

25B8<

27B8<

12A4<

20B8< 25B8<

13B3>

22C8< 27C8<

21B8< 26B8<

22B8<

23B8<

27B8<

12D4< 20B8<

22B8<

24B8<

26B8<

VREG_5P0_PHASE

54B1>

54D8<

VREG_CPU_DRV_EN

50C1>

51D8<

VREG_CPU_EN

34B3>

50D7<

VREG_CPU_PHASE1

51A1>

50C8<

VREG_CPU_PHASE2

51C1>

50C8<

MII_COL

19B6>

39B7>

36C6<

VREG_CPU_PHASE3

51D1>

50C8< 51A7<

MEM_SCAN_TOP_EN_BUFF

13B3>

12B4<

MD_BA<2..0>

15C1>

26C8<

27B8<

MII_CRS

19B6>

39B7>

36C6<

VREG_CPU_PWM1

50C2>

MD_CAS_N

15B1>

26B8<

27B8<

MII_MDC_CLK_OUT

36D2>

19B6<

39C8<

VREG_CPU_PWM2

50C2>

MD_CKE

15C1>

26B8<

27B8<

MII_MDIO

19B6<>

VREG_CPU_PWM3

50C2>

51D7<

MD_CLK0_DN

15C1>

26C8<

MII_RXD0

19B7>

39C7>

36C6<

VREG_CPU_PWRGD

50C2>

34C1<

MD_CLK0_DP

15C1>

26D8<

MII_RXD1

19B6>

39C7>

36C6<

VREG_CPU_VID<5..0>

MD_CLK1_DN

15C1>

27C8<

MII_RXD2

19B6>

39C7>

36C6<

VREG_EFUSE_EN

4D2>

MD_CLK1_DP

15D1>

27D8<

MII_RXD3

19C6>

39C7>

36C6<

VREG_GPU_5VREF

52C3>

36C6<>

39B8<>

51D8<

WSS_CNTL0

33B2>

43B6<

54D7<

WSS_CNTL1

33B2>

43B6<

46B6< 46B6<

46C8<

56D3<

34B3<

15D8<>

13B3>

51D5<

29B8<

15B5>

26A7>

50D7<

54D8<

56C7<>

MC_RAS_N

24C8<

45D1>

33B5<>

MC_DQ31

24D5<>

39B8<

44B6<

54D7<

51B7<

49C2>

50C2<

55C6< 52C6<

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 66/73

REV K7

***

Part

Cross-Reference

for

the

entire

design

***

C1R4

CAPN

47

C2P13

CAPN

38

C3C3

CAPN

46

C1T1

CAPN

47

C2P14

CAPN

38

C3C4

CAPN

46

C1T2

CAPN

47

C2P15

CAPN

38

C3C5

CAPN

24

44

C1T3

CAPN

47

C2P16

CAPN

38

C3D1

CAPN

26

CAPN

44

C1T4

CAPN

47

C2P17

CAPN

38

C3D2

CAPN

26

C1A5

CAP_P

39

C1T5

CAPN

47

C2P18

CAPN

33

C3D3

CAPN

25

C1B1

CAPN

39

C1T6

CAPN

53

C2P19

CAPN

38

C3D4

CAPN

26

C1B2

CAPN

32

C1U1

CAPN

55

C2P20

CAPN

38

C3D5

CAPN

26

C1B3

CAPN

32

C1U2

CAPN

45

C2P21

CAPN

38

C3D6

CAPN

26

C1B4

CAPN

28

C2A1

CAPN

43

C2P22

CAPN

38

C3E1

CAPN

24

C1C1

CAPN

32

C2A2

CAPN

43

C2P23

CAPN

37

C3E2

CAPN

24

C1C2

CAPN

33

C2A3

CAPN

43

C2P24

CAPN

37

C3E3

CAPN

24

C1C3

CAPN

47

C2A4

CAP_P

44

C2P25

CAPN

33

C3E4

CAPN

27

C1C4

CAPN

47

C2A5

CAPN

43

C2P26

CAPN

38

C3E5

CAPN

24

C1C5

CAPN

47

C2A6

CAPN

43

C2P27

CAPN

38

C3E6

CAPN

24

C1C6

CAPN

47

C2A7

CAPN

40

C2P28

CAPN

38

C3E7

CAPN

24

C1C7

CAPN

32

C2A8

CAPN

43

C2P29

CAPN

38

C3E8

CAPN

27

C1C8

CAPN

32

C2B1

CAPN

40

C2P30

CAPN

38

C3F1

CAPN

20

C1C9

CAPN

36

C2B2

CAPN

40

C2P31

CAPN

38

C3F2

CAP_P

54

C1C10

CAP_P

47

C2B3

CAPN

40

C2P32

CAPN

38

C3F3

CAPN

20

C1C11

CAP_P

47

C2B4

CAPN

40

C2P33

CAPN

38

C3F5

CAPN

27

C1C12

CAPN

32

C2B5

CAPN

40

C2P34

CAPN

37

C3F6

CAPN

54

C1C13

CAPN

47

C2B6

CAPN

40

C2P35

CAPN

37

C3G3

CAPN

32

C1C14

CAPN

47

C2B7

CAPN

40

C2P37

CAPN

37

C3M1

CAPN

42

C1C15

CAPN

32

C2B8

CAPN

40

C2P38

CAPN

37

C3N1

CAPN

32

C1D1

CAPN

47

C2B9

CAPN

40

C2P39

CAPN

38

C3N2

CAPN

32

C1D2

CAPN

38

C2B10

CAPN

40

C2P40

CAPN

35

C3N3

CAPN

46

C1D3

CAPN

47

C2B11

CAPN

40

C2P41

CAPN

37

C3N4

CAPN

35

C1D4

CAPN

47

C2B12

CAPN

56

C2P42

CAPN

37

C3N8

CAPN

C1D6

CAPN

47

C2B13

CAPN

56

C2P43

CAPN

37

C3N9

CAPN

46

C1D7

CAPN

56

C2B14

CAPN

28

C2P44

CAPN

37

C3N10

CAPN

29

C1D8

CAPN

32

C2B15

CAPN

56

C2P45

CAPN

37

C3P1

CAPN

46

C1D9

CAP_P

47

C2B16

CAPN

33

C2P46

CAPN

37

C3P2

CAPN

46

C1D10

CAPN

32

C2B17

CAPN

28

C2P47

CAPN

37

C3P4

CAPN

46

C1D11

CAP_P

46

C2C1

CAPN

33

C2P48

CAPN

37

C3P5

CAPN

46

C1E1

CAPN

47

C2C2

CAPN

33

C2P50

CAPN

29

C3P6

CAPN

46

C1E2

CAPN

47

C2C3

CAPN

33

C2P51

CAPN

34

C3P7

CAPN

46

C1E3

CAPN

47

C2C4

CAPN

33

C2P52

CAPN

38

C3P8

CAPN

46

C1E4

CAPN

47

C2C5

CAPN

55

C2R1

CAPN

29

C3R1

CAPN

27

C1E5

CAP_P

47

C2C6

CAPN

55

C2R2

CAPN

29

C3R2

CAPN

27

C1F1

CAPN

32

C2D1

CAPN

26

C2R3

CAPN

37

C3R3

CAPN

26

C1F2

CAPN

32

C2D2

CAPN

26

C2R4

CAPN

53

C3R4

CAPN

27

C1F3

CAP_P

55

C2D3

CAPN

24

C2R5

CAPN

37

C3R5

CAPN

15

C1F4

CAP_P

45

C2D4

CAPN

26

C2R6

CAPN

37

C3R6

CAPN

27

C1F5

CAPN

55

C2D5

CAPN

12

C2R7

CAPN

27

C3R7

CAPN

27

C1F6

CAPN

45

C2D6

CAP_P

53

C2R8

CAPN

27

C3T1

CAPN

25

C1G1

CAPN

32

C2E1

CAPN

24

C2R9

CAPN

24

C3T2

CAPN

25

C1M1

CAPN

44

C2E2

CAPN

26

C2R10

CAPN

27

C3T3

CAPN

25

C1M2

CAPN

44

C2E3

CAPN

24

C2R11

CAPN

41

C3T4

CAPN

25

C1N1

CAPN

39

C2E4

CAPN

12

C2R12

CAPN

12

C3T5

CAPN

25

C1N2

CAPN

39

C2E5

CAPN

41

C2R13

CAPN

27

C3T6

CAPN

25

C1N3

CAPN

39

C2E6

CAPN

41

C2T1

CAPN

25

C3T7

CAPN

25

C1N4

CAPN

39

C2E7

CAP_P

53

C2T2

CAPN

26

C3U1

CAPN

21

C1N5

CAPN

39

C2E8

CAPN

24

C2T3

CAPN

25

C3U2

CAPN

21

C1N6

CAPN

19

C2F2

CAPN

32

C2T4

CAPN

32

C3U3

CAPN

32

C1N7

CAPN

19

C2F3

CAP_P

54

C2T5

CAPN

53

C3U4

CAPN

27

C1N8

CAPN

19

C2G1

CAPN

32

C2T6

CAPN

27

C3U5

CAPN

54

C1N9

CAPN

39

C2G2

CAP_P

45

C2T7

CAPN

27

C3U6

CAPN

54

C1N10

CAPN

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C7R18

CAPN

11

C7R96

CAPN

11

C7T53

CAPN

11

C6V10

CAPN

48

C7R19

CAPN

10

C7R97

CAPN

11

C7T54

CAPN

11

C6V11

CAPN

48

C7R20

CAPN

11

C7R98

CAPN

11

C7T55

CAPN

11

C6V12

CAPN

48

C7R21

CAPN

11

C7R99

CAPN

10

C7T56

CAPN

11

C6V15

CAPN

48

C7R22

CAPN

10

C7R100

CAPN

10

C7T57

CAPN

11

C7B1

CAPN

32

C7R23

CAPN

10

C7R101

CAPN

11

C7T58

CAPN

11

C7B2

CAPN

53

C7R24

CAPN

10

C7R102

CAPN

10

C7T59

CAPN

11

C7B3

CAP_P

49

C7R25

CAPN

10

C7R103

CAPN

11

C7T60

CAPN

11

C7B4

CAPN

49

C7R26

CAPN

9

C7R104

CAPN

11

C7T61

CAPN

11

C7C1

CAP_P

49

C7R27

CAPN

9

C7R105

CAPN

11

C7T62

CAPN

11

C7C2

CAP_P

49

C7R28

CAPN

9

C7R106

CAPN

11

C7T63

CAPN

11

C7D1

CAPN

6

C7R29

CAPN

9

C7R107

CAPN

11

C7T64

CAPN

11

C7D2

CAPN

6

C7R30

CAPN

9

C7R108

CAPN

11

C7T65

CAPN

11

C7D3

CAPN

9

C7R31

CAPN

11

C7R109

CAPN

11

C7T66

CAPN

11

C7D4

CAPN

9

C7R32

CAPN

11

C7R110

CAPN

10

C7T67

CAPN

11

C7D5

CAPN

9

C7R33

CAPN

11

C7R111

CAPN

10

C7T68

CAPN

11

C7D6

CAPN

9

C7R34

CAPN

10

C7R112

CAPN

4

C7T69

CAPN

10

C7D7

CAPN

9

C7R35

CAPN

10

C7R113

CAPN

4

C7T70

CAPN

10

9 9

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 69/73

REV K7

C7T71

CAPN

10

C9B1

CAP_P

48

DB1N1

DBPAD

19

FB2A1

FERRITE

40

C7T72

CAPN

10

C9B2

CAPN

49

DB1N3

DBPAD

39

FB2A2

FERRITE

40

C7T73

CAPN

10

C9B3

CAPN

52

DB1N4

DBPAD

39

FB2N1

FERRITE

35

C7T74

CAPN

10

C9B4

CAPN

49

DB1N5

DBPAD

33

FB2P1

FERRITE

37

C7T75

CAPN

10

C9C1

CAP_P

49

DB1P1

DBPAD

33

FB2P2

FERRITE

38

C7T76

CAPN

9

C9C2

CAPN

52

DB1P2

DBPAD

33

FB2P3

FERRITE

37

C7T77

CAPN

9

C9C3

CAPN

49

DB2N3

DBPAD

33

FB2P4

FERRITE

37

C7T78

CAPN

9

C9C4

CAP_P

49

DB2N4

DBPAD

33

FB2P5

FERRITE

37

C7T79

CAPN

9

C9C5

CAPN

51

DB2N5

DBPAD

33

FB2R1

FERRITE

37

C7T80

CAPN

11

C9C7

CAPN

32

DB2N6

DBPAD

33

FB3B2

FERRITE

30

C7T81

CAPN

10

C9D1

CAPN

51

DB2N7

DBPAD

33

FB3P1

FERRITE

46

C7T82

CAPN

10

C9D2

CAP_P

49

DB2N8

DBPAD

33

FB3P2

FERRITE

46

C7T83

CAPN

9

C9D3

CAPN

51

DB2N9

DBPAD

33

FB4C2

FERRITE

30

C7T84

CAPN

9

C9D4

CAPN

51

DB2N10

DBPAD

33

FB4D1

FERRITE

16

C7T85

CAPN

9

C9E1

CAPN

51

DB2N11

DBPAD

33

FB4N1

FERRITE

30

C7T86

CAPN

9

C9E2

CAPN

32

DB2N12

DBPAD

33

FB4N2

FERRITE

30

C7T87

CAPN

9

C9E3

CAP_P

49

DB2P1

DBPAD

33

FB4N3

FERRITE

30

C7T88

CAPN

9

C9E4

CAPN

51

DB2P2

DBPAD

33

FB4N4

FERRITE

30

C7T89

CAPN

57

C9F1

CAPN

51

DB2P3

DBPAD

33

FB4P1

FERRITE

C7T90

CAPN

57

C9F2

CAPN

32

DB2P4

DBPAD

33

FB4R1

FERRITE

16

C7T91

CAPN

57

C9F3

CAPN

51

DB2P5

DBPAD

33

FB4T1

FERRITE

16

C7T92

CAPN

57

C9F4

CAPN

51

DB2P6

DBPAD

33

FB5G1

FERRITE

45

C7T93

CAPN

9

C9G1

CAPN

45

DB2P7

DBPAD

33

FB5R1

FERRITE

16

C7T94

CAPN

9

C9G2

CAP_P

45

DB2P8

DBPAD

34

FB6D1

FERRITE

6

C7T95

CAPN

9

C9G3

CAP_P

45

DB2P9

DBPAD

34

FB6R1

FERRITE

6

C7T96

CAPN

9

C9G4

CAPN

45

DB2P15

FB6R2

FERRITE

6

C7T97

CAPN

9

C9N1

CAPN

32

DB3B1

DBPAD

28

FB7D1

FERRITE

C7T98

CAPN

55

C9P1

CAPN

52

DB3B2

DBPAD

28

FB7R1

FERRITE

6

C7T99

CAPN

55

C9P2

CAPN

51

DB3B3

DBPAD

28

FT1N1

FTPAD

33

55

C9P3

CAPN

51

DB3B4

DBPAD

28

FT1N2

FTPAD

44

C7T100 C7T101

CAPN CAPN

DBPAD

33

30

6

9

C9P4

CAPN

51

DB3C1

DBPAD

28

FT1P1

FTPAD

C7U1

CAPN

50

C9T1

CAPN

51

DB3C2

DBPAD

28

FT1P2

FTPAD

46

C7U2

CAPN

50

C9T2

CAPN

51

DB3C3

DBPAD

28

FT1R1

FTPAD

46

C7U3

CAPN

50

C9T3

CAPN

51

DB3C4

DBPAD

28

FT1R2

FTPAD

46

C7U4

CAPN

50

C9U1

CAPN

51

DB3F1

DBPAD

54

FT1R3

FTPAD

41

C7V1

CAPN

50

C9U2

CAPN

51

DB3N2

DBPAD

28

FT1R4

FTPAD

41

C7V2

CAPN

54

C9U3

CAPN

51

DB3N3

DBPAD

28

FT1R5

FTPAD

41

C8A1

CAPN

48

C9V3

CAPN

45

DB4D1

DBPAD

13

FT1T1

FTPAD

41

C8A2

CAPN

48

CR1D1

MBT3904DUAL

DB4N4

DBPAD

28

FT1U1

FTPAD

55

C8B1

CAP_P

48

CR1D2

DIOSOT23S

47

DB4P1

DBPAD

29

FT1U2

FTPAD

34

C8B2

CAPN

49

CR1D3

DIOSOT23S

47

DB4P2

DBPAD

29

FT1V1

FTPAD

C8B3

CAPN

52

CR2A1

MBT3904DUAL

43

DB4P3

DBPAD

29

FT2M1

FTPAD

40

C8B4

CAPN

49

CR2N1

MBT3904DUAL

40

DB5P1

DBPAD

29

FT2N1

FTPAD

40

C8B6

CAPN

53

CR4N1

DIOSOT23S

55

DB5P2

DBPAD

29

FT2N2

FTPAD

40

C8B7

CAPN

52

CR4P2

DIOSOT23S

55

DB6E1

DBPAD

31

FT2N3

FTPAD

28

C8B8

CAPN

52

CR6T1

MBT3904DUAL

DB6E2

DBPAD

31

FT2N4

FTPAD

46

C8C1

CAP_P

49

D1A1

DIOSOT23S

44

DB6E3

DBPAD

31

FT2P1

FTPAD

40

C8D1

CAP_P

49

D1A2

DIOSOT23S

44

DB6G1

DBPAD

54

FT2P2

FTPAD

28

C8D4

CAP_P

49

D1B1

DIOSOT23S

44

DB7R1

DBPAD

4

FT2P3

FTPAD

52

C8E3

CAP_P

49

D1E1

DIOSOT23S

47

DB7U3

DBPAD

50

FT2P4

FTPAD

28

C8E8

CAP_P

49

D1E2

DIOSOT23S

47

DB8M1

DBPAD

48

FT2P5

FTPAD

34

C8F1

CAP_P

49

D1E3

DIOSOT23S

47

DB8M2

DBPAD

48

FT2P6

FTPAD

52

C8F2

CAP_P

49

D1E4

DIOSOT23S

47

DB8M3

DBPAD

48

FT2P7

FTPAD

28

C8F3

CAP_P

49

D2A1

DIOSOT23S

43

DB8P1

DBPAD

49

FT2P8

FTPAD

35

C8G1

CAPN

50

D2A2

DIOSOT23S

43

DB8P2

DBPAD

49

FT2P9

FTPAD

35

C8G2

CAPN

32

D2M2

DIOSOT23S

35

EG1A1

ESDGUARD

44

FT2P10

FTPAD

34

C8N1

CAPN

52

D2M3

DIOSOT23S

35

EG1A2

ESDGUARD

44

FT2P11

FTPAD

4

C8N2

CAPN

52

D3A1

DIODE

42

EG1E1

ESDGUARD

47

FT2P12

FTPAD

4

C8N3

CAPN

52

D3A2

DIOSOT23S

43

EG1E2

ESDGUARD

47

FT2P13

FTPAD

13

C8N4

CAPN

52

D3A3

DIOSOT23S

43

EG1E3

ESDGUARD

47

FT2P14

FTPAD

13

C8N5

CAPN

52

D3A4

DIOSOT23S

43

EG1E4

ESDGUARD

47

FT2P15

FTPAD

34

C8P1

CAPN

52

D3B1

DIODE

42

EG2B1

ESDGUARD

40

FT2P16

FTPAD

50

C8P2

CAPN

52

D3M2

DIOSOT23S

43

EG2B2

ESDGUARD

40

FT2P17

FTPAD

50

C8P3

CAPN

52

D3M3

DIOSOT23S

43

EG2G1

ESDGUARD

45

FT2P18

FTPAD

54

C8P4

CAPN

52

D4V1

ZENER

54

EG3G1

ESDGUARD

45

FT2P19

FTPAD

54

C8P5

CAPN

56

D4V2

DIOSOT23S

54

EG4G1

ESDGUARD

45

FT2P20

FTPAD

35

C8U1

CAPN

50

D8B1

ZENER

52

EG4G2

ESDGUARD

45

FT2P21

FTPAD

35

C8U2

CAPN

50

D8B2

DIODE

52

EG9G1

ESDGUARD

45

FT2P22

FTPAD

35

C8U3

CAPN

50

D8B3

DIOSOT23S

52

EG9G2

ESDGUARD

45

FT2P23

FTPAD

35

C8V1

CAPN

50

D8B4

LED

56

EG9V1

ESDGUARD

45

FT2P24

FTPAD

34

C8V14

CAPN

45

D9C1

DIODE

51

EG9V2

ESDGUARD

45

FT2P25

FTPAD

C9A1

CAPN

48

D9E1

DIODE

51

FB1B1

FERRITE

39

FT2P26

FTPAD

C9A2

CAPN

48

D9F1

DIODE

51

FB1N1

FERRITE

19

FT2R1

FTPAD

34

C9A3

CAPN

56

D9G1

DIOSOT23S

45

FB1P1

FERRITE

38

FT2R2

FTPAD

46

C9A4

CAPN

48

D9G2

DIOSOT23S

45

FB1P2

FERRITE

38

FT2R3

FTPAD

41

C9A5

CAPN

48

D9V1

DIOSOT23S

45

FB1P3

FERRITE

38

FT2R4

FTPAD

41

C9A6

CAPN

48

D9V2

DIOSOT23S

45

FB1P4

FERRITE

38

FT2R5

FTPAD

41

46

55

46

45

34 55

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 70/73

REV K7

FT2R6

FTPAD

41

L3A3

INDUCTOR

43

R1B4

RESN

39

R2B16

RESN

FT2R7

FTPAD

41

L4G1

CMCHOKE

45

R1B5

RESN

39

R2B18

RESN

FT2R8

FTPAD

53

L6C1

INDUCTOR

53

R1B6

RESN

39

R2B19

RESN

34

FT2U1

FTPAD

54

L6F1

INDUCTOR

54

R1B7

RESN

39

R2C3

RESN

55

FT3N1

FTPAD

28

L6G1

CMCHOKE

48

R1B9

RESN

36

R2D1

RESN

41

FT3P1

FTPAD

46

L7C1

INDUCTOR

53

R1B10

RESN

36

R2D2

RESN

41

FT3P2

FTPAD

46

L7F1

INDUCTOR

54

R1B11

RESN

39

R2D3

RESN

41

FT3P3

FTPAD

34

L8B1

INDUCTOR

49

R1B12

RESN

19

R2D4

RESN

41

FT3P4

FTPAD

28

L8D1

INDUCTOR

51

R1B13

RESN

39

R2D5

RESN

41

FT4N1

FTPAD

29

L8E1

INDUCTOR

51

R1C1

RESN

39

R2D6

RESN

41

FT4N2

FTPAD

28

L8F1

INDUCTOR

51

R1C2

RESN

33

R2D7

RESN

41

FT4N4

FTPAD

29

L9B1

INDUCTOR

49

R1C3

RESN

36

R2D8

RESN

FT4N5

FTPAD

28

L9G1

CMCHOKE

45

R1C4

RESN

33

R2D9

RESN

13

FT4P1

FTPAD

28

L9V1

CMCHOKE

45

R1C5

RESN

33

R2D10

RESN

13

FT4P2

FTPAD

28

LB7G1

LABEL

58

R1C6

RESN

33

R2D11

RESN

12

FT4P3

FTPAD

28

MTG1B1

58

R1C7

RESN

33

R2D12

RESN

12

FT5N1

FTPAD

55

MTG1G1

STD_MTG_HOLE

58

R1C8

RESN

36

R2E1

RESN

13

FT5N2

FTPAD

55

MTG3C1

STD_MTG_HOLE

58

R1D2

RESN

41

R2E2

RESN

13

FT5R1

FTPAD

55

MTG3E1

STD_MTG_HOLE

58

R1D3

RESN

41

R2E3

RESN

13

FT5R2

FTPAD

49

MTG5B1

STD_MTG_HOLE

58

R1D4

RESN

41

R2E4

RESN

13

FT6U1

FTPAD

31

MTG5C1

STD_MTG_HOLE

58

R1D5

RESN

46

R2E5

RESN

12

FT6U2

FTPAD

31

MTG5E1

STD_MTG_HOLE

58

R1D6

RESN

46

R2F2

RESN

55

FT6U3

FTPAD

31

MTG5G1

STD_MTG_HOLE

58

R1E2

RESN

41

R2G2

RESN

42

FT6U4

FTPAD

31

MTG6C1

STD_MTG_HOLE

58

R1F7

RESN

55

R2G3

RESN

42

FT6U5

FTPAD

31

MTG6E1

STD_MTG_HOLE

58

R1F8

RESN

55

R2G5

RESN

45

FT6U6

FTPAD

31

MTG8C1

STD_MTG_HOLE

58

R1G1

RESN

46

R2M1

RESN

34

FT6U7

FTPAD

31

MTG8E1

STD_MTG_HOLE

58

R1G2

RESN

46

R2M2

RESN

43

FT6U8

FTPAD

31

MTG9B1

STD_MTG_HOLE

58

R1G3

RESN

42

R2M3

RESN

34

FT6U9

FTPAD

31

MTG9G1

STD_MTG_HOLE

58

R1G4

RESN

42

R2M4

RESN

43

STD_MTG_HOLE

34 34

41

FT6U10

FTPAD

31

Q1G1

NPN

29

R1M1

RESN

39

R2M5

RESN

34

FT6U11

FTPAD

31

Q1G2

NPN

46

R1M2

RESN

39

R2M6

RESN

43

FT6V1

FTPAD

54

Q1G3

PNP

29

R1M3

RESN

44

R2M7

RESN

35

FT7R1

FTPAD

4

Q1V1

NPN

46

R1N1

RESN

39

R2M8

RESN

35

FT7R2

FTPAD

4

Q2F2

FET_P

55

R1N2

RESN

39

R2M9

RESN

43

FT7R3

FTPAD

55

Q2G1

FET_VREG

54

R1N3

RESN

39

R2M10

RESN

43

FT7R4

FTPAD

4

Q2M1

PNP

43

R1N4

RESN

39

R2M11

RESN

43

FT7R5

FTPAD

4

Q2N1

PNP

40

R1N5

RESN

39

R2M12

RESN

FT7R6

FTPAD

4

Q2N2

NPN

35

R1N6

RESN

39

R2M13

RESN

40

FT7R7

FTPAD

56

Q3A1

NPN

42

R1N7

RESN

39

R2N1

RESN

40

FT7T1

FTPAD

4

Q3A2

PNP_2C

42

R1N8

RESN

19

R2N2

RESN

40

FT7T2

FTPAD

4

Q3F1

FET_VREG

54

R1P1

RESN

33

R2N3

RESN

40

FT7T3

FTPAD

4

Q3G1

FET

54

R1P2

RESN

33

R2N4

RESN

33

FT7T4

FTPAD

4

Q3M1

PNP_2C

42

R1P3

RESN

33

R2N5

RESN

33

FT7T5

FTPAD

4

Q3M4

NPN

42

R1P5

RESN

33

R2N6

RESN

33

FT7T6

FTPAD

55

Q4G1

FET

54

R1P6

RESN

33

R2N7

RESN

42

FT7T7

FTPAD

4

Q6B1

FET_VREG

53

R1P7

RESN

35

R2N8

RESN

FT7T8

FTPAD

55

Q6B2

FET_VREG

53

R1R1

RESN

35

R2N9

RESN

34

FT7U1

FTPAD

49

Q6C1

FET_VREG

53

R1R2

RESN

46

R2N10

RESN

35

FT8N1

FTPAD

48

Q6F1

FET_VREG

54

R1R3

RESN

46

R2N11

RESN

35

FT9N1

FTPAD

48

Q6F2

FET_VREG

54

R1R4

47

R2N12

RESN

35

J1A1

XENONRJ45USB

Q7B1

FET_VREG

53

R1R5

RESN

46

R2N13

RESN

56

J1C1

1X7SATA

47

Q7B2

FET_VREG

53

R1V1

RESN

46

R2N14

RESN

56

J1D1

2X6HDR2

47

Q7C1

FET_VREG

53

R1V2

RESN

46

R2N15

RESN

34

J1D2

2X5HDR10

56

Q8B3

FET

52

R2A1

RESN

43

R2P1

RESN

28

J1E1

XENONHDD

47

Q8B4

NPN

48

R2A2

RESN

34

R2P2

RESN

33

J1F1

1X6HDR

56

Q8B5

NPN

48

R2A3

RESN

43

R2P3

RESN

28

J2A1

XENONAVIP

43

Q8B6

NPN

56

R2A4

RESN

43

R2P4

RESN

34

J2B1

2X7HDR14

56

Q8C1

FET_VREG

51

R2A5

RESN

43

R2P5

RESN

33

J2D1

2X3HDR

33

Q8F1

FET_VREG

51

R2A6

RESN

43

R2P6

RESN

34

J2D2

2X4HDR

13

Q8N1

PNP_2C

48

R2A7

RESN

43

R2P8

RESN

33

J3A1

2X2HDR

42

Q9C1

FET_VREG

51

R2A8

RESN

43

R2P9

RESN

33

J3G1

XENONMU

45

Q9D1

FET_VREG

51

R2A9

RESN

43

R2P10

RESN

34

J5C1

2X3HDR

28

Q9D2

FET_VREG

51

R2A10

RESN

36

R2P11

RESN

33

J5C2

2X3HDR

13

Q9D3

FET_VREG

51

R2B1

RESN

40

R2P12

RESN

34

J6G1

XENONRF

48

Q9D4

FET_VREG

51

R2B2

RESN

40

R2P13

RESN

34

J7F1

2X3HDR

4

Q9E1

FET_VREG

51

R2B3

RESN

40

R2P14

RESN

35

J7G1

1X3HDR

56

Q9E3

FET_VREG

51

R2B4

RESN

40

R2P15

RESN

34

J8C1

2X5HDR

56

Q9F1

FET_VREG

51

R2B5

RESN

40

R2P16

RESN

33

J9A1

XENONPWR

48

Q9F2

FET_VREG

51

R2B6

RESN

40

R2P17

RESN

J9A2

1X2HDR

56

Q9F4

FET_VREG

51

R2B7

RESN

56

R2P18

RESN

56

J9G1

XENONGAME

45

R1A1

RESN

39

R2B8

RESN

33

R2R1

RESN

24

L1B1

CMCHOKE

44

R1A2

RESN

39

R2B9

RESN

33

R2R2

RESN

24

44

RESN

40

33

38

L2A1

INDUCTOR

43

R1A3

RESN

39

R2B10

RESN

33

R2R3

RESN

25

L2F1

INDUCTOR

54

R1A4

RESN

39

R2B11

RESN

36

R2R4

RESN

25

L2G1

CMCHOKE

45

R1A5

RESN

44

R2B12

RESN

36

R2R5

RESN

12

L3A1

INDUCTOR

43

R1B1

RESN

44

R2B13

RESN

36

R2R6

RESN

12

L3A2

INDUCTOR

43

R1B2

RESN

44

R2B14

RESN

36

R2T1

RESN

12

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 71/73

REV K7

R2T2

RESN

12

R3R1

RESN

25

R4U1

RESN

23

R7E6

RESN

49

R2T3

RESN

26

R3T1

RESN

27

R4U2

RESN

21

R7E7

RESN

4

R2T4

RESN

26

R3T2

RESN

15

R4U3

RESN

21

R7E8

RESN

4

R2T5

RESN

27

R3U1

RESN

21

R4U4

RESN

20

R7F1

RESN

4

R2T6

RESN

27

R3U2

RESN

54

R4U5

RESN

20

R7F2

RESN

4

R2T7

RESN

53

R3V1

RESN

54

R4U6

RESN

12

R7F3

RESN

4

R2T8

RESN

53

R3V2

RESN

54

R4V1

RESN

54

R7F4

RESN

4

R2U1

RESN

54

R3V3

RESN

54

R4V2

RESN

54

R7F5

RESN

50

R2V1

RESN

42

R3V4

RESN

54

R4V3

RESN

54

R7F7

RESN

4

R2V2

RESN

54

R3V5

RESN

54

R5C1

RESN

28

R7N1

RESN

48

R3A1

RESN

42

R3V6

RESN

54

R5C2

RESN

28

R7N2

RESN

48

R3A2

RESN

42

R3V7

RESN

54

R5C3

RESN

28

R7N3

RESN

48

R3A3

RESN

43

R3V8

RESN

54

R5C4

RESN

55

R7N4

RESN

48

R3A4

RESN

43

R3V9

RESN

54

R5C5

RESN

13

R7R1

RESN

4

R3A5

RESN

42

R4B2

RESN

28

R5C6

RESN

55

R7R2

RESN

4

R3A6

RESN

43

R4B3

RESN

28

R5C8

RESN

13

R7R3

RESN

4

R3A7

RESN

42

R4B7

RESN

28

R5C9

RESN

55

R7R4

RESN

4

R3A8

RESN

42

R4B8

RESN

28

R5C10

RESN

13

R7R5

RESN

4

R3B1

RESN

28

R4B9

RESN

28

R5C11

RESN

12

R7R6

RESN

4

R3B4

RESN

46

R4B10

RESN

29

R5C12

RESN

12

R7R7

RESN

4

R3B5

RESN

46

R4B11

RESN

29

R5D1

RESN

13

R7R8

RESN

R3B7

RESN

46

R4B12

RESN

29

R5D2

RESN

13

R7R9

RESN

4

R3B8

RESN

46

R4B13

RESN

29

R5E1

RESN

14

R7R10

RESN

4

R3B15

RESN

28

R4B14

RESN

29

R5E2

RESN

14

R7R11

RESN

4

4

R3B16

RESN

42

R4B15

RESN

29

R5F1

RESN

23

R7R12

RESN

4

R3C1

RESN

46

R4B16

RESN

28

R5F2

RESN

23

R7R13

RESN

4

R3C2

RESN

46

R4B17

RESN

28

R5F3

RESN

22

R7R14

RESN

4

R3C3

RESN

46

R4C1

RESN

29

R5F4

RESN

22

R7R15

RESN

4

R3C4

RESN

46

R4C2

RESN

29

R5F5

RESN

54

R7R16

RESN

4

R3C5

RESN

46

R4C3

RESN

13

R5F6

RESN

54

R7R17

RESN

4

R3C6

RESN

46

R4C4

RESN

13

R5N1

RESN

52

R7R18

RESN

4

R3C7

RESN

46

R4C5

RESN

13

R5P1

RESN

55

R7R19

RESN

4

R3C8

RESN

46

R4C6

RESN

13

R5P2

RESN

55

R7R20

RESN

4

R3C9

RESN

46

R4C7

RESN

13

R5P3

RESN

13

R7R21

RESN

4

R3C10

RESN

46

R4D1

RESN

13

R5R1

RESN

12

R7R22

RESN

4

R3C11

RESN

46

R4D2

RESN

13

R5R2

RESN

12

R7R23

RESN

4

R3C12

RESN

46

R4D3

RESN

13

R5R3

RESN

12

R7R24

RESN

4

R3C13

RESN

28

R4D4

RESN

13

R5U1

RESN

23

R7T2

RESN

6

R3C14

RESN

28

R4F1

RESN

21

R5U2

RESN

23

R7T4

RESN

49

R3C15

RESN

46

R4F2

RESN

21

R5U3

RESN

22

R7T5

RESN

49

R3C16

RESN

46

R4F3

RESN

20

R5U4

RESN

22

R7T6

RESN

49

R3C17

RESN

46

R4F4

RESN

20

R5V2

RESN

42

R7T7

RESN

49

R3C18

RESN

46

R4F5

RESN

22

R5V3

RESN

42

R7T8

RESN

49

R3C19

RESN

28

R4F6

RESN

13

R6B3

RESN

53

R7T9

RESN

49

R3C20

RESN

28

R4F7

RESN

12

R6C1

RESN

55

R7T10

RESN

55

R3C21

RESN

55

R4F8

RESN

12

R6D1

RESN

4

R7T11

RESN

49

R3C22

RESN

55

R4G1

RESN

54

R6D2

RESN

4

R7T12

RESN

49

R3C27

RESN

46

R4G2

RESN

54

R6E1

RESN

4

R7T13

RESN

49

R3C28

RESN

13

R4G3

RESN

54

R6E2

RESN

4

R7T14

RESN

49

R3D1

RESN

24

R4G4

RESN

45

R6G1

RESN

54

R7T15

RESN

49

R3D2

RESN

25

R4G5

RESN

45

R6G7

RESN

48

R7T16

RESN

49

R3D3

RESN

25

R4G6

RESN

54

R6G8

RESN

48

R7U1

RESN

50

R3D4

RESN

24

R4N1

RESN

30

R6R1

RESN

55

R7U2

RESN

50

R3D5

RESN

24

R4N8

RESN

42

R6R2

RESN

55

R7U3

RESN

4

R3E1

RESN

26

R4P1

RESN

28

R6R3

RESN

55

R7V1

RESN

50

R3E2

RESN

27

R4P2

RESN

42

R6R4

RESN

4

R7V2

RESN

50

R3E3

RESN

27

R4P3

RESN

28

R6R5

RESN

4

R7V3

RESN

50

R3E4

RESN

26

R4P4

RESN

28

R6R6

RESN

4

R7V4

RESN

34

R3E5

RESN

26

R4P5

RESN

28

R6R7

RESN

4

R7V5

RESN

50

R3F1

RESN

20

R4P6

RESN

29

R6R8

RESN

4

R7V6

RESN

56

R3G1

RESN

54

R4P7

RESN

29

R6R9

RESN

4

R7V7

RESN

56

R3G4

RESN

45

R4R1

RESN

15

R6R10

RESN

4

R8A1

RESN

48

R3G5

RESN

54

R4R2

RESN

15

R6T1

RESN

55

R8A2

RESN

48

R3G6

RESN

54

R4R3

RESN

13

R6T3

RESN

55

R8A3

RESN

48

R3G7

RESN

54

R4R4

RESN

15

R6T4

RESN

55

R8A4

RESN

48

R3M2

RESN

43

R4R5

RESN

15

R6U1

RESN

54

R8A5

RESN

56

R3M3

RESN

43

R4R6

RESN

15

R6V1

RESN

54

R8B2

RESN

52

R3M4

RESN

42

R4R7

RESN

15

R6V2

RESN

54

R8B3

RESN

52

R3M5

RESN

42

R4R8

RESN

13

R6V3

RESN

54

R8B4

RESN

52

R3N1

RESN

35

R4T1

RESN

13

R7B2

RESN

48

R8B5

RESN

48

R3N3

RESN

35

R4T2

RESN

15

R7B6

RESN

53

R8B6

RESN

56

R3N6

RESN

48

R4T3

RESN

14

R7D1

RESN

4

R8C1

RESN

52

R3N7

RESN

48

R4T4

RESN

14

R7E1

RESN

49

R8C2

RESN

56

R3P2

RESN

46

R4T5

RESN

14

R7E2

RESN

49

R8C3

RESN

56

R3P3

RESN

46

R4T6

RESN

14

R7E3

RESN

49

R8C4

RESN

56

R3P6

RESN

34

R4T7

RESN

14

R7E4

RESN

49

R8C5

RESN

56

R3P7

RESN

34

R4T8

RESN

14

R7E5

RESN

49

R8C6

RESN

56

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 72/73

REV K7

R8G3

RESN

50

ST8F1

R8N1

RESN

48

SW1G1 SWITCH

42

R8N2

RESN

52

SW2G1 SWITCH

42

R8N3

RESN

52

SW2G2 SWITCH

R8N4

RESN

52

SW5G1 SWITCH

42

R8N5

RESN

52

TP6D1

PROBE

4

R8N6

RESN

52

TP6R1

PROBE

4

R8N7

RESN

52

TP6R2

PROBE

4

R8N8

RESN

52

TP7A1

TDRX4

57

R8N9

RESN

52

TP7A2

TDRX4

57

R8N10

RESN

52

TP7M1

TDRX2

57

R8N11

RESN

52

TP7M2

TDRX2

57

R8N12

RESN

52

TP7R1

PROBE

4

R8N17

RESN

34

TP7R2

PROBE

4

R8N18

RESN

34

TP7R3

PROBE

R8P1

RESN

52

TP7R4

PROBE

4

R8P2

RESN

52

TP8A1

TDRX2

57

R8P3

RESN

52

TP8A2

TDRX2

57

R8P4

RESN

52

TP8M1

TDRX4

57

R8P5

RESN

52

TP8M2

TDRX4

57

R8P6

RESN

52

U1B1

BCM5241

R8P7

RESN

52

U1B2

ICS1893BF

39

R8P8

RESN

56

U1E1

NCP1117

53

R8P9

RESN

52

U1F1

NCP1086

55

R8U1

RESN

50

U1F2

NCP1117

45

R8U2

RESN

50

U1G1

IR_WHOLDER

R8U3

RESN

50

U1R1

SI4501DY

46

R8U4

RESN

50

U2B1

XDAC

40

R8V1

RESN

50

U2C1

R8V2

RESN

50

U2D1

SN74LVC1G125

R8V3

RESN

50

U2E1

NAND

R8V4

RESN

50

U2E2

R8V5

RESN

50

U2R1

SN74LVC1G125

R9B1

RESN

52

U2T1

NCP1117

R9C1

RESN

51

U3B4

MK1493REV13

R9E1

RESN

51

U3D1

GDDR136

24

R9F1

RESN

51

U3E1

GDDR136

26

R9G1

RESN

SHORT

SB

50

42

4

19

42

33

35

36

37

38

15

16

17

12

SN74LVC1G125

12 12 53 46

45

U3P1

NCP1117

55

R9G2

RESN

45

U3R1

GDDR136

25

R9P1

RESN

51

U3T1

GDDR136

27

R9P2

RESN

51

U4B1

ANA

28

R9T1

RESN

51

U4C1

AT25020A

13

R9T2

RESN

51

U4D1

NB

12

R9U1

RESN

51

U4F1

GDDR136

20

R9U2

RESN

51

U4U1

GDDR136

21

R9V1

RESN

45

U4V1

NCP5425

54

R9V2

RESN

45

U5B1

NCP1117

RT1B1

THERMISTOR

44

U5B2

NCP1117

55

RT1R1

THERMISTOR

47

U5C1

NCP1117

55

RT1U1

THERMISTOR

47

U5F1

GDDR136

22

RT2G1

THERMISTOR

45

U5U1

GDDR136

RT2M1

THERMISTOR

43

U6R1

NCP1117

55

RT7C1

THERMISTOR

52

U6T1

NCP502D

55

RT8F1

THERMISTOR

50

U6T2

LP2980

55

RT8G1

THERMISTOR

45

U7D1

WATERNOOSE

RT8G2

THERMISTOR

45

U7E1

AT25020A

4

ST1P1

SHORT

38

U7U1

ADP3188

50

ST1P2

SHORT

38

U8N1

ST1P3

SHORT

38

U9P1

MOSDRIVER

51

ST2P1

SHORT

38

U9T1

MOSDRIVER

51

ST2P2

SHORT

37

U9U1

MOSDRIVER

51

ST2P3

SHORT

37

Y3B1

CRYSTAL

46

ST2P4

SHORT

37

ST4C1

SHORT

29

ST4C2

SHORT

29

ST4C3

SHORT

29

ST4C4

SHORT

29

ST4C5

SHORT

29

ST5D1

SHORT

52

ST5R1

SHORT

52

ST5R2

SHORT

52

ST6D1

SHORT

6

ST6R1

SHORT

6

ST6R2

SHORT

6

ST7D1

SHORT

ST7R1

SHORT

6

ST7T1

SHORT

50

NCP5331

34

41

29

30

13

14

57

55

23

4 5 6 7 8 57

52

6

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 73/73

REV K7