Dft

Digital Logic Testing Concepts Introduction A test is an evaluation of a product or a process. It typically means different things to different people. In this section, we focus on the basics of developing fault models and cover some basic test pattern development algorithms for digital logic circuits. Practical DFT methodology and DFT tools are covered separately (dfttools.ppt). The basic digital test problem involves three processes: Fault modeling, test pattern generation and fault simulation. This whole process is targeted at detecting manufacturing defects during the IC fabrication process.

Verification and Testing Both Verification and Testing deal with quality. Verification deals with hardware design which verifies the correctness of the design. Logic, timing, formal and physical verification all fall into this. Testing verifies the manufactured hardware meets intended specification (no shorted signals, no open signals and meet performance). Testing is planned during the design process and test vector generation is done after the design is verified. The test vectors are applied after the devices are manufactured. Verification catches design issues and testing catches manufacturing errors.

Design Spec

Verification Process

Design Process Design database Manufacture Process

Testing Process Product

Economics of Testing “How much testing is enough?” is the question come to mind for test and product development engineers. It is obvious that the more testing the better. Unfortunately, the more testing performed, the more cost associated with it. The primary costs in testing digital integrated circuits are: • • • •

Cost of test engineering staff Initial test plan development, Test pattern development Cost of test equipment. Page 1 of 28

On the other hand, if a product is under tested or not tested, it will be returned for repairs or replacement that cost even more. It is even worse if the component is placed on a complex system. It is obvious that we need a way to calculate the amount of testing required to achieve a given defect level. The following is an example used by a 1997 DFT presentation: • • • •

$1.0 to fix an IC (throw it out) $10.0 to find and replace bad IC on a PC board $100.0 to find a bad PC board in a system $1000.00 to find bad component in fielded system

It is obvious that it is better to test an IC before it becomes part of a larger system.

Defect Level (DL) and Yield Relationship The question becomes how much testing is required so that the overall cost of testing is minimal? The following equation is used for such purposes at the IC component level: DL = 1 – Y

(1-T)

Where DL represents the defect level, the fraction of devices shipped with defect. DL must be minimized and ideally close to “0”. Defect level is defined as the percentage of bad parts passing the test process. Y represents the yield of the manufacturing process. The yield needs to be high and this is often in the 90% range. T represents the test percentage. This represents the effort the product design and product test teams put in and it can affect DL. If it is possible to test for all defects (ideally), then we have T = 1, and DL = 1 – Y(1-1) = 0 If no defective units were manufactured (ideally), then we have Y = 1, and DL = 1 – 1

(1-T)

=0

In both cases, no defective units are shipped. If no testing is performed, then T = 0, and DL = 1 – Y which means the defective units shipped will be directly linked to the yield. This equation can be rewritten as following: T = 1 – log (1 – DL) / log (Y) Page 2 of 28

Example: Integrated circuits are manufactured on wafers. If the yield of good dice is 10%, and we want a defect level not to exceed 2%, what percentage of testing must be achieved? T = 1 – log (1-0.02)/log (0.1) = 1 – 0.00877 = 0.99123 Suppose the yield is improved to 20%, What percentage of testing must be achieved to hold DL below 2%? T = 1 – log (1-0.02)/log (0.2) = 1 – 0.01255 = 0.987 How about the yield is 90%? T = 1 – log (1 – 0.02) / log (0.9) = 1 – 0.1917 = 0.8083 Even yield improves from 10% to 90%, the test percentage only changes from 99.12% to 80.83% in order to maintain a defect level of 2%. It is apparent that even very high yield does not automatically ensure low defect level, and products MUST be tested extensively regardless of yields. During testing, some good chips may be rejected due to the quality of test vectors. The percentage loss of good parts is referred to as yield loss.

Types of Tests DC Parameter Test refers to the measurement of steady-state electrical parameters. This is typically the first sets of tests performed. AC parametric Tests refer to the measurements of transient characteristics such as rise times, fall times and clock to output propagation delays. Characterization Test refers to the process of testing the part before it is sent to production. During this phase, functional correctness, AC and DC tests are performed to make sure the part meet all target specification. Burn-in Tests refers to tests that ensure the reliability of the parts. Potential failures are accelerated by placing the parts in ovens at higher temperature. Production Tests refers is typically a subset of the characterization test which will quickly decide if a part is good or bad. Due to the volume of parts and test costs, test time is minimized.

Digital Circuit Test Flow For small number of inputs, the exhaustive testing works well, but as the number of input increases, it becomes impractical. For example, if a circuit has 32 inputs, it would take 7 minutes (232/107/60) to test the circuit if a tester can evaluate 10 million responses per second. If the number of inputs increases to 40, the time it takes to exhaustively test the circuit will take 30 hours. This is assuming the circuit is purely combinational. If the Page 3 of 28

circuit is sequential, exhaustive testing takes even more vectors and consumes more tester time. The pin counts of modern IC components are in the range of hundreds and up to a few thousands. It becomes unfeasible to perform exhaustive functional tests. Manufactured digital circuits are typically tested against a logic model using a set of test vectors. The vectors are either generated by an Automatic Test Pattern Generation Program (ATPG) program or by a design Engineer or a test Engineer manually. The following shows the design and test processes: bad chip

Design Design Fabrication

no yes =?

v Chip

Chips

try more vectors until all vectors pass

Suppose the design under test (dut) is a combinational circuit with n inputs, it will require 2n vectors to verify all the functionality to detect manufacturing defects (the idea is that if the device works for all possible input combinations, then it must be free of manufacturing defects). It was discovered that it takes considerably fewer vectors to detect manufacturing defects than to test the circuit functionalities. ATPG programs create test vectors to detect manufacturing faults instead of trying to test functionality. In the early days of digital testing when the designs were simple, exhaustive functionality test were typically performed.

Combinational Circuit Testing Rarely pure combinational circuits are produced as chips (the TTL chips are examples of such). Combinational logic regions are typically surrounded by sequential elements, so the inputs to the combinational circuits are first transferred to the sequential elements first and then applied to the inputs of the combinational regions. The outputs of the combinational regions are captured into the sequential logic. With this setup, any logic region can be tested and results transferred out. The objective of testing the combinational regions becomes how to find the most effective vectors first. Such vectors can be developed using some of the basic algorithms such as D. With any piece of combinational logic block, it can be tested exhaustively, but this can take a very large number of vectors if the block has a large number of inputs. More effective ways have been discovered over time.

Sequential Circuit Testing Sequential circuits can be easily tested by chaining them together to form a scan-chain. The sequential elements on the scan chain can be tested easily by making sure that all data transition can be passed through this long shift-register.

Page 4 of 28

If the scan chain is not working, then the chip cannot be tested. Once the scan chain is verified, the rest of the combinational circuit can be verified by scan-in vectors and scanout results of combinational regions.

Memory Testing & Repair Conventional logic testing schemes do not work on hard IP blocks such as memories. Memories make up more than 50% of typical high end ASIC design and memories are also fabricated using more aggressive process rules than logic areas. For standard alone memories such as monolithic SRAM and DRAM, it is relatively easy to test using either logic testers or memory testers.

BIST Controler

For embedded memories, most memory blocks cannot be accessed directly through the chip I/O pins. In order to test embedded memories, memory built in self test (BIST) scheme is used to test the memories. The basic idea of memory BIST is to write patterns to the memory under test and read them back to make sure the memory operates properly. Memory BIST can be created either by logic designers or by embedded memory vendors using automatic BIST insertion tools.

BIST Control BIST EN

Read/write control Data and address Memory

BIST Status

As memory blocks get larger, the chance of having defects is quite high. As a result, many embedded memories have redundancy (either as extra columns or extra rows). Memory BIST controllers can be enhanced to automatically repair defective memories based on BIST run results.

Logic BIST Scanning in and out a large number of vectors to test combinational logic regions in a chip can be timing and effort consuming. The idea of build a “tester” inside the chip to test combinational logic regions is quite attractive since it can be activated at anytime with a simple tester or even without a tester. The major components of logic BIST include a vector generator, an output compressor and a controller. A signature can be generated at the end of the test. Page 5 of 28

vector generator

test output compressor

circuit under test

Controller & Output compare

Signature The idea is good, but logic BIST has never become popular for various reasons including ease of use of the tools and lack of industry standard.

System Level Testing

Systems are made of multiple chips using Printed Circuit Boards (PCB). Typically only good chips are used on the PCB. However, the connections among the different chips may not be properly connected. As the PCB get smaller and smaller and the number of chips on a typical board grows, the industry came up with a standard around 1990. This is the so-called IEEE standard 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture. The basic idea is to create a long shift register using all the chip I/O cells. With this approach, all board level signals can be verified to make sure that all chips are properly mounted. Over time, the Test Access Port (TAP) controller has been used for other purposes including activating chip level functions such as BIST. FPGA and CPLD vendors also utilize the TAP ports for device programming.

DFT Tools & Vendors

The following companies offer commercially available test development tools(as of February, 2007): Synopsys Inc: DFT Compiler, BSD Compiler & TetraMAX Mentor Graphics Corp: FlexTest, DFTAdvisor & FastScan LogicVision Logic & Memory Bist Tools LogicVision is the only EDA-company that focuses solely on DFT. It was able to IPO during the peek of telecommunication boom. The company has been doing quite poorly during the last few years. A few smaller DFT specialist companies have either reduced or gone out of business.

Automatic Test Program Generation (ATPG) Page 6 of 28

Although there are many ways to model defects in the IC manufacturing process, but most of them have not been in practical use. There are a very small number of tools in the ATPG domain. The most commonly used fault model is the so-called “stuck-at” faults. Modeling stuck-at faults on technology library component inputs and outputs are the most commonly used scheme for ATPG programs.

Page 7 of 28

Types of Tests & Fault Models Starting from the late 1950’s, the focus has been on hardware defects rather than logic function. Instead of using logic function models, fault models were used to derive test vectors. The focus changed to detecting manufacturing defects as design size and complexity increased over time and fault models were used to reduce the number of vectors used to uncover hardware defects. In semiconductor industry, manufacturing defects are typically caused by the following: 1. Extra or missing material. Extra materials are mostly due to dust particles on the mask or wafer surface during manufacturing process. Missing material can be caused by excessive removal of material from the wafer surface. 2. Oxide Breakdown Caused by insufficient oxygen at the interface of silicon and silicon dioxide, chemical contamination and silicon crystal defects. 3. Electro-migration Mainly due to the move of metal atoms when current flows through the wire. Aluminum is often used for metal wiring, and due to its lower melting point, it is more subject to metal migration. The following are the types of testing methods used over time: • • •

Exhaustive tests – tests that apply every possible input vector including nonvalid function modes. Major problem is that it takes extremely long time. Functional tests – tests that apply every function of the device. Major problem is that it takes an expert to generate vectors for each of the functions of the device. Fault Model derived tests – tests that apply a test for every “modeled” fault or defect type. Major problem is that it only detects the modeled faults. This is the method currently used by all IC manufactures.

A fault model is a computer model used by ATPG programs to create tests to defect these specific defects. The following are some of the most commonly used fault models.

Page 8 of 28

Stuck-at fault model The stuck-at-x faults, where x can be either “0” or “1”, are used to model faults on the inputs and output ports of a logic gate. When an input/output net is stuck-at-0 (s-a-0), it is equivalent to tie the net to ground. When an input/output net is stuck-at-1 (s-a-1), it is equivalent to tie the net to VCC. There can be multiple stuck-at faults and single stuck-at faults. Single stuck-at faults are the most commonly used fault models. All EDA tools support the single stuck-at faults for test vector generation. s-a-0

Stuck-Open Faults These faults refer to a physical line in the circuit is broken. The resulting unconnected node is not tied to either “1” or “0”. This type of fault is typically modeled by using multiple stuck-at faults. Algorithms for this type of faults are less developed.

Bridging Faults Bridging faults usually refer to the short and/or open of more than one nets. If a signal line is shorted to ground or to a voltage source, it can be modeled as s-a-0 or s-a-1. The most common bridging faults are those with signals shorted to each other.

Bridging faults by shorts

“Or”-type of bridging faults is created if pull-up is stronger than pull-down. “And”-type of bridging faults is created if pull-down is stronger than pull-up.

Page 9 of 28

Delay Faults It is possible that a circuit is free of structural defects but the delay along one or more signal paths is excessive. Simply propagating 1 and 0 along the paths, while sufficient to detect stuck-at faults, is not sufficient to detect delay faults since the signal being propagated to a flip-flop or a primary output may have the same value that existed on the preceding clock period. In order to detect delay faults either a rising or falling edge must be propagated through the paths of interest.

Chip

∆t

1

chip ok if a logic 1 is captured.

Parametric Fault Parametric faults refer to those faults that prevent a chip from performing compliance with its specification. These faults that affect the circuit performance are referred to as parametric faults. In contrast to the logic faults, parametric faults can affect voltage and current levels as well as the speed of the circuit. Parametric faults in components can result from improper fabrication or from degradation as a consequence of a normal aging process. Environmental conditions such as temperature extremes, humidity, or mechanical vibration may accelerate the degradation process. Design problems can produce symptoms similar to parametric faults. They include failure to take into account wire lengths, loading of devices, inadequate decoupling and failure to consider worst-case conditions such as maximum or minimum voltages or temperatures over which a device may be required to operate.

Page 10 of 28

Test Vector Generation and Fault simulation There are two ways to test stuck-at faults: XOR method and Structural search method. The XOR method is straight forward, but it is memory and computation intensive. The XOR method was never popular in real applications. The structural search method is more practical and has been widely used in the industry for ATPG (automatic test pattern generation).

Fault Coverage

Fault Coverage refers to the percentage of total faults for which test patterns have been generated. Fault Coverage = (number of detected faults) / (Total number of faults in CUT) % Stuck at faults are the most likely faults during manufacturing of IC devices. Most commercial tools detect stuck-at faults. The following are some commonly used algorithms in test generation. Example: If the buffer input A is shorted to Power line, the “defect” is “A” shorted to power line during manufacturing.

A

Z

The fault for this defect is “A” stuck-at 1. Good circuit is supposed to give zero at Z when a zero is applied to A input. When A is stuck-at 1, Z will give an error of “1” when zero is applied to the input.

Page 11 of 28

The XOR Method The exclusive OR function has the following properties: 1. F ⊕ F = 0 2. F ⊕ 0 = F (controlled inverter) 3. F ⊕ 1 = F’ (controlled inverter) 4. F ⊕ G = G ⊕ F 5. G = F ⊕ F ⊕ G 6. F + G = F ⊕ G ⊕ F G 7. F G ⊕ F H = F (G ⊕ H) 8. F(x) = xi F(x1,…,1,…,xn) ⊕ xi’ F(x1, …, 0, …, xn) Based on the property of the exclusive or, we can perform ⊕ function on the good circuit and the faulty circuit with a given fault. If the result of such an operation is “1”, not constantly zero, then the fault can be detected. If the result is “0”, then the fault cannot be detected since no matter what inputs are used, the bad circuits always generate the same results as good circuits. It is very likely that the circuit contains redundancy and the fault is not detectable. The problem becomes finding a vector ‘v” such that the output is “1”.

v

good circuit 1 faulty circuit

Page 12 of 28

Example 1: Given a multiple level network f = (g * h)’, g = a + b, and h = bc, use the xor method to find vectors to detect s-a-0 and s-a-1 faults at g output. a b

c

s-a-0 or s-a-1

a b c

The question becomes find a vector for (a,b,c) such that g = f ⊕ f_fault =1. In case of s-a-1: g = (bc)’ ⊕ ((a+b)bc)’ = bc((a+b)bc)’ + (bc)’ (a+b)bc = bc((a+b)’ + (bc)’) = bc(a+b)’ = bc(a’b’) =0 Therefore, the fault is not detectable. (It is redundant). In case of s-a-0: g = 1 ⊕ ((a+b)bc)’ = (a+b)bc = abc + bc = (a+b)bc = bc a  −     The test vector is  b  = 1  where a can be either “0” or “1”. c  1     

Page 13 of 28

Example 2: Given a circuit as shown below. If the gate 5 (inverter) is shorted, find a test for the fault. x2 6 5

x1

F x3

9

8

x4

7

The circuit without the fault, F = x4 (x1’ + x2) (x1 + x3) With the fault, F* = x4 (x1 + x2) ( x1 + x3) F ⊕ F* = F’ F* + F F*’ = (x4’ + x1 x2’ + x1’ x3’)(x1x4 + x1x3x4 + x1x2x4 + x2x3x4) + (x1’ x3x4 + x1x2x4 + x2x3x4)(x4’ + x1’ x2’ + x1’ x3’) = x1 x2’ x4 + x1’ x2’ x3 x4 = x2’ x4 (x1 + x1’ x3) = x2’ x4 (x1 + x3) From the above equation, we can see that if we choose x2 = 0 and x4 = 1, a logic “1” on either x1 or x3, we will be able to produce different outputs for the good circuit and faulted circuit. Therefore, we have a test for the fault. For functions that are larger than 4 variables, it becomes extremely difficult to derive vectors using the method as shown above. There are algorithms used to simplify the process, but they are not very practical and they are rarely used in practice. As can be seen that the XOR method can accommodate different types of fault as long as a functional model can be derived and the functions themselves are relatively small and simple to manipulate.

Page 14 of 28

Structural Search Methods The most practical test vector generation methods are those so-called structural search methods. A structural search method consists of three steps: 1. Fault Excitation 2. Fault Propagation 3. Justification

Fault Excitation

Fault excitation refers to the process of assigning a logical value opposite to the fault value. In the example, a logical value of “0” is assigned to “c” which is opposite of the value of the net “s-a-1”. Example: a b

f sa1

c=0

Fault Propagation

Sensitization Path refers to a path chosen to propagate the fault. It is a signal path originating at the fault origin whose value all along the path is functionally dependent on the presence or absence of the fault. The process of creating a sensitized path is called fault propagation, which is the process of driving the circuit to a state where the error becomes observable at the primary outputs. For simple gates (“and”, “or”, “nand”, “nor”), a controlling value determines the gate’s output regardless of values at other inputs. For each of the gates on the path, the other inputs are made non-controlling.

Page 15 of 28

Example: “zero” is a controlling value and “one is non-controlling for “and” and “nand” gates. “one” is a controlling value and “zero” is non-controlling for “or” and “nor” gates.

Fault Justification Fault justification refers to the process of satisfying assignments by backing up to the circuit primary inputs, which means the process of determining the input combination necessary to drive an internal circuit node to a specific value (opposite of the fault value).

Equivalent Faults Equivalent faults refer to a set of faults whose effects cannot be distinguished at the ATE are equivalent to one another. No test pattern exists that can tell them apart. s-a-0

s-a-1

s-a-0

s-a-1 s-a-1

s-a-0

For a two input “NAND” gate, the input s-a-0 and its output s-a-1 are equivalent faults as shown above.

Fault Collapsing By testing for only one fault per equivalent set, the total number of fault population can be reduced therefore fewer test patterns will be needed. After collapsing, only 8 faults are left.

The total number of faults can be calculated by assigning ONE s-a-0 and ONE s-a-1 fault to each instance pin and module port. The total number of stuck-at faults is: 2*(instance pins) + 2 * (design ports) = 2*(11) + 2*5 = 32 The design ports can be collapsed with the instance pins connected to them. After collapsing the design ports, there are 22 faults left. Faults on the same internal nets can be collapsed: 22 – 3*2 = 16 stuck-at faults left. Page 16 of 28

Additional equivalent faults can be collapsed on the “NAND”, “OR” and “NOR” gates. After collapsing all equivalent faults, only 8 faults are left. After collapsing, only 8 faults are left. s-a-1

s-a-0 s-a-1

s-a-0 s-a-0

s-a-1

s-a-0 s-a-0

Page 17 of 28

D-Algebra The D-Albebra contains the following value set {0, 1, D, D’}. The values of D and D’ are defined according to the following table for the good machine (GM) and the faulty machine (FM). FM GM

0

1

0

0

D’

1

D

1

The “D” can be thought of as “different” between good and faulty machines. Under the D-Algebra the following are true: 1. 1 * D = 1 * 1/0 = D 2. 1 + D = 1 + 1/0 = 1 The truth table for INV and AND are given by the following tables: AND 1 0 D D’

1 1 0 D D’

0 0 0 0 0

D D 0 D 0

D’ D’ 0 0 D’

From the above table, an “D” on the input is interpreted as “good” circuit having a “1” and “bad” circuit having a “0”. That is Good circuit will have (“1” AND “1” = 1), “circuit” has (“1” AND “0” = 0) which gives “D” as indicated in the table. INV 0 1 D D’

1 0 D’ D

Page 18 of 28

The D-Algorithm Based on the D-Algebra, the D-Algorithm using the above three sequences: fault excitation, fault propagation and justification. It selects a fault from a list and works from the point of the fault toward inputs and outputs, employing propagation and justification techniques as it proceeds. This algorithm was developed at IBM in 1966. To detect a s-a-0 fault (good circuit “1”, faulty circuit “0”), it necessary to assign {D} to the net and then the {D/D’} needs to be propagated to the output to detect the fault. For each path chosen to propagate {D/D’}, the other inputs along the gates need to be assigned to non-controlling values. It is possible to have conflicting values assigned to the same primary input. The justification fails and a different path has to be chosen to propagate the {D/D’}. {D’} is assigned to a net to detect s-a-1 fault (good circuit “0”, faulty circuit “1”). The remaining task is the same as that for s-a-0 fault. Example 1: Given the circuit below, generate a test for net C s-a-1 fault using the D-algorithm.

a

1 D

b 3

s-a-1 c

2 D’

f

D’

First, assign {D’} to the net, and propagate it through gate 2. Since gate 2 is noninverting, the output net gets {D’}. Since the path through gate 3 is inverting, {D} will be passed to the circuit output f. To pass {D’} through gate2, the other input to gate 2 must be non-controlling. It needs to be 0. This requires primary input b = 0. To pass {D’} through gate 3, the other input to gate 3 must be 1. In turn, this requires that either “a” input or “b” input to be 1. Since b is already 0, we have a test {a=1, b= 0, c = 0}.

Page 19 of 28

In circuit that contain a large number of re-convergent fan-out nets, such as parity checking, error detection & correction and arithmetic functions, the D-algorithm can result in a large number of conflict situations (All due to the XOR circuit). These conflicts result from the fact that the justification process, proceeding back toward the primary inputs along two or more paths, frequently arrives at a point where signals converge with conflict requirements. To resolve this problem, one way is to try different signal propagation paths and it is unlikely a test can be easily found. Another way to find a test for such convergent fanout rich circuit is to propagate the {D/D’} along multiple paths concurrently. This is the more likely way of avoiding the conflicts. Example 2: Derive a test for the output of gate 1 s-a-1 in the following circuit. D 3

a b

D’

1

4 sa1 D’ 2

Suppose the path gate 3 to gate 4 then to the output is chosen. The {D/D’} values are labelled in the diagram. The requirement on gate 1 is that {a=1, b = 1}. To propagate {D’} through gate 3, the first input to gate 3 must be logic 1 and this gives {a = 1} which is consistent so far. To propagate D through gate 4 requires that the other input of gate 4 be 1. To get logic 1 at the output of gate 2 requires that the second input to gate two be 0. [The other input is {D’}]. This conflicts with {a=1, b= 1} required by gate 1. Therefore, the single path propagation approach in this case is not working.

Page 20 of 28

Example 3: Use the concurrent {D/D’} propagation method, re-work the previous example: Now, suppose we propagate the D’ to both gate 2 and gate 3 at the same time, then we have the diagram shown below: After the {D’} is propagated concurrently towards the primary output, we have the following {D, D’} values shown. For the {D’} to pass through gate 2 and gate3, it is required that the other inputs to both gate 2 and gate 3 be 1. Once this is selected, there are no conflicts for any of the primary inputs. D 3 a b

1

4 sa1 D’

2

D

Page 21 of 28

D’

The PODEM Algorithm The problem with the D-Algorithm is that in the justification process, where proceeding backward traces towards the primary inputs along two or more paths frequently arrive at a point where signals converge with conflicting requirements. As a result, the D-algorithm must find a node where an arbitrary decision was made and choose an alternative assignment. This can be very time consuming and memory intensive. The PODEM (path oriented decision making) test generation algorithm addresses the problem of uncontrollably large numbers of re-made decisions by selecting a fault and then working directly at the inputs to create a test. The PODEM algorithm uses the popular branch-and-bound technique. The algorithm was developed by P. Goel in 1981. He is also the founder of the company that started Verilog HDL.

The PODEM algorithm

PODEM begins by assigning unknown {x} to all inputs. It then starts assigning arbitrary values to the primary inputs. The assignments are propagated forward (eliminating the need for timing consuming justification process). If either of the two conditions is true, the assignment is rejected: 1. The signal net for the stuck-at fault being tested has the same logic level as the stuck-at level (good and bad have the same behavior). 2. There is no signal path from an internal signal net to a primary output such that the internal signal net has value {D} or {D’} and all other nets on the signal path are at {x}. (note: {x} implies the nets do not assume values by the current input value) The first condition excludes input combinations that cause the good machine and the faulted machine to assume identical values at the site of the fault. The second condition excludes input combinations that cause all possible paths from the sensitized path to outputs to become blocked. When making assignments to primary inputs, podem employs a “branch-and-bound” method. The process is viewed as a tree as show below. An assignment is made to a primary input and if it does not violate condition 1 and condition 2, the assignment is retained and a branch is added to the tree.

Page 22 of 28

Branch-and-bound algorithm used in podem p4=0 p2=0 p1=0

start

p4=1

p2=1 p3=0

p4=0

p1=1 p3=1 p4=1

If a violation results, the assignment is rejected and the node is flagged and that branch is bounded. If the node had been previously flagged, then the node is completely rejected and it is necessary to backup in the tree until an unflagged node is encountered. The process continues until a successful test is created or the process returns to the start node. If the process returns to the start node, then no test is found and a test for the given fault does not exist. The criterion for a successful test is the same as that employed by the D-algorithm, namely that a {D} or {D’} has been propagated from the point of the fault to a primary output.

Page 23 of 28

Example: Use the podem algorithm to find a test for a s-a-0 (need “D” at the faulty node) fault at the output of the “or” gate (gate 8). p1

9

p2 p3

6 8

p4 p5

s-a-0

7

The primary inputs p1 to p5 are assigned values and the assignments are checked against the two conditions. The following steps are used: 1. Assign p1 = 0 results in the output of gate 9 to go to “1”. This blocks the fault from propagating to the output. It violates condition 2 and it is rejected. 2. (backup) Assign p1 = 1 does not violate either condition. 3. Assign p2 = 0 does not violate either condition. 4. Assign p3 = 0 does not violate either condition. 5. Assign p4 = 0, the output of gate 8 goes to “0”. It violates condition 1. 6. (backup) Assign p4 = 1 does not violate either condition. 7. Assign p5 = 0, the output of gate 8 goes to “0”. It violates condition 1. 8. (backup) Assign p5 = 1 does not violate any conditions. 9. We have a test, {1,0,0,1,1} for the output of gate 8 sa0. The fault free circuit takes on the value 0 and the faulted circuit takes the value of 1. Podem decision tree

p1=1 p2=0

p1=0 rejected violates condition 2.

p3=0

p4=0 rejected. violates condition 1

p4=1

p5=0 rejected. violates condition 1

p5=1

Selection of inputs and assignment of initial values can influence the success of the podem algorithm. Therefore, when implementing the algorithm, additional capabilities on selection of initial primary inputs and the logic values that have a high probability of helping podem to create a test added to the implementation. Typically, a backtrace process is added to podem, which starts at the gate under test or some other gate where assignments must be made to propagate a test and traces back to the primary inputs. Along the backtrace, it is noted which binary value is most likely to meet the test objective. Page 24 of 28

This back trace operation appears quite similar to the justification process in the Dalgorithm. The major difference is that this back trace process does not require that assignment be justified. It is not part of the podem algorithm to perform the trace back. It is added to speedup the algorithm by helping it to select inputs and logic values with a high probability of success. The inputs and values chosen by the trace back may be rejected by the algorithm.

Page 25 of 28

Iddq Test All of the test techniques discussed above used voltage levels to determine faults. Many defects in CMOS circuits can be detected using current levels. A static CMOS gate consumes current only when switching, and the Quiescent current for CMOS devices (Iddq) is typically in the fA (10-15) range. Most physical defects in CMOS gates raise the Iddq current level by many orders of magnitudes. The advantage of Iddq is obvious, but the disadvantages include the following: • • • • • •

Require precision equipments since the current level is very low. It is hard to determine the threshold for bad devices. The whole circuit must contain static gates (which means they are slower) No pull up or down can be used. Sense amplifier in memory draws significant static current. So it becomes hard to apply to devices contain memory blocks. Internal bus can be a problem for Iddq test.

Page 26 of 28

Sequential Test Generation A sequential circuit model like the one shown below is used to generate tests for sequential circuits. In this circuit model, sequential portion and combinational portion of the circuits are separated and the circuit is represented as a finite state machine. In the following discussion, we assume that all the registers are fault free. inputs

combinational logic

registers

P.S.

outputs

N.S.

Using the above model, the sequential logic testing generation problem contain the following sub-prolbmes: 1. Need a way to drive the P.S vector from unknown state to a known state. 2. Need a way to bring out N.S. vector after a known vector is applied to P.S. Essentially, we need a way to apply the P.S. vector and a way to bring out the N.S. vector. Once this problem is resolved, the sequential circuit test problem is converted into a combinational logic test problem as shown below:

inputs

Combinational Portion of the Circuit

P.S.

outputs

N.S

The new combinational circuit model consists a new set of inputs and outputs: {inputs, P.S. } and {outputs, N.S.}. The following diagram illustrate the sequence we expect: P.S. = X

apply a vector to inputs

apply a vector to P.S.

Capture {D/D’} on N.S. & shift out.

Scan Design

time

In order to convert a sequential test problem into a combinational problem, we need to modify the state registers such that it becomes a shift register to shift in the P.S. and shift out the N.S. vectors. The state registers are modified in such a way Page 27 of 28

that when test mode is enabled, the state registers are configured into a shift register to shift in a P.S. vector, and to shift out a set of {D/D’} from the N.S. If this scheme is applied to all registers, then we have full scan. Otherwise we have partial scan. The following example is used to show how a non-scan design is converted into a scan design: inputs

outputs

P.S.

N.S. R3

P.S.

R2 N.S.

mux

R3

mux

Combinational Circuit

R2

R1 scan out

mux

R1

scan in test pin

In the above circuit with a scan chain, a “test pin” is used to control the mode of operation. If “test pin” is logical 0, the original circuit is restored. If “test pin” is logical 1, then the registers become a shift register. This shift register can be used to shift a vector for P.S. into the circuit and shift the set of {D/D’} to the output of the circuit from N.S. The scan chain insertion can be automatically done by a test program or by an ASIC vendor supplied utility. For a scan-based design, the following procedure can be used to test a sequential circuit: 1. Generate a vector for the combinational circuit with new inputs = {original inputs and P.S.} and new outputs = {original outputs and N.S.} 2. Shift in the P.S. portion of the test vector by setting “test pin” to 1 and then clock in the P.S. vector. 3. Apply the additional input vectors at the chip primary inputs. Now the whole input vector is complete for the combinational circuit. 4. Capture portion of the outputs at the primary outputs. 5. Shift out the N.S. portion by setting “test pin” to 0 and then clock once. This will capture the N.S. into the shift register. 6. Set “test pin” to 1 and shift out the N.S. portion of the output vectors. Now the whole output portion is complete. 7. Continue with the above steps until it the expected vectors fail or until all the vectors are exhausted. Page 28 of 28