Csa.docx

UID: 17BCA1479 NAME: SHIKHA DHADWAL CLASS: BCA-4D ASSIGNMENT 2 COMPUTER SYSTEM ARCHITECTURE GROUP 4 SUBMISSION DATE: 02-04-2019

1. Explain memory-reference instructions. Ans. Memory Reference Instructions memory reference instructions are those commands or instructions (in assembly language, these are a group of letters and are shown in examples below) which are used to make a reference to the memory and allow a program to access the required data from where the data is stored. An instruction consists of an operand and operand code is that which specifies the data that is to be operated or manipulated (operations like addition, subtraction etc. are performed on this data specified by operand). An address is also a part of the instruction if it is used in direct addressing mode (in which memory address of the value is declared in the instruction itself) and this address represents the location of the value in the memory. There are 7 memory reference instructions as below.  LDA  STA  AND  ADD  BUN  BSA  ISZ For the memory reference instructions, you can compare the below flow chart with the figure below that represents the step by step operations performed to execute each of these instructions.

LDA LDA // this instruction is used to load the Accumulator with a value that is located at a specific memory location. The correct usage of this command when we write in an assembly language is as follows: Example of LDA 2500 H This command says that load the value that is stored at the memory location 2500 into the accumulator (a temporary storage area).H represents that the entered address is a hexadecimal memory address. So, when a value is stored in the

accumulator, further operations are performed as required by the user on that value. The changes made to the value stored in the accumulator are updated in regular time intervals. In excess, this instruction comes under direct addressing mode that is the address or memory location of the operand is written in the instruction itself. Opcode

Operand

Description

LDA

16 bit address

Load the accumulator

STA STA //this instruction is exactly opposite to the above one as this memory reference instruction stores the value that is present in the accumulator into a specific memory address that is given to the instruction. Example of STA 2600 H This command says that store the value that is stored in the accumulator to the memory location 2600. When the accumulator is to be assigned with a new value and the present value is to be sent back to some memory location, this instruction is used. In excess, this instruction also comes under direct addressing mode. Opcode

Operand

Description

STA

16 bit address

Store accumulator direct

AND AND //this instruction performs AND operation on the values stored in accumulator and memory location and the resultant is stored in the accumulator that is the previous value in the accumulator is updated with this new result. In assembly language, this instruction is not written as AND but is used as written in the example below: Example of ANA M //don’t confuse, AND is written as ANA but not AND. This command says that perform logical AND operation on the value stored in accumulator and at memory location specified by M as an operand. Here in the above example, the right most A in ANA stands for accumulator and M stands for memory location represented with H-L pair. Observe the below table. Opcode Operand ANA

ADD

R M

Description Logical AND with register or memory with accumulator

ADD //this instruction performs arithmetic operation (addition) on the values stored in the accumulator and memory location. The resultant after addition is stored in the accumulator by replacing the older value. This instruction is written as below in order to perform addition on two values. Example of ADD B This command performs adds the value stored in the accumulator with value at memory location specifies by B as an operand. The operand can be a letter that represents the memory location of the value. Here it is taken as B. There are various types of additions which are discussed below. Opcode

Operand

Description

ADD

B

Add register or memory to accumulator

Other additions and their examples that can be performed using this instruction are as follows: ADC M //this instruction performs addition with carry (carry is a value obtained after addition of the left most digits of both the numbers) by adding the values in accumulator and memory location specified by M as an operand. ADI 45 H //this instruction says add immediate the value stored in accumulator with the 8 bit data. ACI 45 H //this instruction says that add immediate along with carry. DAD B // If we want to perform a hexadecimal addition, we use this instruction. This instruction performs addition of the 16 bit value in the register pair with the value in H-L pair. BUN BUN // BUN stands for branch unconditionally and this instruction allows one to select an instruction from a program (which is a group of instructions) and gives him access to modify the program as he wants to. Example of how to write this instruction in programs is as follows: Example of D4T4: PC <- AR, SC <- 0 //Observe the below table to understand the functionality of BUN instruction. Opcode

Operand

Description

BUN

16 bit address

Branch unconditionally

BSA BSA // BSA instruction in computer architecture stands for branch and save return address which means it performs two functions. Branching means the instruction is currently being executed may have sub routines or procedures within it and returning the address in the sense it stores the address of the

instruction which should be executed immediately after it and is stored as program counter. Example of D5T4 : M[AR] <- PC, AR <- AR + 1 // increments the value of address register (AR) and returns the value of program counter D5T5 : PC <- AR, SC <- 0 Opcode

Operand

Description

BSA

16 bit address

Branch and save return address

Difference between branch unconditionally (bun) and branch and save return address (bsa): Difference between bun and bsa is that in BUN, unconditional branching and no saving of address but allows program modification whereas in BSA, Branching and saving the returned address but no program modification is allowed. ISZ ISZ //ISZ stands for Increment and skip if zero that is this instruction is used for incrementing the value at the specific address and if the value at that address is found to be zero, then this instruction makes the program counter get incremented by 1. Example of D6T4: DR <- M[AR] //assigning the memory location held by address register to data register. D6T5: DR <- DR + 1 //increments the value of data register. D6T4: M[AR] <- DR (if DR = 0, then PC = PC+1 and SC=0) //incremented address in data register is now assigned back to address register. Opcode

Operand

Description

ISZ

16 bit address

Increment and skip if zero

Take a look at the the following table to know the instructions and their symbolic description. Symbol

Operation Decoder

Symbolic Description

AND

D0

AC ← AC /\ M[AR]

ADD

D1

AC ← AC + M[AR] →, E ← Cout

LDA

D2

AC ← M[AR]

STA

D3

M[AR] ← AC

BUN

D4

PC ← AR

BSA

D5

M[AR] ← PC , PC ← AR + 1

ISZ

D6

M[AR] ← M[AR] + 1, if M[AR] + 1 = 0 then PC ← PC + 1

Example on Memory Reference Instructions Let us take an example of stepper motor which can be rotated using a piece of code in assembly language which is given below: MOV AL,0A

OUT 20,AL CALL 2000 // Used to make a delay in rotation of the rotor. MOV AL,06 OUT 20,AL CALL 2000 MOV AL,05 OUT 20,AL CALL 2000 MOV AL,09 OUT 20,AL CALL 2000 JMP 1004 //This instruction helps the whole code run continuously again and again by jumping to the initial memory location. HLT //This terminates the program. 2. Which addressing mode/s uses the PC instead of a general purpose register ? Ans. Addressing Modes– The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode

specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed. Relative addressing mode/s uses the PC instead of a general purpose register. Relative addressing specifies the operand address relative to the instruction location. This is accomplished by using the PC as an index register. The PC is considered as a base address. The offset, the distance between the location of the operand and the PC, is held in the index word of the instruction. When the effective address is relative to the program counter (current instruction, also known as the "PC"). For example, this would let you access a data block that had been assembled into the program. It can also be used for relative jumps.

3. Elaborate the importance of different addressing modes in computer architecture with suitable example. Ans. The addressing modes is a really important topic to be considered in microprocessor or computer organisation. The addressing modes in computer architecture actually define how an operand is chosen to execute an instruction. It is the way that is used to identify the location of an operand which is specified in an instruction. Whenever an instruction executes, it requires operands to be operated on. An instruction field consisting of opcode and operand. Where operand means the data and opcode means the instruction itself. In case of operations like addition or subtraction, they require two data. So, they are called binary instruction. On the other hand, the increment or decrement operations need only one data and are so called unary instruction. Now the question is how these data can be obtained. The various addressing modes in computer architecture can be classified as below. We have some other addressing modes too, but these are the prime addressing modes in computer architecture.

Addressing modes in computer architecture: 

Implicit



Immediate



Direct



Indirect



Register



Register Indirect



Displacement o

Relative

o

Base register

Indexing Implicit addressing mode : o

The term implicit addressing mode means here we are not mentioning clearly in details that from where the instruction can get the operand. But by default, the instruction itself knows from where it is supposed to access the operand. For example, CMA stands for complement accumulator. The meaning of the CMA instruction is whatever the value present in the accumulator will be replaced by its 1’s complement. In this instruction CMA or along with this instruction, we are not mentioning any operand. So here it knows that the operand has to be accessed from the accumulator implicitly. This is known as implicit addressing modes. Immediate addressing mode : In the immediate addressing mode, the instruction contains two fields. One for the opcode and another field contains the operand itself. That means in this addressing mode, there is no need to go anywhere to access the operand because of the instruction itself containing the operand. This is known as immediate addressing mode.

Direct addressing mode : In the direct addressing mode, the instruction will have the two parts. One part will contain the opcode and another one will contain the address of the memory location at where the operand can be found. Here A is the address of the operand. That means at the Ath location in the memory, the operand can be found.

Indirect addressing mode : Indirect addressing mode contains the opcode and address field. But unlike direct addressing mode, it doesn’t contain the address of the operand but contains the address of a memory location in which the actual address of the operand can be found.

Here A contains the address of the location B in memory and B contains the actual address of the operand in memory.

Register addressing mode: In case of register addressing mode, the instruction will have the opcode and a register number. Depending upon the register number, one of the registers will be selected from the available sets of registers by default automatically. The unique identification of the register can be done by the register number which is mentioned in the instruction. In that register, the operand can be found.

Register indirect addressing mode : In the register indirect addressing mode, the instruction will contain the opcode as well as a register number. Depending upon the register number mentioned in the instruction, the corresponding register will be accessed from the set of registers. But here the register doesn’t contain the operand but will contain the address of the operand in the memory at where the operand can be found.

Suppose in memory, the operand is in the Ath location. Now, this address A will be stored in the register and the register number say R will be mentioned in the instruction. This is called register addressing mode. Displacement addressing mode : In the displacement addressing mode, the instruction will be having three fields. One for the opcode, one for the register number and the remaining one for an absolute address. At first, depending upon the register number the register will be selected from the register set. After that its content will be added with the absolute address and the new address formed will be the actual physical address of the operand in the memory.

Displacement addressing mode in computer architecture can be categorized into 3 different modes. 1. Relative 2. Base register 3. Indexing In case of relative addressing mode, the register used will be a program counter. In the base addressing mode, the register will contain the base address and the absolute field will be the offset or displacement from the base address. After adding both the actual physical address of the operand can be obtained and mapping this address in the memory we can access the operand. For example, if the base address is 3000 and the offset is 20, then after adding both i.e. 3020 will be the actual address of the operand. In case of Indexing mode, the absolute field will contain the starting base address of the memory block and the register field will contain the index value. Adding both will give the actual physical address of the operand. 4. Draw detailed flowchart of the instruction cycle. Indicate the conditions in which register-reference / memory-reference and inputoutput instructions are executed. Also include the interrupt cycle micro-operations in the flowchart.

Ans. The Instruction Cycle –

Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-operations. In the above examples, there is one sequence each for the Fetch, Indirect, Execute and Interrupt Cycles.

The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always followed by the Fetch Cycle. For both fetch and execute cycles, the next cycle depends on the state of the system.

We assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC designates the state of processor in terms of which portion of the cycle it is in:-

00 : Fetch Cycle 01 : Indirect Cycle 10 : Execute Cycle 11 : Interrupt Cycle At the end of the each cycles, the ICC is set appropriately.The above flowchart of Instruction Cycle describes the complete sequence of micro-operations, depending only on the instruction sequence and the interrupt pattern(this is a simplified example). The operation of the processor is described as the performance of a sequence of micro-operation. Different Instruction Cycles: 1. The Fetch Cycle – At the beginning of the fetch cycle, the address of the next instruction to be

executed is in the Program Counter(PC).

2. Step 1: The address in the program counter is moved to the memory address register(MAR), as this is the only register which is connected to address lines of the system bus.

Step 2: The address in MAR is placed on the address bus, now the control unit issues a READ command on the control bus, and the result appears on the data bus and is then copied into the memory buffer register(MBR). Program counter is incremented by one, to get ready for the next instruction.(These two action can be performed simultaneously to save time)

Step 3: The content of the MBR is moved to the instruction register(IR).

Thus, a simple Fetch Cycle consist of three steps and four micro-operation. Symbolically, we can write these sequence of events as follows:-

Here ‘I’ is the instruction length. The notations (t1, t2, t3) represents successive time units. We assume that a clock is available for timing purposes and it emits regularly spaced clock pulses. Each clock pulse defines a time unit. Thus, all time units are of equal duration. Each microoperation can be performed within the time of a single time unit. First time unit: Move the contents of the PC to MAR. Second time unit: Move contents of memory location specified by MAR to MBR. Increment content of PC by I. Third time unit: Move contents of MBR to IR. Note: Second and third micro-operations both take place during the second time unit. 3. The Indirect Cycles – Once an instruction is fetched, the next step is to fetch source operands. Source Operand is being fetched by indirect addressing. Register-based operands need not be fetched. Once the opcode is executed, a similar

process may be needed to store the result in main memory. Following micro-operations takes place:-

Step 1: The address field of the instruction is transferred to the MAR. This is used to fetch the address of the operand. Step 2: The address field of the IR is updated from the MBR.(So that it now contains a direct addressing rather than indirect addressing) Step 3: The IR is now in the state, as if indirect addressing has not been occurred. Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment to consider the Interrupt Cycle . 4. The Execute Cycle The other three cycles(Fetch, Indirect and Interrupt) are simple and predictable. Each of them requires simple, small and fixed sequence of micro-operation. In each case same micro-operation are repeated each time around. Execute Cycle is different from them. Like, for a machine with N different opcodes there are N different sequence of micro-operations that can occur. Lets take an hypothetical example :-

consider an add instruction: Here, this instruction adds the content of location X to register R. Corresponding micro-operation will be:-

We begin with the IR containing the ADD instruction. Step 1: The address portion of IR is loaded into the MAR. Step 2: The address field of the IR is updated from the MBR, so the reference memory location is read. Step 3: Now, the contents of R and MBR are added by the ALU. Lets take a complex example :-

Here, the content of location X is incremented by 1. If the result is 0, the next instruction will be skipped. Corresponding sequence of microoperation will be :-

Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not) and action (PC is incremented by 1) can be implemented as one micro-operation. Note : This test and action micro-operation can be performed during the same time unit during which the updated value MBR is stored back to memory.

5. The Interrupt Cycle: At the completion of the Execute Cycle, a test is made to determine whether any enabled interrupt has occurred or not. If an enabled interrupt has occurred then Interrupt Cycle occurs. The natare of this cycle varies greatly from one machine to another. Lets take a sequence of micro-operation:-

Step 1: Contents of the PC is transferred to the MBR, so that they can be saved for return. Step 2: MAR is loaded with the address at which the contents of the PC are to be saved. PC is loaded with the address of the start of the interrupt-processing routine. Step 3: MBR, containing the old value of PC, is stored in memory. Note: In step 2, two actions are implemented as one micro-operation. However, most processor provide multiple types of interrupts, it may take one or more micro-operation to obtain the save_address and the routine_address before they are transferred to the MAR and PC respectively.

5. An instruction is stored at location 350 with its address field at location 351. The address field at location 351. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is (i) Direct (ii) Immediate (iii) Relative (iv) Register indirect (v) Index with R1 as the index register.

Ans. Immediate addressing mode : In the immediate addressing mode, the instruction contains two fields. One for the opcode and another field contains the operand itself. That means in this addressing mode, there is no need to go anywhere to access the operand because of the instruction itself containing the operand. This is known as immediate addressing mode.

Direct addressing mode : In the direct addressing mode, the instruction will have the two parts. One part will contain the opcode and another one will contain the address of the memory location at where the operand can be found. Here A is the address of the operand. That means at the Ath location in the memory, the operand can be found.

Indirect addressing mode : Indirect addressing mode contains the opcode and address field. But unlike direct addressing mode, it doesn’t contain the address of the operand but contains the address of a memory location in which the actual address of the operand can be found.

Here A contains the address of the location B in memory and B contains the actual address of the operand in memory. Register addressing mode: In case of register addressing mode, the instruction will have the opcode and a register number. Depending upon the register number, one of the registers will be selected from the available sets of registers by default automatically. The unique identification of the register can be done by the register number which is mentioned in the instruction. In that register, the operand can be found.

Register indirect addressing mode : In the register indirect addressing mode, the instruction will contain the opcode as well as a register number. Depending upon the register number mentioned in the instruction, the corresponding register will be accessed from the set of

registers. But here the register doesn’t contain the operand but will contain the address of the operand in the memory at where the operand can be found.

Suppose in memory, the operand is in the Ath location. Now, this address A will be stored in the register and the register number say R will be mentioned in the instruction. This is called register addressing mode. Displacement addressing mode : In the displacement addressing mode, the instruction will be having three fields. One for the opcode, one for the register number and the remaining one for an absolute address. At first, depending upon the register number the register will be selected from the register set. After that its content will be added with the absolute address and the new address formed will be the actual physical address of the operand in the memory.

Displacement addressing mode in computer architecture can be categorized into 3 different modes. 4. Relative 5. Base register 6. Indexing In case of relative addressing mode, the register used will be a program counter. In the base addressing mode, the register will contain the base address and the absolute field will be the offset or displacement from the base address. After adding both the actual physical address of the operand can be obtained and mapping this address in the memory we can access the operand. For example, if the base address is 3000 and the offset is 20, then after adding both i.e. 3020 will be the actual address of the operand. In case of Indexing mode, the absolute field will contain the starting base address of the memory block and the register field will contain the index value. Adding both will give the actual physical address of the operand.