Computer Organization- Pipe Lining

What is Pipelining Pipelining is an implementation technique that overlaps multiple instruction execution. MIPS instructions takes 5 steps 1.Fetch instruction from memory [ IF ] 2.Read insrtuction while decoding instruction. [ ID ] 3.Execute operation or calculate an address. [EX] 4.Access an operand in data memory. [ MEM ] 5.Write the result into registers. [ WB ]

Example (without pipelining)

Five steps are involved in the lw fetch and execution. Time taken to complete each step is as follows: Instruction fetch: Register read: ALU: Memory read: Register write:

200 ps 100 ps (for base value) 200 ps (for memory address) 200 ps (for reading data from memory) 100 ps (for register write)

Execution time for lw instruction = 800 ps Execution time for a sequence of 3 lw instructions = 2400 ps

Example (with pipelining) Since the lw instruction is divided into five steps, a 5 stage pipeline is employed.  

Each pipeline stage takes one clock cycle. Clock cycle for a pipeline stage must be long enough to accommodate the slowest operation (200 ps in our example).

Figure 6.3

Nonpipelined versus pipelined execution of 3 lw instructions

Tthe total execution time for the sequence of 3 lw instructions is 1400 ps

Figure 6.3

Nonpipelined versus pipelined execution of 3 lw instructions

Pipeline Performance - Summary 

Pipeline does not change the individual instruction execution time



Pipeline improves performance by increasing the instruction throughput



The pipelined processor has a lower average CPI when compared to a multicycle implementation with the same clock rate.



The pipelined processor has a lower product of clock rate and CPI when compared to the single cycle implementation



Ideal speedup is proportional to the number of stages

Pipeline Hazards

Hazard:

A situation in pipelining when the next instruction cannot execute in the next clock cycle

Three types of hazards:  Structural hazard  Data hazard  Control (branch) hazard

Structural Hazard The hardware cannot support the combination of instructions that we want to execute in the same clock cycle.

Data Hazards Data hazard can occur when one or more of the instructions in the pipeline are data dependent. Consider the following sequence of instructions: add $s0, $t0, $t1 sub $t2, $s0, $t3 The sub instruction is dependent on the result in register $s0 of the first instruction. Consider the following sequence of instructions: lw $s0, 20 ($t1) sub $t2, $s0, $t3 The data required by the sub instruction is available only after the fourth stage of the first instruction. S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

Data Hazard - Solutions Two methods are used to resolve a data hazard.  Forwarding or bypassing Retrieves the missing data element from internal buffers instead of waiting for it to come from the registers or memory location specified by the instruction (Figure 6.5)

 Pipeline stall (bubble) Stall the pipeline by the required number of stages. This guarantees correct execution, but could result in a lower performance. In our example (lw followed by sub), we would have to stall by one stage (Figure 6.6).

Figure 6.5 Forwarding or bypassing

Figure 6.6 Pipeline stall (bubble)

Control (Branch) Hazards In a pipeline, an instruction is fetched at every clock cycle to sustain the pipeline. If the instruction fetched is a “branch” instruction, the decision about whether to branch does not occur until the execution pipeline stage. The delay in determining the proper instruction to fetch is called a “control hazard” or “branch hazard”.

Resolving Branch Hazards Techniques employed are:

 Always stall Pipeline is stalled until the pipeline determines the outcome of the branch and knows what instruction address to fetch from. The penalty will be several clock cycles.

 Assume branch not taken Execution of the branch instruction is continued in the pipeline assuming that the branch is not likely to take place. If the branch is taken, the instructions that are being fetched and decoded are discarded (flushed).

Performance of Pipelined Systems

Pipelining reduces the average execution time per instruction, thereby improving the system performance.

Hazards limit the performance improvement, but appropriate hardware/software techniques can be devised to circumvent these limits.

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

htt

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

sbarufullerton.edu

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu

S. Barua – CPSC 440

[email protected]

http://sbarua.ecs.fullerton.edu