Com Par At Or

Ex.NO: DESIGN AND SIMULATION OF COMPARATOR Date:

AIM: To design and simulate comparator using verilog program and schematic editor.

EQUIPMENTS AND SOFTWARE REQUIRED: PC with Xilinx ISE 9.1 PC with Xilinx project navigator.

PROCEDURE: A. VERILOG PROGRAM: 1. Load Modelsim simulator. 2. Open a new project and verilog programs for the given circuits in all the four models of the project. 3. Simulate and verify the functionality of the circuit.

PROGRAM module mag_comp(less,great,equal,a,b); output less,great,equal; input [3:0]a,b; wire x1,x2,x3,x4,x5,x6,x7,x8; wire y1,y2,y3,y4,y5,y6,y7,y8; wire z1,z2,z3,z4; wire w1,w2,w3,w4,w5,w6; not (x1,a[3]); not (x2,b[3]); not (x3,a[2]); not (x4,b[2]); not (x5,a[1]); not (x6,b[1]);

not (x7,a[0]); not (x8,b[0]); and(y1,x1,b[3]); and(y2,x2,a[3]); and(y3,x3,b[2]); and(y4,x4,a[2]); and(y5,x5,b[1]); and(y6,x6,a[1]); and(y7,x7,b[0]); and(y8,x8,a[0]); nor(z1,y1,y2); nor(z2,y3,y4); nor(z3,y5,y6); nor(z4,y7,y8); and(w1,z1,y3); and(w2,z1,y4); and(w3,z1,z2,y5); and(w4,z1,z2,y6); and(w5,z1,z2,z3,y8); and(w6,z1,z2,z3,y8); and(equal,z1,z2,z3,z4); or(less,y1,w1,w3,w5); or(great,y2,w2,w4,w6); endmodule OUTPUT

B. SCHEMATIC EDITOR: 1. Load Xilinx project navigator. 2. Create new project. 3. Create new source (schematic). 4. Draw the given circuit diagram using schematic editor. 5. View the RTL level schematic. 6. Synthesis project and verify the results in modelsim. CIRCUIT DIAGRAM

OUTPUT

RESULT: Thus the combinational logic circuits are designed using verilog and simulated using modelsim simulator and Xilinx ISE.