Cmos Layout Prog

******************************************************************************** * SPICE netlist generated by HiperVerify's NetList Extractor * * Extract Date/Time: Mon Aug 17 16:16:35 2009 * L-Edit Version: L-Edit Win32 13.13.20081106.17:52:26 * * Rule Set Name: * TDB File Name: C:\Documents and Settings\student\Desktop\vivek\cmos\cmos_lay1.tdb * Command File: C:\Documents and Settings\student\My Documents\Tanner EDA\Tanner Tools v13.1\L-Edit and LVS\Tech\Mosis\morbn20.ext * Cell Name: Cell0 * Write Flat: YES ******************************************************************************** .include "C:\Documents and Settings\student\My Documents\model files\model_file035.md" v1 vdd gnd 3.0 0.0 v2 gnd_ gnd 0.0 0.0 v3 in gnd pulse (0 3 0 1ns 1ns 50ns 100ns) .tran 1ns 1000ns .print v(in) v(out) .dc v3 0 3 5 .print dc v(out) .op .power v1 M1 out in gnd_ gnd_ NMOS l=2.5e-006 w=7e-006 ad=4.55e-011 as=4.9e-011 pd=2.7e-005 ps=2.8e-005 $(20 11 22.5 18) M2 out in vdd vdd PMOS l=2.5e-006 w=7.5e-006 ad=4.125e-011 as=4.5e-011 pd=2.6e-005 ps=2.7e-005 $(20 31 22.5 38.5) ****************************************