Chapter6
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Sequential Logic Sukree Sinthupinyo Department of Computer Science Thammasat University
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 1/17
Overview
● Overview
■
Propagations Delays Latches
Sukree Sinthupinyo, January 28, 2007
■
Sequential logic circuits can store information, different from combinational circuits The ability to store information is a crucial property of most digital systems.
Combinational Design - p. 2/17
● Overview Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.) ● Rise and Fall Delays Latches
Sukree Sinthupinyo, January 28, 2007
Propagations Delays
Combinational Design - p. 3/17
Delay Types
● Overview
■
Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.) ● Rise and Fall Delays
■
Latches
■
Most important of delay are the gate delays. Physical gates impose on the signals that pass through them. Line delays associate with wires, conductors within ICs, and other interconnection media. Line delays tend to be much smaller than gate delays. They can either be assumed to be zero, or else can be lumped into the propagation delay of an associated gate. Can be described by the time-dependent Boolean equation z(t) = x(t − tpd )
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 4/17
Gate Delays
● Overview Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.) ● Rise and Fall Delays
x1(t) x2(t) x3(t)
10 ns z(t)
Latches
z(t) = x1 (t − 10)x2 (t − 10)x3 (t − 10)
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 5/17
Gate Delays (cont.)
● Overview Propagations Delays ● Delay Types ● Gate Delays
10 ns x1(t)
● Gate Delays (cont.) ● Rise and Fall Delays
10 ns
Latches
x2(t)
Sukree Sinthupinyo, January 28, 2007
z(t)
Combinational Design - p. 6/17
Rise and Fall Delays
● Overview
■
Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.)
■
● Rise and Fall Delays Latches
■
The 0-to-1 transition (positive edge) of the signal x is shifted by the amount tP LH , called the rise delay. The 1-to-0 transition (negative edge) of x is shifted by tP HL , called the fall delay. rise-fall delay element tP LH = tP HL = tpd
■
If tP LH 6= tP LH , we may use the appoximation tpd = (tP LH + tP HL )/2
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 7/17
● Overview Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability
Latches
● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 8/17
Feedback
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■
Any logic circuit in which signal flow is unidirectional, a so-called feed-forward circuit. This kind of circuit has a finite memory span bounded by the maximum value of the combined propagation delays along any path from a primary output to a primary input. In order to construct a circuit with unbounded memory span from unidirection logic elements, it is neccessary to create a closed signal path or a feedback loop.
Combinational Design - p. 9/17
Stability
● Overview
0
Propagations Delays
x(t)
Latches
tpd=0 1
z(t)
?
z(t)
● Feedback ● Stability
1
● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches
1
● D Latch Operation
x(t)
tpd=0
? ■
From the figure, we can write the Boolean equation z(t) = x(t) · z(t)
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 10/17
Stability
● Overview
1
Propagations Delays
x(t)
Latches ● Feedback ● Stability
tpd>0 0/1
z(t)
0/1
● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.)
■
● D Latches ● D Latch Operation
■
The inconsistency in the previous slide disappears if the NAND gate has a nonzero propagation delay tpd The equation from the previous slide changes to z(t) = x(t − tpd ) · z(t − tpd )
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 11/17
Metastability
● Overview
■
Propagations Delays
■
Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■
Sometime the signal is pulled equally toward 0 and 1. This condition remains stationary at some in-between value, is called metastability. If we consider a tossed coin to have two stable states-heads and tails-when it falls to the ground, the metastable state corresponds to the coin landing on its edge and remaining upright.
Combinational Design - p. 12/17
Bistable Circuits
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.)
■
We need a memory circuit that is capable of storing the value of a binary quantity Q indefinitely. This circuit must have two stable internal configurations or states, defined as follows: ◆ State Q = 0: the memory circuit stores the value 0. ◆ State Q = 1: the memory circuit stores the value 1.
● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 13/17
SR Latches
● Overview Propagations Delays
S
Q
R
Q
Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 14/17
SR Latches (cont.)
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■
Consist of two primary inputs, set and reset; two ¯ complementary outputs, Q and Q. Operations ◆ It has two stable states defined by Q = 0, which is called the reset state, and Q = 1, which is called the set state. ◆ The input combination (S, R) = (0, 0) is quiescent in that it leaves the latch in either of its stable states indefinitely. ◆ The input combination (S, R) = (1, 0) sets the latch by changing its state from Q = 0 to Q = 1. If the initial state is already Q = 1 setting the latch has no effect. ◆ The input combination (S, R) = (0, 1) resets the latch by changing its state from Q = 1 to Q = 0. If the initial state is already Q = 0 setting the latch has no effect. ◆ A complete change of state takes approximately 2tpd time units, where tpd is the average gate delay.
Combinational Design - p. 15/17
D Latches
● Overview
D (Data)
Q
Propagations Delays Latches
C (Enable)
● Feedback
Q
● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■ ■
Called delay circuit or D latch. Does not have the restriction on input patterns found in the SR case.
Combinational Design - p. 16/17
D Latch Operation
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability
■ ■
● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.)
■
● D Latches ● D Latch Operation
■
Sukree Sinthupinyo, January 28, 2007
To respond to the D input, the latch must be enabled; that is, its C input must be in the active or 1 state. The latch is said to be transparent to the D signal. As long as C = 1, the D latch responds immediately to changes that occur on its D input line. The effect of C = 0 is to disconnect the D input from the latch and to close the feedback loop. The feedback loop holds Q at its current value until the latch is again enabled.
Combinational Design - p. 17/17
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 1/17
Overview
● Overview
■
Propagations Delays Latches
Sukree Sinthupinyo, January 28, 2007
■
Sequential logic circuits can store information, different from combinational circuits The ability to store information is a crucial property of most digital systems.
Combinational Design - p. 2/17
● Overview Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.) ● Rise and Fall Delays Latches
Sukree Sinthupinyo, January 28, 2007
Propagations Delays
Combinational Design - p. 3/17
Delay Types
● Overview
■
Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.) ● Rise and Fall Delays
■
Latches
■
Most important of delay are the gate delays. Physical gates impose on the signals that pass through them. Line delays associate with wires, conductors within ICs, and other interconnection media. Line delays tend to be much smaller than gate delays. They can either be assumed to be zero, or else can be lumped into the propagation delay of an associated gate. Can be described by the time-dependent Boolean equation z(t) = x(t − tpd )
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 4/17
Gate Delays
● Overview Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.) ● Rise and Fall Delays
x1(t) x2(t) x3(t)
10 ns z(t)
Latches
z(t) = x1 (t − 10)x2 (t − 10)x3 (t − 10)
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 5/17
Gate Delays (cont.)
● Overview Propagations Delays ● Delay Types ● Gate Delays
10 ns x1(t)
● Gate Delays (cont.) ● Rise and Fall Delays
10 ns
Latches
x2(t)
Sukree Sinthupinyo, January 28, 2007
z(t)
Combinational Design - p. 6/17
Rise and Fall Delays
● Overview
■
Propagations Delays ● Delay Types ● Gate Delays ● Gate Delays (cont.)
■
● Rise and Fall Delays Latches
■
The 0-to-1 transition (positive edge) of the signal x is shifted by the amount tP LH , called the rise delay. The 1-to-0 transition (negative edge) of x is shifted by tP HL , called the fall delay. rise-fall delay element tP LH = tP HL = tpd
■
If tP LH 6= tP LH , we may use the appoximation tpd = (tP LH + tP HL )/2
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 7/17
● Overview Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability
Latches
● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 8/17
Feedback
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■
Any logic circuit in which signal flow is unidirectional, a so-called feed-forward circuit. This kind of circuit has a finite memory span bounded by the maximum value of the combined propagation delays along any path from a primary output to a primary input. In order to construct a circuit with unbounded memory span from unidirection logic elements, it is neccessary to create a closed signal path or a feedback loop.
Combinational Design - p. 9/17
Stability
● Overview
0
Propagations Delays
x(t)
Latches
tpd=0 1
z(t)
?
z(t)
● Feedback ● Stability
1
● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches
1
● D Latch Operation
x(t)
tpd=0
? ■
From the figure, we can write the Boolean equation z(t) = x(t) · z(t)
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 10/17
Stability
● Overview
1
Propagations Delays
x(t)
Latches ● Feedback ● Stability
tpd>0 0/1
z(t)
0/1
● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.)
■
● D Latches ● D Latch Operation
■
The inconsistency in the previous slide disappears if the NAND gate has a nonzero propagation delay tpd The equation from the previous slide changes to z(t) = x(t − tpd ) · z(t − tpd )
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 11/17
Metastability
● Overview
■
Propagations Delays
■
Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■
Sometime the signal is pulled equally toward 0 and 1. This condition remains stationary at some in-between value, is called metastability. If we consider a tossed coin to have two stable states-heads and tails-when it falls to the ground, the metastable state corresponds to the coin landing on its edge and remaining upright.
Combinational Design - p. 12/17
Bistable Circuits
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.)
■
We need a memory circuit that is capable of storing the value of a binary quantity Q indefinitely. This circuit must have two stable internal configurations or states, defined as follows: ◆ State Q = 0: the memory circuit stores the value 0. ◆ State Q = 1: the memory circuit stores the value 1.
● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 13/17
SR Latches
● Overview Propagations Delays
S
Q
R
Q
Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
Combinational Design - p. 14/17
SR Latches (cont.)
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■
Consist of two primary inputs, set and reset; two ¯ complementary outputs, Q and Q. Operations ◆ It has two stable states defined by Q = 0, which is called the reset state, and Q = 1, which is called the set state. ◆ The input combination (S, R) = (0, 0) is quiescent in that it leaves the latch in either of its stable states indefinitely. ◆ The input combination (S, R) = (1, 0) sets the latch by changing its state from Q = 0 to Q = 1. If the initial state is already Q = 1 setting the latch has no effect. ◆ The input combination (S, R) = (0, 1) resets the latch by changing its state from Q = 1 to Q = 0. If the initial state is already Q = 0 setting the latch has no effect. ◆ A complete change of state takes approximately 2tpd time units, where tpd is the average gate delay.
Combinational Design - p. 15/17
D Latches
● Overview
D (Data)
Q
Propagations Delays Latches
C (Enable)
● Feedback
Q
● Stability ● Stability ● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.) ● D Latches ● D Latch Operation
Sukree Sinthupinyo, January 28, 2007
■ ■
Called delay circuit or D latch. Does not have the restriction on input patterns found in the SR case.
Combinational Design - p. 16/17
D Latch Operation
● Overview
■
Propagations Delays Latches ● Feedback ● Stability ● Stability
■ ■
● Metastability ● Bistable Circuits ● SR Latches ● SR Latches (cont.)
■
● D Latches ● D Latch Operation
■
Sukree Sinthupinyo, January 28, 2007
To respond to the D input, the latch must be enabled; that is, its C input must be in the active or 1 state. The latch is said to be transparent to the D signal. As long as C = 1, the D latch responds immediately to changes that occur on its D input line. The effect of C = 0 is to disconnect the D input from the latch and to close the feedback loop. The feedback loop holds Q at its current value until the latch is again enabled.
Combinational Design - p. 17/17
