Bsim3v3_3.3_manual.pdf

BSIM3v3.3 MOSFET Model Users’Manual

Weidong Liu, Xiaodong Jin, Xuemei Xi, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K. Ko and Chenming Hu

Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720

Copyright © 2005 The Regents of the University of California All Rights Reserved

Developers: The BSIM3v3.3.0 MOSFET model is developed by • Prof. Chenming Hu, UC Berkeley • Dr. Xuemei Xi, UC Berkeley • Mohan Dunga, UC Berkeley

Developers of Previous Versions: • Dr. Mansun Chan, USTHK • Dr. Kai Chen, IBM • Dr. Yuhua Cheng, Rockwell • Dr. Jianhui Huang, Intel Corp. • Dr. Kelvin Hui, Lattice Semiconductor • Dr. James Chen, UC Berkeley • Dr. Min-Chie Jeng, Cadence Design Systems • Dr. Zhi-Hong Liu, BTA Technology Inc. • Dr. Robert Tu, AMD • Prof. Ping K. Ko, UST, Hong Kong • Prof. Chenming Hu, UC Berkeley Web Sites to Visit: BSIM web site: http://www-device.eecs.berkeley.edu/~bsim3 Compact Model Council web site: http://www.eia.org/eig/CMC

Technical Support: Dr. Xuemei (Jane) Xi: [email protected]

Acknowledgment: The development of BSIM3v3.3 benefited from the input of many BSIM3 users, especially the Compact Model Council (CMC) member companies. The developers would like to thank Keith Green, Tom Vrotsos, David Zweidinger and Claude R. Cirba at TI, Joe Watts at IBM, Colin McAndrew at Motorola, Min-Chie Jeng, Zhihong Liu at Cadence, Weidong Liu at Synopsys, Paul Humphries at Analog Devices, Shiuh-Wuu Lee, Paul Packan, Wei-Kai Shih at Intel, Judy An at AMD, Mohamed Ahmed, Mohamed Hassan, and Mohamed Selim at Mentor Graphics, Peter Lee at Renesas, Takahiro Iizuka at NEC, Sally Liu, Ke-Wei Su at TSMC, Daniel Wan, Jin Shyong Jan at UMC for their valuable assistance in identifying the desirable modifications and testing of the new model. Special acknowledgment goes to Dr. Josef Watts, chair of CMC, Dr. Keith Green, former Chairman of the Technical Issue Subcommittee of CMC; and Bhaskar Gadepally, Britt Brooks, former chairs of CMC. The BSIM3 project is partially supported by SRC, CMC and Rockwell Intern:ational.

Table of Contents CHAPTER 1:

Introduction 1-1

1.1 General Information 1-1 1.1 Backward compatibility 1-2 1.2 Organization of This Manual 1-2

CHAPTER 2:

Physics-Based Derivation of I-V Model 2-1

2.1 Non-Uniform Doping and Small Channel Effects on Threshold Voltage 2-1 2.1.1 Vertical Non-Uniform Doping Effect 2-3 2.1.2 Lateral Non-Uniform Doping Effect 2-5 2.1.3 Short Channel Effect 2-7 2.1.4 Narrow Channel Effect 2-12 2.2 Mobility Model 2-15 2.3 Carrier Drift Velocity 2-17 2.4 Bulk Charge Effect

2-18

2.5 Strong Inversion Drain Current (Linear Regime) 2-19 2.5.1 Intrinsic Case (Rds=0) 2-19 2.5.2 Extrinsic Case (Rds>0) 2-21 2.6 Strong Inversion Current and Output Resistance (Saturation Regime) 2-22 2.6.1 Channel Length Modulation (CLM) 2-25 2.6.2 Drain-Induced Barrier Lowering (DIBL) 2-26 2.6.3 Current Expression without Substrate Current Induced Body Effect 2-27 2.6.4 Current Expression with Substrate Current Induced Body Effect 2-28 2.7 Subthreshold Drain Current 2-30 2.8 Effective Channel Length and Width 2.9 Poly Gate Depletion Effect

CHAPTER 3:

2-31

2-33

Unified I-V Model

3.1 Unified Channel Charge Density Expression

3-1 3-1

3.2 Unified Mobility Expression 3-6

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3.3 Unified Linear Current Expression 3-7 3.3.1 Intrinsic case (Rds=0) 3-7 3.3.2 Extrinsic Case (Rds > 0) 3-9 3.4 Unified Vdsat Expression 3-9 3.4.1 Intrinsic case (Rds=0) 3-9 3.4.2 Extrinsic Case (Rds>0) 3-10 3.5 Unified Saturation Current Expression 3-11 3.6 Single Current Expression for All Operating Regimes of Vgs and Vds

3-12

3.7 Substrate Current 3-15 3.8 A Note on Vbs

3-15

CHAPTER 4:

Capacitance Modeling

4.1 General Description of Capacitance Modeling

4-1

4-1

4.2 Geometry Definition for C-V Modeling 4-2 4.3 Methodology for Intrinsic Capacitance Modeling 4-4 4.3.1 Basic Formulation 4-4 4.3.2 Short Channel Model 4-7 4.3.3 Single Equation Formulation 4.4 Charge-Thickness Capacitance Model 4-14

4-9

4.5 Extrinsic Capacitance 4-19 4.5.1 Fringing Capacitance 4-19 4.5.2 Overlap Capacitance 4-19

CHAPTER 5:

Non-Quasi Static Model

5.1 Background Information 5.2 The NQS Model 5-1 5.3 Model Formulation 5.3.1 5.3.2 5.3.3 5.3.4

5-1

5-1

5-2 SPICE sub-circuit for NQS model 5-3 Relaxation time 5-4 Terminal charging current and charge partitioning Derivation of nodal conductances 5-7

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5-5

2

CHAPTER 6:

Parameter Extraction

6-1

6.1 Optimization strategy 6-1 6.2 Extraction Strategies

6-2

6.3 Extraction Procedure 6-2 6.3.1 Parameter Extraction Requirements 6-2 6.3.2 Optimization 6-4 6.3.3 Extraction Routine 6-6 6.4 Notes on Parameter Extraction 6-14 6.4.1 Parameters with Special Notes 6-14 6.4.2 Explanation of Notes 6-15

CHAPTER 7:

Benchmark Test Results

7-1

7.1 Benchmark Test Types 7-1 7.2 Benchmark Test Results 7-2

CHAPTER 8:

Noise Modeling

8-1

8.1 Flicker Noise 8-1 8.1.1 Parameters 8-1 8.1.2 Formulations 8-2 8.2 Channel Thermal Noise 8-4 8.3 Noise Model Flag 8-5

CHAPTER 9:

MOS Diode Modeling 9-1

9.1 Diode IV Model 9-1 9.1.1

Modeling the S/B Diode 9-1

9.1.2

Modeling the D/B Diode 9-3

9.2 MOS Diode Capacitance Model 9-5 9.2.1

S/B Junction Capacitance 9-5

9.2.2

D/B Junction Capacitance 9-7

9.2.3

Temperature Dependence of Junction Capacitance 9-10

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9.2.4

Junction Capacitance Parameters 9-11

APPENDIX A:

Parameter List

A-1

A.1 Model Control Parameters A-1 A.2 DC Parameters A-1 A.3 C-V Model Parameters A-6 A.4 NQS Parameters A-8 A.5 dW and dL Parameters A-9 A.6 Temperature Parameters A-10 A.7 Flicker Noise Model Parameters A-12 A.8 Process Parameters A-13 A.9 Geometry Range Parameters A-14 A.10 Model Parameter Notes A-14

APPENDIX B:

Equation List

B-1

B.1 I-V Model B-1 B.1.1 Threshold Voltage B-1 B.1.2 Effective (Vgs-Vth) B-2 B.1.3 Mobility B-3 B.1.4 Drain Saturation Voltage B-4 B.1.5 Effective Vds B-5 B.1.6 Drain Current Expression B-5 B.1.7 Substrate Current B-6 B.1.8 Polysilicon Depletion Effect B-7 B.1.9 Effective Channel Length and Width B.1.10 Source/Drain Resistance B-8 B.1.11 Temperature Effects B-8 B.2 Capacitance Model Equations B-9 B.2.1 Dimension Dependence B-9 B.2.2 Overlap Capacitance B-10 B.2.3 Instrinsic Charges B-12

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4

APPENDIX C:

References

C-1

APPENDIX D:

Model Parameter Binning

D-1

D.1 Model Control Parameters D-2 D.2 DC Parameters D-2 D.3 AC and Capacitance Parameters D-7 D.4 NQS Parameters D-9 D.5 dW and dL Parameters D-9 D.6 Temperature Parameters D-11 D.7 Flicker Noise Model Parameters D-12 D.8 Process Parameters D-13 D.9 Geometry Range Parameters D-14

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CHAPTER 1: Introduction

1.1 General Information BSIM3v3 is the latest industry-standard MOSFET model for deep-submicron digital and analog circuit designs from the BSIM Group at the University of California at Berkeley. BSIM3v3.3 is based on its predecessor, BSIM3v3.2.4, with the following changes: • A channel thermal noise formulation varying smoothly from linear region to saturation region. The formulation comes from Cadence Spectre.

• A BSIM4 ACNQS model that enbles the NQS effect in AC simulation. • A new parameter LINTNOI introducing an offset to the length reduction parameter(Lint) to improve the accuracy of the flicker noise model;

• Known bugs are fixed.

1.2 Organization of This Manual This manual describes the BSIM3v3.3 model in the following manner: • Chapter 2 discusses the physical basis used to derive the I-V model. • Chapter 3 highlights a single-equation I-V model for all operating regimes. • Chapter 4 presents C-V modeling and focuses on the charge thickness model. • Chapter 5 describes in detail the restrutured NQS (Non-Quasi-Static) Model. • Chapter 6 discusses model parameter extraction. • Chapter 7 provides some benchmark test results to demonstrate the accuracy and performance of the model.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

1-1

Organization of This Manual

• Chapter 8 presents the noise model. • Chapter 9 describes the MOS diode I-V and C-V models. • The Appendices list all model parameters, equations and references.

1-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

CHAPTER 2: Physics-Based Derivation of I-V Model

The development of BSIM3v3 is based on Poisson's equation using gradual channel approximation and coherent quasi 2D analysis, taking into account the effects of device geometry and process parameters. BSIM3v3.2.2 considers the following physical phenomena observed in MOSFET devices [1]: • • • • • • • • • •

Short and narrow channel effects on threshold voltage. Non-uniform doping effect (in both lateral and vertical directions). Mobility reduction due to vertical field. Bulk charge effect. Velocity saturation. Drain-induced barrier lowering (DIBL). Channel length modulation (CLM). Substrate current induced body effect (SCBE). Subthreshold conduction. Source/drain parasitic resistances.

2.1 Non-Uniform Doping and Small Channel Effects on Threshold Voltage Accurate modeling of threshold voltage (Vth) is one of the most important requirements for precise description of device electrical characteristics. In addition, it serves as a useful reference point for the evaluation of device operation regimes. By using threshold voltage, the whole device operation regime can be divided into three operational regions.

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2-1

Non-Uniform Doping and Small Channel Effects on Threshold Voltage

First, if the gate voltage is greater than the threshold voltage, the inversion charge density is larger than the substrate doping concentration and MOSFET is operating in the strong inversion region and drift current is dominant. Second, if the gate voltage is smaller than Vth, the inversion charge density is smaller than the substrate doping concentration. The transistor is considered to be operating in the weak inversion (or subthreshold) region. Diffusion current is now dominant [2]. Lastly, if the gate voltage is very close to Vth , the inversion charge density is close to the doping concentration and the MOSFET is operating in the transition region. In such a case, diffusion and drift currents are both important. For MOSFET’s with long channel length/width and uniform substrate doping concentration, Vth is given by [2]: (2.1.1)

(

Vth =VFB + Φs +γ Φs −Vbs =VTideal +γ Φs −Vbs − Φs

)

where VFB is the flat band voltage, VTideal is the threshold voltage of the long channel device at zero substrate bias, and γ is the body bias coefficient and is given by: (2.1.2) γ =

2ε siqN a Cox

where Na is the substrate doping concentration. The surface potential is given by: (2.1.3) Φs = 2

2-2

k BT  N a   ln  q  ni 

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Equation (2.1.1) assumes that the channel is uniform and makes use of the one dimensional Poisson equation in the vertical direction of the channel. This model is valid only when the substrate doping concentration is constant and the channel length is long. Under these conditions, the potential is uniform along the channel. Modifications have to be made when the substrate doping concentration is not uniform and/or when the channel length is short, narrow, or both.

2.1.1 Vertical Non-Uniform Doping Effect The substrate doping profile is not uniform in the vertical direction as shown in Figure 2-1.

Nch

Nsub

Figure 2-1. Actual substrate doping distribution and its approximation.

The substrate doping concentration is usually higher near the Si/SiO 2 interface (due to Vth adjustment) than deep into the substrate. The distribution of impurity atoms inside the substrate is approximately a half

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

gaussian distribution, as shown in Figure 2-1. This non-uniformity will make γ in Eq. (2.1.2) a function of the substrate bias.

If the depletion

width is less than Xt as shown in Figure 2-1, Na in Eq. (2.1.2) is equal to Nch; otherwise it is equal to Nsub. In order to take into account such non-uniform substrate doping profile, the following Vth model is proposed:

(

)

(2.1.4)

Vth = VTideal + K1 Φ s − Vbs − Φ s − K 2Vbs For a zero substrate bias, Eqs. (2.1.1) and (2.1.4) give the same result. K1 and K2 can be determined by the criteria that Vth and its derivative versus Vbs should be the same at Vbm , where Vbm is the maximum substrate bias voltage. Therefore, using equations (2.1.1) and (2.1.4), K1 and K2 [3] will be given by the following: (2.1.5) K 1 = γ 2 − 2 K 2 Φ s − Vbm

K2 =

(γ 1 − γ 2 )( 2 Φs

(

Φ s − Vbx − Φ s

)

)

(2.1.6)

Φ s − Vbm − Φ s + Vbm

where γ1 and γ2 are body bias coefficients when the substrate doping concentration are equal to Nch and Nsub , respectively: (2.1.7) γ1 =

2-4

2qε si N ch Cox

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

(2.1.8) γ2 =

2qε si N sub Cox

Vbx is the body bias when the depletion width is equal to Xt. Therefore, Vbx satisfies: (2.1.9) 2

qN ch X t = Φ s − Vbx 2ε si

If the devices are available, K1 and K2 can be determined experimentally. If the devices are not available but the user knows the doping concentration distribution, the user can input the appropriate parameters to specify doping concentration distribution (e.g. Nch , Nsub and Xt). Then, K1 and K2 can be calculated using equations (2.1.5) and (2.1.6).

2.1.2 Lateral Non-Uniform Doping Effect For some technologies, the doping concentration near the source/drain is higher than that in the middle of the channel. This is referred to as lateral non-uniform doping and is shown in Figure 2-2. As the channel length becomes shorter, lateral non-uniform doping will cause Vth to increase in magnitude because the average doping concentration in the channel is larger. The average channel doping concentration can be calculated as follows:

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

(2.1.10) N eff =

Na ( L − 2Lx ) + Npocket⋅ 2Lx  2L Npocket− Na  = Na 1+ x ⋅  L L Na  

 Nlx ≡ Na ⋅ 1+  L  

Due to the lateral non-uniform doping effect, Eq. (2.1.4) becomes:

Vth = Vth 0 + K1

(

(2.1.11)

)

Φ s − V bs − Φ s − K 2Vbs

  Nlx + K1  1 + − 1 Φ s   Leff  

Eq. (2.1.11) can be derived by setting Vbs = 0, and using K1 ∝ (Neff) 0.5. The fourth term in Eq. (2.1.11) is used to model the body bias dependence of the lateral non-uniform doping effect. This effect gets stronger at a lower body bias. Examination of Eq. (2.1.11) shows that the threshold voltage will increase as channel length decreases [3].

N(x)

Npocket

Npocket

Na Lx

Lx

X Figure 2-2. Lateral doping profile is non-uniform.

2-6

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

2.1.3 Short Channel Effect The threshold voltage of a long channel device is independent of the channel length and the drain voltage. Its dependence on the body bias is given by Eq. (2.1.4). However, as the channel length becomes shorter, the threshold voltage shows a greater dependence on the channel length and the drain voltage. The dependence of the threshold voltage on the body bias becomes weaker as channel length becomes shorter, because the body bias has less control of the depletion region. The short-channel effect is included in the Vth model as:

(

)

(2.1.12)

Vth = Vth 0 + K1 Φ s − V bs − Φ s − K 2Vbs   Nlx + K1  1 + − 1  Φ s − ∆V th   Leff  

where ∆Vth is the threshold voltage reduction due to the short channel effect. Many models have been developed to calculate ∆Vth. They used either numerical solutions [4], a two-dimensional charge sharing approach [5,6], or a simplified Poisson's equation in the depletion region [7-9]. A simple, accurate, and physical model was developed by Z. H. Liu et al. [10]. Th is model was derived by solving the quasi 2D Poisson equation along the channel. This quasi-2D model concluded that: (2.1.13)

∆Vth = θ th ( L)(2(Vbi − Φ s ) + Vds ) where Vbi is the built-in voltage of the PN junction between the source and the substrate and is given by

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

(2.1.14) K T N N Vbi = B ln( ch 2 d ) q ni

where Nd in is the source/drain doping concentration with a typical value of around

２０

１ × １０

cm-3. The expression θth (L) is a short channel effect

coefficient, which has a strong dependence on the channel length and is given by: (2.1.15) θ th ( L ) = [exp ( − L 2lt ) + 2 exp ( − L lt )]

lt is referred to as the characteristic length and is given by (2.1.16) lt =

ε si Tox X dep ε ox η

Xdep is the depletion width in the substrate and is given by (2.1.17) X dep =

2ε si (Φ s − Vbs ) qN ch

Xdep is larger near the drain than in the middle of the channel due to the drain voltage. Xdep / η represents the average depletion width along the channel. Based on the above discussion, the influences of drain/source charge sharing and DIBL effects onVth are described by (2.1.15). In order to make the model fit different technologies, several parameters such as Dvt0, Dvt2 ,

2-8

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Dsub, Eta0 and Etab are introduced, and the following modes are used to account for charge sharing and DIBL effects separately.

θ th ( L ) = Dvt 0 [exp( − D vt 1 L / 2l t ) + 2 exp( − Dvt 1 L / l t )]

(2.1.18)

(2.1.19) ∆Vth (L) = θ th (L)(Vbi − Φ s ) (2.1.20) lt =

ε si Tox X dep ε ox

(1 + Dvt 2Vbs )

(2.1.21) θ dibl ( L ) = [exp( − Dsub L / 2 lt 0 ) + 2 exp( − D sub L / lt 0 )]

∆Vth(Vds) = θdibl ( L)(Eta0 + EtabVbs)Vds

(2.1.22)

where lt0 is calculated by Eq. (2.1.20) at zero body-bias. Dvt1 is basically equal to 1/(η)1/2 in Eq. (2.1.16). Dvt2 is introduced to take care of the dependence of the doping concentration on substrate bias since the doping concentration is not uniform in the vertical direction of the channel. Xdep is calculated using the doping concentration in the channel (Nch). Dvt 0, Dvt1 ,Dvt2, Eta0, Etab and Dsub, which are determined experimentally, can improve accuracy greatly. Even though Eqs. (2.1.18), (2.1.21) and (2.1.15) have different coefficients, they all still have the same functional forms. Thus the device physics represented by Eqs. (2.1.18), (2.1.21) and (2.1.15) are still the same.

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

As channel length L decreases, ∆Vth will increase, and in turn Vth will decrease. If a MOSFET has a LDD structure, Nd in Eq. (2.1.14) is the doping concentration in the lightly doped region. Vbi in a LDD-MOSFET will be smaller as compared to conventional MOSFET’s; therefore the threshold voltage reduction due to the short channel effect will be smaller in LDD-MOSFET’s. As the body bias becomes more negative, the depletion width will increase as shown in Eq. (2.1.17). Hence ∆Vth will increase due to the increase in lt. The term:

VTideal + K 1 Φ s − Vbs − K 2Vbs will also increase as Vbs becomes more negative (for NMOS). Therefore, the changes in

VTideal + K 1 Φ s − Vbs − K 2Vbs and in ∆Vth will compensate for each other and make Vth less sensitive to Vbs. This compensation is more significant as the channel length is shortened. Hence, the Vth of short channel MOSFET’s is less sensitive to body bias as compared to a long channel MOSFET. For the same reason, the DIBL effect and the channel length dependence of Vth are stronger as Vbs is made more negative. This was verified by experimental data shown in Figure 2-3 and Figure 2-4. Although Liu et al. found an accelerated Vth roll-off and non-linear drain voltage dependence [10] as the channel became very short, a linear dependence of Vth on Vd s is nevertheless a good approximation for circuit simulation as shown in Figure 2-4. This figure shows that Eq. (2.1.13) can fit the experimental data very well.

2-10

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Furthermore, Figure 2-5 shows how this Vth model can fit various channel lengths under various bias conditions.

Figure 2-3. Threshold voltage versus the drain voltage at different body biases.

Figure 2-4. Channel length dependence of threshold voltage.

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

Figure 2-5. Threshold voltage versus channel length at different biases.

2.1.4 Narrow Channel Effect The actual depletion region in the channel is always larger than what is usually assumed under the one-dimensional analysis due to the existence of fringing fields [2]. This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the "classical" depletion layer formed from the vertical field. The net result is an increase in Vth. It is shown in [2] that this increase can be modeled as: (2.1.23) πqN a X d max 2 T = 3π o x Φ s 2 Co xW W

2-12

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

The right hand side of Eq. (2.1.23) represents the additional voltage increase. This change in Vth is modeled by Eq. (2.1.24a). This formulation includes but is not limited to the inverse of channel width due to the fact that the overall narrow width effect is dependent on process (i.e. isolation technology) as well. Hence, parameters K3 , K3b , and W 0 are introduced as (2.1.24a)

( K3 + K 3bVbs )

Tox Φs Weff '+W0

Weff ’is the effective channel width (with no bias dependencies), which will be defined in Section 2.8. In addition, we must consider the narrow width effect for small channel lengths. To do this we introduce the following: (2.1.24b)

Weff Leff Weff Leff   DVT 0 w exp( − DVT 1w ) + 2 exp( − DVT 1w ) ( Vbi − Φs )   2l tw ltw '

'

When all of the above considerations for non-uniform doping, short and narrow channel effects on threshold voltage are considered, the final complete Vth expression implemented in SPICE is as follows:

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

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Non-Uniform Doping and Small Channel Effects on Threshold Voltage

(2.1.25) Vth = Vth0ox + K1ox ⋅ Φs −Vbseff − K2oxVbseff  Nlx  T + K1ox 1 + −1 Φs + (K3 + K3bVbseff) ox Φ s  Leff  Weff '+W0    Weff ' Leff  W ' L    + 2 exp− DV T1w eff eff (Vbi − Φs ) − DV T0w exp − DV T1w 2ltw  ltw       L  L   − DV T0 exp − DV T1 eff  + 2exp− DV T1 eff (Vbi − Φs )  2lt  lt       Leff   Leff  − exp− Dsub  + 2exp− Dsub (Etao + EtabVbseff )Vds 2lto  lto    

where Tox dependence is introduced in the model parameters K1 and K2 to improve the scalibility of Vth model with respect to Tox. Vth 0ox , K1ox and K2ox are modeled as

Vth0ox =Vth0 − K1 ⋅ Φs and

K1ox = K1 ⋅

Tox Toxm

K2 ox = K2 ⋅

Tox Toxm

Toxm is the gate oxide thickness at which parameters are extracted with a default value of Tox . In Eq. (2.1.25), all Vbs terms have been substituted with a Vbseff expression as shown in Eq. (2.1.26). This is done in order to set an upper bound for the body bias value during simulations since unreasonable values can occur if this expression is not introduced (see Section 3.8 for details).

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Mobility Model

(2.1.26) Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ 1) − 4δ 1Vbc ] 2

where δ1 = 0.001V. The parameter Vbc is the maximum allowable Vbs value and is calculated from the condition of dVth/dVbs =0 for the Vth expression of 2.1.4, 2.1.5, and 2.1.6, and is equal to: 2  K1  Vbc = 0.9 Φ s −  4K 2 2 

   

2.2 Mobility Model A good mobility model is critical to the accuracy of a MOSFET model. The scattering mechanisms responsible for surface mobility basically include phonons, coulombic scattering, and surface roughness [11, 12]. For good quality interfaces, phonon scattering is generally the dominant scattering mechanism at room temperature. In general, mobility depends on many process parameters and bias conditions. For example, mobility depends on the gate oxide thickness, substrate doping concentration, threshold voltage, gate and substrate voltages, etc. Sabnis and Clemens [13] proposed an empirical unified formulation based on the concept of an effective field Eeff which lumps many process parameters and bias conditions together. Eeff is defined by Q + ( Qn 2 ) Eeff = B ε si

(2.2.1)

The physical meaning of Eeff can be interpreted as the average electrical field experienced by the carriers in the inversion layer [14]. The unified formulation of mobility is then given by

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

2-15

Mobility Model

µ eff =

(2.2.2)

µ0

1 + ( Eeff E0 ) ν

Values for µ 0, E0 , and ν were reported by Liang et al. [15] and Toh et al. [16] to be the following for electrons and holes

Parameter

Electron (surface)

Hole (surface)

µ 0 (cm 2 /Vsec)

670

160

E0 (MV/cm)

0.67

0.7

ν

1.6

1.0

Table 2-1. Typical mobility values for electrons and holes.

For an NMOS transistor with n-type poly-silicon gate, Eq. (2.2.1) can be rewritten in a more useful form that explicitly relates Eeff to the device parameters [14]

Eeff ≅

Vgs + Vth

(2.2.3)

6 Tox

Eq. (2.2.2) fits experimental data very well [15], but it involves a very time consuming power function in SPICE simulation. Taylor expansion Eq. (2.2.2) is used, and the coefficients are left to be determined by experimental data or to be obtained by fitting the unified formulation. Thus, we have

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Carrier Drift Velocity

(mobMod=1) µeff =

1 + (U a + U c Vbseff )(

µo + 2Vth

Vgst gsteff TOX

(2.2.4) VVgst gsteff + 2V th 2 ) + U b( ) TOX

where Vgst=Vgs-Vth. To account for depletion mode devices, another mobility model option is given by the following (mobMod=2)

(2.2.5) µo µeff = Vgsteff V gsteff 1 + (U a + UcVbseff )( gst ) + U b ( gst ) 2 TOX TOX

The unified mobility expressions in subthreshold and strong inversion regions will be discussed in Section 3.2. To consider the body bias dependence of Eq. 2.2.4 further, we have introduced the following expression:

(For mobMod=3) µeff =

(2.2.6)

µo V gsteff + 2 Vth Vgsteff + 2Vth 2 1 + [Ua ( gst ) + Ub( gst ) ](1 + UcVbseff ) TOX TOX

2.3 Carrier Drift Velocity Carrier drift velocity is also one of the most important parameters. The following velocity saturation equation [17] is used in the model

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Bulk Charge Effect

v=

µ eff E 1 + ( E Esat )

(2.3.1) E < Esat

,

= vsat ,

E > Esat

The parameter Esat corresponds to the critical electrical field at which the carrier velocity becomes saturated. In order to have a continuous velocity model at E = Esat, Esat must satisfy: (2.3.2) Esat =

2 vsat µ eff

2.4 Bulk Charge Effect When the drain voltage is large and/or when the channel length is long, the depletion "thickness" of the channel is non-uniform along the channel length. This will cause Vth to vary along the channel. This effect is called bulk charge effect [14]. The parameter, Abulk, is used to take into account the bulk charge effect. Several extracted parameters such as A0, B0, B1 are introduced to account for the channel length and width dependences of the bulk charge effect. In addition, the parameter Keta is introduced to model the change in bulk charge effect under high substrate bias conditions. It should be pointed out that narrow width effects have been considered in the formulation of Eq. (2.4.1). The Abulk expression is given by (2.4.1)       A0Leff Leff  K1ox    Abulk = 1 +  1 − AgsVgsteff  2 Φ − V L + 2 X X L + 2 X X   s bseff  eff J dep J dep   eff   

2-18

2

   B0  1 +  W '+B  ⋅ 1 + KetaV  eff 1  bseff  

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Strong Inversion Drain Current (Linear Regime)

where A0, Ags , B0, B1 and Keta are determined by experimental data. Eq. (2.4.1) shows that Abulk is very close to unity if the channel length is small, and Abulk increases as channel length increases.

2.5 Strong Inversion Drain Current (Linear Regime) 2.5.1 Intrinsic Case (R ds=0) In the strong inversion region, the general current equation at any point y along the channel is given by (2.5.1) I ds = WC ox (Vgst − AbulkV ( y )) v ( y ) The parameter Vgst = (Vgs - V th), W is the device channel width, Cox is the gate capacitance per unit area, V(y) is the potential difference between minority-carrier quasi-Fermi potential and the equilibrium Fermi potential in the bulk at point y, v(y) is the velocity of carriers at point y. With Eq. (2.3.1) (i.e. before carrier velocity saturates), the drain current can be expressed as (2.5.2) I ds = WC ox (V gs − Vth − AbulkV ( y ))

µ eff E ( y ) 1 + E ( y ) E sat

Eq. (2.5.2) can be rewritten as follows

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2-19

Strong Inversion Drain Current (Linear Regime)

(2.5.3) E (y) =

µ eff WC ox (V

gst

I ds dV ( y ) = − AbulkV ( y ) ) − I ds E sat dy

By integrating Eq. (2.5.2) from y = 0 to y = L and V(y) = 0 to V(y) = Vds, we arrive at the following (2.5.4) I ds = µ eff Cox

W 1 (V gs − Vth − Abulk Vds 2)Vds L 1 + Vds E sat L

The drain current model in Eq. (2.5.4) is valid before velocity saturates. For instances when the drain voltage is high (and thus the lateral electrical field is high at the drain side), the carrier velocity near the drain saturates. The channel region can now be divided into two portions: one adjacent to the source where the carrier velocity is field-dependent and the second where the velocity saturates. At the boundary between these two portions, the channel voltage is the saturation voltage (Vdsat) and the lateral electrical is equal to Esat . After the onset of saturation, we can substitute v = vsat and Vds = Vdsat into Eq. (2.5.1) to get the saturation current: (2.5.5) I ds = WC ox (V gst − AbulkVdsat ) v sat By equating eqs. (2.5.4) and (2.5.5) at E = Esat and Vds = Vdsat , we can solve for saturation voltage Vdsat (2.5.6) Vdsat =

2-20

E sat L(Vgs − Vth ) AbulkE sat L + (Vgs − Vth )

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Strong Inversion Drain Current (Linear Regime)

2.5.2 Extrinsic Case (R ds >0) Parasitic source/drain resistance is an important device parameter which can affect MOSFET performance significantly. As channel length scales down, the parasitic resistance will not be proportionally scaled. As a result, Rds will have a more significant impact on device characteristics. Modeling of parasitic resistance in a direct method yields a complicated drain current expression. In order to make simulations more efficient, the parasitic resistances is modeled such that the resulting drain current equation in the linear region can be calculateed [3] as (2.5.9) I ds =

V ds V ds = R tot R ch + R ds

= µ eff C ox

( V gst − A bulk V ds 2 ) V ds W 1 W ( V gst − A bulk V ds 2 ) L 1 + V ds ( E sat L ) 1 + R ds µ eff C ox L 1 + V ds ( E sat L )

Due to the parasitic resistance, the saturation voltage Vdsat will be larger than that predicted by Eq. (2.5.6). Let Eq. (2.5.5) be equal to Eq. (2.5.9). Vdsat with parasitic resistance Rds becomes (2.5.10) Vdsat =

− b − b2 − 4 ac 2a

The following are the expression for the variables a, b, and c:

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Strong Inversion Current and Output Resistance (Saturation Regime)

(2.5.11) 2 a = Abulk Rds C ox Wvsat

1 + ( − 1) A bulk λ

2 b = −(Vgst ( − 1) + Abulk Esat L + 3 Abulk Rds Cox Wvsat Vgst ) λ 2 c = Esat LVgst + 2 Rds Cox Wvsat Vgst λ = A1V gst + A 2 The last expression for λ is introduced to account for non-saturation effect of the device. The parasitic resistance is modeled as: (2.5.11) Rds =

(

(

Rdsw 1 + PrwgVgsteff + Prwb Φ s − Vbseff − Φ s

(10 W ')

))

Wr

6

eff

The variable Rdsw is the resistance per unit width, Wr is a fitting parameter, Prwb and Prwg are the body bias and the gate bias coeffecients, repectively.

2.6 Strong Inversion Current and Output Resistance (Saturation Regime) A typical I-V curve and its output resistance are shown in Figure 2-6. Considering only the drain current, the I-V curve can be divided into two parts: the linear region in which the drain current increases quickly with the drain voltage and the saturation region in which the drain current has a very weak dependence on the drain voltage. The first order derivative reveals more detailed information about the physical mechanisms which are involved during device operation. The output resistance (which is the reciprocal of the first order derivative of the I-V curve)

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Strong Inversion Current and Output Resistance (Saturation Regime)

curve can be clearly divided into four regions with distinct Rout vs. Vds dependences. The first region is the triode (or linear) region in which carrier velocity is not saturated. The output resistance is very small because the drain current has a strong dependence on the drain voltage. The other three regions belong to the saturation region. As will be discussed later, there are three physical mechanisms which affect the output resistance in the saturation region: channel length modulation (CLM) [4, 14], drain-induced barrier lowering (DIBL) [4, 6, 14], and the substrate current induced body effect (SCBE) [14, 18, 19]. All three mechanisms affect the output resistance in the saturation range, but each of them dominates in only a single region. It will be shown next that channel length modulation (CLM) dominates in the second region, DIBL in the third region, and SCBE in the fourth region. 3.0

14

Triode

CLM

DIBL

SCBE 12

2.5

Ids (mA)

8 1.5 6

Rout (KOhms)

10 2.0

1.0 4 0.5

0.0

2

0

1

2

3

4

0

V ds (V)

Figure 2-6. General behavior of MOSFET output resistance.

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2-23

Strong Inversion Current and Output Resistance (Saturation Regime)

Generally, drain current is a function of the gate voltage and the drain voltage. But the drain current depends on the drain voltage very weakly in the saturation region. A Taylor series can be used to expand the drain current in the saturation region [3]. (2.6.1) Ids ( Vgs , Vds ) = Ids ( Vgs , Vdsat ) +

∂I ds (Vgs , Vds ) ∂Vds

( Vds − Vdsat )

V − Vdsat ≡ I dsat (1 + ds ) VA

where

Idsat = Ids ( Vgs, Vdsat ) = Wv satCox (Vgst − AbulkVdsat )

(2.6.2)

and

VA = I dsat (

∂ Ids − 1 ) ∂ Vds

(2.6.3)

The parameter VA is called the Early voltage and is introduced for the analysis of the output resistance in the saturation region. Only the first order term is kept in the Taylor series. We also assume that the contributions to the Early voltage from all three mechanisms are independent and can be calculated separately.

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Strong Inversion Current and Output Resistance (Saturation Regime)

2.6.1 Channel Length Modulation (CLM) If channel length modulation is the only physical mechanism to be taken into account, then according to Eq. (2.6.3), the Early voltage can be calculated by (2.6.4) ∂I ∂ L −1 Abulk Esat L + Vgst ∂ ∆L −1 VACLM = I dsat ( ds ) = ( ) ∂ L ∂ Vds Abulk Esat ∂ Vds where ∆L is the length of the velocity saturation region; the effective channel length is L-∆L. Based on the quasi-two dimensional approximation, VACLM can be derived as the following

VACLM =

Abulk Esat L + Vgst Abulk Esatl

(2.6.5) (Vds − Vdsat )

where VACLM is the Early Voltage due to channel length modulation alone. The parameter Pclm is introduced into the VACLM expression not only to compensate for the error caused by the Taylor expansion in the Early voltage model, but also to compensate for the error in XJ since

l ∝ XJ

and the junction depth XJ can not generally be determined very accurately. Thus, the VACLM became

VACLM =

1

Abulk Esat L + Vgst

Pclm

Abulk Esat l

(2.6.6) ( Vds − Vdsat )

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Strong Inversion Current and Output Resistance (Saturation Regime)

2.6.2 Drain-Induced Barrier Lowering (DIBL) As discussed above, threshold voltage can be approximated as a linear function of the drain voltage. According to Eq. (2.6.3), the Early voltage due to the DIBL effect can be calculated as: (2.6.7) VADIBLC= I dsat ( VADIBLC =

∂ I ds ∂ Vth −1 1 1 ) = (Vgst − ( + ∂ Vth ∂ Vds θ th ( L ) Abulk Vdsat V

(Vgsteff + 2vt)  AbulkVdsat  1 −  θrout(1 + PDIBLCBVbseff )  AbulkVdsat + Vgsteff + 2vt

During the derivation of Eq. (2.6.7), the parasitic resistance is assumed to be equal to 0. As expected, VADIBLC is a strong function of L as shown in Eq. (2.6.7). As channel length decreases, VADIBLC decreases very quickly. The combination of the CLM and DIBL effects determines the output resistance in the third region, as was shown in Figure 2-6. Despite the formulation of these two effects, accurate modeling of the output resistance in the saturation region requires that the coefficient θth (L) be replaced by θrout(L). Both θ th(L) and θrout(L) have the same channel length dependencies but different coefficients. The expression for θrout(L) is (2.6.8) θ rout ( L) = Pdiblc1 [exp( − Drout L / 2l t ) + 2 exp( − Drout L / l t )] + Pdiblc2 Parameters Pdiblc 1 , Pdiblc 2 , Pdiblcb and Drout are introduced to correct for DIBL effect in the strong inversion region. The reason why Dvt0 is not

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Strong Inversion Current and Output Resistance (Saturation Regime)

equal to Pdiblc 1 and Dvt 1 is not equal to Drout is because the gate voltage modulates the DIBL effect. When the threshold voltage is determined, the gate voltage is equal to the threshold voltage. But in the saturation region where the output resistance is modeled, the gate voltage is much larger than the threshold voltage. Drain induced barrier lowering may not be the same at different gate bias. Pdiblc 2 is usually very small (may be as small as 8.0E-3). If Pdiblc 2 is placed into the threshold voltage model, it will not cause any significant change. However it is an important parameter in VADIBL for long channel devices, because Pdiblc 2 will be dominant in Eq. (2.6.8) if the channel is long.

2.6.3 Current Expression without Substrate Current Induced Body Effect In order to have a continuous drain current and output resistance expression at the transition point between linear and saturation region, the VAsat parameter is introduced into the Early voltage expression. VAsat is the Early Voltage at Vds = Vdsat and is as follows: (2.6.9) Esat L + Vdsat + 2 Rdsv satC oxW ( Vgst − AbulkVds / 2) VAsat = 1 + Abulk Rds vsat Cox W Total Early voltage, VA, can be written as (2.6.10) VA = VAsat + (

1 VACLM

+

1 VADIBL

) −1

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2-27

Strong Inversion Current and Output Resistance (Saturation Regime)

The complete (with no impact ionization at high drain voltages) current expression in the saturation region is given by

Idso = Wvsat Cox (Vgst

V − Vdsat − Abulk Vdsat )(1 + ds ) VA

(2.6.11)

Furthermore, another parameter, Pvag , is introduced in VA to account for the gate bias dependence of VA more accurately. The final expression for Early voltage becomes (2.6.12)

VA = VAsat + (1 +

PvagVgs gsteff 1 1 )( + ) −1 E satL eff VACLM VADIBLC

2.6.4 Current Expression with Substrate Current Induced Body Effect When the electrical field near the drain is very large (> 0.1MV/cm), some electrons coming from the source will be energetic (hot) enough to cause impact ionization. This creates electron-hole pairs when they collide with silicon atoms. The substrate current Isub thus created during impact ionization will increase exponentially with the drain voltage. A well known Isub model [20] is given as: (2.6.13) I sub =

2-28

  Ai Bi l  I ds (Vds − Vdsat )exp  − Bi  Vds − Vdsat 

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Strong Inversion Current and Output Resistance (Saturation Regime)

The parameters Ai and Bi are determined from extraction. I sub will affect the drain current in two ways. The total drain current will change because it is the sum of the channel current from the source as well as the substrate current. The total drain current can now be expressed [21] as follows (2.6.14)

I ds = I dso + I sub    (Vds − Vdsat )  = Idso 1 +  Bi Bil  exp( )  Ai Vds − Vdsat 

The total drain current, including CLM, DIBL and SCBE, can be written as (2.6.15) I ds = Wv sat Cox ( Vgst − Abulk Vdsat )(1 +

Vds − Vdsat Vds − Vdsat )(1 + ) VA VASCBE

where VASCBE can also be called as the Early voltage due to the substrate current induced body effect. Its expression is the following (2.6.16) Bi Bi l VASCBE = exp( ) Ai Vds − Vdsat From Eq. (2.6.16), we can see that VASCBE is a strong function of Vds . In addition, we also observe that VASCBE is small only when Vds is large. This is why SCBE is important for devices with high drain voltage bias. The channel length and gate oxide dependence of VASCBE comes from Vdsat and l. We replace Bi with PSCBE2 and Ai/Bi with PSCBE1/L to yield the following expression for VASCBE

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2-29

Subthreshold Drain Current

(2.6.17) P P l = SCBE 2 exp( − SCBE1 ) VASCBE L Vds − Vdsat 1

The variables Pscbe 1 and Pscbe2 are determined experimentally.

2.7 Subthreshold Drain Current The drain current equation in the subthreshold region can be expressed as [2, 3] (2.7.1) I ds = I s0 (1 − exp( −

Vgs − Vth − Voff Vds )) exp( ) nv vt nvt tm (2.7.2)

I s0 = µ 0

W L

qε si N ch 2 vt 2φ s

Here the parameter vt is the thermal voltage and is given by KBT/q. V off is the offset voltage, as discussed in Jeng's dissertation [18]. Voff is an important parameter which determines the drain current at Vgs = 0. In Eq. (2.7.1), the parameter n is the subthreshold swing parameter. Experimental data shows that the subthreshold swing is a function of channel length and the interface state density. These two mechanisms are modeled by the following (2.7.3) Leff Leff   (Cdsc + CdscdVds + CdscbVbseff )exp(−DVT1 ) + 2 exp(− DVT1 )  Cd 2lt lt  Cit n = 1+ Nfactor + + Cox Cox Cox

where the term

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Effective Channel Length and Width

+

L eff Leff   ( Cdsc + CdscdVds + C dscb Vbseff ) exp( − DVT 1 ) + 2 exp( − DVT1 )  2l t lt 

represents the coupling capacitance between the drain or source to the channel. The parameters Cdsc , Cdscd and Cdscb are extracted. The parameter Cit in Eq. (2.7.3) is the capacitance due to interface states. From Eq. (2.7.3), it can be seen that subthreshold swing shares the same exponential dependence on channel length as the DIBL effect. The parameter Nfactor is introduced to compensate for errors in the depletion width capacitance calculation. Nfactor is determined experimentally and is usually very close to 1.

2.8 Effective Channel Length and Width The effective channel length and width used in all model expressions is given below (2.8.1)

L eff = Ldrawn − 2dL (2.8.2a)

Weff = Wdrawn − 2 dW (2.8.2b)

W eff = Wdrawn − 2 dW The only difference between Eq. (2.8.2a) and (2.8.2b) is that the former includes bias dependencies. The parameters dW and dL are modeled by the following

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Effective Channel Length and Width

(2.8.3) dW = dW '+ dWgV gsteff + dWb dW ' = Wint +

(Φ

s

− Vbseff − Φ s

)

Wl Ww W + Wwn + W ln wl Wwn W ln L W L W

(2.8.4) dL = Lint +

Ll Lw L + Lwn + L ln wl Lwn L ln L W L W

These complicated formulations require some explanation. From Eq. (2.8.3), the variable W int models represents the tradition manner from which "delta W" is extracted (from the intercepts of straights lines on a 1/Rds vs. Wdrawn plot). The parameters dWg and dWb have been added to account for the contribution of both front gate and back side (substrate) biasing effects. For dL, the parameter Lint represents the traditional manner from which "delta L" is extracted (mainly from the intercepts of lines from a Rds vs. Ldrawn plot). The remaining terms in both dW and dL are included for the convenience of the user. They are meant to allow the user to model each parameter as a function of Wdrawn , Ldrawn and their associated product terms. In addition, the freedom to model these dependencies as other than just simple inverse functions of W and L is also provided for the user. For dW, they are Wln and Wwn. For dL they are Lln and Lwn. By default all of the above geometrical dependencies for both dW and dL are turned off. Again, these equations are provided for the convenience of the user. As such, it is up to the user to adopt the correct extraction strategy to ensure proper use.

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Poly Gate Depletion Effect

2.9 Poly Gate Depletion Effect When a gate voltage is applied to a heavily doped poly-silicon gate, e.g. NMOS with n+ poly-silicon gate, a thin depletion layer will be formed at the interface between the poly-silicon and gate oxide. Although this depletion layer is very thin due to the high doping concentration of the poly-Si gate, its effect cannot be ignored in the 0.1µm regime since the gate oxide thickness will also be very small, possibly 50Å or thinner. Figure 2-7 shows an NMOSFET with a depletion region in the n+ poly-silicon gate. The doping concentration in the n+ poly-silicon gate is Ngate and the doping concentration in the substrate is Nsub. The gate oxide thickness is Tox . The depletion width in the poly gate is Xp. The depletion width in the substrate is Xd. If we assume the doping concentration in the gate is infinite, then no depletion region will exist in the gate, and there would be one sheet of positive charge whose thickness is zero at the interface between the poly-silicon gate and gate oxide. In reality, the doping concentration is, of course, finite. The positive charge near the interface of the poly-silicon gate and the gate oxide is distributed over a finite depletion region with thickness Xp. In the presence of the depletion region, the voltage drop across the gate oxide and the substrate will be reduced, because part of the gate voltage will be dropped across the depletion region in the gate. That means the effective gate voltage will be reduced.

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Poly Gate Depletion Effect

Ngate

Figure 2-7. Charge distribution in a MOSFET with the poly gate depletion effect. The device is in the strong inversion region.

The effective gate voltage can be calculated in the following manner. Assume the doping concentration in the poly gate is uniform. The voltage drop in the poly gate (Vpoly ) can be calculated as (2.9.1) V poly =

1 X poly E poly = 2

2 Ngate qN poly X poly

2 ε si

where Epoly is the maximum electrical field in the poly gate. The boundary condition at the interface of poly gate and the gate oxide is (2.9.2) ε ox Eox = ε si E poly = 2qε si Ngate polyV poly

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Poly Gate Depletion Effect

where Eox is the electrical field in the gate oxide. The gate voltage satisfies (2.9.3)

Vgs − VFB − Φs = V poly + Vox where Vox is the voltage drop across the gate oxide and satisfies Vox = Eox Tox . According to the equations (2.9.1) to (2.9.3), we obtain the following (2.9.4)

a(Vgs −VFB − Φs −Vpoly) −Vpoly = 0 2

where

(2.9.5)

a=

ε ox

2

2 qε si N gateTox

2

By solving the equation (2.9.4), we get the effective gate voltage (Vgs_eff) which is equal to: (2.9.6) Vgs_eff

2 2 qε siN gateTox  2εox (Vgs −VFB − Φs )  =VFB +Φs + 1+ −1 2 2   εox qεsiNgateTox  

Figure 2-8 shows Vgs_eff / Vg s versus the gate voltage. The threshold voltage is assumed to be 0.4V. If Tox = 40 Å, the effective gate voltage can be reduced by 6% due to the poly gate depletion effect as the applied gate voltage is equal to 3.5V.

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Poly Gate Depletion Effect

1.00

Vgs_eff / Vgs

80

60 0.95

0.90 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Figure 2-8. The effective gate voltage versus applied gate voltage at different gate oxide thickness.

The drain current reduction in the linear region as a function of the gate voltage can now be determined. Assume the drain voltage is very small, e.g. 50mV. Then the linear drain current is proportional to Cox(Vgs - Vth). The ratio of the linear drain current with and without poly gate depletion is equal to: (2.9.7)

Figure 2-9 shows I d s(Vgs_eff ) / Ids(Vg s) versus the gate voltage using Eq. (2.9.7). The drain current can be reduced by several percent due to gate depletion.

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CHAPTER 3: Unified I-V Model

The development of separate model expressions for such device operation regimes as subthreshold and strong inversion were discussed in Chapter 2. Although these expressions can accurately describe device behavior within their own respective region of operation, problems are likely to occur between two well-described regions or within transition regions. In order to circumvent this issue, a unified model should be synthesized to not only preserve region-specific expressions but also to ensure the continuities of current and conductance and their derivatives in all transition regions as well. Such high standards are kept in BSIM3v3.2.1 . As a result, convergence and simulation efficiency are much improved. This chapter will describe the unified I-V model equations. While most of the parameter symbols in this chapter are explained in the following text, a complete description of all IV model parameters can be found in Appendix A.

3.1 Unified Channel Charge Density Expression Separate expressions for channel charge density are shown below for subthreshold (Eq. (3.1.1a) and (3.1.1b)) and strong inversion (Eq. (3.1.2)). Both expressions are valid for small Vds.

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3-1

Unified Channel Charge Density Expression

(3.1.1a) Vgs − Vth Q chsubs 0 = Q 0 exp( ) nvt

where Q0 is (3.1.1b) Q0 =

qεsiNch Voff vt exp( − ) 2φs nvt

Qchs 0 = Cox( Vgs − Vth)

(3.1.2)

In both Eqs. (3.1.1a) and (3.1.2), the parameters Qchsubs0 and Qchs0 are the channel charge densities at the source for very small Vds. To form a unified expression, an effective (Vgs-Vth) function named Vgsteff is introduced to describe the channel charge characteristics from subthreshold to strong inversion (3.1.3)

Vgsteff

 Vgs − Vth  2 n vt ln1 + exp( ) 2 n vt   = 2Φs Vgs − Vth − 2Voff 1 + 2 n COX exp( − ) qεsiN ch 2 n vt

The unified channel charge density at the source end for both subthreshold and inversion region can therefore be written as (3.1.4)

Qchs0 = CoxVgsteff Figures 3-1 and 3-2 show the smoothness of Eq. (3.1.4) from subthreshold to strong inversion regions. The Vgsteff expression will be used again in subsequent sections of this chapter to model the drain current.

3-2

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Unified Channel Charge Density Expression

Vgs-Vth (V) Figure 3-1. The Vgsteff function vs. (Vgs-V th ) in linear scale.

Vgs-V th (V) Figure 3-2. Vgsteff function vs. (Vgs -Vth) in log scale.

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3-3

Unified Channel Charge Density Expression

Eq. (3.1.4) serves as the cornerstone of the unified channel charge expression at the source for small Vds. To account for the influence of Vds , the Vgsteff function must keep track of the change in channel potential from the source to the drain. In other words, Eq. (3.1.4) will have to include a y dependence. To initiate this formulation, consider first the re-formulation of channel charge density for the case of strong inversion (3.1.5)

Qchs(y) = Cox(Vgs − Vth − AbulkVF(y)) The parameter VF(y) stands for the quasi-Fermi potential at any given point y, along the channel with respect to the source. This equation can also be written as

Qchs ( y ) = Qchs 0 + ∆Qchs ( y )

(3.1.6)

The term ∆Qchs(y) is the incremental channel charge density induced by the drain voltage at point y. It can be expressed as

∆Qchs( y ) = − CoxAbulkVF ( y )

(3.1.7)

For the subthreshold region (Vgs<
Vgs − Vth − AbulkVF ( y) ) nvt AbulkVF ( y) = Qchsubs0 exp(− ) nvt

Qchsubs( y) = Q0 exp(

3-4

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Unified Channel Charge Density Expression

A Taylor series expansion of the right-hand side of Eq. (3.1.8) yields the following (keeping only the first two terms) (3.1.9)

Qchsubs (y) = Qchsubs 0(1 −

AbulkVF ( y) ) nvt

Analogous to Eq. (3.1.6), Eq. (3.1.9) can also be written as (3.1.10)

Qchsubs( y) = Qchsubs0 + ∆Qchsubs( y) The parameter ∆Qchsubs(y) is the incremental channel charge density induced by the drain voltage in the subthreshold region. It can be written as (3.1.11)

∆Qchsubs( y) = −

AbulkVF ( y ) Qchsubs0 nvt

Note that Eq. (3.1.9) is valid only when VF (y) is very small, which is maintained fortunately, due to the fact that Eq. (3.1.9) is only used in the linear regime (i.e. Vds ≤2vt). Eqs. (3.1.6) and (3.1.10) both have drain voltage dependencies. However, they are decupled and a unified expression for Qch (y) is needed. To obtain a unified expression along the channel, we first assume (3.1.12) ∆Qch( y )

∆Qchs( y ) ∆Qchsubs( y ) = ∆Qchs ( y ) + ∆Qchsubs ( y )

Here, ∆Qch (y) is the incremental channel charge density induced by the drain voltage. Substituting Eq. (3.1.7) and (3.1.11) into Eq. (3.1.12), we obtain

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3-5

Unified Mobility Expression

(3.1.13) ∆Q ch( y )

VF ( y ) = Qchs 0 Vb

where Vb = (Vgsteff + n*vt )/Abulk . In order to remove any association between the variable n and bias dependencies (Vgsteff) as well as to ensure more precise modeling of Eq. (3.1.8) for linear regimes (under subthreshold conditions), n is replaced by 2. The expression for Vb now becomes (3.1.14)

Vb =

Vgsteff + 2 vt Abulk

A unified expression for Qch (y) from subthreshold to strong inversion regimes is now at hand (3.1.15)

Qch ( y ) = Qchs0(1 −

VF ( y ) ) Vb

The variable Qchs0 is given by Eq. (3.1.4).

3.2 Unified Mobility Expression Unified mobility model based on the Vgsteff expression of Eq. 3.1.3 is described in the following.

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Unified Linear Current Expression

(mobMod = 1) µeff =

1 + (U a + U c Vbseff )(

µo + 2Vth

Vgsteff TOX

(3.2.1) ) + U b(

Vgsteff + 2Vth 2 ) TOX

To account for depletion mode devices, another mobility model option is given by the following (mobMod = 2)

(3.2.2) µo µeff = Vgsteff Vgsteff 2 1 + (U a + UcVbseff )( ) + Ub ( ) TOX TOX

To consider the body bias dependence of Eq. 3.2.1 further, we have introduced the following expression (For mobMod = 3)

µeff =

(3.2.3)

µo Vgsteff + 2 Vth Vgsteff + 2Vth 2 1 + [U a ( ) + U b( ) ](1 + UcVbseff ) TOX TOX

3.3 Unified Linear Current Expression 3.3.1 Intrinsic case (R ds=0) Generally, the following expression [2] is used to account for both drift and diffusion current

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3-7

Unified Linear Current Expression

(3.3.1) Id ( y )

dVF( y ) = WQc h( y ) µne ( y ) dy

where the parameter une(y) can be written as

µne ( y ) =

(3.3.2)

µeff Ey 1+ Esat

Substituting Eq. (3.3.2) in Eq. (3.3.1) we get

Id ( y ) = WQchso (1 −

VF ( y ) µeff dVF ( y ) ) Vb 1 + Ey dy Esat

(3.3.3)

Eq. (3.3.3) resembles the equation used to model drain current in the strong inversion regime. However, it can now be used to describe the current characteristics in the subthreshold regime when Vds is very small ( Vds<2vt ). Eq. (3.3.3) can now be integrated from the source to drain to get the expression for linear drain current in the channel. This expression is valid from the subthreshold regime to the strong inversion regime (3.3.4)

I ds 0

3-8

 V W µ eff Q chs0V ds 1 − ds 2Vb  =  V  L 1 + ds  E sat L  

   

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Unified Vdsat Expression

3.3.2 Extrinsic Case (R ds > 0) The current expression when Rds > 0 can be obtained based on Eq. (2.5.9) and Eq. (3.3.4). The expression for linear drain current from subthreshold to strong inversion is: (3.3.5)

Ids =

Idso RdsIdso 1+ Vds

3.4 Unified Vdsat Expression 3.4.1 Intrinsic case (R ds=0) To get an expression for the electric field as a function of y along the channel, we integrate Eq. (3.3.1) from 0 to an arbitrary point y. The result is as follows (3.4.1) I dso

Ey = ( WQchs0 µeff −

Idso 2 2 Ids 0WQchs 0µ eff y ) − Esat Vb

If we assume that drift velocity saturates when Ey=Esat, we get the following expression for I dsat

Idsat =

Wµeff Qchs0 Esat LVb 2 L( Esat L + Vb)

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(3.4.2)

3-9

Unified Vdsat Expression

Let Vds=Vdsat in Eq. (3.3.4) and set this equal to Eq. (3.4.2), we get the following expression for Vdsat

EsatL( Vgsteff + 2vt ) Vdsat = AbulkEsatL + Vgsteff + 2vt

(3.4.3)

3.4.2 Extrinsic Case (R ds >0) The Vdsat expression for the extrinsic case is formulated from Eq. (3.4.3) and Eq. (2.5.10) to be the following (3.4.4a)

Vdsat =

− b − b − 4 ac 2a 2

where (3.4.4b)

a = A bulk 2Weff νsatCoxR DS + (

1 − 1) A bulk λ (3.4.4c)

2   b = −  (Vgsteff + 2 vt )( − 1) + A bulk EsatLeff + 3 A bulk (Vgsteff + 2 v t)WeffνsatCoxR DS    λ (3.4.4d)

c = (Vgsteff + 2vt ) E satLeff + 2(Vgsteff + 2vt ) WeffνsatCoxRDS 2

λ = A1Vgsteff + A2

3-10

(3.4.4e)

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Unified Saturation Current Expression

The parameter λ is introduced to account for non-saturation effects. Parameters A1 and A2 can be extracted.

3.5 Unified Saturation Current Expression A unified expression for the saturation current from the subthreshold to the strong inversion regime can be formulated by introducing the Vgsteff function into Eq. (2.6.15). The resulting equations are the following (3.5.1)

Ids =

Idso( Vdsat )  1 + V ds − V dsat   1 + Vds − V dsat  RdsIdso( Vdsat )  VA   VASCBE  1+ Vdsat

where (3.5.2)

VA = VAsat + (1 +

Pvag Vgsteff 1 1 )( + ) −1 EsatLeff VACLM VADIBLC (3.5.3)

EsatLeff + Vdsat + 2 RDSνsatCox WeffVgsteff [1 − VAsat =

AbulkVdsat ] 2(Vgsteff + 2vt )

2 / λ − 1 + RDSνsatCoxWeffAbulk

VACLM =

AbulkEsatLeff + Vgsteff (Vds − Vdsat ) PCLM AbulkEsat litl

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(3.5.4)

3-11

Single Current Expression for All Operating Regimes of Vgs and Vds

(3.5.5) VADIBLC =

(Vgsteff + 2 vt) AbulkVdsat   1 −   θ rout (1 + PDIBLCB Vbseff ) AbulkVdsat + Vgsteff + 2vt 

(3.5.6) L eff L eff  θrout = PDIBLC 1 exp( − DROUT ) + 2 exp( − DROUT 2l t 0 l t0 

 )  + PDIBLC 2 

(3.5.7)

1 VASCBE

=

P scbe 2 − Pscbe 1 litl  exp    Vds − Vdsat  Leff

3.6 Single Current Expression for All Operating Regimes of Vgs and Vds The Vgsteff function introduced in Chapter 2 gave a unified expression for the linear drain current from subthreshold to strong inversion as well as for the saturation drain current from subthreshold to strong inversion, separately. In order to link the continuous linear current with that of the continuous saturation current, a smooth function for Vds is introduced. In the past, several smoothing functions have been proposed for MOSFET modeling [22-24]. The smoothing function used in BSIM3 is similar to that proposed in [24]. The final current equation for both linear and saturation current now becomes (3.6.1)

Ids =

Idso( Vdseff )  1 + Vds − V dseff  1 + V ds − V dseff  RdsIdso( Vdseff )   VA V ASCBE  1+ Vdseff

Most of the previous equations which contain Vds and Vdsat dependencies are now substituted with the Vdseff function. For example, Eq. (3.5.4) now becomes

3-12

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Single Current Expression for All Operating Regimes of Vgs and Vds

(3.6.2)

VACLM =

AbulkEsatLeff + Vgsteff (Vds − Vdseff ) PCLMAbulkEsat litl

Similarly, Eq. (3.5.7) now becomes (3.6.3)

1 VASCBE

=

Pscbe 2  − Pscbe1 litl  exp   Vds − Vdseff  Leff

The Vdseff expression is written as

Vdseff = Vdsat −

(

1 Vdsat − Vds − δ + (Vdsat − Vds − δ)2 + 4δVdsat 2

)

(3.6.4)

The expression for Vdsat is that given under Section 3.4. The parameter δ in the unit of volts can be extracted. The dependence of Vdseff on Vds is given in Figure 33. The Vdseff function follows Vds in the linear region and tends to Vdsat in the saturation region. Figure 3-4 shows the effect of δ on the transition region between linear and saturation regimes.

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3-13

Single Current Expression for All Operating Regimes of Vgs and Vds

Figure 3-3. Vdseff vs. Vds for δ=0.01 and different Vgs.

Figure 3-4. Vdseff vs. Vds for Vgs =3V and different δ values.

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Substrate Current

3.7 Substrate Current The substrate current in BSIM3v3.2.1 is modeled by (3.7.1) I sub =

α 0 + α1 ⋅ Leff Leff

(V

ds

  β0 I ds0  − Vdseff )exp −  Vds − Vdseff    1 + Rds I ds0 Vdseff

 Vds − Vdseff  1 +  VA  

where parameters α0 and β0 are impact ionization coefficients; parameter α1 improves the Isub scalability.

3.8 A Note on Vbs All Vbs terms have been substituted with a Vbseff expression as shown in Eq. (3.8.1). This is done in order to set an upper bound for the body bias value during simulations. Unreasonable values can occur if this expression is not introduced. (3.8.1) Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ1) 2 − 4δ 1Vbc ]

where δ1 =0.001V. Parameter Vbc is the maximum allowable Vbs value and is obtained based on the condition of dVth/dVbs = 0 for the Vth expression of 2.1.4.

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3-15

CHAPTER 4: Capacitance Modeling

Accurate modeling of MOSFET capacitance plays equally important role as that of the DC model. This chapter describes the methodology and device physics considered in both intrinsic and extrinsic capacitance modeling in BSIM3v3.3. Detailed model equations are given in Appendix B. One of the important features of BSIM3v3.2 is introduction of a new intrinsic capacitance model (capMod=3 as the default model), considering the finite charge thickness determined by quantum effect, which becomes more important for thinner Tox CMOS technologies. This model is smooth, continuous and accurate throughout all operating regions.

4.1 General Description of Capacitance Modeling BSIM3v3.3 models capacitance with the following general features: • Separate effective channel length and width are used for capacitance models. • The intrinsic capacitance models, capMod=0 and 1, use piece-wise equations. capMod=2 and 3 are smooth and single equation models; therefore both charge and capacitance are continous and smooth over all regions. • Threshold voltage is consistent with DC part except for capMod=0, where a longchannel V th is used. Therefore, those effects such as body bias, short/narrow channel and DIBL effects are explicitly considered in capMod=1, 2, and 3. • Overlap capacitance comprises two parts: (1) a bias-independent component which models the effective overlap capacitance between the gate and the heavily doped source/drain; (2) a gate-bias dependent component between the gate and the lightly doped source/drain region.

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4-1

Geometry Definition for C-V Modeling

• Bias-independent fringing capacitances are added between the gate and source as well as the gate and drain.

Name

Function

Default

Unit

capMod

Flag for capacitance models

3

(True)

vfbcv

the flat-band voltage for capMod = 0

-1.0

(V)

acde

Exponential coefficient for XDC for accumulation and depletion regions

1

(m/V)

moin

Coefficient for the surface potential

15

(V 0.5)

cgso

Non-LDD region G/S overlap C per channel length

Calculated

F/m

cgdo

Non-LDD region G/D overlap C per channel length

Calculated

F/m

CGS1

Lightly-doped source to gate overlap capacitance

0

(F/m)

CGD1

Lightly-doped drain to gate overlap capacitance

0

(F/m)

CKAPPA

Coefficient for lightly-doped overlap capacitance

0.6

CF

Fringing field capacitance

equation (4.5.1)

(F/m)

CLC

Constant term for short channel model

0.1

µm

CLE

Exponential term for short channel model

0.6

DWC

Long channel gate capacitance width offset

Wint

µm

DLC

Long channel gate capacitance length offset

Lint

µm

Table 4-1. Model parameters in capacitance models.

4.2 Geometry Definition for C-V Modeling For capacitance modeling, MOSFET’s can be divided into two regions: intrinsic and extrinsic. The intrinsic capacitance is associated with the region between the metallurgical source and drain junction, which is defined by the effective length

4-2

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Geometry Definition for C-V Modeling

(Lactive) and width (W active ) when the gate to S/D region is at flat band voltage. Lactive and Wactive are defined by Eqs. (4.2.1) through (4.2.4). (4.2.1)

Lactive = Ldrawn − 2δLeff (4.2.2)

Wactive = Wdrawn − 2δWeff (4.2.3)

δLeff = DLC +

Llc Lwc Lwlc + Lwn + Lln Lwn L ln L W L W (4.2.4)

δWeff = DWC+

Wlc Wwc Wwlc + Wwn + W ln Wwn W ln L W L W

The meanings of DWC and DLC are different from those of Wint and Lint in the IV model. Lactive and Wactive are the effective length and width of the intrinsic device for capacitance calculations. Unlike the case with I-V, we assumed that these dimensions have no voltage bias dependence. The parameter δLeff is equal to the source/drain to gate overlap length plus the difference between drawn and actual POLY CD due to processing (gate printing, etching and oxidation) on one side. Overall, a distinction should be made between the effective channel length extracted from the capacitance measurement and from the I-V measurement. Traditionally, the Leff extracted during I-V model characterization is used to gauge a technology. However this Leff does not necessarily carry a physical meaning. It is just a parameter used in the I-V formulation. This Leff is therefore very sensitive to the I-V equations used and also to the conduction characteristics of the LDD

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4-3

Methodology for Intrinsic Capacitance Modeling

region relative to the channel region. A device with a large Leff and a small parasitic resistance can have a similar current drive as another with a smaller Leff but larger Rds. In some cases Leff can be larger than the polysilicon gate length giving Leff a dubious physical meaning. The Lactive parameter extracted from the capacitance method is a closer representation of the metallurgical junction length (physical length). Due to the graded source/ drain junction profile the source to drain length can have a very strong bias dependence. We therefore define Lactive to be that measured at gate to source/drain flat band voltage. If DWC, DLC and the newly-introduced length/ width dependence parameters (Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc) are not specified in technology files, BSIM3v3.3 assumes that the DC bias-independent Leff and Weff (Eqs. (2.8.1) - (2.8.4)) will be used for C-V modeling, and DWC, DLC,Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc will be set equal to the values of their DC counterparts (default values).

4.3 Methodology for Intrinsic Capacitance Modeling 4.3.1 Basic Formulation To ensure charge conservation, terminal charges instead of the terminal voltages are used as state variables. The terminal charges Qg, Qb, Qs, and Qd are the charges associated with the gate, bulk, source, and drain termianls, respectively. The gate charge is comprised of mirror charges from these components: the channel inversion charge (Qinv ), accumulation charge (Qacc ) and the substrate depletion charge (Qsub ).

4-4

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Methodology for Intrinsic Capacitance Modeling

The accumulation charge and the substrate charge are associated with the substrate while the channel charge comes from the source and drain terminals (4.3.1)

Qg = −( Qsub + Qinv + Qacc )  Qb = Qacc + Qsub Q = Q + Q s d  inv

The substrate charge can be divided into two components - the substrate charge at zero source-drain bias (Qsub0 ), which is a function of gate to substrate bias, and the additional non-uniform substrate charge in the presence of a drain bias (δQsub). Qg now becomes (4.3.2)

Q g = −(Qinv + Qacc + Q sub0 + δQsub )

The total charge is computed by integrating the charge along the channel. The threshold voltage along the channel is modified due to the nonuniform substrate charge by (4.3.3) Vth ( y ) = Vth (0) + ( Abulk −1)Vy

(4.3.4)  Qc = Wactive ∫ qcdy = −WactiveCox ∫ (Vgt − AbulkVy )dy  0 0  L active L active  Qg = Wactive ∫ qg dy = WactiveCox ∫ (Vgt + Vth − VFB − Φs − Vy )dy 0 0  L active L active  Qb = Wactive ∫0 qb dy = −WactiveCox ∫0 Vth − VFB − Φ s + Abulk −1 Vy dy  Lactive

L active

(

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

(

) )

4-5

Methodology for Intrinsic Capacitance Modeling

Substituting the following

dy =

dV y εy

and (4.3.5) I ds =

Wactiveµeff Cox  A  Vgt − bulk Vds Vds = Wactiveµeff Cox (Vgt − AbulkVy )E y Lactive  2 

into Eq. (4.3.4), we have the following upon integration (4.3.6)       2 2 A A V   bulk bulk ds  Q c = −W active L active C ox V gt − V ds +  A bulk  2   12  V gt − V ds     2           2 V ds Abulk V ds    +  Q g = − Q sub 0 + W active Lactive C ox  V gt − A 2    12  V gt − bulk V ds     2      Q b = − Q g − Q c = Q sub + Q sub 0 + Q acc      where

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Methodology for Intrinsic Capacitance Modeling

(4.3.7)  Q sub 0 = −W active L active 2 ε si qN sub (2 Φ B − V bs )       2    1 − Abulk V + Abulk ( Abulk − 1)V ds  δ Q sub = W active L active C ox  ds A 2    12  V gt − bulk V ds     2   

The inversion charges are supplied from the source and drain electrodes such that Qinv = Qs + Qd. The ratio of Qd and Qs is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (XPART = 0, 0.5 and 1) which are the ratios of Qd to Qs in the saturation region. We will revisit charge partitioning in Section 4.3.4. All capacitances are derived from the charges to ensure charge conservation. Since there are four terminals, there are altogether 16 components. For each component (4.3.8) ∂Qi Ci j = ∂V j

where i and j denote the transistor terminals. In addition

∑C

ij

i

=

∑C

ij

=0

j

4.3.2 Short Channel Model In deriving the long channel charge model, mobility is assumed to be constant with no velocity saturation. Therefore in saturation region (Vds ≥Vdsat), the carrier density at the drain end is zero. Since no channel length modulation is assumed, the channel charge will remain a constant throughout the saturation region. In essence, the channel charge in the

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4-7

Methodology for Intrinsic Capacitance Modeling

saturation region is assumed to be zero. This is a good approximation for long channel devices but fails when Leff < 2 µm. If we define a drain bias, Vdsat,cv , in which the channel charge becomes a constant, we will find that Vdsat,cv in general is larger than Vdsat but smaller than the long channel Vdsat , given by Vgt/Abulk. However, in old long channel charge models, Vdsat,cv is set to Vgt/Abulk independent of channel length. Consequently, Cij /Leff has no channel length dependence (Eqs. (4.3.6), (4.37)). A pseudo short channel modification from the long channel has been used in the past. It involved the parameter Abulk in the capacitance model which was redefined to be equal to Vgt/Vdsat, thereby equating Vdsat,cv and Vdsat. This overestimated the effect of velocity saturation and resulted in a smaller channel capacitance. The difficulty in developing a short channel model lies in calculating the charge in the saturation region. Although current continuity stipulates that the charge density in the saturation region is almost constant, it is difficult to calculate accurately the length of the saturation region. Moreover, due to the exponentially increasing lateral electric field, most of the charge in the saturation region are not controlled by the gate electrode. However, one would expect that the total charge in the channel will exponentially decrease with drain bias. Experimentally, (4.3.9) Vdsat ,iv < Vdsat ,cv < Vdsat ,iv

Lactive →∞

=

V gsteff ,cv Abulk

and Vdsat,cv is modeled by the following

4-8

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Methodology for Intrinsic Capacitance Modeling

(4.3.10a) Vdsat,cv cdsat ,cv =

V gsteff ,cv   CLC  Abulk  1 +     L active  

CLE

   

(4.3.10b)

  Vgs −Vth − voffcv    Vgsteff,cv = noff⋅ nvt ln1 + exp  noff ⋅ nv  t  

Parameters noff and voffcv are introduced to better fit measured data above subthreshold regions. The parameter Abulk is substituted Abulk0 in the long channel equation by (4.3.11)

  CLC  CLE   Abulk ' = Abulk 0  1 +    L   active   (4.3.11a)   A0 Leff K1o x B0   1  Abulk = 1 + + ⋅  2 Φ −V L + 2 X X   Weff '+B1 1 + KetaVbseff s bseff  eff J dep  

In (4.3.11), parameters CLC and CLE are introduced to consider channellength modulation.

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4-9

Methodology for Intrinsic Capacitance Modeling

4.3.3 Single Equation Formulation Traditional MOSFET SPICE capacitance models use piece-wise equations. This can result in discontinuities and non-smoothness at transition regions. The following describes single-equation formulation for charge, capacitance and voltage modeling in capMod=2 and 3. (a) Transition from depletion to inversion region The biggest discontinuity is the inversion capacitance at threshold voltage. Conventional models use step functions and the inversion capacitance changes abruptly from 0 to Cox. Concurrently, since the substrate charge is a constant, the substrate capacitance drops abruptly to 0 at threshold voltage. Both of these effects can cause oscillation during circuit simulation. Experimentally, capacitance starts to increase almost quadratically at ~0.2V below threshold voltage and levels off at ~0.3V above threshold voltage. For analog and low power circuits, an accurate capacitance model around the threshold voltage is very important. The non-abrupt channel inversion capacitance and substrate capacitance model is developed from the I-V model which uses a single equation to formulate the subthreshold, transition and inversion regions. The new channel inversion charge model can be modified to any charge model by substituting Vgt with Vgsteff,cv as in the following

Q(Vgt ) = Q(Vgsteff,CV )

(4.3.12)

Capacitance now becomes

4-10

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Methodology for Intrinsic Capacitance Modeling

(4.3.13) C(Vgt ) = C(Vgsteff,CV )

∂Vgsteff,CV Vgs,ds,bs

The “inversion” charge is always non-zero, even in the accumulation region. However, it decreases exponentially with gate bias in the subthreshold region. (b) Transition from accumulation to depletion region An effective flatband voltage VFBeff is used to smooth out the transition between accumulation and depletion regions. It affects the accumulation and depletion charges

{

}

VFBeff = vfb − 0.5 V3 + V3 + 4δ 3 vfb 2

(4.3.14) where V3 = vfb − Vgs + Vbseff − δ 3 ; δ 3 = 0.02V

(4.3.15)

vfb = Vth − Φs − K1ox Φs −Vbseff

In BSIM3v3.3, a bias-independent V th is used to calculate vfb for capMod = 1, 2 and 3. For capMod = 0, Vfbcv is used instead (refer to the appendices).

(

Qacc = −WactiveLactive Cox VFBeff − vfb

)

(4.3.16)

(4.3.17) 4 Vgs −VFBeff −Vgsteff,CV −Vbseff  K 2 Qsub0 = −WactiveLactiveCox ⋅ 1ox −1+ 1+  2  K1ox2  

(

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)

4-11

Methodology for Intrinsic Capacitance Modeling

(c) Transition from linear to saturation region An effective Vds , Vcveff, is used to smooth out the transition between linear and saturation regions. It affects the inversion charge.

{

Vcveff = Vdsat,cv − 0.5 V4 + V4 + 4δ4Vdsat, cv 2

} whereV = V 4

dsat, cv

(4.3.18)

− Vds − δ 4; δ4 = 0.02V (4.3.19)

  2  2  Abulk ' Vcveff A '    Qinv = −Wactive Lactive Cox Vgsteff ,cv− bulk Vcveff  +   Abulk ' 2   12Vgsteff ,cv− V     2 cveff  

(4.3.20) δQsub

   2  1 − A ' A ' V ( ) 1 − Abulk ' bulk bulk cveff  = Wactive LactiveCox  Vcveff −  2 A '   bulk 12Vgsteff ,cv − Vcveff       2

Below is a list of all the three partitioning schemes for the inversion charge: (i) The 50/50 charge partition This is the simplest of all partitioning schemes in which the inversion charges are assumed to be contributed equally from the source and drain nodes.

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Methodology for Intrinsic Capacitance Modeling

(4.3.21)     Abulk ' 2 Vcveff 2 Wactive Lactive Cox  Abulk '  Qs = Qd = 0 .5Qinv = − Vgsteff,cv− Vcveff +  Abulk ' 2 2   12Vgsteff,cv− Vcveff       2

(ii) The 40/60 channel-charge partition This is the most physical model of the three partitioning schemes in which the channel charges are allocated to the source and drain terminals by assuming a linear dependence on the position y. (4.3.22)   Q s = Wactive   Q = W active  d

 y qc 1 −  L active 0 Lactive y ∫ q c L active dy 0

Lactive

∫

  dy 

(4.3.23) Qs = −

4 2 2  3 2 2 3 VgsteffCV − VgsteffCV Abulk 'Vcveff + VgsteffCV(Abulk 'Vcveff ) − ( Abulk 'Vcveff )  3 3 15  A '    2VgsteffCV − bulk Vcveff  2   WactiveLactiveCox

2

(4.3.24) Qd = −

(

)

(

) (

)

WactiveLactiveCox V 3 − 5V cv2 A ' V + V cv A ' V 2 − 1 A ' V 3  gsteff bulk cveff gsteff bulk cveff bulk cveff  2  gsteffcv  3 5 Abulk'    2Vgsteffcv − Vcveff    2

(iii) The 0/100 Charge Partition In fast transient simulations, the use of a quasi-static model may result in a large unrealistic drain current spike. This partitioning scheme is developed to artificially suppress the drain current spike by assigning all inversion

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4-13

Charge-Thickness Capacitance Model

charges in the saturation region to the source electrode. Notice that this charge partitioning scheme will still give drain current spikes in the linear region and aggravate the source current spike problem.

(4.3.25)   2 V  Abulk ' Vcveff Abulk ' Vcveff gsteff,c gstefcvf  Qs = −Wactive Lactive Cox  + − Abulk '  2 4   24 Vgsteff,c − Vcveff     gsteffcv   2

(

)

(4.3.26)   2 V  Abulk ' Vcveff 3 Abulk ' Vcveff gsteffcv gsteff,c  Qd = − Wactive LactiveC ox  − + Abulk '  2 4 V  8 − V    gsteffcv cveff   gsteff,c   2

(

)

(d) Bias-dependent threshold voltage effects on capacitance Consistent Vth between DC and CV is important for acurate circuit simulation. capMod=1, 2 and 3 use the same Vth as in the DC model. Therefore, those effects, such as body bias, DIBL and short-channel effects are all explicitly considered in capacitance modeling. In deriving the capacitances additional differentiations are needed to account for the dependence of threshold voltage on drain and substrate biases.

4.4 Charge-Thickness Capacitance Model Current MOSFET models in SPICE generally overestimate the intrinsic capacitance and usually are not smooth at Vfb and Vth. The discrepancy is more

4-14

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Charge-Thickness Capacitance Model

pronounced in thinner Tox devices due to the assumption of inversion and accumulation charge being located at the interface. The charge sheet model or the band-gap(Eg)-reduction model of quantum effect [31] improves the

ΦB

and thus

the Vth modeling but is inadequate for CV because they assume zero charge thickness. Numerical quantum simulation results in Figure 4-1 indicate the significant charge thickness in all regions of the CV curves [32]. This section describes the concepts used in the charge-thichness model (CTM). Appendix B lists all charge equations. A full report and anaylsis of the CTM model

1.0

E 2

0.15

Cgg (µF/cm )

Normalized Charge Distribution

can be found in [32].

D

0.10

C

E A

0.8

D

B

0.6 0.4

C

0.2 -4

-3

A

-2

-1 0 Vgs (V)

1

2

3

Tox=30A

0.05

-3

Nsub=5e17cm

B 0.00 0

20

40

60

Depth (A)

Figure 4-1. Charge distribution from numerical quantum simulations show significant charge thickness at various bias conditions shown in the inset.

CTM is a charge-based model and therefore starts with the DC charge thicknss, XDC . The charge thicknss introduces a capacitance in series with Cox as illustrated in Figure 4-2, resulting in an effective Cox , Coxeff. Based on numerical selfconsistent solution of Shrodinger, Poisson and Fermi-Dirac equations, universal and analytical XDC models have been developed. Coxeff can be expressed as

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Charge-Thickness Capacitance Model

(4.4.1) C oxeff =

C oxC cen C ox + C cen

where

Ccen = ε si X DC

Vgs Poly depl.

Vgse Cox

Φs

Cacc

Cdep

Cinv

B

Figure 4-2. Charge-thickness capacitance concept in CTM. Vgse accounts for the poly depletion effect.

(i) XDC for accumulation and depletion The DC charge thickness in the accumulation and depletion regions can be expressed by [32] (4.4.2) −0.25  Vgs −Vbs −Vfb  1  N sub  X DC = Ldebyeexpacde⋅  ⋅   16 3 Tox  2 ×10   

4-16

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Charge-Thickness Capacitance Model

where XDC is in the unit of cm and (Vgs - Vbs - vfb) / Tox has a unit of MV/cm. The model parameter acde is introduced for better fitting with a default value of 1. For numerical statbility, (4.4.2) is replaced by (4.4.3) (4.4.3) X DC = X max −

(

1 X0 + 2

X 02 + 4δ x X max

)

where

X 0 = X max − X DC − δ x and Xmax=Ldebye/3;

δx =10-3 Tox.

(ii) XDC of inversion charge The inversion charge layer thichness [32] can be formulated as (4.4.4) XDC =

−7

1.9×10

 V + 4(Vth − vfb−2ΦB )   1 + gsteff  2Tox  

0.7

[cm]

Through vfb in (4.3.30), this equation is found to be applicable to N+ or P+ poly-Si gates as well as other future gate materials. Figure 4-3 illustrates the universality of (4.3.30) as verified by the numerical quantum simulations, where the x-axe

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4-17

Charge-Thickness Capacitance Model

represents the boundary conditions (the average of the electric fields at the top and

Inversion Charge Thickness (A)

the bottom of the charge layers) of the Schrodinger and the Poisson equations. 70 Tox=20A Tox=70A

60

Tox=50A Tox=90A

Solid - Nsub=2e16cm -3

50

Open - Nsub=2e17cm -3 +

40

-3

- Nsub=2e18cm

Model

30 20 10 -0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

(Vgsteff+4(Vth-Vfb-2 Φ f))/Tox (MV/cm)

Figure 4-3. For all T ox and Nsub , modeled inversion charge thickness agrees with numerical quantum simulations.

(iii) Body charge thichness in inversion In inversion region, the body charge thickness effect is accurately modeled by including the deviation of the surface potential

Φs

from 2 Φ B [32]

(

)

(4.4.5)

V  ⋅V + 2K1ox 2ΦB  Φδ = Φs − 2ΦB =νt ln gsteff,cv gsteff,cv + 1 2   moin ⋅ K ν 1ox t   where the model parameter moin (defaulting to 15) is introduced for better fit to different technologies. The inversion channel charge density is therefore derived as

qinv = −Coxeff ⋅ (Vgsteff,cv − Φδ )

4-18

(4.4.6)

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Extrinsic Capacitance

Figure 4-4 illustrates the universality of CTM model by compariing Cgg of a SiON/ Ta2O5 /TiN gate stack structure with an equivalent Tox of 1.8nm between data, numerical quantum simulation and modeling [32]. 10.0 Measured

7.5

Cgg (pF)

Q.M. simulation

CTM

18A equivalent SiO2 thickness

5.0

TiN 60A Ta2O5

2.5

8A SiON p-Si

0.0 -2

-1

0

1

2

3

Vgs (V)

Figure 4-4. Universality of CTM is demonstrated by modeling the C gg of 1.8nm equivalent T ox NMOSFET with SiON/Ta2O 5/TiN gate stack.

4.5 Extrinsic Capacitance 4.5.1 Fringing Capacitance The fringing capacitance consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance. Only the bias independent outer fringing capacitance is implemented. Experimentally, it is virtually impossible to separate this capacitance with the overlap capacitance. Nonetheless, the outer fringing capacitance can be theoretically calculated by (4.5.1) CF =

2ε ox  t poly  ln1 +  π Tox  

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4-19

Extrinsic Capacitance

where t poly is equal to ４ × １０ –７ m. CF is a model parameter.

4.5.2 Overlap Capacitance An accurate model for the overlap capacitance is essential. This is especially true for the drain side where the effect of the capacitance is amplified by the transistor gain. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small, we can model this region with a constant capacitance. However in LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of overlap capacitance. This LDD region can be in accumulation or depletion. We use a single equation for both regions by using such smoothing parameters as Vgs,overlap and Vgd,overlap for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, Cgs,overlap = Csg,overlap and Cgd,overlap = Cdg,overlap . (i) Source Overlap Charge (4.5.2) Qoverlap, s Wactive

4-20

  4V CKAPPA  = CGS 0 ⋅ Vgs + CGS 1Vgs − Vgs ,overlap − − 1 + 1 − gs ,overlap     2 CKAPPA     

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extrinsic Capacitance

(4.5.3)

1 2 Vgs, overlap = Vgs + δ 1 − (Vgs + δ 1) + 4δ1 , δ 1 = 0.02V  2 where CKAPPA is a model parameter. CKAPPA is related to the average doping of LDD region by CKAPPA =

The typical value for NLDD is

2ε si qN LDD 2 C ox １７

５ × １０

cm-3 .

(ii) Drain Overlap Charge (4.5.4) Q overlap, d Wactive

 4V gd ,overlap  CKAPPA  = CGD0 ⋅V gd + CGD1V gd − V gd, overlap − −1 + 1 −   2 CKAPPA    

(4.5.5) V gd , overlap =

1  V gd + δ 1 − 2

(V

+ δ 1 ) + 4δ 1  , δ 1 = 0. 02V  2

gd

(iii) Gate Overlap Charge (4.5.6) Qoverlap, g = − (Qoverlap, d + Qoverlap, s + (CGB 0 ⋅ Lactive ) ⋅V gb )

In the above expressions, if CGS0 and CGD0 (the overlap capacitances between the gate and the heavily doped source/drain regions, respectively) are not given, they are calculated according to the following CGS0 = (DLC*Cox ) - CGS1

(if DLC is given and DLC > 0)

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4-21

Extrinsic Capacitance

CGS0 = 0 (if the previously calculated CGS0 is less than 0) CGS0 = 0.6 Xj*Cox (otherwise) CGD0 = (DLC*Cox ) - CGD1 (if DLC is given and DLC > CGD1/Cox) CGD0 = 0 (if previously calculated CDG0 is less than 0) CGD0 = 0.6 Xj*Cox (otherwise). CGB0 in Eqn. (4.5.6) is a model parameter, which represents the gate-tobody overlap capacitance per unit channel length.

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4-22

CHAPTER 5: Non-Quasi Static Model

5.1 Background Information As MOSFET’s become more performance-driven, the need for accurate prediction of circuit performance near cut-off frequency or under very rapid transient operation becomes more essential. However, most SPICE MOSFET models are based on Quasi-Static (QS) assumptions. In other words, the finite charging time for the inversion layer is ignored. When these models are used with 40/60 charge partitioning, unrealistically drain current spikes frequently occur [33]. In addition, the inability of these models to accurately simulate channel charge re-distribution causes problems in fast switched-capacitor type circuits. Many Non-Quasi-Static (NQS) models have been published, but these models (1) assume, unrealistically, no velocity saturation and (2) are complex in their formulations with considerable simulation time.

5.2 The NQS Model The NQS model has been re-implemented in BSIM3v3.2 to improve the simulation performance and accuracy. This model is based on the channel charge relaxation time approach. A new charge partitioning scheme is used, which is physically consistent with quasi-static CV model.

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5-1

Model Formulation

5.3 Model Formulation The channel of a MOSFET is analogous to a bias dependent RC distributed transmission line (Figure 5-1a). In the Quasi-Static (QS) approach, the gate capacitor node is lumped with both the external source and drain nodes (Figure 51b). This ignores the finite time for the channel charge to build-up. One NonQuasi-Static (NQS) solution is to represent the channel as n transistors in series (Figure 5-1c). This model, although accurate, comes at the expense of simulation time. The NQS model in BSIM3v3.2.2 was based on the circuit of Figure 5-1d. This Elmore equivalent circuit models channel charge build-up accurately because it retains the lowest frequency pole of the original RC network (Figure 5-1a). The NQS model has two parameters as follows. The model flag, nqsMod, is now only an element (instance) parameter, no longer a model parameter. To turn on the NQS model, set nqsMod=1 in the instance statement. nqsMod defaults to zero with this model off.

Name

Function

Default

Unit

nqsMod

Instance flag for the NQS model

0

none

elm

Elmore constant

5

none

Table 5-1. NQS model and instance parameters.

5-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Model Formulation

Figure 5-1. Quasi-Static and Non-Quasi-Static models for SPICE analysis.

5.3.1 SPICE sub-circuit for NQS model Figure 5-2 gives the RC-subcircuit of NQS model for SPICE implementation. An additional node, Qdef(t) , is created to keep track of the amount of deficit/surplus channel charge necessary to reach the equilibrium based on the relaxation time approach. The bias-dependent resistance R (1/R=Gtau ) can be determined from the RC time constant ( τ ). The current source icheq(t) results from the equilibrium channel charge, Qcheq(t). The capacitor C is multiplied by a scaling factor Cfact (with a typical value of

–９

１ × １０

) to improve simulation accuracy. Qdef now becomes

Qdef (t) = Vdef × (1⋅ C fact)

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

(5.3.1)

5-3

Model Formulation

Q def

Vdef

icheq(t)

R

C=1 ×Cfact

Figure 5-2. NQS sub-circuit for SPICE implementation.

5.3.2 Relaxation time The relaxation time

τ

is modeled as two components:

strong inversion region,

τ

is determined by

τdrift

τ drift

and

τd i f f .

, which, in turn, is

determined by the Elmore resistance Relm ; in subthreshold region, dominates.

τ

In

τd i f f

is expressed by (5.3.2)

1 1 1 = + τ τdiff τdrift Relm in strong inversoin is calculated from the channel resistance as (5.3.3)

Relm =

5-4

Leff

2

elm⋅ µ0Qch

≈

Leff

2

elm⋅ µ0Qcheq

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Model Formulation

where elm is the Elmore constant of the RC channel network with a theorectical value of 5. The quasi-static (or equilibrium) channel charge Qcheq(t), equal to Qinv of capMod=0, 1, 2 and 3, is used to approximate the actual channel charge Qch(t) .

τ drift

is formulated as (5.3.4)

τ drift ≈ Relm ⋅ CoxWeff Leff ≈

τd i f f

CoxWeff Leff

3

elm⋅ µ0Qcheq

has the form of (5.3.5)

τ diff =

qLeff

2

16 ⋅ µ 0 kT

5.3.3 Terminal charging current and charge partitioning Considering both the transport and charging component, the total current related to the terminals D, G and S can be written as (5.3.6) iD,G ,S (t ) = I D ,G,S (DC) +

∂Qd , g, s (t ) ∂t

Based on the relaxation time approach, the terminal charge and corresponding charging current can be formulated by

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5-5

Model Formulation

(5.3.7) Qdef (t ) = Qcheq (t ) − Q ch (t )

and (5.3.8a) ∂Qdef (t ) ∂t

=

∂Qcheq (t ) Qdef (t ) − ∂t τ

(5.3.8b) ∂Qd , g ,s (t ) ∂t

= D , G, S xpart

Q def (t ) τ

where D,G,Sxpart are the NQS channel charge partitioning number for terminals D, G and S, respectively; Dxpart + Sxpart = 1 and Gxpart = -1. It is important for Dxpart and Sxpart to be consistent with the quasi-static charge partitioning number XPART and to be equal (Dxpart = Sxpart) at Vds =0 (which is not the case in the previous version), where the transistor operation mode changes (between forward and reverse modes). Based on this consideration, Dxpart is now formulated as (5.3.9) Dxpart =

Qd Q = d Qd + Qs Qcheq

which is now bias dependent. For example, the derivities of Dxpart can be easily obtained based on the quasi-static results: (5.3.10)

dDxpart dVi

=

1 (Sxpart ⋅Cdi − Dxpart ⋅Csi ) Qcheq

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

5-6

Model Formulation

where i represents the four terminals and Cdi and Csi are the intrinsic capacitances calculated from the quasi-static analysis. The corresponding values for Sxpart can be derived from the fact that Dxpart + Sxpart = 1. In the accumulation and depletion regions, Eq. (5.3.9) is simplified as If XPART < 0.5, Dxpart = 0.4; Else if XPART > 0.5, Dxpart = 0.0; Else Dxpart = 0.5;

5.3.4 Derivation of nodal conductances This section gives some examples of how to derive the nodal conductances related to NQS for transient analysis. By noting that τ = RC, Gtau can be derived as (5.3.11) Gtau = τ

C fact τ

is given by Eq. (5.3.2). Based on Eq. (5.3.8b), the self-conductance due

to NQS at the transistor node D can be derived as (5.3.12)

dDxpart dVd

⋅ (Gtau ⋅ Vdef ) + Dxpart ⋅ Vdef ⋅

dGtau dVd

The trans-conductance due to NQS on the node D relative to the node of Qdef can be derived as (5.3.13) Dxpart ⋅ Gtau

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5-7

Model Formulation

Other conductances can also be obtained in a similar way.

5.3.5 The AC Model Similarly, the small-signal AC charge-deficit NQS model can be turned on by setting acnqsMod = 1 and off by setting acnqsMod = 0. For small signals, by substituting (5.3.7) into (5.3.8b), it is easy to show that in the frequency domain, Qch(t) can be transformed into (5.3.14) ∆Qch (t ) =

∆Qcheq (t ) 1 + jωτ

where ω is the angular frequency. Based on (5.3.14), it can be shown that the transcapacitances Cgi, Csi , and Cdi (i stands for any of the G, D, S and B terminals of the device) and the channel transconductances Gm, Gds, and Gmbs all become complex quantities. For example, now Gm have the form of (5.3.15) Gm =

G m0  G ⋅ ωτ  + j  − m0 2 2  2 2 1+ω τ  1+ ω τ 

and (5.3.16)

Cdg =

 Cdg 0 ⋅ ωτ + j  − 2 2 1 +ω τ  1+ω τ Cdg0

2 2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

  

5-8

Model Formulation

Those quantities with sub “0”in the above two equations are known from OP (operating point) analysis.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

5-9

CHAPTER 6: Parameter Extraction

Parameter extraction is an important part of model development. Many different extraction methods have been developed [23, 24]. The appropriate methodology depends on the model and on the way the model is used. A combination of a local optimization and the group device extraction strategy is adopted for parameter extraction.

6.1 Optimization strategy There are two main, different optimization strategies: global optimization and local optimization. Global optimization relies on the explicit use of a computer to find one set of model parameters which will best fit the available experimental (measured) data. This methodology may give the minimum average error between measured and simulated (calculated) data points, but it also treats each parameter as a "fitting" parameter. Physical parameters extracted in such a manner might yield values that are not consistent with their physical intent. In local optimization, many parameters are extracted independently of one another. Parameters are extracted from device bias conditions which correspond to dominant physical mechanisms. Parameters which are extracted in this manner might not fit experimental data in all the bias conditions. Nonetheless, these extraction methodologies are developed specifically with respect to a given parameter’s physical meaning. If properly executed, it should, overall, predict

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6-1

Extraction Strategies

device performance quite well. Values extracted in this manner will now have some physical relevance.

6.2 Extraction Strategies Two different strategies are available for extracting parameters: the single device extraction strategy and group device extraction strategy. In single device extraction strategy, experimental data from a single device is used to extract a complete set of model parameters. This strategy will fit one device very well but will not fit other devices with different geometries. Furthermore, single device extraction strategy can not guarantee that the extracted parameters are physical. If only one set of channel length and width is used, parameters related to channel length and channel width dependencies can not be determined. BSIM3v3 uses group device extraction strategy. This requires measured data from devices with different geometries. All devices are measured under the same bias conditions. The resulting fit might not be absolutely perfect for any single device but will be better for the group of devices under consideration.

6.3 Extraction Procedure 6.3.1 Parameter Extraction Requirements One large size device and two sets of smaller-sized devices are needed to extract parameters, as shown in Figure 6-1.

6-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extraction Procedure

W

Large W and L Orthogonal Set of W and L

Wmin L Lmin Figure 6-1. Device geometries used for parameter extraction

The large-sized device (W ≥ 10µm, L ≥ 10µm) is used to extract parameters which are independent of short/narrow channel effects and parasitic resistance. Specifically, these are: mobility, the large-sized device threshold voltage VTideal, and the body effect coefficients K1 and K2 which depend on the vertical doping concentration distribution. The set of devices with a fixed large channel width but different channel lengths are used to extract parameters which are related to the short channel effects. Similarly, the set of devices with a fixed, long channel length but different channel widths are used to extract parameters which are related to narrow width

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

6-3

Extraction Procedure

effects. Regardless of device geometry, each device will have to be measured under four, distinct bias conditions. (1) Ids vs. Vgs @ Vds = 0.05V with different Vbs. (2) Ids vs. Vds @ Vbs = 0V with different Vgs. (3) Ids vs. Vgs @ Vds = Vdd with different Vbs . (Vdd is the maximum drain voltage). (4) Ids vs. Vds @ Vbs = Vbb with different Vgs . (|Vbb | is the maximum body bias).

6.3.2 Optimization The optimization process recommended is a combination of NewtonRaphson's iteration and linear-squares fit of either one, two, or three variables. This methodology was discussed by M. C. Jeng [18]. A flow chart of this optimization process is shown in Figure 6-2. The model equation is first arranged in a form suitable for Newton-Raphson's iteration as shown in Eq. (6.3.1): (6.3.1) fexp (P10, P20, P30 ) − fsim( P1(m) , P2( m) , P3(m) ) =

∂ fsim m ∂ fsim m ∂ fsim m ∆P + ∆P + ∆P ∂ P1 1 ∂ P2 2 ∂ P3 3

The variable fsim () is the objective function to be optimized. The variable fexp() stands for the experimental data. P10 , P20, and P30 represent the desired extracted parameter values. P1 (m), P2(m) and P3 (m) represent parameter values after the mth iteration.

6-4

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extraction Procedure

Initial Guess of Parameters P

i

Model Equations

Linear Least Squsre Measured Data

Fit Routine ∆P

P

(m+1) i

(m)

=P

i

∆P P

i

+ ∆P i

i (m)

< δ

no

i

yes STOP

Figure 6-2. Optimization flow.

To change Eq. (6.3.1) into a form that a linear least-squares fit routine can be used (i.e. in a form of y = a + bx 1 + cx2), both sides of the Eq. (6.3.1) are divided by ∂fsim / ∂P1. This gives the change in P1 , ∆P1(m) , for the next iteration such that:

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

6-5

Extraction Procedure

(6.3.2)

Pi

( m + 1)

=

Pi( m )

+ ∆ Pi( m )

where i=1, 2, 3 for this example. The (m+1) parameter values for P2 and P3 are obtained in an identical fashion. This process is repeated until the incremental parameter change in parameter values ∆Pi (m) are smaller than a pre-determined value. At this point, the parameters P1, P2 , and P3 have been extracted.

6.3.3 Extraction Routine Before any model parameters can be extracted, some process parameters have to be provided. They are listed below in Table 6-1: Input Parameters Names

Physical Meaning

Tox

Gate oxide thickness

Nch

Doping concentration in the channel

T

Temperature at which the data is taken

Ldrawn

Mask level channel length

W drawn

Mask level channel width

Xj

Junction depth

Table 6-1. Prerequisite input parameters prior to extraction process.

The parameters are extracted in the following procedure. These procedures are based on a physical understanding of the model and based on local

6-6

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extraction Procedure

optimization. (Note: Fitting Target Data refers to measurement data used for model extraction.) Step 1 Extracted Parameters & Fitting Target Data

Device & Experimental Data

Vth 0, K1, K2

Large Size Device (Large W & L). I ds vs. Vgs @ Vds = 0.05V at Different Vbs Extracted Experimental Data Vth(Vbs)

Fitting Target Exp. Data: Vth(Vbs)

Step 2 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

µ0 , Ua , Ub , U c

Large Size Device (Large W & L). I ds vs. Vgs @ Vds = 0.05V at Different Vbs

Fitting Target Exp. Data: Strong Inversion region I ds(Vgs, Vbs )

Step 3 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Lint, Rds(Rdsw , W, Vbs )

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ Vds = 0.05V at Different Vbs

Fitting Target Exp. Data: Strong Inversion region I ds(Vgs, Vbs )

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6-7

Extraction Procedure

Step 4 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Wint, Rds(Rdsw , W, Vbs )

One Set of Devices (Large and Fixed L & Different W). Ids vs. Vgs @ Vds = 0.05V at Different Vbs

Fitting Target Exp. Data: Strong Inversion region Ids(Vgs, Vbs)

Step 5 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Rdsw ,Prwb, Wr

Rds(Rdsw, W, Vbs)

Fitting Target Exp. Data: Rds(Rdsw , W, Vbs)

Step 6 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Dvt0 , Dvt 1, Dvt 2 , Nlx

One Set of Devices (Large and Fixed W & Different L). Vth(Vbs, L, W)

Fitting Target Exp. Data: Vth(Vbs, L, W)

6-8

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extraction Procedure

Step 7 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Dvt0w, Dvt1w , Dvt2w

One Set of Devices (Large and Fixed L & Different W). Vth(Vbs, L, W)

Fitting Target Exp. Data: Vth(Vbs, L, W)

Step 8 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

K3, K3b , W0

One Set of Devices (Large and Fixed L & Different W). Vth(Vbs, L, W)

Fitting Target Exp. Data: Vth(Vbs, L, W)

Step 9 Extracted Parameters & Fitting Target Data Voff , Nfactor, Cdsc, Cdscb Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)

Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ Vds = 0.05V at Different Vbs

Step 10 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

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6-9

Extraction Procedure

Cdscd Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ Vbs = Vbb at Different Vds

Step 11 Extracted Parameters & Fitting Target Data dWb Fitting Target Exp. Data: Strong Inversion region I ds(Vgs, Vbs )

Devices & Experimental Data One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ Vds = 0.05V at Different Vbs

Step 12 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

vsat, A0 , Ags One Set of Devices (Large and Fixed W & Fitting Target Exp. Data: Isat (Vgs, Vbs)/W Different L). I ds vs. Vds @ Vbs = 0V at Different Vgs A1 , A2 (PMOS Only) Fitting Target Exp. Data Vasat (Vgs)

Step 13 Extracted Parameters & Fitting Target Data

6-10

Devices & Experimental Data

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extraction Procedure

B0, B1 One Set of Devices (Large and Fixed L & Fitting Target Exp. Data: Isat (Vgs, Vbs)/W Different W). I ds vs. Vds @ Vbs = 0V at Different Vgs

Step 14 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

dWg One Set of Devices (Large and Fixed L & Fitting Target Exp. Data: Isat (Vgs, Vbs)/W Different W). I ds vs. Vds @ Vbs = 0V at Different Vgs

Step 15 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Pscbe1, Pscbe2

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vds @ Vbs = 0V at Different Vgs

Fitting Target Exp. Data: Rout(Vgs, Vds)

Step 16 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Pclm , θ(Drout , Pdiblc1 , Pdiblc2 , L), Pavg

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vds @ Vbs = 0V at Different Vgs

Fitting Target Exp. Data: Rout(Vgs, Vds )

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6-11

Extraction Procedure

Step 17 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Drout , Pdibl1c , Pdiblc2

One Set of Devices (Large and Fixed W & Different L). θ(Drout , Pdiblc 1, Pdiblc2, L)

Fitting Target Exp. Data: θ(Drout , Pdiblc1 , Pdiblc2, L)

Step 18 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Pdibl1cb

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ fixed Vgs at Different Vbs

Fitting Target Exp. Data: θ(Drout , Pdiblc1 , Pdiblc2, L, Vbs)

Step 19 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

θdibl(Eta0, Etab, Dsub, L)

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ Vds = Vdd at Different Vbs

Fitting Target Exp. Data: Subthreshold region Ids(Vgs, Vbs)

6-12

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Extraction Procedure

Step 20 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Eta0, Etab, Dsub

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vgs @ Vds = Vdd at Different Vbs

Fitting Target Exp. Data: θdibl(Eta0, Etab, L)

Step 21 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

Keta

One Set of Devices (Large and Fixed W & Different L). Fitting Target Exp. Data: Isat (Vgs, Vbs)/W I ds vs. Vds @ Vbs = Vbb at Different Vgs

Step 22 Extracted Parameters & Fitting Target Data

Devices & Experimental Data

α0, α1, β0

One Set of Devices (Large and Fixed W & Different L). I ds vs. Vds @ Vbs = Vbb at Different Vds

Fitting Target Exp. Data: Isub(Vgs , Vbs)/ W

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

6-13

Notes on Parameter Extraction

6.4 Notes on Parameter Extraction 6.4.1 Parameters with Special Notes Below is a list of model parameters which have special notes for parameter extraction. Symbols used in SPICE

Description

Default Value

Vth0

Threshold voltage for large W and L device @ Vbs=0V

K1

Unit

Notes

0.7 (NMOS) -0.7 (PMOS)

V

nI-1

First order body effect coefficient

0.5

V 1/2

nI-2

K2

Second order body effect coefficient

0

none

nI-2

Vbm

Maximum applied body bias

-3

V

nI-2

Nch

Channel doping concentration

1.7E17

1/cm 3

nI-3

gamma1

Body-effect coefficient near interface

calculated

V 1/2

nI-4

gamma2

Body-effect coefficient in the bulk

calculated

V 1/2

nI-5

Vbx

Vbs at which the depletion width equals xt

calculated

V

nI-6

Cgso

Non-LDD source-gate overlap capacitance per channel length

calculated

F/m

nC-1

Cgdo

Non-Ldd drain-gate overlap capacitance per channel length

calculated

F/m

nC-2

CF

Fringing field capacitance

calculated

F/m

nC-3

Table 6-2. Parameters with notes for extraction.

6-14

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Notes on Parameter Extraction

6.4.2 Explanation of Notes nI-1. If Vth0 is not specified, it is calculated by Vth0 = VFB + Φ s + K1 Φ s

where the model parameter VFB=-1.0. If Vth0 is specified, VFB defaults to

VFB = Vth0 − Φs − K1 Φs nI-2. If K1 and K2 are not given, they are calculated based on

K 1 = γ 2 − 2 K 2 Φ s − Vbm

K2 =

(γ 1 −γ 2 )(

(

Φs −Vbx − Φs

)

)

2 Φs Φs −Vbm − Φs +Vbm

where Φ s is calculated by N  Φ s = 2Vtm0 ln  ch   ni 

Vtm0 =

k BTnom q

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6-15

Notes on Parameter Extraction

1.5 Eg 0    Tnom   ni = 1. 45 × 10   exp  21. 5565981− 2Vtm 0   300. 15   10

Eg0

7.02 ×10−4 Tnom = 1.16 − Tnom + 1108

2

where Eg0 is the energy bandgap at temperature Tnom. nI-3. If Nch is not given and γ １ is given, Nch is calculated from γ 1 C ox 2 qε si 2

N ch =

2

If both γ １ and Nch are not given, Nch defaults to 1.7e23 m-3 and γ １ is calculated from Nch. nI-4. If γ １ is not given, it is calculated by

2 qε si Nch Cox

γ1 =

nI-5. If γ ２ is not given, it is calculated by

2qε si N sub Cox

γ2 =

nI-6. If Vbx is not given, it is calculated by 2

qN ch X t = Φ s − Vbx 2ε si

6-16

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Notes on Parameter Extraction

nC-1. If Cgso is not given, it is calculated by if (dlc is given and is greater 0), Cgso = dlc * Cox - Cgs1 if (Cgso < 0) Cgso = 0 else Cgso = 0.6 Xj * Cox nC-2. If Cgdo is not given, it is calculated by if (dlc is given and is greater than 0), Cgdo = dlc * Cox - Cgd1 if (Cgdo < 0) Cgdo = 0 else Cgdo = 0.6 Xj * Cox

nC-3. If CF is not given then it is calculated usin by

CF =

2 ε ox  4 × 10 −7  ln 1 +  π Tox  

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

6-17

CHAPTER 7: Benchmark Test Results

A series of benchmark tests [26] have been performed to check the model robustness, accuracy and performance. Although not all the benchmark test results are included in this chapter, the most important ones are demonstrated.

7.1 Benchmark Test Types Table 7-1 lists the various benchmark test conditions and associated figure number included in this section. Notice that for each plot, smooth transitions are apparent for current, transconductance, and source to drain resistance for all transition regions regardless of bias conditions.

Device Size

Bias Conditions

Notes

Figure Number

W/L=20/5

Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V

Log scale

7-1

W/L=20/5

Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V

Linear scale

7-2

W/L=20/0.5

Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V

Log scale

7-3

W/L=20/0.5

Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V

Linear scale

7-4

W/L=20/5

Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V

Log scale

7-5

W/L=20/5

Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V; W/ L=20/5

Linear scale

7-6

W/L=20/0.5

Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V

Log scale

7-7

W/L=20/0.5

Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V

Linear scale

7-8

W/L=20/5

Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V

Linear scale

7-9

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

7-1

Benchmark Test Results

Device Size

Bias Conditions

Notes

Figure Number

W/L=20/0.5

Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V

Linear scale

7-10

W/L=20/5

Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to 3.3V

Linear scale

7-11

W/L=20/0.5

Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to 3.3V

Linear scale

7-12

W/L=20/0.5

Ids vs. Vds @Vbs=0V; Vgs=0.5V, 0.55V, 0.6V

Linear scale

7-13

W/L=20/5

Ids vs. Vds @Vbs=0V; Vgs=1.15V to 3.3V

Linear scale

7-14

W/L=20/0.5

Ids vs. Vds @Vbs=0V; Vgs=1.084V to 3.3V

Linear scale

7-15

W/L=20/0.5

Rout vs. Vds @ Vbs=0V; Vgs=1.084V to 3.3V

Linear scale

7-16

Table 7-1. Benchmark test information.

7.2 Benchmark Test Results All of the figures listed in Table 7-1 are shown below. Unless otherwise indicated, symbols represent measurement data and lines represent the results of the model. All of these plots serve to demonstrate the robustness and continuous behavior of the unified model expression for not only Ids but Gm , Gm/Ids , and Rout as well.

7-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Benchmark Test Results

Figure 7-1. Continuity from subthreshold to strong inversion (log scale).

Figure 7-2. Continuity from subthreshold to strong inversion (linear scale).

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

7-3

Benchmark Test Results

Figure 7-3. Same as Figure 7-1 but for a short channel device.

Figure 7-4. Same as Figure 7-2 but for a short channel device.

7-4

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Benchmark Test Results

Figure 7-5. Subthreshold to strong inversion continuity as a function of Vb s.

Figure 7-6. Subthreshold to strong inversion continuity as a function of Vb s.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

7-5

Benchmark Test Results

Figure 7-7. Same as Figure 7-5 but for a short channel device.

Figure 7-8. Same as Figure 7-6 but for a short channel device.

7-6

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Benchmark Test Results

Figure 7-9. Gm/Ids continuity from subthreshold to strong inversion regions.

Figure 7-10. Same as Figure 7-9 but for a short channel device.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

7-7

Benchmark Test Results

Figure 7-11. Gm/I ds continuity as a function of Vb s.

Figure 7-12. Same as Figure 7-11 but for a short channel device.

7-8

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Benchmark Test Results

Figure 7-13. Comparison of Gd s with BSIM3v2.

Figure 7-14. Smooth transitions from linear to saturation regimes.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

7-9

Benchmark Test Results

Figure 7-15. Same as Figure 7-14 but for a short channel device.

Figure 7-16. Continuous and non-negative Rout behavior.

7-10

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

CHAPTER 8: Noise Modeling

8.1 Flicker Noise 8.1.1 Parameters There exist two models for flicker noise modeling. One is called SPICE2 flicker noise model; the other is BSIM3 flicker noise model [35-36]. The flicker noise model parameters are listed in Table 8-1. Symbols used in equation

Symbols used in SPICE

Description

Default

Unit

Noia

noia

Noise parameter A

(NMOS) 1e20 (PMOS) 9.9e18

none

Noib

noib

Noise parameter B

(NMOS) 5e4 (PMOS) 2.4e3

none

Noic

noic

Noise parameter C

(NMOS) -1.4e-12 (PMOS) 1.4e-12

none

Em

em

Saturation field

4.1e7

V/m

Af

af

Flick noise exponent

1

none

Ef

ef

Flicker noise frequency exponent

1

none

Kf

kf

Flicker noise coefficient

0

none

Length Reduction Parameter Offset

0.0

m

LINTNOI

lintnoi

Table 8-1. Flicker noise model parameters.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

8-1

Flicker Noise

8.1.2 Formulations 1.

For SPICE2 model (8.1)

Noisedensity=

K f I ds af 2

Cox Leff f ef

where f is the frequency. For BSIM3 model If Vgs > Vth + 0.1 2.

(8.2) kB Tq µeff I ds 2

S id,inv( f ) =

Co x e(Leff − 2⋅ LINTNOI) Abulk f 2

ef

  N + 2 × 1014  NOIC 2 2  NOIA⋅ log 0  + NOIB⋅ ( N 0 − N l ) + N0 − Nl 8  14   ⋅10  2  N l + 2 ×10 

(

kBTI ds ∆Lclm NOIA+ NOIB⋅ N l + NOIC⋅ N l ⋅ 2 Weff ⋅ ( Leff − 2 ⋅ LINTNOI) 2 f ef ⋅108 Nl + N* 2

+

(

) 

2

)

where Vtm is the thermal voltage, µeff is the effective mobiity at the given bias condition, and Leff and Weff are the effective channel length and width, respectively. The parameter N0 is the charge density at the source side given by (8.3) N0 =

Co x (Vgs − Vth ) q

The parameter Nl is the charge density at the drain end given by

8-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Flicker Noise

(8.4)

Nl =

Cox (Vgs − Vth − min(Vds ,Vdsat )) q

∆Lclm is the channel length reduction due to channel length modulation and given by (8.5)   Vds −Vdsat  + Em     (for Vds > Vdsat) Litl ⋅ log  Litl ∆Lclm =   Esat        0 (otherwise) Esat =

2× vsat µeff

where Litl =

3 X jTox

Otherwise (8.6)

Noisedensity=

Slimit × Swi Slimit + Swi

Where, Slimit is the flicker noise calculated at Vgs = Vth + 0.1 and Swi is given by

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

8-3

Channel Thermal Noise

(8.7)

Noia ⋅ Vtm ⋅ I ds Weff Leff ⋅ f ef ⋅ 4×1036 2

Swi =

8.2 Channel Thermal Noise There also exist two models for channel thermal noise modeling. One is called SPICE2 thermal noise model. The other is BSIM3v3 thermal noise model. Each of these can be toggled through the model flag, noiMod. 1.

For SPICE2 thermal noise model (8.8)

8kBT (Gm + Gmbs +Gds ) 3 where Gm, Gmbs and Gd s are the transconductances. 2.

For BSIM3v3 thermal noise model [37] (8.9)

4 k BT ∆ fµ eff

µ eff Q inv R ds (V ) + Leff

2

Q inv

Qinv is the inversion channel charge computed from the capacitance models (capMod = 0, 1, 2 or 3). 3.

New SPICE2 thermal noise model (8.10)

8  3 min( Vds,Vdsat )  kT ( g m + g ds + g mbs ) −  3 2Vdsat 2 

8-4

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Noise Model Flag

8.3 Noise Model Flag A model flag, noiMod, is used to select different combination of flicker and thermal noise models discussed above with possible optoins described in Table 82. noimod flag

Flicker noise model

Thermal noise model

1

SPICE2

SPICE2

2

BSIM3v3

BSIM3v3

3

BSIM3v3

SPICE2

4

SPICE2

BSIM3v3

5

SPICE2

SPICE2new

6

BSIM3v3

SPICE2new

Table 8-2. noiMod flag for differnet noise models.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

8-5

CHAPTER 9: MOS Diode Modeling

9.1 Diode IV Model The diode IV modeling now supports a resistance-free diode model and a currentlimiting feature by introducing a new model parameter ijth (defaulting to 0.1A). If ijth is explicitly specified to be zero, a resistance-free diode model will be triggered; otherwise two critical junction votages Vjsm for S/B diode and Vjdm for D/B diode will be computed from the value of ijth.

9.1.1 Modeling the S/B Diode If the S/B saturation current Isbs is larger than zero, the following equations is used to calculate the S/B diode current Ibs. Case 1 - ijth is equal to zero: A resistance-free diode. (9.1)

  V   Ibs = Isbs exp bs  − 1 + GminVbs   NVtm   where

NV tm = NJ ⋅ (KbT) ⁄ q

; NJ is a model parameter, known as the junction

emission coefficient. Case 2 - ijth is non-zero: Current limiting feature.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

9-1

Diode IV Model

If Vbs < Vjsm (9.2)

  V   Ibs = Isbs exp bs  −1 + GminVbs     NVtm   otherwise (9.3)

Ibs = ijth+

ijth+ Isbs (Vbs −Vjsm) + GminVbs NVtm

with Vjsm computed by  ijth  Vjsm = NVtm ln  + 1  I sbs 

The saturation current I sbs is given by (9.4)

I sbs = As J s + Ps J ssw where Js is the junction saturation current density, AS is the source junction area, Jssw is the sidewall junction saturation current density, Ps is the perimeter of the source junction. Js and Jssw are functions of temperature and can be written as (9.5)

 Eg 0 Eg  T    − + XTI ln  Tnom    Vtm0 Vtm  J s = J s0 exp  NJ      

9-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Diode IV Model

(9.6)  Eg0 Eg  T     − + XTI ln T  Vtm0 Vtm  nom   J ssw = J s0sw exp  NJ      

The energy band-gap Eg0 and Eg at the nominal and operating temperatures are expressed by (9.7a) and (9.7b), repectively: (9.7a) 7 .02 × 10 −4 Tnom Tnom + 1108

2

Eg 0 = 1.16 −

(9.7b) E g = 1.16 −

−4

7 .02 × 10 T T + 1108

2

In the above derivatoins, Js0 is the saturation current density at Tnom. If Js0 is not given,

J s０ = １ × １０

–４

A/m2. Js0sw is the sidewall saturation current density

at Tnom , with a default value of zero. If Isbs is not positive, I b s is calculated by (9.8) I bs = Gmin ⋅ Vbs

9.1.2 Modeling the D/B Diode If the D/B saturation current Isbd is larger than zero, the following equations is used to calculate the D/B diode current I bd. Case 1 - ijth is equal to zero: A resistance-free diode.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

9-3

Diode IV Model

(9.9)   V   Ibd = I sbd exp bd  −1 + GminVbd     NVtm  

Case 2 - ijth is non-zero: Current limiting feature. If Vbd < Vjdm (9.10)

  V   Ibd = I sbd  exp bd  − 1 + GminVbd     NVtm  

otherwise (9.11) Ibd = ijth +

ijth + I sbd (Vbd − Vjdm) + GminVbd NVtm

with Vjdm computed by  ijth  Vjdm = NVtm ln  + 1  I  sbd 

The saturation current I sbd is given by (9.12)

I sbd = Ad J s + Pd J ssw where Ad is the drain junction area and Pd is the perimeter of the drain junction. If Isbd is not positive, Ibd is calculated by (9.13) I bd = Gmin ⋅ Vbd

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

9-4

MOS Diode Capacitance Model

9.1.3 Model Parameter Lists The diode DC model parameters are listed in Table 9-1. Symbols used in equation

Symbols used in SPICE

Description

Default

Unit

Js0

js

Saturation current density

1e-4

A/m2

Js0sw

jssw

Side wall saturation current density

0

A/m

NJ

nj

Emission coefficient

1

none

XTI

xti

Junction current temperature exponent coefficient

3.0

none

ijth

ijth

Limiting current

0.1

A

Table 9-1. MOS diode model parameters.

9.2 MOS Diode Capacitance Model Source and drain junction capacitance can be divided into two components: the junction bottom area capacitance Cjb and the junction periphery capacitance Cjp. The formula for both the capacitances is similar, but with different model parameters. The equation of Cjb includes the parameters such as Cj, Mj, and Pb. The equation of Cjp includes the parameters such as Cjsw, Mjsw, Pbsw , Cjswg , Mjswg , and Pbswg.

9.2.1 S/B Junction Capacitance The S/B junction capacitance can be calculated by If Ps > Weff (9.14) Capbs = As C jbs + (Ps − Weff )C jbssw + Weff C jbsswg

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9-5

MOS Diode Capacitance Model

Otherwise (9.15) Capbs = As C jbs + Ps C jbsswg

where Cjbs is the unit bottom area capacitance of the S/B junction, Cjbssw is the periphery capacitance of the S/B junction along the field oxide side, and Cjbsswg is the periphery capacitance of the S/B junction along the gate oxide side. If Cj is larger than zero, Cjbs is calculated by if Vbs < 0 (9.16)  V  Cjbs = C j 1− bs   Pb 

−M j

otherwise (9.17)

 V  C jbs = C j 1 + M j bs  Pb  

If Cjsw is large than zero, Cjbssw is calculated by if Vb s < 0

9-6

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

MOS Diode Capacitance Model

(9.18)

 V  C jbssw = C jsw1− bs   Pbsw 

− M jsw

otherwise (9.19)  V  Cjbssw = C jsw1 + M jsw bs  Pbsw  

If Cjswg is larger than zero, Cjbsswg is calculated by if Vb s < 0 (9.20) − M jswg

 V  C jbsswg = C jswg1 − bs   Pbswg    otherwise

(9.21)

 V  Cjbsswg = C jswg 1 + M jswg bs   Pbswg  

9.2.2 D/B Junction Capacitance The D/B junction capacitance can be calculated by

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9-7

MOS Diode Capacitance Model

If Pd > W eff (9.22) Capbd = Ad C jbd + (Pd − Weff )C jbdsw + WeffC jbdswg

Otherwise (9.23) Capbd = Ad C jbd + PdC jbdswg

where Cjbd is the unit bottom area capacitance of the D/B junction, Cjbdsw is the periphery capacitance of the D/B junction along the field oxide side, and Cjbdswg is the periphery capacitance of the D/B junction along the gate oxide side. If Cj is larger than zero, Cjbd is calculated by if Vbd < 0 (9.24) C jbd

 V = C j 1 − bd Pb 

  

−M

j

otherwise (9.25)

 V  C jbd = C j 1+ M j bd  Pb  

If Cjsw is large than zero, Cjbdsw is calculated by if Vbd < 0

9-8

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

MOS Diode Capacitance Model

(9.26) − M jsw

 V  C jbdsw = C jsw1 − bd   Pbsw 

otherwise (9.27)

 V  C jbdsw = C jsw1 + M jsw bd  Pbsw  

If Cjswg is larger than zero, Cjbdswg is calculated by if Vbd < 0 (9.28) − M jswg

 V  Cjbdswg = Cjswg1 − bd   Pbswg    otherwise

(9.29)  V  C jbdswg = C jswg1 + M jswg bd   Pbswg  

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9-9

MOS Diode Capacitance Model

9.2.3 Temperature Dependence of Junction Capacitance The temperature dependence of the junction capacitance is modeled. Both zero-bias unit-area junction capacitance (Cj, Cjsw and Cjswg) and built-in potential of the junction (Pb, Pbsw and Pbswg) are temperature dependent and modeled in the following. For zero-bias junction capacitance: (9.30a) C j (T ) = C j (Tnom ) ⋅ (1 + tcj ⋅ ∆T )

(9.30b) C jsw(T ) = Cjsw (Tnom ) ⋅ (1 + tcjsw ⋅ ∆T )

(9.30c) C jswg (T ) = C jswg (Tnom) ⋅ (1 + tcjswg ⋅ ∆T )

For the built-in potential: (9.31a) Pb (T ) = Pb (Tnom ) − tpb ⋅ ∆T (9.31b)

Pbsw(T ) = Pbsw(Tnom ) − tpbsw⋅ ∆T (9.31c)

Pbswg(T ) = Pbswg(Tnom) − tpbswg⋅ ∆T In Eqs. (9.30) and (9.31), the temperature difference is defined as

9-10

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

MOS Diode Capacitance Model

(9.32)

∆T = T −Tnom The six new model parameters in the above equations are described in Table 9-2.

9.2.4 Junction Capacitance Parameters The following table give a full description of those model parameters used in the diode junction capacitance modeling.

Symbols used in equation

Symbols used in SPICE

Cj

Description

Default

Unit

cj

Bottom junction capacitance per unit area at zero bias

5e-4

F/m2

Mj

mj

Bottom junction capacitance grading coefficient

0.5

none

Pb

pb

Bottom junction built-in potential

1.0

V

Cjsw

cjsw

Source/drain sidewall junction capacitance per unit length at zero bias

5e-10

F/m

Mjsw

mjsw

Source/drain sidewall junction capacitance grading coefficient

0.33

none

Pbsw

pbsw

Source/drain side wall junction built-in potential

1.0

V

Cjswg

cjswg

Source/drain gate side wall junction capacitance per unit length at zero bias

Cjsw

F/m

Mjswg

mjswg

Source/drain gate side wall junction capacitance grading coefficient

Mjsw

none

Pbswg

pbswg

Source/drain gate side wall junction built-in potential

Pbsw

V

tpb

tpb

Temperature coefficient of Pb

0.0

V/K

tpbsw

tpbsw

Temperature coefficient of Pbsw

0.0

V/K

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

9-11

MOS Diode Capacitance Model

Symbols used in equation

Symbols used in SPICE

Description

Default

Unit

tpbswg

tpbswg

Temperature coefficient of Pbswg

0.0

V/K

tcj

tcj

Temperature coefficient of Cj

0.0

1/K

tcjsw

tcjsw

Temperature coefficient of Cjsw

0.0

1/K

tcjswg

tcjswg

Temperature coefficient of Cjswg

0.0

1/K

Table 9-2. MOS Junction Capacitance Model Parameters.

9-12

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

APPENDIX A: Parameter List

A.1 Model Control Parameters Symbols used in equation

Symbols used in SPICE

None None None None

level version binUnit paramChk

The model selector Model version selector Bining unit selector Parameter value check

mobMod capMod

mobMod capMod

nqsModa acnqsMod

nqsMod acnqsMod

noiMod

noiMod

Description

Default

Unit

8 3.3 1 False

none none none none

Mobility model selector Flag for capacitance models

1 3

none none

Flag for NQS model Flag for AC NQS model

0 0

none none

Both instance/model parameter Flag for noise models

1

none

Note

a. nqsMod is now an element (instance) parameter, no longer a model parameter.

A.2 DC Parameters

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

A-1

DC Parameters

Symbols used in equation

Symbols used in SPICE

Vth0

vth0

Description

Default

Unit

Note

Threshold voltage @Vbs=0 for Large L.

0.7 (NMOS)

V

nI-1

Calculated

V

nI-1

-0.7 (PMOS) VFB

vfb

Flat-band voltage

K1

k1

First order body effect coefficient

0.5

V1/2

nI-2

K2

k2

Second order body effect coefficient

0.0

none

nI-2

K3

k3

Narrow width coefficient

80.0

none

K3b

k3b

Body effect coefficient of k3

0.0

1/V

W0

w0

Narrow width parameter

2.5e-6

m

Nlx

nlx

Lateral non-uniform doping parameter

1.74e-7

m

Vbm

vbm

Maximum applied body bias in Vth calculation

-3.0

V

Dvt0

dvt0

first coefficient of short-channel effect on Vth

2.2

none

Dvt1

dvt1

Second coefficient of shortchannel effect on Vth

0.53

none

Dvt2

dvt2

Body-bias coefficient of shortchannel effect on Vth

-0.032

1/V

Dvt0w

dvt0w

First coefficient of narrow width effect on Vth for small channel length

0

1/m

Dvt1w

dvtw1

Second coefficient of narrow width effect on Vth for small channel length

5.3e6

1/m

A-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

DC Parameters

Symbols used in equation

Symbols used in SPICE

Dvt2w

Description

Default

Unit

dvt2w

Body-bias coefficient of narrow width effect for small channel length

-0.032

1/V

µ0

u0

Mobility at Temp = Tnom NMOSFET PMOSFET

670.0 250.0

cm2/Vs

Ua

ua

First-order mobility degradation coefficient

2.25E-9

m/V

Ub

ub

Second-order mobility degradation coefficient

5.87E-19

(m/V)2

Uc

uc

Body-effect of mobility degradation coefficient

mobMod =1, 2: -4.65e-11 mobMod =3: -0.046

m/V2

1/V

νsat

vsat

Saturation velocity at Temp = Tnom

8.0E4

m/sec

A0

a0

Bulk charge effect coefficient for channel length

1.0

none

Ags

ags

gate bias coefficient of Abulk

0.0

1/V

B0

b0

Bulk charge effect coefficient for channel width

0.0

m

B1

b1

Bulk charge effect width offset

0.0

m

Keta

keta

Body-bias coefficient of bulk charge effect

-0.047

1/V

A1

a1

First non-saturation effect parameter

0.0

1/V

A2

a2

Second non-saturation factor

1.0

none

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Note

A-3

DC Parameters

Symbols used in equation

Symbols used in SPICE

Rdsw

rdsw

Parasitic resistance per unit width

Prwb

prwb

Prwg

Default

Unit

0.0

Ω-µmWr

Body effect coefficient of Rdsw

0

V-1/2

prwg

Gate bias effect coefficient of Rdsw

0

1/V

Wr

wr

Width Offset from Weff for Rds calculation

1.0

none

Wint

wint

Width offset fitting parameter from I-V without bias

0.0

m

Lint

lint

Length offset fitting parameter from I-V without bias

0.0

m

dWg

dwg

Coefficient of Weff’s gate dependence

0.0

m/V

dWb

dwb

Coefficient of Weff’s substrate body bias dependence

0.0

m/V1/2

Voff

voff

Offset voltage in the subthreshold region at large W and L

-0.08

V

Nfactor

nfactor

Subthreshold swing factor

1.0

none

Eta0

eta0

DIBL coefficient in subthreshold region

0.08

none

Etab

etab

Body-bias coefficient for the subthreshold DIBL effect

-0.07

1/V

Dsub

dsub

DIBL coefficient exponent in subthreshold region

drout

none

Cit

cit

Interface trap capacitance

0.0

F/m2

Cdsc

cdsc

Drain/Source to channel coupling capacitance

2.4E-4

F/m2

A-4

Description

Note

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

DC Parameters

Symbols used in equation

Symbols used in SPICE

Cdscb

cdscb

Cdscd

Description

Default

Unit

Body-bias sensitivity of Cdsc

0.0

F/Vm2

cdscd

Drain-bias sensitivity of Cdsc

0.0

F/Vm2

Pclm

pclm

Channel length modulation parameter

1.3

none

Pdiblc1

pdiblc1

First output resistance DIBL effect correction parameter

0.39

none

Pdiblc2

pdiblc2

Second output resistance DIBL effect correction parameter

0.0086

none

Pdiblcb

pdiblcb

Body effect coefficient of DIBL correction parameters

0

1/V

Drout

drout

L dependence coefficient of the DIBL correction parameter in Rout

0.56

none

Pscbe1

pscbe1

First substrate current bodyeffect parameter

4.24E8

V/m

Pscbe2

pscbe2

Second substrate current bodyeffect parameter

1.0E-5

m/V

Pvag

pvag

Gate dependence of Early voltage

0.0

none

δ

delta

Effective Vds parameter

0.01

V

Ngate

ngate

poly gate doping concentration

0

cm-3

α0

alpha0

The first parameter of impact ionization current

0

m/V

α1

alpha1

Isub parameter for length scaling

0.0

1/V

β0

beta0

The second parameter of impact ionization current

30

V

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Note

nI-3

A-5

C-V Model Parameters

Symbols used in equation

Symbols used in SPICE

Rsh

Description

Default

Unit

Note

rsh

Source drain sheet resistance in ohm per square

0.0

Ω/ square

Js0sw

jssw

Side wall saturation current density

0.0

A/m

Js0

js

Source drain junction saturation current per unit area

1.0E-4

A/m2

ijth

ijth

Diode limiting current

0.1

A

nI-3

Default 0.0

Unit none

Note

A.3 C-V Model Parameters Symbols used in equation

Symbols used in SPICE

Xpart

xpart

Charge partitioning flag

CGS0

cgso

Non LDD region source-gate overlap capacitance per channel length

calculated

F/m

nC-1

CGD0

cgdo

Non LDD region drain-gate overlap capacitance per channel length

calculated

F/m

nC-2

CGB0

cgbo

0.0

F/m

Cj

cj

Gate bulk overlap capacitance per unit channel length Bottom junction capacitance per unit area at zero bias

5.0e-4

F/m2

A-6

Description

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

C-V Model Parameters

Symbols used in equation

Symbols used in SPICE

Mj

mj

Bottom junction capacitance grating coefficient

0.5

Mjsw

mjsw

Source/Drain side wall junction capacitance grading coefficient

0.33

none

Cjsw

cjsw

5.E-10

F/m

Cjswg

cjswg

Cjsw

F/m

Mjswg

mjswg

Mjsw

none

Pbsw

pbsw

Source/Drain side wall junction capacitance per unit area Source/drain gate side wall junction capacitance grading coefficient Source/drain gate side wall junction capacitance grading coefficient Source/drain side wall junction built-in potential

1.0

V

Pb Pbswg

pb pbswg

Bottom built-in potential Source/Drain gate side wall junction built-in potential

1.0 Pbsw

V V

CGS1

cgs1

Light doped source-gate region overlap capacitance

0.0

F/m

CGD1

cgd1

Light doped drain-gate region overlap capacitance

0.0

F/m

CKAPPA

ckappa

Coefficient for lightly doped region overlap capacitance Fringing field capacitance

0.6

V

Cf

cf

fringing field capacitance

calculated

F/m

CLC

clc

Constant term for the short channel model

0.1E-6

m

CLE

cle

Exponential term for the short channel model

0.6

none

Description

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Default

Unit

Note

nC-3

A-7

NQS Parameters

Symbols used in equation

Symbols used in SPICE

DLC

dlc

DWC

Description

Default

Unit

Note

Length offset fitting parameter from C-V

lint

m

dwc

Width offset fitting parameter from C-V

wint

m

Vfbcv

vfbcv

Flat-band voltage parameter (for capMod=0 only)

-1

V

noff

noff

CV parameter in Vgsteff,CV for weak to strong inversion

1.0

none

nC-4

voffcv

voffcv

CV parameter in Vgsteff,CV for week to strong inversion

0.0

V

nC-4

acde

acde

Exponential coefficient for charge thickness in capMod=3 for accumulation and depletion regions

1.0

m/V

nC-4

moin

moin

Coefficient for the gate-bias dependent surface potential

15.0

none

nC-4

Description

Default

Unit

Note

Elmore constant of the channel

5

none

A.4 NQS Parameters Symbols used in equation

Symbols used in SPICE

Elm

elm

A-8

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

dW and dL Parameters

A.5 dW and dL Parameters

Symbols used in equation

Symbols used in SPICE

Wl

wl

Wln

Description

Default

Unit

Coefficient of length dependence for width offset

0.0

mWln

wln

Power of length dependence of width offset

1.0

none

Ww

ww

Coefficient of width dependence for width offset

0.0

mWwn

Wwn

wwn

Power of width dependence of width offset

1.0

none

Wwl

wwl

Coefficient of length and width cross term for width offset

0.0

mWwn+Wln

Ll

ll

Coefficient of length dependence for length offset

0.0

mLln

Lln

lln

Power of length dependence for length offset

1.0

none

Lw

lw

Coefficient of width dependence for length offset

0.0

mLwn

Lwn

lwn

Power of width dependence for length offset

1.0

none

Lwl

lwl

Coefficient of length and width cross term for length offset

0.0

mLwn+Lln

Llc

Llc

Coefficient of length dependence for CV channel length offset

Ll

mLln

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Note

A-9

Temperature Parameters

Symbols used in equation

Symbols used in SPICE

Lwc

Lwc

Lwlc

Description

Default

Unit

Coefficient of width dependence for CV channel length offset

Lw

mLwn

Lwlc

Coefficient of length and widthdependence for CV channel length offset

Lwl

mLwn+Lln

Wlc

Wlc

Coefficient of length dependence for CV channel width offset

Wl

mWln

Wwc

Wwc

Coefficient of widthdependence for CV channel width offset

Ww

mWwn

Wwlc

Wwlc

Coefficient of length and widthdependence for CV channel width offset

Wwl

mWln+Wwn

Note

A.6 Temperature Parameters

Symbols used in equation

Symbols used in SPICE

Tnom µte

A-10

Description

Default

Unit

tnom

Temperature at which parameters are extracted

27

oC

ute

Mobility temperature exponent

-1.5

none

Note

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Temperature Parameters

Symbols used in equation

Symbols used in SPICE

Kt1

kt1

Temperature coefficient for threshold voltage

Kt1l

kt1l

Kt2

Description

Default

Unit

-0.11

V

Channel length dependence of the temperature coefficient for threshold voltage

0.0

Vm

kt2

Body-bias coefficient of Vth temperature effect

0.022

none

Ua1

ua1

Temperature coefficient for Ua

4.31E-9

m/V

Ub1

ub1

Temperature coefficient for Ub

-7.61E18

(m/V)2

Uc1

uc1

Temperature coefficient for Uc

mobMod=1, 2:

m/V2

Note

-5.6E-11 mobMod=3:

1/V

-0.056 At

at

Temperature coefficient for saturation velocity

3.3E4

m/sec

Prt

prt

Temperature coefficient for Rdsw

0.0

Ω-µm

At

at

Temperature coefficient for saturation velocity

3.3E4

m/sec

nj

nj

Emission coefficient of junction

1.0

none

XTI

xti

Junction current temperature exponent coefficient

3.0

none

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

A-11

Flicker Noise Model Parameters

Symbols used in equation

Symbols used in SPICE

tpb

Description

Default

Unit

tpb

Temperature coefficient of Pb

0.0

V/K

tpbsw

tpbsw

Temperature coefficient of Pbsw

0.0

V/K

tpbswg

tpbswg

Temperature coefficient of Pbswg

0.0

V/K

tcj

tcj

Temperature coefficient of Cj

0.0

1/K

tcjsw

tcjsw

Temperature coefficient of Cjsw

0.0

1/K

tcjswg

tcjswg

Temperature coefficient of Cjswg

0.0

1/K

Note

A.7 Flicker Noise Model Parameters Symbols used in equation

Symbols used in SPICE

Noia

noia

Description Noise parameter A

Default

Unit

(NMOS) 1e20

none

Note

(PMOS) 9.9e18 Noib

noib

Noise parameter B

(NMOS) 5e4

none

(PMOS) 2.4e3 Noic

noic

Noise parameter C

(NMOS) -1.4e12

none

(PMOS) 1.4e-12 Em

A-12

em

Saturation field

4.1e7

V/m

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Process Parameters

Symbols used in equation

Symbols used in SPICE

Af

af

Ef

Description

Default

Unit

Flicker noise exponent

1

none

ef

Flicker noise frequency exponent

1

none

Kf

kf

Flicker noise coefficient

0

none

LINTNOI

lintnoi

Length Reduction Parameter Offset

0.0

m

Note

A.8 Process Parameters

Symbols used in equation

Symbols used in SPICE

Tox

tox

Gate oxide thickness

Toxm

toxm

Tox at which parameters are extracted

Xj

xj

γ1

Description

Default

Unit

1.5e-8

m

Tox

m

Junction Depth

1.5e-7

m

gamma1

Body-effect coefficient near the surface

calculated

V1/2

nI-5

γ2

gamma2

Body-effect coefficient in the bulk

calculated

V1/2

nI-6

Nch

nch

Channel doping concentration

1.7e17

1/cm3

nI-4

Nsub

nsub

Substrate doping concentration

6e16

1/cm3

Vbx

vbx

Vbs at which the depletion region width equals xt

calculated

V

Xt

xt

Doping depth

1.55e-7

m

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Note

nI-3

nI-7

A-13

Geometry Range Parameters

A.9 Geometry Range Parameters

Symbols used in equation

Symbols used in SPICE

Lmin

lmin

Lmax

Description

Default

Unit

Minimum channel length

0.0

m

lmax

Maximum channel length

1.0

m

Wmin

wmin

Minimum channel width

0.0

m

Wmax

wmax

Maximum channel width

1.0

m

binUnit

binunit

Bin unit scale selector

1.0

none

Note

A.10Model Parameter Notes nI-1. If Vth0 is not specified, it is calculated by Vth 0 = VFB + Φ s + K1 Φ s

where the model parameter VFB=-1.0. If Vth0 is specified, VFB defaults to

VFB = Vth0 − Φs − K1 Φs nI-2. If K1 and K2 are not given, they are calculated based on

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

A-14

Model Parameter Notes

K1 = γ 2 − 2 K 2 Φ s − Vbm

(γ1 − γ 2 )(

K2 =

where

Φ s is

(

Φs −Vbx − Φs

)

)

2 Φs Φs −Vbm − Φs + Vbm

calculated by Φ s = 2Vtm0 ln

Vtm 0 =

ni = 1.45 × 10

10

Eg 0

Tnom 300 .15

Nch ni

k BTnom q

1 .5

exp 21 .5565981 −

7.02 × 10−4 Tnom = 1.16 − Tnom + 1108

Eg 0 2Vtm 0

2

where Eg0 is the energy bandgap at temperature Tnom. nI-3. If pscbe2 <= 0.0, a warning message will be given. If ijth < 0.0, a fatal error message will occur.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

A-15

Model Parameter Notes

If Toxm < = 0.0, a fatal error message will occur.

nI-4. If Nch is not given and γ is given, Nch is calculated from N ch =

γ 1 2 C ox 2 2 q ε si

If both γ and Nch are not given, Nch defaults to 1.7e23 m-3 and γ is calculated from Nch. nI-5. If γ is not given, it is calculated by

2qε si N ch

γ1 =

Cox

nI-6. If γ is not given, it is calculated by

2qε si N sub Cox

γ2 =

nI-7. If Vbx is not given, it is calculated by 2

qN ch X t = Φ s − Vbx 2ε si nC-1. If Cgso is not given, it is calculated by

if (dlc is given and is greater 0), Cgso = dlc * Cox - Cgs1 if (Cgso < 0) Cgso = 0 else Cgso = 0.6 Xj * Cox

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

A-16

Model Parameter Notes nC-2. If Cgdo is not given, it is calculated by

if (dlc is given and is greater than 0), Cgdo = dlc * Cox - Cgd1 if (Cgdo < 0) Cgdo = 0 else Cgdo = 0.6 Xj * Cox

nC-3. If CF is not given then it is calculated usin by CF =

2ε ox 4 × 10 −7 ln 1 + π Tox

nC-4.

If (acde < 0.4) or (acde > 1.6), a warning message will be given. If (moin < 5.0) or (moin > 25.0), a warning message will be given. If (noff < 0.1) or (noff > 4.0), a warning message will be given. If (voffcv < -0.5) or (voffcv > 0.5), a warning message will be given.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

A-17

APPENDIX B: Equation List

B.1 I-V Model B.1.1 Threshold Voltage

Vth = Vth 0 ox + K1ox ⋅ Φ s − Vbseff − K 2 oxVbseff   Nlx Tox + K1ox  1 + − 1 Φ s + (K 3 + K 3 bVbseff ) Φs   Leff Weff ' +W0    W 'L  W 'L    − DVT 0 w  exp  − DVT1 w eff eff  + 2 exp  − DVT1 w eff eff  (Vbi − Φ s ) 2ltw  ltw        Leff   L   + 2 exp − DVT 1 eff   (Vbi − Φ s ) − DVT 0  exp  − DVT 1 2lt  lt        L   L  −  exp  − Dsub eff  + 2 exp  − Dsub eff  (Etao + EtabVbseff )Vds 2lto  lto     

Vth0ox = Vth0 − K1 ⋅ Φ s

K 1ox = K 1 ⋅

Tox Toxm

K2ox = K 2 ⋅

Tox Toxm

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-1

I-V Model

lt =

ε siX dep / C ox (1 + D VT 2V bseff )

l tw =

ε siX dep / C ox (1 + D VT 2 w V bseff )

lto = ε siX dep 0 / C ox Xdep =

2ε si( Φs − Vbseff ) qN ch

Xdep 0 =

2 εsi Φs qNch

(δ1=0.001)

Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ1) 2 − 4δ1Vbc ] 2  K  Vbc = 0. 9 Φ s − 1 2  4K 2  

Vbi = vt ln(

NchNDS ) 2 ni

B.1.2 Effective (V gs-V th)

Vgsteff

B-2

 Vgs − Vth  2 n v t ln 1 + exp( ) 2 n vt   = 2Φs Vgs − Vth − 2 Voff 1 + 2 n COX exp( − ) qεsiNch 2 n vt

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

I-V Model

Leff Leff (Cdsc + CdscdVds + Cdscb Vbseff )exp(−DVT1 ) + 2 exp(−DVT1 )  Cd 2lt lt  Cit n = 1 + Nfactor + + Cox Cox Cox

Cd =

εsi Xdep

B.1.3 Mobility For mobMod=1

µeff =

µo Vgsteff + 2Vth Vgsteff + 2Vth 2 1 + (Ua + Uc Vbseff )( ) + U b( ) TOX TOX

For mobMod=2

µeff =

µo Vgsteff Vgsteff 2 1 + (U a + UcVbseff )( ) + Ub ( ) TOX TOX

For mobMod=3

µeff =

µo Vgsteff + 2 Vth Vgsteff + 2Vth 2 1 + [Ua ( ) + U b( ) ](1 + UcVbseff ) TOX TOX

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-3

I-V Model

B.1.4 Drain Saturation Voltage For Rds > 0 or λ ≠ 1:

Vdsat

− b − b 2 − 4 ac = 2a

a = A bulk 2Weff νsatCoxR DS + (

1 − 1) A bulk λ

2   b = −  (V gsteff + 2 v t )( − 1) + A bulkE satL eff + 3 Abulk (Vgsteff + 2 vt )WeffνsatC oxR D S   λ

c = (V gsteff + 2 v t ) E satL eff + 2 (V gsteff + 2 vt ) 2 WeffνsatCoxR D S λ = A1Vgsteff + A2 For Rds = 0 and λ = 1:

Vdsat =

Esat L eff ( Vgsteff + 2 vt ) A bulk E sat L eff + (Vgsteff + 2 vt )

2         A0Leff Leff K1ox  B0    1   Abulk = 1+ + ⋅    1− AgsVgsteff  L + 2 X J Xdep   Weff '+B1   1+ KetaV bseff  2 Φs −Vbseff  Leff + 2 XJ Xdep   eff      

B-4

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

I-V Model

E sat =

2νsat µeff

B.1.5 Effective V ds

(

1 Vdseff = Vdsat − Vdsat −Vds − δ + (Vdsat −Vds − δ )2 + 4δVdsat 2

)

B.1.6 Drain Current Expression

Idso( Vdseff )  1 + Vds − V dseff  1 + V ds − V dseff  RdsIdso( Vdseff )   VA V ASCBE  1+ Vdseff

Ids =

Vdseff )Vdseff 2 (Vgsteff + 2 v t ) / ( EsatLeff )]

WeffµeffCoxVgsteff (1 − Abulk Idso =

Leff [1 + Vdseff

VA = VAsat + (1 +

VACLM =

PvagVgsteff 1 1 )( + ) −1 E satL eff VACLM VADIBLC

A bulkE satL eff + Vgsteff (Vds − Vdseff ) P CLMA bulkE sat litl

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-5

I-V Model

VADIBLC =

(Vgsteff + 2 vt) AbulkVdsat   1 −   θ rout (1 + PDIBLCB Vbseff ) AbulkVdsat + Vgsteff + 2vt 

Leff Leff   θrout = PDIBLC 1 exp( − DROUT ) + 2 exp( − DROUT ) + P DIBLC 2 2lt 0 l t 0  

1 VASCBE

=

Pscbe 2  − Pscbe 1 litl  exp   Vds − Vdseff  Leff

EsatLeff + Vdsat + 2 RDSνsatCox WeffVgsteff [1 − VAsat =

AbulkVdsat ] 2(Vgsteff + 2vt )

2 / λ − 1 + RDSνsatCoxWeffAbulk

litl =

ε si Tox X j ε ox

B.1.7 Substrate Current

I sub =

B-6

α 0 + α 1 ⋅ L eff L eff

(V

ds

 β0 − V dseff )exp  −  Vds − Vdseff 

 I ds 0    1 + R ds I ds0 Vdseff

 V ds − V dseff 1 + VA 

  

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

I-V Model

B.1.8 Polysilicon Depletion Effect

2 qN Ngate poly X poly 1 V poly = X poly E poly = 2 2 ε si

ε ox Eox = ε si E poly = 2qε si Ngate polyV poly

Vgs − VFB − Φ s = V poly + Vox

a (V gs − V FB − Φ s − V poly ) − V poly = 0 2

a=

Vgs_ eff

ε ox

2

2qε si N gateTox

2

2 2 qε si NgateTox  2ε ox (Vgs −VFB − Φs )  = VFB + Φs + 1+ −1   ε ox2 qε si NgateTox2  

B.1.9 Effective Channel Length and Width L eff = L drawn − 2 dL

Weff = Wdrawn − 2dW

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-7

I-V Model

Weff ' = Wdrawn − 2 dW '

(

dW = dW '+dWgVgsteff + dWb Φ s −Vbseff − Φ s dW ' = Wint +

)

Wl Ww W + Wwn + W ln wl Wwn W ln L W L W

dL = Lint +

Ll Lw L + Lwn + L ln wl Lwn L ln L W L W

B.1.10Source/Drain Resistance

Rds =

(

(

Rdsw 1 + PrwgVgsteff + Prwb Φ s − Vbseff − Φ s

(10 W ')

))

Wr

6

eff

B.1.11Temperature Effects

Vth (T ) = Vth(Tnorm) + ( KT1 + Kt1l / Leff + KT 2Vbseff)(T / Tnorm − 1)

µo(T ) = µo(Tnorm)(

T µte ) Tnorm

vsat(T ) = vsat (Tnorm) − AT(T / Tnorm −1)

B-8

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Capacitance Model Equations

R dsw( T ) = Rdsw( Tnorm) + Pr t (

T Tnorm

− 1)

U a( T ) = U a( Tnorm ) + U a1( T / Tnorm − 1)

U b( T ) = Ub ( Tnorm) + U b1(T / Tnorm − 1)

U c( T ) = Uc ( Tnorm) + Uc1(T / Tnorm − 1)

B.2 Capacitance Model Equations B.2.1 Dimension Dependence Lactive = Ldrawn − 2δLeff Wactive = Wdrawn − 2δWeff

δLeff = DLC +

δWeff = DWC +

Llc Lwc Lwlc + Lwn + L ln Lwn L ln L W L W

Wlc Wwc Wwlc + Wwn + W ln Wwn W ln L W L W

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-9

Capacitance Model Equations

B.2.2 Overlap Capacitance B.2.2.1 Source Overlap Capacitance

(1) for capMod = 0

Qoverlap,s = CGS0Vgs Wactive (2) for capMod = 1 If Vgs < 0 Q overlap ,s W active

= CGS 0 ⋅ V gs +

4V gs CKAPPA ⋅ CGS 1  −1 + 1 −  2 CKAPPA 

   

Else

Qoverlap ,s Wactive

= (CGS 0 + CKAPPA⋅ CGS1) ⋅ V gs

(3) for capMod = 2

Qoverlap,s Wactive

 4Vgs,overlap CKAPPA  = CGS0 ⋅Vgs + CGS1V gs −V gs,overlap− −1 + 1 −    2 CKAPPA   

1 2 Vgs, overlap = Vgs + δ1 − (Vgs + δ1 ) + 4δ1 , δ1 = 0.02  2

B-10

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Capacitance Model Equations

B.2.2.2 Drain Overlap Capacitance

(1) for capMod = 0

Qoverlap , d Wactive

= CGD0Vgd

(2) for capMod = 1 If Vgd < 0

Qoverlap, d Wactive

= CGD0 ⋅ V gs +

4Vgd  CKAPPA⋅ CGD1   −1 + 1 −   2 CKAPPA  

Else

Qoverlap ,d W active

= (CGD 0 + CKAPPA ⋅ CGD1) ⋅ V gd

(3) for capMod = 2 Qoverlap,d Wactive

 4Vgd, overlap CKAPPA = CGD0⋅Vgd + CGD1Vgd − Vgd,overlap− −1+ 1−   2 CKAPPA   

1 2 V gd,overlap = V gd + δ 1 − (V gd + δ 1 ) + 4δ 1 , δ 1 = 0.02  2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-11

Capacitance Model Equations

B.2.2.3 Gate Overlap Charge

(

Q overlap,g = − Qoverlap,s + Qoverlap, d

)

B.2.3 Instrinsic Charges (1) capMod = 0 a. Accumulation region (Vg s < Vfbcv + Vbs) Qg = WactiveLactiveCox (Vgs − Vbs − V fbcv )

Qsub = −Qg

Qinv = 0 b. Subthreshold region (Vgs < Vth )

K Qsub0 = −WactiveLactiveCox ⋅ 1ox 2

2

   −1+ 1 + 4(Vgs −Vfbcv − Vbs)    K1ox2  

Qg = −Qb

B-12

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Capacitance Model Equations

Qinv = 0 c. Strong inversion (Vgs > Vth ) Vdsat,cv =

Vgs − Vth Abulk '

  CLC  CLE Abulk ' = Abulk 0  1 +     Leff  

 K1ox Abulk0 = 1 + 2 Φ s − Vbseff 

   

 A0 Leff B0   1  + ⋅ L +2 X X Weff '+B1   1 + KetaVbseff J dep  eff 

Vth = V fbcv + Φ s + K1ox Φ s − Vbseff (i) 50/50 Charge partition If Vds < Vdsat

    2 Vds Abulk'Vds   Qg = CoxWactiveLactive Vgs − Vfbcv − Φs − +  Abulk'Vds   2  12Vgs −Vth −   2   

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-13

Capacitance Model Equations

Qinv = −Wactive Lactive Cox [ Vgs − Vth −

Abulk ' Vds Abulk ' 2 Vds 2 + ] Abulk ' 2 12( Vgs − Vth − Vds ) 2

( 1 − Abulk ' ) Vds ( 1 − Abulk ' ) Abulk ' Vds 2 Qb = Wactive Lactive Cox [ Vfb − Vth + Φs + − ] Abulk ' 2 12(Vgs − Vth − Vds ) 2

A ' Vds Qs = Qd = 05Q . inv = −Wactive LactiveCox[Vgs − Vth − bulk + 2

Abulk' 2 Vds 2 ] Abulk ' 12(Vgs − Vth − Vds) 2

otherwise

Qg = Wactive Lactive Cox (Vgs − Vfb − Φs −

Vdsat ) 3

1 Qs = Qd = − Wactive Lactive Cox (Vgs − Vth ) 3

Qb = −Wactive L active Cox (Vfb + Φs − Vth +

( 1 − Abulk ' )Vdsat ) 3

(ii) 40/60 channel-charge Partition

B-14

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Capacitance Model Equations

if (Vds < Vdsat)

Qg = CoxWactive Lactive [ Vgs − Vfb − Φs −

Qinv = −Wactive Lactive Cox [ Vgs − Vth −

Qb = Wactive Lactive Cox [ Vfb − Vth + Φs +

Vds + 2

Abulk ' Vds 2 ] Abulk ' Vds 12(Vgs − Vth − ) 2

Abulk ' Vds Abulk ' 2 Vds 2 + ] Abulk ' 2 12( Vgs − Vth − Vds ) 2

(1 − Abulk ' )Vds ( 1 − Abulk ' ) Abulk ' Vds 2 − ] Abulk ' 2 12(Vgs − Vth − Vds) 2

Qd = −WactiveLactive Cox  (Vgs − Vth)2 Abulk ' Vds(Vgs − Vth ) ( Abulk ' Vds) 2  A ' V ds [ − +  Vgs − Vth Abulk ' bulk  6 8 40 − Vds +   A ' 2 2   (Vgs − Vth − bulk Vds )2   2

Q s = −( Qg + Q b + Qd )

otherwise

Qg = Wactive Lactive Cox (Vgs − Vfb − Φs −

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Vdsat ) 3

B-15

Capacitance Model Equations

Qd = −

4 W L Cox (Vgs − Vth ) 15 active active

Qs = − ( Qg + Qb + Qd )

Q b = −Wactive Lactive Cox ( Vfb + Φ s − Vth +

( 1 − Abulk ' )Vdsat ) 3

(iii) 0/100 Channel-charge Partition if Vd s < Vdsat

Qg = CoxWactive Lactive [ Vgs − Vfb − Φs −

Qinv = −Wactive Lactive Cox [ Vgs − Vth −

Vds + 2

Abulk ' Vds 2 ] Abulk ' Vds 12(Vgs − Vth − ) 2

Abulk ' Vds Abulk ' 2 Vds 2 + ] Abulk ' 2 12( Vgs − Vth − Vds ) 2

( 1 − Abulk ' )Vds (1 − Abulk ' ) Abulk ' Vds 2 Qb = Wactive Lactive Cox[ Vfb − Vth + Φs + − ] A ' 2 12(Vgs − Vth − bulk Vds ) 2

B-16

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Capacitance Model Equations

  2  Vgs − Vth Abulk '  ( Abulk ' Vds) Qd = −Wactive Lactive Cox  + Vds −  A ' 2 4  24(Vgs − Vth − bulk Vds )   2 

Q s = −( Qg + Q b + Qd )

otherwise

Qg = Wactive Lactive Cox (Vgs − Vfb − Φs −

Qb = −Wactive L active Cox (Vfb + Φs − Vth +

Vdsat ) 3

( 1 − Abulk ' )Vdsat ) 3

Qd = 0

Qs = − (Qg + Qb )

(2) capMod = 1 The flat-band voltage Vfb is calculated from

V fb = Vth − Φ s − K1ox Φ s − Vbseff

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-17

Capacitance Model Equations

where the bias dependences of Vth given in Section B.1.1 are not considered in calculating Vfb for capMod = 1. if (Vgs < Vfb + Vb s+ Vgsteffcv)

Qgl = Wactive LactiveC ox (Vgs − V fb − Vbs − Vgsteffcv ) else Qg 1 = WactiveLactiveCox ⋅

(

2 4 V − V fb − Vgsteff, CV − Vbseff K1ox  − 1 + 1 + gs 2 2  K1 ox 

)   

Qb 1 = −Qg 1

Vdsat,cv =

Vgsteffcv Abulk '

  CLC  CLE  A bulk '= A bulk0 1 +    L  eff   

 K1ox Abulk 0 = 1 + 2 Φs − Vbseff 

 A0 Leff B0  1  + ⋅ L +2 X X Weff '+B1  1 + KetaVbseff J dep  eff 

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-18

Capacitance Model Equations

  V − V th − voffcv   V gsteff,cv = noff ⋅ nvt ln 1 + exp  gs     noff ⋅ nvt   

if (Vds <=Vdsat)

    2 Vds Abulk ' Vds   Qg = Qg 1 + Wactive Lactive Cox Vgsteff cv − + Abulk '  2    12 Vgsteff cv − Vds       2

   1− A ' 2  (1 − Abulk ' ) Abulk ' Vds  bulk Qb = Qb 1 + Wactive Lactive Cox  Vds − A '  2  12 Vgsteffcv − bulk Vds       2  (i) 50/50 Channel-charge Partition

Qs = Qd

   W active L active C ox  A bulk ' A bulk ' 2 V ds 2  = − V gsteff cv − V ds + A bulk ' 2  2   1 2 V gsteffcv − Vd s       2

(ii) 40/60 Channel-charge partition

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-19

Capacitance Model Equations

Qs = −

Wactive Lactive Cox A ' 2  2 Vgsteff cv − bulk Vds    2

4 2 2 2 3   Vgsteffcv 3 − Vgstefcvf 2 ( Abulk ' Vds ) + Vgsteffcv ( Abulk ' Vds ) − ( Abulk ' Vds )    3 3 15

Qd = −( Qg + Qb + Qs) (iii) 0/100 Channel-charge Partition

  2 V  A ' V Abulk ' Vds ( gstefcv bulk ds )   Qs = −Wactive Lactive Cox + − Abulk '    2 4  24 Vgsteffcv − Vds       2

Qd = −( Qg + Qb + Qs) if (Vds > Vdsat )

Vdsat   Qg = Q g 1 + Wactive Lactive C ox  Vgsteff cv −   3 

Qb = Q b 1 − Wactive Lactive Cox

(V

gsteffcv

− Vdsat

)

3

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-20

Capacitance Model Equations

(i) 50/50 Channel-charge Partition

Qs = Qd = −

Wactive Lactive Cox Vgsteff cv 3

(ii) 40/60 Channel-charge Partition

Qs = −

2Wactive LactiveCox Vgsteffcv 5

Qd = −( Qg + Qb + Qs) (iii) 0/100 Channel-charge Partition

Qs = −Wactive Lactive Cox

2Vgstefcv 3

Qd = −( Qg + Qb + Qs) (3) capMod = 2 The flat-band voltage Vfb is calculated from

vfb = Vth − Φ s − K1o x Φ s − Vbseff

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-21

Capacitance Model Equations

where the bias dependences of Vth given in Section B.1.1 are not considered in calculating Vfb for capMod = 2. Q g = −( Q inv + Q acc + Q sub0 + δQ sub )

Q b = Q acc + Q sub 0 + δQ sub

Q inv = Q s + Q d

{

}

VFBeff = vfb − 05 . V3 + V32 + 4δ 3vfb

where V3 = vfb − Vgb − δ 3 ; δ 3 = 0.02

(

Qacc = −Wactive Lactive Cox VFBeff − vfb

Qsub0

)

2 4(V gs − V FBeff − V gsteff,CV − Vbseff )  K1ox  = −WactiveL activeC ox ⋅ −1 + 1 + 2  2  K 1ox  

V dsat , cv =

Vgsteff,cv gstefcvf A bulk '

  CLC  CLE Abulk ' = Abulk 0  1 +     L active 

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B-22

Capacitance Model Equations

 K1ox Abulk 0 = 1 + 2 Φs − Vbseff 

 A0 Leff B0   1  +  ⋅ 1 + KetaV L + 2 X X  W ' + B eff 1 bseff J dep  eff 

  Vgs −Vth − voffcv  Vgsteff,cv = noff ⋅ nvt ln 1 + exp     noff ⋅ nv  t  

{

Vcveff = Vdsat, cv − 0.5 V4 + V42 + 4δ 4Vdsat, cv

}

where V4 = Vdsat,cv − Vds − δ 4 ; δ 4 = 0.02

  2 2   A ' V Abulk ' bulk cveff     Qinv = −Wactive Lactive Cox Vgsteff cv − V + Abulk ' 2 cveff     12Vgsteff cv − Vcveff       2

δQsub

  2   1 − A ' A ' V ( ) 1 − A ' bulk bulk cveff bulk  = Wactive L active C ox  Vcveff − Abulk '  2   12 Vgsteffcv − Vcveff       2

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B-23

Capacitance Model Equations

B.2.3.1 50/50 Charge partition    2 2  Abulk ' Vcveff Wactive Lactive Cox  Abulk '  Qs = Qd = 05 . Qinv = − V cv − Vcveff +  gsteff A 2 2   12Vgsteffcv − bulk Vcveff       2

B.2.3.2 40/60 Channel-charge Partition

Qs = −

Qd = −

(

)

(

)

(

)

2 3 Wactive LactiveCox 4 2 2  2 Vgsteffcv 3 − Vgsteffc − Abulk' Vcveff  2 gstefcvf Abulk ' Vcveff + Vgsteff Abulk ' Vcveff   A ' 3 3 15   2Vgsteff cv − bulk Vcveff    2

2 3 WactiveLactiveCox 5 1  3 2 − Abulk ' Vcveff  gsteff cv Abulk ' Vcveff + Vgsteff cv Abulk ' Vcveff 2  Vgsteffcv − Vgsteffc  3 5 A '    2Vgsteffcv − bulk Vcveff    2

(

)

(

)

(

)

B.2.3.3 0/100 Charge Partition   2  Vgsteffcv A ' V  A ' V bulk cveff gstefcvf bulk cveff  Qs = −Wactive Lactive Cox  + − Abulk '  2 4   24 Vgsteffcv − Vcveff       2

(

)

  2 V  A ' V 3 A ' V bulk cveff gsteffcv bulk cveff   Qd = − Wactive Lactive Cox − + Abulk '  2 4    8 Vgsteffcv − Vcveff       2

(

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

)

B-24

Capacitance Model Equations

(3) capMod = 3 (Charge-Thickness Model) capMod = 3 also uses the bias-independent Vth to calculate Vfb as in capMod = 1 and 2.

vfb = Vth − Φ s − K1o x Φ s − Vbseff

For the finite charge thickness (XDC ) formulations, refer to Chapter 4.

Q acc = WLC oxeff ⋅V gbacc

V gbacc =

[

1 ⋅ V0 + V 02 + 4δ 3 V fb 2

]

V0 = V fb + Vbseff − Vgs − δ 3

{

}

VFBeff = vfb − 05 . V3 + V32 + 4δ 3vfb

Coxeff =

where V3 = vfb − Vgb − δ 3; δ 3 = 0.02

Cox Ccen Cox + Ccen

Ccen = ε si X DC

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-25

Capacitance Model Equations

 V gsteffCV ⋅ (V gsteffCV + 2K 1ox 2Φ B Φ δ = Φ s − 2Φ B = ν t ln   moin ⋅ K1 ox 2ν t 

2

Qsub0 = −WLCoxeff ⋅

K1ox 2

V cveff = Vdsat −

   

 4(Vgs − VFBeff − Vbseffs− Vgsteff,cv )  ⋅ -1 + 1 +  K1ox2  

(

1 ⋅ V1 + V12 + 4δ 3V dsat 2

)

V1 = Vdsat − Vds − δ 3

V dsat =

V gsteff , cv − ϕ δ Abulk '

  2 2   Abulk' Vcveff 1  Qinv = −WLCoxeff ⋅ Vgsteff,cv − ϕδ − Abulk'Vcveff + 2 Abulk'Vcveff     12 ⋅ Vgsteff,cv − ϕδ −  2    

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-26

Capacitance Model Equations

δQ sub = WLC oxeff

  2 1 − A '  (1 − Abulk ') ⋅ Abulk 'Vcveff bulk  ⋅ Vcveff −  2 Abulk ' Vcveff    12 ⋅ V gsteff ,cv − ϕ δ −  2    

(i) 50/50 Charge Partition

  2 2   WLC A ' V 1 1 oxeff bulk cveff Vgsteff,cv −ϕδ − Abulk'Vcveff +  QS = QD = Qinv = − 2 2  2 Abulk'Vcveff   12⋅ Vgsteff,cv −ϕδ −  2   

(ii) 40/60 Charge Partition

2 2  3 4 2 2 3 (Vgsteff,cv −ϕδ ) − 3(Vgsteff,cv −ϕδ ) Abulk'Vcveff+ 3(Vgsteff,cv −ϕδ )(Abulk'Vcveff) − 15(Abulk'Vcveff)  A 'V   2Vgsteff,cv −ϕδ − bulk cveff  2 

QS = −

QD =−

WLCoxeff

2

 3 5 2 2 1 3 (Vgsteff,cv −ϕδ ) −3(Vgsteff,cv −ϕδ ) Abulk'Vcveff+(Vgsteff,cv −ϕδ )( Abulk'Vcveff) −5( Abulk'Vcveff)  A 'V   2Vgsteff,cv −ϕδ − bulk cveff  2   WLC oxeff

2

(iii) 0/100 Charge Partition

QS = −

WLCoxeff 2

  2 2   Abulk' Vcveff 1  ⋅ Vgsteff,cv −ϕδ + Abulk'Vcveff − 2 Abulk'Vcveff    12⋅ Vgsteff,cv −ϕδ −  2   

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-27

Capacitance Model Equations

QD = −

WLCoxeff 2

  2 2   Abulk' Vcveff 3  ⋅ Vgsteff, cv − ϕδ − Abulk 'Vcveff + 2 Abulk'Vdveff     4 ⋅ Vgsteff,cv − ϕδ −  2    

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

B-28

APPENDIX C: References

[1] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p.11, vol. 18, 1989. [2] Muller and Kamins, Devices Electronics for Integrated Circuits, Second Edition. [3] J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko and C. Hu., BSIM3 Version 2.0 User’s Manual, March 1994. [4] J.A. Greenfield and R.W. Dutton, "Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation," IEEE Trans. Electron Devices, vol. ED-27, p.1520, 1980. [5] H.S. Lee. "An Analysis of the Threshold Voltage for Short-Channel IGFET's," SolidState Electronics, vol.16, p.1407, 1973. [6] G.W. Taylor, "Subthreshold Conduction in MOSFET's," IEEE Trans. Electron Devices, vol. ED-25, p.337, 1978. [7] T. Toyabe and S. Asai, "Analytical Models of Threshold Voltage and Breakdown Voltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis," IEEE J. Solid-State Circuits, vol. SC-14, p.375, 1979. [8] D.R. Poole and D.L. Kwong, "Two-Dimensional Analysis Modeling of Threshold Voltage of Short-Channel MOSFET's," IEEE Electron Device Letter, vol. ED-5, p.443, 1984.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

C-1

[9] J.D. Kendall and A.R. Boothroyd, "A Two-Dimensional Analytical Threshold Voltage Model for MOSFET's with Arbitrarily Doped Substrate," IEEE Electron Device Letter, vol. EDL-7, p.407, 1986. [10] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C. Cheng, "Threshold Voltage Model For Deep-Submicrometer MOSFETs,"

IEEE Tran.

Electron Devices, vol. 40, pp. 86-95, Jan., 1993. [11] Y.C. Cheng and E.A. Sullivan, "Effect of Coulombic Scattering on Silicon Surface Mobility," J. Appl. Phys. 45, 187 (1974). [12] Y.C. Cheng and E.A. Sullivan, Surf. Sci. 34, 717 (1973). [13] A.G. Sabnis and J.T. Clemens, "Characterization of Electron Velocity in the Inverted <100> Si Surface," Tech. Dig.- Int. Electron Devices Meet., pp. 18-21 (1979). [14] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989. [15] M.S. Liang, J.Y. Choi, P.K. Ko, and C. Hu, "Inversion-Layer Capacitance and Mobility of Very Thin Gate-Oxide MOSFET's," IEEE Trans. Electron Devices, ED33, 409, 1986. [16] F. Fang and X. Fowler, "Hot-electron Effects and Saturation velocity in Silicon Inversion Layer," J. Appl. Phys., 41, 1825, 1969. [17] E. A. Talkhan, I. R. Manour and A. I. Barboor, "Investigation of the Effect of DriftField-Dependent Mobility on MOSFET Characteristics," Parts I and II. IEEE Trans. on Electron Devices, ED-19(8), 899-916, 1972.

C-2

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

[18] M.C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETs," Ph. D. Dissertation, University of California. [19] K.Y. Toh, P.K. Ko and R.G. Meyer, "An Engineering Model for Short-channel MOS Devices," IEEE Jour. of Solid-State Circuits, vol. 23, No. 4, Aug. 1988. [20] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "Hot-Electron Induced MOSFET Degradation - Model, Monitor, Improvement," IEEE Tran. on Electron Devices, Vol. 32, pp. 375-385, Feb. 1985. [21] F.C. Hsu, P.K. Ko, S. Tam, C. Hu and R.S. Muller, "An Analytical Breakdown Model for Short-Channel MOSFET's," IEEE Trans. on Electron Devices, Vol.ED29, pp. 1735, Nov. 1982 [22] H. J. Parke, P. K. Ko, and C. Hu, “A Measurement-based Charge Sheet Capacitance Model of Short-Channel MOSFET’s for SPICE,”in IEEE IEDM 86, Tech. Dig., pp. 485-488, Dec. 1986. [23] M. Shur, T.A. Fjeldly, T. Ytterdal, and K. Lee, “A Unified MOSFET Model,”SolidState Electron., 35, pp. 1795-1802, 1992. [24] MOS9 Documentation. [25] C. F. Machala, P. C. Pattnaik and P. Yang, "An Efficient Algorithms for the Extraction of Parameters with High Confidence from Nonlinear Models," IEEE Electron Device Letters, Vol. EDL-7, no. 4, pp. 214-218, 1986. [26] Y. Tsividis and K. Suyama, “MOSFET Modeling for Analog Circuit CAD: Problems and Prospects,”Tech. Dig. vol. CICC-93, pp. 14.1.1-14.1.6, 1993.

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

C-3

[27] C. L. Huang and G. Sh. Gildenblat, "Measurements and Modeling of the n-channel MOSFET Inversion Layer Mobility and Device Characteristics in the Temperature Range 60-300 K," IEEE Tran. on Electron Devices, vol. ED-37, no.5, pp. 12891300, 1990. [28] D. S. Jeon, et al, IEEE Tran. on Electron Devices, vol. ED-36, no. 8, pp1456-1463, 1989. [29] S. M. Sze, Physics of Semiconductor Devices, 2nd Edition. [30] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition. [31] R. Rios, N. D. Arora, C.-L. Huang, N. Khalil, J. Faricelli, and L. Gruber, “A physical compact MOSFET model, including quantum mechanical effects, for statistical circuit design applications”, IEDM Tech. Dig., pp. 937-940, 1995. [32] Weidong Liu, Xiaodong Jin, Ya-Chin King, and Chenming Hu, “An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness”, IEEE Trans. on Electron Devices, vol. ED-46, May, 1999. [33] Mansun Chan, et al, "A Relaxation time Approach to Model the Non-Quasi-Static Transient Effects in MOSFETs," IEDM, 1994 Technical Digest, pp. 169-172, Dec. 1994. [34] P. K. Ko, “Hot-electron Effects in MOSFET’s”, Ph. D Dissertation, University of California, Berkeley, 1982

C-4

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

[35] K.K. Hung et al, “A Physics-Based MOSFET Noise Model for Circuit Simulators,” IEEE Transactions on Electron Devices, vol. 37, no. 5, May 1990. [36] K.K. Hung et al, “A Unified Model for the Flicker Noise in Metal-Oxide Semiconductor Field-Effect Transistors,” IEEE Transactions on Electron Devices, vol. 37, no. 3, March 1990. [37] T.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, 1987.

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C-5

APPENDIX D: Model Parameter Binning

Below is the information on parameter binning regarding which model parameters can or cannot be binned. All those parameters which can be binned follow this implementation: P = P0 +

PL P PP + W + Leff Weff Leff ×Weff

For example, for the parameter k1: P0 = k1, PL = lk1, PW = wk1, PP = pk1. binUnit is a bining unit selector. If binUnit = 1, the units of Leff and W eff used in the binning equation above have the units of microns; therwise in meters. For example, for a device with Leff = 0.5µm and W eff = 10µm. If binUnit = 1, the parameter values for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively. Therefore, the effective value of vsat for this device is vsat = 1e5 + 1e4/0.5 + 2e4/10 + 3e4/(0.5*10) = 1.28e5 To get the same effective value of vsat for binUnit = 0, the values of vsat, lvsat, wvsat, and pvsat would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus, vsat = 1e5 + 1e-2/0.5e6 + 2e-2/10e-6 + 3e-8/(0.5e-6 * 10e-6) = 1.28e5

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-1

Model Control Parameters

D.1 Model Control Parameters

Symbols used in equation None None None None

Symbols used in SPICE level version binUnit paramChk

mobMod capMod

mobMod capMod

nqsMod noiMod

nqsMod noiMod

Description The model selector Model version selector Bining unit selector Parameter value check Mobility model selector Flag for the short channel capacitance model Flag for NQS model Flag for Noise model

Can Be Binned? NO NO NO NO NO NO NO NO

D.2 DC Parameters

Symbols Symbols used in used in equation SPICE

D-2

Description

Can Be Binned?

Vth0

vth0

Threshold voltage @Vbs =0 for Large L.

YES

VFB

vfb

Flat band voltage

YES

K1

k1

First order body effect coefficient

YES

K2

k2

Second order body effect coefficient

YES

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

DC Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

K3

k3

Narrow width coefficient

YES

K3b

k3b

Body effect coefficient of k3

YES

W0

w0

Narrow width parameter

YES

Nlx

nlx

Lateral non-uniform doping parameter

YES

Dvt0

dvt0

first coefficient of short-channel effect on Vth

YES

Dvt1

dvt1

Second coefficient of shortchannel effect on Vth

YES

Dvt2

dvt2

Body-bias coefficient of shortchannel effect on Vth

YES

Dvt0w

dvt0w

First coefficient of narrow width effect on Vth for small channel length

YES

Dvt1w

dvtw1

Second coefficient of narrow width effect on Vth for small channel length

YES

Dvt2w

dvt2w

Body-bias coefficient of narrow width effect for small channel length

YES

µ0

u0

Mobility at Temp = Tnom NMOSFET PMOSFET

YES

Ua

ua

First-order mobility degradation coefficient

YES

Ub

ub

Second-order mobility degradation coefficient

YES

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-3

DC Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Uc

uc

Body-effect of mobility degradation coefficient

YES

νsat

vsat

Saturation velocity at Temp = Tnom

YES

A0

a0

Bulk charge effect coefficient for channel length

YES

Ags

ags

gate bias coefficient of Abulk

YES

B0

b0

Bulk charge effect coefficient for channel width

YES

B1

b1

Bulk charge effect width offset

YES

Keta

keta

Body-bias coefficient of bulk charge effect

YES

A1

a1

First non0saturation effect parameter

YES

A2

a2

Second non-saturation factor

YES

Rdsw

rdsw

Parasitic resistance per unit width

YES

Prwb

prwb

Body effect coefficient of Rdsw

YES

Prwg

prwg

Gate bias effect coefficient of Rdsw

YES

Wr

wr

Width Offset from Weff for Rds calculation

YES

Wint

wint

Width offset fitting parameter from I-V without bias

NO

Lint

lint

Length offset fitting parameter from I-V without bias

NO

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-4

DC Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

dWg

dwg

Coefficient of Weff’s gate dependence

YES

dWb

dwb

Coefficient of Weff’s substrate body bias dependence

YES

Voff

voff

Offset voltage in the subthreshold region for large W and L

YES

Nfactor

nfactor

Subthreshold swing factor

YES

Eta0

eta0

DIBL coefficient in subthreshold region

YES

Etab

etab

Body-bias coefficient for the subthreshold DIBL effect

YES

Dsub

dsub

DIBL coefficient exponent in subthreshold region

YES

Cit

cit

Interface trap capacitance

YES

Cdsc

cdsc

Drain/Source to channel coupling capacitance

YES

Cdscb

cdscb

Body-bias sensitivity of Cdsc

YES

Cdscd

cdscd

Drain-bias sensitivity of Cdsc

YES

Pclm

pclm

Channel length modulation parameter

YES

Pdiblc1

pdiblc1

First output resistance DIBL effect correction parameter

YES

Pdiblc2

pdiblc2

Second output resistance DIBL effect correction parameter

YES

Pdiblcb

pdiblcb

Body effect coefficient of DIBL correction parameters

YES

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-5

DC Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Drout

drout

L dependence coefficient of the DIBL correction parameter in Rout

YES

Pscbe1

pscbe1

First substrate current bodyeffect parameter

YES

Pscbe2

pscbe2

Second substrate current bodyeffect parameter

YES

Pvag

pvag

Gate dependence of Early voltage

YES

δ

delta

Effective Vds parameter

YES

Ngate

ngate

poly gate doping concentration

YES

α0

alpha0

The first parameter of impact ionization current

YES

α1

alpha1

Isub parameter for length scaling

YES

β0

beta0

The second parameter of impact ionization current

YES

Rsh

rsh

Source drain sheet resistance in ohm per square

NO

Js0

js

Source drain junction saturation current per unit area

NO

ijth

ijth

Diode limiting current

NO

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-6

AC and Capacitance Parameters

D.3 AC and Capacitance Parameters

Symbols used in equation

Symbols used in SPICE

Xpart

xpart

Charge partitioning rate flag

CGS0

cgso

Non LDD region source-gate overlap capacitance per channel length

NO

CGD0

cgdo

Non LDD region drain-gate overlap capacitance per channel length

NO

CGB0

cgbo

NO

Cj

cj

Gate bulk overlap capacitance per unit channel length Bottom junction per unit area

Mj

mj

Bottom junction capacitance grating coefficient

NO

Mjsw

mjsw

Source/Drain side junction capacitance grading coefficient

NO

Cjsw

cjsw

Source/Drain side junction capacitance per unit area

NO

Pb Pbsw

pb pbsw

Bottom built-in potential Source/Drain side junction built-in potential

NO NO

CGS1

cgs1

Light doped source-gate region overlap capacitance

YES

CGD1

cgd1

Light doped drain-gate region overlap capacitance

YES

Description

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Can Be Binned? NO

NO

D-7

AC and Capacitance Parameters

Symbols used in equation

Symbols used in SPICE

CKAPPA

ckappa

Coefficient for lightly doped region overlap capacitance Fringing field capacitance

YES

Cf

cf

fringing field capacitance

YES

CLC

clc

Constant term for the short channel model

YES

CLE

cle

Exponential term for the short channel model

YES

DLC

dlc

Length offset fitting parameter from C-V

YES

DWC

dwc

Width offset fitting parameter from C-V

YES

Vfbcv

vfbcv

Flat-band voltage parameter (for capMod = 0 only)

YES

noff

noff

CV parameter in Vgsteff,CV for weak to strong inversion

YES

voffcv

voffcv

CV parameter in Vgsteff,CV for weak to strong inversion

YES

acde

acde

Exponential coefficient for charge thickness in capMod=3 for accumulation and depletion regions

YES

moin

moin

Coefficient for the gate-bias dependent surface potential

YES

Description

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

Can Be Binned?

D-8

NQS Parameters

D.4 NQS Parameters

Symbols used in equation Elm

Symbols used in Description SPICE elm Elmore constant of the channel

Can Be Binned? YES

D.5 dW and dL Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Wl

wl

Coefficient of length dependence for width offset

NO

Wln

wln

Power of length dependence of width offset

NO

Ww

ww

Coefficient of width dependence for width offset

NO

Wwn

wwn

Power of width dependence of width offset

NO

Wwl

wwl

Coefficient of length and width cross term for width offset

NO

Ll

ll

Coefficient of length dependence for length offset

NO

Lln

lln

Power of length dependence for length offset

NO

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-9

dW and dL Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Lw

lw

Coefficient of width dependence for length offset

NO

Lwn

lwn

Power of width dependence for length offset

NO

Lwl

lwl

Coefficient of length and width cross term for length offset

NO

Llc

Llc

Coefficient of length dependence for CV channel length offset

NO

Lwc

Lwc

Coefficient of width dependence for CV channel length offset

NO

Lwlc

Lwlc

Coefficient of length and widthdependence for CV channel length offset

NO

Wlc

Wlc

Coefficient of length dependence for CV channel width offset

NO

Wwc

Wwc

Coefficient of widthdependence for CV channel width offset

NO

Wwlc

Wwlc

Coefficient of length and widthdependence for CV channel width offset

NO

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-10

Temperature Parameters

D.6 Temperature Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Tnom

tnom

Temperature at which parameters are extracted

NO

µte

ute

Mobility temperature exponent

YES

Kt1

kt1

Temperature coefficient for threshold voltage

YES

Kt1l

kt1l

Channel length dependence of the temperature coefficient for threshold voltage

YES

Kt2

kt2

Body-bias coefficient of Vth temperature effect

YES

Ua1

ua1

Temperature coefficient for Ua

YES

Ub1

ub1

Temperature coefficient for Ub

YES

Uc1

uc1

Temperature coefficient for Uc

YES

At

at

Temperature coefficient for saturation velocity

YES

Prt

prt

Temperature coefficient for Rdsw

YES

nj

nj

Emission coefficient

YES

XTI

xti

Junction current temperature exponent coefficient

YES

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-11

Flicker Noise Model Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

tpb

tpb

Temperature coefficient of Pb

NO

tpbsw

tpbsw

Temperature coefficient of Pbsw

NO

tpbswg

tpbswg

Temperature coefficient of Pbswg

NO

tcj

tcj

Temperature coefficient of Cj

NO

tcjsw

tcjsw

Temperature coefficient of Cjsw

NO

tcjswg

tcjswg

Temperature coefficient of Cjswg

NO

D.7 Flicker Noise Model Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Noia

noia

Noise parameter A

NO

Noib

noib

Noise parameter B

NO

Noic

noic

Noise parameter C

NO

Em

em

Saturation field

NO

Af

af

Flicker noise exponent

NO

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-12

Process Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Ef

ef

Flicker noise frequency exponent

NO

Kf

kf

Flicker noise parameter

NO

D.8 Process Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Tox

tox

Gate oxide thickness

NO

Toxm

toxm

Tox at which parameters are extracted

NO

Xj

xj

Junction Depth

YES

γ1

gamma1

Body-effect coefficient near the surface

YES

γ2

gamma2

Body-effect coefficient in the bulk

YES

Nch

nch

Channel doping concentration

YES

Nsub

nsub

Substrate doping concentration

YES

Vbx

vbx

Vbs at which the depletion region width equals xt

YES

Vbm

vbm

Maximum applied body bias in Vth calculation

YES

Xt

xt

Doping depth

YES

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-13

Geometry Range Parameters

D.9 Geometry Range Parameters

Symbols Symbols used in used in equation SPICE

Description

Can Be Binned?

Lmin

lmin

Minimum channel length

NO

Lmax

lmax

Maximum channel length

NO

Wmin

wmin

Minimum channel width

NO

Wmax

wmax

Maximum channel width

NO

binUnit

binUnit

Binning unit selector

NO

BSIM3v3.3 Manual Copyright © 2005 UC Berkeley

D-14