Bit Circuitry Suggestion

Title – Circuitry for additional BIT benefit. Abstract - This self described 'paper' is an informal suggested use of an additional technique and circuitry to improve the fault detection, localization, isolation, confinement and recovery within a generic electronic hardware system. Keywords - Analog circuits, sensors, signal conditioning, Built In Test, BIT, fault detection, localization and isolation. Please note: This is an original work though it may not be new nor unique. It is based upon my own musings. If FIG 1

doesn't appear reasonable, you probably should stop reading here.

The System The system considered is not specific but a generalization of the systems I've been associated with over the years. The generalized system I imagine is dependent on the electrical inputs of a number of external sensors, the signal conditioning of those sensors, the collection and direction of those signals through various stages of gain and offset and fed to an analog to digital circuit for software processing. The system also generates output signals used elsewhere in the larger system. Typically these systems are boxed hardware systems of one or more custom PWBs with multiple connectors to the outside for AC mains power, communications and sensors. These system boxes could weigh 50 lbs or more and can be rack mounted. The boxes are often machined housings sealed against the environment. The system performs some critical function such as a control law in a larger system, an example being propulsion/ traction control of a diesel electric locomotive. The diagram of FIG 1 summarizes the hardware, focusing only on the input sensors. The signals delivered externally are not given or shown. This paper focuses on the sub circuit in FIG 2, a typical signal conditioner and sensor block diagram and its rule in the system. A large percentage of the 'rest of the system' is digital; CPUs, DSP chips, FPGA circuits and logic glue which are included to allow for rational controlled operation. As a system the embedded software runs real time control algorithms. The overall system function is important to some larger system so additional circuits, hardware and software are added to communicate information to the higher level. Per FIG 1 the digital output of the A/D is segregated in time for each monitored signal in the Sensor, S/C, MUX, G&0 paths and processed into engineering units for use by the control law algorithm. It is noted that the G&O blocks may provide filtering. An A/D per monitored signal is also used in some system designs, but the prior configuration of multiple signals fed into a single A/D is considered here. Because of software embedded in the system and multiple monitoring points the system can be designated a fault tolerant hardware system. If monitored values are in error some logic bits can be set and commands can be modified influencing the system behavior. In such a system designers are including those circuits not always dictated by system specification, but implied as useful by the utility of additional run time data. This paper suggests only one such additional circuit.

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FIG 1 Generalized Hardware System Given – a idealized fault tolerant hardware system that includes the input of external sensors and signals fed to a single precision A/D. This diagram includes Sensors, SN, signal conditioners, S/GN, muxes, MUXN , Gain and Offset blocks, G&O, and a high end analog to digital converter, A/D. FIG 2 presents a typical signal conditioner and sensor block diagram within the system. This configration includes fixed signals in addition to the sensor. Some fixed signals are those that the software can easily handle with additional code, such as the added sensor interface ground, Gnd1, of FIG 2; monitoring this point aids in detecting ground bounce or offset in the sensor input. DC supply voltages and reference voltages, VREF, are also used as such an input. Such additional fixed signals provide additional information, beyond control laws, that may be used in the software processing of data, by BIT routines, for error detection.

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Rest of the system

G&O

M U X N

External Sensors

SN S/CN

Gnd0

Gnd1

Fig 2 Typical Sensor Block Diagram. Given – a typical signal conditioner and sensor block diagram emphasizing the different grounds so marked because these exist at different potentials. Gnd1 is assumed to be above and below Gnd0 at times due to electrical noise. Gnd1 is monitored for purposes of corrections by software. This diagram includes Sensors, SN, signal conditioners, S/GN, muxes, MUXN , Gain and Offset blocks, G&O, and “the rest of the system”. Analog circuit development is an art - not a science- pretty or messy in the eye of the designer/ beholder. Any effort related to the analog design effort also becomes an art, such as the techniques used in adding built in test (BIT) circuitry to the underlying basic circuitry that performs the required operation of the Rambling on a circuit technique by Mr. Bob

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system. The suggested approach may not be desirable by all designers for such systems. The Suggested Accessory Signal A simple accessory signal is suggested. This accessory signal would be a low frequency signal, somewhere between the DC of the supplies and the low frequency sensors, per FIG 4. The accessory signal is treated much like an additional external input that just happens to be internally routed. This is not radically new – grounds, supplies and DC levels are typically fed back into monitoring circuits and used as monitored references.

Ampl

A

C

B Freq

The accessory signal could be implemented in several ways. It can be provided from some other FIG 4 circuit source newly instantiated into the system or Frequency of it can be added to the existing hardware using a free Accessory Signals analog I/O pin on the system FPGA. By The accessory signals (B) are placed low in frequency near configuration it can be synchronous or DC (A), away from the higher frequencies ( C) of most of asynchronous; synchronous is assumed. the sensors and the clock rate of the system. Amplitude is arbitrary The accessory signal can be any time varying signal, triangle waves and sinusoids come to mind. Sinusoids are preferred as the mathematical integrals and derivatives are also sinusoidal. The use of trigonometric identities of sinusoids assist in the possible software algorithms of BIT using these signals. The sinusoidal nature allows for more robust BIT analysis than with DC levels, with a slight increase in size and complexity of the existing software BIT algorithm. DC signals are always available in systems. The accessory signal is a time modulated DC level conceptually. All monitored signals are filtered in some manner between the sensor or input and the A/D input pin, usually by the G&O blocks. Filtering modifies amplitude and phase. The use of low frequency for the accessory signal will cause less amplitude or phase modification to occur as the signal routs through various circuit blocks. The use of low frequency means those components found in the DC paths can be used, no special components need consideration. The use of a nearly DC sinusoid instead of a purely DC signal has a minor benefit in regards to stuck at faults. The DC signal path may fail at a level near enough to the desired to not be detectable. A stuck at fault for a sinusoid will soon be apparent. The suggested accessory signal, a sinusoid, Sig1, follows. Sig 1 ≡ A sin ω t

It is assumed Sig1 is created by the FPGA circuitry and synchronous to the system software. The amplitude versus time commands for the generation of the sinusoidal signal is known. The relationship of the accessory signal to all other signals is known. The monitored signal can be compared with the commands. Trigonometric relationships can be used in the run time monitor algorithms. Rambling on a circuit technique by Mr. Bob

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Application of the Accessory Signal It is suggested here that an additional, accessory, signal be added as diagrammed in FIG 3.

Rest of the system G&O

SIGJ

M U X

Additional differential signal generation

SN

N

Gnd0

S/CN Gnd1

Gnd0 FIG 3 Suggested implementation of accessory signal Additional MUX inputs are used to route the accessory signals through the gain and offset (G&O) blocks used by the sensor signals. The quality of the monitored accessory signal implies the overall health of the sensor monitoring circuits. The straightforward use of the accesory signal is to verify the Mux/ G&O chains are operating as expected. The accessory signal can be buffered and made input to a couple of muxes in the chain at points A & B. If in software the amplitudes are normalized and the sample time for these is sufficiently close where tA ≈ tB then a simple difference relationship, ( Sig1_A – Sig1_B) ≈ 0, can be used on a sample by sample basis, with no storage memory required, a simple software routine. If tA ≠ tB then trigonometric corrections on the synchronous accessory signals may be made before the comparison. A Rambling on a circuit technique by Mr. Bob

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simple relationship holds if the sampling time delta is equivalent to π/2 radians of the accessory signal basic frequency: [ (Sig1_A)2 + (Sig1_B)2 ] ≈ 1 Another use of the accessory signal is for checking ground quality of Gnd1, FIG3. If a given signal from Sig1 is fed into the mux at the sensor/ system boundary by a differential driver, of known behavior from final test, then comparisons of commanded versus monitored values can be used. The delta values from expected can be indicative of the sensor ground potential. The suggestion can provide more sophisticated information if required. If a large amount of monitored data is stored, harmonic distortion analysis can be made. Multiple signals Its no stretch to extend the accessory signal set. The suggested set is not inclusive; readers will consider others just as viable. Sig 2 ≡ A sin 

π π − ω t = A sin ω t   = A cos ω t 2 2

Sig 3 ≡ A sin ω t 

2π  3

Sig 4 ≡ A sin ω t 

4π 2π  = A sin ω t −  3 3

The use of Sig1, Sig3 and Sig4 can be used in conjunction with any 3 phase circuits operating within the system when fed into the signal chain of the phase signals. Expected Concerns of Suggestion Additional I/O circuitry is required. The use of FPGA pinout might not be possible if the FPGA is maxed out. Those FPGAs with analog I/O almost always have few available A/Ds and DACs in use an almost always not available for free use. In systems with tightly coupled analog modules there is still analog I/O shortages. If the FPGA cannot be used for producing the additional accessory signals a more complicated system will be required with subsequent increased costs. The time multiplexed A/D puts constraints on the ability to group the sample time of the accessory signals; the requirements of the control law related signals must be met. Additional software and floating point algorithms will be required. The FPGA may not have sufficient free 'space' to add a place and route of the additional I/O and algorithms. BIT summary Fault tolerance is important in systems. Fault tolerance is a software intensive operation dependent on access to signals important to the control laws of the system and the additional signals useful for determining the run time health of the system. Rambling on a circuit technique by Mr. Bob

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Built In Test (BIT) algorithms operate in real time, parallel to and of a lower priority to the control laws, using the same monitoring points plus those unique to BIT. The BIT algorithm analyzes the signals and sets error bits in software should the amplitude be out of some specified range. These BIT triggered bits are used by the upper level software which may then change the system run time behavior accordingly. The set bits often get logged into non-volatile memory for post processing analysis. BIT is possible because the system requires many many monitored values at run time. The quality and characteristic of many are used by software to make pass/ fail decisions. Sometimes the monitored value itself is used to make some determination, such as a reference being 10% low, which may allow continued control law operation with some correction for this known problem. BIT results can be communicated to and used at a higher level, but discussions here only apply to the given FIG 1 system. There is detection-only BIT—the predominant form of BIT — which monitors signals, mathematically compares the monitored value to some a priori range of values and sets a bit, shouts 'Problem!', if the monitor is out of range. There are methods that examine multiply set bits and the related monitored values to indicate which sub circuit, module or PWB is at fault. This is fault localization. If the data can point to a single definable circuit block with greater than 90% confidence then this is fault isolation. Confinement is the capability of the system to isolate or nullify the behavior of the circuit under suspicion. This can be done by turning off the supply to the circuit or removing its effect on the control laws. Recovery is the modified run time behavior that allows for some level of 'run limp'. The primary purpose of BIT is to allow the system to continue running at some reduced level though there is a circuit problem. BIT also assists maintenance personnel in the proper maintenance of systems in a cost-effective manner. As a logged incident it can be used for design improvements. Test Considerations. The suggestion is intended as an appendage to a given system should there be hardware and software resources available. It can be included or modified for use at initial design development. In any case it is assumed that a test methodology and test equipment for the overall system exists. Most of the test procedures for characterizing and validating correct operation of the accessory signals can be done without external sensors. An external source can be used to implement the ground noise checks. The test measurement of the accessory signal circuitry is suggested to be done in the overall test sequence somewhere after JTAG boundary scan and the system functional test. Some Trigonometric Relationships A sin ω t − A sin ω t = 0

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2

2

 A sinω t   A cos ω t = A A sin ω t  A sin ω t 

2

2π 4π   A sin ω t  =0 3 3

2

2

2

2

2

2

 A sinω t   A cos ω t = A

 A sinω t   B cos ω t  ≠ A or ≠ B sin ω t  sinω t 

2

2π 4π   sin  = 0 3 3

Postscript This suggestion is the result of involvement with such systems and wondering if any benefit is possible for such a small design change. This paper is a chance to focus on one of many concepts churning in my mind. I hope it results in feedback from a fellow engineer so that I can change, improve, refine or reject the underlying concepts.

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