Avr Assembly Examples
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The AVR Assembler Site
The AVR Assembler Site HOME RETRO_DAN ASM FORUM ASM MATH
Welcome to AVR Assembler Site ASSEMBLY LANGUAGE:
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
The Mnemonic Representation of Machine Code. Assembly Language remains in use because of its close relationship to the underlying machine. It is used by those who need to compress programs into the smallest memory space and have it excecute as fast and efficiently as possible. It can be a difficult medium in which to work. Many can forget that whether done by man or compiler, all computer languages must be translated into machine code before they can run in hardware.
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
Submit New Routines, Updates, Bug Reports to AVR Assembler Forum at: http://avr.x. am
The AVR is a family of RISC microcontrollers from Atmel. The AVR architecture, first conceived by two electronic engineering students at the Norwegian Institute of Technology (NTH), has been refined and developed by Atmel Norway, in a division founded by the chip's architects.
The AVR architects, Vergard Wollan and Alf-Egil Bogen. Bogen's 1992 NTH thesis was titled: High Speed Analog to Digital Converters in CMOS.
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
Most high-level languages for the AVR core accomplish this by translating programs into Assembler Instructions first. The resultant Assembler Program is then converted to machinecode instructions. The process may be automated and appear transparent to the programmer. This is how the C compilers work.
A RetroDan (HWMNBN) Site
THE TWO-PASS ASSEMBLER
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
Since assembly language statements have a one-to-one correspondence with binary instructions it seems only logical to simply translate assembly instructions directly into binary machine code, one-ata-time. This method does not work due to forward references and jumps to lables that have not been defined yet. This is the reason most assemblers are the two-pass type.
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
The primary function of pass-one is to build up a symbol table that contain all the constants and labels along with their values. The second-pass then uses this symbol table to create the binary machine code.
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK Programming the AVR Microcontrollers in Machine Language
CLOCK 8564 90 DAYS DELAYS CALL ID
AVR << Prev | Ring Hub | Join | Rate| Next >>
DTMF 314 PWM 6CH PWM 10K
© WebRing Inc.
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ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal
http://avr-asm.tripod.com/ (1 of 2)1/20/2009 8:32:57 PM
The AVR Assembler Site
architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/ (2 of 2)1/20/2009 8:32:57 PM
The AVR Assembler Site
The AVR Assembler Site HOME RETRO_DAN ASM FORUM ASM MATH
Welcome to AVR Assembler Site ASSEMBLY LANGUAGE:
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
The Mnemonic Representation of Machine Code. Assembly Language remains in use because of its close relationship to the underlying machine. It is used by those who need to compress programs into the smallest memory space and have it excecute as fast and efficiently as possible. It can be a difficult medium in which to work. Many can forget that whether done by man or compiler, all computer languages must be translated into machine code before they can run in hardware.
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
Submit New Routines, Updates, Bug Reports to AVR Assembler Forum at: http://avr.x. am
The AVR is a family of RISC microcontrollers from Atmel. The AVR architecture, first conceived by two electronic engineering students at the Norwegian Institute of Technology (NTH), has been refined and developed by Atmel Norway, in a division founded by the chip's architects.
The AVR architects, Vergard Wollan and Alf-Egil Bogen. Bogen's 1992 NTH thesis was titled: High Speed Analog to Digital Converters in CMOS.
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
Most high-level languages for the AVR core accomplish this by translating programs into Assembler Instructions first. The resultant Assembler Program is then converted to machinecode instructions. The process may be automated and appear transparent to the programmer. This is how the C compilers work.
A RetroDan (HWMNBN) Site
THE TWO-PASS ASSEMBLER
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
Since assembly language statements have a one-to-one correspondence with binary instructions it seems only logical to simply translate assembly instructions directly into binary machine code, one-ata-time. This method does not work due to forward references and jumps to lables that have not been defined yet. This is the reason most assemblers are the two-pass type.
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
The primary function of pass-one is to build up a symbol table that contain all the constants and labels along with their values. The second-pass then uses this symbol table to create the binary machine code.
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK Programming the AVR Microcontrollers in Machine Language
CLOCK 8564 90 DAYS DELAYS CALL ID
AVR << Prev | Ring Hub | Join | Rate| Next >>
DTMF 314 PWM 6CH PWM 10K
© WebRing Inc.
Search
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal
http://avr-asm.tripod.com/index.html (1 of 2)1/20/2009 8:33:30 PM
The AVR Assembler Site
architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
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MULTIPLY & DIVIDE (AVR 200)
The AVR Assembler Site
MULTIPLY & DIVIDE (AVR 200) HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202
;**** A P P L I C A T I O N
N O T E
A V R 2 0 0
************************ ;* ;* Title: Multiply and Divide Routines ;* Version: 1.1 ;* Last updated: 97.07.04 ;* Target: AT90Sxxxx (All AVR Devices) ;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application Note lists subroutines for the following ;* Muliply/Divide applications: ;* ;* 8x8 bit unsigned ;* 8x8 bit signed ;* 16x16 bit unsigned ;* 16x16 bit signed ;* 8/8 bit unsigned ;* 8/8 bit signed ;* 16/16 bit unsigned ;* 16/16 bit signed ;* ;* All routines are Code Size optimized implementations ;*; *************************************************************************** .include "1200def.inc"
DEC ASCII
rjmp
RESET
;reset handle
INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; *************************************************************************** ;* ;* "mpy8u" - 8x8 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two register variables mp8u and mc8u. ;* The result is placed in registers m8uH, m8uL ;* ;* Number of words :9 + return ;* Number of cycles :58 + return ;* Low registers used :None ;* High registers used :4 (mp8u,mc8u/m8uL,m8uH,mcnt8u) ;* ;* Note: Result Low byte and the multiplier share the same register. ;* This causes the multiplier to be overwritten by the result. ;* ; *************************************************************************** ;***** Subroutine Register Variables
UART 305 UART 128
.def .def .def .def .def
UART BUFF USB 232 AVR ISP ISP 2313
mc8u mp8u m8uL m8uH mcnt8u
=r16 =r17 =r17 =r18 =r19
;multiplicand ;multiplier ;result Low byte ;result High byte ;loop counter
;***** Code
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
byte
DALLAS-1W
byte
mpy8u: ldi lsr
clr m8uH mcnt8u,8 mp8u
m8u_1: add
brcc m8u_2 m8uH,mc8u
m8u_2:
ror
;
;carry set add multiplicand to result High
m8uH
;rotate right result High
ror
m8uL
;rotate right result L byte and
dec brne ret
mcnt8u m8u_1
;decrement loop counter ;if not done, loop more
DALLAS CRC ETHNET 8019
;clear result High byte ;init loop counter ;rotate multiplier
multiplier
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; *************************************************************************** ;* ;* "mpy8s" - 8x8 Bit Signed Multiplication ;* ;* This subroutine multiplies signed the two register variables mp8s and ;* mc8s. The result is placed in registers m8sH, m8sL ;* The routine is an implementation of Booth's algorithm. If all 16 bits ;* in the result are needed, avoid calling the routine with ;* -128 ($80) as multiplicand ;* ;* Number of words :10 + return ;* Number of cycles :73 + return ;* Low registers used :None ;* High registers used :4 (mc8s,mp8s/m8sL,m8sH,mcnt8s) ;* ; ***************************************************************************
CLOCK 8564 ;***** Subroutine Register Variables
90 DAYS DELAYS
PWM 6CH
.def .def .def .def .def
PWM 10K
;***** Code
CALL ID DTMF 314
mc8s mp8s m8sL m8sH mcnt8s
=r16 =r17 =r17 =r18 =r19
;multiplicand ;multiplier ;result Low byte ;result High byte ;loop counter
mpy8s:
sub
m8sH,m8sH
;clear result High byte and
ldi m8s_1: add
mcnt8s,8 brcc m8s_2 m8sH,mc8s
;init loop counter ;if carry (previous bit) set ; add multiplicand to result
m8s_2: sub
sbrc mp8s,0 m8sH,mc8s
;
;if current bit set subtract multiplicand from
asr ror
m8sH m8sL
;shift right result High byte ;shift right result L byte and
dec brne ret
mcnt8s m8s_1
;decrement loop counter ;if not done, loop more
ENCODE STH-11
carry
ATMEL CORP AVR BUTTERFLY
High byte
AVR BOOK result High
multiplier
; *************************************************************************** ;* ;* "mpy16u" - 16x16 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two 16-bit register variables ;* mp16uH:mp16uL and mc16uH:mc16uL. ;* The result is placed in m16u3:m16u2:m16u1:m16u0. ;* ;* Number of words :14 + return ;* Number of cycles :153 + return ;* Low registers used :None ;* High registers used :7 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/ m16u1,m16u2, ;* m16u3,mcnt16u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def .def
mc16uL mc16uH mp16uL mp16uH m16u0 m16u1 m16u2 m16u3 mcnt16u
=r16 =r17 =r18 =r19 =r18 =r19 =r20 =r21 =r22
;multiplicand low byte ;multiplicand high byte ;multiplier low byte ;multiplier high byte ;result byte 0 (LSB) ;result byte 1 ;result byte 2 ;result byte 3 (MSB) ;loop counter
clr
m16u3
;clear 2 highest bytes of
;***** Code mpy16u: result clr ldi lsr ror m16u_1: add
m16u2 mcnt16u,16 mp16uH mp16uL
;init loop counter
brcc noad8 m16u2,mc16uL
;if bit 0 of multiplier set ;add multiplicand Low to byte 2 of
m16u3,mc16uH
;add multiplicand high to byte 3 of
noad8: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
dec brne ret
mcnt16u m16u_1
;decrement loop counter ;if not done, loop more
res adc res m16u3
multiplier High multiplier Low
; *************************************************************************** ;* ;* "mpy16s" - 16x16 Bit Signed Multiplication ;* ;* This subroutine multiplies signed the two 16-bit register variables ;* mp16sH:mp16sL and mc16sH:mc16sL. ;* The result is placed in m16s3:m16s2:m16s1:m16s0. ;* The routine is an implementation of Booth's algorithm. If all 32 bits ;* in the result are needed, avoid calling the routine with ;* -32768 ($8000) as multiplicand ;* ;* Number of words :16 + return ;* Number of cycles :210/226 (Min/Max) + return ;* Low registers used :None ;* High registers used :7 (mp16sL,mp16sH,mc16sL/m16s0,mc16sH/ m16s1, ;* m16s2,m16s3,mcnt16s) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def .def
mc16sL mc16sH mp16sL mp16sH m16s0 m16s1 m16s2 m16s3 mcnt16s
=r16 =r17 =r18 =r19 =r18 =r19 =r20 =r21 =r22
;multiplicand low byte ;multiplicand high byte ;multiplier low byte ;multiplier high byte ;result byte 0 (LSB) ;result byte 1 ;result byte 2 ;result byte 3 (MSB) ;loop counter
;***** Code mpy16s: sub ldi m16s_1: add
clr m16s3 m16s2,m16s2 mcnt16s,16 brcc m16s_2 m16s2,mc16sL
;clear result byte 3 ;clear result byte 2 and carry ;init loop counter ;if carry (previous bit) set ; add multiplicand Low to result
m16s3,mc16sH
;
byte 2 adc
add multiplicand High to
result byte 3 m16s_2: sub
sbrc mp16sL,0 m16s2,mc16sL ;
;if current bit set sub multiplicand Low from
result byte 2 sbrc sbc
mp16sL,0 m16s3,mc16sH
;if current bit set ; sub multiplicand High from
asr ror ror ror dec brne ret
m16s3 m16s2 m16s1 m16s0 mcnt16s m16s_1
;shift right result and multiplier
result byte 3
;decrement counter ;if not done, loop more
; *************************************************************************** ;* ;* "div8u" - 8/8 Bit Unsigned Division ;* ;* This subroutine divides the two register variables "dd8u" (dividend) and ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in ;* "drem8u". ;* ;* Number of words :14 ;* Number of cycles :97 ;* Low registers used :1 (drem8u) ;* High registers used :3 (dres8u/dd8u,dv8u,dcnt8u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def
drem8u dres8u dd8u dv8u dcnt8u
=r15 =r16 =r16 =r17 =r18
;remainder ;result ;dividend ;divisor ;loop counter
;***** Code div8u: ldi d8u_1: dec brne ret d8u_2:
sub drem8u,drem8u ;clear remainder and carry dcnt8u,9 ;init loop counter rol dd8u ;shift left dividend dcnt8u ;decrement counter d8u_2 ;if done ; return rol drem8u ;shift dividend into
remainder sub brcc add clc
drem8u,dv8u d8u_3 drem8u,dv8u
;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_3:
d8u_1 sec
;else
rjmp
d8u_1
result ;
set carry to be
shifted into result
; *************************************************************************** ;* ;* "div8s" - 8/8 Bit Signed Division ;* ;* This subroutine divides the two register variables "dd8s" (dividend) and ;* "dv8s" (divisor). The result is placed in "dres8s" and the remainder in ;* "drem8s". ;* ;* Number of words :27 ;* Number of cycles :107/108 ;* Low registers used :2 (d8s,drem8s) ;* High registers used :3 (dres8s/dd8s,dv8s,dcnt8s) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def
d8s drem8s dres8s dd8s dv8s dcnt8s
=r14 =r15 =r16 =r16 =r17 =r18
;sign register ;remainder ;result ;dividend ;divisor ;loop counter
mov
d8s,dd8s
;move dividend to sign
;***** Code div8s: register eor
;xor sign with divisor
dv8s,7 dv8s dd8s,7 dd8s drem8s,drem8s dcnt8s,9 rol dd8s dcnt8s d8s_2 d8s,7 dres8s
;if MSB of divisor set ; change sign of divisor ;if MSB of dividend set ; change sign of divisor ;clear remainder and carry ;init loop counter ;shift left dividend ;decrement counter ;if done ; if MSB of sign register set ; change sign of result
sbrc neg sbrc neg sub ldi d8s_1: dec brne sbrc neg
d8s,dv8s
ret d8s_2:
; rol
drem8s
return ;shift dividend into
remainder sub brcc add clc
drem8u,dv8s d8s_3 drem8u,dv8s
;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8s_3:
d8s_1 sec
;else
rjmp
d8s_1
result ;
set carry to be
shifted into result
; *************************************************************************** ;* ;* "div16u" - 16/16 Bit Unsigned Division ;* ;* This subroutine divides the two 16-bit numbers ;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor). ;* The result is placed in "dres16uH:dres16uL" and the remainder in ;* "drem16uH:drem16uL". ;* ;* Number of words :19 ;* Number of cycles :235/251 (Min/Max) ;* Low registers used :2 (drem16uL,drem16uH) ;* High registers used :5 (dres16uL/dd16uL,dres16uH/dd16uH, dv16uL,dv16uH, ;* dcnt16u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def .def
drem16uL=r14 drem16uH=r15 dres16uL=r16 dres16uH=r17 dd16uL =r16 dd16uH =r17 dv16uL =r18 dv16uH =r19 dcnt16u =r20
;***** Code div16u: sub
clr drem16uL ;clear remainder Low byte drem16uH,drem16uH;clear remainder High byte and
ldi d16u_1: rol dec brne ret d16u_2:
dcnt16u,17 rol dd16uL dd16uH dcnt16u d16u_2
carry ;init loop counter ;shift left dividend
;decrement counter ;if done ; return drem16uL ;shift dividend into
rol
remainder rol sub sbc brcc add adc clc
drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_3 drem16uL,dv16uL drem16uH,dv16uH
;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_3:
d16u_1 sec
rjmp
d16u_1
;else ;
set carry to be
shifted into result
; *************************************************************************** ;* ;* "div16s" - 16/16 Bit Signed Division ;* ;* This subroutine divides signed the two 16 bit numbers ;* "dd16sH:dd16sL" (dividend) and "dv16sH:dv16sL" (divisor). ;* The result is placed in "dres16sH:dres16sL" and the remainder in ;* "drem16sH:drem16sL". ;* ;* Number of words :45 ;* Number of cycles :252/268 (Min/Max) ;* Low registers used :3 (d16s,drem16sL,drem16sH) ;* High registers used :7 (dres16sL/dd16sL,dres16sH/dd16sH, dv16sL,dv16sH, ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def
d16s =r13 drem16sL=r14
;sign register ;remainder low
.def .def .def .def .def .def .def .def
drem16sH=r15 dres16sL=r16 dres16sH=r17 dd16sL =r16 dd16sH =r17 dv16sL =r18 dv16sH =r19 dcnt16s =r20
;remainder high byte ;result low byte ;result high byte ;dividend low byte ;dividend high byte ;divisor low byte ;divisor high byte ;loop counter
mov
;move dividend High to sign
byte
;***** Code div16s:
d16s,dd16sH
register eor sbrs rjmp com com subi sbci d16s_1: rjmp com com subi sbci d16s_2: sub
d16s,dv16sH
;xor divisor High with sign register
dd16sH,7 ;if MSB in dividend set d16s_1 dd16sH ; change sign of dividend dd16sL dd16sL,low(-1) dd16sL,high(-1) sbrs dv16sH,7 ;if MSB in divisor set d16s_2 dv16sH ; change sign of divisor dv16sL dv16sL,low(-1) dv16sL,high(-1) clr drem16sL ;clear remainder Low byte drem16sH,drem16sH;clear remainder High byte and
carry ldi d16s_3: rol dec brne sbrs rjmp com com subi sbci
dcnt16s,17
;init loop counter
d16s_4: ret d16s_5:
rol dd16sL ;shift left dividend dd16sH dcnt16s ;decrement counter d16s_5 ;if done d16s,7 ; if MSB in sign register set d16s_4 dres16sH ; change sign of result dres16sL dres16sL,low(-1) dres16sH,high(-1)
; rol
drem16sL
return ;shift dividend into
remainder rol sub sbc brcc add adc clc
drem16sH drem16sL,dv16sL drem16sH,dv16sH d16s_6 drem16sL,dv16sL drem16sH,dv16sH
;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16s_6:
d16s_3 sec
rjmp
d16s_3
;else ;
set carry to be
shifted into result
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct verification. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ;--------------------------------------------------------------;Include these lines for devices with SRAM ; ldi temp,low(RAMEND) ; out SPL,temp ; ldi temp,high(RAMEND) ; out SPH,temp ;init Stack Pointer ;--------------------------------------------------------------;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4) ldi ldi rcall
mc8u,250 mp8u,4 mpy8u
;result: m8uH:m8uL = $03e8 (1000)
;***** Multiply Two Signed 8-Bit Numbers (-99 * 88) ldi mc8s,-99 ldi mp8s,88 rcall mpy8s ;result: m8sH:m8sL = $ddf8 (-8712) ;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000) ldi mc16uL,low(5050) ldi mc16uH,high(5050) ldi mp16uL,low(10000) ldi mp16uH,high(10000) rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0 ;=030291a0 (50,500,000) ;***** Multiply Two Signed 16-Bit Numbers (-12345*(-4321)) ldi mc16sL,low(-12345) ldi mc16sH,high(-12345) ldi mp16sL,low(-4321) ldi mp16sH,high(-4321) rcall mpy16s ;result: m16s3:m16s2:m16s1:m16s0 ;=$032df219 (53,342,745) ;***** Divide Two Unsigned 8-Bit Numbers (100/3) ldi dd8u,100 ldi dv8u,3 rcall div8u ;result: $21 (33) ;remainder: $01 (1) ;***** Divide Two Signed 8-Bit Numbers (-110/-11) ldi dd8s,-110 ldi dv8s,-11 rcall div8s ;result: $0a (10) ;remainder $00 (0)
;***** Divide Two Unsigned 16-Bit Numbers (50,000/60,000) ldi dd16uL,low(50000) ldi dd16uH,high(50000) ldi dv16uL,low(60000) ldi dv16uH,high(60000) rcall div16u ;result: $0000 (0) ;remainder: $c350 (50,000)
;***** Divide Two Signed 16-Bit Numbers (-22,222/10) ldi dd16sL,low(-22222) ldi dd16sH,high(-22222) ldi dv16sL,low(10) ldi dv16sH,high(10) rcall div16s ;result: $f752 (-2222) ;remainder: $0002 (2) forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have http://avr-asm.tripod.com/avr200.html (1 of 2)1/20/2009 8:34:09 PM
MULTIPLY & DIVIDE (AVR 200)
different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr200.html (2 of 2)1/20/2009 8:34:09 PM
MULTIPLY & DIVIDE (AVR 200)
The AVR Assembler Site
FAST MULTIPLY & DIVIDE (AVR 200b) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202
MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16
A V R 2 0 0 b
************************
ASM MATH
MATH 32X
N O T E
Title: Version: Last updated: Target:
Multiply and Divide Routines 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This Application Note lists subroutines for the following Muliply/Divide applications. Routines are straight-line
implementations ;* optimized for speed: ;* ;* 8 x 8 = 16 bit unsigned ;* 16 x 16 = 32 bit unsigned ;* 8 / 8 = 8 + 8 bit unsigned ;* 16 / 16 = 16 + 16 bit unsigned ;* ; ***************************************************************************
MATH 202
.include "1200def.inc"
MATH 202 rjmp
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236
RESET
;reset handle
; *************************************************************************** ;* ;* "mpy8u" - 8x8 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two register variables mp8u and mc8u. ;* The result is placed in registers m8uH, m8uL ;* ;* Number of words :34 + return ;* Number of cycles :34 + return ;* Low registers used :None ;* High registers used :3 (mc8u,mp8u/m8uL,m8uH) ;* ;* Note: Result Low byte and the multiplier share the same register. ;* This causes the multiplier to be overwritten by the result. ;* ; ***************************************************************************
XMODEM REC ;***** Subroutine Register Variables
UART 304
.def .def .def .def
UART 305 UART 128 UART BUFF USB 232
mc8u mp8u m8uL m8uH
=r16 =r17 =r17 =r18
clr mp8u
m8uH
;multiplicand ;multiplier ;result Low byte ;result High byte
;***** Code
AVR ISP mpy8u: lsr
ISP 2313
;clear result High byte ;shift multiplier
ISP 1200 brcc add
AVR SPI I2C 300
I2C/TWI 128
noad80:
;rotate right result L byte and
brcc add
noad81 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
High byte noad81:
IRD 410
m8uH
;shift right result High
ror
m8uL
;rotate right result L byte and
brcc add
noad82 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
High byte
ADC 401 THERM 232
ror
byte
ADC 10B ADC 400
;shift right result High
m8uL
TEA ADC 128
m8uH
ror
DALLAS-1W
ETHNET 8019
ror
byte
I2C/TWI AT8
DALLAS CRC
;if carry set ; add multiplicand to result
High byte
I2C 302 I2C TWI26
noad80 m8uH,mc8u
noad82:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
brcc add
noad83 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
LCD HD44 LCD 2313 LCD44 2313 KBD 240
High byte noad83:
m8uL
;rotate right result L byte and
brcc add
noad84 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
High byte
BOOT MG8 BOOT DR8 ALM CLK
;shift right result High
ror
KBD PC/128 PS2 EMU
m8uH
byte
MUX 242 KBD PS2
ror
noad84:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
brcc add
noad85 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
CLOCK 8564 90 DAYS DELAYS CALL ID
High byte noad85:
m8uL
;rotate right result L byte and
brcc add
noad86 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
ENCODE
ATMEL CORP AVR BUTTERFLY
;shift right result High
ror
PWM 10K
STH-11
m8uH
byte
DTMF 314 PWM 6CH
ror
High byte noad86:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
brcc add
noad87 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
AVR BOOK High byte
noad87:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
multiplier ret
; *************************************************************************** ;* ;* "mpy16u" - 16x16 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two 16-bit register variables ;* mp16uH:mp16uL and mc16uH:mc16uL. ;* The result is placed in m16u3:m16u2:m16u1:m16u0. ;* ;* Number of words :105 + return ;* Number of cycles :105 + return ;* Low registers used :None ;* High registers used :6 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/ m16u1,m16u2, ;* m16u3) ;* ; *************************************************************************** ;***** Subroutine Register Variables
.def .def .def .def .def .def .def .def
mc16uL mc16uH mp16uL mp16uH m16u0 m16u1 m16u2 m16u3
=r16 =r17 =r18 =r19 =r18 =r19 =r20 =r21
;multiplicand low byte ;multiplicand high byte ;multiplier low byte ;multiplier high byte ;result byte 0 (LSB) ;result byte 1 ;result byte 2 ;result byte 3 (MSB)
clr
m16u3
;clear 2 highest bytes of
;***** Code mpy16u: result clr lsr ror
m16u2 mp16uH mp16uL
;rotate multiplier Low ;rotate multiplier High
brcc add
noadd0 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd0: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd1 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd1: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd2 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd2: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd3 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd3: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd4 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd4: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd5 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd5: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd6 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd6: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd7 m16u2,mc16uL
;if carry sett ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd7: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd8 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd8: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd9 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd9: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad10 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad10: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad11 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad11: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad12 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad12: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad13 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad13: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad14 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad14: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad15 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad15: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High ;rotate result byte 0 and
multiplier Low ret
; *************************************************************************** ;* ;* "div8u" - 8/8 Bit Unsigned Division ;* ;* This subroutine divides the two register variables "dd8u" (dividend) and ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in ;* "drem8u". ;* ;* Number of words :66 + return ;* Number of cycles :50/58/66 (Min/Avg/Max) + return ;* Low registers used :1 (drem8u) ;* High registers used :2 (dres8u/dd8u,dv8u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def
drem8u dres8u dd8u dv8u
=r15 =r16 =r16 =r17
;remainder ;result ;dividend ;divisor
sub
drem8u,drem8u
;clear remainder and carry
;***** Code div8u: rol rol sub brcc add clc
dd8u drem8u drem8u,dv8u d8u_1 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_1:
d8u_2 sec
;else
d8u_2: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_3 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_3:
d8u_4 sec
;else
d8u_4: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_5 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_5:
d8u_6 sec
;else
d8u_6: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_7 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_7:
d8u_8 sec
;else
d8u_8: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_9 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_9:
d8u_10 sec
;else
d8u_10: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_11 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_11:
d8u_12 sec
;else
d8u_12: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_13 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_13:
d8u_14 sec
;else
d8u_14: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_15 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_15:
d8u_16 sec
;else
d8u_16: ret
rol
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result dd8u
;shift left dividend
; *************************************************************************** ;* ;* "div16u" - 16/16 Bit Unsigned Division ;* ;* This subroutine divides the two 16-bit numbers ;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor). ;* The result is placed in "dres16uH:dres16uL" and the remainder in ;* "drem16uH:drem16uL". ;* ;* Number of words :196 + return ;* Number of cycles :148/173/196 (Min/Avg/Max) ;* Low registers used :2 (drem16uL,drem16uH) ;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH, dv16uL,dv16uH) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def
drem16uL=r14 drem16uH=r15 dres16uL=r16 dres16uH=r17 dd16uL =r16 dd16uH =r17 dv16uL =r18 dv16uH =r19
;***** Code div16u: sub
clr drem16uL ;clear remainder Low byte drem16uH,drem16uH;clear remainder High byte and
carry rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_1 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_1:
d16u_2 sec
;else
d16u_2: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_3 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_3:
d16u_4 sec
d16u_4: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_5 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_5:
d16u_6 sec
d16u_6: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_7 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_7:
d16u_8 sec
d16u_8: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_9 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_9:
d16u_10 sec
;else
d16u_10:rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_11 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend
;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;else ;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;else ;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;else ;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;
set carry to be
shifted into result
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_12 d16u_11:sec
;else ; set carry to be shifted into
d16u_12:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_13 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_14 d16u_13:sec
;else ; set carry to be shifted into
d16u_14:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_15 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_16 d16u_15:sec
;else ; set carry to be shifted into
d16u_16:rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_17 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend
rjmp d16u_17:
d16u_18 sec
;else
d16u_18:rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_19 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend
result
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;
set carry to be
shifted into result
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_20 d16u_19:sec
;else ; set carry to be shifted into
d16u_20:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_21 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_22 d16u_21:sec
;else ; set carry to be shifted into
d16u_22:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_23 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_24 d16u_23:sec
;else ; set carry to be shifted into
d16u_24:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_25 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_26 d16u_25:sec
;else ; set carry to be shifted into
d16u_26:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_27 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_28 d16u_27:sec
;else ; set carry to be shifted into
d16u_28:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_29 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_30 d16u_29:sec
;else ; set carry to be shifted into
d16u_30:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_31 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_32 d16u_31:sec
;else ; set carry to be shifted into
d16u_32:rol dd16uL rol dd16uH ret
;shift left dividend
result
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct verification. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ;--------------------------------------------------------------;Include these lines for devices with SRAM ; ldi temp,low(RAMEND) ; out SPL,temp ; ldi temp,high(RAMEND) ; out SPH,temp ;init Stack Pointer ;--------------------------------------------------------------;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4) ldi ldi rcall
mc8u,250 mp8u,4 mpy8u
;result: m8uH:m8uL = $03e8 (1000)
;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000) ldi mc16uL,low(5050) ldi mc16uH,high(5050) ldi mp16uL,low(10000) ldi mp16uH,high(10000) rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0 ;=$030291a0 (50,500,000) ;***** Divide Two Unsigned 8-Bit Numbers (100/3) ldi dd8u,100 ldi dv8u,3 rcall div8u ;result: $21 (33) ;remainder: $01 (1) ;***** Divide Two Unsigned 16-Bit Numbers (50,000/24,995) ldi dd16uL,low(50000) ldi dd16uH,high(50000) ldi dv16uL,low(24995) ldi dv16uH,high(24995) rcall div16u ;result: $0002 (2) ;remainder: $000a (10) forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The http://avr-asm.tripod.com/avr200b.html (1 of 2)1/20/2009 8:35:39 PM
MULTIPLY & DIVIDE (AVR 200)
AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr200b.html (2 of 2)1/20/2009 8:35:39 PM
16 BIT MULTIPLY (AVR 201)
The AVR Assembler Site
16 BIT MULTIPLY (AVR 201) HOME RETRO_DAN ;
ASM FORUM ASM MATH TUTORIAL #1
;* ;* Title ;* ;* ;* ;* ;* ;* ;* ;*
MATH 201 MATH 202 MATH 32X
Support email
: [email protected]
: 5 Apr, 1999 : ATmega83/161/163
DESCRIPTION This application note shows a number of examples of
;*
16bit multiplication using hardware multiplier.
;*
funtions headers for details. The functions
;* ;* ;*
are : mul16x16_16
- Multiply of two 16bits numbers
;*
mul16x16_32
- Unsigned multiply of two 16bits
muls16x16_32
result. - Signed multiply of two 16bits
mac16x16_32
result. - Signed multiply accumulate of two
fmuls16x16_32
with a 32bits result. - Signed fractional multiply of two
fmac16x16_32
with 32bits result. - Signed fractional multiply
;* ;* numbers with 32bits ;* ;* 16bits numbers ;* ;*
FFT7 COPY 102
: V1.0
numbers with 32bits
HX2ASC AVG8 222
Version Last updated Target
with 16bits result.
DEC ASCII INT ASCII
: 16bit multiply routines using
included in this file
SQRT16
MATH 202
A V R 2 0 1
Refer to each of the
FLOAT 128
MATH 202
N O T E
how to implement
DIV 24 24 DIV 3216
1:34 pm
hardware multiplier
MATH 200b
DIV16 XX
21 Jul 99
***************************
MATH 200
MATH YX
MWL
;**** A P P L I C A T I O N
TUTORIAL #2 TUTORIAL #3
Last change:
16bits numbers ;* ;*
LPM 108 EPROM 100
accumulate of two 16bits
SER EPROM
;* numbers with a 32bits result. ;* ; ******************************************************************************
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
; ****************************************************************************** ;* ;* FUNCTION ;* mul16x16_16 ;* DECRIPTION ;* Multiply of two 16bits numbers with 16bits result. ;* USAGE ;* r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 9 + ret ;* Words : 6 + ret ;* Register usage: r0, r1 and r16 to r23 (8 registers) ;* NOTE ;* Full orthogonality i.e. any register pair can be used as long as ;* the result and the two operands does not share register pairs. ;* The routine is non-destructive to the operands. ;* ; ******************************************************************************
I2C/TWI 128
mul16x16_16: mul r22, r20 movw r17:r16, r1:r0 mul r23, r20 add r17, r0 mul r21, r22 add r17, r0 ret
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA
; al * bl ; ah * bl ; bh * al
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
; ****************************************************************************** ;* ;* FUNCTION ;* mul16x16_32 ;* DECRIPTION ;* Unsigned multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 17 + ret ;* Words : 13 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* NOTE ;* Full orthogonality i.e. any register pair can be used as long as ;* the 32bit result and the two operands does not share register pairs. ;* The routine is non-destructive to the operands. ;* ; ******************************************************************************
90 DAYS
mul16x16_32: clr r2 mul r23, r21 movw r19:r18, r1:r0 mul r22, r20 movw r17:r16, r1:r0 mul r23, r20 add r17, r0 adc r18, r1 adc r19, r2 mul r21, r22 add r17, r0 adc r18, r1 adc r19, r2 ret
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
; ah * bh ; al * bl ; ah * bl
; bh * al
AVR BOOK ; ****************************************************************************** ;* ;* FUNCTION ;* muls16x16_32 ;* DECRIPTION ;* Signed multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 19 + ret ;* Words : 15 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* NOTE ;* The routine is non-destructive to the operands. ;* ; ****************************************************************************** muls16x16_32: clr r2 muls r23, r21
; (signed)ah *
(signed)bh movw mul movw mulsu sbc add adc adc mulsu sbc add adc adc ret
r19:r18, r1:r0 r22, r20 r17:r16, r1:r0 r23, r20 r19, r2 r17, r0 r18, r1 r19, r2 r21, r22 r19, r2 r17, r0 r18, r1 r19, r2
; al * bl ; (signed)ah * bl
; (signed)bh * al
; ****************************************************************************** ;* ;* FUNCTION ;* mac16x16_32 ;* DECRIPTION ;* Signed multiply accumulate of two 16bits numbers with ;* a 32bits result. ;* USAGE ;* r19:r18:r17:r16 += r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 23 + ret ;* Words : 19 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* ; ****************************************************************************** mac16x16_32: clr r2 muls
r23, r21
; (signed)ah *
add adc
r18, r0 r19, r1
mul add adc adc adc
r22, r16, r17, r18, r19,
r20 r0 r1 r2 r2
; al * bl
mulsu sbc add adc adc
r23, r19, r17, r18, r19,
r20 r2 r0 r1 r2
; (signed)ah * bl
mulsu sbc add adc adc
r21, r19, r17, r18, r19,
r22 r2 r0 r1 r2
; (signed)bh * al
(signed)bh
ret mac16x16_32_method_B:
; uses two
temporary registers ; (r4,r5), but reduces cycles/words ; by 1 clr
r2
muls
r23, r21
movw
r5:r4,r1:r0
mul
r22, r20
add adc adc adc
r16, r17, r18, r19,
r0 r1 r4 r5
mulsu sbc add adc adc
r23, r19, r17, r18, r19,
r20 r2 r0 r1 r2
; (signed)ah * bl
mulsu sbc add adc adc
r21, r19, r17, r18, r19,
r22 r2 r0 r1 r2
; (signed)bh * al
; (signed)ah *
(signed)bh
; al * bl
ret
; ****************************************************************************** ;* ;* FUNCTION ;* fmuls16x16_32 ;* DECRIPTION ;* Signed fractional multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1 ;* STATISTICS ;* Cycles : 20 + ret ;* Words : 16 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* NOTE ;* The routine is non-destructive to the operands. ;* ; ****************************************************************************** fmuls16x16_32: clr r2 fmuls r23, r21
; ( (signed)ah *
(signed)bh ) << 1 movw fmul adc movw fmulsu
r19:r18, r1:r0 r22, r20 r18, r2 r17:r16, r1:r0 r23, r20
sbc add adc adc fmulsu
r19, r17, r18, r19, r21,
r2 r0 r1 r2 r22
sbc add adc adc ret
r19, r17, r18, r19,
r2 r0 r1 r2
; ( al * bl ) << 1
; ( (signed)ah *
bl ) << 1
; ( (signed)bh *
al ) << 1
; ****************************************************************************** ;* ;* FUNCTION ;* fmac16x16_32 ;* DECRIPTION ;* Signed fractional multiply accumulate of two 16bits numbers with ;* a 32bits result. ;* USAGE ;* r19:r18:r17:r16 += (r23:r22 * r21:r20) << 1 ;* STATISTICS ;* Cycles : 25 + ret ;* Words : 21 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* ; ****************************************************************************** fmac16x16_32: clr r2 fmuls
r23, r21
add adc
r18, r0 r19, r1
fmul adc adc add adc adc adc
r22, r18, r19, r16, r17, r18, r19,
fmulsu
r23, r20
sbc add adc adc
r19, r17, r18, r19,
fmulsu
r21, r22
sbc add adc adc
r19, r17, r18, r19,
; ( (signed)ah *
(signed)bh ) << 1
r20 r2 r2 r0 r1 r2 r2
; ( al * bl ) << 1
; ( (signed)ah *
bl ) << 1 r2 r0 r1 r2 ; ( (signed)bh *
al ) << 1 r2 r0 r1 r2
ret fmac16x16_32_method_B:
; uses two
temporary registers ; (r4,r5), but reduces cycles/words ; by 2 clr
r2
fmuls
r23, r21
; ( (signed)ah *
movw fmul adc
r5:r4,r1:r0 r22, r20 r4, r2
; ( al * bl ) << 1
add adc adc adc
r16, r17, r18, r19,
fmulsu
r23, r20
; ( (signed)ah *
sbc add adc adc fmulsu
r19, r17, r18, r19, r21,
r2 r0 r1 r2 r22
; ( (signed)bh *
sbc add adc adc
r19, r17, r18, r19,
r2 r0 r1 r2
(signed)bh ) << 1
r0 r1 r4 r5
bl ) << 1
al ) << 1
ret
;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even http://avr-asm.tripod.com/avr201.html (1 of 2)1/20/2009 8:36:15 PM
16 BIT MULTIPLY (AVR 201)
after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr201.html (2 of 2)1/20/2009 8:36:15 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
16 BIT MATH (AVR 202) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202
A V R 2 0 2
************************
ASM MATH
MATH 202
N O T E
Title: Version: Last updated: Target:
16-bit Arithmetics 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This application note lists applications for the
following ;* Add/Subtract/Compare operations: ;* ;* "add16" ADD 16+16 ;* "adddi16" ADD 16+Immediate(16) ;* "sub16" SUB 16-16 ;* "subi16" SUB 16-Immediate(16) ;* "cp16" COMPARE 16/16 ;* "cpi16" COMPARE 16/Immediate ;* "neg16" NEGATION 16 ;* ; ***************************************************************************
MATH 202 DEC ASCII INT ASCII
r16,0x12
;Set up some registers to
ldi ldi
r17,0x34 r18,0x56
;the subroutines below. ;All expected results are
ldi
r19,0x78
;comments
show usage of
HX2ASC AVG8 222
.cseg ldi
presented as
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
; *************************************************************************** ;* ;* "add16" - Adding 16-bit registers ;* ;* This example adds the two pairs of register variables (add1l,add1h) ;* and (add2l,add2h) The result is placed in (add1l, add1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
AVR ISP
;**** Register Variables .def add1l = r16 .def add1h = r17 .def add2l = r18 .def add2h = r19
ISP 2313 ISP 1200 AVR SPI I2C 300
;***** Code add16: add
I2C 302 I2C TWI26 I2C/TWI 128
add1l, add2l
;Add low
bytes adc
add1h, add2h
;Add high bytes
with carry ;Expected result is 0xAC68
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;* ;* "addi16" - Adding 16-bit register with immediate ;* ;* This example adds a register variable (addi1l, addi1h) with an ;* immediate 16-bit number defined with .equstatement. The result is ;* placed in (addi1l, addi1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
PS2 EMU
;***** Register Variables .def addi1l = r16 .def addi1h = r17
BOOT MG8 BOOT DR8 ALM CLK
;***** Immediate 16-bit number .equ addi2 = 0x1234
CLOCK 8564 90 DAYS
;***** Code addi16: subi
DELAYS CALL ID DTMF 314
add1l, low(-addi2)
;Add low
byte ( x -(-y)) = x + y sbci
add1h, high(-addi2)
;Add high byte with
carry ;Expected result is 0xBE9C
PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* "sub16" - Subtracting 16-bit registers ;* ;* This example subtracts two pairs of register variables (sub1l,sub1h) ;* from (sub2l, sub2h) The result is stored in registers sub1l, sub1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The result and "sub1" share the same register. This causes "sub1" ;* to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def sub1l = r16 .def sub1h = r17 .def sub2l = r18 .def sub2h = r19 ;***** Code sub16: sub
sub1l,sub2l
;Subtract
low bytes sbc
sub1h,sub2h
;Add high byte with
carry ;Expected result is 0x4646
; *************************************************************************** ;* ;* "subi16" - Subtracting immediate 16-bit number from a 16-bit register ;* ;* This example subtracts the immediate 16-bit number subi2 from the ;* 16-bit register (subi1l,subi1h) The result is placed in registers ;* subi1l, subi1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The result and "subi1" share the same register. This causes ;* "subi1" to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def subi1l = r16 .def subi1h = r17 ;***** Immediate 16-bit number .equ subi2 = 0x1234 ;***** Code subi16: subi
subi1l,low(subi2)
;Subtract
low bytes sbci
subi1h,high(subi2)
;Subtract high byte
with carry ;Expected result is 0x3412
; *************************************************************************** ;* ;* "cp16" - Comparing two 16-bit numbers ;* ;* This example compares the register pairs (cp1l,cp1h) with the register ;* pairs (cp2l,cp2h) If they are equal the zero flag is set(one) ;* otherwise it is cleared(zero) ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The contents of "cp1" will be overwritten. ;* ; *************************************************************************** ;***** Register Variables .def cp1l = r16 .def cp1h = r17 .def cp2l = r18 .def cp2h = r19 ;***** Code cp16: cp cp1l,cp2l ;Compare low byte cpc cp1h,cp2h ;Compare high byte with carry from ;previous operation ncp16: ;Expected result is Z=0
; *************************************************************************** ;* ;* "cpi16" - Comparing 16-bit register with 16-bit immediate ;* ;* This example compares the register pairs (cpi1l, cpi1h) with the value ;* cpi2. If they are equal the zero flag is set(one), otherwise it is ;* cleared(zero). This is enabled by the AVR's zero propagation. Carry is ;* also set if the result is negative. This means that all conditional ;* branch instructions can be used after the comparison. ;* ;* Number of words :3 ;* Number of cycles :3 ;* Low registers used :None ;* High registers used :3 ;* ;* ; *************************************************************************** ;***** Register Variables .def cp1l =r16 .def cp1h =r17 .def c_tmp=r18 .equ cp2 = 0x3412
;Immediate to compare with
;***** Code cpi16: cpi cp1l,low(cp2) ;Compare low byte ldi c_tmp,high(cp2) ; cpc cp1h,c_tmp ;Compare high byte ;Expected result is Z=1, C=
; *************************************************************************** ;* ;* "neg16" - Negating 16-bit register ;* ;* This example negates the register pair (ng1l,ng1h) The result will ;* overwrite the register pair. ;* ;* Number of words :4 ;* Number of cycles :4 ;* Low registers used :None ;* High registers used :2 ;* ; *************************************************************************** ;***** Register Variables .def ng1l = r16 .def ng1h = r17 ;***** Code ng16: com ng1l
;Invert low byte
;
Calculated by com
ng1h
;Invert high byte
;
subi
ng1l,low(-1)
;Add 0x0001, low byte
;
sbci
ng1h,high(-1)
;Add high byte
;
incverting all bits then adding one (0x0001) ;Expected result is 0xCBEE
; *************************************************************************** ;* ;* End of examples. ;* ; ***************************************************************************
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, http://avr-asm.tripod.com/avr202.html (1 of 2)1/20/2009 8:37:09 PM
16 BIT MATH (AVR 202)
the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr202.html (2 of 2)1/20/2009 8:37:09 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
32 BIT MATH (AVR XXX) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N
TUTORIAL #3 MATH 200 MATH 200b
MATH 202 MATH 32X
FLOAT 128
MATH 202 DEC ASCII
;*
;* INTERPRETATION ;* This package of assembler subprograms is developed for integer arithmetic ;* with tracing of sign bit in 32 bits calculations and data reloads. ;* It is based on microcontroller register file to the maximum. ;* In real users projects available abundant digit capacity allows to avoid ;* overflow and reduces inaccuracy of rounding errors in chain calculations. ;* Included macro definitions will increase readability
AVG8 222
AVR software model
;* at bit by bit and multibyte data operations inside ;* ;* DESCRIPTION ;* This Application Note lists: ;* i) Math32 subroutines for the following: ;* Add/Subtract/Multiply/Divide/Complement 32 bits
FFT7 COPY 102 LPM 108 operands,
;* ;* ;* ;* ;*
SER EPROM DFLASH AT45 FLASH CARD
;* iii) useful general macroinstructions for the AVR 8Bit RISC family
CRC 236
UART 304
UART BUFF USB 232
I2C/TWI AT8 DALLAS-1W
DELAYS CALL ID
;* ;* ;* ;* ;*
"BCD2bin" "BCD3bin" "Bin2BCD" "Bin3BCD" "Bin4BCD"
BCD to BCD to Binary Binary Binary
Rd16 Rd24 Rd24 Rd32 Rd40
;* ;* ;* ;* ;* ;*
"MathMem" "MathLoad" "MathSave"
Init Data Memory Load Registers Store Registers
Binary 16 Binary 24 16 to BCD 24 to BCD 32 to BCD
= = = = =
Rd24|Rr24 Rd32|Rr32 Rd16|Rr16 Rd24|Rr24 Rd32|
(MA) = 0x00|0xff Rd32|Rr32 = (MA) (MA) = Rd32|Rd64
Rd64: destination registers (8) in the register file Rd32: destination (and source) registers (4) in the
so Rd64=r20:r27, Rd32=r20:r23, Rd24=r20:r22, Rd40=r20:r24, Rr32=r16:r19, Rr24=r16:r18, Rr16=r16:
c o
;* "ADD32" ;* "SUB32" ;* "MUL32"
6 16 24
4|5 6|15 460|556
Size of Add32sign Size of Sub32sign Size of Mul32b, based on
;* "DIV32"
28
528|688
Size of Div32b, based on
;* "COM32" ;* "NEG32" ;* "BCD2bin"
5 9 26
4|4 8|8 86|89
Part of Sub32 Part of Sub32 Equivalent of AVR204, but
;* "BCD3bin"
43
38|402
Different from BCD2bin
;* "Bin2BCD"
22
19|177
Equivalent of AVR204, but
;* "Bin3BCD"
21
36|366
In the form of preamble for
;* "Bin3BCD"
40
36|333
All-sufficient expansion of
;* "Bin4BCD"
37
515|671
Based on AVR204 16-bit Bin
;* "Bin4BCD"
48
874|878
All-sufficient transform
;* "MathMem"
10
7|645
;* "MathLoad"
15
41|46
Size and max cycle for Rr32
;* "MathSave"
14
13|78
Size and max cycle for Rd64
AVR200 16x16 unsigned AVR200 16/16 unsigned
smaller & quicker translation algorithm smaller & much faster Bin2BCD Bin2BCD to BCD conversion instead of pre-Bin4BCD cycle for 128 bytes
PWM 10K
load
ENCODE
AVR BUTTERFLY
Rd32 =
m m e n t s
PWM 6CH
ATMEL CORP
Two's Complement
;* ;* Number of words & cycles (Min|Max)
DTMF 314
STH-11
;* "NEG32"
r17, MA=0:511
CLOCK 8564 90 DAYS
Rd32 =
;*
BOOT MG8
ALM CLK
One's Complement
;*
KBD PS2
BOOT DR8
;* "COM32"
Rd16=r20:r21,
MUX 242
PS2 EMU
Rd32 = Rd32 /
bytes of data space,
LCD 2313
KBD PC/128
Divide Unsigned
;* Note: Math32 use high registers, r0 and lower 512
LCD HD44
KBD 240
;* "DIV32"
memory (SRAM)
THERM 232
LCD44 2313
Rd64 = Rd32 *
;* Rr32: source registers (4) in the register file ;* (MA): address for access to variable in the internal
ADC 10B
IRD 410
Multiply Unsigned
register file
ETHNET 8019
ADC 401
;* "MUL32"
Rr32 || hwrd(Rr32)&Rd16
I2C/TWI 128
ADC 400
Rd32 = Rd32 -
0x00000000 - Rd32
I2C TWI26
ADC 128
Subtract without Carry
0xffffffff - Rd32
I2C 300
TEA
;* "SUB32"
Rr32 (Rd64)
AVR SPI
DALLAS CRC
Rd32 = Rd32 +
Rr32
ISP 1200
I2C 302
Add without Carry
Rr32
AVR ISP ISP 2313
;* ;* "ADD32" Rr32
UART 305 UART 128
Binary 16 & 24 bits operand to/back BCD conversion, Binary 32 bits operand to BCD conversion, Initialization of data memory on a pattern, Load/Store group of registers from/to data space; ii) macro definitions call mathematical and data
transfer subroutines;
VFX MEM
XMODEM REC
This Application Note absolutely
free in use anybody
HX2ASC
SORT 220
(C) 1999-2003 Andre Birua
(mailto:[email protected])
of assembler source
VFX SMIL
(C) ATMEL Corporation (mailto:
;* Originator:
INT ASCII
EPROM 100
Math32 2.3 2003.09.15 1999.10.25 AT90S8515 (as well as
Project: Version: Last updated: Create Date: Target MCU:
[email protected])
SQRT16 MATH 202
;* ;* ;* ;* ;* ;*
DIV 24 24 DIV 3216
32-bit Arithmetic Routines with
others AVR uC)
MATH YX DIV16 XX
;* ;* Title: Macrolibrary
TUTORIAL #2
MATH 201
A V R ? ? ?
************************
ASM MATH TUTORIAL #1
N O T E
Size of MathMemLimit, max
save ;* In total:
350 words
Usually +7 cycles: rcall &
ret ;* ;* All routines are Code Size` optimized implementations and debugged with ;* macrocode for AVR macro assembler version 1.30 (Jan
AVR BOOK 27 1999 01:30:00) &
;*
AVR32 macro assembler version 1.30 (Sep
8
1999 01:30:00). ;*
However, AVR32 macro assembler version 1.54 (Nov
14 2001 14:05:48) & ;*
AVR32 macro assembler version 1.56 (May
6
2002 14:54:01) ;* generate dummy warnings: Register already defined by the .DEF directive ;* (command option for disable this kind of warning as yet is absent...) ;* CheckIt with AVR Studio ! ;* NOTE ;* ` Bin4BCD transformations has partial loop optimization for speed-up ;* While using Math32, it is important to consider the allocation of the ;* microcontroller resources available for the program. It is required: ;* - to use r0,r16..r31 with Math32; ;* - to allocate variables used in calculation in the bottom of the memory; ;* - to use T flag as a sign bit (input, output and temporary), ;*
if you need to operate negative numbers or up-down
overflow error ;* ;* VERSION ;* 1.0 Original version (in use starting with 1999.12.22) ;* 1.1 Fixed precedence bugs if macroparameter is an assembler expression ;* 1.2 Modify CBF & SBF & IBF macrocalls ;* 1.3 Full modification mathematical and data transfer macronotation ;* 1.4 Optimaze for speed and code size Mul32 & Div32 & BCD2bin & Bin2BCD ;* 2.0 Version for publication (added description, note and demo sections) ;* 2.1 Updated Bin2BCD, added Bin4BCD conversion & XCH macrocall ;* 2.2 Added functionally closed modifications of Bin3&4BCD translation ;* 2.3 Added BCD3bin conversion, normalize the comment of Bin3&4BCD ;* ;* DEMO ;* section below is a sample of macrocalls and not an ordinary Math32 usage ;* ; *************************************************************************** .include "8515def.inc" .listmac
;split Toggle_mode
at AVR
Studio .cseg
;press Step_Over
etceteras of rjmp
Demo
;trace Registers
and
Memory ;Words *** general macrocode for the AVR 8-Bit RISC microcontroller *** ;2 "CLF" ;2 "SEF" ;2 "CBF"
CLear bit Flag in register via T flag SEt bit Flag in register via T flag Clear Bit(s) Flag(s) in register via
;2 "SBF"
Set Bit(s) Flag(s) in register via temporary
;2 "IBF"
Invert Bit(s) Flag(s) in register via
temporary register register temporary register ;2 "OUTI" OUT port Immediate via temporary register ;4 "OUTIW" OUT port Immediate Word via temporary register ;2 "OUTW" ;2 "INW" ;3 "XCH"
OUT port Word from register pair IN port Word to register pair data eXCHange between a two registers as
;2 "MVW" ;2 "MVI" ;4 "MOVS"
MoVe register pair as Word MoVe temporary register loaded Immediate MOVe direct in data Space via temporary
exclusive OR only
register ;8 "MOVSW" MOVe direct in data Space Word via temporary register ;3 "STSI"
STore direct to data Space Immediate via
temporary register ;4 "STSIW" STore direct to data Space Immediate Word via temporary register ;4 "LDSW"
LoaD direct from data Space Word to register
;4 "STSW"
STore direct to data Space Word from
;2 "LDIW" ;2 "LDDW"
LoaD Immediate Word to register pair LoaD indirect with Displacement from data
;2 "STDW"
STore indirect with Displacement to data
pair register pair
space Word to register pair space Word from register pair ;2 "PUSHW" PUSH register pair (Word) on stack ;2 "POPW" POP register pair (Word) from stack .macro CLF ; Register,Bit# clt bld @0,@1 .endmacro .macro SEF ; Register,Bit# set bld @0,@1 .endmacro .macro CBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][, Bit#][,Bit#][,Bit#][,Bit#][,Bit#] ldi @1,~(exp2(@2)|(-@3-1<0)*exp2(@3-0)| (-@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@81<0)*exp2(@8-0)|(-@9-1<0)*exp2(@9-0)) and @0,@1 .endmacro .macro SBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][, Bit#][,Bit#][,Bit#][,Bit#][,Bit#] ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0) *exp2(@8-0)|(-@9-1<0)*exp2(@9-0) or @0,@1 .endmacro .macro IBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][, Bit#][,Bit#][,Bit#][,Bit#][,Bit#] ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0) *exp2(@8-0)|(-@9-1<0)*exp2(@9-0) eor @0,@1 .endmacro .macro OUTI ; Port,RegisterH,ConstantB ldi @1,@2 out @0,@1 .endmacro .macro OUTIW ; PortHL,RegisterH,ConstantW ldi @1,high(@2) out @0h,@1 ldi @1,low(@2) out @0l,@1 .endmacro .macro OUTW ; PortHL,RegisterHL out @0h,@1h out @0l,@1l .endmacro .macro INW ; RegisterHL,PortHL in @0l,@1l in @0h,@1h .endmacro .macro XCH ; Register,Register eor @0,@1 eor @1,@0 eor @0,@1 .endmacro .macro MVW ; RegisterHL,RegisterHL mov @0h,@1h mov @0l,@1l .endmacro .macro MVI ; RegisterL,RegisterH,ConstantB ldi @1,@2 mov @0,@1 .endmacro .macro MOVS ; Address,Register,Address lds @1,@2 sts @0,@1 .endmacro .macro MOVSW ; Address,Register,Address lds @1,@2 sts @0,@1 lds @1,(@2)+1 sts (@0)+1,@1 .endmacro .macro STSI ; Address,RegisterH,ConstantB ldi @1,@2 sts @0,@1 .endmacro .macro STSIW ; Address,RegisterH,ConstantW ldi @1,low(@2) sts @0,@1 ldi @1,high(@2) sts (@0)+1,@1 .endmacro .macro LDSW ; RegisterHL,Address lds @0l,@1 lds @0h,(@1)+1 .endmacro .macro STSW ; Address,RegisterHL sts (@0)+1,@1h sts @0,@1l .endmacro .macro LDIW ; RegisterHL,ConstantW ldi @0l,low(@1) ldi @0h,high(@1) .endmacro .macro LDDW ; RegisterHL,RegisterPair+Displacement ldd @0l,@1 ldd @0h,@1+1 .endmacro .macro STDW ; RegisterPair+Displacement,RegisterHL std @0+1,@1h std @0,@1l .endmacro .macro PUSHW ; RegisterHL push @0l push @0h .endmacro .macro POPW ; RegisterHL pop @0h pop @0l .endmacro ;Words ***** mathematical and data transfer macrocalls ***** ;3 "INITMEM" INITialize math data space (MEMory variable) in 0|0xff ;3 "MATHR16" load from MATH data space to Registers r16, r17,r18,r19 ;3 "MATHR20" load from MATH data space to Registers r20, r21,r22,r23 ;3 "OPERAND" load registers as mathematical OPERAND from math data space ;3 "RESULT2" store registers as mathematical RESULT to math data space (call) ;3 "RESULT3" store registers as mathematical RESULT to math data space (jump) ;1 "CNST16B" load immediate CoNSTant to r16 as Byte ;2 "CNST16W" load immediate CoNSTant to r16,r17 as Word ;3 "CNST16T" load immediate CoNSTant to r16,r17,r18 as Three bytes ;4 "CONST16" load immediate CONSTant to r16,r17,r18,r19 as double word ;4 "CONST20" load immediate CONSTant to r20,r21,r22,r23 as double word .macro INITMEM ; Address[,Counter(1-128)[,0|1|limit]] ldi ZL,@0 ldi ZH,@1-1<<1|high(@0)&1 rcall MathMem@2 .endmacro .macro MATHR16 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
R16MathLoad
.endmacro .macro MATHR20 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
R20MathLoad
.endmacro .macro OPERAND ; Address[,[Bitmap][,r16|r20]] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
@2MathLoad
.endmacro .macro RESULT2 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f) .endmacro .macro RESULT3 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rjmp
MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f) .endmacro .macro CNST16B ; ldi .endmacro .macro CNST16W ; ldi ldi .endmacro .macro CNST16T ; ldi ldi ldi .endmacro .macro CONST16 ; ldi ldi ldi ldi .endmacro .macro CONST20 ; ldi ldi ldi ldi .endmacro
ConstantB (8 bits) r16,byte1(@0) ConstantW (16 bits) r16,byte1(@0) r17,byte2(@0) ConstantT (24 bits) r16,byte1(@0) r17,byte2(@0) r18,byte3(@0) ConstantD (32 bits) r16,byte1(@0) r17,byte2(@0) r18,byte3(@0) r19,byte4(@0) ConstantD (32 bits) r20,byte1(@0) r21,byte2(@0) r22,byte3(@0) r23,byte4(@0)
; *************************************************************************** ;# # # # # # # # # Assign Math32 Symbol and Notation # # # # # # # # # ; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ;* ;* Add32[sign], Sub32[sign], Mul32[b|w|t], Div32[b|w| t] : ;* operand1 operand2 result ;* r20r21r22r23 +|-|*|/ r16r17r18r19 = r20r21r22r23[r24r25r26r27] ;* ;* Com32, Neg32 : Bin2BCD20, BCD2bin20 : ;* operand result operand result ;* r20r21r22r23 >>> r20r21r22r23 r20r21[r22] >>> r20r21[r22] ;* ;* BCD3bin, Bin3BCD, Bin4BCD : Bin2BCD16, BCD2bin16 : ;* operand result operand result ;* r16...r23 >>> r20r21r22[r23[r24]] r16r17 [r18] >>> r20r21[r22] ;* ; *************************************************************************** .set ObXXXX=0b1111 ;default load & store memory variable bitmap upon ;little-endian format of numbers, i.e. abs.address(LSB) < abs.address(MSB) ; *************************************************************************** ;* ;* Initialize Memory in Math Data Space ;* ;* First 512+127 bytes of data space can be initialize in 0 or 0xff ;* Limit: if Flag T==1 then EachMemoryByte=0 else EachMemoryByte=0xff ;* ; *************************************************************************** .def MathPattern=r28 ;YL .def MathCounter=r29 ;YH MathMemLimit: MathMem0x1: ser cpse
brts MathMem0x0 ; MathPattern ; ZH,ZH ;skip next
MathMem0x0: clr mov cbr
MathPattern MathCounter,ZH ZH,0xfe
NextMemByte:
st Z+,MathPattern MathCounter,2 ; NextMemByte ;while
instruction ; ;copy counter ;Z points to math
data space subi brcc
;
MathCounter>=0 ret ; .equ MathMem=MathMem0x0 ;default initialize memory call ; *************************************************************************** ;* ;* Registers Load from Math Data Space ;* ;* Load: r16r17r18r19r20r21r22r23 from first 512+3 bytes of data space ;* operand2 operand1 (max starting address: 0x1ff) ;* ; *************************************************************************** .def MathBmp=r26 ;only XL,XH from high registers .def MathTmp=r27 ;do not keep useful data or not used below R16MathLoad:
ldi
YL,16
;Y points
to operand2 LSB cpse
ZH,ZH
;skip next
instruction R20MathLoad:
ldi
YL,20
;Y points
to operand1 LSB clr mov cbr
YH MathBmp,ZH ZH,0xfe
; ;copy bitmap ;Z points to math
sbr
MathBmp,0xe0
;it is possible in
data space each macrocall MathLoadNext: clr
lsr MathBmp ; MathTmp ;load 0 to temp
register sbrc
MathBmp,0
;if bit 0 bitmap
ld
MathTmp,Z+
;
st
Y+,MathTmp
;store temp to math
sbrc rjmp
MathBmp,4 MathLoadNext
; ;while bit 4 of
not clear load operand
from memory to temp register
bitmap not clear ret ; .equ MathLoad=R20MathLoad ;default registers load call ; *************************************************************************** ;* ;* Registers Save to Math Data Space ;* ;* Save: r20r21r22r23r24r25r26r27 to first 512 +7 bytes of data space ;* result (remainder) (max starting address: 0x1ff) ;* ; *************************************************************************** .def MathBmp=r0 ;all high registers keep useful data or used below sec cpse
ZH,ZH
; ;skip next
mov cbr
clc MathBmp,ZH ZH,0xfe
; ;copy bitmap ;Z points to math
ror
MathBmp
;now bitmap have
ldi
YL,20
;Y points to result
instruction R20MathSave:
data space all 8 bits LSB MathSaveNext: ld
clr YH,Y+
YH
; ;in order to not
use other registers sbrc
MathBmp,0
;if bit 0 bitmap
st
Z+,YH
;
lsr brne
MathBmp MathSaveNext
; ;while not empty
not clear store
result byte to memory
bitmap ret ; .equ MathSave=R20MathSave ;default registers save call ; *************************************************************************** ;* ;* Add32 == 32+32 Bit Unsigned Addition ;* ;* add1L::add1H + add2L::add2H = add1L::add1H ;* item item sum ;* r20r21r22r23 + r16r17r18r19 = r20r21r22r23 ;* ; *************************************************************************** .def add20 = r16 ; item 2 byte 0 (LSB) .def add21 = r17 ; item 2 byte 1 .def add22 = r18 ; item 2 byte 2 .def add23 = r19 ; item 2 byte 3 (MSB) .def add10 = r20 ; item 1 byte 0 (LSB) .def add11 = r21 ; item 1 byte 1 .def add12 = r22 ; item 1 byte 2 .def add13 = r23 ; item 1 byte 3 (MSB) Add32sign: Add32:
brts
Sub32sign ; add add10,add20
;Add low
bytes adc
add11,add21
;Add higher bytes
adc adc ret
add12,add22 add13,add23
; ; ;
with carry
; *************************************************************************** ;* ;* Sub32 == 32-32 Bit Unsigned Subtraction ;* ;* sub1L::sub1H - sub2L::sub2H = sub1L::sub1H ;* minuend subtrahend difference ;* r20r21r22r23 - r16r17r18r19 = r20r21r22r23 ;* ; *************************************************************************** .def sub20 = r16 ; subtrahend byte 0 (LSB) .def sub21 = r17 ; subtrahend byte 1 .def sub22 = r18 ; subtrahend byte 2 .def sub23 = r19 ; subtrahend byte 3 (MSB) .def sub10 = r20 ; minuend byte 0 (LSB) .def sub11 = r21 ; minuend byte 1 .def sub12 = r22 ; minuend byte 2 .def sub13 = r23 ; minuend byte 3 (MSB) Sub32sign: Sub32:
clt sub
;sign + sub10,sub20 ;Subtract
low bytes sbc
sub11,sub21
;Subtract higher
sbc sbc brcc
sub12,sub22 sub13,sub23 Return32u
; ; ;return clear carry
bytes with carry
if result>=0 set Neg32:
;sign -
com com com
subi sub10,1 sub11,0 ; sub12,0 ; sub13,0 ; com sub10 sub11 ; sub12 ; sub13 ;
ret
;
sbci sbci sbci Com32:
;if result<0 neg result (dec result) ; & (com result) return set
carry after com Return32u:
; *************************************************************************** ;* ;* Mul32 == 32x32 Bit Unsigned Multiplication ;* ;* mp32uL::mp32uH x mc32uL::mc32uH = m32uL::m32uH ;* multiplier multiplicand result ;* r20r21r22r23 x r16r17r18r19 = r20r21r22r23r24r25r26r27 ;* ; *************************************************************************** .def mc32u0 =r16 ; multiplicand byte 0 (LSB) .def mc32u1 =r17 ; multiplicand byte 1 .def mc32u2 =r18 ; multiplicand byte 2 .def mc32u3 =r19 ; multiplicand byte 3 (MSB) .def mp32u0 =r20 ; multiplier byte 0 (LSB) .def mp32u1 =r21 ; multiplier byte 1 .def mp32u2 =r22 ; multiplier byte 2 .def mp32u3 =r23 ; multiplier byte 3 (MSB) .def m32u0 =r20 ; result byte 0 (LSB) .def m32u1 =r21 ; result byte 1 .def m32u2 =r22 ; result byte 2 .def m32u3 =r23 ; result byte 3 .def m32u4 =r24 ; result byte 4 .def m32u5 =r25 ; result byte 5 .def m32u6 =r26 ; result byte 6 .def m32u7 =r27 ; result byte 7 (MSB) .def mcnt32u =r28 ; loop counter Mul32b:
clr
mc32u1
;multiplicand is
Mul32w:
clr
mc32u2
;
Mul32t:
clr
mc32u3
;
one byte two bytes three bytes Mul32:
clr
m32u7
;clear 4
highest bytes of result
m32u_loop:
clr clr sub ldi ror
m32u6 m32u5 m32u4,m32u4 mcnt32u,33 m32u3
; ; ;and carry ;init loop counter ;rotate result and
ror ror ror dec
m32u2 m32u1 m32u0 mcnt32u
; ; ; ;decrement loop
breq
Return32u
;if counter zero
brcc
m32u_skip
;if bit 0 of
add
m32u4,mc32u0
;
adc adc adc ror
m32u5,mc32u1 m32u6,mc32u2 m32u7,mc32u3 m32u7
; ; ; ;shift right result
ror ror ror rjmp
m32u6 m32u5 m32u4 m32u_loop
;rotate right result ; ; ;
multiplier
counter return multiplier set add
multiplicand to result
m32u_skip: byte 7
; *************************************************************************** ;* ;* Div32 == 32/32 Bit Unsigned Division ;* ;* dd32uL::dd32uH / dv32uL::dv32uH = dres32uL::dres32uH (drem32uL::drem32uH) ;* dividend divisor result remainder ;* r20r21r22r23 / r16r17r18r19 = r20r21r22r23 r24r25r26r27 ;* ; *************************************************************************** .def dv32u0 =r16 ; divisor byte 0 (LSB) .def dv32u1 =r17 ; divisor byte 1 .def dv32u2 =r18 ; divisor byte 2 .def dv32u3 =r19 ; divisor byte 3 (MSB) .def dres32u0 =r20 ; result byte 0 (LSB) .def dres32u1 =r21 ; result byte 1 .def dres32u2 =r22 ; result byte 2 .def dres32u3 =r23 ; result byte 3 (MSB) .def dd32u0 =r20 ; dividend byte 0 (LSB) .def dd32u1 =r21 ; dividend byte 1 .def dd32u2 =r22 ; dividend byte 2 .def dd32u3 =r23 ; dividend byte 3 (MSB) .def drem32u0 =r24 ; remainder byte 0 (LSB) .def drem32u1 =r25 ; remainder byte 1 .def drem32u2 =r26 ; remainder byte 2 .def drem32u3 =r27 ; remainder byte 3 (MSB) .def dcnt32u =r28 ; loop counter Div32b: Div32w:
clr clr
dv32u1 dv32u2
;divisor is one byte ; two
Div32t:
clr
dv32u3
;
bytes three
bytes Div32:
clr
drem32u0
;clear 4
lower remainde byte
d32u_loop:
clr clr sub ldi rol rol rol rol dec
drem32u1 ; drem32u2 ; drem32u3,drem32u3;and carry dcnt32u,33 ;init loop counter dd32u0 ;shift left dividend dd32u1 ; dd32u2 ; dd32u3 ; dcnt32u ;decrement loop
breq
Com32
;if counter zero
rol
drem32u0
;shift dividend
rol rol rol sub
drem32u1 drem32u2 drem32u3 drem32u0,dv32u0
; ; ; ;remainder =
sbc sbc sbc brcc
drem32u1,dv32u1 drem32u2,dv32u2 drem32u3,dv32u3 d32u_loop
; ; ; ;clear carry to be
add adc
drem32u0,dv32u0 ;if result negative drem32u1,dv32u1 ; restore
adc adc rjmp
drem32u2,dv32u2 ; drem32u3,dv32u3 ; d32u_loop ;
counter invert result into remainder
remainder - divisor
shifted into res
remainder
set carry to be
shifted into res ; *************************************************************************** ;* ;* BCD2bin == BCD to 16-Bit Binary Conversion ;* ;* fBCD0:fBCD1:fBCD2 >>> tbinL:tbinH ;* dec hex ;* r16r17r18 >>> r20r21 ;* ; *************************************************************************** .def fBCD0 =r16 ; BCD value digits 0 and 1 .def fBCD1 =r17 ; BCD value digits 2 and 3 .def fBCD2 =r18 ; BCD value digit 4 (MSD is lowermost nibble) .def mp10L =r20 : Low byte of number to be multiplied by 10 .def mp10H =r21 ; High byte of number to be multiplied by 10 .def tbinL =r20 ; Low byte of binary result (same as mp10L) .def tbinH =r21 ; High byte of binary result (same as mp10H) .def copyL =r22 ; temporary register .def copyH =r23 ; temporary register BCD2bin20:
mov
r16,r20
;for compatibility
BCD2bin16:
mov mov cbr
r17,r21 r18,r22 fBCD2,0xf0
; ; ;mask away upper
mov clr clr
mp10L,fBCD2 mp10H fBCD2
;mp10L:mp10H = MSD ; ;for adci mp10H,0
with Math32
nibble of fBCD2
below rcall mul10bcd ;fBCDX = fBCD1 mov fBCD1,fBCD0 ;fBCDX = fBCD0 mul10bcd: ;mp10L:mp10H=10(10*mp10L:mp10H+highnibble (fBCDX))+lownibble(fBCDX) rcall
mul10add
;10*mp10L:mp10H
+highnibble(fBCDX) mul10add: ;mp10L:mp10H = 10*mp10L:mp10H+lownibble(fBCDX) lsl mp10L ;multiply original by 2 rol mov mov lsl
mp10H copyL,mp10L copyH,mp10H copyL
; ;make copy (x2) ; ;multiply copy by 2
rol lsl
copyH copyL
; ;multiply copy by 2
rol add
copyH mp10L,copyL
; ;add copy to
adc swap
mp10H,copyH fBCD1
; ;fBCDX
mov andi
copyL,fBCD1 copyL,0x0f
; ;mask away upper
add adc
mp10L,copyL mp10H,fBCD2
;add lower nibble ;high byte of
(x4)
(x8)
original (x10)
upper<=>lower nibble
nibble
result + carry ret ; .equ BCD2bin=BCD2bin20 ;default registers BCD to BIN call ; *************************************************************************** ;* ;* BCD3bin == BCD to 24-Bit Binary Conversion ;* ;* fBCD0:fBCD1:fBCD2:fBCD3 >>> tbin0:tbin1:tbin2 ;* dec hex ;* r16r17r18r19 >>> r20r21r22 ;* ; *************************************************************************** .def fBCD0 =r16 ; BCD value digits 0 and 1 .def fBCD1 =r17 ; BCD value digits 2 and 3 .def fBCD2 =r18 ; BCD value digits 4 and 5 .def fBCD3 =r19 ; BCD value digits 6 and 7 (MSD is 0|1) .def tbin0 =r20 ; binary value byte 0 (LSB) .def tbin1 =r21 ; binary value byte 1 .def tbin2 =r22 ; binary value byte 2 (MSB) BCD3bin20:
mov
r16,r20
;for compatibility
r17,r21 r18,r22 r19,r23 tbin0,0xca
; ; ;
BCD3bin16:
mov mov mov ldi ldi
tbin1,0x1b
;-
ldi ;0xff1bca=0xef0bba-0xefeff0 sbrc
fBCD3,4
; delete
subi
fBCD3,6
; if
with Math32
;digit-to-
digit presetting 1111110=0xef0bba tbin2,0xff decimal correction NUMBER<10000000 always bcdbin_106: subi
tbin0,byte1(-1000*1000) ;addit
sbci sbci subi brcc bcdbin_105: subi
tbin1,byte2(-1000*1000) tbin2,byte3(-1000*1000) fBCD3,0x01 bcdbin_106 tbin0,byte1(-100*1000)
; ; ; ; ;addit
sbci sbci subi brcc bcdbin_104: subi
tbin1,byte2(-100*1000) tbin2,byte3(-100*1000) fBCD2,0x10 bcdbin_105 tbin0,byte1(-10*1000)
; ; ; ; ;addit
sbci sbci subi brhc bcdbin_103: subi
tbin1,byte2(-10*1000) tbin2,byte3(-10*1000) fBCD2,0x01 bcdbin_104 tbin0,byte1(-1000)
; ; ; ; ;addit
sbci sbci subi brcc bcdbin_102: subi
tbin1,byte2(-1000) tbin2,byte3(-1000) fBCD1,0x10 bcdbin_103 tbin0,byte1(-100)
; ; ; ; ;addit
sbci sbci subi brhc bcdbin_101: subi
tbin1,byte2(-100) tbin2,byte3(-100) fBCD1,0x01 bcdbin_102 tbin0,byte1(-10)
; ; ; ; ;addit
sbci sbci subi brcc
tbin1,byte2(-10) tbin2,byte3(-10) fBCD0,0x10 bcdbin_101
; ; ; ;addit
add
tbin0,fBCD0
; addend of
adc
tbin1,fBCD1
;
adc
tbin2,fBCD2
; (pre take
tbin,10^6
tbin,10^5
tbin,10^4
tbin,10^3
tbin,10^2
tbin,10^1
tbin,0xefeff0+LSD tbin1 & tbin2 is arbitrarily chosen const off from tbin) ret
http://avr-asm.tripod.com/math32x.html (1 of 3)1/20/2009 8:37:55 PM
16 BIT MATH (AVR 202)
.equ BCD3bin=BCD3bin20 ;default registers BCD to BIN call ; *************************************************************************** ;* ;* Bin2BCD == 16-bit Binary to BCD conversion ;* ;* fbinL:fbinH >>> tBCD0:tBCD1:tBCD2 ;* hex dec ;* r16r17 >>> r20r21r22 ;* ; *************************************************************************** .def fbinL =r16 ; binary value Low byte .def fbinH =r17 ; binary value High byte .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digit 4 (MSD is lowermost nibble) Bin2BCD20:
mov
r16,r20
;for compatibility
mov ldi inc subi sbci brcc ldi
r17,r21 ; tBCD2,0xff ;initialize digit 4 tBCD2 ; fbinL,low(10000);subiw fbin,10000 fbinH,high(10000) binbcd_4 ; tBCD1,0x9f ;initialize digits
subi subi sbci brcs inc subi sbci brcc ldi
tBCD1,0x10 ; fbinL,low(-1000);addiw fbin,1000 fbinH,high(-1000) binbcd_3 ; tBCD1 ; fbinL,low(100) ;subiw fbin,100 fbinH,high(100) ; binbcd_2 ; tBCD0,0xa0 ;initialize digits
with Math32 Bin2BCD16: binbcd_4:
3 and 2 binbcd_3:
binbcd_2:
1 and 0 binbcd_1:
subi tBCD0,0x10 ; subi fbinL,-10 ;addi fbin,10 brcs binbcd_1 ; add tBCD0,fbinL ;LSD binbcd_ret: ret ; .equ Bin2BCD=Bin2BCD20 ;default registers BIN to BCD call ; *************************************************************************** ;* ;* Bin4BCD == 32-bit Binary to BCD conversion [ together with Bin2BCD ] ;* ;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2: tBCD3:tBCD4 ;* hex dec ;* r18r19r20r21 >>> r20r21r22r23r24 ;* ; *************************************************************************** .def fbin0 =r18 ; binary value byte 0 (LSB) .def fbin1 =r19 ; binary value byte 1 .def fbin2 =r20 ; binary value byte 2 .def fbin3 =r21 ; binary value byte 3 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 (same as fbin2) .def tBCD1 =r21 ; BCD value digits 2 and 3 (same as fbin3) .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 .def tBCD4 =r24 ; BCD value digits 8 and 9 (MSD) Bin4BCD:
rcall clr
Bin2BCD20 tBCD3
; ;initial highest
ldi
tBCD4,0xfe ; subi tBCD0,-0x33
bytes of result binbcd_loop:
;add 0x33
to digits 1 and 0 sbrs subi sbrs subi subi
tBCD0,3 tBCD0,0x03 tBCD0,7 tBCD0,0x30 tBCD1,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi subi
tBCD1,3 tBCD1,0x03 tBCD1,7 tBCD1,0x30 tBCD2,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi lsl rol rol rol rol rol rol brmi
tBCD2,3 tBCD2,0x03 tBCD2,7 tBCD2,0x30 fbin0 fbin1 tBCD0 tBCD1 tBCD2 tBCD3 tBCD4 binbcd_loop
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ; ;shift lower word ;through all bytes ; ; ; ; ;7 shifts w/o
rol
fbinH
;since Bin2BCD
brcc
binbcd_ret
;
subi
tBCD3,-0x33
;add 0x33 to digits
sbrs subi sbrs subi subi
tBCD3,3 tBCD3,0x03 tBCD3,7 tBCD3,0x30 tBCD4,-0x03
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x03 to digit
sbrs subi rjmp
tBCD4,3 tBCD4,0x03 binbcd_loop
;if bit 3 clear ; sub 3 ;
3 and 2
5 and 4
correction of MSD fbinH = 0xff so as to do
16_lsl in total 7 and 6
8 only
; *************************************************************************** ;* ;* Bin4BCD == 32-bit Binary to BCD conversion ;* ;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2: tBCD3:tBCD4 ;* hex dec ;* r16r17r18r19 >>> r20r21r22r23r24 ;* ; *************************************************************************** .def fbin0 =r16 ; binary value byte 0 (LSB) .def fbin1 =r17 ; binary value byte 1 .def fbin2 =r18 ; binary value byte 2 .def fbin3 =r19 ; binary value byte 3 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 .def tBCD4 =r24 ; BCD value digits 8 and 9 (MSD) Bin4BCD20:
mov
r16,r20
;for compatibility
Bin4BCD16:
mov mov mov clr
r17,r21 r18,r22 r19,r23 tBCD0
; ; ; ;initial result (5
clr clr ldi
tBCD1 tBCD2 tBCD3,0xfe
; ; ;
rjmp
binbcd_jump
;for speed-up and
binbcd_876: subi
tBCD4,-0x03
;add 0x03 to digit
sbrs subi subi
tBCD4,3 tBCD4,0x03 tBCD3,-0x33
;if bit 3 clear ; sub 3 ;add 0x33 to digits
sbrs subi sbrs subi subi
tBCD3,3 tBCD3,0x03 tBCD3,7 tBCD3,0x30 tBCD2,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi
tBCD2,3 ;if bit 3 clear tBCD2,0x03 ; sub 3 tBCD2,7 ;if bit 7 clear tBCD2,0x30 ; sub $30 subi tBCD1,-0x33 ;add 0x33
with Math32
bytes) & shift loop
counter ldi tBCD4,0xff
;
too
skip of MSD corr 8 only
7 and 6
binbcd_54: 5 and 4
binbcd_3210: to digits 3 and 2 sbrs subi sbrs subi subi
tBCD1,3 tBCD1,0x03 tBCD1,7 tBCD1,0x30 tBCD0,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi rol rol rol rol rol rol rol rol brcs
tBCD0,3 tBCD0,0x03 tBCD0,7 tBCD0,0x30 lsl fbin0 fbin1 fbin2 fbin3 tBCD0 tBCD1 tBCD2 tBCD3 tBCD4 binbcd_3210
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ; ; ; ;shift input value ;through all bytes ; ; ; ; ;16_lsl w/o
inc brpl
fbin0 binbcd_54
; ;+7_lsl w/o
sbrs rjmp
fbin2,0 binbcd_876
; ;32_lsl in total
1 and 0
binbcd_jump:
correction of dig_87654
correction of dig_876
(fbin = 0x1ffff) ret
;
; *************************************************************************** ;* ;* Bin3BCD == 24-bit Binary to BCD conversion [ together with Bin2BCD ] ;* ;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3 ;* hex dec ;* r16r17r18 >>> r20r21r22r23 ;* ; *************************************************************************** .def fbin0 =r16 ; binary value byte 0 (LSB) .def fbin1 =r17 ; binary value byte 1 .def fbin2 =r18 ; binary value byte 2 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 (MSD) Bin3BCD:
ldi
tBCD3,0xff
;initialize
binbcd_7:
inc subi
tBCD3 fbin0,byte1(10000*100)
; ;subit
sbci sbci brcc subi
fbin1,byte2(10000*100) fbin2,byte3(10000*100) binbcd_7 tBCD3,-6
; ; ; ; delete
sbrs
tBCD3,4
; if
subi ldi
tBCD3,6 tBCD2,0x9f
; ;initialize
subi subi
tBCD2,0x10 fbin0,byte1(-10000*10)
; ;addit
sbci sbci brcs inc subi
fbin1,byte2(-10000*10) fbin2,byte3(-10000*10) binbcd_6 tBCD2 fbin0,byte1(10000)
; ; ; ; ;subit
sbci sbci brcc rjmp
fbin1,byte2(10000) fbin2,byte3(10000) binbcd_5 binbcd_3-1
; ; ; ;initialize
digits 7 and 6
fbin,1000000
decimal correction NUMBER<10000000 always
digits 5 and 4 binbcd_6: fbin,100000
binbcd_5: fbin,10000
digits 3 and 2 ; *************************************************************************** ;* ;* Bin3BCD == 24-bit Binary to BCD conversion ;* ;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3 ;* hex dec ;* r16r17r18 >>> r20r21r22r23 ;* ; *************************************************************************** .def fbin0 =r16 ; binary value byte 0 (LSB) .def fbin1 =r17 ; binary value byte 1 .def fbin2 =r18 ; binary value byte 2 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 (MSD) Bin3BCD20:
mov
r16,r20
;for compatibility
r17,r21 r18,r22 tBCD3,0xfa
; ;
Bin3BCD16:
mov mov ldi
with Math32
;initialize
digits 7 and 6 binbcd_107: subi subi
tBCD3,-0x10 ; fbin0,byte1(10000*1000) ;subit
sbci sbci brcc binbcd_106: dec subi
fbin1,byte2(10000*1000) fbin2,byte3(10000*1000) binbcd_107 tBCD3 fbin0,byte1(-10000*100)
; ; ; ; ;addit
sbci sbci brcs ldi
fbin1,byte2(-10000*100) fbin2,byte3(-10000*100) binbcd_106 tBCD2,0xfa
; ; ; ;initialize
binbcd_105: subi subi
tBCD2,-0x10 fbin0,byte1(10000*10)
; ;subit
sbci sbci brcc binbcd_104: dec subi
fbin1,byte2(10000*10) fbin2,byte3(10000*10) binbcd_105 tBCD2 fbin0,byte1(-10000)
; ; ; ; ;addit
fbin1,byte2(-10000) fbin2,byte3(-10000) binbcd_104 tBCD1,0xfa
; ; ; ;initialize
binbcd_103: subi subi
tBCD1,-0x10 fbin0,byte1(1000)
; ;subiw
sbci brcc binbcd_102: dec subi
fbin1,byte2(1000) binbcd_103 tBCD1 fbin0,byte1(-100)
; ; ; ;addiw
sbci brcs ldi
fbin1,byte2(-100) binbcd_102 tBCD0,0xfa
; ; ;initialize
binbcd_101: subi subi
tBCD0,-0x10 fbin0,10
; ;subi
brcc add ret
binbcd_101 tBCD0,fbin0
; ;LSD ;
fbin,10^7
fbin,10^6
digits 5 and 4
fbin,10^5
fbin,10^4 sbci sbci brcs ldi digits 3 and 2
fbin,10^3
fbin,10^2
digits 1 and 0
fbin,10^1
; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Demo: ;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-) (-:-)(-;-)(-:-)(-;-)(-:-) ; *************************************************************************** ;$ $ $ $ $ $ $ $ $ Illustrations with comments field $ $ $ $ $ $ $ $ $ ; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .dseg Variable: .byte 4 VarWord1: .byte 2 VarWord2: .byte 2 Result: .byte 8 .equ Address1 =VarWord1 .equ Address2 =VarWord2 .equ Address =Variable .set Constant =0x4321 .cseg .def Temp =r16 .def TempL =r16 .def TempH =r17 .def Flags =r15 .equ _Flag1 =1 .equ _Flag2 =2 .equ _Flag3 =3 .equ _signResult=0 ;*** OUTI, OUTIW, OUTW, INW outiw SP,Temp,RAMEND
;initialize 16-bit
Stack Pointer outi
TCNT0,Temp,0
;clear Timer/
inw
Temp,TCNT1
;read Timer/
outw
TCNT1,Temp
;write Timer/
Counter0 (8-bit) Counter1 (16-bit) Counter1 (16-bit) ;*** CLF, SEF, CBF, SBF, IBF clf Flags,_Flag1
;clear (0)
bit _Flag1 bld
Flags,_Flag2
;
and
cbf
Flags,Temp,_Flag1,_Flag2 ;clear
sef
Flags,_Flag1
;set (1)
bld
Flags,_Flag2
;
sbf
Flags,Temp,_Flag1,_Flag2 ;set both
ibf
Flags,Temp,_Flag1,_Flag2,_Flag3 ;
ibf
TempL,TempH,0,2,4,6
bit _Flag2 both at once bit _Flag1 and
bit _Flag2 at once invert of 3 flags ;invert
only even bits ;*** XCH, MVW, MVI, MOVS, MOVSW xch TempL,TempH
;swap in Temp
register pair xch
Temp,r0
;swap bytes r0 &
mvw
X,Y
;copy of Y register pair
mvw
Z,Temp
;copy of TempL&TempH into Z
mvi
Flags,Temp,exp2(_Flag1)|1<<_Flag2 ;
mvi
r0,Temp,Constant
;load to
movs
Address1,Temp,Address2
;copy of
movsw
Address1,Temp,Address2
;copy of
Temp into X pair register pair initialize flags low register (0-15) one memory byte two memory bytes ;*** STSI, STSIW, LDSW, STSW stsi Address,Temp,Constant
;initialize
of one memory byte stsiw
Address,Temp,Constant
;initialize
ldsw
Temp,Address1
;copy of two memory
stsw
Address2,Temp
;
of two memory bytes bytes via Temp
register pair ;*** LDIW, LDDW, STDW ldiw Temp,Constant
;initialize of
register pair ldiw
Z,Address
;initialize of
lddw
Temp,Z+(Address1-Address) ;copy of
stdw
Z+(Address2-Address),Temp ;
address pointer two memory bytes via
Temp register pair ;*** PUSHW, POPW pushw
Y
;copy of Y register
popw
X
;
ldiw pushw ret
Temp,Maths Temp
pair into X register
pair
;equ jmp Maths
Maths: ;***** INITMEM InitMem Address
;clear 128 bytes
(latest Address+127) InitMem Address,0 InitMem Address,0,0 InitMem Address,,1
;equ InitMem Address ;equ InitMem Address ;for 128 bytes each:
InitMem Address,1
;clear one byte at
=0xff Address InitMem Address1,Address2-Address1+2,Limit ;limitation: if bit_T=0 then 4_bytes:=0xff else 4_bytes:=0 ldi MathPattern,0xab InitMem Address,,+1 ;128_bytes:=0xab doubly, but possibly ;***** MATHR16, MATHR20, OPERAND Operand Address
;equ MathR20
Address,obXXXX MathR20 Address .set ObXXXX=0b11 MathR16 Address
;equ Operand Address ;equ Operand
Address,0b0011,r16 .set ObXXXX=0b1111 ;default Operand Address,,r16
;equ MathR16
Operand Address,,r20
;equ MathR20
Operand Address,0b11
;equ MathR20
Address,obXXXX Address,obXXXX Address,0b0011 Operand Address,0b11,r16;equ MathR16 Address,0b0011 ;load data with displacement (equ *256, *65536, *16777216) MathR20 Address,0b0110
;(data word)
MathR16 Address,0b1000
;(data byte)
<<8 <<24 ;***** CONST20, CONST16, CNST16T ; WARNING: AVRASM ver. 1.30 don't understand 32 bits constants, but all it ; expressions are internally 32 bits (the higher versions of assembler ; directly operate on value up to 0xffffffff) Const20 0x76543210 ;error v1.30 (0x00003210) Const20 1985229328
;error
Const16 0x7654<<16|0x3210
;ok
v1.30 (12816) (0x76543210) Cnst16t 0x7654*1024*1024+0x1234 ;ok (0x401234) ;***** CNST16B, CNST16W Cnst16b Constant
;equ Const16 byte1
(Constant) rcall
Div32b
;
rcall Div32 ;
but briefly Cnst16w Constant<<1
;non-equ Const16
rcall
;
Constant<<1 Mul32w
rcall
Mul32 ;word overflow ;***** RESULT2, RESULT3 Result2 Address
;equ Result2
Address,obXXXX ;store data with displacement (equ /256, /65536, /16777216 and more) Result2 Address,1<<7 ;(byte result)>>56 Result2 Address,0b111100 ;(double word result)>>16 Result2 Address,obXXXX<<4 ;(double word result)>>32 rjmp JointTail+3 JointTail: Result3 Address,0xff ;equ Result2 Address,0b11111111 rcall JointTail ;concluding RET inside Result call ;******* register pairs .def AL=r16 .def AH=r17 .def BL=r18 .def BH=r19 .def CL=r20 .def CH=r21 .def DL=r22 .def DH=r23 .def WL=r24 .def WH=r25 ldiw C,0 ldiw D,0x7654
;equ ; Const20
0x7654<<16 ldiw ldi mvw mvw adiw
A,0x3210 ;equ Cnst16w 0x3210 AL,0x10 ;equ Cnst16b 0x10 A,C ;copy of Const20 B,D ; into Const16 WL,1 ;as well as "adiw" for X,Y,
sbiw
WL,1
Z register pairs ;as well as "sbiw" for X,Y,
Z register pairs ;******* testing calculations InitMem Variable,4,1
;
0xffffffff to memory Operand Variable Const16 0xffff<<16|0xffff rcall Mul32
;
Result2 Result,0b11111111
;
Operand Variable Const16 0x1010<<16|0x1010 rcall Div32
;
Result2 Result,0b11111111
; 0xf
Operand Variable,0b111 Cnst16t 0x00ff<<16|0xffff rcall Div32t
;
Result2 Result
; 0x1 (0x0
Operand Variable,0b1100 Cnst16w 0xffff rcall Div32w
;
Result2 Result
; 0x10000
0xffffffff * 0xffffffff 0xfffffffe00000001
0xffffffff / 0x10101010 (0x0f0f0f0f)
0xffffff / 0xffffff no rollout)
0xffff0000 / 0xffff (0x0 no rollout) ;******* data translations 16-bit (overall maximum 65535=0xffff) ;result Rd16|24 Const20 rcall Cnst16t rcall Result2 rcall Cnst16w rcall
0x2748 BCD2bin 6<<16|0x5535 BCD2bin16 Address,0b11 Bin2BCD 0xabba Bin2BCD16
;02748 = 0x0abc ;65535 = 0xffff ;0xffff = 65535 ;0xabba = 43962
;******* data translations 32-bit (overall maximum 655359999=0x270fffff) ;BCD2Bin stsiw stsiw
Variable,Temp,0x5432 Variable+2,Temp,0x9876
; ;BCD
98765432 >>> Operand Variable,0b11 rcall BCD2bin pushw C
;temporary result
always is 2 bytes Operand Variable+2,0b11 ;or 0b111 if BCD have all 5 digits rcall ldiw Cnst16w rcall popw
BCD2bin D,0 10000 Mul32w A
;B pair by this
time =0 rcall Add32 Result2 Result,0b1111
;>>> HEX
stsiw stsiw
; ;HEX
0x05e30a78 ;Bin2BCD Variable,Temp,0xffff Variable+2,Temp,0x270f
0x270fffff >>> Operand Variable,0b1111 Cnst16w 10000 ;remainder always is 2 bytes rcall
Div32w
;
as
temporary result rcall Bin2BCD Result2 Result+2,0b111 mvw A,W
;W pair do not
changed beyond rcall Bin2BCD16 Result2 Result,0b11
;>>> BCD
655359999 ;******* 32-bit Bin4BCD conversion (overall maximum 4294967295=0xffffffff) ;result Rd40 ldi
YL,18
;one more dishonest
trick Operand Variable,0b1111,1+ rcall Bin4BCD ;0x270fffff >>> 655359999 Const20 0x1234<<16|0x5678 Result2 18 rcall Bin4BCD ;0x12345678 >>> 305419896 Const16 0xab98<<16|0xfedc mvw C,A rcall Bin4BCD ;0xfedcab98 >>> 4275874712 InitMem MathR20 MathR16 rcall
Variable,3,1 Variable,0b111 Variable,0b111 Mul32t
; 0xffffff to memory
;(0xffffff)^2 =
0xfffffe000001 Result2 18,0b111100
;
/65536 =
rcall
;0xfffffe00 >>>
0xfffffe00 Bin4BCD
4294966784 ;******* data translations 32-bit (overall maximum 4294967295=0xffffffff) ;Bin4BCD20 Operand Variable,0b1111 rcall Bin4BCD20 ;0x27ffffff >>> 671088639 Const20 0x1234<<16|0x5678 rcall Bin4BCD20 ;0x12345678 >>> 305419896 ldiw ldiw rcall
D,0 C,0xab Bin4BCD20
;
rcall
Bin4BCD16
;
0xab >>> 171
;Bin4BCD16 0x1ffff >>>
131071 Const16 0xfedc<<16|0xab98 rcall Bin4BCD16 ;0xfedcab98 >>> 4275874712 InitMem Variable,4,1 MathR16 Variable,0b1111 rcall Bin4BCD16 ;0xffffffff >>> 4294967295 ;******* data translations 24-bit (overall maximum 16777215=0xffffff) ;BCD3bin Const20 $1670<<16|$2650 rcall BCD3bin ;16702650 >>> 0xfedcba ldiw ldiw rcall
B,0 A,9 BCD3bin16
;00000009 >>>
ldiw ldiw rcall
D,0x1599 C,0x9990 BCD3bin20
;15999990 >>>
0x000009 (fastest)
0xf423f6 (slowest) ;Bin3BCD Const16 0x98<<16|0x967f rcall Bin3BCD ;0x98967f >>> 09999999 rcall
Bin3BCD
;0xffff09 >>>
16776969 Cnst16t $0d00*256+$df22 rcall Bin3BCD ;0x0ddf22 >>> 00909090 (fastest) Cnst16t $f500*256+$871d rcall Bin3BCD ;0xf5871d >>> 16090909 (slowest) ;Bin3BCD20 MathR20 Variable,0b111 rcall Bin3BCD20
;0xffffff >>>
rcall
;0x777215 >>>
16777215 Bin3BCD20
07827989 Const20 $a600*256+$75a2 rcall Bin3BCD20 ;0xa675a2 >>> 10909090 (slowest) ;Bin3BCD16 Cnst16t $8a00*256+$b75d rcall Bin3BCD16 ;0x8ab75d >>> 09090909 (fastest) ldi rcall ldi rcall
AH,0xff Bin3BCD16 AL,0 Bin3BCD16
;
0xffff >>> 65535
;0x000000 >>>
00000000 ;******* formula recalculation: Result=(VarWord10xfff)/7+VarWord2/0x100 ;VarWordX>=0 InitMem Variable,16
;clear
rcall
Formula
; -
ldiw
Temp,0xabcd
;these 2
stsw
VarWord1,Temp
;stsiw
stsw rcall
VarWord2,Temp Formula
; 0x16ed.
stsiw stsiw rcall
VarWord1,Temp,0x00ff VarWord2,Temp,0xff00 Formula
; -
stsiw stsiw rcall
VarWord1,Temp,0x0f0f VarWord2,Temp,0xf0f0 Formula
; 0x00ce.
VarWordX & Result 0x249.0000 as result
lines are not equ VarWord1,Temp,0xabcd
cd00 as result
0x125.9249 as result
a6dc as result InitMem VarWord1,4,1
;
ldiw pushw
Temp,Demo Temp
;getting
MathR20 Const16 rcall Cnst16b rcall Result2
VarWord1,0b1100 0xfff<<16 Sub32sign 7 Div32b 16 ;faster than call
0x2349.2392 at the end
into demo loop Formula:
MathR16 20 MathR16 20
;included for
comparison only MathR20 rcall bld Result3
VarWord2,0b110 Add32sign Flags,_signResult Result
.exit ; *************************************************************************** ;* ;* REMARK ;* Sometimes expression as macroparameter must be enclosed in parentheses, ;* because they not are always present in above macrocalls ;* (remember about the priority of AVR assembler operators). ;* Accommodate oneself to ATmega: MOVW instruction e. g., etc. ;* ; *************************************************************************** ;Feedback: please, include abbr."Math32" in Your e-mail subject line (!spam) ;from time to time it is possible mailbox overflow &| shut-down - I am sorry ;to make mention of http://www.i.com.ua/~birua when occasion offers - Thanks ;All the best & good luck!
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 http://avr-asm.tripod.com/math32x.html (2 of 3)1/20/2009 8:37:55 PM
16 BIT MATH (AVR 202)
have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/math32x.html (3 of 3)1/20/2009 8:37:55 PM
AVR MATH YX
The AVR Assembler Site
MATH YX PACKAGE HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202
A V R 2 0 2
************************
ASM MATH
MATH 202
N O T E
Title: Version: Last updated: Target:
16-bit Arithmetics 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This application note lists applications for the
following ;* Add/Subtract/Compare operations: ;* ;* "add16" ADD 16+16 ;* "adddi16" ADD 16+Immediate(16) ;* "sub16" SUB 16-16 ;* "subi16" SUB 16-Immediate(16) ;* "cp16" COMPARE 16/16 ;* "cpi16" COMPARE 16/Immediate ;* "neg16" NEGATION 16 ;* ; ***************************************************************************
MATH 202 DEC ASCII INT ASCII
r16,0x12
;Set up some registers to
ldi ldi
r17,0x34 r18,0x56
;the subroutines below. ;All expected results are
ldi
r19,0x78
;comments
show usage of
HX2ASC AVG8 222
.cseg ldi
presented as
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
; *************************************************************************** ;* ;* "add16" - Adding 16-bit registers ;* ;* This example adds the two pairs of register variables (add1l,add1h) ;* and (add2l,add2h) The result is placed in (add1l, add1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
AVR ISP
;**** Register Variables .def add1l = r16 .def add1h = r17 .def add2l = r18 .def add2h = r19
ISP 2313 ISP 1200 AVR SPI I2C 300
;***** Code add16: add
I2C 302 I2C TWI26 I2C/TWI 128
add1l, add2l
;Add low
bytes adc
add1h, add2h
;Add high bytes
with carry ;Expected result is 0xAC68
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;* ;* "addi16" - Adding 16-bit register with immediate ;* ;* This example adds a register variable (addi1l, addi1h) with an ;* immediate 16-bit number defined with .equstatement. The result is ;* placed in (addi1l, addi1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
PS2 EMU
;***** Register Variables .def addi1l = r16 .def addi1h = r17
BOOT MG8 BOOT DR8 ALM CLK
;***** Immediate 16-bit number .equ addi2 = 0x1234
CLOCK 8564 90 DAYS
;***** Code addi16: subi
DELAYS CALL ID DTMF 314
add1l, low(-addi2)
;Add low
byte ( x -(-y)) = x + y sbci
add1h, high(-addi2)
;Add high byte with
carry ;Expected result is 0xBE9C
PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* "sub16" - Subtracting 16-bit registers ;* ;* This example subtracts two pairs of register variables (sub1l,sub1h) ;* from (sub2l, sub2h) The result is stored in registers sub1l, sub1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The result and "sub1" share the same register. This causes "sub1" ;* to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def sub1l = r16 .def sub1h = r17 .def sub2l = r18 .def sub2h = r19 ;***** Code sub16: sub
sub1l,sub2l
;Subtract
low bytes sbc
sub1h,sub2h
;Add high byte with
carry ;Expected result is 0x4646
; *************************************************************************** ;* ;* "subi16" - Subtracting immediate 16-bit number from a 16-bit register ;* ;* This example subtracts the immediate 16-bit number subi2 from the ;* 16-bit register (subi1l,subi1h) The result is placed in registers ;* subi1l, subi1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The result and "subi1" share the same register. This causes ;* "subi1" to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def subi1l = r16 .def subi1h = r17 ;***** Immediate 16-bit number .equ subi2 = 0x1234 ;***** Code subi16: subi
subi1l,low(subi2)
;Subtract
low bytes sbci
subi1h,high(subi2)
;Subtract high byte
with carry ;Expected result is 0x3412
; *************************************************************************** ;* ;* "cp16" - Comparing two 16-bit numbers ;* ;* This example compares the register pairs (cp1l,cp1h) with the register ;* pairs (cp2l,cp2h) If they are equal the zero flag is set(one) ;* otherwise it is cleared(zero) ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The contents of "cp1" will be overwritten. ;* ; *************************************************************************** ;***** Register Variables .def cp1l = r16 .def cp1h = r17 .def cp2l = r18 .def cp2h = r19 ;***** Code cp16: cp cp1l,cp2l ;Compare low byte cpc cp1h,cp2h ;Compare high byte with carry from ;previous operation ncp16: ;Expected result is Z=0
; *************************************************************************** ;* ;* "cpi16" - Comparing 16-bit register with 16-bit immediate ;* ;* This example compares the register pairs (cpi1l, cpi1h) with the value ;* cpi2. If they are equal the zero flag is set(one), otherwise it is ;* cleared(zero). This is enabled by the AVR's zero propagation. Carry is ;* also set if the result is negative. This means that all conditional ;* branch instructions can be used after the comparison. ;* ;* Number of words :3 ;* Number of cycles :3 ;* Low registers used :None ;* High registers used :3 ;* ;* ; *************************************************************************** ;***** Register Variables .def cp1l =r16 .def cp1h =r17 .def c_tmp=r18 .equ cp2 = 0x3412
;Immediate to compare with
;***** Code cpi16: cpi cp1l,low(cp2) ;Compare low byte ldi c_tmp,high(cp2) ; cpc cp1h,c_tmp ;Compare high byte ;Expected result is Z=1, C=
; *************************************************************************** ;* ;* "neg16" - Negating 16-bit register ;* ;* This example negates the register pair (ng1l,ng1h) The result will ;* overwrite the register pair. ;* ;* Number of words :4 ;* Number of cycles :4 ;* Low registers used :None ;* High registers used :2 ;* ; *************************************************************************** ;***** Register Variables .def ng1l = r16 .def ng1h = r17 ;***** Code ng16: com ng1l
;Invert low byte
;
Calculated by com
ng1h
;Invert high byte
;
subi
ng1l,low(-1)
;Add 0x0001, low byte
;
sbci
ng1h,high(-1)
;Add high byte
;
incverting all bits then adding one (0x0001) ;Expected result is 0xCBEE
; *************************************************************************** ;* ;* End of examples. ;* ; ***************************************************************************
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, http://avr-asm.tripod.com/mathyx.html (1 of 2)1/20/2009 8:38:35 PM
AVR MATH YX
the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/mathyx.html (2 of 2)1/20/2009 8:38:35 PM
AVR MATH YX
The AVR Assembler Site
DIV16 XX PACKAGE HOME RETRO_DAN ASM FORUM
; DIVISION ROUTINES with scaled reciprocals for constants ; (all functions optimized for speed, ~ <36 cycles w/o push/pop)
ASM MATH TUTORIAL #1
; Target: AVR MCUs with hardware multiplier ("mul" instruction) ; Author: Andreas Lenze ([email protected]) ; Feb. 2003
TUTORIAL #2 TUTORIAL #3 MATH 200
;div. by n: n: scaled reciprocal:
shift count:
;Div16_3 ;Div16_5 ;Div16_6 ;Div16_7 ;Div16_7a
3 5 6 7 7
1010101010101011 AAAB 1100110011001101 CCCD 1010101010101011 AAAB 10010010010010011 1001001001001001 9249
17 18 18 19 -> 17 bits req'd,(MSB=1,rest 2493h) 18 -> needs correction for accurate
;Div16_9 ;Div16_10 ;Div16_11 ;Div16_12 ;Div16_13 ;Div16_14 ;Div16_15 ;Div16_17 ;Div16_18 ;Div16_19 ;Div16_20 ;Div16_21
9 10 11 12 13 14 15 17 18 19 20 21
1110001110001111 E38F 1100110011001101 CCCD 1011101000101111 BA2F 1010101010101011 AAAB 1001110110001010 9D8A 10010010010010011 1000100010001001 8889 1111000011110001 F0F1 1110001110001111 E38F 0110101111001011 6BCB 1100110011001101 CCCD 1100001100001011 C30B
19 19 19 19 19 20 -> 17 bits req'd,(MSB=1,rest 2493h) 19 20 20 19 20 20 -> needs correction for accurate
;Div16_22 ;Div16_23
22 1011101000101111 BA2F 23 1011001000010101 B215
MATH 200b MATH 201 MATH 202 MATH 32X MATH YX
result
DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII
result
HX2ASC AVG8 222
20 20 -> needs correction for accurate
result
FFT7
;D16_nn(by) 2-23 -> "C-style" function with macro 'Div16by' to perform a ; constants division with all divisors from 2 to 23. Price ; tag for the comfort is ~50 cycles / ~50 words overhead
COPY 102 LPM 108 EPROM 100
; NOTE: Other divisor constants like /24 etc. can easily be created by ; modifying the shift count in "Q = Q >> x": add 1 shift right for ; 'divisor x 2' (e.g. for "/24" we need a total of 20 instead of ; the 19 shifts needed for "/12")
SER EPROM DFLASH AT45 FLASH CARD
; ; ; ;
VFX SMIL VFX MEM SORT 220 CRC 236
r19:r18 now "Q" (= result >> xx)
; R = A - xx*Q (start removal ; ldi r16,xx ; .... ; sbc XH,YH (end removal) ; ; may be omitted to save another 9 cycles / 7 words ; (* not applicable for 'Div16_7a' - remainder is always needed *) ; ; "Div16_7a" and "Div16_21/3" demonstrate and use the 'approximate and
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
If the remainder of the division is not needed, the multiply/subtract operation after the comment
correct'
AVR ISP ISP 2313
; technique which may be necessary for some larger divisors (e.g. /21, /23) ;---------------------------------------------------------------------------
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
;*************************************************************************** ;* ;* Function "Div16_3" ;* Divides an unsigned 16 bit word (XH:XL) by 3 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xAAAB; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xAAAB) >> 17) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 10 words) ;* cycles: 48 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_3: push push push push
KBD PC/128
ldi ldi
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE
r2 r19 r18 r17 YH,0xAA YL,0xAB
; scaled reciprocal for /3
; Q = A * 0xAAAB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2
STH-11
; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 1 lsr r19 ; do the last shift ror r18
ATMEL CORP AVR BUTTERFLY
; r19:r18 now "Q" (= result >> 17) ; R = A - 3*Q; ldi r17,3 ; multiply r19:r18 by 3 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q
AVR BOOK
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_3 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_5" ;* Divides an unsigned 16 bit word (XH:XL) by 5 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xCCCD; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xCCCD) >> 18) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 54 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_5: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xCC YL,0xCD
; scaled reciprocal for /5
; Q = A * 0xCCCD ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 2 lsr r19 ; do the last 2 shifts ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 18) ; R = A - 5*Q; ldi r17,5 ; multiply r19:r18 by 5 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_5 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_6" ;* Divides an unsigned 16 bit word (XH:XL) by 6 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xAAAB; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xAAAB) >> 18) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 54 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_6: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xAA YL,0xAB
; scaled reciprocal for /6
; Q = A * 0xAAAB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 2 lsr r19 ; do the last 2 shifts ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 18) ; R = A - 6*Q; ldi r17,6 ; multiply r19:r18 by 6 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_6 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_7" ;* Divides an unsigned 16 bit word (XH:XL) by 7 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x2493; ;* unsigned int Q; /* the quotient */ ;* ;* Q = (((A * 0x2493) >> 16) + A) >> 3 -> 17 bits reciprocal! ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_7: push push push push
r2 r19 r18 r17
ldi ldi
YH,0x24 YL,0x93
; scaled reciprocal for /7
; Q = A * 0x2493 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q + A add r18,XL adc r19,XH ; Q = Q >> 3 ror r19 ror r18 lsr r19 ror r18 lsr r19 ror r18
; do the last 3 shifts, including ; carry (!) from previous addition
; r19:r18 now "Q" (= result >> 19) ; R = A - 7*Q; ldi r17,7 ; multiply r19:r18 by 7 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_7 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_7a" ;* Divides an unsigned 16 bit word (XH:XL) by 7 ;* Call with 16 bit number in XH:XL ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* (Equations partly by D. W. Jones) ;* ;* Reciprocal multiplication w. extra precision: ;* (This version uses correction to achieve the required precision) ;* unsigned int R; /* remainder */ ;* unsigned int long A; /* dividend */ ;* unsigned int long Q; /* quotient */ ;* ;* Q = ((A * 0x9249) >> 18) ;* ;* /* Q = A/7 or Q+1 = A/7 for all A <= 65535 */ ;* /* correct Q and calculate remainder */ ;* R = A - 7*Q ;* if (R >= 7) { ;* R = R - 7; ;* Q = Q + 1; ;* } ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 59 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_7a: push r2 push r19 push r18 push r17
; Tmp3 ; Tmp2
ldi ldi
; scaled reciprocal for /7 ; (16 bit only, 0/-1 error possible)
YH,0x92 YL,0x49
; Q = A * 0x9249 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 2 lsr r19 ; 2 shifts remaining ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 18) ; R = A - 7*Q; ldi r17,7 ; multiply r19:r18 by 7 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of current Q ; XH:XL ; if (R ; ; cpi brlo subi adiw
now "R": >= 7) R = R - 7; Q = Q + 1; XL,0x07 PC+3 XL,7 YL,1
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_7a -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_9" ;* Divides an unsigned 16 bit word (XH:XL) by 9 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xE38F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xE38F) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_9: push push push push ldi ldi
r2 r19 r18 r17 YH,0xE3 YL,0x8F
; scaled reciprocal for /9
; Q = A * 0xE38F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 9*Q; ldi r17,9 ; multiply r19:r18 by 9 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_9 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_10" ;* Divides an unsigned 16 bit word (XH:XL) by 10 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xCCCD; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xCCCD) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_10: push push push push ldi ldi
r2 r19 r18 r17 YH,0xCC YL,0xCD
; scaled reciprocal for /10
; Q = A * 0xCCCD ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 10*Q; ldi r17,10 ; multiply r19:r18 by 10 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_10 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_11" ;* Divides an unsigned 16 bit word (XH:XL) by 11 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xBA2F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xBA2F) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_11: push push push push ldi ldi
r2 r19 r18 r17 YH,0xBA YL,0x2F
; scaled reciprocal for /11
; Q = A * 0xBA2F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 11*Q; ldi r17,11 ; multiply r19:r18 by 11 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_11 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_12" ;* Divides an unsigned 16 bit word (XH:XL) by 12 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xAAAB; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xAAAB) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_12: push push push push ldi ldi
r2 r19 r18 r17 YH,0xAA YL,0xAB
; scaled reciprocal for /12
; Q = A * 0xAAAB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 12*Q; ldi r17,12 ; multiply r19:r18 by 12 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_12 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_13" ;* Divides an unsigned 16 bit word (XH:XL) by 13 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x9D89; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0x9D8A) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_13: push push push push ldi ldi
r2 r19 r18 r17 YH,0x9D YL,0x8A
; scaled reciprocal for /13
; Q = A * 0x9D8A ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 13*Q; ldi r17,13 ; multiply r19:r18 by 13 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_13 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_14" ;* Divides an unsigned 16 bit word (XH:XL) by 14 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x2493; ;* unsigned int Q; /* the quotient */ ;* ;* Q = (((A * 0x2493) >> 16) + A) >> 4 -> 17 bits reciprocal! ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 40 (w. push/pop = 8 words) ;* cycles: 44 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_14: push push push push ldi ldi
r2 r19 r18 r17 YH,0x24 YL,0x93
; scaled reciprocal for /7, /14
; Q = A * 0x2493 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0
http://avr-asm.tripod.com/div16xx.html (1 of 3)1/20/2009 8:39:37 PM
AVR MATH YX
mul
XL, YL mov r17,r1 mul XH, YL add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL add r17, r0 adc r18, r1 adc r19, r2
; al * bl ; r0 to [rXX] is superfluous ; ah * bl
; bh * al
; Q = Q >> 16: use r19:r18 as word ; Q = Q + A add r18,XL adc r19,XH ; Q = Q >> 4 ror r19 ror r18 lsr r19 ror r18 lsr r19 ror r18 lsr r19 ror r18
; do the last 4 shifts, including ; carry (!) from previous addition
; r19:r18 now "Q" (= result >> 20) ; R = A - 14*Q; ldi r17,14 ; multiply r19:r18 by 14 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_14 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_15" ;* Divides an unsigned 16 bit word (XH:XL) by 15 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x8889; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0x8889) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_15: push push push push
r2 r19 r18 r17
ldi ldi
YH,0x88 YL,0x89
; scaled reciprocal for /15
; Q = A * 0x8889 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 15*Q; ldi r17,15 ; multiply r19:r18 by 15 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_15 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_17" ;* Divides an unsigned 16 bit word (XH:XL) by 17 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xF0F1; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xF0F1) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 44 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_17: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xF0 YL,0xF1
; scaled reciprocal for /17
; Q = A * 0xF0F1 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 17*Q; ldi r17,17 ; multiply r19:r18 by 17 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_17 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_18" ;* Divides an unsigned 16 bit word (XH:XL) by 18 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xE38F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xE38F) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 44 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_18: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xE3 YL,0x8F
; scaled reciprocal for /9 /18
; Q = A * 0xE38F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 18*Q; ldi r17,18 ; multiply r19:r18 by 18 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_18 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_19" ;* Divides an unsigned 16 bit word (XH:XL) by 19 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x6BCA; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0x6BCB) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_19: push push push push
r2 r19 r18 r17
ldi ldi
YH,0x6B YL,0xCB
; scaled reciprocal for /19
; Q = A * 0x6BCB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 19*Q; ldi r17,18 ; multiply r19:r18 by 18 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_19 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_20" ;* Divides an unsigned 16 bit word (XH:XL) by 20 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xCCCD; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xCCCD) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_20: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xCC YL,0xCD
; scaled reciprocal for /10, /20
; Q = A * 0xCCCD ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 20*Q; ldi r17,20 ; multiply r19:r18 by 20 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_20 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_21" ;* Divides an unsigned 16 bit word (XH:XL) by 21 ;* Call with 16 bit number in XH:XL ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* (Equations partly by D. W. Jones) ;* ;* Reciprocal multiplication w. extra precision: ;* (uses correction to achieve the required precision) ;* unsigned int R; /* remainder */ ;* unsigned int long A; /* dividend */ ;* unsigned int long Q; /* quotient */ ;* ;* Q = ((A * 0xC30B) >> 20) ;* ;* /* Q = A/21 or Q+1 = A/21 for all A <= 65535 */ ;* /* correct Q and calculate remainder */ ;* R = A - 21*Q ;* if (R >= 21) { ;* R = R - 21; ;* Q = Q + 1; ;* } ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 40 (w. push/pop = 8 words) ;* cycles: 52 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_21: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xC3 YL,0x0B
; scaled reciprocal for /21 ; (16 bit only, 0/-1 error possible)
; Q = A * 0xC30B ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 21*Q; ldi r17,21 ; multiply r19:r18 by 21 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of current Q ; XH:XL ; if (R ; ; cpi brlo subi adiw
now "R": >= 21) R = R - 21; Q = Q + 1; XL,0x15 PC+3 XL,21 YL,1
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_21 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_22" ;* Divides an unsigned 16 bit word (XH:XL) by 22 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xBA2F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xBA2F) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_22: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xBA YL,0x2F
; scaled reciprocal for /11, /22
; Q = A * 0xBA2F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 22*Q; ldi r17,22 ; multiply r19:r18 by 22 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_22 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_23" ;* Divides an unsigned 16 bit word (XH:XL) by 23 ;* Call with 16 bit number in XH:XL ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* (Equations partly by D. W. Jones) ;* ;* Reciprocal multiplication w. extra precision: ;* (uses correction to achieve the required precision) ;* unsigned int R; /* remainder */ ;* unsigned int long A; /* dividend */ ;* unsigned int long Q; /* quotient */ ;* ;* Q = ((A * 0xB215) >> 20) ;* ;* /* Q = A/23 or Q+1 = A/23 for all A <= 65535 */ ;* /* correct Q and calculate remainder */ ;* R = A - 1*Q ;* if (R >= 23) { ;* R = R - 23; ;* Q = Q + 1; ;* } ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 59 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_23: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xB2 YL,0x15
; scaled reciprocal for /23 ; (16 bit only, 0/-1 error possible)
; Q = A * 0xB215 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 23*Q; ldi r17,23 ; multiply r19:r18 by 23 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of currentQ ; XH:XL ; if (R ; ; cpi brlo subi adiw
now "R": >= 23) R = R - 23; Q = Q + 1; XL,0x17 PC+3 XL,23 YL,1
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_23 -----------------------------------------****
;*************************************************************************** ; macro definition to call/use "division by xx" - module (D16_nn) macro Div16by push r20 ldi r20,@0 call D16_nn pop r20 .endm ;***************************************************************************
;*************************************************************************** ;* ;* Function "D16_nn" ;* Divides an unsigned 16 bit word by [2] -> [23] ;* Note: divisor 2, 4, 8, 16 options are provided for remainder calculation ;* and (for ease-of-use) to cover the complete divisors range (2-23) ;* ;* Call with dividend loaded to XH:XL (high/low bytes) ;* Returns quotient in YH:YL and remainder in XL ;* ;* Usage: define the macro "Div16by" prior to using the function, ;* use macro with divisor as parameter, e.g. "Div16by 17" to ;* divide XH:XL by 17 decimal ;* ;* .macro Div16_by ;* push r20 ;* ldi r20,@0 ;* call D16_nn ;* pop r20 ;* .endm ;* ;* Author: Andreas Lenze ([email protected]) ;* Feb. 2003 ;* Equations mostly by D. W. Jones ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = xxxx ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * scaled_reciprocal) >> 16) >> nn ;* or ;* Q = (((A * scaled_reciprocal) >> 16) + A) >> nn -> for /7 and /14 ;* ;* /* special case: use correction for Q (e.g. for /21, /23) */ ;* if (R >= divisor) ;* R = R - divisor; ;* Q = Q + 1; ;* ;* div. by n: scaled reciprocal: shift count: ;* ;* 2 1 ;* 3 1010101010101011 AAAB 17 ;* 4 2 ;* 5 1100110011001101 CCCD 18 ;* 6 1010101010101011 AAAB 18 ;* 7 10010010010010011 19 -> 17 bits req'd,(MSB=1,rest 2493h) ;* 8 3 ;* 9 1110001110001111 E38F 19 ;* 10 1100110011001101 CCCD 19 ;* 11 1011101000101111 BA2F 19 ;* 12 1010101010101011 AAAB 19 ;* 13 1001110110001010 9D8A 19 ;* 14 10010010010010011 20 -> 17 bits req'd,(MSB=1,rest 2493h) ;* 15 1000100010001001 8889 19 ;* 16 4 ;* 17 1111000011110001 F0F1 20 ;* 18 1110001110001111 E38F 20 ;* 19 0110101111001011 6BCB 19 ;* 20 1100110011001101 CCCD 20 ;* 21 1100001100001011 C30B 20 -> needs correction for accurate result ;* ;*
22 1011101000101111 BA2F 23 1011001000010101 B215
20 20 -> needs correction for accurate
result ;* ;* Uses: high regs: 11 (r16, r17, r18, r19, r20, X, Y, Z) ;* low regs: 3 (r0, r1, r2) ;* regs 16-20 saved, all others destroyed ;* T-flag destroyed (cleared) ;* ;* words: 97 (incl. 5 words for macro) ;* cycles: 85-111 (w. call/ret & macro), typically 102 ;* table bytes: 66 ;* ;* Target: AVR MCUs with hardware multiplier ("mul" instruction and ;* "lpm rd,Z/Z+" functionality required) ;* ;***************************************************************************
D16_nT: ; look-up table for D16_nn: 3 bytes per entry, range for divisor "2" to "23" ; data format: 2 bytes scaled reciprocal (word, high/low), 3rd byte "flags" .cseg .db 0x00, 0xFF, 0x01, 0xAA, 0xAB, 0x01, 0x00, 0xFF, 0x02, 0xCC, 0xCD, 0x02, 0xAA, 0xAB ; by /2
/3
/4
/5
/6
.db 0x02, 0x24, 0x93, 0x13, 0x00, 0xFF, 0x03, 0xE3, 0x8F, 0x03, 0xCC, 0xCD, 0x03, 0xBA ; by
/7
/8
/9
/10
/11
.db 0x2F, 0x03, 0xAA, 0xAB, 0x03, 0x9D, 0x8A, 0x03, 0x24, 0x93, 0x14, 0x88, 0x89, 0x03 ;by
/12
/13
/14
/15
.db 0x00, 0xFF, 0x04, 0xF0, 0xF1, 0x04, 0xE3, 0x8F, 0x04, 0x6B, 0xCB, 0x03, 0xCC, 0xCD ; by /16
/17
/18
/19
/20
.db 0x04, 0xC3, 0x0B, 0x04, 0xBA, 0x2F, 0x04, 0xB2, 0x15, 0x04 ;by /21 /22 /23 D16_nn: push push
r19
; save scrap regs
r18 push push
r17 r16
clt push cpi brsh subi brmi
r20 r20,24 D16_0 r20,2 D16_0
ldi ldi clr mov lsl add add adc
ZH,high(D16_nT*2) ZL,low(D16_nT*2) r2 r1,r20 r20 ; x2 (3 bytes per entry) r20,r1 ; + org value = x3 ZL,r20 ; point Z to divisor's data table position ZH,r2
lpm lpm cpi
YH,Z+ YL,Z+ YL,0xFF
brne mov mov rjmp
D16_1 r19,XH r18,XL D16_2
; ; ; ; ; ; ; ;
pop r20 D16_Err
; clean up stack before exit ; intermediate label (avoid "out of reach" for
D16_0: rjmp
; make sure T-flag is cleared ; save divisor ; exit if divisor > 23
; exit if divisor <= 1
scaled reciprocal for /xx Z now points at flags low byte "FFh" in the scaled_reciprocal data indicates divisor 2, 4, 8, 16 -> no 'mul' req. != FFh -> mul required FFh: no div., shifts only: move input to "result registers" and go to shifts directly (saves ~18 cycles)
brxx) ; Q = A * scaled_reciprocal ; (r19:r18:r17:r16 = XH:XL * YH:YL) D16_1: clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to r16 is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; do the remaining shifts D16_2: lpm r20,Z ; fetch "flag" cpi breq
r20,3 D16_6
; flag = 3 -> 3 normal shifts required ; (div. 8, 9, 10, 11, 12, 13, 15, 19)
cpi breq
r20,4 D16_3
; flag = 4 -> 4 normal shifts required ; (div. 16, 17, 18, 20, 21, 22, 23)
cpi breq
r20,2 D16_7
; flag = 2 -> 2 normal shifts required ; (div. 4, 5, 6)
cpi breq
r20,1 D16_8
; flag = 1 -> 1 normal shift required ; (div. 2, 3)
cpi breq
r20,0x14 D16_5
; flag = 4spec -> 4 special shifts required ; (div. 14, extra addition, 1st shift w. carry)
cpi breq rjmp
r20,0x13 D16_4 D16_Err
; flag = 3spec -> 3 special shifts required ; (div. 7, extra addition, 1st shift w. carry) ; no valid flags, exit
; Q = Q >> 4 D16_3: swap r18 swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 rjmp D16_9
http://avr-asm.tripod.com/div16xx.html (2 of 3)1/20/2009 8:39:37 PM
; 4 normal shifts
AVR MATH YX
; Q = (Q + A) >> 3-4 D16_4: set D16_5: add r18,XL adc r19,XH ror r19 ror r18 D16_6: lsr r19 ror r18 D16_7: lsr r19 ror r18 brts D16_9 D16_8: lsr r19 ror r18
; (Q + A) ; 3-4 "special" shifts, include ; carry from previous addition into 1st shift
; if T-flag set, skip this shift
; r19:r18 now "Q" (= result >> yy) ; R = A - xx*Q; D16_9: pop r16 ; multiply r19:r18 by divisor mul sub clr movw
r18, r16 XL,r0 XH YL,r18
; al * bl
; make copy of Q
; XL = "R" (remainder) ; /* use correction - can be omitted if /21, /23 are not used */ ; if (R >= divisor) ; R = R - divisor; ; Q = Q + 1; cp XL,r16 brlo PC+3 sub XL,r16 adiw YL,1 ; YH:YL = "Q" (quotient, result) D16_Err:clt ; make sure T-flag is cleared pop r16 ; restore regs pop r17 pop r18 pop r19 ret ;**** End of function D16_nn -------------------------------------------****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/div16xx.html (3 of 3)1/20/2009 8:39:37 PM
AVR MATH YX
The AVR Assembler Site
24 BIT BY 24 BIT DIVISION ROUTINE HOME RETRO_DAN ;******** div24u *********** ;*Division 24/24 ;* Dividend(dvd) ;* Result = --------------;* Divisor(dvr) ;* ;*
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200
.def .def .def .def .def .def .def .def .def .def .def .def
MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128
rem24L =r3 rem24M =r4 rem24H =r5 result24L =r9 result24M =r10 result24H =r11 dvd24L =r9 dvd24M =r10 dvd24H =r11 dvr24L =r12 dvr24M =r13 dvr24H =r14
;*Unsigned* Division 24bit/24bit
SQRT16 div24u: clr rem24L ;clear remainder Low byte clr rem24M ;clear remainder mid byte sub rem24H,rem24H ;clear remainder High byte and
MATH 202 MATH 202 DEC ASCII
carry ldi rLoopCnt1,25 ;init loop counter
INT ASCII d16u_1: rol dvd24L ;shift left dividend rol dvd24M rol dvd24H dec rLoopCnt1 ;decrement counter brne d16u_2 ;if done ret ; return
HX2ASC AVG8 222 FFT7 COPY 102 LPM 108
d16u_2: rol rem24L ;shift dividend into remainder rol rem24M rol rem24H sub rem24L,dvr24L ;remainder = remainder - divisor sbc rem24M,dvr24M ; sbc rem24H,dvr24H brcc d16u_3 ;if result negative add rem24L,dvr24L ; restore remainder adc rem24M,dvr24M adc rem24H,dvr24H clc ; clear carry to be shifted into result rjmp d16u_1 ;else d16u_3: sec ; set carry to be shifted into result rjmp d16u_1
EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
ret
UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
Programming the AVR Microcontrollers in Machine Language
I2C/TWI 128 I2C/TWI AT8
AVR << Prev | Ring Hub | Join | Rate| Next >>
DALLAS-1W DALLAS CRC © WebRing Inc.
ETHNET 8019
Search
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/div2424.html (1 of 2)1/20/2009 8:40:09 PM
AVR MATH YX
http://avr-asm.tripod.com/div2424.html (2 of 2)1/20/2009 8:40:09 PM
AVR MATH YX
The AVR Assembler Site
32 BIT BY 16 BIT DIVISION ROUTINE HOME RETRO_DAN ASM FORUM
;divide r21:r18/refH:refL result in XH: XL
ASM MATH
__DIVD21U: CLR XL CLR XH CLR R0 CLR R1 LDI R17,32 __DIVD21U1: LSL R18 ROL R19 ROL R20 ROL R21 ROL XL ROL XH ROL R0 ROL R1 SUB XL,scaleL SBC XH,scaleH SBC R0,zeroreg SBC R1,zeroreg BRCC __DIVD21U2 ADD XL,scaleL ADC XH,scaleH ADC R0,zeroreg ADC R1,zeroreg RJMP __DIVD21U3 __DIVD21U2: SBR R18,1 __DIVD21U3: DEC R17 BRNE __DIVD21U1 mov XL, r19 mov XH, r18 ; result in X
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102
ret
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
Programming the AVR Microcontrollers in Machine Language
UART 305
AVR << Prev | Ring Hub | Join | Rate| Next >>
UART 128 UART BUFF USB 232 © WebRing Inc.
AVR ISP
Search
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232, RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232, RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232, RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/div3216.html (1 of 2)1/20/2009 8:40:41 PM
AVR MATH YX
http://avr-asm.tripod.com/div3216.html (2 of 2)1/20/2009 8:40:41 PM
AVR MATH YX
The AVR Assembler Site
FLOATING POINT MATH HOME RETRO_DAN ;*************************************************************************** ; ; File Name :'Main.asm" ; Title :Matmatikai rutinok, test verzio ; Date :2003.07.16. ; Version :1.0.0 ; Support telephone :+36-70-333-4034 ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ;*************************************************************************** ; D E S C R I P T I O N ; ; ;*************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ------------------------------------; 0.01 2003.07.16 VFX Creation, mult ; 0.02 2004.03.30 VFX Add float add & sub ; ; ;*************************************************************************** ;Hardware ;*************************************************************************** ;* ;* f=external 16MHz (t=-.--ns) ;* ;*************************************************************************** ; ; ; .include "m128def.inc"
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
;*************************************************************************** ;* Const Def
SER EPROM DFLASH AT45 FLASH CARD
;************************************************************************** ;* Hardware Def. ;
VFX SMIL VFX MEM
;*************************************************************************** ;** VARIABLES .DSEG
SORT 220 CRC 236 XMODEM REC
;*************************************************************************** .ESEG
UART 304 UART 305
;*************************************************************************** ;**** I N T E R R U P T S ;**** ;*************************************************************************** .CSEG
UART 128 UART BUFF USB 232 AVR ISP
RESET:
ISP 2313
CLI
ISP 1200
ldi out ldi out
AVR SPI I2C 300
;GLOBAL INTERRUP DIS.
R16, high(RAMEND) SPH,R16 R16, low(RAMEND) SPL,R16
;setup stack
I2C 302 I2C TWI26
;PI/2 = 81 49 0F DA A2 ;1,570796326734125614166259765625
I2C/TWI 128 I2C/TWI AT8
ldi ldi ldi ldi ldi mov mov mov mov mov
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
R24,0x81 R23,0xC9 R22,0x0F R21,0xDA R20,0xA2 R6,R24 R5,R23 R4,R22 R3,R21 R2,R20
Sign bit!!!
;exponens ;mantissa
; const ;0,79411764699034392833709716796875
THERM 232 IRD 410
R24,0x80 R23,0x4b R22,0x4b R21,0x4b R20,0x4b
rcall
multiply
rcall
addition
LCD HD44
ldi ldi ldi ldi ldi
LCD 2313 LCD44 2313
;exponens ;mantissa
KBD 240 MUX 242
;
KBD PS2 KBD PC/128 veges:
PS2 EMU
rjmp veges
BOOT MG8 BOOT DR8 ; ; ; ; ; ; ; ; ; ; ; ; ;
ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
----------------------------Prepare to multiply or divide ----------------------------This routine is called in succession from multiply and divide to prepare two mantissas by setting the leftmost bit that is used for the sign. m1: R25, R24:R21 m2: R6, R5:R2 T flag = Sign of result R6,R24 corrected exponent R5,R23 restored sign bit of mantissa cycles +
(RET) =
Cycles
PREP_Mul_Div: mov eor bst
ATMEL CORP AVR BUTTERFLY
;T flag = result sign bit
ldi
R16,0xA0
;Binary point offset is 0x20 to
ldi
R17,0x80
;MSB sign bit
AVR BOOK
R16,R5 R16,R23 R16,7
integer number
tst brne add rjmp
R24 PREP_MD01 ;First number is floating point format R24,R16 PREP_MD02
PREP_MD01: or
R23,R17
;restore msb bit
PREP_MD02: tst brne add rjmp
R6 PREP_MD03 R6,R16 PREP_MD04
;Second number is floating point format
PREP_MD03: or
R5,R17
;restore msb bit
sub sub
R24,R17 R6,R17
;shift zero point by 0x80 (back
PREP_MD04:
to 2's complement) ret ; -----------------------------; THE 'MULTIPLICATION' OPERATION ; -----------------------------; (offset: $04 'multiply') ; ; m1: R6, R5:R2 ; m2: R24, R23:R20 ; ------------------; Res: R6, R5:R2 ; ; cycles + (RET) = Cycles ; multiply: rcall PREP_Mul_Div mov or or or breq mov or or or breq
R0,R2 R0,R3 R0,R4 R0,R5 Res_Zero R0,R20 R0,R21 R0,R22 R0,R23 Res_Zero
rcall clr rcall sub
mult32
brcs add brvs ldi sub
NumberTooBig R6,R24 NumberTooBig R16,0x80 R6,R16
rcall brcs
Round NumberTooBig
R7 Normalize R6,R16
;shift exponent by
normalized value
ldi bld and
;2^x *2^y = 2^(x+y)
;set offset by 0x80
R17,0xFF R17,7 R5,R17
;get result sign bit ;set result sign bit
clc ret NumberTooBig: sec ret Res_Zero: clr clr movw clr clc ret
R2 R3 R4,R2 R6
;*************************************************** ;* Mutiply 32x32 -> 64 bit ;* ;* R23:R20 x R5:R2 -> R15:R8 ;* ;* 86 cycles + 4 (RET) = 90 Cycles ;* mult32: clr R16 mul R20,R2 movw R8,R0 clr R10 clr R11 movw R12,R10 movw R14,R10 mul R21,R2 add R9,R0 adc R10,R1 mul R22,R2 add R10,R0 adc R11,R1 mul R23,R2 add R11,R0 adc R12,R1 mul add adc adc adc adc mul add adc adc adc mul add adc adc mul add adc
R20,R3 R9,R0 R10,R1 R11,R16 R12,R16 R13,R16 R21,R3 R10,R0 R11,R1 R12,R16 R13,R16 R22,R3 R11,R0 R12,R1 R13,R16 R23,R3 R12,R0 R13,R1
mul add adc adc adc adc mul add adc adc adc mul add adc adc mul add adc
R20,R4 R10,R0 R11,R1 R12,R16 R13,R16 R14,R16 R21,R4 R11,R0 R12,R1 R13,R16 R14,R16 R22,R4 R12,R0 R13,R1 R14,R16 R23,R4 R13,R0 R14,R1
mul add adc adc adc adc mul add adc adc adc mul add adc adc mul add adc ret
R20,R5 R11,R0 R12,R1 R13,R16 R14,R16 R15,R16 R21,R5 R12,R0 R13,R1 R14,R16 R15,R16 R22,R5 R13,R0 R14,R1 R15,R16 R23,R5 R14,R0 R15,R1
;********************************************************** ; R15:R8:R7 -> R15:R12 ; R16 - 64-exponent Normalize: ldi R17,64 ;max 64 bitet kell vegigrotalni Norm0: tst R15 brne Norm1 mov R15,R14 mov R14,R13 mov R13,R12 mov R12,R11 mov R11,R10 mov R10,R9 mov R9,R8 mov R8,R7 clr R7 subi R17,8 cpi R17,8 brne Norm0 Norm1: ;legnagyobb helyiertek felrotalasa bit7-ig sbrc rjmp lsl rol rol rol rol rol rol rol rol dec brne
R15,7 Norm2 R7 R8 R9 R10 R11 R12 R13 R14 R15 R17 Norm1
Norm2: ldi sub
R16,64 R16,R17 ;R16-ban az
exponens ret
; ------------------------------; THE 'PREPARE TO ADD' SUBROUTINE ; ------------------------------; This routine is called twice by addition to prepare the two numbers. ; The sign bit is tested before being set to the implied state. ; Negative numbers are twos complemented. ; ; m1: R6, R5:R2 -> R6, R7:R5:R2 ; m2: R24, R23:R20 -> R24, R25:R23:R20 ; R25,R7 -> sign ; PREP_ADD: clr R25 clr R7 ldi R16,0x80 tst brne mov
R24 Prep_Add1 R24,R16
;ide jon majd a normalas R23:R20 rjmp
M1Pos
Prep_Add1: bst or brtc
R23,7 R23,R16 M1Pos
;test the sign bit ;set it to implied state ;jump if positive number
NEG_M1: clr clr movw movw
R8 R9 R10,R8 R12,R8
;clear result regs
sub sbc
R8,R20 R9,R21
;complement ;add in initial carry
sbc sbc sbc movw movw mov
R10,R22 R11,R23 R12,R13
or from prev operation
R20,R8 R22,R10 R25,R12
M1Pos: tst brne mov
R6 Prep_Add2 R6,R16
;ide jon majd a normalas R5:R2 rjmp M2Pos Prep_Add2: bst or brtc
R5,7 R5,R16
;test the sign bit ;set it to implied state ;jump if positive number
M2Pos
NEG_M2: clr clr movw movw
R8 R9 R10,R8 R12,R8
;clear result regs
sub sbc
R8,R2 R9,R3
;complement ;add in initial carry
sbc sbc sbc movw movw mov
R10,R4 R11,R5 R12,R13
or from prev operation
R2,R8 R4,R10 R7,R12
M2Pos: ret
;return
; ------------------------; THE 'SHIFT FP Right' SUBROUTINE ; ------------------------; In: mantissa R7:R5:R2 ; Exponent : R6 ; Shift right by R16 ; ; Out: R17,R15,R14,R13,R12,R11,R10,R9,R8,R7 ; s s s s s m m m m SHIFT_FP: movw R12,R2 movw R14,R4 mov R17,R7 clr R7 clr R8 clr R9 movw R10,R8 tst brne ret
g
R16 Shift_fp1 ;diff
== 0 no rota Shift_fp1: cpi brcc
R16,0x21 ADDEND_0
cpi brcs mov mov mov mov mov mov mov mov mov bst
R16,8 ONE_SHIFT R7,R8 R8,R9 R9,R10 R10,R11 R11,R12 R12,R13 R13,R14 R14,R15 R15,R17 R17,7
clr brtc ser R16,8 rjmp
R17 SHIFT_FP2 R17
;diff>33 bit ;we add 0 to 1st param
EIGHT_SHIFT:
;negative
number?
SHIFT_FP2:
ONE_SHIFT:
subi
bst
EIGHT_SHIFT R17,7
lsr ror ror ror ror ror ror ror ror ror bld
;store sign bit R17 R15 R14 R13 R12 R11 R10 R9 R8 R7 R17,7
;set back to
sign bit dec brne ret
R16 ONE_SHIFT
ADDEND_0: clr clr clr movw movw movw movw ret
; ; ; ;
R7 R8 R9 R10,R8 R12,R8 R14,R8 R16,R8
--------------------------THE 'SUBTRACTION' OPERATION --------------------------(offset: $03 'subtract')
; m1: R6, R5:R2 ; m2: R24, R23:R20 ; ------------------; Res: R6, R5:R2 ; ; Subtraction is done by switching the sign byte/bit of the second ; number and continuing into addition. subtract: tst brne mov or or or brne ret
R24 Sub_NoZero R0,R20 R0,R21 R0,R22 R0,R23 addition ;x - 0 = x
Sub_NoZero: ori
R23,0x80
;make to negative
; -----------------------; THE 'ADDITION' OPERATION ; -----------------------; (offset: $0F 'addition') ; ; m1: R6, R5:R2 ; m2: R24, R23:R20 ; ------------------; Res: R6, R5:R2 ; ; cycles + (RET) = Cycles ; addition: rcall PREP_ADD cp R24,R6
;exp.
M1 < M2? brcc
SHIFT_LEN
;to SHIFT_LEN
movw
R8,R2
; exchange M1 &
movw movw
R2,R20 R20,R8
movw movw movw
R8,R4 R4,R22 R22,R8
movw movw movw
R8,R6 R6,R24 R24,R8
M2
SHIFT_LEN: mov sub R6
R16,R24 R16,
;length of shift mov rcall
R6,R24 SHIFT_FP ;
R17,R15,R14,R13,R12,R11,R10,R9,R8,
; ; +
s m m m m m R25,R23,R22,R21,R20 0
R7 m 0
m 0
m 0
g
0 ;--------------------------------------; R17,R15,R14,R13,R12,R11,R10,R9,R8, R7 add adc adc adc adc brlt
R12,R20 R13,R21 R14,R22 R15,R23 R17,R25 NoAdd_Overf1
inc brne rjmp
R6 Add_Rota Add_Rep_6
ldi rcall
R16,1 ONE_SHIFT
Add_Rota:
NoAdd_Overf1: mov bst
R20,R17 R17,7
;store sign ;sign =
positive? brtc clr clr movw sub mov movw sbc sbc movw
Add_Pos R0 R1
;negate
R2,R0 R0,R7 R7,R0 R0,R2 R0,R8 R1,R9 R8,R0
movw sbc sbc movw
R0,R2
movw sbc sbc movw
R0,R2
movw sbc sbc movw
R0,R2
R0,R10 R1,R11 R10,R0
R0,R12 R1,R13 R12,R0
R0,R14 R1,R15 R14,R0
mov sbc mov
R0,R2 R0,R17 R17,R0
tst breq inc brne rjmp
R17
Add_Pos: Add_Norm R6 Add_Rota1 Add_Rep_6
Add_Rota1: ldi rcall rjmp
R16,1 ONE_SHIFT Add_Pos
rcall
Normalize
bst brts
R15,7 Add_Norm1
rjmp
Res_Zero
sub breq brcs
R6,R16 Add_Rep_6 Add_Rep_6
rcall brcs
Round Add_Rep_6
bst brts ldi and
R20,7 Add_NegResult R16,0x7F R5,R16
Add_Norm:
;ha 7. =0 ,akkor nincs mit tenni
Add_Norm1:
;make pos sign
Add_NegResult: clc ret Add_Rep_6: sec
;
overflow error ret
Round: movw movw
R4,R14 R2,R12
;ide jon majd a kerekites mov or or or brne clr
R0,R2 R0,R3 R0,R4 R0,R5 Round1 R6
Round1: clc ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data http://avr-asm.tripod.com/float128.html (1 of 2)1/20/2009 8:41:21 PM
AVR MATH YX
address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/float128.html (2 of 2)1/20/2009 8:41:21 PM
AVR MATH YX
The AVR Assembler Site
16 SQUARE ROOT ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; ***************************************************************************** ;* ;* sqrt16 V 1.00 ;* ;* r16 - SQUARE LOW BYTE ;* r17 - SQUARE HIGH BYTE ;* ;* r18,19 - SQRT, returned in r16 ;* ;* Low registers used : None ;* High registers used : r16 - r19, r24, r25, r26 ;* ; ***************************************************************************** .area text _sqrt16:: st -y,r18 st -y,r19 st -y,r24 st -y,r25 st -y,r26 ldi r24,0 ; remainder low ldi r25,0 ; remainder high ldi r18,0 ; divisor low ldi r19,0 ; divisor high ldi r26,8 ; loop count sqrt16loop: lsl r18 ; divisor <<= 1 rol r19 lsl r16 ; shift two msb's into remainder rol r17 rol r24 rol r25 lsl r16 rol r17 rol r24 rol r25 cp r18,r24 ; divisor < remainder ? cpc r19,r25 brcc sqrt16bitdone inc r18 ; divisor++, lsb = 0 sub r24,r18 ; remainder -= divisor sbc r25,r19 inc r18 ; divisor++, bit_1 = 0 sqrt16bitdone: dec r26 ; decrement loop count brne sqrt16loop ; branch if not done lsr r19 ; root = divisor / 2 ror r18 mov r16,r18 ld r26,y+ ld r25,y+ ld r24,y+ ld r19,y+ ld r18,y+ ret
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Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/ loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/ loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/ loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/sqrt16.html (1 of 2)1/20/2009 8:41:53 PM
AVR MATH YX
http://avr-asm.tripod.com/sqrt16.html (2 of 2)1/20/2009 8:41:53 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BCD MATH (AVR 204) HOME RETRO_DAN ;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************ ;* ;* Title: BCD Arithmetics ;* Version: 1.1 ;* Last updated: 97.07.04 ;* Target: AT90Sxxxx (All AVR Devices) ;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application Note lists subroutines for the following Binary Coded ;* Decimal arithmetic applications: ;* ;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x) ;* Binary 8 to BCD Conversion ;* BCD to Binary 16 Conversion ;* BCD to Binary 8 Conversion ;* 2-Digit BCD Addition ;* 2-Digit BCD Subtraction ;* ;***************************************************************************
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128
.include "8515def.inc"
SQRT16 MATH 202
rjmp
RESET
;reset handle
MATH 202 ;*************************************************************************** ;* ;* "bin2BCD16" - 16-bit Binary to BCD conversion ;* ;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0). ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2. ;* ;* Number of words :25 ;* Number of cycles :751/768 (Min/Max) ;* Low registers used :3 (tBCD0,tBCD1,tBCD2) ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a) ;* Pointers used :Z ;* ;***************************************************************************
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
;***** Subroutine Register Variables
VFX MEM
.equ .equ
AtBCD0 AtBCD2
=13 =15
;address of tBCD0 ;address of tBCD1
.def .def .def .def .def .def .def
tBCD0 tBCD1 tBCD2 fbinL fbinH cnt16a tmp16a
=r13 =r14 =r15 =r16 =r17 =r18 =r19
;BCD value digits 1 and 0 ;BCD value digits 3 and 2 ;BCD value digit 4 ;binary value Low byte ;binary value High byte ;loop counter ;temporary value
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
;***** Code
AVR ISP
bin2BCD16: ldi clr clr clr clr bBCDx_1:lsl rol rol rol rol dec brne ret
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
cnt16a,16 tBCD2 tBCD1 tBCD0 ZH fbinL fbinH tBCD0 tBCD1 tBCD2 cnt16a bBCDx_2
;Init loop counter ;clear result (3 bytes)
;clear ZH (not needed for AT90Sxx0x) ;shift input value ;through all bytes ;
;decrement loop counter ;if counter not zero ; return
DALLAS CRC bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1 bBCDx_3: ld tmp16a,-Z ;get (Z) with pre-decrement ;---------------------------------------------------------------;For AT90Sxx0x, substitute the above line with: ; ; dec ZL ; ld tmp16a,Z ; ;---------------------------------------------------------------subi tmp16a,-$03 ;add 0x03 sbrc tmp16a,3 ;if bit 3 not clear st Z,tmp16a ; store back ld tmp16a,Z ;get (Z) subi tmp16a,-$30 ;add 0x30 sbrc tmp16a,7 ;if bit 7 not clear st Z,tmp16a ; store back cpi ZL,AtBCD0 ;done all three? brne bBCDx_3 ;loop again if not rjmp bBCDx_1
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
;*************************************************************************** ;* ;* "bin2BCD8" - 8-bit Binary to BCD conversion ;* ;* This subroutine converts an 8-bit number (fbin) to a 2-digit ;* BCD number (tBCDH:tBCDL). ;* ;* Number of words :6 + return ;* Number of cycles :5/50 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (fbin/tBCDL,tBCDH) ;* ;* Included in the code are lines to add/replace for packed BCD output. ;* ;***************************************************************************
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE
;***** Subroutine Register Variables
STH-11
.def .def .def
ATMEL CORP AVR BUTTERFLY
fbin tBCDL tBCDH
=r16 =r16 =r17
;8-bit binary value ;BCD result MSD ;BCD result LSD
;***** Code
AVR BOOK
bin2bcd8: clr tBCDH ;clear result MSD bBCD8_1:subi fbin,10 ;input = input - 10 brcs bBCD8_2 ;abort if carry set inc tBCDH ;inc MSD ;--------------------------------------------------------------------------; ;Replace the above line with this one ; ;for packed BCD output ; subi tBCDH,-$10 ;tBCDH = tBCDH + 10 ;--------------------------------------------------------------------------rjmp bBCD8_1 ;loop again bBCD8_2:subi fbin,-10 ;compensate extra subtraction ;--------------------------------------------------------------------------; ;Add this line for packed BCD output ; add fbin,tBCDH ;--------------------------------------------------------------------------ret
;*************************************************************************** ;* ;* "BCD2bin16" - BCD to 16-Bit Binary Conversion ;* ;* This subroutine converts a 5-digit packed BCD number represented by ;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL). ;* MSD of the 5-digit number must be placed in the lowermost nibble of fBCD2. ;* ;* Let "abcde" denote the 5-digit number. The conversion is done by ;* computing the formula: 10(10(10(10a+b)+c)+d)+e. ;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation ;* which is repeated four times during the computation. ;* ;* Number of words :30 ;* Number of cycles :108 ;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH) ;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder) ;* ;*************************************************************************** ;***** "mul10a"/"mul10b" Subroutine Register Variables .def .def .def
copyL copyH mp10L
=r12 =r13 =r14
;temporary register ;temporary register ;Low byte of number to be multiplied by
.def
mp10H
=r15
;High byte of number to be multiplied
.def
adder
=r19
;value to add after multiplication
10 by 10
;***** Code mul10a:
;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high
swap mul10b:
adder ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
mov mov lsl rol lsl rol lsl rol lsl rol add adc andi add brcc inc m10_1:
copyL,mp10L copyH,mp10H mp10L mp10H copyL copyH copyL copyH copyL copyH mp10L,copyL mp10H,copyH adder,0x0f mp10L,adder m10_1 mp10H ret
nibble
nibble ;make copy ;multiply original by 2 ;multiply copy by 2 ;multiply copy by 2 (4) ;multiply copy by 2 (8) ;add copy to original ;mask away upper nibble of adder ;add lower nibble of adder ;if carry not cleared ; inc high byte
;***** Main Routine Register Variables .def
tbinL
=r14
;Low byte of binary result (same as
.def
tbinH
=r15
;High byte of binary result (same as
.def .def .def
fBCD0 fBCD1 fBCD2
=r16 =r17 =r18
;BCD value digits 1 and 0 ;BCD value digits 2 and 3 ;BCD value digit 5
mp10L) mp10H)
;***** Code BCD2bin16: andi clr mov mov rcall mov rcall mov rcall mov rcall ret
fBCD2,0x0f mp10H mp10L,fBCD2 adder,fBCD1 mul10a adder,fBCD1 mul10b adder,fBCD0 mul10a adder,fBCD0 mul10b
;mask away upper nibble of fBCD2 ;mp10H:mp10L = a ;mp10H:mp10L = 10a+b ;mp10H:mp10L = 10(10a+b)+c ;mp10H:mp10L = 10(10(10a+b)+c)+d ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
;*************************************************************************** ;* ;* "BCD2bin8" - BCD to 8-bit binary conversion ;* ;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an ;* 8-bit number (tbin). ;* ;* Number of words :4 + return ;* Number of cycles :3/48 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (tbin/fBCDL,fBCDH) ;* ;* Modifications to make the routine accept a packed BCD number is indicated ;* as comments in the code. If the modifications are used, fBCDH shall be ;* loaded with the BCD number to convert prior to calling the routine. ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
tbin fBCDL fBCDH
=r16 =r16 =r17
;binary result ;lower digit of BCD input ;higher digit of BCD input
;***** Code BCD2bin8: ;-------------------------------------------------------------------------;| ;For packed BCD input, add these two lines ;| mov tbin,fBCDH ;copy input to result ;| andi tbin,$0f ;clear higher nibble of result ;-------------------------------------------------------------------------BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1 brcs BCDb8_1 ;if carry not set ;-------------------------------------------------------------------------;| ;For packed BCD input, replace the above ;| ;two lines with these. ;| subi fBCDH,$10 ;MSD = MSD - 1 ;| brmi BCDb8_1 ;if Zero flag not set ;-------------------------------------------------------------------------subi tbin,-10 ; result = result + 10 rjmp BCDb8_0 ; loop again BCDb8_1:ret ;else return
;*************************************************************************** ;* ;* "BCDadd" - 2-digit packed BCD addition ;* ;* This subroutine adds the two unsigned 2-digit BCD numbers ;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow ;* carry in "BCD2". ;* ;* Number of words :19 ;* Number of cycles :17/20 (Min/Max) ;* Low registers used :None ;* High registers used :3 (BCD1,BCD2,tmpadd) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
BCD1 BCD2 tmpadd
=r16 =r17 =r18
;BCD input value #1 ;BCD input value #2 ;temporary register
;***** Code BCDadd: ldi add clr brcc ldi add_0: add brhs subi rjmp add_1: add_2: add brcs sbrs subi add_3: add_4: ret
tmpadd,6 ;value to be added later BCD1,BCD2 ;add the numbers binary BCD2 ;clear BCD carry add_0 ;if carry not clear BCD2,1 ; set BCD carry brhs add_1 ;if half carry not set BCD1,tmpadd ; add 6 to LSD add_2 ; if half carry not set (LSD <= 9) BCD1,6 ; restore value add_2 ;else add BCD1,tmpadd ; add 6 to LSD swap tmpadd BCD1,tmpadd ;add 6 to MSD add_4 ;if carry not set (MSD <= 9) BCD2,0 ; if previous carry not set BCD1,$60 ; restore value ret ;else ldi BCD2,1 ; set BCD carry
;*************************************************************************** ;* ;* "BCDsub" - 2-digit packed BCD subtraction ;* ;* This subroutine subtracts the two unsigned 2-digit BCD numbers ;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and ;* the underflow carry in "BCDb". ;* ;* Number of words :13 ;* Number of cycles :12/17 (Min/Max) ;* Low registers used :None ;* High registers used :2 (BCDa,BCDb) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def
BCDa BCDb
=r16 =r17
;BCD input value #1 ;BCD input value #2
;***** Code BCDsub: sub clr brcc ldi sub_0: subi sub_1: ret subi ldi brcc ldi sub_2:
BCDa,BCDb BCDb sub_0 BCDb,1 brhc sub_1 BCDa,$06 sbrs BCDb,0 BCDa,$60 BCDb,1 sub_2 BCDb,1 ret
;subtract the numbers binary ;if carry not clear ; store carry in BCDB1, bit 0 ;if half carry not clear ; LSD = LSD - 6 ;if previous carry not set ; return ;subtract 6 from MSD ;set underflow carry ;if carry not clear ; clear underflow carry
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct operation. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ldi out ldi out
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)
;***** Convert 54,321 to 2.5-byte packed BCD format ldi ldi rcall
fbinL,low(54321) fbinH,high(54321) bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321
;***** Convert 55 to 2-byte BCD ldi rcall
fbin,55 bin2BCD8
;result: tBCDH:tBCDL = 0505
;***** Convert $065535 to a 16-bit binary number ldi fBCD2,$06 ldi fBCD1,$55 ldi fBCD0,$35 rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535) ;***** Convert $0403 (43) to an 8-bit binary number ldi fBCDL,3 ldi fBCDH,4 rcall BCD2bin8 ;result: tbin = $2b (43) ;***** Add BCD numbers 51 and 79 ldi BCD1,$51 ldi BCD2,$79 rcall BCDadd ;result: BCD2:BCD1=$0130 ;***** Subtract BCD numbers 72 - 28 ldi BCDa,$72 ldi BCDb,$28 rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44 ;***** Subtract BCD numbers 0 - 90 ldi BCDa,$00 ldi BCDb,$90 rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that http://avr-asm.tripod.com/avr204.html (1 of 2)1/20/2009 8:42:33 PM
16 BIT MATH (AVR 202)
share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr204.html (2 of 2)1/20/2009 8:42:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BCD MATH (AVR 204) HOME RETRO_DAN ;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************ ;* ;* Title: BCD Arithmetics ;* Version: 1.1 ;* Last updated: 97.07.04 ;* Target: AT90Sxxxx (All AVR Devices) ;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application Note lists subroutines for the following Binary Coded ;* Decimal arithmetic applications: ;* ;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x) ;* Binary 8 to BCD Conversion ;* BCD to Binary 16 Conversion ;* BCD to Binary 8 Conversion ;* 2-Digit BCD Addition ;* 2-Digit BCD Subtraction ;* ;***************************************************************************
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128
.include "8515def.inc"
SQRT16 MATH 202
rjmp
RESET
;reset handle
MATH 202 ;*************************************************************************** ;* ;* "bin2BCD16" - 16-bit Binary to BCD conversion ;* ;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0). ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2. ;* ;* Number of words :25 ;* Number of cycles :751/768 (Min/Max) ;* Low registers used :3 (tBCD0,tBCD1,tBCD2) ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a) ;* Pointers used :Z ;* ;***************************************************************************
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
;***** Subroutine Register Variables
VFX MEM
.equ .equ
AtBCD0 AtBCD2
=13 =15
;address of tBCD0 ;address of tBCD1
.def .def .def .def .def .def .def
tBCD0 tBCD1 tBCD2 fbinL fbinH cnt16a tmp16a
=r13 =r14 =r15 =r16 =r17 =r18 =r19
;BCD value digits 1 and 0 ;BCD value digits 3 and 2 ;BCD value digit 4 ;binary value Low byte ;binary value High byte ;loop counter ;temporary value
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
;***** Code
AVR ISP
bin2BCD16: ldi clr clr clr clr bBCDx_1:lsl rol rol rol rol dec brne ret
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
cnt16a,16 tBCD2 tBCD1 tBCD0 ZH fbinL fbinH tBCD0 tBCD1 tBCD2 cnt16a bBCDx_2
;Init loop counter ;clear result (3 bytes)
;clear ZH (not needed for AT90Sxx0x) ;shift input value ;through all bytes ;
;decrement loop counter ;if counter not zero ; return
DALLAS CRC bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1 bBCDx_3: ld tmp16a,-Z ;get (Z) with pre-decrement ;---------------------------------------------------------------;For AT90Sxx0x, substitute the above line with: ; ; dec ZL ; ld tmp16a,Z ; ;---------------------------------------------------------------subi tmp16a,-$03 ;add 0x03 sbrc tmp16a,3 ;if bit 3 not clear st Z,tmp16a ; store back ld tmp16a,Z ;get (Z) subi tmp16a,-$30 ;add 0x30 sbrc tmp16a,7 ;if bit 7 not clear st Z,tmp16a ; store back cpi ZL,AtBCD0 ;done all three? brne bBCDx_3 ;loop again if not rjmp bBCDx_1
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
;*************************************************************************** ;* ;* "bin2BCD8" - 8-bit Binary to BCD conversion ;* ;* This subroutine converts an 8-bit number (fbin) to a 2-digit ;* BCD number (tBCDH:tBCDL). ;* ;* Number of words :6 + return ;* Number of cycles :5/50 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (fbin/tBCDL,tBCDH) ;* ;* Included in the code are lines to add/replace for packed BCD output. ;* ;***************************************************************************
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE
;***** Subroutine Register Variables
STH-11
.def .def .def
ATMEL CORP AVR BUTTERFLY
fbin tBCDL tBCDH
=r16 =r16 =r17
;8-bit binary value ;BCD result MSD ;BCD result LSD
;***** Code
AVR BOOK
bin2bcd8: clr tBCDH ;clear result MSD bBCD8_1:subi fbin,10 ;input = input - 10 brcs bBCD8_2 ;abort if carry set inc tBCDH ;inc MSD ;--------------------------------------------------------------------------; ;Replace the above line with this one ; ;for packed BCD output ; subi tBCDH,-$10 ;tBCDH = tBCDH + 10 ;--------------------------------------------------------------------------rjmp bBCD8_1 ;loop again bBCD8_2:subi fbin,-10 ;compensate extra subtraction ;--------------------------------------------------------------------------; ;Add this line for packed BCD output ; add fbin,tBCDH ;--------------------------------------------------------------------------ret
;*************************************************************************** ;* ;* "BCD2bin16" - BCD to 16-Bit Binary Conversion ;* ;* This subroutine converts a 5-digit packed BCD number represented by ;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL). ;* MSD of the 5-digit number must be placed in the lowermost nibble of fBCD2. ;* ;* Let "abcde" denote the 5-digit number. The conversion is done by ;* computing the formula: 10(10(10(10a+b)+c)+d)+e. ;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation ;* which is repeated four times during the computation. ;* ;* Number of words :30 ;* Number of cycles :108 ;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH) ;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder) ;* ;*************************************************************************** ;***** "mul10a"/"mul10b" Subroutine Register Variables .def .def .def
copyL copyH mp10L
=r12 =r13 =r14
;temporary register ;temporary register ;Low byte of number to be multiplied by
.def
mp10H
=r15
;High byte of number to be multiplied
.def
adder
=r19
;value to add after multiplication
10 by 10
;***** Code mul10a:
;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high
swap mul10b:
adder ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
mov mov lsl rol lsl rol lsl rol lsl rol add adc andi add brcc inc m10_1:
copyL,mp10L copyH,mp10H mp10L mp10H copyL copyH copyL copyH copyL copyH mp10L,copyL mp10H,copyH adder,0x0f mp10L,adder m10_1 mp10H ret
nibble
nibble ;make copy ;multiply original by 2 ;multiply copy by 2 ;multiply copy by 2 (4) ;multiply copy by 2 (8) ;add copy to original ;mask away upper nibble of adder ;add lower nibble of adder ;if carry not cleared ; inc high byte
;***** Main Routine Register Variables .def
tbinL
=r14
;Low byte of binary result (same as
.def
tbinH
=r15
;High byte of binary result (same as
.def .def .def
fBCD0 fBCD1 fBCD2
=r16 =r17 =r18
;BCD value digits 1 and 0 ;BCD value digits 2 and 3 ;BCD value digit 5
mp10L) mp10H)
;***** Code BCD2bin16: andi clr mov mov rcall mov rcall mov rcall mov rcall ret
fBCD2,0x0f mp10H mp10L,fBCD2 adder,fBCD1 mul10a adder,fBCD1 mul10b adder,fBCD0 mul10a adder,fBCD0 mul10b
;mask away upper nibble of fBCD2 ;mp10H:mp10L = a ;mp10H:mp10L = 10a+b ;mp10H:mp10L = 10(10a+b)+c ;mp10H:mp10L = 10(10(10a+b)+c)+d ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
;*************************************************************************** ;* ;* "BCD2bin8" - BCD to 8-bit binary conversion ;* ;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an ;* 8-bit number (tbin). ;* ;* Number of words :4 + return ;* Number of cycles :3/48 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (tbin/fBCDL,fBCDH) ;* ;* Modifications to make the routine accept a packed BCD number is indicated ;* as comments in the code. If the modifications are used, fBCDH shall be ;* loaded with the BCD number to convert prior to calling the routine. ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
tbin fBCDL fBCDH
=r16 =r16 =r17
;binary result ;lower digit of BCD input ;higher digit of BCD input
;***** Code BCD2bin8: ;-------------------------------------------------------------------------;| ;For packed BCD input, add these two lines ;| mov tbin,fBCDH ;copy input to result ;| andi tbin,$0f ;clear higher nibble of result ;-------------------------------------------------------------------------BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1 brcs BCDb8_1 ;if carry not set ;-------------------------------------------------------------------------;| ;For packed BCD input, replace the above ;| ;two lines with these. ;| subi fBCDH,$10 ;MSD = MSD - 1 ;| brmi BCDb8_1 ;if Zero flag not set ;-------------------------------------------------------------------------subi tbin,-10 ; result = result + 10 rjmp BCDb8_0 ; loop again BCDb8_1:ret ;else return
;*************************************************************************** ;* ;* "BCDadd" - 2-digit packed BCD addition ;* ;* This subroutine adds the two unsigned 2-digit BCD numbers ;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow ;* carry in "BCD2". ;* ;* Number of words :19 ;* Number of cycles :17/20 (Min/Max) ;* Low registers used :None ;* High registers used :3 (BCD1,BCD2,tmpadd) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
BCD1 BCD2 tmpadd
=r16 =r17 =r18
;BCD input value #1 ;BCD input value #2 ;temporary register
;***** Code BCDadd: ldi add clr brcc ldi add_0: add brhs subi rjmp add_1: add_2: add brcs sbrs subi add_3: add_4: ret
tmpadd,6 ;value to be added later BCD1,BCD2 ;add the numbers binary BCD2 ;clear BCD carry add_0 ;if carry not clear BCD2,1 ; set BCD carry brhs add_1 ;if half carry not set BCD1,tmpadd ; add 6 to LSD add_2 ; if half carry not set (LSD <= 9) BCD1,6 ; restore value add_2 ;else add BCD1,tmpadd ; add 6 to LSD swap tmpadd BCD1,tmpadd ;add 6 to MSD add_4 ;if carry not set (MSD <= 9) BCD2,0 ; if previous carry not set BCD1,$60 ; restore value ret ;else ldi BCD2,1 ; set BCD carry
;*************************************************************************** ;* ;* "BCDsub" - 2-digit packed BCD subtraction ;* ;* This subroutine subtracts the two unsigned 2-digit BCD numbers ;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and ;* the underflow carry in "BCDb". ;* ;* Number of words :13 ;* Number of cycles :12/17 (Min/Max) ;* Low registers used :None ;* High registers used :2 (BCDa,BCDb) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def
BCDa BCDb
=r16 =r17
;BCD input value #1 ;BCD input value #2
;***** Code BCDsub: sub clr brcc ldi sub_0: subi sub_1: ret subi ldi brcc ldi sub_2:
BCDa,BCDb BCDb sub_0 BCDb,1 brhc sub_1 BCDa,$06 sbrs BCDb,0 BCDa,$60 BCDb,1 sub_2 BCDb,1 ret
;subtract the numbers binary ;if carry not clear ; store carry in BCDB1, bit 0 ;if half carry not clear ; LSD = LSD - 6 ;if previous carry not set ; return ;subtract 6 from MSD ;set underflow carry ;if carry not clear ; clear underflow carry
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct operation. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ldi out ldi out
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)
;***** Convert 54,321 to 2.5-byte packed BCD format ldi ldi rcall
fbinL,low(54321) fbinH,high(54321) bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321
;***** Convert 55 to 2-byte BCD ldi rcall
fbin,55 bin2BCD8
;result: tBCDH:tBCDL = 0505
;***** Convert $065535 to a 16-bit binary number ldi fBCD2,$06 ldi fBCD1,$55 ldi fBCD0,$35 rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535) ;***** Convert $0403 (43) to an 8-bit binary number ldi fBCDL,3 ldi fBCDH,4 rcall BCD2bin8 ;result: tbin = $2b (43) ;***** Add BCD numbers 51 and 79 ldi BCD1,$51 ldi BCD2,$79 rcall BCDadd ;result: BCD2:BCD1=$0130 ;***** Subtract BCD numbers 72 - 28 ldi BCDa,$72 ldi BCDb,$28 rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44 ;***** Subtract BCD numbers 0 - 90 ldi BCDa,$00 ldi BCDb,$90 rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that http://avr-asm.tripod.com/id77.html (1 of 2)1/20/2009 8:43:13 PM
16 BIT MATH (AVR 202)
share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/id77.html (2 of 2)1/20/2009 8:43:13 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DECIMAL TO ASCII ROUTINE HOME RETRO_DAN ASM FORUM
; universal signed, unsigned decimal number to ASCII convert
ASM MATH TUTORIAL #1
; MSB -> LSB = r23:r22 ZH:ZL _print24bit: ; Print unsigned 24 bit values
TUTORIAL #2 TUTORIAL #3
clr rjmp
MATH 200
_printsdecw:
MATH 200b
r23 _prnum ; Print signed decimal (16
bit) sbrs rjmp ser ser rjmp
MATH 201 MATH 202 MATH 32X
zh,7 _printdecw r22 r23 _printsdecdw
; Is the number < 0 ? ; No, print 0 to 32767
MATH YX DIV16 XX
_printdecb: clr zh
; Print (8 bit) value
_printdecw:
; Print unsigned decimal
DIV 24 24 DIV 3216
(16 bit)
FLOAT 128
clr clr
SQRT16 MATH 202 MATH 202
r22 r23
_printsdecdw:
; Print signed decimal (32
bit) sbrs rjmp com com com com subi sbci sbci sbci ldi rcall
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
r23,7 _printdecdw zl zh r22 r23 zl,-1 zh,-1 r22,-1 r23,-1 r24,'-' _putchar
SER EPROM DFLASH AT45
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; convert to ASCII and
yl yh r1 r2 r3 r4 r5 r20,32 yl,1 yh r21,5 r25,51 r24,y r24,r25 r24,7 r25,15 r24,3 r25,240 r24,r25 y+,r24 r21 _prnum2 zl zh r22 r23 r1 r2 r3 r4 r5 r20 _prnum1 zl,6 zh r24,-z _prnum5 zl,2 _prnum3 _prnum4 r24,r1 _prnum6 yh yl
r24 r24 _prnum6 r24 r24,0x0f
subi r24,-'0' brts _putchar cpi r24,'0' brne _prnum7 ; if you want leading spaces for nice format, add
DELAYS CALL ID here "ldi r24, ' '
rjmp _putchar ret _prnum7: set _putchar: rjmp
PWM 6CH PWM 10K ENCODE STH-11
_prnum: push push clr clr clr clr clr ldi _prnum1: ldi clr ldi _prnum2: ldi ld add sbrc andi sbrc andi sub st dec brne lsl rol rol rol rol rol rol rol rol dec brne clt ldi clr _prnum3: ld rcall cpi brsh brts set mov rcall _prnum4: pop pop ret _prnum5: push swap rcall pop _prnum6: andi eliminate leading zeros
90 DAYS
DTMF 314
; Print unsigned decimal
(32 bit)
FLASH CARD
CLOCK 8564
_printdecdw:
_my_output_char_routine ; RS232, LCD, I2C
etc, etc...
ATMEL CORP AVR BUTTERFLY AVR BOOK
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/decascii.html (1 of 2)1/20/2009 8:44:04 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/decascii.html (2 of 2)1/20/2009 8:44:04 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
INTEGER TO ASCII ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7
; ****************************************************************************** ; Author : Nay Oo ; DESCRIPTION : ; - This program convert an integer number to ASCII ; AVR Newbie Learning program ; - The integer Range (0..127) ; - You can use AVRStudio 4 simulator to see the register ; contents (recommended) ; ; uController : AT90S8515 ; Development Board : STK500 ; ; ; ; AUTHOR NOTE: ; This file was written by me to educate myself in AVR ; Initial ideas was gathered from the http://www. avrbeginners.net/ ; Please do refer to them for more indept theroritical aspects. ; ; After the convertion is done, you can send these ASCII coded ; numbers to UART,USB, LCD interface, etc. ; ; If you have any thing to discuss about this file, you can contact ; me via my personal email : [email protected] ; ; ******************************************************************************
COPY 102 ;* Include Microcontroller Device specific file .include "8515def.inc"
LPM 108 EPROM 100 SER EPROM DFLASH AT45
.def
intval = r17
; the variable which
.def .def .def
HundredCounter = r18 TenthCounter = r19 OneCounter = r20
stores the integer value
VFX MEM SORT 220 CRC 236
; eg. 127 = '1' ; eg. 127 = '2' ; eg. 127 = '7'
;* Integer Value .equ Number=127
XMODEM REC UART 304
; temporary storage
register
FLASH CARD VFX SMIL
;* Register Variable Declaration Here .def temp = r16
; You can change
any number from 0 to 127
UART 305 .org 0x0000 rjmp RESET
UART 128
; program reset vector
UART BUFF USB 232
;* Integer to ASCII converter subrountine here IntToASCII: cpi intVal,100 brge DivideBy100
AVR ISP ISP 2313 ISP 1200
(intVal>=100) cpi brge
AVR SPI I2C 300
; jump if
mov add
OneCounter,IntVal HundredCounter,temp
; here, we got
add
TenthCounter,temp
; from that, we
add ret
OneCounter,temp
; ASCII values !!!
there single digits
I2C/TWI 128 I2C/TWI AT8
intVal,10 DivideBy10
(intVal>=10)
I2C 302 I2C TWI26
; ; jump if
convert them to
DALLAS-1W DALLAS CRC
DivideBy100: subi intVal,100 inc HundredCounter rjmp IntToASCII
ETHNET 8019 TEA ADC 128 ADC 10B
DivideBy10: subi intVal,10 inc TenthCounter rjmp IntToASCII
ADC 400 ADC 401 THERM 232 IRD 410
;* Main Program Starts here RESET: ldi temp,low(RAMEND)
LCD HD44 LCD 2313 LCD44 2313 KBD 240
BOOT DR8
CLOCK 8564 90 DAYS
; started
ldi out
temp,high(RAMEND) SPH,temp
; end of SRAM ; RAMEND
ldi
HundredCounter,0
; set counters
ldi ldi ldi
TenthCounter,0 OneCounter,0 temp,48
; ;
values to zero
BOOT MG8
ALM CLK
SPL,temp
is declared in 8515def.inc file
KBD PC/128 PS2 EMU
out from the
MUX 242 KBD PS2
; STACK pointer
location
; ASCII =
Number + 48 ; In ASCII table, we can see that '0' is 48 (0x30) ; therefore, need to add 48 to the single digits
DELAYS ldi rcall
CALL ID
intVal,Number IntToASCII
; subroutine call ;
DTMF 314 PWM 6CH
which convert integer value to
PWM 10K
ASCII value
;
ENCODE forever: rjmp
STH-11
forever
; infinite loop
ATMEL CORP AVR BUTTERFLY AVR BOOK
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/intascii.html (1 of 2)1/20/2009 8:44:37 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/intascii.html (2 of 2)1/20/2009 8:44:37 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
TWO HEX TO ASCII ROUTINES HOME RETRO_DAN ASM FORUM
;----------------------------------------------; HEX TO ASCII ;----------------------------------------------;I think, this was the smallest (only 10 words).
ASM MATH TUTORIAL #1 TUTORIAL #2
;input: R16 = 8 bit value 0 ... 255 ;output: R18, R17, R16 = digits ;bytes: 20 ; bcd: ldi r18, -1 + '0' _bcd1: inc r18 subi r16, 100 brcc _bcd1 ldi r17, 10 + '0' _bcd2: dec r17 subi r16, -10 brcs _bcd2 sbci r16, -'0' ret
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45
; ********************************************************************************************** ;E. Seah ;03/24/01 ;HEX-TO-ASCII conversion subroutine ;"high" registers : 4 (3 if "value" can be "low" register) ;"low" registers : 0 (1 if "value" can be "low" register) ;program words : 22+1 (including return) ; ;description : convert 0x00<="value"<=0xff to 3 digits of ASCII in "hundreds","tens" and "ones" ; _h2a: ldi hundreds,200 ;init hundreds for hundreds cp loop ldi ones,2 ;init ones for hundreds cp loop
FLASH CARD a100: cp value,hundreds brlo sub100 ;if value=hundreds sub value,hundreds ;remove 100s from value subi ones,-0x30 ;?00<=x<=?99, 1st digit is '?' mov hundreds,ones ldi tens,90 ;init tens for tens cp loop ldi ones,9 ;init ones for tens cp loop a10: cp value,tens brlo sub10 ;if value=tens sub value,tens ;remove 10s from value subi ones,-0x30 ;?0<=x<=?9, 2nd digit is '?' mov tens,ones
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF
mov ones,value ;3rd digit is the remainder subi ones,-0x30 ;'ones' in ASCII
USB 232 AVR ISP ISP 2313
ret
ISP 1200
sub100: subi hundreds,100 ;for compare with value subi ones,1 ;use ones as temp storage for 1st digit rjmp a100
AVR SPI I2C 300 I2C 302
sub10: subi tens,10 ;for compare with value subi ones,1 ;use ones as temp storage for 2nd digit rjmp a10
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
Programming the AVR Microcontrollers in Machine Language
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MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/hx2asc.html (1 of 2)1/20/2009 8:45:10 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/hx2asc.html (2 of 2)1/20/2009 8:45:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
8 POINT MOVING AVERAGE (AVR 222) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
[email protected]
DESCRIPTION This Application note shows an implementation of an
;* elements starting at T_START. The App. note contains
DIV 24 24
program memory to
MATH 202
Support E-mail:
array containing SIZE a test
SQRT16
8-Point Moving Average Filter 1.0 97.07.04 AT90Sxx1x (Devices with SRAM)
;* Average (MAV) filter. The program filters a data
DIV16 XX
FLOAT 128
Title: Version: Last updated: Target:
8-point Moving
MATH YX
DIV 3216
A V R 2 2 2
************************
ASM MATH
MATH 202
N O T E
;* program which copies a 60-byte block of data from ;* SRAM and filters the data. Note that the ends of the data array are not ;* filtered. ;* ; ***************************************************************************
MATH 202 .include "8515def.inc"
DEC ASCII INT ASCII HX2ASC
SIZE =60 TABLE_L =$60
;data array size ;Low SRAM address
.equ
TABLE_H =$00
;High SRAM address
of first data element
AVG8 222 FFT7
.equ .equ
of first data element
COPY 102
rjmp
RESET
;Reset Handle
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; *************************************************************************** ;* ;* "mav8" ;* ;* This subroutine filters SIZE bytes with the first element in SRAM ;* location T_START. The filter routine uses an 8-byte ring buffer which ;* occupies working registers r0-r7. As filtering progresses, this ring ;* buffer always contains the 8-byte window to be averaged. ;* ;* Number of words :31 + return ;* Number of cycles :59 + (SIZE-7)*75 + return ;* Low registers used :11 (r0-r7,mav_tmp,AL,AH) ;* High registers used :1 (t_size) ;* Pointers used :X,Y,Z ;* ; ***************************************************************************
ISP 2313
;***** Subroutine Register Variables
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
mav_tmp =r8
;temprary
.def
AL
=r9
;ring
.def
AH
=r10
;ring
.def
t_size
=r16
;size of
buffer sum, low byte buffer sum, high byte
I2C/TWI 128 I2C/TWI AT8
.def storage register
table
DALLAS-1W
;***** Code
DALLAS CRC mav8: clr clr clr clr
ETHNET 8019 TEA ADC 128
YH YL XH XL
;init pointers
ADC 10B ;***** Fill ring buffer with first-8 byte data segment
ADC 400 ADC 401 THERM 232
mav8_1:
mav_tmp,Z+
;get SRAM
data st cpi brne sbiw
Y+,mav_tmp YL,8 mav8_1 ZL,5
;store in register ;got all? ;if not, loop more ;Z points to first
average AH AL YL ld mav_tmp,Y+ AL,mav_tmp AH,XH
;Clear avg High byte ;Clear avg Low byte ;init Y-pointer ; ;add value to AL ;add carry to AH
cpi brne
YL,8 mav8_3
;added all ? ;if not, loop
lsr ror lsr ror lsr ror ldd
AH AL AH AL AH AL mav_tmp,Z+5
;divide by 8 ; ; ; ; ; ;get next value to
st andi
X+,mav_tmp XL,$07
;store to buffer ;mask away pointer
st dec cpi brne
Z+,AL t_size t_size,4 mav8_2
;store average
IRD 410 LCD HD44 LCD 2313
ld
value to filter
LCD44 2313 mav8_2: ;***** Find clr clr clr mav8_3: add adc
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
(XH is zero)
BOOT DR8 ALM CLK
again
CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
buffer
PWM 10K ENCODE
upper bits
STH-11 ATMEL CORP AVR BUTTERFLY
;end of array? ;if not, loop
more ret
AVR BOOK ; *************************************************************************** ;* ;* Test Program ;* ;* This program copies 60 bytes of data from Program memory to SRAM. It ;* then calls "mav8" to get the data filtered. ;* ; *************************************************************************** RESET: ;***** Main program Register variables .def
temp
=r16
;***** Code ldi out ldi out
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer
;***** Memory fill clr ldi
ZH ZL,tableend*2+1 ;Z-pointer <- ROM table end
ldi ldi
YL,low(256*TABLE_H+TABLE_L+SIZE) YH,high(256*TABLE_H+TABLE_L+SIZE) ;Y pointer <- SRAM table
+ 1
end + 1 loop: st
lpm -Y,r0
;get ROM constant ;store in SRAM and
ZL,1 YL,TABLE_L loop YH,TABLE_H loop
;decrement Z-pointer ;if not done ; loop more
decrement Y-pointer sbiw cpi brne cpi brne
;***** Filter data ldi ldi ldi rcall
ZL,TABLE_L ZH,TABLE_H T_size,SIZE mav8
forever:rjmp
forever
;***** 60 ROM Constants table: .db 120,196 .db 78,216 .db 78,100 .db 43,39 .db 241,43 .db 62,172 .db 109,69 .db 48,184 .db 215,231 .db 63,133 .db 216,8 .db 121,126 .db 188,98 .db 168,205 .db 157,172 .db 108,233 .db 80,255 .db 252,102 .db 198,0 .db 171,239 .db 107,114 .db 172,170 .db 17,45 .db 42,55 .db 34,174 .db 229,250 .db 12,179 .db 187,243 .db 44,231 tableend: .db 76,48
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr222.html (1 of 2)1/20/2009 8:45:45 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr222.html (2 of 2)1/20/2009 8:45:45 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
7 BIT FAST FOURIER TRANSFORMATION HOME RETRO_DAN ASM FORUM ASM MATH
This is an attempt to provide some FFT-math to the AVR community. Code has been tested with AVR-Studio4. Works fine! FFT-Output is about 7 bits accurate.
TUTORIAL #1
****************** Known limitations and problems: The code assumes input Data to be in the range -127
TUTORIAL #2 TUTORIAL #3
($81)...+127($FF).
MATH 200
MATH 202
Input-data is organized in SRAM as Data1LowByte,Data1HighByte, Data2LowByte,Data2HighByte, Data3LowByte,Data3HighByte,....
MATH 32X
The FFT uses "in-place" operations and produces the
MATH 200b MATH 201
MATH YX
following output:
DIV16 XX
Re(f0)LowByte,Re(f0HighByte), Im(f0)LowByte,Im(f0HighByte), Re(f1)LowByte,Re(f1HighByte), Im(f1)LowByte,Im(f1HighByte),....
DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII
Thus for n=128 data points (at the moment this is the maximum), we get 64 frequency Data points. CPU time for different FFT-lengths: n=32 T=4,05ms n=64 T=9,3ms n=128 T=20,95ms
INT ASCII ************************** Things to do: 1) I hope to find some inspiration on the scaling issue
HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM
(to allow greater input range). 2) The loop-counters are still 8bit only, so these would need to be 16bit to get longer FFTs working. At the moment 64 frequency bins represent maximum resolution. 3) Include amplitude calculation, because most people just want to know amplitude vs. frequency and nothing more.
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
; ************************************************************* ;* FFT-Programm für bis zu 128 Datenpunkte * ;* reelle Eingangsdaten werden "in place" transformiert * ;* 128 Datenpunkte ergeben 64 Real/ImaginärDatenpaare * ;* Programmiert von niels laugwitz für avrMikrocontroller * ; ************************************************************* ; ;.device ATmega8 .include "m8def.inc" ;Lade die Registerdefinitionen für AT-Mega8 .DEF temprL = r2 .def temprH = r3 .DEF tempiL = r4 .def tempiH = r5 .DEF i1 = r2 ;Benutzt in for_Schleife_i .def i2 = r3 ;Benutzt in for_Schleife_i .DEF i3 = r4 ;Benutzt in for_Schleife_i .def i4 = r5 ;Benutzt in for_Schleife_i .def sortierzeiger=r0; .def nullwert=r6 .def jjende=r7 .def data1 = R8 .def data2 =R9 .def data3 =R10 .def data4 =R11 .def wrL=r12 .def wrH=r13 .def wiL=r14 .def wiH=r15 .DEF temp =r16 .DEF ii =r17 .DEF jj =r18 .DEF mmax =r19 .DEF j =r20 .DEF istep=r21 .def i =r22 .DEF m =r23 .def zaehler=r24 .DEF tmp_lo =r18 ;Benutzt in for_Schleife_i .DEF tmp_hi =r19 ;Benutzt in for_Schleife_i
LCD44 2313 KBD 240
.set
nn2 =128
;Anzahl der Datenpunkte (FFT-
Länge)
MUX 242
;8 =< nn2 =< 128 .equ h1r_lo =$60 .equ h1r_hi =$61 .equ h1i_lo =$62 .equ h1i_hi =$63 .equ h2r_lo =$64 .equ h2r_hi =$65 .equ h2i_lo =$66 .equ h2i_hi =$67 .equ sramstart = $0080
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
.org $0000 rjmp main ;reset .include "avr201.asm"
90 DAYS DELAYS CALL ID
schleife_jj_body: ;Berechnung der Indexe i und j: mov i,m mul jj,istep ;r0 := jj*istep mov i,r0 add i,m ;i:=m+jj*istep mov temp,i add temp,mmax mov j,temp ;j:=i+mmax ;Hole data[j] und data[j+1] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,j adc XH,nullwert ;da das Array Data als 16bit-Werte
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK abgespeichert ist,
add XL,j ;muss der Index verdoppelt werden. adc XH,nullwert ld data1,X+ ;hole Data[j]low-byte ld data2,X+ ;hole Data[j]High-byte ld data3,X+ ;Hole Data[j+1]low-Byte ld data4,X ;hole Data[j+1]High-Byte ;Berechne tempr und tempi mehrere Multiplikationen erfordern ;etwas platz in den oberen registern. Im Moment brauchen wir die ; nicht: Also ab auf den Stack! push r23 push r22 push r21 push r20 push r19 push r18 push r17 push r16 ;Berechne tempr movw r21:r20,wrh:wrl movw r23:r22,data2:data1 rcall muls16x16_32 ;tempr:=wr*data[j] (16bit signed) MOV temprH,r18 ;we take just the middle-resultbytes MOV temprL,r17 movw r21:r20,wih:wil movw r23:r22,data4:data3 rcall muls16x16_32 ;tempi:=wi*data[j+1] (16bit signed) MOV tempiH,r18 ;we take just the middle-resultbytes MOV tempiL,r17 sub temprL,tempiL sbc temprH,tempiH
;tempr := wr*data[j]-wi*data[j
+1] ;Berechne tempi push temprL push temprH movw r21:r20,wrh:wrl movw r23:r22,data4:data3 rcall muls16x16_32 ;tempr:=wr*data[j+1] (16bit signed) MOV temprH,r18
;we take just the middle-result-
bytes MOV temprL,r17 movw r21:r20,wih:wil movw r23:r22,data2:data1 rcall muls16x16_32 ;tempi:=wi*data[j] (16bit signed) MOV tempiH,r18 ;we take just the middle-resultbytes MOV tempiL,r17 add tempiL,temprL adc tempiH,temprH
;tempi := wr*data[j+1]+wi*data
[j] pop temprH pop temprL pop r16 pop r17 pop r18 pop r19 pop r20 pop r21 pop r22 pop r23 ;multiplikationen beendet, Stack und Register wieder in Ordnung ;Hole data[i] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert ld data3,X+ ;hole Data[i]Low-Byte ld data4,X ;Hole Data[i]high-Byte ;data[j]:=data[i]-tempr movw data2:data1, data4:data3 sub data1,temprL sbc data2,temprH ldi XH,0 ldi XL,sramstart add XL,j adc XH,nullwert add XL,j adc XH,nullwert st X+,data1 st X,data2 ;Hole data[i+1] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert adiw XH:XL,2 ld data3,X+ ;hole Data[i+1]low-Byte ld data4,X ;Hole Data[i+1]high-Byte ;data[j+1]:=data[i+1]-tempi movw data2:data1, data4:data3 sub data1,tempiL sbc data2,tempiH ldi XH,0 ldi XL,sramstart add XL,j adc XH,nullwert add XL,j adc XH,nullwert adiw XH:XL,2 st X+,data1 st X,data2 ;data[i+1]:=data[i+1]+tempi add data3,tempiL adc data4,tempiH ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert adiw XH:XL,2 st X+,data3 st X,data4 ;Hole data[i] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert ld data3,X+ ;hole Data[i]low-Byte ld data4,X ;Hole Data[i]high-Byte ;data[i]:=data[i]+tempr add data3,temprL adc data4,temprH ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert st X+,data3 st X,data4 ret ;Rücksprung zur Schleife_jj ;**************************** ;****** HAUPTPROGRAMM ******* ;**************************** main: ;initialisieren des Stacks ldi r16,high(RAMEND) out spH,r16 ldi r16,low(RAMEND) out spl,r16 sei ;Kopieren der Test-Daten ins SRAM ;Testdaten werden als 16-bit-signed abgespeichert. ;Die FFT ergibt ebenfalls 16-bit Daten, ;davon sind aber nur ca. 7 bit relevant. ldi ZH,high(2*testdata) ldi ZL, low(2*testdata) clr i blockkopieren: ;Das Kopieren der Werte erspart mir eine ;butterfly-sort zu programmieren, simple stupid! LPM temp,Z+
;Lade Werte aus der Ursprungstabelle
testdata push ZH push ZL ldi ZH,high(2*speicherorte_128_werte) ldi ZL, low(2*speicherorte_128_werte) add ZL,i adc ZH,nullwert lpm sortierzeiger,Z pop ZL pop ZH ldi XH,0 ldi XL,sramstart add XL,sortierzeiger adc XH,nullwert add XL,sortierzeiger adc XH,nullwert sbrc temp,7 ;wenn temp negativ, dann dec nullwert ;setze register nullwert ausnahmsweise auf $FF st X+,temp st X,nullwert
;speichere lower-Byte zuerst ;Highbyte (enthält zunächst nur das
Vorzeichen) ;speichere alle Daten umsortiert im SRAM clr nullwert ;setze Nullwert wieder auf Null! inc i cpi i,nn2 brne blockkopieren ;nun sind die daten für die FFT umsortiert und stehen im SRAM ab ;Adresse (sramstart+2)=$0082. Für Eigene Anwendungen sollten die Daten ;von Anfang an nach der Sortiertabelle "speicherorte_XX_werte" geordnet ;werden. Die Werte sind im SRAM abgelegt als 16 bit signed integer! ;dw = LOW:HIGH = value:sign ;**************************************** ;hier beginnt die eigentliche FFT ldi mmax,2 while_schleife_start: cpi mmax,nn2 ;nn2=64 brlo while_schleife_body
;while nn2>mmax do
rjmp while_schleife_ende
;ende der while-Schleife
while_schleife_body erreicht while_schleife_body: mov istep,mmax lsl istep ;istep:=2*mmax clr ii ;ii:=0 for_schleife_ii_start: ;for ii=1 to (mmax div 2) inc ii mov m,ii lsl m ;m:=2*ii dec m ;m:=2*ii-1 ldi temp,nn2 ;nn2=64 sub temp,m ;nn2-m mov dd8u,temp mov dv8u,istep rcall div8u ;Divisionsroutine ;.def drem8u =r15 ;remainder ;.def dres8u =r24 ;result ;.def dd8u =r24 ;dividend ;.def dv8u =r25 ;divisor mov jjende,dres8u ;jjende:=nn2-m div istep clr jj ;jj:=0 Initialisierung für Schleife ;Nun holen wir die Cosinuswerte ldi ZH,high(2*cosinetab) ldi ZL, low(2*cosinetab) ldi zaehler,nn2 mov temp,mmax lsr temp pp: lsr zaehler lsr temp brne pp mov temp,ii dec temp mul temp,zaehler add ZL,r0 adc ZH,r1 add ZL,r0 ;addition des pointers doppelt wegen adc ZH,r1 ;2Byte pro Tabelleneintrag lpm wrL,Z+ ;jetzt haben wir wrL(ow) lpm wrH,Z ;jetzt haben wir wrH(igh) ;Nun holen wir die Sinuswerte ldi ZH,high(2*sinetab) ldi ZL, low(2*sinetab) ldi zaehler,nn2 mov temp,mmax lsr temp pq: lsr zaehler lsr temp brne pq mov temp,ii dec temp mul temp,zaehler add ZL,r0 adc ZH,r1 add ZL,r0 ;Addition des Pointer-Werts doppelt wegen adc ZH,r1 ;2Byte pro Tabelleneintrag lpm wiL,Z+ ;jetzt haben wir wiL(ow) lpm wiH,Z ;jetzt haben wir wiH(igh) for_schleife_jj_start: rcall Schleife_jj_body ;damit die Schleife mit einer branch-instruktion ;abgeschlossen werden kann, wird die eigentliche ;Abarbeitungsroutine mit rcall aufgerufen. ;(Problem ist die Sprungreichweite von brsh) inc jj cp jjende,jj brsh for_schleife_jj_start ;ende der jj-Schleife mov temp,mmax lsr temp ;iiende:=mmax div 2 cp ii,temp brlo for_schleife_ii_start ;hier ist das ende der for_schleife_ii mov mmax,istep rjmp while_schleife_start While_schleife_ende: ; Die FFTransformation ist geschafft! Jetzt muß nur noch richtig ; sortiert werden, da Inputdaten reelle Werte waren. ldi i,1 ;Initialisierung von i for_schleife_i_anfang: inc i ;for i:=2 to ((nn2 div 4)+1) ;Berechnung der Indizes i1..i4 mov i1,i lsl i1 dec i1 ; i1:=i+i-1 mov i2,i1 inc i2 ; i2:= i1+1 ldi temp,nn2 sub temp,i2 subi temp,-3 mov i3,temp ; i3:=nn2-i2+3 mov i4,i3 inc i4 ; i4:=i3+1 ;Nun holen wir die wr ldi ZH,high(2*cosinetab) ldi ZL, low(2*cosinetab) mov temp,i dec temp lsl temp add ZL,temp adc ZH,nullwert lpm wrL,Z+ ;jetzt haben wir wrL(ow) lpm wrH,Z ;jetzt haben wir wrH(igh) ;Nun holen wir die wi ldi ZH,high(2*sinetab) ldi ZL, low(2*sinetab) mov temp,i dec temp lsl temp add ZL,temp adc ZH,nullwert lpm wiL,Z+ ;jetzt haben wir wiL(ow) lpm wiH,Z ;jetzt haben wir wiH(igh) rcall for_schleife_calculus ;auch hier Unterprogramm, damit die ;Schleife mit brlo enden kann. ;test ob FOR_Schleife schon fertig ldi temp,nn2 lsr temp lsr temp inc temp cp i,temp brlo for_schleife_i_anfang for_schleife_i_exit: ;Umsortieren ist geschafft. nop ;here comes compensation for DC-Value. ; if DC is not important, then just skip the following routine rcall DC_compensation ; *********************************************************** ;now the fft is done. ;data contains real-part and imaginary-part as 16bit values ;arranged in pairs first real, then imaginary ; *********************************************************** ende: ;Das Werk ist vollbracht! rjmp ende ;SCHLUSS! ENDE! AUS! for_schleife_calculus: ;***** Berechnung von h1r und h2i ;hole Data[i1] in reg. data2:data1 ldi XH,0 ldi XL,sramstart add XL,i1 adc XH,nullwert add XL,i1 adc XH,nullwert ld data1,X+ ;lower-Byte zuerst ld data2,X ;Highbyte ;hole Data[i3] in register-pair data4:data3 ldi XH,0 ldi XL,sramstart add XL,i3 adc XH,nullwert add XL,i3 adc XH,nullwert ld data3,X+ ;lower-Byte zuerst ld data4,X ;Highbyte asr data2 ror data1 ;data[i1]:=data[i1]/2 asr data4 ror data3 ;data[i3]:=data[i3]/2 movw tmp_hi:tmp_lo,data2:data1 add tmp_lo,data3 adc tmp_hi,data4 ;h1r:=data[i1]+data[i3] sts h1r_lo,tmp_lo sts h1r_hi,tmp_hi ;save h1r to sram-location movw tmp_hi:tmp_lo,data2:data1 sub tmp_lo,data3 sbc tmp_hi,data4 ;h1r:=-1*(data[i1]-data[i3]) com tmp_lo com tmp_hi ldi temp,1 add tmp_lo,temp adc tmp_hi,nullwert sts h2i_lo,tmp_lo sts h2i_hi,tmp_hi ;save h1r to sram-location ;***** Berechnung von h1i und h2r ;hole Data[i2] in reg. data2:data1 ldi XH,0 ldi XL,sramstart add XL,i2 adc XH,nullwert add XL,i2 adc XH,nullwert ld data1,X+ ;lower-Byte zuerst ld data2,X ;Highbyte ;hole Data[i4] in register-pair data4:data3 ldi XH,0 ldi XL,sramstart add XL,i4 adc XH,nullwert add XL,i4 adc XH,nullwert ld data3,X+ ;lower-Byte zuerst ld data4,X ;Highbyte asr data2 ror data1 ;data[i2]:=data[i2]/2 asr data4 ror data3 ;data[i4]:=data[i4]/2 movw tmp_hi:tmp_lo,data2:data1 sub tmp_lo,data3 sbc tmp_hi,data4 sts h1i_lo,tmp_lo sts h1i_hi,tmp_hi ;save h1i to sram-location add data1,data3 adc data2,data4 sts h2r_lo,data1 sts h2r_hi,data2 ;save h2r to sram-location push r23 push r22 push r21 push r20 push r19 push r18 push r17 push r16 ; **** Data[i1]:=h1r+wr*h2r-wi*h2i movw R21:R20,wrh:wrl lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wih:wil lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 sub data1,r17 sbc data2,r18 lds r18,h1r_hi lds r17,h1r_lo add data1,r17 adc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i1 adc XH,nullwert add XL,i1 adc XH,nullwert st X+,data1 st X ,data2 ; **** Data[i2]:=h1i+wr*h2i+wi*h2r movw R21:R20,wrh:wrl lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wih:wil lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 add data1,r17 adc data2,r18 lds r18,h1i_hi lds r17,h1i_lo add data1,r17 adc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i2 adc XH,nullwert add XL,i2 adc XH,nullwert st X+,data1 st X ,data2 ; **** Data[i3]:=h1r-wr*h2r+wi*h2i movw R21:R20,wih:wil lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wrh:wrl lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 sub data1,r17 sbc data2,r18 lds r18,h1r_hi lds r17,h1r_lo add data1,r17 adc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i3 adc XH,nullwert add XL,i3 adc XH,nullwert st X+,data1 st X ,data2 ; **** Data[i4]:=-h1i+wr*h2i+wi*h2r movw R21:R20,wrh:wrl lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wih:wil lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 add data1,r17 adc data2,r18 lds r18,h1i_hi lds r17,h1i_lo sub data1,r17 sbc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i4 adc XH,nullwert add XL,i4 adc XH,nullwert st X+,data1 st X ,data2 pop r16 pop r17 pop r18 pop r19 pop r20 pop r21 pop r22 pop r23 ret ;ende der umfangreichen Berechnungen in For_schleife_i DC_compensation: lds data1,sramstart+2 lds data2,sramstart+3 lds data3,sramstart+4 lds data4,sramstart+5 movw tmp_hi:tmp_lo,data2:data1 add data1,data3 adc data2,data4 sub tmp_lo,data3 sbc tmp_hi,data4 sts sramstart+2,data1 sts sramstart+3,data2 sts sramstart+4,tmp_lo sts sramstart+5,tmp_hi ret ;ende DC-kompensation sinetab:
;Jede Tabelle 128 Werte = Anzahl
Datenpunkte .dw
0,
13,
25,
38,
50,
62,
74,
86,
98, 109,
121, 132, 142, 152, 162, 172 .dw
181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256 cosinetab:
;überlappt mit Sinustabelle um
Speicherplatz sparen .dw
256, 256, 255, 253, 251, 248, 245, 241, 237, 231,
.dw
181, 172, 162, 152, 142, 132, 121, 109,
226, 220, 213, 206, 198, 190 74,
62,
50,
38,
25,
98,
86,
13 .dw
0, -13, -25, -38, -50, -62, -74, -86, -98,-109,-
121,-132,-142,-152,-162,-172 .dw -181,-190,-198,-206,-213,-220,-226,-231,-237,-241,245,-248,-251,-253,-255,-256 .dw -256,-256,-255,-253,-251,-248,-245,-241,-237,-231,226,-220,-213,-206,-198,-190 .dw -181,-172,-162,-152,-142,-132,-121,-109, -98, -86, 74, -62, -50, -38, -25, -13 .dw
0,
13,
25,
38,
50,
62,
74,
86,
98, 109,
121, 132, 142, 152, 162, 172 .dw
181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256
sinetab_64:
;Jede Tabelle 64 Werte = Anzahl
Datenpunkte .dw 0, 25, 50, 74, 98, 121, 142,162 .dw 181,198,213,226,237,245,251,255 cosinetab_64: ;überlappt mit Sinustabelle um Speicherplatz sparen .dw 256, 255, 251, 245, 237, 226, 213, 198 .dw 181, 162, 142, 121, 98, 74, 50, 25 .dw 0, -25, -50, -74, -98,-121,-142,-162 .dw -181,-198,-213,-226,-237,-245,-251,-255 .dw -256,-255,-251,-245,-237,-226,-213,-198 .dw -181,-162,-142,-121, -98, -74, -50, -25 .dw 0, 25, 50, 74, 98, 121, 142,162 .dw 181,198,213,226,237,245,251,255 sinetab_32:
;Jede Tabelle 32 Werte = Anzahl
Datenpunkte .dw 0, 50, 98, 142 .dw 181, 213, 237, 251 cosinetab_32: ;überlappt mit Sinustabelle um Speicherplatz sparen .dw 256, 251, 237, 213 .dw 181, 142, 98, 50 .dw 0, -50, -98,-142 .dw -181,-213,-237,-251 .dw -256,-251,-237,-213 .dw -181,-142, -98, -50 .dw 0, 50, 98, 142 .dw 181, 213, 237, 251 testdata: ;128 Datenpunkte mit 7bit + sign !! .db 1,2,3,4,5,6,7,8 .db 9,10,11,12,13,14,15,16 .db 17,18,19,20,21,22,23,24 .db 25,25,27,28,29,30,31,32 .db 33,34,35,36,37,38,39,40 .db 41,42,43,44,45,46,47,48 .db 49,50,51,52,53,54,55,56 .db 57,58,59,60,61,62,63,64 .db 65,66,67,68,69,70,71,72 .db 73,74,75,76,77,78,79,80 .db 81,82,83,84,85,86,87,88 .db 89,90,91,92,93,94,95,96 .db 97,98,99,100,101,102,103,104 .db 105,106,107,108,109,110,111,112 .db 113,114,115,116,117,118,119,120 .db 121,122,123,124,125,126,127,0 speicherorte_128_werte: .db 1,2 .db 65,66 .db 33,34 .db 97,98 .db 17,18 .db 81,82 .db 49,50 .db 113,114 .db 9,10 .db 73,74 .db 41,42 .db 105,106 .db 25,26 .db 89,90 .db 57,58 .db 121,122 .db 5,6 .db 69,70 .db 37,38 .db 101,102 .db 21,22 .db 85,86 .db 53,54 .db 117,118 .db 13,14 .db 77,78 .db 45,46 .db 109,110 .db 29,30 .db 93,94 .db 61,62 .db 125,126 .db 3,4 .db 67,68 .db 35,36 .db 99,100 .db 19,20 .db 83,84 .db 51,52 .db 115,116 .db 11,12 .db 75,76 .db 43,44 .db 107,108 .db 27,28 .db 91,92 .db 59,60 .db 123,124 .db 7,8 .db 71,72 .db 39,40 .db 103,104 .db 23,24 .db 87,88 .db 55,56 .db 119,120 .db 15,16 .db 79,80 .db 47,48 .db 111,112 .db 31,32 .db 95,96 .db 63,64 .db 127,128 speicherorte_64_werte:
;Sortiertabelle für 64
Werte .db 1, 2, .db 17, 18, .db 9, 10, .db 25, 26, .db 5, 6, .db 21, 22, .db 13, 14, .db 29, 30, .db 3, 4, .db 19, 20, .db 11, 12, .db 27, 28, .db 7, 8, .db 23, 24, .db 15, 16, .db 31, 32, ;*********************
33, 49, 41, 57, 37, 53, 45, 61, 35, 51, 43, 59, 39, 55, 47, 63,
speicherorte_32_werte:
34 50 42 58 38 54 46 62 36 52 44 60 40 56 48 64
;Sortiertabelle für 32
Werte .db .db .db .db .db .db .db .db
1, 9, 5, 13, 3, 11, 7, 15,
2, 10, 6, 14, 4, 12, 8, 16,
17, 25, 21, 29, 19, 27, 23, 31,
18 26 22 30 20 28 24 32
; ****************************************************************************** ;* ;* FUNCTION ;* muls16x16_32 ;* DECRIPTION ;* Signed multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 19 + ret ;* Words : 15 + ret ;* Register usage: r0:r1 and r6 and r16 to r23 (11 registers) ;* NOTE ;* The routine is non-destructive to the operands. ;* ; ****************************************************************************** muls16x16_32: ; clr r6 muls r23, r21 ; (signed)ah * (signed)bh movw r19:r18, r1:r0 mul r22, r20 ; al * bl movw r17:r16, r1:r0 mulsu r23, r20 ; (signed)ah * bl sbc r19, r6 add r17, r0 adc r18, r1 adc r19, r6 mulsu r21, r22 ; (signed)bh * al sbc r19, r6 add r17, r0 adc r18, r1 adc r19, r6 ret ; *************************************************************************** ;* ;* "div8u" - 8/8 Bit Unsigned Division ;* ;* This subroutine divides the two register variables "dd8u" (dividend) and ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in ;* "drem8u". ;* ;* Number of words :66 + return ;* Number of cycles :50/58/66 (Min/Avg/Max) + return ;* Low registers used :1 (drem8u) ;* High registers used :2 (dres8u/dd8u,dv8u) ;*
http://avr-asm.tripod.com/fft7.html (1 of 2)1/20/2009 8:46:26 PM
16 BIT MATH (AVR 202)
; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def
drem8u =r15 dres8u =r24 dd8u =r24 dv8u =r25
;remainder ;result ;dividend ;divisor
;***** Code div8u:
sub
drem8u,drem8u
;clear remainder and
carry rol rol sub brcc add clc
dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_1 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result rjmp d8u_1:
d8u_2 sec
;else ; set carry to be shifted into
d8u_2: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_3 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_3:
d8u_4 sec
d8u_4: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_5 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_5:
d8u_6 sec
d8u_6: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_7 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_7:
d8u_8 sec
d8u_8: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_9 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_9:
d8u_10 sec
d8u_10: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_11 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result rjmp d8u_11:
d8u_12 sec
;else ; set carry to be shifted into
result d8u_12: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_13 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result rjmp d8u_13:
d8u_14 sec
;else ; set carry to be shifted into
result d8u_14: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_15 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result rjmp d8u_15:
d8u_16 sec
d8u_16: ret
rol
;else ; set carry to be shifted into
result dd8u
;shift left dividend
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/fft7.html (2 of 2)1/20/2009 8:46:26 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BLOCK COPY (AVR 102) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X MATH YX DIV16 XX
A V R 1 0 2
************************
ASM MATH
MATH 202
N O T E
Title: Version: Last updated: Target:
Block Copy Routines 1.1 97.07.04 AT90Sxx1x (Devices with SRAM)
Support E-mail:
[email protected]
DESCRIPTION This Application Note shows how to copy a block of
data from Program ;* memory to SRAM and from one SRAM area to another ;* ; ***************************************************************************
DIV 24 24
.include "8515def.inc"
DIV 3216
rjmp
RESET
;reset handle
FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM
; *************************************************************************** ;* ;* "flash2ram" ;* ;* This subroutine copies a block of data from the Program memory (Flash) ;* to the internal SRAM. The following parameters must be set up prior to ;* calling the subroutine: ;* Z-pointer: Flash block start address x 2 (WORD oriented code segment) ;* Y-pointer: ram block start address ;* romsize: block size ;* ;* Number of words :5 + return ;* Number of cycles :10 x block size + return ;* Low Registers used :1 (r0) ;* High Registers used :1 (flashsize) ;* Pointers used :Y, Z ;* ; ***************************************************************************
SORT 220
;***** Subroutine Register variables
CRC 236 .def
XMODEM REC UART 304
;***** Code
UART 128
flash2ram: lpm st
UART BUFF
;get constant ;store in SRAM and
Y+,r0
increment Y-pointer
AVR ISP
adiw dec brne
ISP 2313 ISP 1200
;size of block to
be copied
UART 305
USB 232
flashsize=r16
ZL,1 flashsize flash2ram
;increment Z-pointer ;if not end of table, loop
more ret
AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
; *************************************************************************** ;* ;* "ram2ram" ;* ;* This subroutine copies one block of data from one SRAM area to another. ;* The following parameters must be set up prior to calling the subroutine: ;* ;* Z-pointer: start of RAM area to copy from ;* Y-pointer: start of RAM area to copy to ;* ramsize : size of block to copy ;* ;* Number of words :4 + return ;* Number of cycles :6 x block size + return ;* Low Registers used :1 (ramtemp) ;* High Registers used :1 (ramsize) ;* Pointers used :Y, Z ;* ; *************************************************************************** ;***** Subroutine Register variables
LCD44 2313 KBD 240 MUX 242 KBD PS2
.def
ramtemp =r1
;temporary storage
.def
ramsize =r16
;size of block to
register be copied
KBD PC/128 ;***** Code
PS2 EMU BOOT MG8
ram2ram: ld st dec brne ret
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
ramtemp,Z+ Y+,ramtemp ramsize ram2ram
;get data from BLOCK1 ;store data to BLOCK2 ; ;if not done, loop more
; **************************************************************************** ;* ;* Test Program ;* ;* This program copies 20 bytes of data from the Program memory to the SRAM ;* area beginning at location BLOCK1. It then makes a second copy to the ;* area beginning at location BLOCK2. ;* ; ****************************************************************************
AVR BOOK
.equ
BLOCK1
=$60
;start address of
.equ
BLOCK2
=$80
;start address of
SRAM array #1 SRAM array #2 ;***** Main Program Register variables .def
temp
=r16
;temporary storage
variable ;***** Code RESET: ldi out
temp,low(RAMEND) SPL,temp ;init Stack
Pointer ldi out
temp,high(RAMEND) SPH,temp
;***** Copy 20 bytes ROM -> RAM ldi ldi ldi ldi ldi rcall
ZH,high(F_TABLE*2) ZL,low(F_TABLE*2);init Z-pointer YH,high(BLOCK1) YL,low(BLOCK1) ;init Y-pointer flashsize,20 flash2ram ;copy 20 bytes
;***** Copy 20 bytes RAM -> RAM ldi ldi ldi
ZH,high(BLOCK1) ZL,low(BLOCK1) ;init Z-pointer YH,high(BLOCK2) ;(not necessary in this
ldi ldi rcall
YL,low(BLOCK2) ramsize,20 ram2ram
specific case)
forever:rjmp F_TABLE: .db .db .db .db .db .db .db .db .db .db
forever
0,1 2,3 4,5 6,7 8,9 10,11 12,13 14,15 16,17 18,19
;init Y-pointer ;copy 20 bytes ;eternal loop
;start of table (20 bytes)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr102.html (1 of 2)1/20/2009 8:47:00 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr102.html (2 of 2)1/20/2009 8:47:00 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LOAD PROGRAM MEMORY (AVR 108) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2
Title: Version: Last updated: Target:
Load Program Memory 1.0 98.02.27 AT90Sxx1x and higher (Devices with
SRAM)
MATH 200
;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application note shows how to use the Load
MATH 200b MATH 201 MATH 202 MATH 32X
A V R 1 0 8
************************
ASM MATH
TUTORIAL #3
N O T E
Program Memory (LPM) ;* instruction. The App. note loads the string "Hello
MATH YX
World" from
DIV16 XX
;* program memory byte by byte, and puts it onto port B. ;* ; ***************************************************************************
DIV 24 24 DIV 3216 FLOAT 128
.include "8515def.inc"
SQRT16 MATH 202
.device AT90S8515
; Specify device
MATH 202 DEC ASCII
.def
temp
=r16
; Define
start: out
ldi temp,low(RAMEND) SPL,temp ; Set stack pointer
temporary variable
INT ASCII HX2ASC AVG8 222 FFT7
to last internal RAM location
COPY 102
ldi out
temp,high(RAMEND) SPH,temp
ldi out
temp,$ff PORTB,temp
; Set all pins at
out
DDRB,temp
; Set port B as
LPM 108 EPROM 100 SER EPROM DFLASH AT45
port B high output
FLASH CARD VFX SMIL
; Load the address of 'message' into the Z register. Multiplies
VFX MEM SORT 220 CRC 236
; word address with 2 to achieve the byte address, and uses the ; functions high() and low() to calculate high and low address byte.
XMODEM REC UART 304
; Load high part of
ldi
ZL,low(2*message)
; Load low part of
byte address into ZL
UART BUFF USB 232
ZH,high(2*message)
byte address into ZH
UART 305 UART 128
ldi
loadbyte: lpm
; Load byte from
program memory into r0
AVR ISP ISP 2313
tst
r0
; Check if we've
breq
quit
; If so, quit
out
PORTB,r0
; Put the character
rcall
one_sec_delay
; A short delay
adiw
ZL,1
; Increase Z
rjmp
loadbyte
reached the end of the message
ISP 1200 AVR SPI I2C 300
onto Port B
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
registers
DALLAS-1W DALLAS CRC quit:
ETHNET 8019
rjmp quit
TEA one_sec_delay: ldi r20, 20 ldi r21, 255 ldi r22, 255 delay: dec r22 brne delay dec r21 brne delay dec r20 brne delay ret
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
message: .db "Hello World" .db 0
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314
Programming the AVR Microcontrollers in Machine Language
PWM 6CH PWM 10K
AVR << Prev | Ring Hub | Join | Rate| Next >>
ENCODE STH-11 ATMEL CORP
© WebRing Inc.
Search
AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr108.html (1 of 2)1/20/2009 8:47:33 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr108.html (2 of 2)1/20/2009 8:47:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
EPROM STORAGE (AVR 100) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
DEC ASCII INT ASCII
[email protected]
DESCRIPTION This Application note shows how to read data from
;* The code is written for 8515, to modify for 4414,2313,2323... apply the ;* following changes: ;* - Remove all entries to EEARH ;* - Rename EEARL to EEAR ;* ;* To modify for 1200, apply the changes above, and
FLOAT 128
MATH 202
Support E-mail:
routines are listed.
DIV 3216
MATH 202
Accessing the EEPROM 2.0 98.06.15 AT90Sxxxx (All AVR Devices)
;* EEPROM. Both random access and sequential access
DIV 24 24
SQRT16
Title: Version: Last updated: Target:
and write data to the
MATH YX DIV16 XX
A V R 1 0 0
************************
ASM MATH
MATH 202
N O T E
change the code ;* as commented inside the routines ;* ;* ; *************************************************************************** .include "8515def.inc"
HX2ASC
rjmp
RESET
;Reset Handle
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128
; *************************************************************************** ;* ;* EEWrite ;* ;* This subroutine waits until the EEPROM is ready to be programmed, then ;* programs the EEPROM with register variable "EEdwr" at address "EEawr:EEawr" ;* ;* Number of words :1200 ; 5 + return ;* :8515 ; 7 + return ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready) ;* :8515 ; 11 + return (if EEPROM is ready) ;* Low Registers used :None ;* High Registers used: ;3 (EEdwr,EEawr,EEawrh) ;* ; ***************************************************************************
UART BUFF
;***** Subroutine register variables
USB 232 AVR ISP ISP 2313
EEdwr
=r16
;data byte to write
.def
EEawr
=r17
;address low byte
.def
EEawrh
=r18
;address high byte
to EEPROM to write to
ISP 1200 AVR SPI
.def
to write to
I2C 300
;***** Code
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
EEWrite: sbic rjmp
EECR,EEWE EEWrite
;if EEWE not clear ; wait more
;
EEAR,EEawr
;output address for 1200,
out
commented out !
DALLAS CRC ETHNET 8019
; the two following lines must be replaced with the line above if 1200 is used out
EEARH,EEawrh
;output address high for
out
EEARL,EEawr
;output address low for 8515
out sbi
EEDR,EEdwr EECR,EEMWE
;output data ;set master write enable,
sbi
EECR,EEWE
;set EEPROM Write strobe ;This instruction takes 4
TEA ADC 128
8515
ADC 10B ADC 400 ADC 401 THERM 232
remove if 1200 is used
IRD 410 LCD HD44
clock cycles since
LCD 2313
clock cycles
;it halts the CPU for two ret
LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K
; *************************************************************************** ;* ;* EERead ;* ;* This subroutine waits until the EEPROM is ready to be programmed, then ;* reads the register variable "EEdrd" from address "EEardh:EEard" ;* ;* Number of words :1200 ; 5 + return ;* :8515 ; 6 + return ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready) ;* :8515 ; 9 + return (if EEPROM is ready) ;* Low Registers used :1 (EEdrd) ;* High Registers used: :2 (EEard,EEardh) ;* ; ***************************************************************************
ENCODE ;***** Subroutine register variables
STH-11 ATMEL CORP AVR BUTTERFLY
read from
AVR BOOK
read from
.def .def
EEdrd EEard
=r0 =r17
;result data byte ;address low to
.def
EEardh
=r18
;address high to
;***** Code EERead: sbic rjmp ; out
EECR,EEWE EERead EEAR,EEard
;if EEWE not clear ; wait more ;output address for 1200,
commented out ! ; the two following lines must be replaced with the line above if 1200 is used out
EEARH,EEardh
;output address high for
out
EEARL,EEard
;output address low for 8515
sbi
EECR,EERE
;set EEPROM Read strobe ;This instruction takes 4
8515
clock cycles since ;it halts the CPU for two clock cycles in ret
EEdrd,EEDR
;get data
; *************************************************************************** ;* ;* EEWrite_seq ;* ;* This subroutine increments the EEPROM address by one and waits until the ;* EEPROM is ready for programming. It then programs the EEPROM with ;* register variable "EEdwr_s". ;* Number of words :1200 ; 7 + return ;* :8515 ; 10 + return ;* Number of cycles :1200 ; 10 + return (if EEPROM is ready) ;*
:8515 ; 15 + return (if EEPROM is
ready) ;* Low Registers used :None ;* High Registers used: :3 (EEdwr_s,EEwtmp,EEwtmph) ;* ; *************************************************************************** ;***** Subroutine register variables .def
EEwtmp
=r24
;temporary storage
.def
EEwtmph =r25
;temporary storage
.def
EEdwr_s =r18
;data to write
of address low byte of address high byte
;***** Code EEWrite_seq: sbic EECR,EEWE rjmp EEWrite_seq
;if EEWE not clear ; wait more
; Write sequence for 1200 ; in EEwtmp,EEAR
;get address for 1200,
;
inc
EEwtmp
;increment address 1200,
;
out
EEAR,EEwtmp
;output address 1200
commented out ! commented out !
; Write sequence for 8515, must be replaced with the lines above if 1200 is used in in adiw out out
EEwtmp,EEARL EEwtmph,EEARH EEwtmp,0x01 EEARL,EEwtmp EEARH,EEwtmph
;get address low 8515 ;get address high 8515 ;increment address 8515 ;output address 8515 ;output address 8515
out sbi
EEDR,EEdwr_s EECR,EEMWE
;output data ;set master write enable,
sbi
EECR,EEWE
;set EEPROM Write strobe ;This instruction takes 4
remove if 1200 is used
clock cycles since ;it halts the CPU for two clock cycles ret ; *************************************************************************** ;* ;* EERead_seq ;* ;* This subroutine increments the address stored in EEAR and reads the ;* EEPROM into the register variable "EEdrd_s". ;* Number of words :1200 ; 5 + return ;* :8515 ; 7 + return ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready) ;*
:8515 ; 11 + return (if EEPROM is
ready) ;* Low Registers used :1 (EEdrd_s) ;* High Registers used: :2 (EErtmp,EErtmph) ;* ; *************************************************************************** ;***** Subroutine register variables .def
EErtmp
=r24
;temporary storage
.def
EErtmph =r25
;temporary storage
.def
EEdrd_s =r0
;result data byte
of low address of high address
;***** Code EERead_seq: sbic EECR,EEWE ;if EEWE not clear rjmp EERead_seq ; wait more ; The above sequence for EEWE = 0 can be skipped if no write is initiated. ; Read sequence for 1200 ; in EErtmp,EEAR
;get address for 1200,
;
inc
EErtmp
;increment address 1200,
;
out
EEAR,EErtmp
;output address 1200
commented out ! commented out !
; Read sequence for 8515, must be replaced with the lines above if 1200 is used in in adiw out out
EErtmp,EEARL EErtmph,EEARH EErtmp,0x01 EEARL,EErtmp EEARH,EErtmph
;get address low 8515 ;get address high 8515 ;increment address 8515 ;output address 8515 ;output address 8515
sbi
EECR,EERE
;set EEPROM Read strobe ;This instruction takes 4
clock cycles since ;it halts the CPU for two clock cycles in ret
EEdrd_s,EEDR
;get data
; **************************************************************************** ;* ;* Test/Example Program ;* ; **************************************************************************** ;***** Main Program Register variables .def .def
counter =r19 temp =r20
;***** Code RESET: ;***** Initialize stack pointer ;* Initialize stack pointer to highest address in internal SRAM ;* Comment out for devices without SRAM ldi
r16,high(RAMEND) ;High byte only required
out
SPH,r16
ldi out
r16,low(RAMEND) SPL,r16
if ;RAM is bigger than 256
Bytes
;***** Program a random location ldi ldi ldi rcall
EEdwr,$aa EEawrh,$00 EEawr,$10 EEWrite
;store $aa in EEPROM
location $0010 ;***** Read from a random locations ldi ldi rcall out
EEardh,$00 EEard,$10 EERead PORTB,EEdrd
;read address $10 ;output value to Port B
;***** Fill the EEPROM address 1..64 with bit pattern $55,$aa,$55,$aa,... ldi clr out clr out
counter,63 temp EEARH,temp temp EEARL,temp
;init loop counter ;EEARH <- $00 ;EEAR <- $00 (start address
- 1) loop1: rcall ldi rcall dec brne
ldi EEdwr_s,$55 EEWrite_seq ;program EEPROM with $55 EEdwr_s,$aa EEWrite_seq ;program EEPROM with $aa counter ;decrement counter loop1 ;and loop more if not done
;***** Copy 10 first bytes of EEPROM to r1-r11 clr out ldi out
temp EEARH,temp temp,$00 EEARL,temp
clr ldi
ZH ZL,1
;EEARH <- $00 ;EEAR <- $00 (start address
- 1)
loop2: st inc cpi brne
;Z-pointer points to r1
rcall EERead_seq ;get EEPROM data Z,EEdrd_s ;store to SRAM ZL ZL,12 ;reached the end? loop2 ;if not, loop more
forever:rjmp
forever
;eternal loop
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing http://avr-asm.tripod.com/avr100.html (1 of 2)1/20/2009 8:48:10 PM
16 BIT MATH (AVR 202)
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr100.html (2 of 2)1/20/2009 8:48:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SERIAL EPROM STORAGE HOME RETRO_DAN ;*****read/write spi( in/out temp ) ;caller is responsible for setting ss_inactive.. ;....after command completion
ASM FORUM ASM MATH TUTORIAL #1
rw_spi: cli cbi portd, nss ;ss-active, just in case ldi temp2, 8 ;load counter spi_loop: cbi portd, sck ;sck_lo lsl temp ;move 0 into D0, all other bits UP brcc
TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
lo_mosi ;msb into Carry sbi portd, mosi ;mosi_hi, Carry into output rjmp mosi_done lo_mosi: cbi portd, mosi ;mosi_lo, Carry into output mosi_done: sbic pinb, miso ;read in SPI bit & put into D0 inc temp;we FORCED D0=0, so use INC to set D0. sbi portd, sck ;sck_hi dec temp2 ;count bits brne spi_loop ret ;end of routine
MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
Programming the AVR Microcontrollers in Machine Language
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SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two singlebyte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirtytwo memory spaces (000016-001F16) followed by the 64 I/ O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/sereprom.html (1 of 2)1/20/2009 8:48:42 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/sereprom.html (2 of 2)1/20/2009 8:48:42 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SPI INTERFACE FOR AT45 SERIAL DATAFLASH HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; *************************************************************************** ; ; File Name :'DFlash.asm" ; Title :SPI interface to Serial DataFlash ; Date :2003.06.01. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega8 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; SPI interface to AT45DBxxx Serial DataFlash ; ; Functions to access the Atmel AT45Dxxx dataflash series ; Supports 1Mbit - 128Mbit ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.06.01 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ; CS - Chip Select ; SCK - Serial Clock ; SI - Serial Input ; SO - Serial Output ; WP - Hardware Page Write Protect Pin ; RESET - Chip Reset ; RDY/BUSY - Ready/Busy ; ; To provide optimal flexibility, the memory array of the AT45DB081B is ;divided into three levels of granularity comprising of sectors, blocks, ;and pages. All program operations to the DataFlash occur on a page-by-page ;basis; however, the optional erase operations can be performed at the block ;or page level. ; ; ;The device operation is controlled by instructions from the host processor. ;The list of instructions and their associated opcodes are contained in ;Tables 1 through 4. A valid instruction starts with the falling edge of CS ;followed by the appropriate 8-bit opcode and the desired buffer or main memory ;address location. While the CS pin is low, tog-gling the SCK pin controls the ;loading of the opcode and the desired buffer or main memory address location ;through the SI (serial input) pin. All instructions, addresses and data are ;transferred with the most significant bit (MSB) first. ;Buffer addressing is referenced in the datasheet using the terminology ;BFA8 - BFA0 to denote the nine address bits required to designate a byte address ;within a buffer. Main memory addressing is referenced using the terminology ;PA11 - PA0 and BA8 - BA0 where PA11 - PA0 denotes the 12 address bits required ;to designate a page address and BA8 - BA0 denotes the nine address bits ;required to designate a byte address within the page. ; ; ;Status Register Format ;Bit 7 6 5 4 3 2 1 0 ; RDY/BUSY COMP 1 0 0 1 X X 45DB161 ; *************************************************************************** ;* Const Def ; ;Look-up table for these sizes ->
CLOCK 8564 90 DAYS DELAYS
512k, 1M, 2M, 4M,
8M, 16M, 32M, 64M 9,
10,
10,
;flash unsigned char DF_pagebits[] //index of internal page address bits
11};
={
9,
9,
9,
9,
CALL ID DTMF 314 ;Dataflash opcodes .equ MainMemPageRead
PWM 6CH PWM 10K
ATMEL CORP AVR BUTTERFLY AVR BOOK
0x52
;Main Memory Page
0x52
;Main memory page
.equ FlashToBuf1Transfer=
0x53
;Main memory page
.equ Buf1Read
=
0x54
.equ FlashToBuf2Transfer=
0x55
;Main memory page
.equ Buf2Read
=
0x56
;Buffer 2
.equ StatusReg
=
0x57
;Status
.equ StatusRegMode3 =
0xD7
;Status register
.equ AutoPageReWrBuf1
=
0x58
;Auto page
.equ AutoPageReWrBuf2
=
0x59
;Auto page
.equ FlashToBuf1Compare
=
0x60
;Main
.equ FlashToBuf2Compare
=
0x61
;Main
0x68
;Continuous Array
0x82
;Main memory page
0x83
;Buffer 1 to main
=
0x84
0x85
;Main memory page
0x86
;Buffer 2 to main
=
0x87
0x88
;Buffer 1 to main
0x89
;Buffer 2 to main
0xD2
;Main Memory Page
0xE8
;Continuous Array
Read Inactive Clk Pol Low or High .equ FlashPageRead
ENCODE STH-11
= =
read to buffer 1 transfer ;Buffer 1
read to buffer 2 transfer read register read SPI Mode 0 or 3 rewrite through buffer 1 rewrite through buffer 2 memory page to buffer 1 compare memory page to buffer 2 compare .equ ContArrayRead = Read (Note : Only A/B-parts supported) .equ FlashProgBuf1 = program through buffer 1 .equ Buf1ToFlashWE = memory page program with built-in erase .equ Buf1Write write .equ FlashProgBuf2 = program through buffer 2 .equ Buf2ToFlashWE = memory page program with built-in erase .equ Buf2Write write .equ Buf1ToFlash = memory page program without built-in erase .equ Buf2ToFlash = memory page program without built-in erase .equ MainMemPageReadSPI = Read SPI Mode 0 or 3 .equ ContArrayReadSPI = Read SPI Mode 0 or 3
;Buffer 1
;Buffer 2
;Table 2. Program and Erase Commands .equ Buffer1Write = 0x84 ;Buffer 1 Write .equ Buffer2Write = 0x87 ;Buffer 2 Write .equ Buffer1toMem = 0x88 ;Buffer 1 to Main Memory Page Program without Built-in Erase .equ Buffer2toMem
= 0x89 ;Buffer 2 to Main Memory
.equ DFPageErase .equ DFBlockErase .equ MemPageProgBuff1
= 0x81 ;Page Erase = 0x50 ;Block Erase = 0x82 ;Main Memory Page
.equ MemPageProgBuff2
= 0x85 ;Main Memory Page
Page Program without Built-in Erase
Program through Buffer 1 Program through Buffer 2
;Table 3. Additional Commands .equ MemPagetoBuff1 = 0x53 ;Main Memory Page to Buffer 1 Transfer .equ MemPagetoBuff2
= 0x55 ;Main Memory Page to
.equ MemPagetoBuff1Cmp
= 0x60 ;Main Memory Page to
.equ MemPagetoBuff2Cmp
= 0x61 ;Main Memory Page to
.equ PageRewriteBuff1
= 0x58 ;Auto Page Rewrite
.equ PageRewriteBuff2
= 0x59 ;Auto Page Rewrite
Buffer 2 Transfer Buffer 1 Compare Buffer 2 Compare through Buffer 1 through Buffer 2
; ************************************************************************** ;* Hardware Def. ; ; RDY/BUSY - Ready/Busy .equ DFRDY_PORT = PORTD .equ DFRDY_DIR = DDRD .equ DFRDY_PIN = PIND .equ DFRDY = 7 .equ .equ .equ
DFRES_PORT = PORTD DFRES_DIR = DDRD DFRES = 5
.equ .equ .equ
DFCS_PORT = PORTC DFCS_DIR = DDRC DFCs = 2
.equ .equ .equ
MOSI_DIR = DDRB MOSI_PORT = PORTB MOSI = 3
.equ .equ .equ .equ
MISO_DIR = DDRB MISO_PORT = PORTB MISO_PIN = PINB MISO = 4
.equ .equ .equ
SCLK_DIR = DDRB SCLK_PORT = PORTB SCLK = 5
.equ .equ .equ
DFSS_DIR = DDRB DFSS_PORT = PORTB DFSS = 2
; *************************************************************************** ;**** VARIABLES .DSEG DFSize: .byte 1 DFPageSize: .byte 1 DFPageBits: .byte 1 .equ
DFBuffer = AppData
;DFBuffer: .byte 128 ;Data buffer ; !!! use AppData buffer from user.asm --> save RAM Space !!! ; !!! Self update not supported in application !!! ; *************************************************************************** .ESEG
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG ;p,x,y,z,0 ;page bits = p ;page number = x * 256 ;page size = y * 256 (264) ;type = z ; AT45DBxxx: .db 9, 2,1,0b00001100 ;AT45DB011 1Mbit .db 9, 4,1,0b00010100 ;AT45DB021 2Mbit .db 9, 8,1,0b00011100 ;AT45DB041 4Mbit .db 9,16,1,0b00100100 ;AT45DB081 8Mbit .db 10,16,2,0b00101100 ;AT45DB161 16Mbit .db 10,32,2,0b00110100 ;AT45DB321 32Mbit .db 11,32,4,0b00111000 ;AT45DB642 64Mbit .db 11,64,4,0b00010000 ;AT45DB1282 128Mbit .dw 0,0
; **************************************************************************** ;*** S P I R U T I N S ;*** ; **************************************************************************** ;* SPI_init ;* ;* Initialize our port pins for use as SPI master. ;* ; *************************************************************************** ; SPI_init: sbi DFCS_PORT,DFCS ;DFlash CE pin is output for ATmega sbi DFCS_DIR,DFCS ;CS=1 sbi sbi
DFRES_PORT,DFRES DFRES_DIR,DFRES
;DFlash
cbi sbi
DFRDY_DIR,DFRDY DFRDY_PORT,DFRDY
;DFlash R/B
in andi ori out
R16,PORTB R16,0b11000011 R16,0b00101100 PORTB,R16
;SS, MOSI,
in andi ori out
R16,DDRB R16,0b11000011 R16,0b00101100 DDRB,R16
ldi out
R16,0b01011100 SPCR,R16
Reset = H
pullup input
SCK output; MISO input
;[7] - SPIE: SPI
Interrupt Enable ;[6] - SPE: SPI Enable ;[5] - DORD: Data Order ;[4] - MSTR: Master/ Slave Select ;[3] - CPOL: Clock Polarity ;[2] - CPHA: Clock Phase ;[1:0] - SPR1,SPR0: SPI Clock Rate Select ; SPI2X SPR1 SPR0 SCK Frequency 0
;
0
0
;
0
0
1
;
0
1
;
0
1
;
1
0
;
1
0
;
1
1
;
1
1
fosc/4
0
fosc/16 fosc/64
1
fosc/128
0
fosc/2
1 0
fosc/8
1
fosc/32 fosc/64 ldi out
R16,0b00000001 SPSR,R16
;[7] - SPIF: SPI
Interrupt Flag ;[6] - WCOL: Write COLlision flag ;[5:1] - Res: Reserved Bits ;[0] - SPI2X: Double SPI Speed Bit in in
R16,SPSR R16,SPDR
cbi
DFRES_PORT,DFRES
;Clear SPIF & WCOL
bits
;DFlash
Reset ;DFlash Reset>10us ldi ldi brne
ZL,low(SYSCLK/100000) ZH,High(SYSCLK/100000) sbiw ZL,1 W10us1
sbi
DFRES_PORT,DFRES
;DFlash
ldi
R16,50
;Reset
brne
dec W10us2
rcall cbr ldi
DF_ReadStatus R16,0b11000011 ZL,low(AT45DBxxx*2)
ldi lpm sts lpm sts lpm sts lpm cp breq tst brne
ZH,high(AT45DBxxx*2) R17,Z+ DFPageBits,R17 R18,Z+ DFSize,R18 R18,Z+ DFPageSize,R18 R2,Z+ R16,R2 DFHit R17 SearchDF
W10us1:
Reset = 1
Recoveri time = 1 us W10us2:
R16
;ATmega128 -
> set PAMPZ!! SearchDF:
DFHit: ret ; ***************************************************************************** ;*DF_SPI_RW ;* ;* Read and writes one byte from/to SPI master ;* ;* In: R16 - Byte to be written to SPI data register ;* ;* Out: R16 - Byte read from SPI data register ;* ; ****************************************************************************** ; DF_SPI_RW: out SPDR,R16 DF_SPI_RW0: sbis SPSR,spif rjmp DF_SPI_RW0 ;wait for transfer complete, poll SPIF-flag in R16,SPDR ret ; ***************************************************************************** ;*Read_DF_status ;* ;* Status info concerning the Dataflash is busy or not. ;* Status info concerning compare between buffer and flash page ;* Status info concerning size of actual device ;* ;* In: ;* ;* Out: R16 - status byte. Consult Dataflash datasheet for further decoding info ;* ; ****************************************************************************** ; DF_ReadStatus: sbi DFCS_PORT,DFCS ;DF CS inactive nop nop cbi DFCS_PORT,DFCS ;DF CS Active! ;to reset dataflash command decoder ldi R16,StatusRegMode3 rcall DF_SPI_RW ;send status register read op-code clr R16 rcall DF_SPI_RW ;dummy write to get result ret
; ***************************************************************************** ;* WaitToDF ;* ;* Wait for DataFlash to Ready ;* ;* In: ;* ;* Out: ;* ; ****************************************************************************** ; WaitToDF: rcall DF_ReadStatus cbr R16,0x7F Csak a Busy Flag marad meg breq WaitToDF monitor the status register, wait until busy-flag is high sbi DFCS_PORT,DFCS inactive nop cbi DFCS_PORT,DFCS Active! , reset dataflash command decoder ret
; ; ;DF CS
;DF CS
; ***************************************************************************** ;Page_To_Buffer ; ; Transfers a page from flash to dataflash SRAM buffer ; ; In: R0 = BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 = PageAdr -> Address of page to be transferred to buffer ; ; Out: ; ***************************************************************************** ; DF_PageToBuffer: rcall WaitToDF ldi R16,FlashToBuf1Transfer ;transfer to buffer 1 op-code tst R0 breq DF_PageToBuff01 ldi R16,FlashToBuf2Transfer ;transfer to buffer 2 op-code DF_PageToBuff01: rcall DF_SPI_RW ;send opcode lds R16,DFPageBits subi R16,8 DF_PageToBuff02: lsl R18 rol R19 dec R16 brne DF_PageToBuff02 mov rcall
R16,R19 DF_SPI_RW
;upper part of page
mov rcall
R16,R18 DF_SPI_RW
;lower part of page
clr rcall
R16 DF_SPI_RW
sbi
DFCS_PORT,DFCS
address
address
;DF CS
inactive ret
; ***************************************************************************** ;DF_BufferReadByte ; ; Reads one byte from one of the dataflash internal SRAM buffers ; ; In: R0 = BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 = IntPageAdr -> Internal page address ; ; Out: R16 - One read byte (any value) ; ; ***************************************************************************** ; DF_BufferReadByte: rcall WaitToDF ldi R16,Buf1Read ;read byte from buffer 1 tst R0 breq BufferReadByte01 ldi R16,Buf2Read ;read byte from buffer 2 BufferReadByte01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address clr R16 rcall DF_SPI_RW ;additional don't cares clr R16 rcall DF_SPI_RW ;read byte sbi DFCS_PORT,DFCS ;DF CS inactive ret
; ***************************************************************************** ;DF_BufferReadStr ; ; Reads one or more bytes from one of the dataflash internal SRAM buffers, ; and puts read bytes into buffer pointed to by X ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address ; R21:R20 -> Number of bytes to be read ; X -> address of buffer to be used for read bytes ; ; Out: ; ; ***************************************************************************** ; DF_BufferReadStr: rcall WaitToDF ldi R16,Buf1Read ;read byte from buffer 1 tst R0 breq DF_BufferReadStr01 ldi R16,Buf2Read ;read byte from buffer 2 DF_BufferReadStr01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address clr R16 rcall DF_SPI_RW ;additional don't cares push YL push YH movw YL,R20 ;Internal page address + Number of bytes to be read <= Page Size!!! DF_BufferReadStr02: clr R16 rcall DF_SPI_RW st X+,R16 ;Store DF data byte sbiw YL,1 brne DF_BufferReadStr02 pop YH pop YL sbi DFCS_PORT,DFCS ;DF CS inactive ret ; ***************************************************************************** ; DF_BufferWriteEnable ; ; Enables continous write functionality to one of the dataflash buffers ; NOTE : User must ensure that CS goes high to terminate this mode ; before accessing other dataflash functionalities ; ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address to start writing from ; ; Out: None ; ; ***************************************************************************** ; DF_BufferWriteEnable: rcall WaitToDF ldi R16,Buf1Write ;buffer 1 write op-code tst R0 breq DF_BufferWriteEnable01 ldi R16,Buf2Write ;buffer 2 write op-code DF_BufferWriteEnable01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address ret ; ***************************************************************************** ; DF_BufferWriteByte: ; ; Writes one byte to one of the dataflash internal SRAM buffers ; ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address to write byte to ; R16 -> Data byte to be written ; ; Out: None ; ; ***************************************************************************** ; DF_BufferWriteByte: push R16 rcall WaitToDF ldi R16,Buf1Write ;buffer 1 write op-code tst R0 breq DF_BufferWriteByte01 ldi R16,Buf2Write ;buffer 2 write op-code DF_BufferWriteByte01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address pop R16 rcall DF_SPI_RW ;write data byte DF_EndWrite: sbi DFCS_PORT,DFCS ;DF CS inactive ret ; ***************************************************************************** ; DF_BufferWriteStr ; ; Copies one or more bytes to one of the dataflash internal SRAM buffers ; from AVR SRAM buffer pointed to by X ; ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address ; R21:R20 -> Number of bytes to be read ; X -> address of buffer to be used for write bytes ; ; Out: None ; ; ***************************************************************************** ; DF_BufferWriteStr: rcall WaitToDF ldi R16,Buf1Write ;write byte to buffer 1 tst R0 breq DF_BufferWriteStr01 ldi R16,Buf2Write ;write byte to buffer 2 DF_BufferWriteStr01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address push YL push YH movw YL,R20 ;Internal page address + Number of bytes to be read <= Page Size!!! DF_BufferWriteStr02: ld R16,X+ ;Store DF data byte rcall DF_SPI_RW sbiw YL,1 brne DF_BufferWriteStr02 pop YH pop YL ret ; ***************************************************************************** ; DF_BufferToPage ; DF_BufferToPageWErase ; ; Transfers a page from dataflash SRAM buffer to flash ; ; In: R0 = BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 = PageAdr -> Address of flash page to be programmed ; ; Out: None ; ; ***************************************************************************** ; DF_BufferToPage: rcall WaitToDF ldi R16,Buffer1toMem ;buffer 1 to flash without erase tst R0 breq DF_BufferToPage01 ldi R16,Buffer1toMem rjmp DF_BufferToPage01 DF_BufferToPageWErase: rcall WaitToDF ldi R16,Buf1ToFlashWE
;buffer 1
to flash with erase op-code tst breq ldi
R0 DF_BufferToPage01 R16,Buf2ToFlashWE
;buffer 2
DF_SPI_RW
;send op-
to flash with erase op-code DF_BufferToPage01: rcall code lds subi DF_BufferToPage02: lsl rol dec brne
R16,DFPageBits R16,8 R18 R19 R16 DF_BufferToPage02
mov rcall
R16,R19 DF_SPI_RW
;upper part of page
mov rcall
R16,R18 DF_SPI_RW
;lower part of page
clr rcall nop sbi
R16 DF_SPI_RW
address
address
DFCS_PORT,DFCS
;DF CS
inactive ret ; ***************************************************************************** ; DF_PageErase ; ; Erase Flash Page ; ; In: R19:R18 = PageAdr -> Address of flash page to be erased ; ; Out: None ; ; ***************************************************************************** ; DF_PageErase: rcall WaitToDF ldi R16,DFPageErase rcall DF_SPI_RW ;send opcode lds subi DF_PageErase01: lsl rol dec brne
R16,DFPageBits R16,8 R18 R19 R16 DF_PageErase01
mov rcall
R16,R19 DF_SPI_RW
;upper part
mov rcall
R16,R18 DF_SPI_RW
;lower part
clr rcall
R16 DF_SPI_RW
;dumpy part
nop sbi
DFCS_PORT,DFCS
;DF CS
of page address
of page address
of address!!!
inactive ret
; ***************************************************************************** ; DF_CheckErasedPage ; ; Test Erased Flash Page ; ; In: R19:R18 = PageAdr -> Address of flash page to be tested ; R0 = used buffer 0 = buffer0 other = buffer1 ; ; Out: c=0 no error ; c=1 Bad Page! Dont use!! ; ; ***************************************************************************** ; DF_CheckErasedPage: rcall WaitToDF push R0 rcall DF_PageToBuffer
ldi lds mul add adc
clr XL R16,8 XH,DFPageSize R16,XH XL,R0 XH,R1
lenght of page in byte pop
R0
push push push sbiw movw rcall pop pop pop cpi
R0 XL XH XL,1 R18,XL DF_BufferReadByte XH XL R0 R16,0xFF
DF_Check00:
http://avr-asm.tripod.com/dfat45.html (1 of 2)1/20/2009 8:49:19 PM
;X full
16 BIT MATH (AVR 202)
brne sbiw brne clc ret
DF_BadPage XL,1 DF_Check00 ;ok page
cleared well DF_BadPage: sec ret
;Bad Page!
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dfat45.html (2 of 2)1/20/2009 8:49:19 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
COMPACT FLASH CARD INTERFACE HOME RETRO_DAN ;*************************************************************************** ; ; File Name :'cf.asm" ; Title :Compact Flash Common Memory Mode Driver ; Date :2004.05.12. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AVR ; ;*************************************************************************** ; D E S C R I P T I O N ; ; Memory Interface to a compact flash card. ; Compact flash card is used in memory mapped mode. ; Registers are located at ADR_CFC in external RAM space of Mega128 ; ; ;*************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2004.05.12 VFX Creation ; ;*************************************************************************** ;Hardware ;*************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ;*************************************************************************** ; ; ;************************************************************************** ;* Hardware Def. ; ; CompactFlash hardware definitions ; Table 34: Memory Mapped Decoding ; -REG A10 A9-A4 A3 A2 A1 A0 Offset -OE=0 -WE=0 Notes ; 1 0 X 0 0 0 0 0 Even RD Data Even WR Data 1, 2 ; 1 0 X 0 0 0 1 1 Error Features 1, 2 ; 1 0 X 0 0 1 0 2 Sector Count Sector Count ; 1 0 X 0 0 1 1 3 Sector No. Sector No. ; 1 0 X 0 1 0 0 4 Cylinder Low Cylinder Low ; 1 0 X 0 1 0 1 5 Cylinder High Cylinder High ; 1 0 X 0 1 1 0 6 Select Card/Head Select Card/Head ; 1 0 X 0 1 1 1 7 Status Command ; 1 0 X 1 0 0 0 8 Dup. Even RD Data Dup. Even WR Data 2 ; 1 0 X 1 0 0 1 9 Dup. Odd RD Data Dup. Odd WR Data 2 ; 1 0 X 1 1 0 1 D Dup. Error Dup. Features 2 ; 1 0 X 1 1 1 0 E Alt Status Device Ctl ; 1 0 X 1 1 1 1 F Drive Address Reserved ; 1 1 X X X X 0 8 Even RD Data Even WR Data 3 ; 1 1 X X X X 1 9 Odd RD Data Odd WR Data 3
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
;Note: 1) Register 0 is accessed with -CE1 low and -CE2 low as a word register ;on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may ;also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and ;-CE2 high. Note that the address space of this word register overlaps ;the address space of the Error and Feature byte-wide registers that lie at ;offset 1. When accessed twice as byte register with -CE1 low, the first byte ;to be accessed is the even byte of the word and the second byte accessed ;is the odd byte of the equivalent word access. ;A byte access to address 0 with -CE1 high and -CE2 low accesses the error ;(read) or feature (write) register.
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
;2) Registers at offset 8, 9 and D are non-overlapping duplicates of the ;registers at offset 0 and 1. Register 8 is equivalent to register 0, ;while register 9 accesses the odd byte. Therefore, if the registers are byte ;accessed in the order 9 then 8 the data will be transferred odd byte then even ;byte. Repeated byte accesses to register 8 or 0 will access consecutive ;(even then odd) bytes from the data buffer. Repeated word accesses to register ;8, 9 or 0 will access consecutive words from the data buffer. Repeated byte ;accesses to register 9 are not supported. However, repeated alternating byte ;accesses to registers 8 then 9 will access consecutive (even then odd) bytes ;from the data buffer. Byte accesses to register 9 access only the odd byte of ;the data.
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
;3) Accesses to even addresses between 400h and 7FFh access register 8. ;Accesses to odd addresses between 400h and 7FFh access register 9. This ;1 Kbyte memory window to the data register is provided so that hosts can ;perform memory to memory block moves to the data register when the register ;lies in memory space. ;
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
; ;CF register addresses ; .equ CF_EvenData .equ CF_OddData .equ CF_Error .equ CF_SECCOUNT .equ CF_LBA0 .equ CF_LBA1 .equ CF_LBA2 .equ CF_LBA3 .equ CF_STACOM .equ CF_DecCont
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
= = = = = = = = = =
ADR_CFC+0x08 ADR_CFC+0x09 ADR_CFC+0x0D ADR_CFC+0x02 ADR_CFC+0x03 ADR_CFC+0x04 ADR_CFC+0x05 ADR_CFC+0x06 ADR_CFC+0x07 ADR_CFC+0x0E
;Dupl. DAta ;Dupl. Data ;Dupl. Errors / Features ;Sectorcount ;LBA 0-7 ;LBA 8-15 ;LBA 16-23 ;LBA 24-27 ;Status / Command ;
90 DAYS DELAYS ;Class 1 ;Upon receipt of a Class 1 command, the CompactFlash Storage Card sets BSY ;within 400 nsec.
CALL ID DTMF 314 PWM 6CH PWM 10K
;Class 2 ;Upon receipt of a Class 2 command, the CompactFlash Storage Card sets BSY ;within 400 nsec, sets up the sector buffer for a write operation, sets DRQ ;within 700 usec, and clears BSY within 400 nsec of setting DRQ.
ENCODE STH-11 ATMEL CORP
;Class 3 ;Upon receipt of a Class 3 command, the CompactFlash Storage Card sets BSY ;within 400 nsec, sets up the sector buffer for a write operation, sets DRQ ;within 20 msec (assuming no re-assignments), and clears BSY within 400 nsec ;of setting DRQ.
AVR BUTTERFLY AVR BOOK
;Table 37: CF-ATA Command Set ; ;Class COMMAND Code FR SC SN CY DH LBA ;1 Check Power Mode E5h or 98h - - - - D ;1 Execute Drive Diagnostic 90h - - - - D ;1 Erase Sector(s) C0h - Y Y Y Y Y ;1 Flush Cache E7h - - - - D ;2 Format Track 50h - Y - Y Y Y ;1 Identify Drive ECh - - - - D ;1 Idle E3h or 97h - Y - - D ;1 Idle Immediate E1h or 95h - - - - D ;1 Initialize Drive Parameters 91h - Y - - Y ;1 Key Management Structure Read B9 Feature 0-127 C C C C D C ;1 Key Management Read Keying Material B9 Feature 80 C C C C D C ;2 Key Management Change Key Management Value B9 Feature 81 C C C C D C ;1 NOP 00h - - - - D ;1 Read Buffer E4h - - - - D ;1 Read Long Sector 22h or 23h - - Y Y Y Y ;1 Read Multiple C4h - Y Y Y Y Y ;1 Read Sector(s) 20h or 21h - Y Y Y Y Y ;1 Read Verify Sector(s) 40h or 41h - Y Y Y Y Y ;1 Recalibrate 1Xh - - - - D ;1 Request Sense 03h - - - - D ;1 Security Disable Password F6h - - - - D ;1 Security Erase Prepare F3h - - - - D ;1 Security Erase Unit F4h - - - - D ;1 Security Freeze Lock F5h - - - - D ;1 Security Set Password F1h - - - - D ;1 Security Unlock F2h - - - - D ;1 Seek 7Xh - - Y Y Y Y ;1 Set Features EFh Y - - - D ;1 Set Multiple Mode C6h - Y - - D ;1 Set Sleep Mode E6h or 99h - - - - D ;1 Standby E2h or 96h - - - - D ;1 Standby Immediate E0h or 94h - - - - D ;1 Translate Sector 87h - Y Y Y Y Y ;1 Wear Level F5h - - - - Y ;2 Write Buffer E8h - - - - D ;2 Write Long Sector 32h or 33h - - Y Y Y Y ;3 Write Multiple C5h - Y Y Y Y Y ;3 Write Multiple w/o Erase CDh - Y Y Y Y Y ;2 Write Sector(s) 30h or 31h - Y Y Y Y Y ;2 Write Sector(s) w/o Erase 38h - Y Y Y Y Y ;3 Write Verify 3Ch - Y Y Y Y Y ; ;Definitions: ;FR = Features Register ;SC = Sector Count Register ;SN = Sector Number Register ;CY = Cylinder Registers ;DH = Card/Drive/Head Register ;LBA = Logical Block Address Mode Supported (see command descriptions for use). ;Y - The register contains a valid parameter for this command. For the Drive/Head Register Y ;means both the CompactFlash Storage Card and head parameters are used; D - only the ;CompactFlash Storage Card parameter is valid and not the head parameter; C - The register ;contains command specific data (see command descriptions for use). ; ;CF-ATA Command Set .equ CF_CMD_READ_SEC = 0x20 .equ CF_CMD_WRITE_SEC = 0x30 .equ CF_CMD_IDENTIFY = 0xEC
.equ .equ
CFRDY CFVS1
= 2 = 3
;bit 2 = 1 CF ready ;bit 3 = 0 CF in slot
; *************************************************************************************** ;*** Definition of the status register bits ;*** ;*** Bit7 Bit0 ;*** BSY DRDY DWF DSC DRQ CORR IDX ERR ; *************************************************************************************** .equ CFC_STATUS_BSY = 0x80 ;Busy flag .equ CFC_STATUS_DRDY = 0x40 ;Drive ready .equ CFC_STATUS_DWF = 0x20 ;Drive write fault .equ CFC_STATUS_DSC = 0x10 ;Drive seek complete .equ CFC_STATUS_DRQ = 0x08 ;Data request .equ CFC_STATUS_CORR = 0x04 ;Corrected data .equ CFC_STATUS_IDX = 0x02 ;Index .equ CFC_STATUS_ERR = 0x01 ;Error
; ;*************************************************************************** ;**** VARIABLES .DSEG ;*************************************************************************** .ESEG
;*************************************************************************** ;**** CODE SEG ;*************************************************************************** .CSEG
;******************************************************** ;CFRdy ; ; Wait until CF not busy ; ; Out: c= 0 no error ; 1 error ; ; Alt: R16,R17 ; CFHWRdy: lds R16,ADR_CFST bst R16,CFVS1 ;CF inserted? brtc CFHWRdy0 rjmp CFDrvError CFHWRdy0: lds R16,ADR_CFST bst R16,CFRDY ;CF ready? brtc CFHWRdy clc ret ;******************************************************** ;CFWaitDRQ ; ; Wait until Data will available ; ; Out: c= 0 no error ; 1 error ; ; Alt: R16,R17 ; CFWaitDRQ: rcall CFHWRdy brcc CFWaitDRQ00 ret CFWaitDRQ00: lds R16,CF_STACOM bst R16,0 brtc CFWaitDRQ0 CFWaitErr: ldi R16,low(0xFFF0) ;Error in last command ldi R17,high(0xFFF0) ;ide keresunk egy error kodot!!! sec ret CFWaitDRQ0: andi cpi brne clc ret
R16,0xF8 R16,0x58 CFWaitDRQ
;******************************************************** ;CFWaitReady ; ; Wait until CF will ready ; ; Out: c= 0 no error ; 1 error ; ; Alt: R16,R17 ; CFWaitReady: rcall CFHWRdy brcc CFWaitRdy0 ret CFWaitRdy0: lds R16,CF_STACOM bst R16,0 brts CFWaitErr CFWaitReady01: andi R16,0xF0 cpi R16,0x50 brne CFWaitReady clc ret ;******************************************************** ;CFReadSector ; ; In: R13:R12:R11:R10 - LBA sector number ; Page: Y - Pointer to Data Buffer [512 byte] ; Z - Phis. Drive Descriptor ; ; Out: c= 0 no error ; 1 error ; CFReadSector: ldd R0,Z+MaxSector+0 ldd R1,Z+MaxSector+1 ldd R2,Z+MaxSector+2 ldd R3,Z+MaxSector+3 cp R10,R0 cpc R11,R1 cpc R12,R2 cpc R13,R3 brcs CFReadSec00 ldi ldi sec ret
R16,low(ERROR_SECTOR_NOT_FOUND) ;Sector number too big R17,high(ERROR_SECTOR_NOT_FOUND)
CFReadSec00: std std std std
Z+CurrentSector+0,R10 Z+CurrentSector+1,R11 Z+CurrentSector+2,R12 Z+CurrentSector+3,R13
rcall brcc ret
CFWaitReady CFReadSec01 ;Error in last command
CFReadSec01: ldi sts nop sts nop sts nop sts ldi and ori sts
R16,1 CF_SECCOUNT,R16
ldi sts
R16,CF_CMD_READ_SEC CF_STACOM,R16
;Set Read Sector Command
ldi ldi
XL,0 XH,1
;if X==0 -> X=256 word;
movw
R0,YL
;save Y reg.
rcall brcc ret
CFWaitDrq CFReadSec02
CF_LBA0,R10
;D7..D0
CF_LBA1,R11
;D15..D8
CF_LBA2,R12 R16,0x0F R16,R13 R16,0xE0 CF_LBA3,R16
;D23..D16
;set LBA mode ;D27..D24 + LBA mode + Drive0
;Drive error
CFReadSec02: lds bst brts bst brtc
R16,ADR_CFST R16,CFVS1 CFDrvError R16,CFRDY CFReadSec02
lds st lds st sbiw brne
R16,CF_EvenData Y+,R16 R16,CF_OddData Y+,R16 XL,1 CFReadSec02
movw clc ret
YL,R0
ldi ldi sec ret
R16,low(ERROR_BAD_UNIT) R17,high(ERROR_BAD_UNIT) ;Drive not present
;CF inserted? ;CF ready?
;restore Y reg.
CFDrvError:
;******************************************************** ;CFWriteSector ; ; In: R13:R12:R11:R10 - LBA sector number ; Page: Y - Pointer to Data Buffer [512 byte] ; Z - Phis. Drive Descriptor ; ; Out: c= 0 no error ; 1 error ; CFWriteSector: ldd R0,Z+MaxSector+0 ldd R1,Z+MaxSector+1 ldd R2,Z+MaxSector+2 ldd R3,Z+MaxSector+3 cp R10,R0 cpc R11,R1 cpc R12,R2 cpc R13,R3 brcs CFWriteSec00 ldi ldi sec ret CFWriteSec00: rcall brcc ret CFWriteSec01: ldi sts nop sts nop sts nop sts ldi and ori sts ldi sts
R16,low(ERROR_SECTOR_NOT_FOUND) ;Sector number too big R17,high(ERROR_SECTOR_NOT_FOUND)
CFWaitReady CFWriteSec01 ;Error in last command R16,1 CF_SECCOUNT,R16 CF_LBA0,R10
;D7..D0
CF_LBA1,R11
;D15..D8
CF_LBA2,R12 R16,0x0F R16,R13 R16,0xE0 CF_LBA3,R16 R16,CF_CMD_WRITE_SEC CF_STACOM,R16
;D23..D16
ldi ldi
XL,0 XH,1
movw
R0,YL
rcall brcc ret CFWriteSec02: lds bst brts bst brtc
;set LBA mode ;D27..D24 + LBA mode + Drive0 ;Write sector command
;if X==0 -> X=256 word;
CFWaitDrq CFWriteSec02 ;Drive error R16,ADR_CFST R16,CFVS1 CFDrvError R16,CFRDY CFWriteSec02
ld sts ld sts sbiw brne
R16,Y+ CF_EvenData,R16 R16,Y+ CF_OddData,R16 XL,1 CFWriteSec02
movw clc ret
YL,R0
;CF inserted? ;CF ready?
;******************************************************** ;CFResetDevice ; ; In: ; ; Out: c= 0 no error ; 1 error R17:R16 error code ; CFResetDevice: ldi R16,0b00000100 ;Force SW reset sts ADR_CFC+0x0E,R16 ;Device Control Register ldi R16,64 CFRes0: dec R17 brne CFRes0 dec R16 brne CFRes0 clr R16 sts ADR_CFC+0x0E,R16 ;Device Control Register rcall CFWaitReady ret
;******************************************************** ;CFIdentify ; ; In: Z - Phis. Drive Descriptor ; Page: Y - Pointer to temporary Data Buffer [512 byte] ; ; Out: c= 0 no error ; 1 error ; CFIdentify: rcall CFWaitReady brcc CFIdent01 ret ;Error code in R17:R16 CFIdent01: ldi R16,1 sts CF_SECCOUNT,R16 clr R16 sts CF_LBA0,R16 nop sts CF_LBA1,R16 nop sts CF_LBA2,R16 ldi R16,0xE0 sts CF_LBA3,R16 ldi R16,CF_CMD_IDENTIFY sts CF_STACOM,R16 ldi ldi movw
XL,0 XH,1 R0,YL
;read fixed 256 word
call brcc ret
CFWaitDRQ CFIdent02
lds st nop lds st sbiw brne
R16,CF_EvenData Y+,R16
movw
YL,R0
clr ldd cpi brne ldd cpi brne inc
R0 R16,Y+0 R16,0x8A CFIDs0 R16,Y+1 R16,0x84 CFIDs0 R0
std
Z+MediaFlag,R0
ldi std
R16,RemovableMedia Z+MediaType,R16
ldi std
R16,0x80 Z+DiskNumber,R16
ldd ldd std std
R16,Y+2 R17,Y+3 Z+Cylinders+0,R16 Z+Cylinders+1,R17
;Drive error
CFIdent02:
R16,CF_OddData Y+,R16 XL,1 CFIdent02
;CF IDs: 848Ah
CFIDs0:
std
ldd R16,Y+6 Z+Heads,R16
;Store CF ID
;First HDD => HDD0
;Default tracks/cylinders
;Default Heads
ldd std
R16,Y+12 Z+SectorsPerTrack,R16
;default Sectors per track
ldd std ldd std ldd std ldd std
R16,Y+14 Z+MaxSector+2,R16 R16,Y+15 Z+MaxSector+3,R16 R16,Y+16 Z+MaxSector+0,R16 R16,Y+17 Z+MaxSector+1,R16
;Number of Sectors per Card ;MSW -LSW !!!
clc ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout http://avr-asm.tripod.com/flashcard.html (1 of 2)1/20/2009 8:49:58 PM
16 BIT MATH (AVR 202)
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/flashcard.html (2 of 2)1/20/2009 8:49:58 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SMART MEDIA MANAGER FOR SMIL HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ; ; File Name :'SmartM.asm" ; Title :SmartMedia Driver for External SMIL Controller ; Date :2003.05.05. ; Version :1.11.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; VFX SMIL Smart Media Manager ; ;Why is FTL needed? ; • Flash are not 100% perfect . It needs bad block management. ; • Flash is erased in blocks(typical 16KB) larger than disk sectors(512Byte) ; • Flash has a limited number of erase cycles (1M Cycles). So it needs wear-leveling algorithm. ; • Flash is essentially non-writable (must be erased before it can be written) ; ; · Converts the sector addresses addressed by the host to physical addresses of Flash Memory ; · Converts host requests into the programming/ erasing algorithms of associated Flash technology ; · Detects the error and replaces the encountered bad sectors with the good by mapping them out ; -------------------------------------------------------------------------------------; Linear address Logical Address ; - Address Map, Address Configuration ; I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 ;1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 CA0 ~ CA7 : column address ;2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 PA0 ~ PA7 : page address 1 ;3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 PA8 ~ PA15 : page address 2 ;4th Cycle A25 A26 PA16 ~ PA23 : page address 3 ; ;Model Valid Page Address Fixed Low ;2MB PA0 ~ PA12 PA13 ~ PA15 ;4MB PA0 ~ PA12 PA13 ~ PA15 ;8MB PA0 ~ PA13 PA14 ~ PA15 ;16MB PA0 ~ PA14 PA15 ;32MB PA0 ~ PA15 ;64MB PA0 ~ PA16 PA17 ~ PA23 ;128MB PA0 ~ PA17 PA18 ~ PA23 ; ; -------------------------------------------------------------------------------------; Considerations for High Density Considerations for High Density SmartMedia ; Zone-based block management for 32MB,64MB and 128MB ; ;Zone Physical Block Description ; 0 0 CIS/Identify Drive Information Area ; 0 1 ~ 1023 Data Area (Logical Block : 0 ~ 999) ; 1 0 ~ 1023 Data Area (Logical Block :1000 ~1999) ; ... ; Last 0 ~ 1023 Data Area (Logical Block : Zone x 1000 + 999 ) ; ;* CIS/Identify Drive Information Area ==>Zone 0 ; Each zone has 1000 data blocks. ; -------------------------------------------------------------------------------------; ; CIS (Card Information System) Area 1 and CIS (Card Information System) Area (1 and 2) Physical BLOCK 1 ; ;Addr Data Contents ; ;00 01h Tuple ID(CIS TPL_Device) ;01 03h Link to Next Tuple ;02 D9h Device Type : I/O, Rate : 250ns ;03 01h Device Size : 2 K Byte ;04 FFh End of Device ID Tuple ;05 01h Tuple ID(CIS TPL_JEDEC_C) ;06 20h Link to Next Tuple ;07 DFh JEDEC Manufacture ID(PC Card ATA) ;08 18h JEDEC Device ID(VPP not required) ;09 02h Tuple ID(CIS TPL_MANF ID) ;0A 04h Link to Next Tuple ;0B 00h Manufacture Code ;0C 00h Manufacture Code ;0D 00h Manufacture Info. ;0E 00h Manufacture Info. ;0F 21h Tuple ID(CIS TPL_FUNC ID) ;10 02h Link to Next Tuple ;11 04h PL FID_FUNCTION ;12 01h TPL_FID_SYS INIT ;13 22h Tuple ID(CIS TPL_FUNCE) ;14 02h Link to Next Tuple ;15 01h Disk Device Interface Tuple ;16 01h PC Card ATA Interface ;17 22h Tuple ID(CIS TPL_FUNCE) ;18 03h Link to Next Tuple ;19 02h PC Card ATA Extension Tuple ;1A 04h ATA Function Byte1 ;1B 07h ATA Function Byte2 ;1C 1Ah Tuple ID(CIS TPL_CONFIG) ;1D 05h Link to Next Tuple ;1E 01h Field Size Byte ;1F 03h Last Entry in the Card Configuration Table ;20 00h CCR Base Address(Low-order Byte) ;21 02h CCR Base Address(High-order Byte) ;22 0Fh CCR Present Mask ;23 1Bh Tuple ID(CIS TPL_CFTABLE_ENTRY) ;24 08h Link to Next Tuple ;25 C0h Configuration Table Index Byte ;26 C0h Interface Description Field ;27 A1h Feature Selection Byte ;28 01h Power Parameter Selection Byte ;29 55h Power Voltage(5V) ;2A 08h Memory Space(Low-order byte) ;2B 00h Memory Space(High-order byte) ;2C 20h Miscellaneous (ex: CCSR power down) ;2D 1Bh Tuple ID(CIS TPL_CFTABLE_ENTRY) ;2E 0Ah Link to Next Tuple ;2F C1h Configuration Table Index Byte ;30 41h Interface Description Field ;31 99h Feature Selection Byte ;32 01h Power Parameter Selection Byte ;33 55h Power Voltage(5V) ;34 64h I/O Space Description Byte ;35 F0h Interrupt IRQ Condition Info. ;36 FFh Interrupt IRQs 0 to 7 ;37 FFh Interrupt IRQs 8 to 15 ;38 20h Miscellaneous (ex: CCSR power down) ;39 1Bh Tuple ID [I/O Primary] ;3A 0Ch Link to Next Tuple ;3B 82h Configuration Table Index Byte ;3C 41h Interface Description Field ;3D 18h Feature Selection Byte ;3E EAh I/O Space Description Byte ;3F 61h I/O Range Description Byte ;40 F0h I/O Address Range(01F0h-01F7h) ;41 01h I/O Address Range(01F0h-01F7h) ;42 07h 8 Bytes ;43 F6h I/O Address Range(03F6h-03F7h) ;44 03h I/O Address Range(03F6h-03F7h) ;45 01h 2 Bytes ;46 EEh IRQ Condition Info. (IRQ14) ;47 1Bh Tuple ID[I/O secondary] ;48 0Ch Link to Next Tuple ;49 83h Configuration Table Index Byte ;4A 41h Interface Description Field ;4B 18h Feature Selection Byte ;4C EAh I/O Space Description Byte ;4D 61h I/O Range Description Byte ;4E 70h I/O Address Range(0170h-0177h) ;4F 01h I/O Address Range(0170h-0177h) ;50 07h 8 Bytes ;51 76h I/O Address Range(0376h-0377h) ;52 03h I/O Address Range(0376h-0377h) ;53 01h 2 Bytes ;54 EEh IRQ Condition Info. (IRQ14) ;55 15h Tuple ID(CIS TPL_VERS_1) ;56 14h Link to Next Tuple ;57 05h Major Version Number[Ver.5] ;58 00h Minor Version Number[Ver.0] ;59 20h Name of Manufacture ;5A 20h Name of Manufacture ;5B 20h Name of Manufacture ;5C 20h Name of Manufacture ;5D 20h Name of Manufacture ;5E 20h Name of Manufacture ;5F 20h Name of Manufacture ;60 00h End of Manufacture Name ;61 20h Name of Product ;62 20h Name of Product ;63 20h Name of Product ;64 20h Name of Product ;65 00h End of Product Name ;66 30h Product Version “0” ;67 2Eh Product Version "." ;68 30h Product Version "0" ;69 00h End of Product Version ;6A FFh End of Product Info. Tuple ;6B 14h CIS TPL_NO_LINK ;6C 00h Link to Next Tuple ;6D FFh CIS TPL_END ;6E-7F 00h Null-Tuple ; ; -------------------------------------------------------------------------------------; ; Logical Format Parameter ; ; 1 MB 2 MB 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB ;NumCylinder 125 125 250 250 500 500 500 500 ;NumHead 4 4 4 4 4 8 8 16 ;NumSector 4 8 8 16 16 16 32 32 ;SumSector 2,000 4,000 8,000 16,000 32,000 64,000 128,000 256,000 ;SectorSize 512 512 512 512 512 512 512 512 ;Logical Block Size 4k 4k 8k 8k 16k 16k 16k 16k ;Unformatted 1MB 2MB 4MB 8MB 16MB 32MB 64MB 128MB ;Formatted 0.977MB 1.953MB 3.906MB 7.813MB 16.63MB 31.25MB 62.5MB 125MB ; ; Physical Format Parameter ; ;Page Size (byte) 256+8 256+8 512+16 512 +16 512+16 512+16 512+16 512+16 (byte/sectror) ;Number of page/block ? 16 16 16 32 32 32 32 (sectror/Cluster) ;Number of block/device ? 512 512 1024 1024 2048 4096 8192 (Cluster)
; -------------------------------------------------------------------------------------; Sector Data Structure ; [1 Sector = 1 Page] ; 0-255 Data Area-1 ; 256-511 Data Area-2 ; ; Spare Area Information (4 ~ 128 MB) ; 512-515 Reserved Area ; 516 Data/User Status Flag/Area ; 517 Block Status Flag/Area ; 518-519 Block Address Area-1 ; 520-522 ECC Area-2 ; 523-524 Block Address Area-2 ; 525-527 ECC Area-1 ; ; -------------------------------------------------------------------------------------; Block Address Area Information ; [Block Address Configuration] ;D7 D6 D5 D4 D3 D2 D1 D0 1,2 MB SM 4,8,16 MB and above SM ; ;0 0 0 1 0 BA9 BA8 BA7 262 bytes(even) 518, 523 bytes ; 259 bytes(odd) ; ;BA6 BA5 BA4 BA3 BA2 BA1 BA0 P 263 bytes(even) 519, 524 bytes ; 260 bytes(odd) ; ;BA9 ~ BA0 : Block Address (values=0 through n,where n = maximum logical block count - 1) ;P : Even Parity bit ; ; -------------------------------------------------------------------------------------; Block_a Parameter Definition ; - Used Valid Block is block_a[ Physical block number] = bl_addr(Block Address value) ; - Invalid Block is block_a[Physical block number] = 0xffee(Invalid Mark is defined as ‘ 0xffee’ ) ; - CIS Block is block_a[Physical block number] = 0 (Actual Block Addess Value is ‘ 0x0000’ .) ; - Unused Valid Block[Physical block number] = 0xffff ; ; -------------------------------------------------------------------------------------; ; Support Devices ; K9S2808V0M-SSB0 16M x 8 bit SmartMedia Card - tested ; [32768 rows(pages), 528 columns] ; ; ; Command Latch Enable(CLE) ; The CLE input controls the path activation for commands sent to the ; command register. When active high, commands are latched into the ; command register through the I/O ports on the rising edge of the ; WE signal. ; ; Address Latch Enable(ALE) ; The ALE input controls the activating path for address to the internal ; address registers. Addresses are latched on the rising edge of WE with ; ALE high. ; ; Chip Enable(CE) ; The CE input is the device selection control. When CE goes high during ; a read operation the device is returned to standby mode. ; However, when the device is in the busy state during program or erase, ; CE high is ignored, and does not return the device to standby mode. ; ; Write Enable(WE) ; The WE input controls writes to the I/O port. Commands, address and data ; are latched on the rising edge of the WE pulse. ; ; Read Enable(RE) ; The RE input is the serial data-out control, and when active drives the ; data onto the I/O bus. Data is valid tREA after the falling edge of RE ; which also increments the internal column address counter by one. ; ; I/O Port : I/O 0 ~ I/O 7 ; The I/O pins are used to input command, address and data, and to output ; data during read operations. The I/O pins float to high-z when the chip ; is deselected or when the outputs are disabled. ; ; Write Protect(WP) ; The WP pin provides inadvertent write/erase protection during power ; transitions. The internal high voltage generator is reset when the ; WP pin is active low. ; ; Ready/Busy(R/B) ; The R/B output indicates the status of the device operation. When low, ; it indicates that a program, erase or random read operation is ; in process and returns to high state upon completion. It is an open ; drain output and does not float to high-z condition when the chip ; is deselected or when outputs are disabled. ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2002.07.19 VFX Creation ; 1.10 2003.02.02 VFX Redesign all functions ; 1.11 2003.05.05 VFX Remove IO pin and change to XMEM mode ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ;
; *************************************************************************** ;* Const Def ;SmartMedia Commands .EQU SM_ReadLowHalf 0x00h
=
;Page read A .EQU .EQU
0x50h
SM_ReadHiHalf SM_ReadEnd
= 0x01h =
SM_ReadID
=
;Page read C .EQU
0x90h
;Read ID .EQU SM_ReadUnique ;Read Unique 128 bit .EQU SM_Reset ;Device reset .EQU SM_PageProgram ;Ready to write, Serial Data Input .EQU SM_PageProgramTrue ;Start to write page, auto program (Toshiba) .EQU SM_PageProgramDumy ; .EQU SM_PageProgramMultiBlk ; .EQU SM_BlockErase ;Erase block (block#) .EQU SM_BlockErase2nd ;Erase block (start) .EQU SM_ReadStatus ;Read status .EQU SM_ReadMultiPlaneStatus ;
0x91h 0xFFh 0x80h 0x10h 0x11h 0x15h 0x60h 0xD0h 0x70h 0x71h
= = = = = = = = = =
;SMIL Commands .equ
SMIL_Standby
= 0x00h ;Standby
.equ
SMIL_RM_ReadData
= 0x14h ;Data
.equ
SMIL_RM_WriteCmd
= 0x15h ;Command
.equ
SMIL_RM_WriteAddr
= 0x16h ;Address
.equ
SMIL_RM_WriteData
= 0x14h ;Data
.equ
SMIL_WM_ReadData
= 0x94h ;Data
.equ
SMIL_WM_WriteCmd
= 0x95h ;Command
.equ
SMIL_WM_WriteAddr
= 0x96h ;Address
.equ
SMIL_WM_WriteData
= 0x94h ;Data
.equ .equ .equ
SMIL_ResetECCLogic SMIL_RWwithECC SMIL_RWwithoutECC
= 0b01100000 = 0b00100000 = 0b00000000
Mode
Read
( SmartMedia Data Read )
Write ( SmartMedia Data Read ) Write ( SmartMedia Data Read ) Write
Read
( SmartMedia Data Read )
( SmartMedia Data Write)
Write ( SmartMedia Data Write) Write ( SmartMedia Data Write) Write
( SmartMedia Data Write)
;SM Manufacturer ID .equ MakerSamsung = 0xEC .equ MakerToshiba = 0x98
;SM IDs, .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
only 3.3V or 2.7-3.6V devices Sign05 = 0xA4 ;0.5 Mb Sign1 = 0x6E ;1 Mb Sign2 = 0xEA ;2 Mb Samsung Sign2a = 0x64 ;2 Mb Toshiba Sign4 = 0xE3 ;4 MB Samsung Sign4a = 0xE5 ;4 MB Toshiba Sign8 = 0xE6 ;8 Mb Sign16 = 0x73 ;16 MB Sign32 = 0x75 ;32 Mb Sign64 = 0x76 ;64 Mb Sign128 = 0x79 ;128 Mb
.EQU .EQU .equ
SM_UniqueIDcode = 0xA5 SM_MultiplaneSupportCode = 0xC0 ExtendedID = 0x21
.equ SM_Protected = ;bit = 1, media write protect .equ SM_Busy = ;bit = 1, media ready .equ SM_Fail = ;bit = 1, Fail
7 6 0
;SmFlags .EQU .EQU .EQU ;Device < 16 MB .EQU ;Device Unknown
5 4
of
SM_UniqueID = 7 SM_MultiplaneSupport = 6 SM_DeviceTooSmall = SM_DeviceUnkown
=
.equ
W500us
= SYSCLK/8000
;Delay 500us units
.equ
W10us
= SYSCLK/160
;Delay 10us
SYSCLK
; ************************************************************************** ;* Hardware Def. ; ; External Controller Address def. by main.asm ;.equ ADR_SMDATA = 0x3F00 ;SmartMedia Data Register ;.equ
ADR_SMMODE = 0x3F01
;SmartMedia
;.equ
ADR_SMSTAT = 0x3F01
;SmartMedia
Mode Register Mode Register
; *************************************************************************** ;**** VARIABLES .DSEG ;-Memory Card-----------Egymas utan kell aljanak -Struct ;dont remove or insert any line here!! SmManufacturerID: .byte 1 ; SM Manufacturer code SmDeviceCode:
.byte 1
; SM Device
Code SmFlags:
.byte 1
; 7 bit = 1
UniqueID Supported ; 6 bit = 1 MultiPlane Supported SmPages:
.byte 3
; Number of pages
(physical sectors) SmPPB:
.byte 1
; Pages per
block SmBlocks:
.byte 2
; Blocks per Devices
;end struct SMDataBuffer:
.byte 512
;I/O Data
buffer
; *************************************************************************** .ESEG
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG Init_SMedia: ldi sts
R16, SMIL_Standby ADR_SMMODE,R16
;SmartMedia
clr sts
R16 SmManufacturerID,R16
;No valid
sts sts
SmDeviceCode,R16 SmFlags,R16
rcall
SM_ResetDevice
;Reset
rcall
SM_GetType
;Get
lds andi
R18,SmFlags R18,(1<
Controller is StandBy
Card in socket
SmartMedia PrintSMType: SmartMedia Type
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that http://avr-asm.tripod.com/vfxsmil.html (1 of 2)1/20/2009 8:50:36 PM
16 BIT MATH (AVR 202)
are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/vfxsmil.html (2 of 2)1/20/2009 8:50:36 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
VFX MEMORY MANAGER HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305
; *************************************************************************** ; ; File Name :'memory.asm" ; Title :Memory Manager for VFX's DataLog ; Date :2003.08.03. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; MCB ; 0. byte - Type/Flag ; 7. =1 last block ; 6. =1 first block ; 5. =1 used block ; 4. = nc ; 3:0 = process number Hi part ; 1. byte - process number low part ; 2. word - low part of length ; 4. byte - hi part of length ; 5. word - low part offset of prev. MCB ; 7. byte - hi part offset of prev. MCB ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.08.03 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; ***************************************************************************
UART 128 UART BUFF USB 232 AVR ISP ISP 2313
.equ .equ .equ .equ .equ .equ .equ
MCB_Type MCB_Proc MCB_LenL MCB_LenH MCB_PrevL MCB_PrevH MCB_Size
= = = = = = =
0 1 2 4 5 7 8
.equ .equ .equ .equ .equ
MCBLast = 7 MCBFirst = 6 MCBUsed = 5 ProcMask = 0x0F NonProcMask = 0xF0
.equ .equ .equ .equ
MMAP0 MMAP1 MMAP2 MMAP3
.equ .equ
MaxMemoryLW = 0x0000 MaxMemoryHW = 0x0002
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
= = = =
0x0000 0x4000 0x8000 0xC000
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
;max memory
0x00020000 == 128kb ; ; ************************************************************************** ;* Hardware Def. ; ; *************************************************************************** ;**** VARIABLES .DSEG
KBD 240 MUX 242 KBD PS2 KBD PC/128
LargeMCB:
.byte
3
;Egybefuggo nagy blokkok
SmallMCB:
.byte
3
;kicsi blokkok <4kb
>4kb kezdopozicioja
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; *************************************************************************** .ESEG
CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG
PWM 10K
ExtSRAMTest:
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
ldi
R20,SRAMBASE
;External
ldi
R18,8
;8x16k page
ldi
R21,0x5A sts ADR_EXHH,R20
;test byte ;
ldi ldi
ZL,0 ZH,192
;Z point to
ldi ldi
XL,low(16384) XH,high(16384)
;Count of
sbiw brne inc dec brne
st XL,1 srt1 R20 R18 SRT0
SRAM Base Address = 128k SRT0: Upper memory to SRAM Banks
AVR BOOK upper memory
test byte srt1:
ldi ldi ldi
Z+,R21 ;fill bank
ldi ldi
R20,SRAMBASE R18,8 R21,0x5A sts ADR_EXHH,R20 ZL,0 ZH,192
ldi ldi
XL,low(16384) XH,high(16384)
cp brne sbiw brne inc dec brne
ld R3,Z+ R21,R3 SRAMERR XL,1 srt3 R20 R18 srt2
SRT2:
;test byte
;Z point to
upper memory ;Count of
test byte srt3:
;check bank
clc ret SRAMERR:
sec ret
;****************************************************** ; Convert Phisycal address to Logical Address ; In: R18:R17:R16 Phisycal address ; Out R18 - page, ; R17:R16 - offset address (must add MMAP1,2,3) ; MmTranslatePhysicalAddress: push R17 rol R17 rol R18 rol R17 rol R18 pop R17 andi R17,0b00111111 ret
;****************************************************** ; Set Page at R18:R16 ; In: R18:R17:R16 Phisycal address ; Out R18 - page+1, ; R17:R16 - offset address on MMAP2 ; Z - mapped address on MMAP2 ; MmSetPage: rcall MmTranslatePhysicalAddress MmSetPageMap: ori R17,high(MMAP2) sts ADR_EXHL,R18 inc R18 sts ADR_EXHH,R18 ;2 page -> no page border fault movw
ZL,R16
;Z - offset
at first page RET
;****************************************************** ; Initialize Memory & setup MCBs ; Mem_Init: ldi R16,S1D_DISPLAY_HEIGHT ldi R17,S1D_DISPLAY_SCANLINE_BYTES mul R16,R17 inc R1 ;skip Video RAM + 256 byte clr
R2
sts sts sts movw mov rcall
LargeMCB+0,R0 LargeMCB+1,R1 LargeMCB+2,R2 R16,R0 R18,R2 MmSetPage
ldi
R16,(1<= old delta
movw mov movw mov rjmp
R12,R16 R14,R18 R8,R0 R10,R2 MMVanMeg
MMTeljesenJo: movw mov clr clr clr rjmp
;First MCB
;delta ;best pointer
R8,R0 R10,R2 R12 R13 R14 MMLastInChain
;pointer
;delta=0
MMVanMeg: ldd sbrc rjmp
R16,Z+MCB_Type R16,MCBLast MMLastInChain
ldd ldd ldd add adc adc add adc adc rjmp
R18,Z+MCB_LenH R17,Z+MCB_LenL+1 R16,Z+MCB_LenL+0 R16,R21 R17,R15 R18,R15 R0,R16 R1,R17 R2,R18 MmNextMCB01
MMLastInChain: mov or or brne rjmp mmMoreM00:
R0,R8 R0,R9 R0,R10 mmMoreM00 mmNoMoreMemory ;Memory block
Allocation/sharing ;Alloc = delta < 40 byte (32+8) ;share = delta => 40 byte ldi clr cp cpc cpc brsh
R16,40 R17 R12,R16 R13,R17 R14,R17 MMShare
movw mov movw mov rcall
R0,R8 R2,R10 R16,R8 R18,R10 MmSetPage
ldd
R16,Z+MCB_Type
ori
R16,(1< Proc
ldd cbr
R16,Z+MCB_Type R16,(1<
mmAllocAll:
;set
MCBUsed & Process
mmMakeFree:
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ http://avr-asm.tripod.com/vfxmem.html (1 of 2)1/20/2009 8:51:14 PM
16 BIT MATH (AVR 202)
USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/vfxmem.html (2 of 2)1/20/2009 8:51:14 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BUBBLE SORT (AVR 220) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
DIV 24 24 DIV 3216
Title: Version: Last updated: Target:
Bubble Sort Algorithm 1.0 97.07.04 AT90Sxx1x (Devices with SRAM)
Support E-mail:
[email protected]
DESCRIPTION This Application note shows how to sort a block of
data in SRAM using ;* the code efficient Bubble Sort Algorithm. The App. note contains a test
MATH YX DIV16 XX
A V R 2 2 0
************************
ASM MATH
MATH 202
N O T E
;* program which copies a 60-byte block of data from program memory to ;* SRAM and sorts the data. ;* ; ***************************************************************************
FLOAT 128 .include "8515def.inc"
SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII
.equ .equ
SIZE =60 TABLE_L =$60
;data block size ;Low SRAM address
.equ
TABLE_H =$00
;High SRAM address
of first data element of first data element
HX2ASC
rjmp
RESET
;Reset Handle
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
; *************************************************************************** ;* ;* "bubble" ;* ;* This subroutine bubble sorts the number of bytes found in "cnt1" + 1 ;* with the last element in SRAM at location "last". ;* This implementation sorts the data with the highest element at the ;* lowest SRAM address. The sort order can be reversed by changing the ;* "brlo" statement to "brsh". Signed sort can be obtained by using "brlt" ;* or "brge" ;* ;* Number of words :13 + return ;* Number of cycles :6*(SIZE-1)+10*(SIZE(SIZE-1)) +return (Min) ;* 6*(SIZE-1)+13*(SIZE(SIZE-1)) +return (Max) ;* Low registers used :3 (A,B,cnt2) ;* High registers used :3 (cnt1,endL,endH) ;* Pointers used :Z ;* ; ***************************************************************************
ISP 1200
;***** Subroutine Register Variables
AVR SPI I2C 300
;first value to be
.def
B
=r14
;second value to be
.def .def .def
cnt2 cnt1 endL
=r15 =r16 =r17
;inner loop counter ;outer loop counter ;end of data array
.def
endH
=r18
;end of data array
low address
DALLAS-1W DALLAS CRC
=r13
compared
I2C/TWI 128 I2C/TWI AT8
A
compared
I2C 302 I2C TWI26
.def
high address
ETHNET 8019
;***** Code
TEA bubble: mov mov mov i_loop:
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
ZL,endL ZH,endH cnt2,cnt1 ld A,Z
;init Z pointer ;counter2 <- counter1 ;get first byte, A
B,-Z
;decrement Z and get second
A,B L1 Z,A Z+1,B cnt2 i_loop cnt1 bubble
;compare A with B ;if A not lower ; store swapped
(n) ld byte, B (n-1)
IRD 410
cp brlo st std L1: dec brne dec brne ret
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
;end inner loop ;end outer loop
KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
; *************************************************************************** ;* ;* Test Program ;* ;* This program copies 60 bytes of data from Program memory to SRAM. It ;* then calls "bubble" to get the data sorted. ;* ; ***************************************************************************
DTMF 314
RESET:
PWM 6CH
;***** Main program Register variables
PWM 10K .def
ENCODE STH-11
temp
=r16
;***** Code
ATMEL CORP ldi out ldi out
AVR BUTTERFLY AVR BOOK
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer
;***** Memory fill clr ldi
ZH ZL,tableend*2+1 ;Z-pointer <- ROM table end
ldi ldi
YL,low(256*TABLE_H+TABLE_L+SIZE) YH,high(256*TABLE_H+TABLE_L+SIZE) ;Y pointer <- SRAM table
+ 1
end + 1 loop: st
lpm -Y,r0
;get ROM constant ;store in SRAM and
ZL,1 YL,TABLE_L loop YH,TABLE_H loop
;decrement Z-pointer ;if not done ; loop more
decrement Y-pointer sbiw cpi brne cpi brne
;***** Sort data sort: ldi ldi rcall
ldi endL,low(TABLE_H*256+TABLE_L+SIZE-1) endH,high(TABLE_H*256+TABLE_L+SIZE-1) ;Z <- end of array address cnt1,SIZE-1 ;cnt1 <- size of array - 1 bubble
forever:rjmp
forever
;***** 60 ROM Constants table: .db 120,196 .db 78,216 .db 78,100 .db 43,39 .db 241,43 .db 62,172 .db 109,69 .db 48,184 .db 215,231 .db 63,133 .db 216,8 .db 121,126 .db 188,98 .db 168,205 .db 157,172 .db 108,233 .db 80,255 .db 252,102 .db 198,0 .db 171,239 .db 107,114 .db 172,170 .db 17,45 .db 42,55 .db 34,174 .db 229,250 .db 12,179 .db 187,243 .db 44,231 tableend: .db 76,48
Programming the AVR Microcontrollers in Machine Language
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Search
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr220.html (1 of 2)1/20/2009 8:51:49 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr220.html (2 of 2)1/20/2009 8:51:49 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
CIRCULAR REDUNDANCY CHECK (AVR 236) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3
MATH 202 com for the latest and updated
;* version of the software. ;* ;* DESCRIPTION ;* This application note describes how to perform CRC
MATH YX DIV16 XX computation
;* of code memory contents using a simple algoritm. ;* To generate CRC checksum load the register "status"
DIV 3216 FLOAT 128
with 00 and call the routine ;* "crc_gen". The resulting checksum is placed in the
SQRT16 MATH 202
registers ;* byte_2(low byte) and byte_3(high byte). ;* ;* To check the CRC checksum load the register "status"
MATH 202 DEC ASCII
with FF and call the routine
INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108
CRC check of program memory 1.3 11.11.2004 AT90Sxxx, ATtinyxxx, ATmegaxxx (All AVR Devices with LPM
;* ;* Support E-mail: [email protected] ;* ;* NOTE: Always check out Atmels web site, www.atmel.
MATH 201
DIV 24 24
Title: Version: Last updated: Target:
instr, not AT90S1200)
MATH 200b
MATH 32X
A V R 236
************************
ASM MATH
MATH 200
N O T E
;* "crc_gen". The resulting checksum is placed in the registers ;* byte_2(low byte) and byte_3(high byte). If the checksum is 00 the program code is ;* correct, if the checksum is non-zero an error has been introduced in the program code ; **************************************************************************
EPROM 100 .include "8515def.inc"
SER EPROM DFLASH AT45
;***** Constants
FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128
.equ Last program memory address(byte address) .equ divisor value
LAST_PROG_ADDR CR
= 0x1FFF
= 0x8005
; ; CRC
; ************************************************************************** ;* ;* PROGRAM START - EXECUTION STARTS HERE ;* ; **************************************************************************
UART BUFF USB 232
;
AVR ISP
.org $0000 rjmp RESET
ISP 2313
.cseg
;Reset handle
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
; *************************************************************************** ;* ;* "crc_gen" - Generation and checking of CRC checksum ;* ;* This subroutine generates the checksum for the program code. ;* 32 bits are loaded into 4 register, the upper 16 bits are XORed ;* with the divisor value each time a 1 is shifted into the carry flag ;* from the MSB. ;* ;* If the status byte is 0x00,the routine will generate new checksum: ;* After the computing the code 16 zeros are ;* appended to the code and the checksum is calculated. ;* ;* If the status byte is different from 0X00, the routine will check if the current checksum is valid. ;* After the computing the code the original checksum are ;* appended to the code and calculated. The result is zero if no errors occurs ;* The result is placed in registers byte_2 and byte_3 ;* ;* Number of words :44 + return ;* Number of cycles :program memory size(word) * 175 (depending on memory contens) ;* Low registers used :6 (byte_0,byte_1,byte_2, byte_3) ;* High registers used :7 (sizel,sizeh,crdivl,crdivh, count,status,zl,zh) ;* ; ***************************************************************************
BOOT DR8 ;***** Subroutine Register Variables
ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
byte_0
= r0
; Lower byte of
.def
byte_1
= r1
; Upper byte of
.def
byte_2
= r2
; Lower byte of
.def
byte_3
= r3
; Upper byte of
.def
crc
= r4
; CRC
.def
crch
= r5
; CRC
.def .def .def .def .def count .def
sizel sizeh crdivl crdivh = r21 status
crc_gen: ldi
sizel,low(LAST_PROG_ADDR)
lower word lower word upper word
DTMF 314 PWM 6CH
upper word
PWM 10K
checksum low byte
ENCODE STH-11
.def
checksum high byte
ATMEL CORP AVR BUTTERFLY AVR BOOK
= = = = ; =
r17 ; Program code size register r18 r19 ; CRC divisor register r20 Bit counter r22 ; Status byte: generate(0)
or check(1)
;Load last
program memory address ldi clr clr ldi ldi lpm
sizeh,high(LAST_PROG_ADDR) zl ;Clear Z pointer zh crdivh,high(CR);Load divisor value crdivl,low(CR) ;Load first memory
mov adiw lpm
byte_3,byte_0 zl,0x01
mov
byte_2,byte_0
location ;Move to highest byte ;Increment Z pointer ;Load second memory
location
next_byte: cp cpc
zl,sizel zh,sizeh
;Loop starts here ;Check for end of
brge adiw lpm mov adiw lpm
end zl,0x01
;Jump if end of code
rcall rjmp
rot_word next_byte
code
;Load high byte ;Move to upper byte ;Increment Z pointer ;Load program
byte_1,byte_0 zl,0x01
memory location ;Call the rotate routine
end: ;ret
;uncomment this line if checksum is stored
ldi cpi brne clr clr
count,0x11 status,0x00 check byte_0 byte_1
in last flash memory address.
;Append 16 bits(0x0000) to ;the end of the code for
CRC generation rjmp check: mov
gen byte_0,crc
;Append the
original checksum to mov
byte_1,crch
;the end of the code for
rot_word crc,byte_2 crch,byte_3
;Call the rotate routine
CRC checking gen: rcall mov mov ret rot_word: ldi rot_loop: dec breq
;Return to main prog
count,0x11 count stop
;Decrement bit counter ;Break if bit
lsl rol
byte_0 byte_1
;Shift zero into lowest bit ;Shift in carry from
rol rol brcc
byte_2 byte_3 rot_loop
;Preceede shift
counter = 0
previous byte
;Loop if MSB =
0 eor eor rjmp stop: ret
byte_2,crdivl byte_3,crdivh rot_loop
;XOR high word if MSB = 1
; *************************************************************************** ;* ;* EERead_seq ;* ;* This routine reads the ;* EEPROM into the global register variable "temp". ;* ;* Number of words :4+ return ;* Number of cycles :8 + return ;* High Registers used :4 (temp,eeadr,eeadrh, eedata) ;* ; *************************************************************************** .def .def .def .def
temp eeadr eeadrh eedata
= r16 = r23 = r24 = r25
;***** Code eeread: out out sbi
EEARH,eeadrh EEARL,eeadr EECR,EERE
;output address high byte ;output address low byte ;set EEPROM Read
eedata,EEDR
;get data
strobe in ret
; *************************************************************************** ;* ;* EEWrite ;* ;* This subroutine waits until the EEPROM is ready to be programmed, then ;* programs the EEPROM with register variable "EEdwr" at address "EEawr" ;* ;* Number of words :7 + return ;* Number of cycles :13 + return (if EEPROM is ready) ;* Low Registers used :None ;* High Registers used: ;4 (temp,eeadr,eeadr,eedata) ;* ; *************************************************************************** .def .def .def .def
temp eeadr eeadrh eedata
= r16
eewrite: sbic rjmp out out out sbi sbi
EECR,EEWE EEWrite EEARH,eeadrh EEARL,eeadr EEDR,eedata EECR,EEMWE EECR,EEWE
= r23 = r24 = r25
;If EEWE not clear ; Wait more ;Output address high byte ;Output address low byte ;Output data ;Set EEPROM Write
strobe ret ; ************************************************************************ ;* ;* Start Of Main Program ;* .cseg .def crc = r4 ;Low byte of checksum to be returned .def crch = r5 ;High byte of checksum to be returned .def temp = r16 .def status = r22 ;Status byte: generate(0) or check(1) .def eeadr = r23 .def eeadrh = r24 .def eedata = r25 RESET: ldi
r16,high(RAMEND)
;Initialize stack
out
SPH,r16
;High byte only
ldi
r16,low(RAMEND) ;RAM is bigger than 256
out
SPL,r16
ldi out out clr
temp,0xff DDRB,temp PORTB,temp status
rcall
crc_gen
ldi
eeadr,0x01
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
mov
eedata,crc
;Set CRC low byte in EEPROM
rcall
eewrite
;Write EEPROM
ldi
eeadr,0x02
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
mov
eedata,crch
;Set CRC high byte in
rcall
eewrite
;Write EEPROM
out
PORTB,crc
;Output CRC low value to
EECR,EEWE mainloop
;If EEWE not clear ; Wait more
pointer required if Bytes
;Set PORTB as output ;Write 0xFF to PORTB ;Clear status register,
prepare for CRC generation
EEPROM write EEPROM write data
EEPROM write EEPROM write EEPROM data
PORTB mainloop: sbic rjmp
;********** Insert program code here ************* ldi
eeadr,0x01
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
rcall mov
eeread crc,eedata
;Read EEPROM ;Read CRC low byte from
ldi
eeadr,0x02
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
rcall mov
eeread crch,eedata
;Read EEPROM ;Read CRC low byte from
ser
status
;Set status register,
rcall
crc_gen
EEPROM read EEPROM read
EEPROM
EEPROM read EEPROM read
EEPROM
prepare for CRC checking
loop: out
PORTB,crc
;Output CRC low value to
PORTB rjmp loop .exit
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the http://avr-asm.tripod.com/arv236.html (1 of 2)1/20/2009 8:52:28 PM
16 BIT MATH (AVR 202)
same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/arv236.html (2 of 2)1/20/2009 8:52:28 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
XMODEM RECEIVE ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220
; *************************************************************************** ; ; File Name :'xmodem.asm" ; Title :XMODEM only receive ; Date :2002.07.03. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2002.07.03 VFX Creation ; ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* Kvarc: f=7.3728 MHz (T=135.63368 ns) ;* ; *************************************************************************** ; ; ; ; *************************************************************************** ;* Const Def
CRC 236 .EQU
Xmodem_Sync
=
0
;
.EQU
Xmodem_SOH
=
1
;SOH byte-
.EQU
Xmodem_Fill
=
2
;SOH byte
Xmodem_Err
=
3
;megszakadt
SyncTiming
=
300
;ket
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
szinkronizalasi fazis ra var megjott, block init megvolt .EQU az atvitel, NAK kuldese 3 masodpercenkent
AVR ISP ISP 2313
.EQU karakter elkuldese kozott
ISP 1200 AVR SPI
;eltelt ido szinc. uzemmodban 3sec @100Hz
I2C 300 I2C 302 I2C TWI26 I2C/TWI 128
; ************************************************************************** ;* Hardware Def. ;
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
; *************************************************************************** ;**** VARIABLES .DSEG
TEA ADC 128 ADC 10B
CRC:
.BYTE
XmodemFlag: .BYTE
1
Xm_BlkCounter:
.BYTE
XmodemPTR:
1
;Xmodem Buffer
XmodemBuf: .BYTE FileLength: .byte LastPocketSize:
133 4 .byte
;XMODEM RxBuffer ;File hossz 32 bites ;utolso
XmodemMode: .byte
1
;Mode0 - Nul modem
.byte
;Mode1 - DSP Boot ;Xmodem
BOOT MG8 BOOT DR8 ALM CLK
1
letolti de nem csinal semmit
KBD PC/128 PS2 EMU
.BYTE
pocket merete byte-ban [0...128]
MUX 242 KBD PS2
;Xmodem
pointer
LCD44 2313 KBD 240
1
Block Counter [00-FF]
LCD HD44 LCD 2313
;Xmodem Flag ;[2:0] = 000
sending 'c' Phase 1: syncronize
THERM 232 IRD 410
; CRC for
XMODEM
ADC 400 ADC 401
2
Xm_ErrorCNT:
1
Time to Abort counter ; *************************************************************************** .ESEG
CLOCK 8564 90 DAYS DELAYS
; *************************************************************************** .CSEG
CALL ID DTMF 314 PWM 6CH PWM 10K
; *************************************************************************** ;** Init Xmodem File Receive ;**
ENCODE Init_Xmodem:
STH-11
ldi R16,128 LastPocketSize,R16 R0 FileLength+0,R0 FileLength+1,R0 FileLength+2,R0 FileLength+3,R0 Xm_ErrorCNT,R0 XmodemFlag,R0 Xm_BlkCounter,R0 clr R0 CRC+0,R0 CRC+1,R0 XmodemPTR,R0 SCNT2+0,R0 SCNT2+1,R0
sts clr sts sts sts sts sts sts sts Init_XmNextBl: sts sts sts STS STS ret
ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;** Calc & Update XMODEM CRC ;* ;* In: R0 - data byte
UpdateCRC:
lds mov swap mov
R17,CRC+1 R15,R17 R17 R16,R17
eor andi andi eor
R17,R15 R17,0xF0 R16,0x0F R15,R16
mov lsl rol
R14,R17 R14 R16
eor eor
R15, R14 R17,R16
lds eor eor
R14,CRC+0 R15,R0 R17,R14
sts sts ret
CRC+0,R15 CRC+1,R17
; *************************************************************************** ;** XMODEM Receive File & Block ;* ;* Xmodem_Rec: lds R16,XmodemFlag cpi R16,Xmodem_Sync breq Xm_Sync cpi brne rjmp
R16,Xmodem_Fill Xmodem_Rec1 Xm_Fill
Xmodem_Rec1:
Xm_Sync:
breq
cpi Xm_SOH
R16,Xmodem_SOH
cpi breq
R16,Xmodem_Err Xm_Sync
rjmp
Xmodem_Cancel
call brcs
Rs232GetByte Xm_valamijott ;itt meg
mindig nem jott semmi lds lds or
R16,SCNT2+0 R17,SCNT2+1 R16,R17
breq ret
Xm_Sync1
ldi
R16,NAK
lds cpi breq
R17,XmodemFlag R17,Xmodem_Err Xm_Sync2
;Timer
lejart?
Xm_Sync1: hiba van
;akkor, ha
NAK megy 3 masodpercenkent
;mivel meg mindig nem jott semmi kuldunk egy ;CRC karaktert 3 masodpercenkent lds
R16,Xm_ErrorCNT
inc sts cpi brne rjmp
R16 Xm_ErrorCNT,R16 R16,20 Xm_Sync25 Xm_Abort
Xm_Sync25:
ldi
R16,'C'
Xm_Sync2:
call ldi
SendChrW R16,Low(SyncTiming)
sts ldi sts ret
SCNT2+0,R16 R17,High(SyncTiming) SCNT2+1,R17
;ha 20 'C'
ideig nem jon semmi akkor abort!!!
;Timer=3sec
@100Hz
Xm_SOH:
call Rs232GetByte Xm_valamijott
brcs ret Xm_valamijott: cpi breq cpi breq cpi breq
mov R16,R0 R16,CAN Xmodem_Cancel R16,SOH Xmodem_StartOfH R16,EOT Xmodem_EndOfT rjmp Xmodem_Rec
Xm_ByteStr: .db
" Bytes received ",CR,0 ;End of
Trans == Canacel Xmodem_EndOfT: ldi call
R16,ACK SendChrW
;Pozitiv
ldi call
R16,CR SendChrW
;soremeles
lds lds lds lds call
R16,FileLength+0 R17,FileLength+1 R18,FileLength+2 R19,FileLength+3 ULTOA
;ACC1 LSByte
ldi
XL,low(ASCIIBuf)
;Ascii
ldi
XH,high(ASCIIBuf)
nyugta Xm_Abort:
;Print
FileLength
Buffer Ptr ;ldi R22,12 call
PrintASCII
;rcall
ldi ldi call
R16,Low(Xm_ByteStr) R17,High(Xm_ByteStr) SendStrW
DumpASCII
Xmodem_Cancel:
lds
R16,Term_Stat
;
End of Xmodem receiving cbr
R16,Term_Rec_Xmodem
sts
Term_Stat,R16
lds cpi brne
R17,XmodemMode R17,1 Xm_CancelEnd
;Normal
Terminal Mode
;itt lesz vege a FALSH update-nak Xm_CancelEnd: sts
clr R17 Updating,R17
;Ezel
sts
XmodemMode,R17
;barmi volt
jmp
CMDOk
jelzzuk keszen vagyunk is, most null modem
Xmodem_StartOfH: ldi sts rcall ldi
R16,Xmodem_Fill XmodemFlag,R16 Init_XmNextBl ZL,Low(SyncTiming)
;Timer=3sec
sts
SCNT2+0,ZL
;he nem jon
ldi sts rjmp
ZL,High(SyncTiming) SCNT2+1,ZL Xmodem_Rec
call
Rs232GetByte
;itt
brcs
Xm_data
; blk
@100Hz ujjab byte, akkor baj van!!
Xm_Fill: beolvasunk 132 byte-ot counter,255-blk counter [2 byte]
; adatblok [128 byte] ; CRC [2 byte] ;total 132 byte lds
R16,SCNT2+0
;he nem jon
lds or brne
R17,SCNT2+1 R16,R17 Xm_vanido
ldi sts
R16,Xmodem_Err XmodemFlag,R16
;Time Out,
ldi
ZL,Low(SyncTiming)
;Timer=3sec
sts
SCNT2+0,ZL
;he nem jon
ldi sts
ZL,High(SyncTiming) SCNT2+1,ZL
ldi ldi clr lds add adc
ZL,Low(XmodemBuf) ZH,High(XmodemBuf) R1 R16,XmodemPTR ZL,R16 ZH,R1
;ZL:ZH ->
st
Z,R0
;Char
inc sts cpi
R16 XmodemPTR,R16 R16,3
;3
ujjab byte, akkor baj van!!
Ismetles kell Xm_vanido:
ret
Xm_data: @100Hz ujjab byte, akkor baj van!!
Xmodem Actualis Pos. eltarolasa
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations http://avr-asm.tripod.com/xmodemrec.html (1 of 2)1/20/2009 8:53:11 PM
16 BIT MATH (AVR 202)
R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/xmodemrec.html (2 of 2)1/20/2009 8:53:11 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
HALF DUPLEX SOFTWARE UART (AVR 304) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* Title: ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
MATH 202
AVG8 222 FFT7
;* ;* The constants N and R determine the data rate. R selects clock frequency ;* as described in the T/C Prescaler in the AVR databook. If the T/C pre;* scaling factor is denoted C, the following expression yields the data rate: ;* ;* XTAL ;* BAUD = -----min. N*C = 17 ;* N*C max. N = 170 ;* ;* Absolute minimum value for N*C is 17 (which causes the interrupt flag to be
FLASH CARD
;* set again before the interrupt is finished).
VFX SMIL
Absolute maximum is 170.
VFX MEM
receive bits correctly.)
;* (Caused by the 1.5bit-lenght that is necessary to ;* ;* The UART uses PD2 as receive pin because it utilizes
SORT 220 the external interrupt.
;* The transmit-pin is PD4 in this example, but it can
XMODEM REC be any other pins.
;* ;* Since the UART is half duplex, it can either send or
UART 305
UART BUFF USB 232
recieve data. It can't ;* do both simoutaneausly. When idle it will automatically recieve incoming ;* data, but if it is transmitting data while incoming data arrives, it will
AVR ISP
;* ignore it. Also, if u_transmit is called without
ISP 2313
waiting for the 'READY' bit
ISP 1200
will abort any pending
;* in the 'u_status' register to become cleared, it ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
This application note describes how to make a half
resources.
SER EPROM
UART 128
DESCRIPTION
;* only, a half duplex UART will limit the usage of MCU
EPROM 100
UART 304
Code Size :72 words Low Register Usage :2 High Register Usage :5 Interrupt Usage :External Interrupt, Timer/Counter0 overflow interrupt
direction at a time
LPM 108
CRC 236
[email protected]
;* As a lot of control applications communicate in one
COPY 102
DFLASH AT45
Support E-mail:
External Interrupt.
INT ASCII HX2ASC
1.0 97.07.18 AT90Sxxxx (All AVR Devices)
;* on any AVR device with the 8-bit Timer/Counter0 and
MATH 202 DEC ASCII
Version: Last updated: Target:
duplex software UART
FLOAT 128 SQRT16
Half Duplex Interrupt Driven
Software UART
TUTORIAL #2
DIV 3216
A V R 3 0 4
************************
ASM MATH TUTORIAL #1
N O T E
reception or transmittal.
*** Initialization 1. Call uart_init 2. Enable global interrupts (with 'sei') *** Receive 1. Wait until RDR in 'u_status' becomes set 2. Read 'u_buffer' *** Transmit (0. Initialize the UART by executing uart_init and
sei) ;* 1. Wait until READY in 'u_status' becomes clear ;* 2. Set 'u_buffer' ;* 3. Call 'u_transmit' ;* ; **************************************************************************
LCD HD44 .include "1200def.inc"
LCD 2313
;***** BAUD-rate settings
LCD44 2313 KBD 240 MUX 242
;BAUD-RATES @1MHz XTAL AND R=1 ;.equ ;.equ .equ .equ .equ
KBD PS2 KBD PC/128 PS2 EMU
N=104 N=52 N=26 C=1 R=1
; 9600 ;19200 ;38400 ;Divisor ;R=1 when C=1
BOOT MG8 BOOT DR8 ;***** UART Global Registers
ALM CLK CLOCK 8564 90 DAYS
u_buffer u_sr
=r14 =r15
;Serial buffer ;Status-register
.def .def .def .def
u_tmp u_bit_cnt u_status u_reload
=r16 =r17 =r18 =r19
;Scratchregister ;Bit counter ;Status buffer ;Reload-register
.def
u_transmit
=r20
;Data to transmit
storage
DELAYS CALL ID DTMF 314 PWM 6CH
.def .def
(internal - do not use)
PWM 10K ENCODE ;***** Bit positions in the Status-register
STH-11 ATMEL CORP AVR BUTTERFLY
.equ
RDR=0
;Receive data ready
.equ
TD=6
;Transmitting data
.equ
BUSY=7
;Busy-flag
bit (internal - read-only)
AVR BOOK (internal - read-only)
; ************************************************************************** ;* ;* PROGRAM START - EXECUTION STARTS HERE ;* ; ************************************************************************** .cseg .org $0000 rjmp start
;Reset handler
.org INT0addr rjmp ext_int0
;External interrupt
.org OVF0addr rjmp tim0_ovf
;Timer0 overflow
.org ACIaddr reti
;Analog comparator
handler
handler
handler (Not Used)
; ************************************************************************** ;* ;* EXT_INT0 - External Interrupt Routine 0 ;* ;* ;* DESCRIPTION ;* This routine is executed when a negative edge on the incoming serial ;* signal is detected. It disables further external interrupts and enables ;* timer interrupts (bit-timer) because the UART must now receive the ;* incoming data. ;* ;* This routine sets bits in the GIMSK, TIFR and TIMSK registers. In this ;* code when the bits are set, it overwrites all other bits. This is done ;* because of the lack of available cycles when it operates at low clock ;* rate and high baudrates. ;* ;* ;* Total number of words : 12 ;* Total number of cycles : 15 (incl. reti) ;* Low register usage : 1 (u_sr) ;* High register usage : 4 (u_bit_cnt, u_tmp,u_status,u_reload) ;* ; ************************************************************************** ext_int0: in u_sr,SREG ;Store Status Register ldi rjmp
u_status,1<7) is set tim0_stopb
;
sbrc
u_buffer,0
;if LSB in buffer
sbi
PORTD,PD4
;
sbrs
u_buffer,0
;if LSB in buffer
cbi
PORTD,PD4
;
lsr
u_buffer
;Shift buffer right
out reti
SREG,u_sr
;Restore SREG
jump to stop-
bit-part
is 1 Set transmit
to 1 is 0 Set transmit
to 0
tim0_stopb: sbi PORTD,PD4
;Generate stop-bit
sbrs
u_bit_cnt,0
;if u_bit_cnt==8
rjmp
tim0_ret
;
(stop-bit) jump to exit
tim0_complete: ldi u_tmp,1<' is sent back. The character is also ;* presented on port B. ;* ; ************************************************************************** .def
tmp=r21
;Temp.
.def
buffer=r22
;Recieved
.def
adr=r23
;EEPROM
start: out
ser tmp PORTD,tmp
;Initialize ;Set port D as
sbi
DDRD,DDD4
;
out
DDRB,tmp
;Set port B as
out
PORTB,tmp
rcall sei
uart_init
register byte Address
input with pullups except PD4 ->
output with 1's output with 1's (LED-off)
idle:
sbrs
;Init UART ;Enable interrupts
u_status,RDR
;Wait for
Character rjmp mov
idle buffer,u_buffer
;Get recieved
out
PORTB,u_buffer
;Output the byte on
ldi
adr,example_data
;Set/Restore
character port B pointer to EEPROM data loop:
out
EEAR,adr
;Set the
EEPROM's address sbi
EECR,EERE
;Send the Read
in
u_transmit,EEDR
;Put the data in
rcall
uart_transmit
;And transmit the
strobe the transmit register data wait:
sbrc
u_status,TD
;Wait until
data is sent rjmp
wait
inc cpi
adr adr,example_data+12
;Increase pointer ;Reached byte 12?
breq
idle
;
cpi brne
adr,example_data+10 loop
;Reached byte 10? ; No, jump back
mov
u_transmit,buffer
;Put data in
rcall
uart_transmit
;And transmit it
(End?) Yes, wait for
new char.
transmit register
wait2:
sbrc
u_status,TD
;Wait until
data is sent rjmp
wait2
rjmp
loop
;Continue sendig
chars
; ************************************************************************** ;* ;* Test/Example program data. ;* ;* This is the data that will be sent back when a character is recieved. ;* ; ************************************************************************** .eseg example_data: .db 89 ;'Y' .db 111 ;'o' .db 117 ;'u' .db 32 ;' ' .db 116 ;'t' .db 121 ;'y' .db 112 ;'p' .db 101 ;'e' .db 100 ;'d' .db 32 ;' ' .db 13 ; .db 10 ;
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC http://avr-asm.tripod.com/avr304.html (1 of 2)1/20/2009 8:53:46 PM
16 BIT MATH (AVR 202)
Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr304.html (2 of 2)1/20/2009 8:53:46 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
HALF DUPLEX SOFTWARE UART (AVR 305) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* Title ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX
DIV 3216 FLOAT 128 SQRT16
: Half Duplex Interrupt Driven
Software UART
TUTORIAL #2
DIV 24 24
A V R 3 0 5
************************
ASM MATH TUTORIAL #1
N O T E
Version Last updated Target
: 1.1
Support email
: [email protected]
: 97.08.27 : AT90Sxxxx (All AVR Device)
Code Size Low Register Usage High Register Usage Interrupt Usage : None
: 32 Words : 0 : 4
DESCRIPTION This Application note contains a very code efficient
software UART. ;* The example program receives one character and echoes it back. ; ***************************************************************************
MATH 202
.include "1200def.inc"
MATH 202 ;***** Pin definitions
DEC ASCII INT ASCII HX2ASC
pin is PD0
AVG8 222
pin is PD1
FFT7
.equ
RxD
=0
;Receive
.equ
TxD
=1
;Transmit
;***** Global register variables
COPY 102 LPM 108 EPROM 100
.def .def
bitcnt temp
=R16 =R17
;bit counter ;temporary
.def
Txbyte
=R18
;Data to be
.def
RXbyte
=R19
;Received
storage register
SER EPROM DFLASH AT45
transmitted
FLASH CARD VFX SMIL
data
VFX MEM
.cseg .org 0
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
; *************************************************************************** ;* ;* "putchar" ;* ;* This subroutine transmits the byte stored in the "Txbyte" register ;* The number of stop bits used is set with the sb constant ;* ;* Number of words :14 including return ;* Number of cycles :Depens on bit rate ;* Low registers used :None ;* High registers used :2 (bitcnt,Txbyte) ;* Pointers used :None ;* ; *************************************************************************** .equ sb =1 ;Number of stop bits (1, 2, ...)
I2C/TWI 128 I2C/TWI AT8
putchar:
ldi
bitcnt,9+sb
;1+8+sb (sb is # of
com sec
Txbyte
;Inverte everything ;Start bit
putchar0:
brcc cbi rjmp
putchar1 PORTD,TxD putchar2
;If carry set ; send a '0' ;else
putchar1:
sbi nop
PORTD,TxD
;
putchar2:
rcall UART_delay rcall UART_delay
;One bit delay
lsr dec brne
;Get next bit ;If not all bit sent ; send next ;else ; return
stop bits)
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
Txbyte bitcnt putchar0
ret
LCD44 2313
send a '1'
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
; *************************************************************************** ;* ;* "getchar" ;* ;* This subroutine receives one byte and returns it in the "Rxbyte" register ;* ;* Number of words :14 including return ;* Number of cycles :Depens on when data arrives ;* Low registers used :None ;* High registers used :2 (bitcnt,Rxbyte) ;* Pointers used :None ;* ; ***************************************************************************
DTMF 314 PWM 6CH
getchar:
ldi
bitcnt,9
;8 data bit + 1
getchar1:
sbic rjmp
PIND,RxD getchar1
;Wait for start bit
stop bit
PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
getchar2:
rcall UART_delay
;0.5 bit delay
rcall UART_delay rcall UART_delay
;1 bit delay
clc sbic sec
PIND,RxD
;clear carry ;if RX pin high ;
dec breq
bitcnt getchar3
ror
Rxbyte
;If bit is stop bit ; return ;else ; shift bit into
rjmp
getchar2
;
AVR BOOK
Rxbyte
getchar3:
go get next
ret
; *************************************************************************** ;* ;* "UART_delay" ;* ;* This delay subroutine generates the required delay between the bits when ;* transmitting and receiving bytes. The total execution time is set by the ;* constant "b": ;* ;* 3·b + 7 cycles (including rcall and ret) ;* ;* Number of words :4 including return ;* Low registers used :None ;* High registers used :1 (temp) ;* Pointers used :None ;* ; *************************************************************************** ; Some b values: (See also table in Appnote documentation) ; ; 1 MHz crystal: ; 9600 bps - b=14 ; 19200 bps - b=5 ; 28800 bps - b=2 ; ; 2 MHz crystal: ; 19200 bps - b=14 ; 28800 bps - b=8 ; 57600 bps - b=2 ; 4 MHz crystal: ; 19200 bps - b=31 ; 28800 bps - b=19 ; 57600 bps - b=8 ; 115200 bps - b=2 .equ
b
=31
UART_delay: ldi UART_delay1: brne
;19200 bps @ 4 MHz crystal
temp,b dec temp UART_delay1
ret ;***** Program Execution Starts Here ;***** Test program reset:
sbi
PORTD,TxD
;Init port
pins
forever:
sbi
DDRD,TxD
ldi rcall
Txbyte,12 putchar
rcall mov rcall rjmp
getchar Txbyte,Rxbyte putchar forever
;Clear terminal
;Echo received char
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr305.html (1 of 2)1/20/2009 8:54:26 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr305.html (2 of 2)1/20/2009 8:54:26 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
UART ROUTINES FOR ATMEGA128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; *************************************************************************** ; ; File Name :'M_rs232.asm" ; Title : ATmega128 UART, RS-232 komunikacios rutinok ; Date :2003.02.08. Lastmod.: [2003.02.08.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) ; ;Circular serial I/O buffers, with handshake handling for hardware. ;Interupt driven, thus 'transparent' to User functions ; ;You have a head and tail pointer, a constant that tells the size of the array ; ;One thing to note, is that the buffer store routine is only concerned with the ;tail pointer, and the recall routine is only concerned with the head pointer. ;Only the buffer init routine is concerned with both pointers! ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2001.07.21 VFX Creation (Base on 8515) ; 1.00 2003.02.08 VFX Redesign for Atmega128 ; ; *************************************************************************** ; ; Init_UART ; SendChr ; SendStr ; ; ;Hardware ; *************************************************************************** ;* ;RTS pin , Adas keres DSUB9 7. .equ SER_HSO_PORT=PORTD ;Hardware Handshake output port .equ SER_HSO_DIR=DDRD ;Hardware Handshake output control .equ SER_HSO=7 ;Hardware Handshake Output bit
DALLAS-1W ;CTS pin , Vetelkezseg
DALLAS CRC ETHNET 8019 TEA ADC 128
nyugtazo DSUB9 8. .equ
SER_HSI_PORT=PIND
;Hardware Handshake
.equ
SER_HSI_DIR=DDRD
;Hardware Handshake
.equ
SER_HSI=5
;Hardware Handshake
input port input control
ADC 10B ADC 400
Input bit
ADC 401 .MACRO HS_Enabled cbi
THERM 232 IRD 410
;
SER_HSO_PORT,SER_HSO
;
Set low, HS to off
LCD HD44
.endm
LCD 2313
.MACRO HS_Disabled sbi
LCD44 2313 KBD 240
SER_HSO_PORT,SER_HSO
Set Hi for Dis .endm
MUX 242 KBD PS2 KBD PC/128 PS2 EMU
; ************************************************************************** ;* Const Def
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ******************************************************************** ; ;ASCII Equivalents ; .equ NUL=0x00 ;Null .equ SOH=0x01 ;Start of Header .equ STX=0x02 ;Start of Text .equ ETX=0x03 ;End of Text .equ EOT=0x04 ;End of Transmission .equ ENQ=0x05 ;Enquiry .equ ACK=0x06 ;Acknowlege .equ BEL=0x07 ;Bell .equ BS=0x08 ;Backspace .equ HT=0x09 ;Horizontal Tab .equ LF=0x0A ;Line Feed .equ VT=0x0B ;Vertical Tab .equ FF=0x0C ;Form Feed .equ CR=0x0D ;Carriage Return .equ SO=0x0E ; .equ SI=0x0F ; .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
DLE=0x10 XON=0x11 XOFF=0x12 DC3=0x13 DC4=0x14 NAK=0x15 SYN=0x16 ETB=0x17 CAN=0x18 EM=0x19 SUB=0x1A ESC=0x1B FS=0x1C GS=0x1D RS=0x1E US=0x1F
;Delete ;AKA DC1 ;AKA DC2 ; ; ;Negative Acknowlege ;Sync ; ;Cancel ; ;End of File ; ;Field Separator ;Group Separator ;Record Separator ;
;From the data sheet:BAUD = XTAL/(16*(UBRR+1)) ;Rearranging you get:UBRR = XTAL/(16*BAUD) - 1 ; ;This would work except that any fraction will be truncated. ;For least error we want to round off the result. ;So we add 1/2 as follows: UBRR = XTAL/(16*BAUD) - 1 + 0.5 ;Combining the -1 and the +0.5 we can rewrite this as follows: ; ;UBRR = INT(XTAL/(16*BAUD) - 0.5) .equ .equ
Rx_Buffer_Length = 24 Tx_Buffer_Length = 32
.equ
SendROMTXT = 0x02
;RS232 Tx
.equ
FlSending = 0b00000001
;Tx Send
.equ
FlSendROM = 0b00000010
;Tx Send
func. Send ROM text to RS232
running ROM TXT Flag
; *************************************************************************** .DSEG Rx_Buffer: Rx_Head: Rx_Tail: Rx_Data:
.byte 1 .byte 1 .byte Rx_Buffer_Length
Tx_Buffer: Tx_Head: Tx_Tail: Tx_Data:
.byte 1 .byte 1 .byte Tx_Buffer_Length
UARTFlg: ROMTXT: kuldeskor az aktualis ROM pozicio cime
.byte 1
;UART Flags ;ROM TXT
.byte 3
; ************************************************************************* ;* Text Const ;* .CSEG
; ************************************************************************ ;** Init_UART1 ;** Set up the inital states for the buffers, and make sure the handshake ;** is turned on (Not the Shaddap state), so we can talk. ;** ;** ; ************************************************************************ Init_UART1: ldi R16,0 sts Tx_Tail,R16 sts Tx_Head,R16 sts Rx_Tail,R16 sts Rx_Head,R16 sts UARTFlg,R16 sts sts
CMD_Len,R16 CMD_Pos,R16 ;Set up
Hardware HS I/O bits sbi
SER_HSO_DIR,SER_HSO
;Set as
output HS_Enabled cbi
SER_HSI_PORT,SER_HSI
;Set as
cbi
SER_HSI_DIR,SER_HSI
ldi sts ldi sts
R16,High(SYSCLK/(16*BaudSpeed1)-1) UBRR1H,R16 R16,Low(SYSCLK/(16*BaudSpeed1)-1) UBRR1L,R16 ;BaudRate
ldi
R16,0b00000000
sts
UCSR1A,R16
ldi
R16,0b11011000
sts
UCSR1B,R16
ldi
R16,0b00000110
sts ret
UCSR1C,R16
input, Pull-up
Gen. ;RXCn,
TXCn, UDREn, FEn, DORn, UPEn, U2Xn, MPCMn
;RXCIE,
TXCIE,UDRIE,RXEN,TXEN,UCSZn2,RXB8,TXB8
;–, UMSELn,
UPMn1, UPMn0, USBSn, UCSZn1, UCSZn0, UCPOLn
ECopyr:
.DB "(C) 2003 VFX ATmega128 Service
Terminal [2003.02.08.]",CR .DB "Firmware version ",MAJOR_REV,".", MINOR_REV,MINOR_REVB," " .DB "Latest Upd.: 2003.05.01.",CR,0
;*********************************************** ;* Megnezi, hogy kell-e ujrainditani a Tx muveletet TxRunning:
lds lds cp
ZL,Tx_Head ZH,Tx_Tail ZL,ZH
;ha
breq lds andi
TxRun1 ZL,UARTFlg ZL,FlSending
;Tx
brne
TxRun1
;ha igen
rjmp
USART1_TXC ret
azonosak akkor nincs mit tenni
folyamatban? nincs mit tenni TxRun1:
; *************************************************************************** ; *************************************************************************** ; *************************************************************************** ;** UART TX Functions ; *************************************************************************** ; kod Bufferbe Osszesen ; 0x02 - send ROM TXT -> 0xE0, 0x02, low addr, hi addr ; 4 byte ; 0xE0 - send 0xE0 -> 0xE0, 0xE0 ; 2 byte
; ************************************************************************ ;** Calc Tx Buffer Free Space ; In: ; Out: R18 - Tx_Tail ; R19 - Tx_Head ; R20 - Free Space in Tx Buffer ; Alt: R21 ; ; Tail < Head -> Free= LEN+Tail-Head-1 ; Tail = Head -> Free= LEN ; Tail > Head -> Free= Tail-Head-1 ; FreeInTxBuff: lds R19,Tx_Head lds R18,Tx_Tail ldi R20,Tx_Buffer_Length mov R21,R18 sub R21,R19 breq FreeInTx1 Tx_Buffer_Length brcs FreeInTx2 clr R20 FreeInTx2: add R20,R21 dec R20 FreeInTx1: ret
;T=H, Free=
;************************************************ ;* The RS232 Tx FIFO manager ROM TEXT ;* In: (R16, R17) address word of text (L, H)
*
* ;* Out: c=1 hiba * ;************************************************ SendStr: rcall FreeInTxBuff ;R18,R19-t
is beallitja cpi brcs
R20,4 ExitwError
;ha <4
clr ldi
R18 ZL,low(Tx_Data)
;R18=0 ;Z to the
ldi add adc
ZH,high(Tx_Data) ZL,R19 ZH,R18
;add
push ldi
R16 R16,0xE0
;
rcall ldi
StoreChar R16,SendROMTXT
;Buf
rcall pop rcall
StoreChar R16 StoreChar
;Buf
mov
R16,R17
;Store
rcall sts
StoreChar Tx_Head,R19
;Store new
rcall
TxRunning
nincs eleg hely! Hiba!
addr of txbuffer (FIFO)
address offset...
z = @Buf[Tx_head]
Alternative function indicator cli
[Tx_head]=SendROMTXT indicate Send ROM TXT
[Tx_head]=RomTXT low address sei
RomTXT high address
pointer
clc ret
;Nincs hiba
ExitwError: sec
;Return
with error ret
SendStrW:
rcall brcs ret
SendStr SendStrW
;************************************************ ;* The RS232 Tx FIFO manager Send CHAR * ;* in: R16 char * ;* out c=1 hiba * ;************************************************ SendChr: rcall FreeInTxBuff ;R18,R19-t is beallitja cpi brcs
R20,2 ExitwError
;ha <1
clr ldi
R18 ZL,low(Tx_Data)
;R18=0 ;Pointer to
ldi add adc
ZH,high(Tx_Data) ZL,R19 ZH,R18
;add
cpi
R16,0xE0
;
brne
only1char
;ha igen
rcall rcall sts
StoreChar StoreChar Tx_Head,R19
rcall
TxRunning
nincs elg hely! Hiba!
the txbuffer (FIFO)
address offset...
z = @Buf[txhead]
Alternative kod? akkor ketszer kell atkuldeni!! only1char:
clc ret SendChrW:
; Nincs hiba
push push rcall pop pop brcs ret
ZL ZH SendChr ZH ZL SendChrW
;*********************************************** ; Subrutin for SendROMTXT & SendChar StoreChar:
st inc cpi brcs
Z+,R16 R19 R19,Tx_Buffer_Length StoreC1
;Store char
;TxHead
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is http://avr-asm.tripod.com/uart128.html (1 of 2)1/20/2009 8:55:05 PM
16 BIT MATH (AVR 202)
either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/uart128.html (2 of 2)1/20/2009 8:55:05 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
UART RING BUFFER HOME RETRO_DAN ;-------------------------------------------------------; A UART RING BUFFER ;-------------------------------------------------------.equ rxfifo_length = 0x40 ; length or size
ASM FORUM ASM MATH TUTORIAL #1
of RX fifo buffer (64 bytes)
TUTORIAL #2 TUTORIAL #3
.equ
MATH 201
DIV 24 24 DIV 3216
; length or size
; UART ring buffers
MATH 202
DIV16 XX
0x40
; Arrays .DSEG .org 0x00C0
MATH 200b
MATH YX
=
of TX fifo buffer (64 bytes)
MATH 200
MATH 32X
txfifo_length
rxfifo_n: .byte 1 bytes currently stored in buffer (init: 0)
; number of
rxfifo_in: .byte 2 address in buffer written to (init: rxfifo_base)
; pointer to
rxfifo_out: .byte 2 address in buffer read from (init: rxfifo_base)
; pointer to
FLOAT 128 SQRT16 MATH 202 MATH 202 rxfifo_base: .byte rxfifo_length
DEC ASCII INT ASCII HX2ASC
; reserves
fifo_length bytes for the ; buffer and is used as the buffer’s base address
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
txfifo_n: .byte 1 bytes currently stored in buffer (init: 0)
; number of
txfifo_in: .byte 2 address in buffer written to (init: txfifo_base)
; pointer to
txfifo_out: .byte 2 address in buffer read from (init: txfifo_base)
; pointer to
VFX MEM txfifo_base: .byte txfifo_length
SORT 220 CRC 236
; reserves
fifo_length bytes for the ; buffer and is
XMODEM REC UART 304
used as the buffer’s base address
UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
;--------------; *************************************************************************** ;* ;* "USART_UDRE" interrupt handler ;* Transmits data pending in TX buffer in predefined baud rate & 8n1 ;* (RTS handshake via pin PB0, CTS_in; single- or multibyte transfers) ;* ;* All regs saved ;* ; ***************************************************************************
I2C/TWI 128 I2C/TWI AT8
USART_UDRE: sbic
UCSRA,RXC
; if receiving (RXC
rjmp
U_Tx5
; exit immediately
push in
Flags_tmp Flags_tmp,SREG
; flags may be changed
push
Flags_tmp
;
push push
Tmp1 Tmp2
sbrs rjmp sbic
B_Flags4,2 Get_txfifo PINB,0
; set: use HW handshake ; don't use handshake ; check CTS_in (low =
rjmp
U_Tx3
; pardner not ready, try
"1"),
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128
by arithmetics, so save the
status register
ADC 10B ADC 400 ADC 401
U_Tx1:
THERM 232 IRD 410 LCD HD44
pardner ready for receive)
LCD 2313
later (exit), else
LCD44 2313 KBD 240 MUX 242
Get_txfifo: transmit it lds tst breq sts sts lds lds ld out dec sts brne cbr
Tmp1,txfifo_n Tmp1 ; buffer empty? U_Tx3 save_Y,YL save_Y + 1,YH YL,txfifo_out YH,txfifo_out + 1 Tmp2,Y+ ; ** data_out ** UDR,Tmp2 ; to UART transmit Tmp1 txfifo_n,Tmp1 tx_notclr ; buffer not yet empty! B_Flags3,0x40 ; else: clear TX data
cbi
UCSRB,UDRIE
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
; fetch a byte from TX buffer and
pending flag ; and disable UDRE int
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
tx_notclr: ldi cpi cpc brne ldi ldi
Tmp2,high(txfifo_base + txfifo_length) YL,low(txfifo_base + txfifo_length) YH,Tmp2 end_get_txfifo YL,low(txfifo_base) YH,high(txfifo_base)
end_get_txfifo: sts sts lds lds
txfifo_out,YL txfifo_out + 1,YH YL,save_Y YH,save_Y + 1
exit_get_txfifo: rjmp U_Tx4
; (remove this for multi-
byte transmits) ;rjmp
U_Tx1
; (loop until all bytes
are sent ;
remove this for a one
byte transmit) U_Tx3: cbi
UCSRB,UDRIE
; disable UDRE int to
avoid ADC lock-up if ; HW handshake is active U_Tx4: pop pop pop out
Tmp2 Tmp1 Flags_tmp SREG,Flags_tmp
pop
Flags_tmp
; restore the status
register
U_Tx5: reti ;**** End of USART_UDRE interrupt handler **********************************
; *************************************************************************** ;* ;* "USART_Rx" interrupt handler ;* ;* Stores received bytes to fifo ring buffer ("Add_txfifo") ;* Checks for errors, skips byte if error ;* ;* All regs saved ;* ; *************************************************************************** USART_RXC: push in
Flags_tmp Flags_tmp,SREG
; flags may be changed
push
Flags_tmp
;
push push
Tmp1 Tmp3
in ldi and tst
Tmp1,UCSRA ; get status Tmp3,0b00011100 Tmp1,Tmp3 ; isolate bits 4-2 Tmp1 ; if not zero, we have
breq
U_R_cont
; no error
in
Tmp1,UDR
; fetch defective byte,
;call
Init_rxbuf
; (flush rx fifo buffer,
by arithmetics, so save the
status register
U_R1:
an error
clear its error bits too) ;**call error handler rjmp U_R2
; continue -> test fifo
for another byte U_R_cont: in
Tmp1,UDR
; Add_rxfifo - routine
; get data from UDR ... ; ... and store it to RX
buffer lds
Tmp3,rxfifo_n
; check if
cpi
Tmp3,rxfifo_length - 3
; if buffer
brsh
stop_rx
; (-> HW
buffer full
almost full, push RTS_out high handshake, "stop", used if no rollover) add_rxfifo_HWoff: cpi Tmp3,rxfifo_length
; check if
buffer full breq
full_rxfifo_n
; if so, deal
with that add_rxfifo_cont: sts save_Y,YL
; save Y reg
pair sts lds lds st
save_Y + 1,YH YL,rxfifo_in YH,rxfifo_in + 1 Y+,Tmp1
sbr
B_Flags4,0x02
; set bit 1: rx
inc sts
Tmp3 rxfifo_n,Tmp3
; inc FIFO_n
; setup FIFO_in ; ** store data
from Tmp1 **
data received and pending
; 16-bit cpi with FIFO_base + FIFO_length ldi Tmp3,high(rxfifo_base + rxfifo_length) cpi YL,low(rxfifo_base + rxfifo_length) cpc YH,Tmp3 brne end_add_rxfifo ; if end of buffer ram reached, ldi
YL,low(rxfifo_base)
; rollover: load
ldi
YH,high(rxfifo_base)
; FIFO_base
FIFO_in with
end_add_rxfifo: sts rxfifo_in,YL sts rxfifo_in + 1,YH lds YL,save_Y
; store FIFO_in ; restore Y reg
pair lds
YH,save_Y + 1
exit_add_rxfifo: rjmp U_R2
; return (Exit
Add_rxfifo routine)
full_rxfifo_n:
; buffer is full: either ; overwrite older data in buffer (buffer
rollover) ;sbr
B_Flags4,0x02
;rjmp
add_rxfifo_cont
; clear bit 1,
no more rx data pending
; or, alternative: call error handler and end rjmp
;**call rxfifo_err exit_add_rxfifo
stop_rx:
; alternative if no buffer rollover RTS_high ; HW handshake,
"stop" rjmp
add_rxfifo_HWoff
sbic
UCSRA,RXC
; another byte pending
rjmp
U_R1
; yes, loop
pop pop pop out
Tmp3 Tmp1 Flags_tmp SREG,Flags_tmp
; restore the status
pop reti
Flags_tmp
U_R2: in fifo?
U_R_exit:
register
;**** End of USART_RCX interrupt handler -------------------------------****
; *************************************************************************** ;* ;* UART ring buffer functions ;* ;* ("Add_rxfifo": store a byte from IO_Source (UDR) to buffer, -> ISR) ;* "Get_rxfifo": return 1 byte from rx ring buffer in Tmp2 ;* ;* "Add_txfifo": store a byte to transmit buffer ;* ("Get_txfifo": transmits the bytes stored in transmit buffer -> ISR) ;* ;* "Init_rx/txbuf": initialize/clear fifo ring buffers (RX / TX) ;* ; *************************************************************************** ; ************************************************************************** Get_rxfifo:
; returns a byte from RX buffer in Tmp2 ; (all regs saved, comments cf.
add_rxFIFO) push push lds cpi
Tmp1 Tmp3 Tmp1,rxfifo_n Tmp1,rxfifo_length - 8
; if buffer no
brlo
start_rx
; set RTS_out
longer almost full, low again (ready to receive) get_rxfifo_cont: tst Tmp1 breq exit_get_rxfifo sts save_Y,YL sts save_Y + 1,YH lds YL,rxfifo_out lds YH,rxfifo_out + 1 ld Tmp2,Y+
; ** data_out to
Tmp2 ** dec sts brne cbr
Tmp1 rxfifo_n,Tmp1 rx_notclr B_Flags4,0x02
; rx buffer
empty: clear "data pending" bit rx_notclr: ldi cpi cpc brne ldi ldi
Tmp3,high(rxfifo_base + rxfifo_length) YL,low(rxfifo_base + rxfifo_length) YH,Tmp3 end_get_rxfifo YL,low(rxfifo_base) YH,high(rxfifo_base)
end_get_rxfifo: sts sts lds lds
rxfifo_out,YL rxfifo_out + 1,YH YL,save_Y YH,save_Y + 1
exit_get_rxfifo: pop Tmp3 pop Tmp1 ret
; EXIT function
start_rx:
; switch receive
on again RTS_low rjmp get_rxfifo_cont ; ************************************************************************** ; ************************************************************************** Add_txfifo:
; stores a byte to TX buffer / all regs
saved push push
; entry with data to-be-stored in Tmp2 Tmp1 Tmp3
lds
Tmp3,txfifo_n
; load # of
cpi
Tmp3,txfifo_length
; check if
breq
full_txfifo_n
; if so, deal
add_txfifo_cont: sbr B_Flags3,0x40
; set TX data
chars pending
buffer full with that
pending flag ;sbi
UCSRB,UDRIE
; (enable UDRE
sts
save_Y,YL
; save Y reg
sts lds lds st
save_Y + 1,YH YL,txfifo_in YH,txfifo_in + 1 Y+,Tmp2
inc sts
Tmp3 txfifo_n,Tmp3
int to start transmit!) pair ; setup FIFO_in ; ** store data
from Tmp2 ** ; inc FIFO_n
; 16-bit cpi with FIFO_base + FIFO_length ldi Tmp3,high(txfifo_base + txfifo_length) cpi YL,low(txfifo_base + txfifo_length) cpc YH,Tmp3 brne end_add_txfifo ; if end of buffer ram reached, ldi
YL,low(txfifo_base)
; rollover: load
ldi
YH,high(txfifo_base)
; FIFO_base
FIFO_in with
end_add_txfifo: sts txfifo_in,YL sts txfifo_in + 1,YH lds YL,save_Y
; store FIFO_in ; restore Y reg
pair lds
YH,save_Y + 1
exit_add_txfifo: pop Tmp3 pop Tmp1 ret full_txfifo_n:
; return
; buffer is full: either ; overwrite older data in buffer (buffer
rollover) ;rjmp
add_txfifo_cont ; or, alternative: call error handler
and end rjmp
;call txfifo_err exit_add_txfifo
; ************************************************************************** ; ************************************************************************** ; routines to initialize the RX / TX buffers ; All regs saved Init_rxbuf: push push push
YH YL Tmp1
; init rx buffer clr YL sts rxfifo_n,YL ldi YL,low(rxfifo_base) ldi YH,high(rxfifo_base) sts rxfifo_in,YL sts rxfifo_in + 1,YH sts rxfifo_out,YL sts rxfifo_out + 1,YH cbr
B_Flags4,0x02
; clear "rx data
clr sts
Tmp1 rxfifo_n,Tmp1
; reset FIFO_n
pop pop pop ret
Tmp1 YL YH
pending" bit
Init_txbuf: push push push
YH YL Tmp1
; init tx buffer clr YL sts txfifo_n,YL ldi YL,low(txfifo_base) ldi YH,high(txfifo_base) sts txfifo_in,YL sts txfifo_in + 1,YH sts txfifo_out,YL sts txfifo_out + 1,YH cbr
B_Flags3,0x40
; clear "tx data
clr sts
Tmp1 txfifo_n,Tmp1
; reset FIFO_n
pop pop pop ret
Tmp1 YL YH
pending" bit
;**** End of UART buffer functions -----
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler http://avr-asm.tripod.com/uartbuff.html (1 of 2)1/20/2009 8:55:41 PM
16 BIT MATH (AVR 202)
programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/uartbuff.html (2 of 2)1/20/2009 8:55:41 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
UNIVERSAL SERIAL BUS TO RS232 HOME RETRO_DAN ;*************************************************************************** ;* U S B S T A C K F O R T H E A V R F A M I L Y ;* ;* File Name :"USBtoRS232.asm" ;* Title :USB stack: USB to RS232 converter + USB to 8-bit I/O pins
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2
converter + USB to EEPROM recorder ;* Date :15.09.2003 ;* Version :2.4 ;* Target MCU :ATmega8 ;* AUTHOR :Ing. Igor Cesko ;* Slovakia ;* [email protected] ;* http://www.cesko.host.sk ;* ;* DESCRIPTION: ;* USB protocol implementation into MCU with noUSB interface: ;* Device: ;* Universal USB interface (3x8-bit I/O port + RS232 serial line + EEPROM) ;* + added RS232 FIFO buffer ;* ;* The timing is adapted for 12 MHz crystal ;* ;* Copyright (c) Ing. Igor Cesko 2002-2003 ;* All rights reserved ;* ;* to add your own functions - see section: TEMPLATE OF YOUR FUNCTION ;* ;*************************************************************************** .include "m8def.inc" ;comment for AT90S2313 .equ UCR =UCSRB .equ UBRR =UBRRL .equ EEAR =EEARL .equ USR =UCSRA .equ E2END =127 .equ RAMEND128 =96+127
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
.equ .equ .equ .equ
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
inputport outputport USBdirection DATAplus
=PINB =PORTB =DDRB =1
;signal D+ na PB1
;ENG;signal D+
on PB1 .equ DATAminus =0 ;signal D- na PB0 - treba dat na tento pin pull-up 1.5kOhm ;ENG;signal D- on PB0 - give on this pin pull-up 1.5kOhm .equ USBpinmask =0b11111100 ;mask low 2 bits (D+,D-) on PB ;ENG; mask low 2 bit (D+,D-) on PB .equ USBpinmaskDplus =~(1<
UART 305 .equ .equ .equ ;ENG;signal OUT from IR sensor TSOP1738
UART 128 UART BUFF USB 232
PB2
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44
KBD 240
KBD PC/128 PS2 EMU
ALM CLK
DELAYS CALL ID
STH-11
=PIND
;pripojenie LED diod LSB
LEDdirectionLSB
=DDRD
;vstup/vystup LED LSB
LEDPortMSB
=PORTB
;pripojenie LED diod MSB
LEDPinMSB
=PINB
;pripojenie LED diod MSB
LEDdirectionMSB
=DDRB
;vstup/vystup LED MSB
;ENG;input/
LEDlsb0
=3
;LED0 na pin PD3
;ENG;LED0 on
LEDlsb1
=5
;LED1 na pin PD5
;ENG;LED1 on
LEDlsb2
=6
;LED2 na pin PD6
;ENG;LED2 on
LEDmsb3
=3
;LED3 na pin PB3
;ENG;LED3 on
LEDmsb4
=4
;LED4 na pin PB4
;ENG;LED4 on
LEDmsb5
=5
;LED5 na pin PB5
;ENG;LED5 on
LEDmsb6
=6
;LED6 na pin PB6
;ENG;LED6 on
LEDmsb7
=7
;LED7 na pin PB7
;ENG;LED7 on
.equ
SOPbyte
=0b10000000
;Start of Packet byte
;ENG;Start of
.equ
DATA0PID
=0b11000011
;PID pre DATA0 pole
;ENG;PID for
.equ
DATA1PID
=0b01001011
;PID pre DATA1 pole
;ENG;PID for
.equ
OUTPID
=0b11100001
;PID pre OUT pole
;ENG;PID for
.equ
INPID
=0b01101001
;PID pre IN pole
;ENG;PID for
.equ
SOFPID
=0b10100101
;PID pre SOF pole
;ENG;PID for
.equ
SETUPPID
=0b00101101
;PID pre SETUP pole
;ENG;PID for
.equ
ACKPID
=0b11010010
;PID pre ACK pole
;ENG;PID for
.equ
NAKPID
=0b01011010
;PID pre NAK pole
;ENG;PID for
.equ
STALLPID
=0b00011110
;PID pre STALL pole
;ENG;PID for
.equ
PREPID
=0b00111100
;PID pre PRE pole
;ENG;PID for
=0b00000001
;Start of Packet byte - opacne
=0b11000011
;PID pre DATA0 pole - opacne
=0b11010010
;PID pre DATA1 pole - opacne
=0b10000111
;PID pre OUT pole - opacne
=0b10010110
;PID pre IN pole - opacne
=0b10100101
;PID pre SOF pole - opacne
=0b10110100
;PID pre SETUP pole - opacne
=0b01001011
;PID pre ACK pole - opacne
=0b01011010
;PID pre NAK pole - opacne
=0b01111000
;PID pre STALL pole - opacne
=0b00111100
;PID pre PRE pole - opacne
;ENG;input/ ;ENG;
OUT field IN field SOF field SETUP field ACK field NAK field STALL field FOR field
poradie
.equ nSOPbyte ;ENG;Start of Packet byte - reverse order .equ nDATA0PID ;ENG;PID for DATA0 field - reverse order .equ nDATA1PID ;ENG;PID for DATA1 field - reverse order .equ nOUTPID ;ENG;PID for OUT field - reverse order .equ nINPID ;ENG;PID for IN field - reverse order .equ nSOFPID ;ENG;PID for SOF field - reverse order .equ nSETUPPID ;ENG;PID for SETUP field - reverse order .equ nACKPID ;ENG;PID for ACK field - reverse order .equ nNAKPID ;ENG;PID for NAK field - reverse order .equ nSTALLPID ;ENG;PID for STALL field - reverse order .equ nPREPID ;ENG;PID for FOR field - reverse order
poradie
ATMEL CORP AVR BUTTERFLY
LEDPinLSB
;ENG;
DATA1 field
PWM 10K ENCODE
;pripojenie LED diod LSB
DATA0 field
DTMF 314 PWM 6CH
=PORTD
Packet byte
CLOCK 8564 90 DAYS
LEDPortLSB
;.equ (vstup) ;ENG;connecting LED diode LSB (input) ;.equ output LED LSB ;.equ connecting LED diode MSB ;.equ (vstup) ;ENG;connecting LED diode MSB (input) ;.equ output LED MSB ;.equ pin PD3 ;.equ pin PD5 ;.equ pin PD6 ;.equ pin PB3 ;.equ pin PB4 ;.equ pin PB5 ;.equ pin PB6 ;.equ pin PB7
BOOT MG8 BOOT DR8
;signal OUT z IR senzora TSOP1738 na
connecting LED diode LSB
MUX 242 KBD PS2
=PINB =PORTB =2
;.equ
LCD 2313 LCD44 2313
TSOPPort TSOPpullupPort TSOPPin on PB2
poradie poradie
AVR BOOK poradie poradie poradie poradie poradie poradie poradie
.equ nNRZITokenPID =~0b10000000 SETUP) - opacne poradie NRZI ;ENG;PID mask for Token packet (IN,OUT,SOF,SETUP) - reverse order NRZI .equ nNRZISOPbyte =~0b10101011 NRZI ;ENG;Start of Packet byte - reverse order NRZI .equ nNRZIDATA0PID =~0b11010111 NRZI ;ENG;PID for DATA0 field - reverse order NRZI .equ nNRZIDATA1PID =~0b11001001 NRZI ;ENG;PID for DATA1 field - reverse order NRZI .equ nNRZIOUTPID =~0b10101111 NRZI ;ENG;PID for OUT field - reverse order NRZI .equ nNRZIINPID =~0b10110001 NRZI ;ENG;PID for IN field - reverse order NRZI .equ nNRZISOFPID =~0b10010011 NRZI ;ENG;PID for SOF field - reverse order NRZI .equ nNRZISETUPPID =~0b10001101 NRZI ;ENG;PID for SETUP field - reverse order NRZI .equ nNRZIACKPID =~0b00100111 NRZI ;ENG;PID for ACK field - reverse order NRZI .equ nNRZINAKPID =~0b00111001 NRZI ;ENG;PID for NAK field - reverse order NRZI .equ nNRZISTALLPID =~0b00000111 NRZI ;ENG;PID for STALL field - reverse order NRZI .equ nNRZIPREPID =~0b01111101 NRZI ;ENG;PID for FOR field - reverse order NRZI .equ nNRZIADDR0 =~0b01010101 NRZI ;ENG;Address = 0 - reverse order NRZI
;PID maska pre Token paket (IN,OUT,SOF,
;Start of Packet byte - opacne poradie ;PID pre DATA0 pole - opacne poradie ;PID pre DATA1 pole - opacne poradie ;PID pre OUT pole - opacne poradie ;PID pre IN pole - opacne poradie ;PID pre SOF pole - opacne poradie ;PID pre SETUP pole - opacne poradie ;PID pre ACK pole - opacne poradie ;PID pre NAK pole - opacne poradie ;PID pre STALL pole - opacne poradie ;PID pre PRE pole - opacne poradie ;Adresa = 0 - opacne poradie
;stavove byty - State
;ENG;status bytes -
State .equ .equ .equ .equ .equ .equ
BaseState SetupState InState OutState SOFState DataState
=0 =1 =2 =3 =4 =5
; ; ; ; ; ; ;Flagy pozadovanej akcie
;ENG;Flags of
action .equ .equ .equ .equ .equ
DoNone DoReceiveOutData DoReceiveSetupData DoPrepareOutContinuousBuffer DoReadySendAnswer
.equ
CRC5poly
=0 =1 =2 =3 =4
=0b00101
;CRC5 polynom
;ENG;CRC5
=0b01100
;CRC5 zvysok po uspesnom
=0b1000000000000101
;CRC16 polynom
=0b1000000000001101
;CRC16 zvysok po uspesnom
polynomial .equ CRC5zvysok CRC5 ;ENG;CRC5 remainder after successful CRC5 .equ CRC16poly polynomial .equ CRC16zvysok CRC16 ;ENG;CRC16 remainder after successful CRC16
;ENG;CRC16
.equ MAXUSBBYTES =14 ;maximum bytes in USB input message ;ENG;maximum bytes in USB input message .equ NumberOfFirstBits =10 ;kolko prvych bitov moze byt dlhsich ;ENG;how many first bits allowed be longer .equ NoFirstBitsTimerOffset =256-12800*12/1024 ;Timeout 12.8ms (12800us) na ukoncenie prijmu po uvodnych bitoch (12Mhz:clock, 1024:timer predivider, 256:timer overflow value) ;ENG;Timeout 12.8ms (12800us) to terminate after firsts bits .equ InitBaudRate =12000000/16/57600-1 ;nastavit vysielaciu rychlost UART-u na 57600 (pre 12MHz=12000000Hz) ;ENG;UART on 57600 (for 12MHz=12000000Hz) .equ InputBufferBegin ;ENG;compare of receiving shift buffer .equ InputShiftBufferBegin ;ENG;compare of receiving buffera
=RAMEND128-127
;zaciatok
=InputBufferBegin+MAXUSBBYTES
;zaciatok
prijimacieho shift buffera prijimacieho buffera
.equ OutputBufferBegin buffera ;ENG;compare of transmitting buffer .equ AckBufferBegin Ack ;ENG;compare of transmitting buffer Ack .equ NakBufferBegin Nak ;ENG;compare of transmitting buffer Nak .equ ConfigByte ENG;0=unconfigured state .equ AnswerArray byte answer array .equ StackBegin velky cca 68 bytov) ;ENG;low reservoir (stack is big cca 68 byte)
=RAMEND128-MAXUSBBYTES-2 =OutputBufferBegin-3
;zaciatok vysielacieho buffera
=AckBufferBegin-3
;zaciatok vysielacieho buffera
=NakBufferBegin-1
;0=unconfigured state
;
=ConfigByte-8
;8 byte answer array
;ENG;8
=AnswerArray-1
;spodok zasobnika (stack je
=RAMEND-RAMEND128-10
;maximalna dlzka RS232
=RAMEND128+1
;zaciatok buffera pre RS232
.equ MAXRS232LENGTH ;ENG;maximum length RS232 code .equ RS232BufferBegin ;ENG;compare of buffer for RS232 - receiving .equ RS232BufferEnd .equ RS232ReadPosPtr .equ RS232WritePosPtr .equ RS232LengthPosPtr .equ RS232Reserved .equ RS232FIFOBegin
kodu prijem
.def
;zaciatok vysielacieho
RS232BufferFull
=RS232BufferBegin+MAXRS232LENGTH =RS232BufferBegin+0 =RS232BufferBegin+2 =RS232BufferBegin+4 =RS232BufferBegin+6 =RS232BufferBegin+8
=R1
;priznak plneho RS232 buffera
;ENG;
=R2
;zaloha bitcount registra v INT0
=R3
;ci sa ma citat zo SRAM-ky
=R4
;zaloha Flag registra v Timer
=R5
;zaloha Flag registra v INT0
=R6 =R7
;accumulator ;ENG;accumulator ;pozicia bitstuffingu ;ENG;position
=R8
;kolko bitov sa ma este odvysielat z
=R9
;ci sa ma vkladat alebo mazat
=R10
;kolko sa ma poslat bytov
=R11
;poradove cislo vysielacej
=R12
;dlzka pripravena vo vstupnom USB
=R13
;dlzka odpovede pripravena v USB
=R14
;moja USB adresa na update
=R15
;moja USB adresa
=R16
;co sa ma urobit v hlavnej slucke
=R17
;temporary register
;ENG;temporary
flag of full RS232 buffer .def backupbitcount ;ENG;backup bitcount register in INT0 disconnected .def RAMread if reading from SRAM .def backupSREGTimer interrupte ;ENG;backup Flag register in Timer interrupt .def backupSREG preruseni ;ENG;backup Flag register in INT0 interrupt .def ACC .def lastBitstufNumber in bitstuffing .def OutBitStuffNumber posledneho bytu - bitstuffing ;ENG;how many bits to send last byte - bitstuffing .def BitStuffInOut bitstuffing ;ENG;if insertion or deleting of bitstuffing .def TotalBytesToSend how many bytes to send .def TransmitPart casti ;ENG;order number of transmitting part .def InputBufferLength bufferi ;ENG;length prepared in input USB buffer .def OutputBufferLength bufferi ;ENG;length answers prepared in USB buffer .def MyUpdatedAddress my USB address for update .def MyAddress address preruseni
.def ActionFlag ;ENG;what to do in main program loop .def temp3
programu
;ENG;
;ENG;
;ENG;
;ENG;my USB
register .def
temp2
=R18
;temporary register
;ENG;temporary
.def
temp1
=R19
;temporary register
;ENG;temporary
.def
temp0
=R20
;temporary register
;ENG;temporary
.def
bitcount
=R21
;counter of bits in byte
=R22
;pocitadlo maximalneho poctu prijatych
=R23
;prijimaci register
=R24
;posuvny prijimaci register
;ENG;
;byte stavu stavoveho stroja
;ENG;
register register register ;ENG;
counter of bits in byte bajtov
.def ByteCount ;ENG;counter of maximum number of received bytes .def inputbuf
;ENG;receiver
register .def
shiftbuf
shift receiving register .def State =R25 state byte of status of state machine .def RS232BufptrX =R26 prijatych IR kodov ;ENG;XL register - pointer to buffer of received IR codes .def RS232BufptrXH =R27 .def USBBufptrY =R28 input/output ;ENG;YL register - pointer to USB buffer input/output .def ROMBufptrZ =R30 dat ;ENG;ZL register - pointer to buffer of ROM data
;poziadavky .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
;XL register - pointer do buffera
;YL register - pointer do USB buffera ;ZL register - pointer do buffera ROM
na deskriptory ;ENG;requirements on descriptors GET_STATUS =0 CLEAR_FEATURE =1 SET_FEATURE =3 SET_ADDRESS =5 GET_DESCRIPTOR =6 SET_DESCRIPTOR =7 GET_CONFIGURATION =8 SET_CONFIGURATION =9 GET_INTERFACE =10 SET_INTERFACE =11 SYNCH_FRAME =12
;typy deskriptorov ;ENG;descriptor .equ DEVICE .equ CONFIGURATION .equ STRING .equ INTERFACE .equ ENDPOINT
types =1 =2 =3 =4 =5
;databits .equ .equ .equ .equ
;ENG;databits DataBits5 DataBits6 DataBits7 DataBits8
=0 =1 =2 =3
;parity .equ .equ .equ .equ .equ
;ENG;parity ParityNone ParityOdd ParityEven ParityMark ParitySpace
=0 =1 =2 =3 =4
;stopbits .equ .equ
;ENG;stopbits StopBit1 StopBit2
=0 =1
;user function start number .equ USER_FNC_NUMBER
=100
;-----------------------------------------------------------------------------------------;******************************************************************** ;* Interrupt table ;ENG;* Interrupt table ;******************************************************************** .cseg ;-----------------------------------------------------------------------------------------.org 0 ;po resete ;ENG;after reset rjmp reset ;-----------------------------------------------------------------------------------------.org INT0addr ;externe prerusenie INT0 ;ENG; external interrupt INT0 rjmp INT0handler ;-----------------------------------------------------------------------------------------.org URXCaddr ;prijem zo seriovej linky ;ENG; receiving from serial line push temp0 cbi UCR,RXCIE ;zakazat interrupt od prijimania UART ;ENG;disable interrupt from UART receiving sei ;povol interrupty na obsluhu USB ;ENG;enable interrupts to service USB in temp0,UDR ;nacitaj do temp0 prijate data z UARTu ;ENG;put to temp0 received data from UART in backupSREGTimer,SREG ;zaloha SREG ;ENG;backup SREG push temp2 push temp3 lds temp2,RS232LengthPosPtr lds temp3,RS232LengthPosPtr+1 ;zisti dlzku buffera RS232 kodu ;ENG;determine length of RS232 code buffer cpi temp3,HIGH(RS232BufferEnd-RS232FIFOBegin-1) ;ci by mal pretiect buffer ;ENG;if the buffer would overflow brlo FIFOBufferNoOverflow ;ak nepretecie, tak zapis do FIFO ;ENG;if not overflow then write to FIFO brne NoIncRS232BufferFull ;ak by mal pretiect, tak zabran prepisaniu ;ENG;if buffer would overflow, then prevent of overwriting ;inak (pri rovnosti) este porovnaj Lo byty ;ENG;otherwise (if equall) still compare Lo bytes cpi temp2,LOW(RS232BufferEnd-RS232FIFOBegin-1) ;ak by mal pretiect buffer (Lo byte) ;ENG;if buffer would overflow (Lo byte) brcc NoIncRS232BufferFull ;tak zabran prepisaniu ;ENG; then prevent of overwriting FIFOBufferNoOverflow: push RS232BufptrX push RS232BufptrXH lds RS232BufptrX,RS232WritePosPtr ;nastavenie sa na zaciatok buffera zapisu RS232 kodu ;ENG;set position to begin of buffer write RS232 code lds RS232BufptrXH,RS232WritePosPtr+1 ;nastavenie sa na zaciatok buffera zapisu RS232 kodu ;ENG;set position to begin of buffer write RS232 code st
X+,temp0
;a uloz ho do buffera
;ENG;
and save it to buffer RS232 buffera
cpi RS232BufptrXH,HIGH(RS232BufferEnd+1) ;ENG;if not reached maximum of RS232 buffer brlo NoUARTBufferOverflow
;ak sa nedosiahol maximum ;tak pokracuj
;ENG;then
continue brne
UARTBufferOverflow
;skontroluj aj LSB
;ENG;
check althen LSB RS232 buffera
cpi RS232BufptrX,LOW(RS232BufferEnd+1) ;ENG;if not reached maximum of RS232 buffer brlo NoUARTBufferOverflow
;ak sa nedosiahol maximum ;tak pokracuj
;ENG;then
continue UARTBufferOverflow: ldi RS232BufptrX,LOW(RS232FIFOBegin) ;inak sa nastav na zaciatok buffera ;ENG;otherwise set position to buffer begin ldi RS232BufptrXH,HIGH(RS232FIFOBegin) ;inak sa nastav na zaciatok buffera ;ENG;otherwise set position to buffer begin NoUARTBufferOverflow: sts RS232WritePosPtr,RS232BufptrX ;ulozenie noveho offsetu buffera zapisu RS232 kodu ;ENG;save new offset of buffer write RS232 code sts RS232WritePosPtr+1,RS232BufptrXH ;ulozenie noveho offsetu buffera zapisu RS232 kodu ;ENG;save new offset of buffer write RS232 code ldi temp0,1 ;zvys dlzku RS232 buffera ;ENG;increment length of RS232 buffer add temp2,temp0 ldi temp0,0 adc temp3,temp0 sts RS232LengthPosPtr,temp2 ;uloz dlzku buffera RS232 kodu ;ENG;save length of buffer RS232 code sts RS232LengthPosPtr+1,temp3 ;uloz dlzku buffera RS232 kodu ;ENG;save length of buffer RS232 code pop RS232BufptrXH pop RS232BufptrX NoIncRS232BufferFull: pop temp3 pop temp2 pop temp0 out SREG,backupSREGTimer ;obnova SREG ;ENG;restore SREG cli ;zakazat interrupt kvoli zacykleniu ;ENG;disable interrupt because to prevent reentrant interrupt call sbi UCR,RXCIE ;povolit interrupt od prijimania UART ;ENG;enable interrupt from receiving of UART reti ;-----------------------------------------------------------------------------------------;******************************************************************** ;* Init program ;ENG;* Init program ;******************************************************************** ;-----------------------------------------------------------------------------------------reset: ;inicializacia procesora a premennych na spravne hodnoty ;ENG;initialization of processor and variables to right values ldi temp0,StackBegin ;inicializacia stacku ;ENG;initialization of stack out SPL,temp0 clr clr clr ldi
XH YH ZH temp0,LOW(RS232FIFOBegin)
;RS232 pointer ;ENG;RS232 pointer ;USB pointer ;ENG;USB pointer ;ROM pointer ;ENG;ROM pointer ;nastav na zaciatok buffera Low ;ENG;
sts
RS232ReadPosPtr,temp0
;znuluj ukazovatel citania
;ENG;
sts
RS232WritePosPtr,temp0
;znuluj ukazovatel zapisu
;ENG;
ldi
temp0,HIGH(RS232FIFOBegin)
;nastav na zaciatok buffera
sts
RS232ReadPosPtr+1,temp0
;znuluj ukazovatel citania
;ENG;
sts
RS232WritePosPtr+1,temp0
;znuluj ukazovatel zapisu
;ENG;
sts
RS232LengthPosPtr,YH
;znuluj ukazovatel dlzky
;ENG;
sts
RS232LengthPosPtr+1,YH
;znuluj ukazovatel dlzky
;ENG;
clr
RS232BufferFull
clr
MyUpdatedAddress
;nova adresa USB -
rcall
InitACKBufffer
;inicializacia ACK buffera
;ENG;
rcall
InitNAKBufffer
;inicializacia NAK buffera
;ENG;
rcall
USBReset
;inicializacia USB adresy
;ENG;
ldi
temp0,0b00111100
;nahodit pull-up na PORTB
;ENG;set pull-
out ldi
PORTB,temp0 temp0,0b11111111
;nahodit pull-up na PORTC
;ENG;set pull-
out ldi
PORTC,temp0 temp0,0b11111011
;nahodit pull-up na PORTD
;ENG;set pull-
out
PORTD,temp0
clr out
temp0 UBRRH,temp0
; ;nastavit vysielaciu rychlost UART-u
out
EEARH,temp0
;znulovat EEPROM ukazovatel
;ENG;zero
ldi
temp0,1<
;nastavit mod X2 na UART-e
;ENG;set mode
out ldi
USR,temp0 temp0,InitBaudRate
;nastavit vysielaciu rychlost UART-u
out sbi
UBRR,temp0 UCR,TXEN
;povolit vysielanie UART-u
;ENG;enable
sbi
UCR,RXEN
;povolit prijimanie UART-u
;ENG;enable
sbi
UCR,RXCIE
;povolit interrupt od prijimania UART
;ENG;
ldi
temp0,0x0F
;INT0 - reagovanie na nabeznu hranu
;ENG;
out ldi
MCUCR,temp0 temp0,1<
; ;povolit externy interrupt INT0 ;ENG;enable
set Low to begin of buffer zero index of reading zero index of writing High
;ENG;set High to begin of buffer
zero index of reading zero index of writing zero index of length zero index of length
new address USB -
nedekodovana
;ENG;
non-decoded
initialization of ACK buffer initialization of NAK buffer
initialization of USB addresses
up on PORTB
up on PORTC
up on PORTD
High
;ENG;set UART speed High
EEPROM index
X2 on UART ;ENG;
set UART speed
transmiting of UART receiving of UART enable interrupt from receiving of UART
INT0 - respond to leading edge
external interrupt INT0 out GIMSK,temp0 ;------------------------------------------------------------------------------------------
;******************************************************************** ;* Main program ;ENG;* Main program ;******************************************************************** sei ;povolit interrupty globalne
;ENG;
enable interrupts globally Main: sbis
inputport,DATAminus
;cakanie az sa zmeni D- na 0
;ENG;waiting
rjmp
CheckUSBReset
;a skontroluj, ci to nie je USB reset
cpi breq cpi breq rjmp
ActionFlag,DoReceiveSetupData ProcReceiveSetupData ActionFlag,DoPrepareOutContinuousBuffer ProcPrepareOutContinuousBuffer Main
till change D- to 0 ;ENG;
and check, if isn't USB reset
cca 10ms - tu je to cca 100us)
CheckUSBReset: ldi temp0,255 ;pocitadlo trvania reset-u (podla normy je to ;ENG;counter duration of reset (according to specification is that cca 10ms - here is cca 100us) WaitForUSBReset: sbic inputport,DATAminus ;cakanie az sa zmeni D+ na 0 ;ENG;waiting
till change D+ to 0 rjmp dec brne rcall rjmp
Main temp0 WaitForUSBReset USBReset Main
ProcPrepareOutContinuousBuffer: rcall PrepareOutContinuousBuffer ;priprav pokracovanie odpovede do buffera ;ENG;prepare next sequence of answer to buffer ldi ActionFlag,DoReadySendAnswer rjmp Main ProcReceiveSetupData: ldi USBBufptrY,InputBufferBegin ;pointer na zaciatok prijimacieho buffera ;ENG;pointer to begin of receiving buffer mov ByteCount,InputBufferLength ;dlzka vstupneho buffera ;ENG; length of input buffer rcall DecodeNRZI ;prevod kodovania NRZI na bity ;ENG;transfer NRZI coding to bits rcall MirrorInBufferBytes ;prehodit poradie bitov v bajtoch ;ENG; invert bits order in bytes rcall BitStuff ;odstranenie bit stuffing ;ENG;removal of bitstuffing ;rcall CheckCRCIn ;kontrola CRC ;ENG;rcall CheckCRCIn ;check CRC rcall PrepareUSBOutAnswer ;pripravenie odpovede do vysielacieho buffera ;ENG;prepare answers to transmitting buffer ldi ActionFlag,DoReadySendAnswer rjmp Main ;******************************************************************** ;* Main program END ;ENG;* Main program END ;******************************************************************** ;-----------------------------------------------------------------------------------------;******************************************************************** ;* Interrupt0 interrupt handler ;ENG;* Interrupt0 interrupt handler ;******************************************************************** INT0Handler: ;prerusenie INT0 ;ENG;interrupt INT0 in backupSREG,SREG push temp0 push temp1 ldi
temp0,3
;pocitadlo trvania log0 ;ENG;counter of
ldi
temp1,2
;pocitadlo trvania log1 ;ENG;counter of
duration log0 duration log1 ;cakanie na zaciatok paketu CheckchangeMinus: sbis inputport,DATAminus
;ENG;waiting for begin packet ;cakanie az sa zmeni D- na 1
;ENG;waiting
;cakanie az sa zmeni D+ na 1
;ENG;waiting
till change D- to 1 rjmp CheckchangePlus: sbis
CheckchangeMinus
rjmp DetectSOPEnd: sbis rjmp Increment1: ldi
CheckchangePlus
inputport,DATAplus
till change D+ to 1
inputport,DATAplus Increment0
;D+ =0
temp0,3
;pocitadlo trvania log0 ;ENG;counter of
dec
temp1
;kolko cyklov trvala log1
nop breq
USBBeginPacket
;ak je to koniec SOP - prijimaj paket
rjmp
DetectSOPEnd
ldi
temp1,2
;pocitadlo trvania log1 ;ENG;counter of
dec
temp0
;kolko cyklov trvala log0
;ENG;how many
nop brne
DetectSOPEnd
;ak nenastal SOF - pokracuj
;ENG;if there
;ENG;D+ =0
duration log0 ;ENG;how many
cycles takes log1 ;ENG;
if this is end of SOP - receive packet Increment0: duration log1 cycles take log0
isn't SOF - continue rjmp EndInt0Handler: pop pop pop pop EndInt0HandlerPOP: pop pop mov
EndInt0HandlerPOP2 ACC RS232BufptrX temp3 temp2 USBBufptrY ByteCount bitcount,backupbitcount ;obnova bitcount registra
;ENG;restore
bitcount register EndInt0HandlerPOP2: pop pop out ldi
temp1 temp0 SREG,backupSREG shiftbuf,1<
;znulovat flag interruptu INTF0 ;ENG;zero
interruptu flag INTF0
milisekundu)
out GIFR,shiftbuf reti ;ENG;otherwise finish (was only SOF - every millisecond) USBBeginPacket: mov
;inak skonci (bol iba SOF - kazdu
backupbitcount,bitcount ;zaloha bitcount registra
;ENG;backup
bitcount register in shiftbuf,inputport ;ak ano nacitaj ho ako nulty bit priamo do shift registra ;ENG;if yes load it as zero bit directly to shift register USBloopBegin: push ByteCount ;dalsia zaloha registrov (setrenie casu) ;ENG;additional backup of registers (save of time) push USBBufptrY ldi bitcount,6 ;inicializacia pocitadla bitov v bajte ;ENG; initialization of bits counter in byte ldi ByteCount,MAXUSBBYTES ;inicializacia max poctu prijatych bajtov v pakete ;ENG;initialization of max number of received bytes in packet ldi USBBufptrY,InputShiftBufferBegin ;nastav vstupny buffera ;ENG; set the input buffer USBloop1_6: in inputbuf,inputport cbr inputbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask low 2 bits breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG; if they are zeros - end of USB packet ror inputbuf ;presun Data+ do shift registra ;ENG;transfer Data+ to shift register rol shiftbuf dec bitcount ;zmensi pocitadlo bitov ;ENG;decrement bits counter brne USBloop1_6 ;ak nie je nulove - opakuj naplnanie shift registra ;ENG;if it isn't zero - repeat filling of shift register nop ;inak bude nutne skopirovat shift register bo buffera ;ENG;otherwise is necessary copy shift register to buffer USBloop7: in inputbuf,inputport cbr inputbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask low 2 bits breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG; if they are zeros - end of USB packet ror inputbuf ;presun Data+ do shift registra ;ENG;transfer Data+ to shift register rol shiftbuf ldi bitcount,7 ;inicializacia pocitadla bitov v bajte ;ENG; initialization of bits counter in byte st Y+,shiftbuf ;skopiruj shift register bo buffera a zvys pointer do buffera ;ENG;copy shift register into buffer and increment pointer to buffer USBloop0: ;a zacni prijimat dalsi bajt ;ENG;and start receiving next byte in shiftbuf,inputport ;nulty bit priamo do shift registra ;ENG; zero bit directly to shift register cbr shiftbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask low 2 bits breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG; if they are zeros - end of USB packet dec bitcount ;zmensi pocitadlo bitov ;ENG;decrement bits counter nop ; dec ByteCount ;ak sa nedosiahol maximum buffera ;ENG; if not reached maximum buffer brne USBloop1_6 ;tak prijimaj dalej ;ENG;then receive next rjmp
EndInt0HandlerPOP
;inak opakuj od zaciatku
;ENG;otherwise
cpi
USBBufptrY,InputShiftBufferBegin+3
brcs lds
EndInt0HandlerPOP ;tak skonci ;ENG;then finish temp0,InputShiftBufferBegin+0 ;identifikator paketu do temp0
lds
temp1,InputShiftBufferBegin+1
repeat back from begin USBloopEnd: byte
;ak sa neprijali aspon 3
;ENG;if at least 3 byte not received ;ENG;
identifier of packet to temp0 ;adresa do temp1
;ENG;address
to temp1 brne TestDataPacket ;ak je dlzka ina ako 3 - tak to moze byt iba DataPaket ;ENG;if is length different from 3 - then this can be only DataPaket TestIOPacket: cp temp1,MyAddress ;ak to nie je urcene (adresa) pre mna ;ENG; if this isn't assigned (address) for me brne TestDataPacket ;tak to moze byt este Data Packet ;ENG; then this can be still DataPacket TestSetupPacket:;test na SETUP paket ;ENG;test to SETUP packet cpi temp0,nNRZISETUPPID brne TestOutPacket ;ak nie je Setup PID - dekoduj iny paket ;ENG;if this isn't Setup PID - decode other packet ldi State,SetupState rjmp EndInt0HandlerPOP ;ak je Setup PID - prijimaj nasledny Data paket ;ENG;if this is Setup PID - receive consecutive Data packet TestOutPacket: ;test na OUT paket ;ENG;test for OUT packet cpi temp0,nNRZIOUTPID brne TestInPacket ;ak nie je Out PID - dekoduj iny paket ;ENG; if this isn't Out PID - decode other packet ldi State,OutState rjmp EndInt0HandlerPOP ;ak je Out PID - prijimaj nasledny Data paket ;ENG;if this is Out PID - receive consecutive Data packet TestInPacket: ;test na IN paket ;ENG;test on IN packet cpi temp0,nNRZIINPID brne TestDataPacket ;ak nie je In PID - dekoduj iny paket ;ENG; if this isn't In PID - decode other packet rjmp AnswerToInRequest TestDataPacket: ;test na DATA0 a DATA1 paket ;ENG;test for DATA0 and DATA1 packet cpi temp0,nNRZIDATA0PID breq Data0Packet ;ak nie je Data0 PID - dekoduj iny paket ;ENG;if this isn't Data0 PID - decode other packet cpi temp0,nNRZIDATA1PID brne NoMyPacked ;ak nie je Data1 PID - dekoduj iny paket ;ENG;if this isn't Data1 PID - decode other packet Data0Packet: cpi State,SetupState ;ak bol stav Setup ;ENG;if was state Setup breq ReceiveSetupData ;prijmi ho ;ENG;receive it cpi State,OutState ;ak bol stav Out ;ENG;if was state Out breq ReceiveOutData ;prijmi ho ;ENG;receive it NoMyPacked: ldi State,BaseState ;znuluj stav ;ENG;zero state rjmp EndInt0HandlerPOP ;a prijimaj nasledny Data paket ;ENG;and receive consecutive Data packet AnswerToInRequest: push
temp2
;zazalohuj dalsie registre a pokracuj
;ENG;
backup next registers and continue push push push cpi
temp3 RS232BufptrX ACC ActionFlag,DoReadySendAnswer
brne rcall
NoReadySend SendPreparedUSBAnswer
;ak nie je pripravena odpoved
;ENG;
if isn't prepared answer ;tak posli NAK ;ENG;then send NAK ;poslanie odpovede naspat ;ENG;
transmitting answer back and MyUpdatedAddress,MyUpdatedAddress ;ak je MyUpdatedAddress nenulova ;ENG;if is MyUpdatedAddress nonzero brne SetMyNewUSBAddress ;tak treba zmenit USB adresu ;ENG;then is necessary to change USB address ldi State,InState ldi ActionFlag,DoPrepareOutContinuousBuffer rjmp EndInt0Handler ;a opakuj - cakaj na dalsiu odozvu z USB ;ENG;and repeat - wait for next response from USB ReceiveSetupData: push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG; backup next registers and continue push temp3 push RS232BufptrX push ACC rcall SendACK ;akceptovanie Setup Data paketu ;ENG;accept Setup Data packet rcall FinishReceiving ;ukonci prijem ;ENG;finish receiving ldi ActionFlag,DoReceiveSetupData rjmp EndInt0Handler ReceiveOutData: push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG; backup next registers and continue push temp3 push RS232BufptrX push ACC cpi ActionFlag,DoReceiveSetupData ;ak sa prave spracovava prikaz Setup ;ENG;if is currently in process command Setup breq NoReadySend ;tak posli NAK ;ENG;then send NAK rcall SendACK ;akceptovanie Out paketu ;ENG;accept Out packet clr ActionFlag rjmp EndInt0Handler NoReadySend: rcall SendNAK ;este nie som pripraveny s odpovedou ;ENG; still I am not ready to answer rjmp EndInt0Handler ;a opakuj - cakaj na dalsiu odozvu z USB ;ENG;and repeat - wait for next response from USB ;-----------------------------------------------------------------------------------------SetMyNewUSBAddress: ;nastavi novu USB adresu v NRZI kodovani ;ENG;set new USB address in NRZI coded clr MyAddress ;vychodzi stav odpovede - mojej nNRZI USB adresy ;ENG;original answer state - of my nNRZI USB address ldi temp2,0b00000001 ;maska na xorovanie ;ENG;mask for xoring ldi temp3,8 ;pocitadlo bitov ;ENG;bits counter SetMyNewUSBAddressLoop: mov temp0,MyAddress ;zapamatat si koncovu odpoved ;ENG;remember final answer ror MyUpdatedAddress ;do carry vysielany bit LSB (v smere naskor LSB a potom MSB) ;ENG;to carry transmitting bit LSB (in direction firstly LSB then MSB) brcs NoXORBit ;ak je jedna - nemen stav ;ENG;if one don't change state eor temp0,temp2 ;inak sa bude stav menit podla posledneho bitu odpovede ;ENG;otherwise state will be changed according to last bit of answer NoXORBit: ror temp0 ;posledny bit zmenenej odpovede do carry ;ENG;last bit of changed answer to carry rol MyAddress ;a z carry do koncovej odpovede na miesto LSB (a sucasne prehodenie LSB a MSB poradia) ;ENG;and from carry to final answer to the LSB place (and reverse LSB and MSB order) dec temp3 ;zmensi pocitadlo bitov ;ENG;decrement bits counter brne SetMyNewUSBAddressLoop ;ak pocitadlo bitov nie je nulove opakuj vysielanie s dalsim bitom ;ENG;if bits counter isn't zero repeat transmitting with next bit clr MyUpdatedAddress ;znulovanie adresy ako priznak jej buduceho nemenenia ;ENG;zero addresses as flag of its next unchanging rjmp EndInt0Handler ;-----------------------------------------------------------------------------------------FinishReceiving: ;korekcne akcie na ukoncenie prijmu ;ENG;corrective actions for receive termination cpi bitcount,7 ;prenes do buffera aj posledny necely byte ;ENG;transfer to buffer also last not completed byte breq NoRemainingBits ;ak boli vsetky byty prenesene, tak neprenasaj nic ;ENG;if were all bytes transfered, then nothing transfer inc bitcount ShiftRemainingBits: rol shiftbuf ;posun ostavajuce necele bity na spravnu poziciu ;ENG;shift remaining not completed bits on right position dec bitcount brne ShiftRemainingBits st Y+,shiftbuf ;a skopiruj shift register bo buffera - necely byte ;ENG;and copy shift register bo buffer - not completed byte NoRemainingBits: mov ByteCount,USBBufptrY subi ByteCount,InputShiftBufferBegin-1 ;v ByteCount je pocet prijatych byte (vratane necelych byte) ;ENG;in ByteCount is number of received bytes (including not completed bytes) mov InputBufferLength,ByteCount ;ENG;and save for use in main program ldi USBBufptrY,InputShiftBufferBegin prijimacieho shift buffera ;ENG;pointer to begin of receiving shift buffer ldi RS232BufptrX,InputBufferBegin+1 SOP) ;ENG;data buffer (leave out SOP) push XH ukazovatela ;ENG;save RS232BufptrX Hi index clr XH MoveDataBuffer: ld temp0,Y+ st X+,temp0 dec ByteCount brne MoveDataBuffer
;a uchovat pre pouzitie v
hlavnom programe
;pointer na zaciatok
;data buffer (vynechat ;uschova RS232BufptrX Hi
pop XH ;obnova RS232BufptrX Hi ;ENG;restore RS232BufptrX Hi index ldi ByteCount,nNRZISOPbyte sts InputBufferBegin,ByteCount ;ako keby sa prijal SOP nekopiruje sa zo shift buffera ;ENG;like received SOP - it is not copied from shift buffer ret ;-----------------------------------------------------------------------------------------ukazovatela
;******************************************************************** ;* Other procedures ;ENG;* Other procedures ;******************************************************************** ;-----------------------------------------------------------------------------------------USBReset: ;inicializacia USB stavoveho stroja ;ENG;initialization of USB state engine ldi
temp0,nNRZIADDR0
;inicializacia USB adresy
;ENG;
mov clr
MyAddress,temp0 State
;inicializacia stavoveho stroja ;ENG;
clr clr clr clr
BitStuffInOut OutBitStuffNumber ActionFlag RAMread
;bude sa vycitavat z ROM-ky
initialization of USB address
initialization of state engine
;ENG;will be
reading from ROM
OutputBufferLength do USB
sts ConfigByte,RAMread ;nenakonfiguravany stav ;ENG;unconfigured state ret ;-----------------------------------------------------------------------------------------SendPreparedUSBAnswer: ;poslanie kodovanim NRZI OUT buffera s dlzkou ;ENG;transmitting by NRZI coding OUT buffer with length OutputBufferLength to USB mov ByteCount,OutputBufferLength ;dlzka odpovede ;ENG;length of
answer SendUSBAnswer:
;poslanie kodovanim NRZI OUT buffera do USB
;ENG;transmitting by
NRZI coding OUT buffer to USB ldi USBBufptrY,OutputBufferBegin ;pointer na zaciatok vysielacieho buffera ;ENG;pointer to begin of transmitting buffer SendUSBBuffer: ;poslanie kodovanim NRZI dany buffer do USB ;ENG;transmitting by NRZI coding given buffer to USB ldi temp1,0 ;zvysovanie pointera (pomocna premenna) ;ENG; incrementing pointer (temporary variable) mov temp3,ByteCount ;pocitadlo bytov: temp3 = ByteCount ;ENG; byte counter: temp3 = ByteCount ldi temp2,0b00000011 ;maska na xorovanie ;ENG;mask for xoring ld inputbuf,Y+ ;nacitanie prveho bytu do inputbuf a zvys
http://avr-asm.tripod.com/usb232.html (1 of 4)1/20/2009 8:56:38 PM
16 BIT MATH (AVR 202)
pointer do buffera
;ENG;load first byte to inputbuf and increment pointer to buffer
USB
cbi ;ENG;down DATAPLUS : idle state of USB port sbi ;ENG;set DATAMINUS : idle state of USB port sbi sbi
USB
outputport,DATAplus
;USB ako vystup: ;ENG;USB as output: ;zhodenie DATAplus : kludovy stav portu
outputport,DATAminus
;nahodenie DATAminus : kludovy stav portu
USBdirection,DATAplus USBdirection,DATAminus
;DATAplus ako vystupny ;ENG;DATAPLUS as output ;DATAminus ako vystupny ;ENG;DATAMINUS as
temp0,outputport
;kludovy stav portu USB do temp0
output in
;ENG;
idle state of USB port to temp0 SendUSBAnswerLoop: ldi bitcount,7 SendUSBAnswerByteLoop: nop
;pocitadlo bitov
;ENG;bits counter
;oneskorenie kvoli casovaniu
;ENG;delay
because timing ror inputbuf ;ENG;to carry transmiting bit (in direction first LSB then MSB) brcs NoXORSend if that it is one - don't change USB state eor temp0,temp2 state will be changed NoXORSend: out outputport,temp0 dec bitcount flagu ;ENG;decrement bits counter - according to carry flag brne SendUSBAnswerByteLoop vysielanie s dalsim bitom ;ENG;if bits counter isn't zero - repeat transmiting with next bit sbrs inputbuf,0 USB ;ENG;if is transmiting bit one - don't change USB state eor temp0,temp2 state will be changed NoXORSendLSB: dec temp3 counter ld inputbuf,Y+ buffera ;ENG;load next byte and increment pointer to buffer out outputport,temp0 brne SendUSBAnswerLoop temp3=0) ;ENG;repeat for all buffer (till temp3=0)
;do carry vysielany bit (v smere naskor LSB a
potom MSB)
;ak je jedna - nemen stav na USB ;inak sa bude stav menit
;ENG; ;ENG;otherwise
;vysli von na USB ;ENG;send out to USB ;zmensi pocitadlo bitov - podla carry ;ak pocitadlo bitov nie je nulove - opakuj
;ak je vysielany bit jedna - nemen stav na ;inak sa bude stav menit
;zniz pocitadlo bytov
;ENG;otherwise
;ENG;decrement bytes
;nacitanie dalsieho bytu a zvys pointer do ;vysli von na USB ;ENG;transmit to USB ;opakuj pre cely buffer (pokial
mov
bitcount,OutBitStuffNumber
cpi
bitcount,0
;pocitadlo bitov pre bitstuff
;ENG;
bits counter for bitstuff ;ak nie je potrebny bitstuff
;ENG;if not be
needed bitstuff breq ZeroBitStuf SendUSBAnswerBitstuffLoop: ror inputbuf ;do carry vysielany bit (v smere naskor LSB a potom MSB) ;ENG;to carry transmiting bit (in direction first LSB then MSB) brcs NoXORBitstuffSend ;ak je jedna - nemen stav na USB ;ENG; if is one - don't change state on USB eor temp0,temp2 ;inak sa bude stav menit ;ENG;otherwise state will be changed NoXORBitstuffSend: out outputport,temp0 ;vysli von na USB ;ENG;transmit to USB nop ;oneskorenie kvoli casovaniu ;ENG;delay because of timing dec bitcount ;zmensi pocitadlo bitov - podla carry flagu ;ENG;decrement bits counter - according to carry flag brne SendUSBAnswerBitstuffLoop ;ak pocitadlo bitov nie je nulove opakuj vysielanie s dalsim bitom ;ENG;if bits counter isn't zero - repeat transmiting with next bit ld inputbuf,Y ;oneskorenie 2 cykly ;ENG;delay 2 cycle ZeroBitStuf: nop ;oneskorenie 1 cyklus ;ENG;delay 1 cycle cbr temp0,3 out outputport,temp0 ;vysli EOP na USB ;ENG;transmit EOP on USB
(16 cyklov pri 12MHz)
ldi bitcount,5 ;ENG;delay counter: EOP shouls exists 2 bits (16 cycle at 12MHz) SendUSBWaitEOP: dec bitcount brne SendUSBWaitEOP
;pocitadlo oneskorenia: EOP ma trvat 2 bity
sbi outputport,DATAminus ;nahodenie DATAminus : kludovy stav na port USB ;ENG;set DATAMINUS : idle state on USB port sbi outputport,DATAminus ;oneskorenie 2 cykly: Idle ma trvat 1 bit (8 cyklov pri 12MHz) ;ENG;delay 2 cycle: Idle should exists 1 bit (8 cycle at 12MHz) cbi USBdirection,DATAplus ;DATAplus ako vstupny ;ENG;DATAPLUS as input cbi USBdirection,DATAminus ;DATAminus ako vstupny ;ENG;DATAMINUS as input cbi outputport,DATAminus ;zhodenie DATAminus : treti stav na port USB ;ENG;reset DATAMINUS : the third state on USB port ret ;-----------------------------------------------------------------------------------------ToggleDATAPID: lds temp0,OutputBufferBegin+1 ;nahraj posledne PID ;ENG;load last PID cpi temp0,DATA1PID ;ak bolo posledne DATA1PID byte ;ENG; if last was DATA1PID byte ldi temp0,DATA0PID breq SendData0PID ;tak posli nulovu odpoved s DATA0PID ;ENG;then send zero answer with DATA0PID ldi temp0,DATA1PID ;inak posli nulovu odpoved s DATA1PID ;ENG;otherwise send zero answer with DATA1PID SendData0PID: sts OutputBufferBegin+1,temp0 ;DATA0PID byte ;ENG;DATA0PID byte ret ;-----------------------------------------------------------------------------------------ComposeZeroDATA1PIDAnswer: ldi temp0,DATA0PID ;DATA0 PID - v skutocnosti sa stoggluje na DATA1PID v nahrati deskriptora ;ENG;DATA0 PID - in the next will be toggled to DATA1PID in load descriptor sts OutputBufferBegin+1,temp0 ;nahraj do vyst buffera ;ENG;load to output buffer ComposeZeroAnswer: ldi temp0,SOPbyte sts OutputBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte rcall ToggleDATAPID ;zmen DATAPID ;ENG;change DATAPID ldi temp0,0x00 sts OutputBufferBegin+2,temp0 ;CRC byte ;ENG;CRC byte sts OutputBufferBegin+3,temp0 ;CRC byte ;ENG;CRC byte ldi ByteCount,2+2 ;dlzka vystupneho buffera (SOP a PID + CRC16) ;ENG;length of output buffer (SOP and PID + CRC16) ret ;-----------------------------------------------------------------------------------------InitACKBufffer: ldi temp0,SOPbyte sts ACKBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte ldi temp0,ACKPID sts ACKBufferBegin+1,temp0 ;ACKPID byte ;ENG;ACKPID byte ret ;-----------------------------------------------------------------------------------------SendACK: push USBBufptrY push bitcount push OutBitStuffNumber ldi USBBufptrY,ACKBufferBegin ;pointer na zaciatok ACK buffera ;ENG;pointer to begin of ACK buffer ldi ByteCount,2 ;pocet vyslanych bytov (iba SOP a ACKPID) ;ENG;number of transmit bytes (only SOP and ACKPID) clr OutBitStuffNumber rcall SendUSBBuffer pop OutBitStuffNumber pop bitcount pop USBBufptrY ret ;-----------------------------------------------------------------------------------------InitNAKBufffer: ldi temp0,SOPbyte sts NAKBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte ldi temp0,NAKPID sts NAKBufferBegin+1,temp0 ;NAKPID byte ;ENG;NAKPID byte ret ;-----------------------------------------------------------------------------------------SendNAK: push OutBitStuffNumber ldi USBBufptrY,NAKBufferBegin ;pointer na zaciatok ACK buffera ;ENG;pointer to begin of ACK buffer ldi ByteCount,2 ;pocet vyslanych bytov (iba SOP a NAKPID) ;ENG;number of transmited bytes (only SOP and NAKPID) clr OutBitStuffNumber rcall SendUSBBuffer pop OutBitStuffNumber ret ;-----------------------------------------------------------------------------------------ComposeSTALL: ldi temp0,SOPbyte sts OutputBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte ldi temp0,STALLPID sts OutputBufferBegin+1,temp0 ;STALLPID byte ;ENG;STALLPID byte ldi ByteCount,2 ;dlzka vystupneho buffera (SOP a PID) ;ENG;length of output buffer (SOP and PID) ret ;-----------------------------------------------------------------------------------------DecodeNRZI: ;enkodovanie buffera z NRZI kodu do binarneho ;ENG;encoding of buffer from NRZI code to binary push USBBufptrY ;zalohuj pointer do buffera ;ENG;back up pointer to buffer push ByteCount ;zalohuj dlzku buffera ;ENG;back up length of buffer add ByteCount,USBBufptrY ;koniec buffera do ByteCount ;ENG;end of buffer to ByteCount ser temp0 ;na zabezpecenie jednotkoveho carry (v nasledujucej rotacii) ;ENG;to ensure unit carry (in the next rotation) NRZIloop: ror temp0 ;naplnenie carry z predchadzajuceho byte ;ENG;filling carry from previous byte ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load received byte from buffer mov temp2,temp0 ;posunuty register o jeden bit vpravo a XOR na funkciu NRZI dekodovania ;ENG;shifted register to one bit to the right and XOR for function of NRZI decoding ror temp2 ;carry do najvyssieho bitu a sucasne posuv ;ENG;carry to most significant digit bit and shift eor temp2,temp0 ;samotne dekodovanie NRZI ;ENG;NRZI decoding com temp2 ;negovanie ;ENG;negate st Y+,temp2 ;ulozenie spat ako dekodovany byte a zvys pointer do buffera ;ENG;save back as decoded byte and increment pointer to buffer cp USBBufptrY,ByteCount ;ak este neboli vsetky ;ENG;if not all bytes brne NRZIloop ;tak opakuj ;ENG;then repeat pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length pop USBBufptrY ;obnov pointer do buffera ;ENG;restore pointer to buffer ret ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------BitStuff: ;odstranenie bit-stuffingu v buffri ;ENG;removal of bitstuffing in buffer clr temp3 ;pocitadlo vynechanych bitov ;ENG;counter of omitted bits clr lastBitstufNumber ;0xFF do lastBitstufNumber ;ENG;0xFF to lastBitstufNumber dec lastBitstufNumber BitStuffRepeat: push USBBufptrY ;zalohuj pointer do buffera ;ENG;back up pointer to buffer push ByteCount ;zalohuj dlzku buffera ;ENG;back up buffer length mov temp1,temp3 ;pocitadlo vsetkych bitov ;ENG;counter of all bits ldi temp0,8 ;spocitat vsetky bity v bufferi ;ENG;sum all bits in buffer SumAllBits: add temp1,temp0 dec ByteCount brne SumAllBits ldi temp2,6 ;inicializuj pocitadlo jednotiek ;ENG; initialize counter of ones pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length push ByteCount ;zalohuj dlzku buffera ;ENG;back up buffer length add ByteCount,USBBufptrY ;koniec buffera do ByteCount ;ENG;end of buffer to ByteCount inc ByteCount ;a pre istotu ho zvys o 2 (kvoli posuvaniu) ;ENG;and for safety increment it with 2 (because of shifting) inc ByteCount BitStuffLoop: ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load received byte from buffer ldi bitcount,8 ;pocitadlo bitov v byte ;ENG;bits counter in byte BitStuffByteLoop: ror temp0 ;naplnenie carry z LSB ;ENG;filling carry from LSB brcs IncrementBitstuff ;ak LSB=0 ;ENG;if that LSB=0 ldi temp2,7 ;inicializuj pocitadlo jednotiek +1 (ak bola nula) ;ENG;initialize counter of ones +1 (if was zero) IncrementBitstuff: dec temp2 ;zniz pocitadlo jednotiek (predpoklad jednotkoveho bitu) ;ENG;decrement counter of ones (assumption of one bit) brne NeposunBuffer ;ak este nebolo 6 jednotiek za sebou - neposun buffer ;ENG;if there was not 6 ones together - don't shift buffer cp temp1,lastBitstufNumber ; ldi temp2,6 ;inicializuj pocitadlo jednotiek (ak by sa nerobil bitstuffing tak sa musi zacat odznova) ;ENG;initialize counter of ones (if no bitstuffing will be made then must be started again) brcc NeposunBuffer ;ak sa tu uz robil bitstuffing - neposun buffer ;ENG;if already was made bitstuffing - don't shift buffer dec temp1 ; mov lastBitstufNumber,temp1 ;zapamataj si poslednu poziciu bitstuffingu ;ENG;remember last position of bitstuffing cpi bitcount,1 ;aby sa ukazovalo na 7 bit (ktory sa ma vymazat alebo kde sa ma vlozit nula) ;ENG;for pointing to 7-th bit (which must be deleted or where to insert zero) brne NoBitcountCorrect ldi bitcount,9 ; inc USBBufptrY ;zvys pointer do buffera ENG;increment pointer to buffer NoBitcountCorrect: dec bitcount bst BitStuffInOut,0 brts CorrectOutBuffer ;ak je Out buffer - zvys dlzku buffera ;ENG; if this is Out buffer - increment buffer length rcall ShiftDeleteBuffer ;posun In buffer ;ENG;shift In buffer dec temp3 ;zniz pocitadlo vynechani ;ENG;decrement counter of omission rjmp CorrectBufferEnd CorrectOutBuffer: rcall ShiftInsertBuffer ;posun Out buffer ;ENG;shift Out buffer inc temp3 ;zvys pocitadlo vynechani ;ENG;increment counter of omission CorrectBufferEnd: pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length pop USBBufptrY ;obnov pointer do buffera ;ENG;restore pointer to buffer rjmp BitStuffRepeat ;a restartni od zaciatku ;ENG;and restart from begin NeposunBuffer: dec temp1 ;ak uz boli vsetky bity ;ENG;if already were all bits breq EndBitStuff ;ukonci cyklus ;ENG;finish cycle dec bitcount ;zniz pocitadlo bitov v byte ;ENG;decrement bits counter in byte brne BitStuffByteLoop ;ak este neboli vsetky bity v byte - chod na dalsi bit ;ENG;if not yet been all bits in byte - go to next bit ;inak nahraj dalsi byte ;ENG;otherwise load next byte inc USBBufptrY ;zvys pointer do buffera ;ENG;increment pointer to buffer rjmp BitStuffLoop ;a opakuj ;ENG;and repeat EndBitStuff: pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length pop USBBufptrY ;obnov pointer do buffera ;ENG;restore pointer to buffer bst BitStuffInOut,0 brts IncrementLength ;ak je Out buffer - zvys dlzku Out buffera ;ENG;if this is Out buffer - increment length of Out buffer DecrementLength: ;ak je In buffer - zniz dlzku In buffera ;ENG;if this is In buffer - decrement length of In buffer cpi temp3,0 ;bolo aspon jedno znizenie ;ENG;was at least one decrement breq NoChangeByteCount ;ak nie - nemen dlzku buffera ;ENG;if no don't change buffer length dec ByteCount ;ak je In buffer - zniz dlzku buffera ;ENG; if this is In buffer - decrement buffer length subi temp3,256-8 ;ak nebolo viac ako 8 bitov naviac ;ENG; if there wasn't above 8 bits over brcc NoChangeByteCount ;tak skonci ;ENG;then finish dec ByteCount ;inak este zniz dlzku buffera ;ENG;otherwise next decrement buffer length ret ;a skonci ;ENG;and finish IncrementLength: mov OutBitStuffNumber,temp3 ;zapamataj si pocet bitov naviac ;ENG; remember number of bits over subi temp3,8 ;ak nebolo viac ako 8 bitov naviac ;ENG; if there wasn't above 8 bits over brcs NoChangeByteCount ;tak skonci ;ENG;then finish inc ByteCount ;inak zvys dlzku buffera ;ENG;otherwise increment buffer length mov OutBitStuffNumber,temp3 ;a zapamataj si pocet bitov naviac (znizene o 8) ;ENG;and remember number of bits over (decremented by 8) NoChangeByteCount: ret ;skonci ;ENG;finish ;-----------------------------------------------------------------------------------------ShiftInsertBuffer: ;posuv buffer o jeden bit vpravo od konca az po poziciu: byteUSBBufptrY a bit-bitcount ;ENG;shift buffer by one bit to right from end till to position: byte-USBBufptrY and bit-bitcount mov temp0,bitcount ;vypocet: bitcount= 9-bitcount ;ENG; calculation: bitcount= 9-bitcount ldi bitcount,9 sub bitcount,temp0 ;do bitcount poloha bitu, ktory treba nulovat ;ENG;to bitcount bit position, which is necessary to clear ld temp1,Y ;nahraj byte ktory este treba posunut od pozicie bitcount ;ENG;load byte which still must be shifted from position bitcount rol temp1 ;a posun vlavo cez Carry (prenos z vyssieho byte a LSB do Carry) ;ENG;and shift to the left through Carry (transmission from higher byte and LSB to Carry) ser temp2 ;FF do masky - temp2 ;ENG;FF to mask - temp2 HalfInsertPosuvMask: lsl temp2 ;nula do dalsieho spodneho bitu masky ;ENG; zero to the next low bit of mask dec bitcount ;az pokial sa nedosiahne hranica posuvania v byte ;ENG;till not reached boundary of shifting in byte brne HalfInsertPosuvMask and temp1,temp2 v temp1 ;ENG;unmask that remains only high shifted bits in temp1 com temp2 lsr temp2 bitu ;ENG;shift mask to the right - for insertion of zero bit ld temp0,Y pozicie bitcount do temp0 ;ENG;load byte which must be shifted from position bitcount to temp0 and temp0,temp2 bity v temp0 ;ENG;unmask to remains only low non-shifted bits in temp0 or temp1,temp0 and put together shifted and nonshifted part
;odmaskuj aby zostali iba vrchne posunute bity
;invertuj masku ;ENG;invert mask ;posun masku vpravo - na vlozenie nuloveho ;nahraj byte ktory este treba posunut od
;odmaskuj aby zostali iba spodne neposunute
;a zluc posunutu a neposunutu cast
;ENG;
ld temp0,Y ;nahraj byte ktory este treba posunut od pozicie bitcount ;ENG;load byte which must be shifted from position bitcount rol temp0 ;a posun ho vlavo cez Carry (aby sa nastavilo spravne Carry pre dalsie prenosy) ;ENG;and shift it to the left through Carry (to set right Carry for further carry) st Y+,temp1 ;a nahraj spat upraveny byte ;ENG;and load back modified byte ShiftInsertBufferLoop: cpse USBBufptrY,ByteCount ;ak nie su vsetky cele byty ;ENG;if are not all entire bytes rjmp NoEndShiftInsertBuffer ;tak pokracuj ;ENG;then continue ret ;inak skonci ;ENG;otherwise finish NoEndShiftInsertBuffer: ld temp1,Y ;nahraj byte ;ENG;load byte rol temp1 ;a posun vlavo cez Carry (prenos z nizsieho byte a LSB do Carry) ;ENG;and shift to the left through Carry (carry from low byte and LSB to Carry) st Y+,temp1 ;a nahraj spat ;ENG;and store back rjmp ShiftInsertBufferLoop ;a pokracuj ;ENG;and continue ;-----------------------------------------------------------------------------------------ShiftDeleteBuffer: ;posuv buffera o jeden bit vlavo od konca az po poziciu: byteUSBBufptrY a bit-bitcount ;ENG;shift buffer one bit to the left from end to position: byte-USBBufptrY and bit-bitcount mov temp0,bitcount ;vypocet: bitcount= 9-bitcount ;ENG; calculation: bitcount= 9-bitcount ldi bitcount,9 sub bitcount,temp0 ;do bitcount poloha bitu, ktory este treba posunut ;ENG;to bitcount bit position, which must be shifted mov temp0,USBBufptrY ;uschovanie pointera do buffera ;ENG;backup pointera to buffer inc temp0 ;pozicia celych bytov do temp0 ;ENG;position of completed bytes to temp0 mov USBBufptrY,ByteCount ;maximalna pozicia do pointera ;ENG;maximum position to pointer ShiftDeleteBufferLoop: ld temp1,-Y ;zniz buffer a nahraj byte ;ENG;decrement buffer and load byte ror temp1 ;a posun vpravo cez Carry (prenos z vyssieho byte a LSB do Carry) ;ENG;and right shift through Carry (carry from higher byte and LSB to Carry) st Y,temp1 ;a nahraj spat ;ENG;and store back cpse USBBufptrY,temp0 ;ak nie su vsetky cele byty ;ENG;if there are not all entire bytes rjmp ShiftDeleteBufferLoop ;tak pokracuj ;ENG;then continue ld temp1,-Y ;zniz buffer a nahraj byte ktory este treba ;ENG;decrement buffer and load byte which must be shifted from position bitcount ror temp1 ;a posun vpravo cez Carry (prenos z vyssieho byte a LSB do Carry) ;ENG;and right shift through Carry (carry from higher byte and LSB to Carry) ser temp2 ;FF do masky - temp2 ;ENG;FF to mask - temp2 HalfDeletePosuvMask: dec bitcount ;az pokial sa nedosiahne hranica posuvania v byte ;ENG;till not reached boundary of shifting in byte breq DoneMask lsl temp2 ;nula do dalsieho spodneho bitu masky ;ENG; zero to the next low bit of mask rjmp HalfDeletePosuvMask DoneMask: and temp1,temp2 ;odmaskuj aby zostali iba vrchne posunute bity v temp1 ;ENG;unmask to remain only high shifted bits in temp1 com temp2 ;invertuj masku ;ENG;invert mask ld temp0,Y ;nahraj byte ktory este treba posunut od pozicie bitcount do temp0 ;ENG;load byte which must be shifted from position bitcount to temp0 and temp0,temp2 ;odmaskuj aby zostali iba spodne neposunute bity v temp0 ;ENG;unmask to remain only low nonshifted bits in temp0 or temp1,temp0 ;a zluc posunutu a neposunutu cast ;ENG; and put together shifted and nonshifted part st Y,temp1 ;a nahraj spat ;ENG;and store back ret ;a skonci ;ENG;and finish ;-----------------------------------------------------------------------------------------MirrorInBufferBytes: push USBBufptrY push ByteCount ldi USBBufptrY,InputBufferBegin rcall MirrorBufferBytes pop ByteCount pop USBBufptrY ret ;-----------------------------------------------------------------------------------------MirrorBufferBytes: add ByteCount,USBBufptrY ;ByteCount ukazuje na koniec spravy ;ENG; ByteCount shows to the end of message MirrorBufferloop: ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load received byte from buffer ldi temp1,8 ;pocitadlo bitov ;ENG;bits counter MirrorBufferByteLoop: ror temp0 ;do carry dalsi najnizsi bit ;ENG;to carry next least bit rol temp2 ;z carry dalsi bit na obratene poradie ;ENG; from carry next bit to reverse order dec temp1 ;bol uz cely byte ;ENG;was already entire byte brne MirrorBufferByteLoop ;ak nie tak opakuj dalsi najnizsi bit ;ENG; if no then repeat next least bit st Y+,temp2 ;ulozenie spat ako obrateny byte a zvys pointer do buffera ;ENG;save back as reversed byte and increment pointer to buffer cp USBBufptrY,ByteCount ;ak este neboli vsetky ;ENG;if not yet been all brne MirrorBufferloop ;tak opakuj ;ENG;then repeat ret ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------;CheckCRCIn: ;ENG;CheckCRCIn: ; push USBBufptrY ;ENG; kiss USBBUFPTRY ; push ByteCount ;ENG; kiss ByteCount ; ldi USBBufptrY,InputBuffercompare ;ENG; ldi USBBUFPTRY, InputBuffercompare ; rcall CheckCRC ;ENG; rcall CheckCRC ; pop ByteCount ;ENG; pope ByteCount ; pop USBBufptrY ;ENG; pope USBBUFPTRY ; ret ;ENG; lip ;-----------------------------------------------------------------------------------------AddCRCOut: push USBBufptrY push ByteCount ldi USBBufptrY,OutputBufferBegin rcall CheckCRC com temp0 ;negacia CRC ;ENG;negation of CRC com temp1 st Y+,temp1 ;ulozenie CRC na koniec buffera (najskor MSB) ;ENG;save CRC to the end of buffer (at first MSB) st Y,temp0 ;ulozenie CRC na koniec buffera (potom LSB) ;ENG;save CRC to the end of buffer (then LSB) dec USBBufptrY ;pointer na poziciu CRC ;ENG;pointer to CRC position ldi ByteCount,2 ;otocit 2 byty CRC ;ENG;reverse bits order in 2 bytes CRC rcall MirrorBufferBytes ;opacne poradie bitov CRC (pri vysielani CRC sa posiela naskor MSB) ;ENG;reverse bits order in CRC (transmiting CRC - MSB first) pop ByteCount pop USBBufptrY ret ;-----------------------------------------------------------------------------------------CheckCRC: ;vstup: USBBufptrY = zaciatok spravy ,ByteCount = dlzka spravy ;ENG; input: USBBufptrY = begin of message ,ByteCount = length of message add ByteCount,USBBufptrY ;ByteCount ukazuje na koniec spravy ;ENG; ByteCount points to the end of message inc USBBufptrY ;nastav pointer na zaciatok spravy - vynechat SOP ;ENG;set the pointer to message start - omit SOP ld temp0,Y+ ;nahraj PID do temp0 ;ENG;load PID to temp0 ;a nastav pointer na zaciatok spravy vynechat aj PID ;ENG;and set the pointer to start of message - omit also PID cpi temp0,DATA0PID ;ci je DATA0 pole ;ENG;if is DATA0 field breq ComputeDATACRC ;pocitaj CRC16 ;ENG;compute CRC16 cpi temp0,DATA1PID ;ci je DATA1 pole ;ENG;if is DATA1 field brne CRC16End ;ak nie tak skonci ;ENG;if no then finish ComputeDATACRC: ser temp0 ;inicializacia zvysku LSB na 0xff ;ENG; initialization of remaider LSB to 0xff ser temp1 ;inicializacia zvysku MSB na 0xff ;ENG;initialization of remaider MSB to 0xff CRC16Loop: ld temp2,Y+ ;nahraj spravu do temp2 a zvys pointer do buffera ;ENG;load message to temp2 and increment pointer to buffer ldi temp3,8 ;pocitadlo bitov v byte - temp3 ;ENG;bits counter in byte - temp3 CRC16LoopByte: bst temp1,7 ;do T uloz MSB zvysku (zvysok je iba 16 bitovy - 8 bit vyssieho byte) ;ENG;to T save MSB of remainder (remainder is only 16 bits - 8 bit of higher byte) bld bitcount,0 ;do bitcount LSB uloz T - MSB zvysku ;ENG; to bitcount LSB save T - of MSB remainder eor bitcount,temp2 ;XOR bitu spravy a bitu zvysku - v LSB bitcount ;ENG;XOR of bit message and bit remainder - in LSB bitcount rol temp0 ;posun zvysok dolava - nizsi byte (dva byty cez carry) ;ENG;shift remainder to the left - low byte (two bytes - through carry) rol temp1 ;posun zvysok dolava - vyssi byte (dva byty cez carry) ;ENG;shift remainder to the left - high byte (two bytes - through carry) cbr temp0,1 ;znuluj LSB zvysku ;ENG;znuluj LSB remains lsr temp2 ;posun spravu doprava ;ENG;shift message to right ror bitcount ;vysledok XOR-u bitov z LSB do carry ;ENG; result of XOR bits from LSB to carry brcc CRC16NoXOR ;ak je XOR bitu spravy a MSB zvysku = 0 , tak nerob XOR ;ENG;if is XOR bitmessage and MSB of remainder = 0 , then no XOR ldi bitcount,CRC16poly>>8 ;do bitcount CRC polynom - vrchny byte ;ENG; to bitcount CRC polynomial - high byte eor temp1,bitcount ;a urob XOR zo zvyskom a CRC polynomom vrchny byte ;ENG;and make XOR from remains and CRC polynomial - high byte ldi bitcount,CRC16poly ;do bitcount CRC polynom - spodny byte ;ENG; to bitcount CRC polynomial - low byte eor temp0,bitcount ;a urob XOR zo zvyskom a CRC polynomom spodny byte ;ENG;and make XOR of remainder and CRC polynomial - low byte CRC16NoXOR: dec temp3 ;boli uz vsetky bity v byte ;ENG;were already all bits in byte brne CRC16LoopByte ;ak nie, tak chod na dalsi bit ;ENG;unless, then go to next bit cp USBBufptrY,ByteCount ;bol uz koniec spravy ;ENG;was already endof-message brne CRC16Loop ;ak nie tak opakuj ;ENG;unless then repeat CRC16End: ret ;inak skonci (v temp0 a temp1 je vysledok) ;ENG;otherwise finish (in temp0 and temp1 is result) ;-----------------------------------------------------------------------------------------LoadDescriptorFromROM: lpm ;nahraj z pozicie ROM pointera do R0 ;ENG; load from ROM position pointer to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index to ROM dec ByteCount ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromROM ;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadDescriptorFromROMZeroInsert: lpm ;nahraj z pozicie ROM pointerra do R0 ;ENG; load from ROM position pointer to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer posunut od pozicie bitcount
bst nula
RAMread,3
;ak je 3 bit jednotkovy - nebude sa vkladat
brtc
InsertingZero
;inak sa bude vkladat nula
adiw
ZH:ZL,1
;zvys ukazovatel do ROM ;ENG;increment index
;ENG;if bit 3 is one - don't insert zero ;ENG;otherwise
zero will be inserted to ROM lpm
;nahraj z pozicie ROM pointerra do R0
;ENG;
;R0 uloz do buffera a zvys buffer
;ENG;
load from ROM position pointer to R0 st
Y+,R0
R0 save to buffer and increment buffer
vkladali nuly
clt bld RAMread,3 ;ENG;the third bit in RAMread - for to the next zero insertion will be made rjmp InsertingZeroEnd InsertingZero: clr R0
;a znuluj ;ENG;and clear ;treti bit v RAMread - aby sa v dalsom
;a pokracuj
;ENG;and continue
;na vkladanie nul
;ENG;for insertion of
zero st
Y+,R0
;nulu uloz do buffera a zvys buffer
;ENG;
zero save to buffer and increment buffer InsertingZeroEnd: adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index to ROM subi ByteCount,2 ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromROMZeroInsert ;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadDescriptorFromSRAM: ld R0,Z ;nahraj z pozicie RAM pointerra do R0 ;ENG; load from position RAM pointer to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer adiw ZH:ZL,1 ;zvys ukazovatel do RAM ;ENG;increment index to RAM dec ByteCount ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromSRAM ;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadDescriptorFromEEPROM: out EEARL,ZL ;nastav adresu EEPROM Lo ;ENG;set the address EEPROM Lo out EEARH,ZH ;nastav adresu EEPROM Hi ;ENG;set the address EEPROM Hi sbi EECR,EERE ;vycitaj EEPROM do registra EEDR ;ENG; read EEPROM to register EEDR in R0,EEDR ;nahraj z EEDR do R0 ;ENG;load from EEDR to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer adiw ZH:ZL,1 ;zvys ukazovatel do EEPROM ;ENG;increment index to EEPROM dec ByteCount ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromEEPROM;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadXXXDescriptor: ldi temp0,SOPbyte ;SOP byte ;ENG;SOP byte sts OutputBufferBegin,temp0 ;na zaciatok vysielacieho buffera dat SOP ;ENG;to begin of tramsmiting buffer store SOP ldi ByteCount,8 ;8 bytov nahrat ;ENG;8 byte store ldi USBBufptrY,OutputBufferBegin+2 ;do vysielacieho buffera ;ENG; to transmitting buffer and RAMread,RAMread ;ci sa bude citat z RAM alebo ROM-ky alebo EEPROM-ky ;ENG;if will be reading from RAM or ROM or EEPROM brne FromRAMorEEPROM ;0=ROM,1=RAM,2=EEPROM,4=ROM s vkladanim nuly ;ENG;0=ROM,1=RAM,2=EEPROM,4=ROM with zero insertion (string) FromROM: rjmp LoadDescriptorFromROM ;nahrat descriptor z ROM-ky ;ENG; load descriptor from ROM FromRAMorEEPROM: sbrc RAMread,2 ;ak RAMread=4 ;ENG;if RAMREAD=4 rjmp LoadDescriptorFromROMZeroInsert ;citaj z ROM s vkladanim nuly ;ENG; read from ROM with zero insertion sbrc RAMread,0 ;ak RAMread=1 ;ENG;if RAMREAD=1 rjmp LoadDescriptorFromSRAM ;nahraj data zo SRAM-ky ;ENG;load data from SRAM rjmp LoadDescriptorFromEEPROM ;inak citaj z EEPROM ;ENG;otherwise read from EEPROM EndFromRAMROM: sbrc RAMread,7 ;ak je najvyssi bit v premennej RAMread=1 ;ENG;if is most significant bit in variable RAMread=1 clr RAMread ;znuluj RAMread ;ENG;clear RAMread rcall ToggleDATAPID ;zmenit DATAPID ;ENG;change DATAPID ldi USBBufptrY,OutputBufferBegin+1 ;do vysielacieho buffera - pozicia DATA PID ;ENG;to transmitting buffer - position of DATA PID ret ;-----------------------------------------------------------------------------------------PrepareUSBOutAnswer: ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer rcall PrepareUSBAnswer ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer MakeOutBitStuff: inc BitStuffInOut ;vysielaci buffer - vkladanie bitstuff bitov ;ENG;transmitting buffer - insertion of bitstuff bits ldi USBBufptrY,OutputBufferBegin ;do vysielacieho buffera ;ENG; to transmitting buffer rcall BitStuff mov OutputBufferLength,ByteCount ;dlzku odpovede zapamatat pre vysielanie ;ENG;length of answer store for transmiting clr BitStuffInOut ;prijimaci buffer - mazanie bitstuff bitov ;ENG;receiving buffer - deletion of bitstuff bits ret ;-----------------------------------------------------------------------------------------PrepareUSBAnswer: ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer clr RAMread ;nulu do RAMread premennej - cita sa z ROM-ky ;ENG;zero to RAMread variable - reading from ROM lds temp0,InputBufferBegin+2 ;bmRequestType do temp0 ;ENG; bmRequestType to temp0 lds temp1,InputBufferBegin+3 ;bRequest do temp1 ;ENG;bRequest to temp1 cbr temp0,0b10011111 ;ak je 5 a 6 bit nulovy ;ENG;if is 5 and 6 bit zero brne VendorRequest ;tak to nie je Vendor Request ;ENG; then this isn't Vendor Request rjmp StandardRequest ;ale je to standardny request ;ENG; but this is standard Request ;-------------------------VendorRequest: clr ZH ;pre citanie z RAM alebo EEPROM ;ENG; for reading from RAM or EEPROM cpi temp1,1 brne NoDoSetInfraBufferEmpty rjmp DoSetInfraBufferEmpty zastavene citanim z RAM-ky) ;ENG;restart infra receiving (if it was stopped by reading from RAM) NoDoSetInfraBufferEmpty: cpi temp1,2 brne NoDoGetInfraCode rjmp DoGetInfraCode bufferi) ;ENG;transmit received infra code (if it is in buffer) NoDoGetInfraCode: cpi temp1,3 brne NoDoSetDataPortDirection rjmp DoSetDataPortDirection bitov ;ENG;set flow direction of datal bits NoDoSetDataPortDirection: cpi temp1,4 brne NoDoGetDataPortDirection rjmp DoGetDataPortDirection detect of flow direction of data bits NoDoGetDataPortDirection: cpi temp1,5 brne NoDoSetOutDataPort rjmp DoSetOutDataPort tak ich pull-up) ;ENG;set data bits (if they are inputs, then pull-ups) NoDoSetOutDataPort: cpi temp1,6 brne NoDoGetOutDataPort rjmp DoGetOutDataPort (ak su vstupne, tak ich pull-up) ;ENG;detect settings of data out bits (if they are input, then pull-ups) NoDoGetOutDataPort: cpi temp1,7 brne NoDoGetInDataPort rjmp DoGetInDataPort portu ;ENG;return value of input data port NoDoGetInDataPort: cpi temp1,8 brne NoDoEEPROMRead rjmp DoEEPROMRead adresy ;ENG;return contents of EEPROM from given address NoDoEEPROMRead: cpi temp1,9 brne NoDoEEPROMWrite rjmp DoEEPROMWrite data ;ENG;write to EEPROM to given address given data NoDoEEPROMWrite: cpi temp1,10 brne NoDoRS232Send rjmp DoRS232Send transmit byte to serial line NoDoRS232Send: cpi temp1,11 brne NoDoRS232Read rjmp DoRS232Read (ak sa nejaky prijal) ;ENG;returns received byte from serial line NoDoRS232Read: cpi temp1,12 brne NoDoSetRS232Baud rjmp DoSetRS232Baud linky ;ENG;set line speed of of serial line NoDoSetRS232Baud: cpi temp1,13 brne NoDoGetRS232Baud rjmp DoGetRS232Baud linky ;ENG;return line speed of serial line NoDoGetRS232Baud: cpi temp1,14 brne NoDoGetRS232Buffer rjmp DoGetRS232Buffer linky ;ENG;return line speed of serial line NoDoGetRS232Buffer: cpi temp1,15 brne NoDoSetRS232DataBits rjmp DoSetRS232DataBits linky ;ENG;set line speed of serial line NoDoSetRS232DataBits: cpi temp1,16 brne NoDoGetRS232DataBits rjmp DoGetRS232DataBits linky ;ENG;return line speed of serial line NoDoGetRS232DataBits: cpi temp1,17 brne NoDoSetRS232Parity rjmp DoSetRS232Parity linky ;ENG;set line speed of serial line NoDoSetRS232Parity: cpi temp1,18 brne NoDoGetRS232Parity rjmp DoGetRS232Parity linky ;ENG;return line speed of serial line NoDoGetRS232Parity: cpi temp1,19 brne NoDoSetRS232StopBits rjmp DoSetRS232StopBits linky ;ENG;set line speed of serial line NoDoSetRS232StopBits: cpi temp1,20 brne NoDoGetRS232StopBits rjmp DoGetRS232StopBits linky ;ENG;return line speed of serial line NoDoGetRS232StopBits: cpi brne rjmp
; ; ;restartne infra prijimanie (ak bolo
; ;vysle prijaty infra kod (ak je v
; ;nastavi smer toku datovych
; ;zisti smer toku datovych bitov ;ENG;
; ;nastavi datove bity (ak su vstupne,
; ;zisti nastavenie datovych out bitov
; ;vrati hodnotu datoveho vstupneho
; ;vrati obsah EEPROM od urcitej
; ;zapise EEPROM na urcitu adresu urcite
; ;vysle byte na seriovy linku
;ENG;
; ;vrati prijaty byte zo seriovej linky
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
temp1,USER_FNC_NUMBER+0 NoDoUserFunction0 DoUserFunction0
;
NoDoUserFunction0: cpi brne rjmp
temp1,USER_FNC_NUMBER+1 NoDoUserFunction1 DoUserFunction1
;
NoDoUserFunction1: cpi brne rjmp
temp1,USER_FNC_NUMBER+2 NoDoUserFunction2 DoUserFunction2
;
;vykona uzivatelsku rutinu0
;ENG;
execute of user function0
;vykona uzivatelsku rutinu1
;ENG;
execute of user function1
;vykona uzivatelsku rutinu2
;ENG;
execute of user function1 NoDoUserFunction2:
nulovu odpoved
rjmp ZeroDATA1Answer ;ENG;if that it was something unknown, then prepare zero answer
;ak to bolo nieco nezname, tak priprav
;----------------------------- USER FUNCTIONS -------------------------------------;------------------------------TEMPLATE OF YOUR FUNCTION---------------------------;------------------ BEGIN: This is template how to write own function -------------;free of use are registers: ;temp0,temp1,temp2,temp3,ACC,ZH,ZL ;registers are destroyed after execution (use push/pop to save content) ;at the end of routine you must correctly set registers: ;RAMread - 0=reading from ROM, 1=reading from RAM, 2=reading from EEPROM ;temp0 - number of transmitted data bytes ;ZH,ZL - pointer to buffer of transmitted data (pointer to ROM/RAM/EEPROM) ;to transmit data (preparing data to buffer) : ;to transmit data you must jump to "ComposeEndXXXDescriptor" ;to transmit one zero byte you can jump to "OneZeroAnswer" (commonly used as confirmation of correct processing) ;to transmit two zero byte you can jump to "TwoZeroAnswer"
(commonly used as
confirmation of error in processing) ;for small size (up to 8 bytes) ansver use buffer AnswerArray (see function DoGetOutDataPort:) DoUserFunctionX: DoUserFunction0:
;send byte(s) of RAM starting at position given by first parameter in
function lds lds ;lds ;lds ;lds
temp0,InputBufferBegin+4 temp1,InputBufferBegin+5 temp2,InputBufferBegin+6 temp3,InputBufferBegin+7 ACC,InputBufferBegin+8
;first parameter Lo into temp0 ;first parameter Hi into temp1 ;second parameter Lo into temp2 ;second parameter Hi into temp3 ;number of requested bytes from USB
host (computer) into ACC ;Here add your own code: ;------------------------------------------------------------------nop ;example of code - nothing to do nop nop nop nop ;------------------------------------------------------------------mov ZL,temp0 ;will be sending value of RAM - from address stored in temp0 (first parameter Lo of function) mov ZH,temp1 ;will be sending value of RAM - from address stored in temp1 (first parameter Hi of function) inc RAMread ;RAMread=1 - reading from RAM ldi temp0,255 ;send max number of bytes - 255 bytes are maximum rjmp ComposeEndXXXDescriptor ;a prepare data DoUserFunction1: rjmp OneZeroAnswer ;only confirm receiving by one zero byte answer DoUserFunction2: rjmp TwoZeroAnswer ;only confirm receiving by two zero bytes answer ;------------------ END: This is template how to write own function ----------------
;----------------------------- USER FUNCTIONS -------------------------------------;-------------------------DoSetInfraBufferEmpty: rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-------------------------DoGetInfraCode:
http://avr-asm.tripod.com/usb232.html (2 of 4)1/20/2009 8:56:38 PM
16 BIT MATH (AVR 202)
rjmp
OneZeroAnswer
;potvrd prijem jednou nulou
acknowledge reception with single zero ;-------------------------DoSetDataPortDirection: lds temp1,InputBufferBegin+7 porty menit ;ENG;fourth parameter - bit mask - which port(s) to change
;ENG;
;stvrty parameter - bitova maska ktore
lds temp0,InputBufferBegin+4 DDRB ;ENG;first parameter - direction of data bits DDRB andi temp0,0b00111100 mask unused pins sbrc temp1,0 if bit0 is zero - don't change port state out DDRB,temp0 and update direction of data port
;prvy parameter - smer datovych bitov
lds DDRC ;ENG;second parameter - direction of data bits DDRC sbrc if bit1 is zero - don't change port state out and update direction of data port
temp0,InputBufferBegin+5
;druhy parameter - smer datovych bitov
temp1,1
;ak je bit1 nulovy - nemen port ;ENG;
DDRC,temp0
;a update smeru datoveho portu
;zamaskovat nepouzite piny
;ak je bit0 nulovy - nemen port ;ENG; ;a update smeru datoveho portu
lds temp0,InputBufferBegin+6 DDRD ;ENG;third parameter - direction of data bits DDRD andi temp0,0b11111000 mask unused pins ori temp0,0b00000010 mask unused pins sbrc temp1,2 if bit2 is zero - don't change port state out DDRD,temp0 and update direction of data port rjmp
;ENG;
;ENG;
;treti parameter - smer datovych bitov ;zamaskovat nepouzite piny
;ENG;
;zamaskovat nepouzite piny
;ENG;
;ak je bit2 nulovy - nemen port ;ENG;
OneZeroAnswer
acknowledge reception with single zero ;-------------------------DoGetDataPortDirection: in temp0,DDRB read direction of DDRB sts AnswerArray,temp0 AnswerArray in temp0,DDRC read direction of DDRC sts AnswerArray+1,temp0 AnswerArray in temp0,DDRD read direction of DDRD sts AnswerArray+2,temp0 AnswerArray ldi ZL,AnswerArray AnswerArray ;ENG;sending is value from AnswerArray ldi temp0,0x81 RAMREAD=1 - reading from RAM mov RAMread,temp0 premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,3 are three bytes rjmp ComposeEndXXXDescriptor ;-------------------------DoSetOutDataPort: lds temp1,InputBufferBegin+7 porty menit ;ENG;fourth parameter - bit mask - which port(s) to change
;a update smeru datoveho portu
;ENG;
;potvrd prijem jednou nulou
;ENG;
;nacitaj stav smeru DDRB
;ENG;
;do pola AnswerArray
;ENG;to array
;nacitaj stav smeru DDRC
;ENG;
;do pola AnswerArray
;ENG;to array
;nacitaj stav smeru DDRD
;ENG;
;do pola AnswerArray
;ENG;to array
;posiela sa hodnota z ;RAMread=1 - cita sa z RAM-ky
;ENG;
;(najvyssi bit na 1 - aby sa hned
;posielaju sa tri byty
;ENG;sending
;a priprav data ;ENG;and prepare data
;stvrty parameter - bitova maska ktore
lds temp0,InputBufferBegin+4 ;ENG;first parameter - value of data bits PORTB andi temp0,0b00111100
bitov PORTB
;ENG;
;prvy parameter - hodnota datovych ;zamaskovat nepouzite piny
;ENG;
mask unused pins sbrc
temp1,0
;ak je bit0 nulovy - nemen port ;ENG;
out
PORTB,temp0
;a update datoveho portu
if bit0 is zero - don't change port state ;ENG;
and update data port lds temp0,InputBufferBegin+5 bitov PORTC ;ENG;second parameter - value of data bits PORTC sbrc temp1,1 if bit1 is zero - don't change port state out PORTC,temp0 and update data port
;druhy parameter - hodnota datovych
lds temp0,InputBufferBegin+6 ;ENG;third parameter - value of data bits PORTD andi temp0,0b11111000
;treti parameter - hodnota datovych
bitov PORTD
;ak je bit1 nulovy - nemen port ;ENG; ;a update datoveho portu
;ENG;
;zamaskovat nepouzite piny
;ENG; ;ENG;
mask unused pins ori
temp0,0b00000011
;zamaskovat nepouzite piny
sbrc
temp1,2
;ak je bit2 nulovy - nemen port ;ENG;
out
PORTD,temp0
;a update datoveho portu
;ENG;
rjmp
OneZeroAnswer
;potvrd prijem jednou nulou
;ENG;
mask unused pins if bit2 is zero - don't change port state and update data port
acknowledge reception with single zero ;-------------------------DoGetOutDataPort: in temp0,PORTB ;nacitaj stav PORTB ;ENG;read PORTB sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PORTC ;nacitaj stav PORTC ;ENG;read PORTC sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PORTD ;nacitaj stav PORTD ;ENG;read PORTD sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray ldi ZL,AnswerArray ;posiela sa hodnota z AnswerArray ;ENG;sending is value from AnswerArray ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG; RAMREAD=1 - reading from RAM mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,3 ;posielaju sa tri byty ;ENG;sending are three bytes rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-------------------------DoGetInDataPort: in temp0,PINB ;nacitaj stav PINB ;ENG;read PINB sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PINC ;nacitaj stav PINC ;ENG;read PINC sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PIND ;nacitaj stav PIND ;ENG;read PIND sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray ldi ZL,AnswerArray ;posiela sa hodnota z AnswerArray ;ENG;sending is value from AnswerArray ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG; RAMREAD=1 - reading from RAM mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,3 ;posielaju sa tri byty ;ENG;sending are three bytes rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-----------------------------------------------------------------------------------------DoGetIn: ldi ZL,0 ;posiela sa hodnota v R0 ;ENG; sending value in R0 ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG; RAMread=1 - reading from RAM mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,1 ;posli iba jeden byte ;ENG;send only single byte rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-----------------------------------------------------------------------------------------DoEEPROMRead: lds ZL,InputBufferBegin+4 ;prvy parameter - offset v EEPROMke ;ENG;first parameter - offset in EEPROM lds ZH,InputBufferBegin+5 ldi temp0,2 mov RAMread,temp0 ;RAMread=2 - cita sa z EEPROMky ;ENG;RAMREAD=2 - reading from EEPROM ldi temp0,E2END+1 ;pocet mojich bytovych odpovedi do temp0 - cela dlzka EEPROM ;ENG;number my byte answers to temp0 entire length of EEPROM rjmp ComposeEndXXXDescriptor ;inak priprav data ;ENG;otherwise prepare data ;-------------------------DoEEPROMWrite: lds ZL,InputBufferBegin+4 ;prvy parameter - offset v EEPROM-ke (adresa) ;ENG;first parameter - offset in EEPROM (address) lds ZH,InputBufferBegin+5 lds R0,InputBufferBegin+6 ;druhy parameter - data, ktore sa maju zapisat do EEPROM-ky (data) ;ENG;second parameter - data to store to EEPROM (data) out EEAR,ZL ;nastav adresu EEPROM ;ENG;set the address of EEPROM out EEARH,ZH out EEDR,R0 ;nastav data do EEPROM ;ENG;set the data to EEPROM cli ;zakaz prerusenie ;ENG;disable interrupt sbi EECR,EEMWE ;nastav master write enable ;ENG; set the master write enable sei ;povol prerusenie (este sa vykona nasledujuca instrukcia) ;ENG;enable interrupt (next instruction is performed) sbi EECR,EEWE ;samotny zapis ;ENG;write WaitForEEPROMReady: sbic EECR,EEWE ;pockaj si na koniec zapisu ;ENG; wait to the end of write rjmp WaitForEEPROMReady ;v slucke (max cca 4ms) (kvoli naslednemu citaniu/zapisu) ;ENG;in loop (max cca 4ms) (because of possible next reading/writing) rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-------------------------DoRS232Send: lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota vysielana na RS232 ;ENG;first parameter - value transmitted to RS232 out UDR,temp0 ;vysli data na UART ;ENG;transmit data to UART WaitForRS232Send: sbis UCR,TXEN ;ak nie je povoleny UART vysielac ;ENG;if disabled UART transmitter rjmp OneZeroAnswer ;tak skonci - ochrana kvoli zacykleniu v AT90S2323/2343 ;ENG;then finish - protection because loop lock in AT90S2323/2343 sbis USR,TXC ;pockat na dovysielanie bytu ;ENG; wait for transmition finish rjmp WaitForRS232Send rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-------------------------DoRS232Read: rjmp TwoZeroAnswer ;iba potvrd prijem dvoma nulami ;ENG; only acknowledge reception with two zero ;-------------------------DoSetRS232Baud: lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota baudrate na RS232 ;ENG;first parameter - value of baudrate of RS232 lds temp1,InputBufferBegin+6 ;druhy parameter - hodnota baudrate na RS232 - high byte ;ENG;second parameter - baudrate of RS232 - high byte cbr temp1,1<
temp0,0
;ak nie je RS232 Buffer prazdny ;ENG;
brne cpi
SomeRS232Send temp1,0
;tak ho posli ;ENG;then send it ;ak nie je RS232 Buffer prazdny ;ENG;
if this isn't RS232 Buffer empty
if this isn't RS232 Buffer empty brne SomeRS232Send rjmp OneZeroAnswer jednou nulou ;ENG;otherwise nothing send and acknowledge reception with single zero SomeRS232Send: lds ACC,InputBufferBegin+8 ACC ;ENG;number of requiring bytes to ACC ldi temp2,2 word dlzky buffera) ;ENG;number of possible bytes (plus word of buffer length) add temp0,temp2 ldi temp2,0 adc temp1,temp2 cpi temp1,0 brne AsRequiredGetRS232Buffer transmit as many as requested cp ACC,temp0 dodat ;ENG;if no requested more that I can send brcc NoShortGetRS232Buffer transmit as many as requested AsRequiredGetRS232Buffer: mov temp0,ACC ldi temp1,0 NoShortGetRS232Buffer: subi temp0,2 word length sbci temp1,0 lds temp2,RS232ReadPosPtr RS232 kodu ;ENG;obtain index of reading of buffer of RS232 code lds temp3,RS232ReadPosPtr+1 add temp2,temp0 where is end adc temp3,temp1 cpi temp3,HIGH(RS232BufferEnd+1) would overflow brlo ReadNoOverflow brne ReadOverflow if yes - skip to overflow cpi
;tak ho posli ;ENG;then send it ;inak nic neposli a potvrd prijem
;pocet pozadovanych bytov do ;pocet moznych dodanych bajtov (plus
;ak je MSB>0 ;ENG;if is MSB>0 ;vysli tolko kolko sa ziada ;ENG; ;ak sa neziada viac ako mozem ;vysli tolko kolko sa ziada
;uber word dlzky
;ENG;
;ENG;substract
;zisti ukazovatel citania buffera
;zisti kde je koniec
;ENG;obtain
;ci by mal pretiect
;ENG;if it
; ;ak ano - skoc na pretecenie
;ENG;
temp2,LOW(RS232BufferEnd+1)
;inak porovnaj LSB
;ENG;otherwise
ReadNoOverflow
;a urob to iste ;ENG;and do the same
temp2,LOW(RS232BufferEnd+1)
;vypocitaj kolko sa neprenesie
;ENG;
sbci
temp3,HIGH(RS232BufferEnd+1)
;vypocitaj kolko sa neprenesie
;ENG;
sub
temp0,temp2
;a o to skrat dlzku citania
;ENG;
sbc
temp1,temp3
;a o to skrat dlzku citania
;ENG;
ldi
temp2,LOW(RS232FIFOBegin)
;a zacni od nuly
;ENG;and start
ldi
temp3,HIGH(RS232FIFOBegin)
;a zacni od nuly
;ENG;and start
compare LSB brlo ReadOverflow: subi caculate how many not transfered caculate how many not transfered and with this short length of reading and with this short length of reading from zero from zero
RS232 kodu
ReadNoOverflow: lds ZL,RS232ReadPosPtr ;ENG;obtain index of reading of buffer of RS232 code lds ZH,RS232ReadPosPtr+1 ;ENG;obtain index of reading of buffer of RS232 code
RS232 kodu
;zisti ukazovatel citania buffera
sts RS232ReadPosPtr,temp2 ;ENG;write new index of reading of buffer of RS232 code sts RS232ReadPosPtr+1,temp3 ;ENG;write new index of reading of buffer of RS232 code sbiw ZL,2 ;ENG;space for length data - transmitted as first word
RS232 kodu
RS232 kodu
ako prvy word
cbi UART ;ENG;disable interrupt from UART receiving inc RAMread=1 reading from RAM lds lds kodu ;ENG;obtain buffer length of RS232 code sub buffer length sbc sts kodu ;ENG;write new buffer length of RS232 code sts sbi UART ;ENG;enable interrupt from UART receiving
paketu
;zisti ukazovatel citania buffera
;zapis novy ukazovatel citania buffera
;zapis novy ukazovatel citania buffera
;priestor pre udaj dlzky - prenasa sa
UCR,RXCIE
;zakazat interrupt od prijimania
RAMread
;RAMread=1 - cita sa z RAM-ky
temp2,RS232LengthPosPtr temp3,RS232LengthPosPtr+1
;zisti dlzku buffera RS232
temp2,temp0
;zniz dlzku buffera
temp3,temp1 RS232LengthPosPtr,temp2
;zapis novu dlzku buffera RS232
RS232LengthPosPtr+1,temp3 UCR,RXCIE
;povolit interrupt od prijimania
st
Z+,temp2
;a uloz skutocnu dlzku do
st
Z,temp3
;a uloz skutocnu dlzku do
sbiw
ZL,1
;a nastav sa na zaciatok
;ENG;
;ENG;decrement
paketu
;ENG;and save real length to packet ;ENG;and save real length to packet ;ENG;
and set to begin inc temp0 ;a o tento jeden word zvys pocet prenasanych bajtov (dlzka buffer) ;ENG;and about this word increment number of transmited bytes (buffer length) inc temp0 rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-----------------------------------------------------------------------------------------DoSetRS232DataBits: lds temp0,InputBufferBegin+4 ;prvy parameter - data bits 0=5db, 1=6db, 2=7db, 3=8db ;ENG;first parameter - data bits 0=5db, 1=6db, 2=7db, 3=8db cpi temp0,DataBits8 ;ak sa ma nastavit 8-bitova komunikacia ;ENG;if to set 8-bits communication breq Databits8or9Set ;tak nemen 8/9 bitovu komunikaciu ;ENG;then don't change 8/9 bit communication in temp1,UCSRB ;inak nacitaj UCSRB ;ENG;otherwise load UCSRB cbr temp1,(1<
temp0,3
;nastav 9-databit
;ENG;set the 9-
rcall
RS232DataBitsLocal
;a sucasne vrat v temp1 obsah
cbr rcall rjmp
temp1,(1<
;zakaz paritu
databit UCSRC
;ENG;and return in temp1 contents UCSRC ;ENG;disable parity
;potvrd prijem jednou nulou
;ENG;
acknowledge reception with single zero ParityErrorAnswer: rjmp TwoZeroAnswer ;potvrd prijem dvoma nulami ;ENG; acknowledge reception with two zero ;-----------------------------------------------------------------------------------------DoGetRS232Parity: in temp1,UCSRB ;nacitaj UCSRB ;ENG;load UCSRB sbrc temp1,UCSZ2 ;ak je 9-bitova komunikacia ;ENG; if is 9-bits communication rjmp ParityIsStable ;tak je parita space alebo mark ;ENG; then parity is space or mark
bity
rcall cbr
GetUCSRCtotemp1 temp1,~((1<
;a nechaj nenulove iba paritne
cpi
temp1,(1<
;ak su obidva nastavene ;ENG;if are
ldi
temp0,ParityOdd
;je to odd parita
breq cpi
RetGetParity temp1,(1<
;a skonci ;ENG;and finish ;ak je nastaveny UPM1 ;ENG;if is
ldi
temp0,ParityEven
;je to even parita
breq ldi
RetGetParity temp0,ParityNone
;a skonci ;ENG;and finish ;inak je to none parita ;ENG;otherwise
RetGetParity
;a skonci
temp1,TXB8
;zisti ake je 9.-ty bit ;ENG;obtain
ldi
temp0,ParityMark
;priprav si mark odpoved
;ENG;
brts
RetGetParity
;ak je 1 potom vrat mark
;ENG;
ldi
temp0,ParitySpace
;inak vrat space
R0,temp0
;odpoved daj z temp0 do R0
;ENG;and let nonzero only parity bits
both set ;ENG;this is
odd parity
UPM1 set ;ENG;this is
even parity
is that none parity rjmp ParityIsStable: bst
;ENG;and finish
what is 9-th bit prepare mark answer if is 1 then return mark ;ENG;otherwise
return space RetGetParity: mov
;ENG;
answer move from temp0 to R0 rjmp DoGetIn ;a ukonci ;ENG;and finish ;-----------------------------------------------------------------------------------------DoSetRS232StopBits: lds temp0,InputBufferBegin+4 ;prvy parameter - stop bits 0=1stopbit 1=2stopbits ;ENG;first parameter - stop bit 0=1stopbit 1=2stopbits rcall GetUCSRCtotemp1 bst temp0,0 ;a najnizsi bit z parametra ;ENG; and lowest bit from parameter bld temp1,USBS ;uloz ako stopbit ;ENG;save as stopbit rcall Settemp1toUCSRC rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-----------------------------------------------------------------------------------------DoGetRS232StopBits: rcall GetUCSRCtotemp1 clr R0 ;znuluj odpoved ;ENG;clear answer bst temp1,USBS ;a bit USBS ;ENG;and bit USBS bld R0,0 ;zapis do odpovede ;ENG;write to answer rjmp DoGetIn ;a ukonci ;ENG;and finish ;-----------------------------------------------------------------------------------------;----------------------------- END USER FUNCTIONS ------------------------------------END USER FUNCTIONS -----------------------------OneZeroAnswer: ;posle jednu nulu ;ENG;send single zero ldi temp0,1 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeGET_STATUS2 ;----------------------------- STANDARD USB REQUESTS ---------------------------------STANDARD USB REQUESTS -----------------------------StandardRequest: cpi temp1,GET_STATUS ; breq ComposeGET_STATUS ; cpi breq
temp1,CLEAR_FEATURE ComposeCLEAR_FEATURE
; ;
cpi breq
temp1,SET_FEATURE ComposeSET_FEATURE
; ;
cpi
temp1,SET_ADDRESS
;ak sa ma nastavit adresa
breq
ComposeSET_ADDRESS
;nastav adresu
cpi
temp1,GET_DESCRIPTOR
;ak sa ziada descriptor ;ENG;if
breq
ComposeGET_DESCRIPTOR
;vygeneruj ho
cpi breq
temp1,SET_DESCRIPTOR ComposeSET_DESCRIPTOR
; ;
cpi breq
temp1,GET_CONFIGURATION ComposeGET_CONFIGURATION
; ;
cpi breq
temp1,SET_CONFIGURATION ComposeSET_CONFIGURATION
; ;
cpi breq
temp1,GET_INTERFACE ComposeGET_INTERFACE
; ;
cpi breq
temp1,SET_INTERFACE ComposeSET_INTERFACE
; ;
cpi breq
temp1,SYNCH_FRAME ComposeSYNCH_FRAME
; ; ;ak sa nenasla znama poziadavka ;ENG;
;ENG;
if to set address ;ENG;set the address
requested descriptor ;ENG;generate it
if not found known request nulovu odpoved
rjmp ZeroDATA1Answer ;ENG;if that was something unknown, then prepare zero answer
;ak to bolo nieco nezname, tak priprav
MyUpdatedAddress
ComposeSET_ADDRESS: lds MyUpdatedAddress,InputBufferBegin+4 ;nova adresa do ;ENG;new address to MyUpdatedAddress rjmp ZeroDATA1Answer ;posli nulovu odpoved ;ENG;send zero
answer
ConfigByte
ComposeSET_CONFIGURATION: lds temp0,InputBufferBegin+4 ;ENG;number of configuration to variable ConfigByte sts ConfigByte,temp0 ComposeCLEAR_FEATURE: ComposeSET_FEATURE: ComposeSET_INTERFACE: ZeroStringAnswer: rjmp ZeroDATA1Answer
;cislo konfiguracie do premennej ;
;posli nulovu odpoved
;ENG;send zero
answer ComposeGET_STATUS: TwoZeroAnswer: ldi temp0,2 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 ComposeGET_STATUS2: ldi ZH, high(StatusAnswer<<1) ;ROMpointer na odpoved ;ENG; ROMpointer to answer ldi ZL, low(StatusAnswer<<1) rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeGET_CONFIGURATION: lds temp0,ConfigByte and temp0,temp0 ;ak som nenakonfigurovany ;ENG; if I am unconfigured breq OneZeroAnswer ;tak posli jednu nulu - inak posli moju konfiguraciu ;ENG;then send single zero - otherwise send my configuration ldi temp0,1 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 ldi ZH, high(ConfigAnswerMinus1<<1) ;ROMpointer na odpoved ;ENG; ROMpointer to answer ldi ZL, low(ConfigAnswerMinus1<<1)+1 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeGET_INTERFACE: ldi ZH, high(InterfaceAnswer<<1) ;ROMpointer na odpoved ;ENG; ROMpointer to answer ldi ZL, low(InterfaceAnswer<<1) ldi temp0,1 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeSYNCH_FRAME: ComposeSET_DESCRIPTOR: rcall ComposeSTALL ret ComposeGET_DESCRIPTOR: lds temp1,InputBufferBegin+5 ;DescriptorType do temp1 ;ENG; DescriptorType to temp1 cpi temp1,DEVICE ;DeviceDescriptor ;ENG; DeviceDescriptor breq ComposeDeviceDescriptor ; cpi temp1,CONFIGURATION ;ConfigurationDescriptor ;ENG; ConfigurationDescriptor breq ComposeConfigDescriptor ; cpi temp1,STRING ;StringDeviceDescriptor ;ENG; StringDeviceDescriptor breq ComposeStringDescriptor ; ret ComposeDeviceDescriptor: ldi ZH, high(DeviceDescriptor<<1) ;ROMpointer na descriptor ;ENG; ROMpointer to descriptor ldi ZL, low(DeviceDescriptor<<1) ldi temp0,0x12 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeConfigDescriptor: ldi ZH, high(ConfigDescriptor<<1) ;ROMpointer na descriptor ;ENG; ROMpointer to descriptor ldi ZL, low(ConfigDescriptor<<1) ldi temp0,9+9+7 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 ComposeEndXXXDescriptor: lds TotalBytesToSend,InputBufferBegin+8 ;pocet pozadovanych bytov do TotalBytesToSend ;ENG;number of requested bytes to TotalBytesToSend cp TotalBytesToSend,temp0 ;ak sa neziada viac ako mozem dodat ;ENG;if not requested more than I can send brcs HostConfigLength ;vysli tolko kolko sa ziada ;ENG; transmit the requested number mov TotalBytesToSend,temp0 ;inak posli pocet mojich odpovedi ;ENG;otherwise send number of my answers HostConfigLength: mov temp0,TotalBytesToSend ; clr TransmitPart ;nuluj pocet 8 bytovych odpovedi ;ENG;zero the number of 8 bytes answers andi temp0,0b00000111 ;ak je dlzka delitelna 8-mimi ;ENG; if is length divisible by 8 breq Length8Multiply ;tak nezapocitaj jednu necelu odpoved (pod 8 bytov) ;ENG;then not count one answer (under 8 byte) inc TransmitPart ;inak ju zapocitaj ;ENG;otherwise count it Length8Multiply: mov temp0,TotalBytesToSend ; lsr temp0 ;dlzka 8 bytovych odpovedi sa dosiahne ;ENG;length of 8 bytes answers will reach lsr temp0 ;delenie celociselne 8-mimi ;ENG; integer division by 8 lsr temp0 add TransmitPart,temp0 ;a pripocitanim k poslednej necelej 8mici do premennej TransmitPart ;ENG;and by addition to last non entire 8-bytes to variable TransmitPart ldi temp0,DATA0PID ;DATA0 PID - v skutocnosti sa stoggluje na DATA1PID v nahrati deskriptora ;ENG;DATA0 PID - in the next will be toggled to DATA1PID in load descriptor sts OutputBufferBegin+1,temp0 ;nahraj do vyst buffera ;ENG;store to output buffer rjmp ComposeNextAnswerPart ComposeStringDescriptor: ldi temp1,4+8 ;ak RAMread=4(vkladaj nuly z ROMkoveho citania) + 8(za prvy byte nevkldadaj nulu) ;ENG;if RAMread=4(insert zeros from ROM reading) + 8(behind first byte no load zero) mov RAMread,temp1 lds temp1,InputBufferBegin+4 ;DescriptorIndex do temp1 ;ENG; DescriptorIndex to temp1 cpi temp1,0 ;LANGID String ;ENG;LANGID String breq ComposeLangIDString ; cpi temp1,2 ;DevNameString ;ENG;DevNameString breq ComposeDevNameString ; brcc ZeroStringAnswer ;ak je DescriptorIndex vyssi nez 2 posli nulovu odpoved ;ENG;if is DescriptorIndex higher than 2 - send zero answer ;inak to bude VendorString ;ENG; otherwise is VendorString ComposeVendorString: ldi ZH, high(VendorStringDescriptor<<1) ;ROMpointer na descriptor ;ENG;ROMpointer to descriptor ldi ZL, low(VendorStringDescriptor<<1) ldi temp0,(VendorStringDescriptorEnd-VendorStringDescriptor)*4-2 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeDevNameString: ldi ZH, high(DevNameStringDescriptor<<1) ;ROMpointer na descriptor ;ENG;ROMpointer to descriptor ldi ZL, low(DevNameStringDescriptor<<1) ldi temp0,(DevNameStringDescriptorEnd-DevNameStringDescriptor)*4-2 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeLangIDString: clr RAMread ldi ZH, high(LangIDStringDescriptor<<1) ;ROMpointer na descriptor ;ENG;ROMpointer to descriptor ldi ZL, low(LangIDStringDescriptor<<1) ldi temp0,(LangIDStringDescriptorEnd-LangIDStringDescriptor)*2;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ;-----------------------------------------------------------------------------------------ZeroDATA1Answer: rcall ComposeZeroDATA1PIDAnswer ret ;----------------------------- END positionARD USB REQUESTS ------------------------------------- END DATA ENCRYPTION USB REQUESTS -----------------------------PrepareOutContinuousBuffer: rcall PrepareContinuousBuffer rcall MakeOutBitStuff ret ;-----------------------------------------------------------------------------------------PrepareContinuousBuffer: mov temp0,TransmitPart cpi temp0,1 brne NextAnswerInBuffer ;ak uz je buffer prazdny ;ENG; if buffer empty rcall
ComposeZeroAnswer
;priprav nulovu odpoved ;ENG;prepare
zero answer ret NextAnswerInBuffer: dec TransmitPart
;znizit celkovu dlzku odpovede
;ENG;
decrement general length of answer ComposeNextAnswerPart: mov temp1,TotalBytesToSend
;zniz pocet bytov na vyslanie
;ENG;decrement
number of bytes to transmit subi temp1,8 ;ci je este treba poslat viac ako 8 bytov ;ENG;is is necessary to send more as 8 byte ldi temp3,8 ;ak ano - posli iba 8 bytov ;ENG;if yes send only 8 byte brcc Nad8Bytov mov temp3,TotalBytesToSend ;inak posli iba dany pocet bytov ;ENG; otherwise send only given number of bytes clr TransmitPart inc TransmitPart ;a bude to posledna odpoved ;ENG;and this will be last answer Nad8Bytov: mov TotalBytesToSend,temp1 ;znizeny pocet bytov do TotalBytesToSend ;ENG;decremented number of bytes to TotalBytesToSend rcall LoadXXXDescriptor ldi ByteCount,2 ;dlzka vystupneho buffera (iba SOP a PID) ;ENG;length of output buffer (only SOP and PID) add ByteCount,temp3 ;+ pocet bytov ;ENG;+ number of bytes rcall AddCRCOut ;pridanie CRC do buffera ;ENG;addition of CRC to buffer inc ByteCount ;dlzka vystupneho buffera + CRC16 ;ENG; length of output buffer + CRC16 inc ByteCount ret ;skonci ;ENG;finish ;-----------------------------------------------------------------------------------------.equ USBversion =0x0100 ;pre aku verziu USB je to (1.00) ;ENG;for what version USB is that (1.00) .equ VendorUSBID =0x03EB ;identifikator dodavatela (Atmel=0x03EB) ;ENG; vendor identifier (Atmel=0x03EB) .equ DeviceUSBID =0x0004 ;identifikator vyrobku (USB to RS232 converter ATmega8=0x0004) ;ENG;product identifier (USB to RS232 converter ATmega8=0x0004) .equ DeviceVersion =0x0003 ;cislo verzie vyrobku (verzia=0.03) ;ENG;version number of product (version=0.03) ;(0.01=AT90S2313 Infra buffer) ;ENG; (0.01=AT90S2313 Infra buffer) ;(0.02=AT90S2313 RS232 buffer 32bytes) ;ENG; (0.02=AT90S2313 RS232 buffer 32bytes) ;(0.03=ATmega8 RS232 buffer 800bytes) ;ENG; (0.03=ATmega8 RS232 buffer 800bytes) .equ MaxUSBCurrent =50 ;prudovy odber z USB (50mA) - rezerva na MAX232 ;ENG;current consumption from USB (50mA) - together with MAX232 ;-----------------------------------------------------------------------------------------DeviceDescriptor: .db 0x12,0x01 ;0 byte - velkost deskriptora v bytoch ;ENG;0 byte - size of descriptor in byte ;1 byte - typ deskriptora: Deskriptor zariadenia ;ENG;1 byte - descriptor type: Device descriptor .dw USBversion ;2,3 byte - verzia USB LSB (1.00) ; ENG;2,3 byte - version USB LSB (1.00) .db 0x00,0x00 ;4 byte - trieda zariadenia ;ENG;4 byte device class ;5 byte - podtrieda zariadenia ;ENG;5 byte subclass .db 0x00,0x08 ;6 byte - kod protokolu ;ENG;6 byte - protocol code ;7 byte - velkost FIFO v bytoch ;ENG;7 byte FIFO size in bytes .dw VendorUSBID ;8,9 byte - identifikator dodavatela (Cypress=0x04B4) ;ENG;8,9 byte - vendor identifier (Cypress=0x04B4) .dw DeviceUSBID ;10,11 byte - identifikator vyrobku (teplomer=0x0002) ;ENG;10,11 byte - product identifier (teplomer=0x0002) .dw DeviceVersion ;12,13 byte - cislo verzie vyrobku (verzia=0.01) ;ENG;12,13 byte - product version number (verzia=0.01) .db 0x01,0x02 ;14 byte - index stringu "vyrobca" ; ENG;14 byte - index of string "vendor" ;15 byte - index stringu "vyrobok" ; ENG;15 byte - index of string "product" .db 0x00,0x01 ;16 byte - index stringu "seriove cislo" ;ENG;16 byte - index of string "serial number" ;17 byte - pocet moznych konfiguracii ; ENG;17 byte - number of possible configurations DeviceDescriptorEnd: ;-----------------------------------------------------------------------------------------ConfigDescriptor: .db 0x9,0x02 ;dlzka,typ deskriptoru ;ENG;length, descriptor type ConfigDescriptorLength: .dw 9+9+7 ;celkova dlzka vsetkych deskriptorov ;ENG; entire length of all descriptors ConfigAnswerMinus1: ;pre poslanie cisla congiguration number (pozor je treba este pricitat 1) ;ENG;for sending the number - congiguration number (attention - addition of 1 required) .db 1,1 ;numInterfaces,congiguration number ;ENG; numInterfaces, congiguration number .db 0,0x80 ;popisny index stringu, atributy;bus powered ;ENG;string index, attributes; bus powered .db MaxUSBCurrent/2,0x09 ;prudovy odber, interface descriptor length ;ENG;current consumption, interface descriptor length .db 0x04,0 ;interface descriptor; cislo interface ;ENG; interface descriptor; number of interface InterfaceAnswer: ;pre poslanie cisla alternativneho interface ;ENG;for sending number of alternatively interface .db 0,1 ;alternativne nastavenie interface; pocet koncovych bodov okrem EP0 ;ENG;alternatively interface; number of endpoints except EP0 StatusAnswer: ;2 nulove odpovede (na usetrenie miestom) ;ENG;2 zero answers (saving ROM place) .db 0,0 ;trieda rozhrania; podtrieda rozhrania ;ENG; interface class; interface subclass .db 0,0 ;kod protokolu; index popisneho stringu ;ENG; protocol code; string index .db 0x07,0x5 ;dlzka,typ deskriptoru - endpoint ;ENG; length, descriptor type - endpoint .db 0x81,0 ;endpoint address; transfer type ;ENG; endpoint address; transfer type .dw 0x08 ;max packet size ;ENG;max packet size .db 10,0 ;polling interval [ms]; dummy byte (pre vyplnenie) ;ENG;polling interval [ms]; dummy byte (for filling) ConfigDescriptorEnd: ;-----------------------------------------------------------------------------------------LangIDStringDescriptor: .db (LangIDStringDescriptorEnd-LangIDStringDescriptor)*2,3 ;dlzka, typ: string deskriptor ;ENG;length, type: string descriptor .dw 0x0409 ;English ;ENG;English LangIDStringDescriptorEnd: ;-----------------------------------------------------------------------------------------VendorStringDescriptor: .db (VendorStringDescriptorEnd-VendorStringDescriptor)*4-2,3 ; dlzka, typ: string deskriptor ;ENG;length, type: string descriptor CopyRight: .db "Ing. Igor Cesko, Copyright(c) 2003" CopyRightEnd: VendorStringDescriptorEnd: ;-----------------------------------------------------------------------------------------DevNameStringDescriptor: .db (DevNameStringDescriptorEnd-DevNameStringDescriptor)*4-2,3;dlzka, typ: string deskriptor ;ENG;length, type: string descriptor .db "Igor Atmel-AVR device: Advanced USB to RS232 converter + I/O pins control + EEPROM scratch pad" DevNameStringDescriptorEnd: ;-----------------------------------------------------------------------------------------;******************************************************************** ;* End of Program ;ENG;* End of program ;******************************************************************** ;-----------------------------------------------------------------------------------------;******************************************************************** ;* EEPROM contents ;ENG;* EEPROM contents ;******************************************************************** ;-----------------------------------------------------------------------------------------.eseg ;data v EEPROM-ke (vo finalnej verzii zapoznamkovat) ;ENG;data in EEPROM (at final version comment) ;.org 0x400 ;pre naplnenie EEPROM dat na spravne adresy - hned za kod programu (vo finalnej verzii odpoznamkovat) ;ENG;.org 0x400 ;for filling EEPROM give on right addresses - behind the program code (at final version uncomment) EEData: .db "This device was developed by Ing. Igor Cesko: [email protected] " .db "For more information see: http://www.cesko.host.sk. " .db "S/N:00000001" ;-----------------------------------------------------------------------------------------;******************************************************************** ;* End of file ;ENG;* End of file ;********************************************************************
http://avr-asm.tripod.com/usb232.html (3 of 4)1/20/2009 8:56:38 PM
16 BIT MATH (AVR 202)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/usb232.html (4 of 4)1/20/2009 8:56:38 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ISP PROTOCOL HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* Title : AVR ISP (Auto adr inc, 19200bps) ;* Version : 2.0 ;* Last updated : 1998.01.06 (mlund) ;* Target : AT90S1200 ;* File : ispprog.asm ;* Author : Atmel Norway ;* ;* DESCRIPTION ;* The firmware on all programmers now support a unified protocol for ;* program and data memory programming. The host computer do not need ;* to know if the programmer operates in serial or parallel mode. ;* ;* The following commands are supported. All commands start with a ;* single letter. The programmer returns 13d (carriage return) or the ;* data read after the command is finished. ;* ;* +------------+------------+------+ ;* Commands | Host writes | Host reads | | ;* -------+-----+------+------+-----+ | ;* | ID | data | data | | Note | ;* +-----------------------------------+-----+------+------+-----+------+ ;* | Enter programming mode | 'P' | | | 13d | 1 | ;* | Set address | 'A' | ah al | | 13d | 2 | ;* | Write program memory, low byte | 'c' | dd | | 13d | 3 | ;* | Write program memory, high byte | 'C' | dd | | 13d | 3 | ;* | Issue Page Write | 'm' | | | 13d | | ;* | Read program memory | 'R' | |dd (dd)| | 4 | ;* | Write data memory | 'D' | dd | | 13d | | ;* | Read data memory | 'd' | | dd | | | ;* | Chip erase | 'e' | | | 13d | | ;* | Write lock bits | 'l' | dd | | 13d | | ;* | Write fuse bits | 'f' | dd | | 13d | 11 | ;* | Read fuse and lock bits | 'F' | | dd | | 11 | ;* | Leave programming mode | 'L' | | | 13d | 5 | ;* | Select device type | 'T' | dd | | 13d | 6 | ;* | Read signature bytes | 's' | | 3*dd | | | ;* | Return supported device codes | 't' | | n*dd | 00d | 7 | ;* | Return software identifier | 'S' | | s [7] | | 8 | ;* | Return sofware version | 'V' | | dd dd | | 9 | ;* | Return hardware version | 'v' | | dd dd | | 9 | ;* | Return programmer type | 'p' | | dd | | 10 | ;* | Set LED | 'x' | dd | | 13d | 12 | ;* | Clear LED | 'y' | dd | | 13d | 12 | ;* | Universial command | ':' | 3*dd | dd | 13d | | ;* +-----------------------------------+-----+------+------+-----+------+ ;* ;* NOTE 1 ;* The Enter programming mode command MUST be sent one time prior to ;* the other commands, with the exception of the 't', 'S', 'V', 'v' ;* and 'T' commands. The 'T' command must be sent before this command ;* (see note 6). ;* ;* For programmers supporting both parallel and serial programming ;* mode this command enters parallel programming mode. For programmers ;* supporting only serial programming mode, this command enters serial ;* programming mode. ;* ;* NOTE 2 ;* The ah and al are the high and low order bytes of the address. For ;* parallel programmers this command issues the Load Address Low/High ;* Byte command. For serial programmers the address byte is stored for ;* use by the Read/Write commands. ;* ;* NOTE 3 ;* For parallel programmers this command issues the Program Flash ;* command. For serial programmers this command iussues the Write ;* Program Memory Command. For devices with byte-wide program memories ;* only the low byte command should be used. ;* ;* NOTE 4 ;* The contents of the program memory at the address given by the 'A' ;* command are written to the serial port in binary form. For byte ;* wide memories one byte is written. For 16 bit memories two bytes ;* are written,MSB first. ;* ;* NOTE 5 ;* This command must be executed after the programming is finished. ;* ;* NOTE 6 ;* The select device type command must be sent before the enter ;* programming command ;* ;* NOTE 7 ;* The supported device codes are returned in binary form terminated ;* by 0x00. ;* ;* NOTE 8 ;* This return a 7 character ASCII string identifying the programmer. ;* For the in-system programmer it is "AVR ISP". ;* ;* NOTE 9 ;* The software/hardware version are returned as two ASCII numbers. ;* ;* NOTE 10 ;* This command should be used to identify the programmer type. The ;* return value is 'S' for serial (or SPI) programmers or 'P' for ;* parallel programmers. ;* ;* NOTE 11 ;* The write fuse bits command are available only on parallel ;* programmers and only for AVR devices (device code < 0x80). The host ;* should use the return programmer type command to determine the ;* programmer type, do not use the "AVR PPR" idenifier because other ;* programmers may be available in the future. ;* ;* NOTE 12 ;* Currently only the AVR development board has LEDs. The other boards ;* must implement this commands as NOPs. ;* ;* NOTE 13 ;* Devices using Page Mode Programming write one page of flash memory ;* before issuing a Page Mode Write Pulse. ; *************************************************************************** ;**** includes **** .include "1200def.inc" ; *************************************************************************** ;* ;* CONSTANTS ;* device codes ;* ;* DESCRIPTION ;* The following device codes must be used by the host computer. Note ;* that the device codes are arbitrary selected, they do not have any ;* thing in common with the signature bytes stored in the device. ;* ;* The following devices are supported (make a new table for each ;* software release): ;* ;* SW_MAJOR=1, SW_MINOR=5 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ;* SW_MAJOR=1, SW_MINOR=6 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ATmega103 rev. A (abbreviated S01838A) ;* ; *************************************************************************** .equ .equ .equ .equ .equ .equ .equ
S1200C S1200D S2313A S4414A S8515A S8252 S2323A
= = = = = = =
0x12 0x13 0x20 0x28 0x38 0x86 0x48
.equ .equ
S01838C = 0x40 S01838D = 0x41
;**** Revision Codes **** .equ
SW_MAJOR = 2
; Major SW revision
.equ
SW_MINOR = 0
; Minor SW revision
.equ
HW_MAJOR = 1
; Major HW revision
.equ
HW_MINOR = 0
; Minor HW revision
number number number number
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following four macros if the RESET pin to the ;* target moves and/or if the SCK/MISO/MOSO moves. ;* ; *************************************************************************** .macro sbi .endm
set_reset portb,4
.macro cbi .endm
clr_reset portb,4
.macro nop ; sbi .endm
ddrd_init
.macro ldi out
ddrb_init temp1,0xdf ddrb,temp1
ddrd,3
; PB5 is input, the rest is
output .endm .macro ldi brlo tst brmi s0b: ldi s1: rcall == 0x53)
ddrb_release temp1,(1<= 0x20) && (device <= 0x7F) ) s2 device s2 ; { count,32 ; count = 32; ; do { rdser ; if (rdser
// SPI read (byte 3) cpi breq
s_data,0x53 s3
;
ldi
s_data,0x00
;
wrser
rcall wrser pulse_sck ldi s_data,0xac
; ;
pulse SCK wrser
rcall ldi
wrser s_data,0x53
;
wrser
rcall dec brne rjmp
wrser count s1 s3
ldi
s_data,0x00
rcall
wrser
cpi breq ldi
device,S8252 s4 s_data,0x00
rcall
wrser
break; (0x00);
(0xac);
// SPI write (byte 4)
(0x53);
// SPI write (byte 1)
// SPI write (byte 2) } while(--count);
; } ; else ; { ;
wrser
s2:
;
(0x00);
// SPI write (byte 3) s3:
; } ; if (device != S8252) ; { ; wrser(0x00);
//
SPI write (byte 4) s4: ldi rcall ret
temp1,0x10 delay
; } ; delay(0x10);
; *************************************************************************** ;* ;* FUNCTION ;* show_id ;* ;* DESCRIPTION ;* Show our ID ("AVR ISP") on the serial line. ;* ; *************************************************************************** show_id:ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ret
u_data,0x41 putc u_data,0x56 putc u_data,0x52 putc u_data,0x20 putc u_data,0x49 putc u_data,0x53 putc u_data,0x50 putc
; 'A' ; 'V' ; 'R' ; ' ' ; 'I' ; 'S' ; 'P'
; *************************************************************************** ;* ;* RESET ;* ;* DESCRIPTION ;* Initialization ;* ; *************************************************************************** RESET: clr temp1 out GIMSK,temp1 ser temp1 out PORTD,temp1 set_reset out PORTB,temp1 ddrb_release rcall u_init sei
; disable external interrupt ; Initialize ; set RESET=1
; Initialize UART ; Enable interrupts
; *************************************************************************** ;* ;* PROGRAM ;* waitcmd -> main ;* ;* DESCRIPTION ;* Wait for and execute commands. ;* ; *************************************************************************** waitcmd:rcall
getc
; while (getc() ==
ESC) {}; cpi breq
u_data,0x1b waitcmd
;**** Device Type **** cpi brne rcall mov rjmp
u_data,0x54 w0 getc device,u_data put_ret
; 'T' Device type ; getc(); // dummy ; putc(device);
;**** Return Software Identifier **** w0: cpi
u_data,0x53
; 'S' Return software
w1 show_id waitcmd
; show_id();
identifier brne rcall rjmp
;**** Return Software Version **** w1: cpi brne ldi rcall ldi rcall rjmp
u_data,0x56 ;'V' Return software version w2 u_data,0x30+SW_MAJOR ; putc(0x30+SW_MAJOR); putc u_data,0x30+SW_MINOR ; putc(0x30+SW_MINOR); putc waitcmd
;**** Return Hardware Version **** w2: cpi brne ldi rcall ldi rcall rjmp
u_data,0x76 ;'v' Return hardware version w3 u_data,0x30+HW_MAJOR ; putc(0x30+HW_MAJOR); putc u_data,0x30+HW_MINOR ; putc(0x30+HW_MINOR); putc waitcmd
;**** Show Supported Devices **** w3: cpi brne ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi
u_data,0x74 w4 u_data,S1200C putc u_data,S1200D putc u_data,S2313A putc u_data,S4414A putc u_data,S8515A putc u_data,S2323A putc u_data,S8252 putc u_data,0x00
; 't' Show supported devices ; putc(S1200C); ; putc(S1200D); ; putc(S2313A); ; putc(S4414A); ; putc(S8515A); ; putc(S2323A); ; putc(S8252); ; putc(0x00);
// end of
device list rcall rjmp
putc waitcmd
;**** Return Programmer Type **** w4: cpi brne ldi
u_data,0x70 w5 u_data,0x53
; 'p' Return programmer type ; putc('S');
// serial
programmer rcall rjmp
putc waitcmd
;**** Set LED **** w5: cpi brne rjmp
u_data,0x78 w6 put_ret
; 'x' Set LED (ignored)
;**** Clear LED **** w6: cpi brne rjmp
u_data,0x79 w7 put_ret
; 'y' Clear LED (ignored)
;**** Enter Programming Mode **** ; We require that the device code be selected before any of the other commands w7: cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq rjmp w72:
device,S1200C w72 device,S1200D w72 device,S8515A w72 device,S4414A w72 device,S2313A w72 device,S8252 w72 device,S01838C w72 device,S01838D w72 device,S2323A w72 put_err cpi
; if ((device != S1200C) && ;
(device != S1200D) &&
;
(device != S8515A) &&
;
(device != S4414A) &&
;
(device != S2313A) &&
;
(device != S8252) &&
;
(device != S01838C) &&
;
(device != S01838D) &&
;
(device != S2323A))
;
goto put_err();
u_data,0x50
; 'P' Enter
programming mode brne rcall rjmp
w8 spiinit put_ret
; spiinit();
;**** Wait Program Memory **** ;* USAGE ;* wait_pm(byte cmd, byte c_data); ;* ;* cmd : 0x28 - wait for high byte written ;* 0x20 - wait for low byte written ;* u_data : current data written ;wait_pm: ; ; mov (cmd); // SPI write (byte 1) ; rcall ; mov (addrh); // SPI write (byte 2) ; rcall ; mov (addrl); // SPI write (byte 3) ; rcall ; rcall (); // SPI read (byte 4) ; ; ;
cp brne ret
s_data,cmd
; do ; { ;
wrser
wrser s_data,addrh
;
wrser
wrser s_data,addrl
;
wrser
wrser rdser
;
s_data = rdser
s_data,u_data wait_pm
; } ; while(s_data != u_data);
;**** Write Program Memory, High Byte **** w8: cpi
u_data,0x43
; 'C' Write program memory,
high byte brne rcall cpi brne rjmp
w9 getc device,S8252 w81 put_err
; if (device == S8252) ; { ; goto err(); ; // (AT89 series
have byte wide program memory !)
(0x48);
w81: // SPI write (byte 1)
ldi
; } s_data,0x48
; wrser
rcall mov
wrser s_data,addrh
; wrser(addrh);
//
rcall mov
wrser s_data,addrl
; wrser(addrl);
//
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
SPI write (byte 2)
SPI write (byte 3)
C! brne com w81b: mov
w81b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq
w82 device,S01838D w82
ldi
temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
ldi
temp1,0x01
; Auto increment
clr add adc rjmp
temp2 addrl,temp1 addrh,temp2 put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w82: address
!!!!
;**** Write Program Memory, Low Byte **** w9: cpi
u_data,0x63
; 'c' Write program memory,
low byte brne rcall
w12 getc
cpi breq ldi
device,S8252 w989 s_data,0x40
rcall mov rjmp
wrser s_data,addrh w91
; if (device != S8252) ; { ; wrser(0x40);
//
SPI write (byte 1)
w989: mov
s_data,addrh
; ; } ; else
s_data = addrh;
;
; { s_data = (addrh <<
3) | 0x02; rcall ori
shift_s_data3 s_data,0x02
w91: rcall
wrser
; } ; wrser(s_data);
mov
s_data,addrl
; wrser(addrl);
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
// //
SPI write (byte 2) SPI write (byte 3)
C! brne com w91b: mov
w91b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq ldi
w92 device,S01838D w92 temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w92: rjmp
;**** Read Program Memory **** w12:
cpi
u_data,0x52
; 'R' Read program
memory brne cpi breq ldi
w10 device,S8252 w1289 s_data,0x28
rcall mov rjmp
wrser s_data,addrh w121
; ; if (device != S8252) ; { ; wrser(0x28);
//
SPI write (byte 1)
w1289: mov
s_data,addrh
; ; } ; else
s_data = addrh;
;
; { s_data = (addrh <<
3) | 0x01; rcall ori w121: rcall
shift_s_data3 s_data,0x01 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall cpi brne rjmp
u_data,s_data putc device,S8252 w122 waitcmd
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
s_data,0x20
if (device == S8252) { goto waitcmd(); } else ; { ; wrser(0x20); //
rcall mov
wrser s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall rcall
wrser rdser
;
putc(rdser());
//
mov rcall
u_data,s_data putc
ldi
temp1,0x01
;
Auto increment
clr add adc
temp2 addrl,temp1 addrh,temp2
rjmp
waitcmd
; ; }
goto waitcmd();
w122: ldi
; ; ; ; ;
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
Send data (byte 4)
address
!!!!
shift_s_data3: lsl s_data lsl s_data lsl s_data ret ;**** Load Address **** w10: brne rcall mov rcall mov rjmp
cpi u_data,0x41 ; 'A' Load address w11 getc ; addrh = getc(); addrh,u_data getc ; addrl = getc(); addrl,u_data put_ret ; goto reply();
;**** Write Data Memory **** w11:
cpi
u_data,0x44
; 'D' Write data
memory brne rcall cpi breq
w13 getc device,S8252 w1189
ldi rcall mov rjmp
s_data,0xc0 wrser s_data,addrh w111
w1189: rcall ori
mov s_data,addrh shift_s_data3 s_data,0x06
w111: mov rcall mov rcall ldi rcall rjmp
rcall wrser s_data,addrl wrser s_data,u_data wrser temp1,0x20 delay put_ret
;;**** Read Data Memory **** w13:
cpi
u_data,0x64
; 'd' Read data
memory brne cpi breq ldi
w14 device,S8252 w1389 s_data,0xa0
rcall mov rjmp
wrser s_data,addrh w131
; if (device != S8252) ; { ; wrser(0xA0);
//
SPI write (byte 1)
w1389: mov
s_data,addrh
; ; } ; else
s_data = addrh;
;
; { s_data = (addrh <<
3) | 0x05; rcall ori w131: rcall
shift_s_data3 s_data,0x05 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall rjmp
u_data,s_data putc waitcmd
; goto waitcmd();
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
;**** Leave Programming Mode **** w14:
cpi
u_data,0x4c
; 'L' Leave
programming mode brne w15 ddrb_release cpi device,S8252 breq w141 set_reset rjmp put_ret w141: clr_reset rjmp put_ret
; set RESET = 1 ; set RESET = 0
;**** Chip Erase **** w15:
cpi
u_data,0x65 brne w16 ldi s_data,0xac rcall wrser cpi device,S8252 breq w1589 ldi s_data,0x80 rcall wrser w1589: ldi s_data,0x04 rcall wrser ldi s_data,0x00 rcall wrser ldi temp1,0x30 rcall delay rjmp put_ret
; 'e' Chip erase
;**** Write Lock Bits **** w16:
cpi
u_data,0x6c
; 'l' Write lock
bits brne rcall ldi rcall mov cpi breq andi ori rcall ldi rcall rjmp w1689: ori rcall w162: rcall ldi rcall rjmp
w17 getc s_data,0xac wrser s_data,u_data device,S8252 w1689 s_data,0x06 s_data,0xe0 wrser s_data,0x00 wrser w162 andi s_data,0xe0 s_data,0x07 wrser ldi s_data,0x00 wrser temp1,0x30 delay put_ret
;**** Read Signature Bytes **** w17:
cpi
u_data,0x73
brne cpi brne rjmp w17begin: ldi rcall ldi rcall ldi rcall rjmp
w18 device,S8252 w17begin put_err
w17call:ldi rcall ldi rcall mov rcall rcall mov rcall ret
s_data,0x30 wrser s_data,0x00 wrser s_data,param1 wrser rdser u_data,s_data putc
; 's' Read
signature bytes
param1,0x02 w17call param1,0x01 w17call param1,0x00 w17call waitcmd
;**** Write Program Memory Page **** w18:
cpi
u_data,0x6D
; 'm' Write Program
Memory Page brne
w19
ldi
s_data,0x4c
rcall
wrser
mov
;
wrser(0x4c);
//
s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall
wrser
ldi
s_data,0x00
;
wrser(0x00);
//
rcall ldi
wrser temp1,0xff
;
delay(0xFF);
//
rcall rjmp
delay put_ret
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
SPI write (byte 4)
0x20 = 24585 cycles delay
;**** Universal Command **** w19:
cpi
u_data,0x3A
; ':' Universal
Command brne
w99
rcall mov rcall mov rcall mov rcall ldi
getc cmd1,u_data getc cmd2,u_data getc cmd3,u_data universal temp1,0xff
rcall rjmp
delay put_ret
;
delay(0xFF);
//
0x20 = 24585 cycles delay
universal: mov rcall mov rcall mov rcall rcall mov rcall ret
s_data,cmd1 wrser s_data,cmd2 wrser s_data,cmd3 wrser rdser u_data,s_data putc
w99: ;**** Command Error **** put_err:ldi u_data,0x3f rcall putc rjmp waitcmd
; putc('?');
\\ send '?'
; putc(0x0D);
\\ send CR
;**** Reply Command **** put_ret:ldi u_data,0x0d rcall putc rjmp waitcmd ;**** End of File ****
http://avr-asm.tripod.com/avrisp.html (1 of 2)1/20/2009 8:57:59 PM
16 BIT MATH (AVR 202)
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avrisp.html (2 of 2)1/20/2009 8:57:59 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ISP FOR 2313 HOME RETRO_DAN ;* ;* Title
ASM FORUM ASM MATH
: AVR ISP (Auto adr inc, 115200bps,
supports AVR109 commands) ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3
Version Last updated Target File Author(s)
: 3.7e : Jan 14 2005 : AT90S2313 : avr910_2313_v37e.asm : klaus@mikrocontroller-
MATH 200
projekte.de
MATH 200b
;* last Filename : avr910_2313_V36.asm ;* initial File : avr910_31.asm, Author: [email protected], source: www.mit8.ru/~mars/ ) ;* ;* DESCRIPTION ;* The firmware on all programmers now support a unified protocol for ;* program and data memory programming. The host computer do not need ;* to know if the programmer operates in serial or parallel mode. ;* ;* The following commands are supported. All commands start with a ;* single letter. The programmer returns 13d (carriage return) or the ;* data read after the command is finished. ;* ;* +-------------------+-------------+------+ ;* Commands | Host writes | Host reads | | ;* -------+----------+-------+-------+-----+ | ;* | ID (hex ) | data | data | | Note | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* | Enter programming mode | 'P'(0x50) | | | 13d | 1 | ;* | Report autoincrement address | 'a'(0x61) | | | 'Y' | | ;* | Set address | 'A'(0x41) | ah al | | 13d | 2 | ;* | Write program memory, low byte | 'c'(0x63) | dd | | 13d | 3 | ;* | Write program memory, high byte | 'C'(0x43) | dd | | 13d | 3 | ;* | Issue Page Write | 'm'(0x6d) | | | 13d | 13 | ;* | Read program memory | 'R'(0x52) | | dd(dd)| | 4 | ;* | Write data memory | 'D'(0x44) | dd | | 13d | | ;* | Read data memory | 'd'(0x64) | | dd | | | ;* | Chip erase | 'e'(0x65) | | | 13d | | ;* | Write lock bits | 'l'(0x6c) | dd | | 13d | | ;* | Leave programming mode | 'L'(0x4c) | | | 13d | 5 | ;* | Select device type | 'T'(0x54) | dd | | 13d | 6 | ;* | Read signature bytes | 's'(0x73) | | 3*dd | | | ;* | Return supported device codes | 't'(0x74) | | n*dd | 00d | 7 | ;* | Return software identifier | 'S'(0x53) | | s[7] | | 8 | ;* | Return sofware version | 'V'(0x56) | | dd dd | | 9 | ;* | Return hardware version | 'v'(0x76) | | dd dd | | 9 | ;* | Return programmer type | 'p'(0x70) | | dd | | 10 | ;* | Set LED | 'x'(0x78) | dd | | 13d | 12 | ;* | Clear LED | 'y'(0x79) | dd | | 13d | 12 | ;* | Universial command | ':'(0x3a) | 3*dd | dd | 13d | 15 | ;* | New universal command | '.'(0x2E) | 4*dd | dd | 13d | 15 | ;* |-----------------------------------+----------+-------+-------+-----+------| ;* | New Commands since Version 3.3 | | | | | | ;* | Exit (AVR109, Bootloader) | 'E'(0x45) | | | 13d | 15 | ;* | Return Chip ID (Terminalmode only)| 'i'(0x69) | | s[n] | | 14 | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* | New Commands since Version 3.5 | | | | | | ;* | Implemented Atmel Bootloader commands (Atmel Appl. Note 109) | | | ;* | Report Block write Mode | 'b'(0x62) | |'Y'2*nn| 13d | 16 | ;* | Block Write | 'B'(0x42) | 2*nn'M'| n*dd | 13d | 16 | ;* | Block Read | 'g'(0x67) | 2*nn'M'| n*dd | 13d | 16 | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* | Commands to test (Since V3.6, (Unverified) | | | | | ;* | Return Lockbits | 'r'(0x72) | | dd | 13d | 17 | ;* | Return High Fusebits | 'N'(0x4E) | | dd | 13d | 17 | ;* | Return extendet Fusebits | 'Q'(0x51) | | dd | 13d | 17 | ;* | Write fuse bits (reserved) | 'f'(0x66) | dd | | 13d | 11 | ;* | Read fuse and lock bits (reserved)| 'F'(0x46) | | dd | | 11 | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* ;* NOTE 1 ;* The Enter programming mode command MUST be sent one time prior to ;* the other commands, with the exception of the 't', 'S', 'V', 'v' ;* and 'T' commands. The 'T' command must be sent before this command ;* (see note 6). ;* ;* For programmers supporting both parallel and serial programming ;* mode this command enters parallel programming mode. For programmers ;* supporting only serial programming mode, this command enters serial ;* programming mode. ;* ;* NOTE 2 ;* The ah and al are the high and low order bytes of the address. For ;* parallel programmers this command issues the Load Address Low/High ;* Byte command. For serial programmers the address byte is stored for ;* use by the Read/Write commands. ;* ;* NOTE 3 ;* For parallel programmers this command issues the Program Flash ;* command. For serial programmers this command iussues the Write ;* Program Memory Command. For devices with byte-wide program memories ;* only the low byte command should be used. ;* ;* NOTE 4 ;* The contents of the program memory at the address given by the 'A' ;* command are written to the serial port in binary form. For byte ;* wide memories one byte is written. For 16 bit memories two bytes ;* are written,MSB first. ;* ;* NOTE 5 ;* This command must be executed after the programming is finished. ;* ;* NOTE 6 ;* The select device type command must be sent before the enter ;* programming command ;* ;* NOTE 7 ;* The supported device codes are returned in binary form terminated ;* by 0x00. ;* ;* NOTE 8 ;* This return a 7 character ASCII string identifying the programmer. ;* For the development board it is "AVR DEV", for the parallel ;* programmer it is "AVR PPR" and for the in-curcuit programmer it is ;* "AVR ISP". ;* ;* NOTE 9 ;* The software/hardware version are returned as two ASCII numbers. ;* ;* NOTE 10 ;* This command should be used to identify the programmer type. The ;* return value is 'S' for serial (or SPI) programmers or 'P' for ;* parallel programmers. ;* ;* NOTE 11 ;* The write fuse bits command are available only on parallel ;* programmers and only for AVR devices (device code < 0x80). The host ;* should use the return programmer type command to determine the ;* programmer type, do not use the "AVR PPR" idenifier because other ;* programmers may be available in the future. ;* ;* NOTE 12 ;* Currently only the AVR development board has LEDs. The other boards ;* must implement this commands as NOPs. ;* ;* NOTE 13 ;* Devices using Page Mode Programming write one page of flash memory ;* before issuing a Page Mode Write Pulse. ;* ;* NOTE 14 ;* The 'i' command is only used with a Terminal, for debug reasons. ;* Not used in any Programmer so far ;* ;* NOTE 15 ;* Lock and Fuse Bits are written using the "universal command" (:) and ;* "new universal command" (.) in AVRProg and AVRDUDE. ;* AVRProg has an Exit (E) command implemented, which switches AVRProg offline ;* ;* NOTE 16 ;* Atmel Bootloader commands described in Atmel Application Note 109 implemented. ;* Very useful if you use USB to serial converter. ;* AVRProg since Version 1.33 checks if Programmer supports Block Mode, ;* IF Programmer responds 'Y' and the size of the internal Buffer (nn nn), Bootloader commands ;* are used automatically from AVRProg. (faster Protocoll) ;* Block commands send size Buffersize (nn nn) and Type of Memory ('F'=Flash, 'E'=Data) ;* Compatibility to AVR Butterfly command set and Bootloader. Works with AVR911 Open Source ;* Programmer. ;* For avrdude use -c butterfly instead of -c avr910 and you get same behaviour. ;* ;* NOTE 17 ;* Commands implemented but not tested yet. ;* ;* NOTE 18 ;* Device 89S8252 was tested to programm with avrprog. Shows a avrprog bug in "block Mode". Works in "standart" ;* avr910 Programming Mode. To program this Device, disable the "Block Mode" by changing "w53: rjmp w6" ;* ;* HISTORY ;* V3.7e 11.01.05 (Klaus) Matched Devicecodes to the new Atmel AVRProgV1.40 ;* V3.7d 05.01.05 (Klaus) Removed 1200A/B/C devicecodes, Polling 0x7F for AT90S4414, default PollcodeF = 0xFF ;* V3.7c 04.01.05 (Klaus/Micha) Some devicecodes changed (Bootloader and "default" mode). ;* V3.7b 03.01.05 (Klaus/Leo) Bugfix for Block read of Flash Mamory for AT89Snnnn Controllers. ;* V3.7a 29.12.04 (Klaus/Micha) addet devicecodes for m64, m162 and m169. ;* V3.7 15.12.04 (Klaus) Rewriting polled timing for "non Page Mode" Chips, reorganised Table for ;* different polling Codes. Skip 0xFF Byte polling. (was buggy for some Controllers) ;* Added ATTiny2313 (device Code 0x23), and ATMega8535 (0x6A)Support. ;* Not Supported from avrprog, avrdude Support possible. ;* Reorganised Table for Page Mode Chips with Pagesize. Adding different Pagesizes ;* Try to fix S89 write, BUG in avrprog detected. Firmware should be OK now. (NOTE 18) ;* After 256 unsuccesful polls for Flash wait additional standart time. ;* Modified "release_ports" so that RESET is released also. ;* V3.6 10.07.04 (Klaus) Changed Block Mode Commands to AVR109 compatibility. ;* Additional AVR109 Commands, not testet yet. ;* V3.4-V3.5 unreleased (Klaus) cleaning up, tests for Block Modes ;* V3.3 25.06.04 (Klaus, Thomas) added enhanced Block write commands ; with own Protocol. ; Add 0xFF, 0x7F (2313) check for polling Mode ;* V3.2.1 18.11.03 (Klaus) Commented out some Controller Types, which are ; not really Supported by the hardware, but from ; AVRProg Software. See Comments at the end. ;* V3.2 16.11.03 (Klaus) Correctet typo in Chrystal frequency. ;* V3.2 13.10.03 (Klaus) 7,3728 Mhz chrystal for 115.200 Baud. ;* Swap MOSI <> MISO Pinnumbers. ;* Add dual color LED Support. ;* Add some new Dewices. ;* V3.0 02.01.23 (wubble) Ported from 1200 to 2313. ;* Serial IO modified to use hardware UART. ;* Added support for multiple new devices. ;* Used data polling to short write process. ;* Added LED support to indicate R/W process. ;* V2.2 00.03.10 (pkastnes) Added support for multiple new devices. ;* V2.1 98.10.26 (mlund) New date marking. ;* Removed support for AT90S1200C. ;* Added support for AT90S4433A. ;* V2.0 98.01.06 (mlund) ATmega103 support. ;* V1.7 97.11.06 (mlund) Universial command (':') implemented. ;* Releases all pins when not in ;* programming mode. ;* V1.6e 97.11.04 (mlund) mega103 rev D support ;* V1.6c 97.10.30 (mlund) Auto incrementing / SPI sync ;* also works for mega103. ;* V1.6 97.09.09 (hskar) Created Page Mode Version (mega103) ;* V1.5 97.08.21 (mlund) Modified / Bugfix / Major cleanup ;* ... ... (no records) ;* V?.? 97.03.15 (OS) Created ;* ;* ;* Device Support List: see table "Devices" at the end of this file.
MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;**** includes **** .include "2313def.inc" ; *************************************************************************** ;* ;* CONSTANTES ;* ; *************************************************************************** ;**** Constant declarations Data Rate **** ;******** Chrystals for maximum Baudrates .equ XTAL = 7373
; XTAL
frequency, Khz (7.3728 Mhz) ;******** .equ .equ
BAUD = 115200 N = 3
; Data rate, bauds ; for
;******** ;.equ ;.equ
BAUD = 38400 N = 11
; Data rate, bauds ; for
7.3728 Mhz/115.200Baud
7.3728 Mhz/38400Baud ;******** ;**** definitions for different chrystals and 115.200 baud **** ;.equ
XTAL = 3686
;********* ;.equ ;.equ
BAUD = 115200 N = 1
; XTAL
frequency, Khz (3.6864 Mhz) ; Data rate, bauds ; for
3.6864 Mhz/115.200Baud ;********* ; ;********* Baudrates for 8 Mhz Chrystal ;.equ XTAL = 8000
; XTAL
frequency, Khz (8.000 Mhz) ;********* ;.equ ;.equ
BAUD = 38400 N = 12
; Data rate, bauds ; for 8.00
;********* ;.equ ;.equ
BAUD = 19200 N = 25
;Data rate, bauds ; for 8.00
Mhz/38.400 Baud
Mhz/19.200 Baud ;********* ;.equ BAUD = 9600 rate, bauds ! Not valid for AVRProg, use for avrdude only ! ;.equ N = 51 Mhz/9.600 Baud ;*********
; Data ; for 8.00
;********* Baudrates for 4 Mhz Chrystal ;.equ XTAL = 4000
; XTAL
frequency, Khz (4.000 Mhz) ;********* ;.equ ;.equ
BAUD = 19200 N = 12
; Data rate, bauds ; for 4.00
Mhz/19.200 Baud ;********* ;.equ BAUD = 9600 rate, bauds ! Not valid for AVRProg, use for avrdude only ! ;.equ N = 25 Mhz/9.600 Baud ;*********
; Data ; for 4.00
.equ RAMSTART = 0x60
; first SRAM Adress
.equ PAGESIZE = 0x10
; default Page size
.equ BUFSIZE
; 64 bytes internal
of 2313 for Programming = 0x40
RAM for Buffer ; *************************************************************************** ;* ;* PORTS ;* Ports Definitions ;* ;* DESCRIPTION ;* Change the following definitions if the RESET pin to the ;* target moves and/or if the SCK/MISO/MISO/LED moves. ;* ; *************************************************************************** .equ
LEDH
= PB3
; dual color LED
.equ active low, dual color LED Kathode green .equ target (input) .equ target (output)
LED (output) MISO
= PB0
; LED output,
= PB6
; MISO
pin of the
MOSI
= PB5
; MOSI
pin of the
.equ
RESET
= PB4
; RESET pin of the
.equ
SCK
= PB7
; SCK
.equ .equ
RXD TXD
= PD0 = PD1
; UART RXD line ; UART TXD line
output, anode green
(output)
target (output) pin of the
target (output)
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following macros if the RESET pin to the ;* target moves and/or if the SCK/MISO/MISO/LED moves. ;* ; *************************************************************************** .macro ldi out ldi out .endm
init_ports temp2,0xff PORTD,temp2 temp2,0xff PORTB,temp2
; init ports
.macro
catch_ports
; catch
ports ldi temp2,(1<<TXD) out DDRD,temp2 ldi temp2,(1<<RESET) | (1<<MOSI) | (1<<SCK) | (1<<LED) | (1<<LEDH) out DDRB,temp2 .endm .macro ldi out ldi out .endm
release_ports ; release ports temp2,(1<<TXD) DDRD,temp2 temp2,(1<<LED) | (1<<LEDH) DDRB,temp2
.macro
pas_RESET
tst brmi sbi rjmp m2: cbi m3: .endm
device m2 PORTB,RESET m3 PORTB,RESET
.macro
act_RESET
tst brmi cbi rjmp m4: sbi m5: .endm
device m4 PORTB,RESET m5 PORTB,RESET
; set RESET
passive ; S89 device
; set RESET
active ; S89 device
.macro set_LED Port -> Standart LED off, dual LED green sbi PORTB,LED cbi PORTB,LEDH color support .endm
; set LED
; added for dual
.macro clr_LED Port --> Standart LED on, dual LED red cbi PORTB,LED sbi PORTB,LEDH color support .endm
; clear LED
; added for dual
.macro LED_off
; for dual
color LED, not in use cbi PORTB,LED cbi PORTB,LEDH .endm .macro
sbic_MISO
; skip if
sbic .endm
PINB,MISO
.macro sbi .endm
set_MOSI PORTB,MOSI
; set MOSI
.macro cbi .endm
clr_MOSI PORTB,MOSI
; clear MOSI
.macro cbi .endm
clr_SCK PORTB,SCK
; clear SCK
MISO cleared
.macro pulse_SCK sbi PORTB,SCK ldi temp2,(XTAL/750+1) for ATTiny2313 (internal clock) default was (XTAL/1500+1) m0: dec temp2 brne m0 cbi PORTB,SCK ldi temp2,(XTAL/1500+1) for ATTiny2313 (internal clock) default was (XTAL/3000+1) m1: dec temp2 brne m1 .endm .macro
table
ldi ldi .endm
ZL,low(@0*2) ZH,high(@0*2)
; pulse SCK ; had to slow down
; had to slow down
; load Z
pointer ; low ; high
; *************************************************************************** ;* ;* Global Register Variables ;* ; *************************************************************************** ;r0 used with lpm instruction .def cmd1 = r1
; Universal
.def .def .def
cmd2 cmd3 pol_al
= r2 = r3 = r4
; .. ; .. ; Polling address
.def
pol_ah
= r5
; Polling address
.def
Bcnt1
= r6
; Block Mode
.def
Bcnt2
= r7
; Block Mode
.def
Bcnt3
= r8
; Block Mode
commands params
low high Counter1 Counter2 Counter2 .def
B_Flag
= r9
; Flag for ws_del
.def
B_Mode
= r10
; Marks Block Mode
= r11
; Flag for
= r12
; Size of
= r13
; Code for Polling
Routine commands (See Note 16) .def Memtype Memorytype for Block Commands (See Note 16) .def Pagewords Controller page to program in Page Mode (Words!) .def PollcodeF Flash .def
temp1
= r16
; Temporary
.def
temp2
= r17
; Temporary
.def
temp3
= r18
; Temporary
.def .def .def .def
s_data u_data device param1
= = = =
; ; ; ;
register 1 register 2 register 3 r19 r20 r21 r22
SPI data UART data Device code Param to read
signature .def rd_s_data .def pol_cmd .def p_data ;r26,r27 used as X register .def addrl
= r23 = r24 = r25
; Read data on SPI ; Polling command ; Polling data
= r28
; (YL) Low order
.def
= r29
; (YH) High order
byte of address addrh
byte of address ;r30,r31 used as Z register ; *************************************************************************** ;* ;* Interrupt Vectors ;* ; *************************************************************************** .CSEG rjmp
INIT
; Reset Handle
; *************************************************************************** ;* ;* FUNCTION ;* u_init ;* ;* DESCRIPTION ;* Initialize UART. ;* ; *************************************************************************** u_init: ldi
temp1,N
; set baud
rate out ldi
UBRR,temp1 temp1,(1<<TXEN)|(1<<RXEN) ;
out ret
UCR,temp1
initialize UART for TX and RX
; *************************************************************************** ;* ;* FUNCTION ;* getc ;* ;* DESCRIPTION ;* Wait for start bit and receive a character on the UART Rx line. ;* ; *************************************************************************** getc: sbis
USR,RXC
; wait until a
character has been received rjmp in
getc u_data,UDR
; Read byte
from the UART ret ; *************************************************************************** ;* ;* FUNCTION ;* putc ;* ;* DESCRIPTION ;* Send a character on the UART Tx line. ;* ; *************************************************************************** putc: sbis
USR,UDRE
; test for TX
rjmp
putc
; loop until TX
out
UDR,u_data
register empty empty ; send the
byte ret ; *************************************************************************** ;* ;* FUNCTION ;* put_string ;* ;* DESCRIPTION ;* Send Z - pointed null-terminated string on the UART Tx line. ;* ; *************************************************************************** put_string: lpm tst r0 breq ps_ret
; check for end of
string (0x00) mov rcall adiw rjmp ps_ret:
u_data,r0 putc ZL,1 put_string ret
; putc(char) ; next char
; *************************************************************************** ;* ;* FUNCTION ;* put_table ;* ;* DESCRIPTION ;* Send Z - pointed table on the UART Tx line. ;* ; *************************************************************************** put_table: lpm tst breq
r0 pt_ret
mov rcall adiw rjmp pt_ret:
u_data,r0 putc ZL,2 put_table ret
; check for end of
table (0x00) ; putc(Byte) ; skip MSB
; *************************************************************************** ;* ;* FUNCTION ;* bel_table ;* ;* DESCRIPTION ;* C=0 if device belongs to table. ;* ; *************************************************************************** bel_table: lpm
;
read table tst
r0
;
check for end of table breq cp breq adiw rjmp c1_ret:
c1_ret device,r0 c0_ret ZL,2 bel_table sec
c0_ret:
ret
; C=0 ; skip MSB ;
C=1
; *************************************************************************** ;* ;* FUNCTION ;* set_pagesize ;* ;* DESCRIPTION ;* sets programming Page size for selected Device. ;* ; *************************************************************************** set_pagesize: lpm tst r0
; read table ; check for end of
table breq cp breq adiw rjmp spa_set: adiw
spa_end device,r0 spa_set ZL,2 set_pagesize
; no Pagesize to set
ZL,1
; Point to high
; C=0 ; skip MSB
Byte of Word lpm mov Pagewords,r0 mov Bcnt3,Pagewords spa_end: ret
; get Pagesize to R0 ; initiate Counter
; *************************************************************************** ;* ;* FUNCTION ;* set_pollcode ;* ;* DESCRIPTION ;* sets Code for Polling Flash for selected Device. ;* ; *************************************************************************** set_pollcode: lpm tst r0
; read table ; check for end of
table breq cp breq adiw rjmp spo_set: adiw
spo_end device,r0 spo_set ZL,2 set_pollcode
; no Pollcode to set
ZL,1
; Point to high
; C=0 ; skip MSB
Byte of Word lpm mov PollcodeF,r0
; get Pagesize to R0 ; Set Pollcode for
Flash Rom spo_end: ret ; *************************************************************************** ;* ;* FUNCTION ;* delay ;* ;* DESCRIPTION ;* Make delay 1mS (x temp1). ;* ; *************************************************************************** delay: ldi dl2: dl1: brne dec brne dec brne ret
temp2,40 ldi temp3,(XTAL/120) dec temp3 dl1 temp2 dl2 temp1 delay
; *************************************************************************** ;* ;* FUNCTION ;* spi123 ;* ;* DESCRIPTION ;* Write bytes 1 to 3 on the SPI. Byte 1 must be loadet into s_data ;* Byte 2 ist addrh, Byte 3 ist addrl ;* ; *************************************************************************** spi123: rcall
wrser
; wrser(s_data) SPI
mov rcall
s_data,addrh wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
write (byte 1)
write (byte 2)
write (byte 3) ret ; *************************************************************************** ;* ;* FUNCTION ;* w1234 (for Code simplification, not used yet) ;* ;* DESCRIPTION ;* Write SPI bytes 1 to 4. ; Byte 1 must be loadet into cmd1 ; Byte 2 must be loadet into cmd2 ; Byte 3 must be loadet into cmd3 ; Byte 4 must be loadet into u_data ;* ; *************************************************************************** w1234: mov s_data,cmd1 rcall wrser mov s_data,cmd2 rcall wrser mov s_data,cmd3 rcall wrser mov s_data,u_data rcall wrser ret ; *************************************************************************** ;*
http://avr-asm.tripod.com/isp2313.html (1 of 4)1/20/2009 8:58:51 PM
16 BIT MATH (AVR 202)
;* FUNCTION ;* w123r4 (for Code simplification, not used yet) ;* ;* DESCRIPTION ;* Write SPI bytes 1 to 3, read Byte 4 to serial. ; Byte 1 must be loadet into cmd1 ; Byte 2 must be loadet into cmd2 ; Byte 3 must be loadet into cmd3 ;* ; *************************************************************************** w123r4: mov s_data,cmd1 rcall wrser mov s_data,cmd2 rcall wrser mov s_data,cmd3 rcall wrser rcall rdser mov u_data,s_data rcall wrser ; get Byte 4 from serial rcall putc ret
; *************************************************************************** ;* ;* FUNCTION ;* rdser, wrser ;* ;* DESCRIPTION ;* Write and read bytes on the SPI. ;* ; *************************************************************************** rdser: clr s_data wrser: ldi temp1,8 ldi rd_s_data,0 wrs0: rol s_data brcc wrs1 set_MOSI rjmp wrs2 wrs1: clr_MOSI wrs2: lsl rd_s_data sbic_MISO ori rd_s_data,1 pulse_SCK dec temp1
; load bit counter
; MOSI = 1
; MOSI = 0
; read MISO ; pulse SCK ; advance bit
counter brne mov ret
wrs0 s_data,rd_s_data
; loop
; *************************************************************************** ;* ;* FUNCTION ;* read_send_progmem ;* ;* DESCRIPTION ;* Read one adress (2 Byte) from Program Memory and send it through UART ;* ; *************************************************************************** read_send_progmem: tst device brmi rsp1 ; S89 device ldi s_data,0x20 ; read low Byte rcall wrser ; wrser(0x28) SPI write (byte 1) mov s_data,addrh rjmp rsp2 rsp1: mov s_data,addrh ; s_data = (addrh << 3) | 0x01; rcall shift_s_data3 ori s_data,0x01 rsp2: rcall wrser ; wrser(addrh) SPI write (byte 2) (S89=byte1) mov s_data,addrl rcall wrser ; wrser(addrl) SPI write (byte 3) rcall rdser ; SPI read (byte 4) mov u_data,s_data rcall putc ; send data tst device brmi rsp3 ; S89 device ldi s_data,0x28 ; read High Byte rcall wrser ; wrser(0x20) SPI write (byte 1) mov s_data,addrh rcall wrser ; wrser(addrh) SPI write (byte 2) mov s_data,addrl rcall wrser ; wrser(addrl) SPI write (byte 3) rcall rdser ; SPI read (byte 4) mov u_data,s_data rcall putc ; send data rsp3: adiw addrl,1 ; Auto increment address ret ; *************************************************************************** ;* ;* FUNCTION ;* read_send_datamem ;* ;* DESCRIPTION ;* Read one Byte from Data Memory (eeprom) and send it through UART ;* ; *************************************************************************** read_send_datamem: ; Subroutine to read one eeprom Address tst device brmi rsd1 ; S89 device ldi s_data,0xa0 rcall wrser ; wrser(0xa0) SPI write (byte 1) mov s_data,addrh rjmp rsd2 rsd1: cpi device,0x87 ; if (device == S53) breq rsd3 ; no Support for 89S53 device due to Bug in AVRProg V1.37 mov s_data,addrh rcall shift_s_data3 ori s_data,0x05 rsd2: rcall wrser ; wrser(addrh) SPI write (byte 2) mov s_data,addrl rcall wrser ; wrser(addrl) SPI write (byte 3) rcall rdser ; SPI read (byte 4) mov u_data,s_data rcall putc ; send data adiw addrl,1 ; Auto increment address ret rsd3: pop temp1 ; remove return Adress from Stack in case of Error pop temp1 rjmp put_err
; *************************************************************************** ;* ;* FUNCTION ;* eeprom_write ;* ;* DESCRIPTION ;* Write u_data to Data Memory (eeprom) ;* ; *************************************************************************** eeprom_write: tst device brmi eew1 ; S89 device ldi s_data,0xc0 rcall wrser ; wrser(0xc0) write (byte 1) mov s_data,addrh rjmp eew2 eew1: cpi device,0x87 ; if (device == breq eew3 mov s_data,addrh rcall shift_s_data3 ori s_data,0x06 eew2: rcall wrser ; wrser(addrh) write (byte 2) mov s_data,addrl rcall wrser ; wrser(addrl) write (byte 3) mov s_data,u_data rcall wrser ; wrser(u_data) write (byte 4) ldi temp1,10 ; delay 10mS rcall delay adiw
addrl,1
SPI
S53)
SPI
SPI
SPI
; Auto increment
address ret eew3: pop temp1
; remove return
Adress from Stack in case of failure pop temp1 rjmp put_err ; *************************************************************************** ;* ;* FUNCTION ;* shift_s_data3 ;* ;* DESCRIPTION ;* Shift s_data 3 times left for S89 device. ;* ; *************************************************************************** shift_s_data3: lsl s_data lsl s_data lsl s_data brcc s3_ret cpi device,0x87 brne s3_ret sbr s_data, 4 s3_ret: ret
; if (device != S53) ; a13 +
; *************************************************************************** ;* ;* FUNCTION ;* healthcheck ;* ;* DESCRIPTION ;* changes color of dual color led. ;* ; *************************************************************************** healthcheck:
; for dual
color LED clr_LED ldi temp1,200 rcall delay ldi temp1,200 rcall delay ldi s_data,200
; LED red ; 200 ms ; again 200 ms ; counter Register
LEDloop:
; Pulse for yellow
LED set_LED ldi temp1,2 rcall delay clr_LED ldi temp1,1 rcall delay dec s_data brne LEDloop set_LED ret
; LED green ; 2 ms ; LED red ; 1 ms ; dec. counter ; LED green
; *************************************************************************** ; *************************************************************************** ; *************************************************************************** ;* ;* INIT ;* ;* DESCRIPTION ;* Initialization ;* ; *************************************************************************** ; *************************************************************************** ; *************************************************************************** INIT: ldi temp1,RAMEND out SPL,temp1 ldi temp1,PAGESIZE mov Pagewords,temp1 mov Bcnt3,Pagewords
; Locate stack ; default Pagesize ; set counter for
Pagesize ldi device,0x20 clr B_Mode
; S2313 as default ; Flag for Block
clr B_Flag
; Flag for eNhanced
init_ports release_ports rcall u_init rcall healthcheck
; ; ; ;
Modes (see Note 16) Block write Initialize ports Release ports Initialize UART show that Prog is
working after Powerup (LED test)
; *************************************************************************** ;* ;* PROGRAM ;* waitcmd -> main ;* ;* DESCRIPTION ;* Wait for and execute commands. ;* ; *************************************************************************** waitcmd: rcall
getc
; while (getc() ==
ESC) {}; cpi breq
u_data,0x1b waitcmd
;====== 'T' - Device Type ================================================== cpi u_data,'T' brne w0 rcall getc mov device,u_data table Dev_M
; 'T' Device type
rcall set_pagesize
; If device has
; get device type ; prepare to set
Pagesize Page Mode support, set Pagesize ldi temp1,0xFF mov PollcodeF,temp1 with 0xFF, will be overwritten if Pollcode known table Dev_S Polling Code rcall set_pollcode Page Size support, set code for Polling Flash rjmp put_ret
; preset PollcodeF ; prepare to set ; If device has no
;====== 'S' - Return Software Identifier =================================== w0: cpi
u_data,'S'
; 'S' Return
brne table rcall
w1 ID_Str put_string
; put string "AVR
rjmp
waitcmd
software identifier
ISP"
;====== 'V' - Return Software Version ====================================== w1: cpi
u_data,'V'
; 'V' Return
brne table rcall
w2 SW_Ver put_string
; put software
rjmp
waitcmd
software version
version
;====== 'v' - Return Hardware Version ====================================== w2: cpi
u_data,'v'
; 'v' Return
brne table rcall
w3 HW_Ver put_string
; put hardware
rjmp
waitcmd
hardware version
version
;====== 't' - Show Supported Devices ======================================= w3: cpi
u_data,'t'
; 't' Show
brne table rcall
w4 Dev_S put_table
; put supported
table rcall
Dev_M put_table
; put supported
ldi
u_data,0x00
; putc(0x00) - end
rcall rjmp
putc waitcmd
supported devices
devices codes
devices codes of device list
;====== 'p' - Return Programmer Type ======================================= w4: cpi
u_data,'p'
; 'p' Return
brne ldi
w5 u_data,'S'
; putc('S') -
rcall rjmp
putc waitcmd
programmer type
serial programmer
;====== 'a' - Return autoincrement address support ========================= w5: cpi
u_data,'a'
; 'a' Return
brne ldi
w51 u_data,'Y'
; putc('Y') -
rcall rjmp
putc waitcmd
address auto increment
supports autoinc
;====== 'M' - Return enhanced Mode support (Note 14) ======================== w51: ; cpi
u_data,'M'
; 'M' Return
enhanced mode Support ; ;
brne w52 ldi u_data,'Y'
; ;
rcall putc rjmp waitcmd
; putc('Y') -
supports enhanced Mode
;====== 'i' - Return Chip ID (Note 14) ====================================== w52: cpi brne table rcall
u_data,'i' w53 ChipID put_string
; 'i' Return Chip ID
; put Chip ID
string ldi u_data,0x0a rcall putc rjmp put_ret
; putc(LF)
;====== 'b' - Return Block write Mode support (Note 17) ======================== w53: cpi
u_data,'b'
; 'b' Return
enhanced mode Support brne w6 ldi u_data,'Y'
; putc('Y') -
rcall putc ldi u_data,high(BUFSIZE)
; putc((BUFSIZE>
rcall putc ldi u_data,low(BUFSIZE)
; putc
supports enhanced Mode
>8) & 0xff);
(BUFSIZE&0xff); rcall putc rjmp waitcmd ;====== 'x' - Set LED ====================================================== w6: cpi
u_data,'x'
; 'x' Set LED (LED
off or green) brne w61 rcall getc set_LED rjmp put_ret
; get parameter
;====== 'y' - Clear LED ==================================================== w61: cpi
u_data,'y'
; 'y' Clear LED
(LED on or red) brne w7 rcall getc clr_LED rjmp put_ret
; get parameter
; =========================================================================== ; We require that the device code be selected before any of the other commands w7: table rcall brcc
Dev_S bel_table w71
; load pointer
table rcall brcc
Dev_M bel_table w71
; device belongs to
rjmp
put_err
; not match, goto
; device belongs to
table
table put_err(); ;====== 'P' - Enter Programming Mode ======================================= w71: cpi
u_data,'P'
breq rjmp
w70 w8
; 'P' Enter
programming mode
w70: clr_LED catch_ports clr_SCK pas_RESET ldi temp1,50 rcall delay act_RESET ldi temp1,50 rcall delay ldi s_data,0xac rcall wrser
; ; ; ; ;
LED on catch ports clear SCK set RESET passive delay 50mS;
; set RESET active ; delay 50mS;
; wrser(0xac) SPI
write (byte 1) ldi rcall
s_data,0x53 wrser
; wrser(0x53) SPI
write (byte 2) ; SPI Synchronization (fix!) cpi
device,0x20
; if ( (device >
s2 device s2 temp3,32 rdser s_data,0x53 s3
; ; ; ;
wrser
; wrser(0x00) SPI
= 0x20) && (device <= 0x7F) ) brlo tst brmi ldi s1: rcall cpi breq ldi
count = 32; SPI read (byte 3) if (rdser == 0x53) break
s_data,0x00 rcall write (byte 4) pulse_SCK ldi s_data,0xac rcall wrser
; pulse SCK ; wrser(0xac) SPI
write (byte 1) ldi rcall
s_data,0x53 wrser
dec brne rjmp s2: ldi rcall
temp3 s1 s3 s_data,0x00 wrser
s3: tst brmi ldi rcall
device s4 s_data,0x00 wrser
s4: ldi rcall rjmp
temp1,4 delay put_ret
; wrser(0x53) SPI
write (byte 2) ; count-1 ; loop ; else ; wrser(0x00) SPI
write (byte 3) ; S89 device ; wrser(0x00) SPI
write (byte 4) ; delay 4mS;
;====== 'c' - Write Program Memory, Low Byte =============================== w8: cpi
u_data,'c'
brne rcall mov
w9 getc ldi s_data,0x40 pol_cmd,s_data
tst brmi rcall
device w81 wrser
mov rjmp
s_data,addrh w82
; 'c' Write program
memory, low byte
w8b:
; get data byte ; save command for
polling ; S89 device ; wrser(0x40)
SPI
write (byte 1)
w81: mov
s_data,addrh
rcall ori
shift_s_data3 s_data,0x02
; s_data = (addrh
<< 3) | 0x02;
w82: rcall
wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
mov rcall
s_data,u_data wrser
; wrser(u_data) SPI
mov
p_data,u_data
; save data for
mov
pol_al,addrl
; save address for
mov tst brpl adiw
pol_ah,addrh device w83 addrl,1
; Auto increment
wait_S
; write FLASH delay
write (byte 2)
write (byte 3)
write (byte 4) polling polling
address for S89 device w83: rjmp
;====== 'C' - Write Program Memory, High Byte ============================== w9: cpi
u_data,'C'
; 'C' Write program
brne rcall brmi ldi mov
w92 getc tst device w91 s_data,0x48 pol_cmd,s_data
rcall
wrser
; wrser(0x48)
SPI
mov rcall
s_data,addrh wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
mov
s_data,u_data
; wrser(u_data) SPI
rcall mov
wrser p_data,u_data
; save data for
mov
pol_al,addrl
; save address for
mov adiw
pol_ah,addrh addrl,1
; Auto increment
rjmp
wait_S
; write FLASH delay
put_err
; S89 device have
memory, high byte
w9a:
; get data byte ; S89 device ; save command for
polling write (byte 1)
write (byte 2)
write (byte 3) write (byte 4)
polling polling
address w91: rjmp byte wide program memory! ;====== 'B' Block Write Memory (see Note 17) ====================== w92: cpi
u_data,'B'
; 'B' Block Write
Program Memory breq w92a rjmp w10 w92a: rcall getc
; get count High
tst u_data breq w92b ldi u_data,1 rjmp put_err w92b: rcall getc cpi u_data,BUFSIZE+1
; get count Low Byte ; check maximum
brlo w92c ldi u_data,2 rjmp put_err w92c: mov Bcnt1, u_data
; ignore BUFSIZE
Byte
count
high Byte (must be 0 here) mov Bcnt2, u_data rcall getc
; get Memory type
to write mov Memtype,u_data clr XH ldi XL, RAMSTART
; Flag for Memtype ; set X pointer to
SRAM begin w93: rcall
getc
; get data until
Bcnt1 is reached st X+, u_data dec Bcnt1 brne w93 clr XH ldi XL, RAMSTART
; store data to SRAM
; set X pointer to
SRAM begin ldi temp3,1 mov B_Mode,temp3 mov u_data,Memtype cpi u_data,'F'
; B_Mode != 0 ; restore Memtype ; 'F' Flash Memory
breq cpi
w94a u_data,'E'
; 'E' eeprom Memory
breq
w94
; Entry Point for
ist to write
ist to write Data Memory Block write ldi u_data,3 rjmp put_err w94:
; write
Data Memory ld u_data,X+ rcall eeprom_write dec Bcnt2 brne w94 rjmp put_ret ;Entry Point for Flash Block write w94a: table Dev_M rcall bel_table brcc w95
; device belongs to
table rjmp
w96
; not match, goto
"non Paged" Mode w95:
; Entry
Point for AVRProg Block Flash write ldi s_data,0x40 rcall spi123 ld s_data, X+ rcall wrser
; write low byte
ldi mov
; write high byte ; save command for
; wrser(s_data) SPI
write (byte 4) s_data,0x48 pol_cmd,s_data
polling rcall spi123 ld s_data, X+ mov p_data,s_data
; save data for
mov
pol_al,addrl
; save address for
mov rcall
pol_ah,addrh wrser
; wrser(u_data) SPI
adiw
addrl,1
; Auto increment
polling polling
write (byte 4) address dec Bcnt2 breq w95b dec Bcnt2 breq w95b tst B_Mode breq w95
; Loop for "Block
dec Bcnt3
; count Bytes for
Mode Commands" see Note 16 Pagesize brne w95 w95b: tst B_Mode brne w95c rjmp put_ret w95c: dec Bcnt3
; Bcnt3 will be set
correct after write ldi rcall
s_data,0x4c wrser
; write Memory Page ; wrser(0x4c) SPI
mov
s_data,pol_ah
; last written
rcall
wrser
; wrser(addrh) SPI
mov
s_data,pol_al
; last written
rcall
wrser
; wrser(addrl) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
write (byte 1) Adress is in Page to be programmed! write (byte 2) Adress is in Page to be programmed! write (byte 3) SPI
write (byte 4) mov Bcnt3,Pagewords
; reload Counter
für Pagesize rjmp wait_M
;#@KL4 test for 89S8252 Device w96:
; Non Page
Mode Flash write tst brmi ld
device w96b p_data, X+
; S89 device ; load byte to Poll
cpi
p_data,0xFF
; if (p_data ==
breq ldi mov
w961 s_data,0x40 pol_cmd,s_data
; skip burning ; write low byte ; save command for
data 0xFF)
polling rcall spi123 mov s_data,p_data
; reload data from
rcall
wrser
; wrser(s_data) SPI
mov
pol_al,addrl
; save address for
Poll data write (byte 4) polling mov pol_ah,addrh rcall Bws_pol w961: dec Bcnt2 ld p_data, X+
; load byte to Poll
data cpi
p_data,0xFF
; if (p_data ==
breq ldi mov
w962 s_data,0x48 pol_cmd,s_data
; write high byte ; save command for
0xFF)
polling rcall spi123 mov s_data,p_data
; reload data from
rcall
; wrser(u_data) SPI
Poll data wrser
write (byte 4) w96a:
mov
pol_al,addrl
; save
address for polling mov pol_ah,addrh rcall Bws_pol w962: adiw addrl,1
; Auto increment
address dec Bcnt2 brne w96 rjmp put_ret
; reply
w96b:
; Code for
89S8252 ; ;
ldi mov
s_data,0x40 pol_cmd,s_data
; save command for
mov
s_data,addrh
; s_data = (addrh
rcall ori rcall
shift_s_data3 s_data,0x02 wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
ld mov
s_data, X+ p_data,s_data
; save data for
rcall
wrser
; wrser(u_data) SPI
rjmp
w96a
polling << 3) | 0x02;
write (byte 1)
write (byte 2)
polling write (byte 3)
;====== 'R' - Read Program Memory ========================================== w10: cpi
u_data,'R'
; 'R' Read program
w10B device rpm1 s_data,0x28
; S89 device ; read high
wrser
; wrser(0x28)
memory
Byte (order write (byte
<< 3)
write (byte
write (byte read
(byte
brne tst brmi ldi is different from Block Read!) rcall 1) mov rjmp rpm1: mov | 0x01; rcall ori rpm2: rcall 2) mov rcall 3) rcall 4) mov rcall tst brmi ldi
SPI
s_data,addrh rpm2 s_data,addrh
; s_data = (addrh
shift_s_data3 s_data,0x01 wrser
; wrser(addrh) SPI
s_data,addrl wrser
; wrser(addrl) SPI
rdser
;
u_data,s_data putc device rpm3 s_data,0x20
SPI
; send data ; S89 device ; read Low
Byte rcall
wrser
; wrser(0x20)
SPI
mov rcall
s_data,addrh wrser
; wrser(addrh) SPI
mov rcall
s_data,addrl wrser
; wrser(addrl) SPI
rcall
rdser
;
u_data,s_data putc
; send data
addrl,1
; Auto increment
waitcmd
; goto waitcmd();
write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4) mov rcall rpm3: adiw
address rjmp
;====== 'g' - Block Read Memory (See Note 17) ====================== w10B: cpi
u_data,'g'
; 'g' Block Read
Program Memory brne w11 rcall getc mov XH,u_data rcall getc mov XL,u_data rcall getc cpi u_data,'F' breq w10B2 cpi u_data,'E' breq w10B1 rjmp put_err w10B1: rcall read_send_datamem sbiw XL, 1 brne w10B1 rjmp waitcmd w10B2: rcall read_send_progmem tst device
http://avr-asm.tripod.com/isp2313.html (2 of 4)1/20/2009 8:58:51 PM
; XH = getc(); ; XL = getc(); ; getc(Memorytype);
; goto waitcmd();
16 BIT MATH (AVR 202)
brmi sbiw brne rjmp w10B3: sbiw brne rjmp
w10B3 XL, 2 w10B2 waitcmd XL, 1 w10B2 waitcmd
; goto waitcmd();
;====== 'A' - Load Address ================================================= w11: cpi brne rcall mov rcall mov rjmp
u_data,'A' w12 getc addrh,u_data getc addrl,u_data put_ret
; 'A' Load address ; addrh = getc(); ; addrl = getc(); ; goto reply();
;====== 'D' - Write Data Memory ============================================ w12: cpi
u_data,'D'
; 'D' Write data
memory brne w13 rcall getc rcall eeprom_write rjmp put_ret
; get data
;====== 'd' - Read Data Memory ============================================= w13: cpi
u_data,'d'
; 'd' Read data
brne rcall rjmp
w14 read_send_datamem waitcmd
; goto waitcmd();
memory
;====== 'L' - Leave Programming Mode ======================================= w14: cpi
u_data,'L'
; 'L' Leave
programming mode brne w142 w141: pas_RESET release_ports set_LED rjmp put_ret
; set RESET passive ; release ports ; LED off
;====== 'E' - Exit , release all Ports, inhibit AVR910 ===================== w142: cpi u_data,'E' brne w15 rjmp w141
; 'E' xit ; exit command for
AVR Prog ;====== 'e' - Chip Erase =================================================== w15: cpi brne ldi rcall
u_data,'e' w16 s_data,0xac wrser
; 'e' Chip erase
tst brmi ldi rcall
device w151 s_data,0x80 wrser
w151: ldi rcall
s_data,0x04 wrser
; wrser(0x04) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00) SPI
ldi rcall rjmp
temp1,40 delay put_ret
; wrser(0xac) SPI
write (byte 1) ; S89 device ; wrser(0x80) SPI
write (byte 2)
write (byte 3)
write (byte 4)
;====== 'l' ============================================== ; Some more w16: cpi bits brne rcall ldi rcall write (byte 1) tst brmi cpi tn26) breq mov andi 0x06) | 0xe0 ori rcall write (byte 2) ldi rcall write (byte 3) rjmp w163: ldi rcall write (byte 2) ldi rcall write (byte 3) mov ori rcall write (byte 4) rjmp w161: mov andi ori rcall w162: ldi rcall write (byte 4) w164: ldi rcall rjmp
; delay 40mS
- Write Lock Bits different Adresses for other devices? u_data,'l'
; 'l' Write lock
w17 getc s_data,0xac wrser
; get data ; wrser(0xac)
SPI
device w161 device,0x5e
; S89 device ; if (device ==
w163 s_data,u_data s_data,0x06
; (u_data &
s_data,0xe0 wrser
; wrser(u_data) SPI
s_data,0x00 wrser
; wrser(0x00)
SPI
s_data,0xe0 wrser
; tn26 device ; wrser(0xe0)
SPI
s_data,0x00 wrser
; wrser(0x00)
SPI
s_data,u_data s_data,0xfc wrser
; wrser(u_data) SPI
w162
w164 s_data,u_data s_data,0xe0 s_data,0x07 wrser
; S89 device
s_data,0x00 wrser
; wrser(0x00)
temp1,10 delay put_ret
SPI
; delay 10mS
;====== 's' - Read Signature Bytes ========================================= w17: cpi
u_data,'s'
; 's' Read
signature bytes brne tst brmi ldi rcall ldi rcall ldi rcall rjmp w171: rjmp ca17: ldi rcall
w18 device w171 param1,0x02 ca17 param1,0x01 ca17 param1,0x00 ca17 waitcmd
s_data,0x30 wrser
; wrser(0x30)
SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
SPI
mov rcall
s_data,param1 wrser
; wrser(param1) SPI
rcall
rdser
;
mov rcall ret
u_data,s_data putc
; send data
; S89 device ; param1 = 0x02 ; param1 = 0x01 ; param1 = 0x00
put_err
write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4)
;====== 'm' - Write Program Memory Page ==================================== w18: cpi
u_data,'m'
; 'm' Write Program
brne ldi rcall
w19 s_data,0x4c wrser
; wrser(0x4c)
mov
s_data,addrh
; original, reload
mov
s_data,pol_ah
; for speeding up
rcall
wrser
; wrser(addrh) SPI
mov
s_data,addrl
; original, reload
mov
s_data,pol_al
; for speeding up
rcall
wrser
; wrser(addrl) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
rjmp
wait_M
; write FLASH delay
Memory Page
SPI
write (byte 1) ; address transfer write (byte 2) ; address transfer write (byte 3) SPI
write (byte 4)
;====== ':' - Universal Command ============================================ w19: cpi
u_data,':'
brne rcall mov rcall mov rcall mov mov rcall
w20 getc cmd1,u_data getc cmd2,u_data getc cmd3,u_data s_data,cmd1 wrser
mov rcall
; ':' Universal
Command ; ; ; ; ; ;
get data1 cmd1 = data1 get data2 cmd2 = data2 get data3 cmd3 = data3
; wrser(cmd1)
SPI
s_data,cmd2 wrser
; wrser(cmd2)
SPI
mov rcall
s_data,cmd3 wrser
; wrser(cmd3)
SPI
rcall
rdser
;
SPI
mov rcall ldi rcall rjmp
u_data,s_data putc temp1,50 delay put_ret
write (byte 1)
write (byte 2)
write (byte 3) read
(byte 4) ; send data ; delay 50mS
;====== '.' - New Universal Command ======================================== w20: cpi
u_data,'.'
; '.' New Universal
brne rcall mov
w21 getc cmd1,u_data
; get data1 ; cmd1 =
rcall mov
getc cmd2,u_data
; get data2 ; cmd2 =
rcall mov
getc cmd3,u_data
; get data3 ; cmd3 =
rcall mov rcall
getc s_data,cmd1 wrser
; get data4
mov rcall
Command
data1
data2
data3
; wrser(cmd1)
SPI
s_data,cmd2 wrser
; wrser(cmd2)
SPI
mov rcall
s_data,cmd3 wrser
; wrser(cmd3)
SPI
mov rcall
s_data,u_data wrser
; wrser(u_data) SPI
mov rcall ldi rcall rjmp
u_data,rd_s_data putc temp1,50 delay put_ret
write (byte 1)
write (byte 2)
write (byte 3)
write (byte 4) ; send data ; delay 50mS
;====== 'r' - Read Lock Bits ============================================== w21: cpi brne ldi rcall
u_data,'r' w30 s_data,0x58 wrser
; 'r' Read lock bits
; wrser(0x58)
SPI
write (byte 1) ;
ldi s_data,0x00 clr s_data rcall wrser
; wrser(0x00) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
rcall
rdser
;
mov rcall rjmp
u_data,s_data putc put_ret
; send data
write (byte 2) ;
SPI
write (byte 3) read
SPI
(byte 4)
;====== Unknown Command ==================================================== w30:
rjmp
put_err
;====== Wait for FLASH write in avr910 mode ================================== wait_S: table rcall brcs
Dev_M bel_table ws_pol
; No Page Mode,
put_ret
; in Byte Mode time
poll last Byte rjmp is long enougt to get next Byte... Bws_pol:
; entry adress for
Block mode delay ldi temp3,1 mov B_Flag,temp3
; set Flag that
ws_poll comes back with ret ... ws_pol: tst
PollcodeF
; if polling not
ws_del
; polling not used
p_data,PollcodeF
; if (data ==
breq andi
ws_del pol_cmd,0x0f
; wait default delay ; write command:
ori
pol_cmd,0x20
; read
clr
temp3
; clear polling
applicable, standart delay breq ws_def: cp PollcodeF)
0x48, 0x40 command:
0x28, 0x20 counter ws_cy: tst brmi mov rcall
device ws_89 s_data,pol_cmd wrser
; S89 device ; wrser(pol_cmd)
SPI write (byte 1) mov rjmp ws_89: mov
s_data,pol_ah ws_90
rcall ori ws_90: rcall
shift_s_data3 s_data,0x01 wrser
; wrser(pol_ah) SPI
mov rcall
s_data,pol_al wrser
; wrser(pol_al) SPI
rcall
rdser
;
tst brpl andi
device ws_cb s_data,0x80
; compare only MSB
s_data,pol_ah
; s_data = (pol_ah
<< 3) | 0x01;
write (byte 2) (S89=byte1)
write (byte 3) (S89=byte2) read
SPI
(byte 4) (S89=byte3)
for S89 device andi p_data,0x80 ws_cb: cp s_data,p_data breq ws_ok dec temp3 brne ws_cy ws_del: polling cycles are over, give additional standart Time ldi temp1,10 rcall delay ws_ok: tst B_Flag breq put_ret clr B_Flag normal operation ret
; s_data = p_data ; loop ; 256 ; delay 10mS
; Reset B_Flag for
;====== Wait for FLASH write in page mode ================================== wait_M: cpi breq
device,0x41 wm_del
; polling
cpi breq
device,0x23 poll_t2313
; polling different
cpi
p_data, 0xFF
; if last Byte was
breq andi
wm_del pol_cmd,0x0f
; write command:
ori
pol_cmd,0x20
; read
clr
temp3
; clear polling
s_data,pol_cmd wrser
; wrser(pol_cmd)
mov rcall
s_data,pol_ah wrser
; wrser(pol_ah) SPI
mov rcall
s_data,pol_al wrser
; wrser(pol_al) SPI
rcall
rdser
;
inapplicable for m103
for t2313 0xFF give standart delay
0x48, 0x40 command:
0x28, 0x20 counter wm_cy: mov rcall SPI write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4)
cp s_data,p_data breq wm_ok dec temp3 breq wm_del cycles are over, give another 50ms delay... rjmp wm_cy wm_del: ldi temp1,50 rcall delay wm_ok: tst B_Mode breq wm_end tst Bcnt2 breq wm_end rjmp w95 wm_end: clr B_Mode Flag rjmp put_ret poll_t2313:
; s_data = p_data ; 256 polling ; loop ; delay 50mS
; Reset Block Mode
; Polling
ATTiny2313 is different ldi clr
pol_cmd,0xf0 temp3
; Byte1= 0xF0 ; clear polling
pol_ah,temp3
; Byte2= 0x00
s_data,pol_cmd wrser
; wrser(pol_cmd)
mov rcall
s_data,pol_ah wrser
; wrser(pol_ah) SPI
mov rcall
s_data,pol_al wrser
; wrser(pol_al) SPI
rcall
rdser
;
andi
s_data,0x01
; last Bit tells if
wm_ok temp3 wm_del
; s_data = p_data
p2313_1
; loop
counter mov p2313_1: mov rcall SPI write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4)
polling OK breq dec breq cycles are over, give another 50ms delay... rjmp
; 256 polling
;====== Command Error ====================================================== put_debug:
; shows u_data on
serial for debug reason rcall putc put_err: ldi u_data,'?' rcall putc rjmp waitcmd
; putc('?') ; send '?'
;====== Reply Command ====================================================== put_ret: ldi rcall rjmp
u_data,0x0d putc waitcmd
; putc(0x0D) ; send CR
; *************************************************************************** ;* ;* TABLE ;* device codes ;* ;* DESCRIPTION ;* The following device codes must be used by the host computer. Note ;* that the device codes are arbitrary selected, they do not have any ;* thing in common with the signature bytes stored in the device. ;* This are the device Codes recognized by the AVRprog Software. Some ;* Devices may require special hardware or a different, not yet ;* implemented Protocol! Use at your own risk. ;* ; *************************************************************************** Dev_S: ; byte write ; avr910-devcode ,Code during polling Flash. 0x00: no polling supported, program default time ; .db 0x10 ,0x00 ;AT90S1200A No support for this type ; .db 0x11 ,0x00 ;AT90S1200B No support for this type ; .db 0x12 ,0x00 ;AT90S1200C No support for this type .db 0x13 ,0x00 ;AT90S1200 .db 0x20 ,0x7F ;AT90S2313A .db 0x28 ,0x7F ;AT90S4414A .db 0x30 ,0xFF ;AT90S4433A .db 0x34 ,0xFF ;AT90S2333A .db 0x38 ,0x7F ;AT90S8515A .db 0x48 ,0xFF ;AT90S2323A .db 0x4C ,0xFF ;AT90S2343A .db 0x51 ,0xFF ;tn10 .db 0x55 ,0xFF ;tn12 .db 0x56 ,0xFF ;tn15 .db 0x68 ,0xFF ;AT90S8535 .db 0x6C ,0xFF ;AT90S4434 .db 0x86 ,0xFF ;AT89S8252 bug in avrprog in Block write Mode!(See Note 18 for Workaround) .db 0x87 ,0xFF ;AT89S53 bug in avrprog .dw 0 ;End of table Dev_M: ; Devices which support Page Programming. Dont forget the Page Size of different Devices. ; Maximum ist 0x40 due to limitated RAM in 2313 Chip. (Pages with bigger Pages are programmed multiple times) ; avr910-devcode ,Pagesite in Words .db 0x23 ,0x10 ;tn2313 avr910-Devicecode not official (STK500 Code used, avrdude.conf modification!) .db 0x3a ,0x20 ;m8515, Pagesize 32 words (0x20) .db 0x3b ,0x20 ;m8515boot Bootloader Mode untested! .db 0x41 ,0x40 ;m103 .db 0x43 ,0x40 ;m128 .db 0x44 ,0x40 ;m128boot Bootloader Mode untested! .db 0x45 ,0x40 ;m64 .db 0x46 ,0x40 ;m64boot Bootloader Mode untested! .db 0x5E ,0x10 ;tn26 .db 0x60 ,0x40 ;m161 .db 0x61 ,0x40 ;m161boot Bootloader Mode untested! .db 0x62 ,0x40 ;m162 .db 0x63 ,0x40 ;m162boot Bootloader Mode untested! .db 0x64 ,0x40 ;m163 .db 0x66 ,0x40 ;m163boot Bootloader Mode untested! .db 0x69 ,0x20 ;m8535 .db 0x6a ,0x20 ;m8535boot Bootloader Mode untested! .db 0x72 ,0x40 ;m32 .db 0x73 ,0x40 ;m32boot Bootloader Mode untested! .db 0x74 ,0x40 ;m16 .db 0x75 ,0x40 ;m16boot Bootloader Mode untested! .db 0x76 ,0x20 ;m8 .db 0x77 ,0x20 ;m8boot Bootloader Mode untested! .db 0x78 ,0x40 ;m169 .db 0x79 ,0x40 ;m169boot Bootloader Mode untested! .db 0x65 ,0x20 ;m83 obsolete .db 0x67 ,0x20 ;m83boot obsolete .db 0x42 ,0x40 ;m603 obsolete .dw 0 ;End of Table
; Devices with known avr910 Devicecodes, but not supported with this Programmer ; .db 0x50 Voltage Hardware and uses different Protocoll! No Support! ; .db 0x58 ; .db 0x5C parallel Programming Mode! ; .db 0x70 Hardware, untested! ; .db 0x71 Hardware, untested! ; .db 0x80 Hardware, untested! ; .db 0x81 Hardware, untested!
;tn11 Needs additional High ;tn19 Obsolete ;tn28 Only supported in ;AT90C8534
unknown
;AT90C8544
unknown
;AT89C1051
unknown
;AT89C2051
unknown
; *************************************************************************** ;* ;* TABLE ;* revision codes ;* ; *************************************************************************** SW_Ver: .db "37",0,0 HW_Ver: .db "12",0,0 ; *************************************************************************** ;* ;* TABLE ;* ID string "AVR ISP" ;* ; *************************************************************************** ID_Str: .db "AVR ISP",0 ; *************************************************************************** ;* ;* TABLE ;* Chip ID string to identify the Firmware ;* ; *************************************************************************** ChipID: .db "Ver.3.7e (AVR109 Mode, 7.3728Mhz, 115.200 baud) for AN910, AT90S2313" .db "www.mikrocontroller-projekte.de 14.Jan.2005",0 ;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and http://avr-asm.tripod.com/isp2313.html (3 of 4)1/20/2009 8:58:51 PM
16 BIT MATH (AVR 202)
Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/isp2313.html (4 of 4)1/20/2009 8:58:51 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ISP FOR 1200 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* Title : AVR ISP (Auto adr inc, 19200bps) ;* Version : 2.0 ;* Last updated : 1998.01.06 (mlund) ;* Target : AT90S1200 ;* File : ispprog.asm ;* Author : Atmel Norway ;* ;* DESCRIPTION ;* The firmware on all programmers now support a unified protocol for ;* program and data memory programming. The host computer do not need ;* to know if the programmer operates in serial or parallel mode. ;* ;* The following commands are supported. All commands start with a ;* single letter. The programmer returns 13d (carriage return) or the ;* data read after the command is finished. ;* ;* +------------+------------+------+ ;* Commands | Host writes | Host reads | | ;* -------+-----+------+------+-----+ | ;* | ID | data | data | | Note | ;* +-----------------------------------+-----+------+------+-----+------+ ;* | Enter programming mode | 'P' | | | 13d | 1 | ;* | Set address | 'A' | ah al | | 13d | 2 | ;* | Write program memory, low byte | 'c' | dd | | 13d | 3 | ;* | Write program memory, high byte | 'C' | dd | | 13d | 3 | ;* | Issue Page Write | 'm' | | | 13d | | ;* | Read program memory | 'R' | |dd (dd)| | 4 | ;* | Write data memory | 'D' | dd | | 13d | | ;* | Read data memory | 'd' | | dd | | | ;* | Chip erase | 'e' | | | 13d | | ;* | Write lock bits | 'l' | dd | | 13d | | ;* | Write fuse bits | 'f' | dd | | 13d | 11 | ;* | Read fuse and lock bits | 'F' | | dd | | 11 | ;* | Leave programming mode | 'L' | | | 13d | 5 | ;* | Select device type | 'T' | dd | | 13d | 6 | ;* | Read signature bytes | 's' | | 3*dd | | | ;* | Return supported device codes | 't' | | n*dd | 00d | 7 | ;* | Return software identifier | 'S' | | s [7] | | 8 | ;* | Return sofware version | 'V' | | dd dd | | 9 | ;* | Return hardware version | 'v' | | dd dd | | 9 | ;* | Return programmer type | 'p' | | dd | | 10 | ;* | Set LED | 'x' | dd | | 13d | 12 | ;* | Clear LED | 'y' | dd | | 13d | 12 | ;* | Universial command | ':' | 3*dd | dd | 13d | | ;* +-----------------------------------+-----+------+------+-----+------+ ;* ;* NOTE 1 ;* The Enter programming mode command MUST be sent one time prior to ;* the other commands, with the exception of the 't', 'S', 'V', 'v' ;* and 'T' commands. The 'T' command must be sent before this command ;* (see note 6). ;* ;* For programmers supporting both parallel and serial programming ;* mode this command enters parallel programming mode. For programmers ;* supporting only serial programming mode, this command enters serial ;* programming mode. ;* ;* NOTE 2 ;* The ah and al are the high and low order bytes of the address. For ;* parallel programmers this command issues the Load Address Low/High ;* Byte command. For serial programmers the address byte is stored for ;* use by the Read/Write commands. ;* ;* NOTE 3 ;* For parallel programmers this command issues the Program Flash ;* command. For serial programmers this command iussues the Write ;* Program Memory Command. For devices with byte-wide program memories ;* only the low byte command should be used. ;* ;* NOTE 4 ;* The contents of the program memory at the address given by the 'A' ;* command are written to the serial port in binary form. For byte ;* wide memories one byte is written. For 16 bit memories two bytes ;* are written,MSB first. ;* ;* NOTE 5 ;* This command must be executed after the programming is finished. ;* ;* NOTE 6 ;* The select device type command must be sent before the enter ;* programming command ;* ;* NOTE 7 ;* The supported device codes are returned in binary form terminated ;* by 0x00. ;* ;* NOTE 8 ;* This return a 7 character ASCII string identifying the programmer. ;* For the in-system programmer it is "AVR ISP". ;* ;* NOTE 9 ;* The software/hardware version are returned as two ASCII numbers. ;* ;* NOTE 10 ;* This command should be used to identify the programmer type. The ;* return value is 'S' for serial (or SPI) programmers or 'P' for ;* parallel programmers. ;* ;* NOTE 11 ;* The write fuse bits command are available only on parallel ;* programmers and only for AVR devices (device code < 0x80). The host ;* should use the return programmer type command to determine the ;* programmer type, do not use the "AVR PPR" idenifier because other ;* programmers may be available in the future. ;* ;* NOTE 12 ;* Currently only the AVR development board has LEDs. The other boards ;* must implement this commands as NOPs. ;* ;* NOTE 13 ;* Devices using Page Mode Programming write one page of flash memory ;* before issuing a Page Mode Write Pulse. ; *************************************************************************** ;**** includes **** .include "1200def.inc" ; *************************************************************************** ;* ;* CONSTANTS ;* device codes ;* ;* DESCRIPTION ;* The following device codes must be used by the host computer. Note ;* that the device codes are arbitrary selected, they do not have any ;* thing in common with the signature bytes stored in the device. ;* ;* The following devices are supported (make a new table for each ;* software release): ;* ;* SW_MAJOR=1, SW_MINOR=5 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ;* SW_MAJOR=1, SW_MINOR=6 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ATmega103 rev. A (abbreviated S01838A) ;* ; *************************************************************************** .equ .equ .equ .equ .equ .equ .equ
S1200C S1200D S2313A S4414A S8515A S8252 S2323A
= = = = = = =
0x12 0x13 0x20 0x28 0x38 0x86 0x48
.equ .equ
S01838C = 0x40 S01838D = 0x41
;**** Revision Codes **** .equ
SW_MAJOR = 2
; Major SW revision
.equ
SW_MINOR = 0
; Minor SW revision
.equ
HW_MAJOR = 1
; Major HW revision
.equ
HW_MINOR = 0
; Minor HW revision
number number number number
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following four macros if the RESET pin to the ;* target moves and/or if the SCK/MISO/MOSO moves. ;* ; *************************************************************************** .macro sbi .endm
set_reset portb,4
.macro cbi .endm
clr_reset portb,4
.macro nop ; sbi .endm
ddrd_init
.macro ldi out
ddrb_init temp1,0xdf ddrb,temp1
; PB5 is input, the rest is
ddrb_release temp1,(1<
; PB4 (RESET) is output,
ddrd,3
output .endm .macro ldi out the rest is input .endm .macro sbi ldi m0: dec brne cbi ldi m1: dec brne .endm
pulse_sck portb,SCK temp2,6 temp2 m0 portb,SCK temp2,1 temp2 m1
; 3
;***************** ;* SPI Constants * ;***************** .equ
MOSI
= 6
; Bit number on
.equ
MISO
= 5
; Bit number on
.equ
SCK
= 7
; Bit number on
PORTB PORTB PORTB
;****************** ;* UART Constants * ;****************** ;**** Constant declarations Data Rate **** ;.equ
N = 95
; 115200 BAUD when
;.equ
N = 31
; 57600 BAUD when
;.equ
N = 43
; 38400 BAUD when
.equ
N = 33
; 19200 BAUD when
;.equ
N = 102
; 38400 BAUD when
.equ
R = 2
R=1 and XTAL=11.059MHz R=2 and XTAL=11.059MHz R=2 and XTAL=11.059MHz R=2 and XTAL=4.00MHz R=1 and XTAL=4.00MHz
;**** UART transmit pin in PORTD **** .equ .equ
TXPIN = 1 RXPIN = 0
; Receive pin must
be external interrupt !! ;**** Bit positions in UART Status Register **** .equ .equ
TXC = 0 RXC = 1
; Transmit ; Receive
;***************************** ;* Global Register Variables * ;***************************** .def .def .def .def .def .def
device temp1 temp2 s_data u_data addrl
= = = = = =
r16 r17 r18 r19 r20 r21
; Device code
.def
addrh
= r22
.def
bit_cnt = r23
; Bit count used by
.def
u_stat
= r24
; Status byte used
.def
cmd
= r25
; Serial
.def
count
= r26
; Time out variable
.def .def .def .def
param1 cmd1 cmd2 cmd3
= = = =
; SPI data ; UART data ; Low order byte of
address ; High order byte
of address UART routine by UART routine programming command for "enter programming mode" r27 r28 r29 r30
;********************* ;* Interrupt Vectors * ;********************* .CSEG rjmp reti rjmp reti
RESET
; ; ; ;
TIM0_OVF
Reset Handle IRQ0 Handle (not used) Timer0 Overflow Handle Analog Comparator Handle
(not used)
; *************************************************************************** ;* ;* INTERRUPT ;* TIM0_OVF - Software UART Service Routine ;* ; *************************************************************************** TIM0_OVF: in ldi out
r0,SREG ; store SREG temp1,(256-N+8) TCNT0,temp1 ; reset T/C0 to one bit
lenght inc sbrs
bit_cnt u_stat,TXC
; increment bit counter ; if (transmit complete
rjmp
transmit
;
sec PIND,RXPIN u_data
; set carry ; if (RxD == LOW) ; clear carry ; shift carry into u_data
bit_cnt,8 to_1 temp1
; if (bit_cnt == 8) ; { ; disable T/C0 Overflow
TIMSK,temp1 u_stat,1<
;
flag clear)
to_0: sbis clc ror cpi brne clr
goto transmit
Interrupt out sbr to_1: out reti transmit: cpi
SREG,r0
set receive complete ; } ; restore SREG ; exit
bit_cnt,1
; if (bit_cnt == 1)
\\
brne cbi rjmp to_2: cpi
to_2 PORTD,TXPIN to_1
; { ; ;
bit_cnt,10
generate start bit exit ; } ; if (bit_cnt == 10) \\
brne sbi clr
to_3 PORTD,TXPIN temp1
; { ; ;
generate stop bit disable TC0
out sbr
TIMSK,temp1 u_stat,1<
;
set transmit
to_1
;
u_data,0 PORTD,TXPIN u_data,0 PORTD,TXPIN u_data to_1
; ; ; ; ; ;
start bit
stop bit
overflow interrupt
complete bit rjmp to_3: sbrc sbi sbrs cbi lsr rjmp
exit ; } if (LSB set) PD3 = HIGH if (LSB clear) PD3 = LOW shift left u_data exit
; *************************************************************************** ;* ;* FUNCTION ;* u_init ;* ;* DESCRIPTION ;* Initialize UART. ;* ; *************************************************************************** u_init: ldi out sbi cbi ret
ldi u_stat,1<
; *************************************************************************** ;* ;* FUNCTION ;* putc ;* ;* DESCRIPTION ;* Send a character on the UART Tx line. ;* ; *************************************************************************** putc:
clr
u_stat
; clear UART status
flags clr ldi
bit_cnt temp1,1<
; clear bit counter ; enable T/C0 overflow
interrupt out putc0:
TIMSK,temp1 sbrs u_stat,TXC
; while (!(u_stat &
TXC)); // Wait for TXC rjmp ret
putc0
; *************************************************************************** ;* ;* FUNCTION ;* getc ;* ;* DESCRIPTION ;* Wait for start bit and receive a character on the UART Rx line. ;* ; *************************************************************************** getc: rjmp getc0: rjmp ldi out
sbis PIND,RXPIN getc sbic PIND,RXPIN getc0 temp1,(256-(N+N/2)+8+12); TCNT0,temp1 ; preset T/C0 to 1.5 bit
lengths ldi out out
temp1,1<
; clear T/C0 overflow flag ; enable T/C0 overflow
Interrupt clr getc1:
bit_cnt ; clear bit counter sbrs u_stat,RXC ; wait for Receive
Complete rjmp cbr ret
getc1 u_stat,1<
; clear RXC
; *************************************************************************** ;* ;* FUNCTION ;* delay ;* ;* DESCRIPTION ;* Make a small delay. ;* ; *************************************************************************** delay: dl: dec brne dec brne ret
ldi temp2 dl temp1 delay
temp2,0xff
; *************************************************************************** ;* ;* FUNCTION ;* wrser ;* ;* DESCRIPTION ;* Write a byte to the SPI. ;* ; *************************************************************************** wrser: wrs0: brcc sbi rjmp wrs1: wrs2: dec brne ret
ldi temp1,8 rol s_data wrs1 portb,MOSI wrs2 cbi portb,MOSI pulse_sck temp1 wrs0
; *************************************************************************** ;* ;* FUNCTION ;* rdser ;* ;* DESCRIPTION ;* Read a byte from the SPI. ;* ; *************************************************************************** rdser: ldi temp1,8 ldi s_data,0 rd0: lsl s_data sbic pinb,MISO ori s_data,1 pulse_sck dec temp1 brne rd0 ret
; *************************************************************************** ;* ;* FUNCTION ;* spiinit (Enter programming mode) ;* ;* DESCRIPTION ;* Initialize SPI interface on AVR or 'AT89 device. ;* ; *************************************************************************** spiinit:ddrd_init ddrb_init cbi portb,SCK cpi device,S8252 breq s89 set_reset ldi temp1,0xff rcall delay clr_reset rjmp s0
; ; ; ; ; ; ;
initialize port D initialize port B clear SCK if (device != S8252) { set RESET = 1 delay(0xff);
; ; } ; else
s89:
set RESET = 0
clr_reset ldi temp1,0xff rcall delay set_reset s0:
; ;
; { set RESET = 0 delay(0xff);
; set RESET = 1 ; } ; delay(0xff);
ldi rcall
temp1,0xff delay
ldi
s_data,0xac
; wrser(0xac);
//
rcall ldi
wrser s_data,0x53
; wrser(0x53);
//
rcall
wrser
SPI write (byte 1)
SPI write (byte 2)
; // SPI Synchronization (fix!) cpi
device,0x20
brlo tst brmi
s2 device s2
; if ( (device >= 0x20) &&
(device <= 0x7F) )
s0b: ldi
count,32
rcall
rdser
; ; ;
cpi breq
s_data,0x53 s3
;
ldi
s_data,0x00
;
wrser
rcall wrser pulse_sck ldi s_data,0xac
; ;
pulse SCK wrser
rcall ldi
wrser s_data,0x53
;
wrser
rcall dec brne rjmp
wrser count s1 s3
ldi
s_data,0x00
rcall
wrser
s1: == 0x53)
; { count = 32; do { if (rdser
// SPI read (byte 3)
break; (0x00);
(0xac);
// SPI write (byte 4)
(0x53);
// SPI write (byte 1)
// SPI write (byte 2)
s2: (0x00);
;
} while(--count);
; } ; else ; { ;
wrser
// SPI write (byte 3) s3: cpi breq ldi
device,S8252 s4 s_data,0x00
rcall
wrser
; } ; if (device != S8252) ; { ; wrser(0x00);
//
SPI write (byte 4) s4: ldi rcall ret
temp1,0x10 delay
; } ; delay(0x10);
; *************************************************************************** ;* ;* FUNCTION ;* show_id ;* ;* DESCRIPTION ;* Show our ID ("AVR ISP") on the serial line. ;* ; *************************************************************************** show_id:ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ret
u_data,0x41 putc u_data,0x56 putc u_data,0x52 putc u_data,0x20 putc u_data,0x49 putc u_data,0x53 putc u_data,0x50 putc
; 'A' ; 'V' ; 'R' ; ' ' ; 'I' ; 'S' ; 'P'
; *************************************************************************** ;* ;* RESET ;* ;* DESCRIPTION ;* Initialization ;* ; *************************************************************************** RESET: clr temp1 out GIMSK,temp1 ser temp1 out PORTD,temp1 set_reset out PORTB,temp1 ddrb_release rcall u_init sei
; disable external interrupt ; Initialize ; set RESET=1
; Initialize UART ; Enable interrupts
; *************************************************************************** ;* ;* PROGRAM ;* waitcmd -> main ;* ;* DESCRIPTION ;* Wait for and execute commands. ;* ; *************************************************************************** waitcmd:rcall
getc
; while (getc() ==
ESC) {}; cpi breq
u_data,0x1b waitcmd
;**** Device Type **** cpi brne rcall mov rjmp
u_data,0x54 w0 getc device,u_data put_ret
; 'T' Device type ; getc(); // dummy ; putc(device);
;**** Return Software Identifier **** w0: cpi
u_data,0x53
; 'S' Return software
w1 show_id waitcmd
; show_id();
identifier brne rcall rjmp
;**** Return Software Version **** w1: cpi brne ldi rcall ldi rcall rjmp
u_data,0x56 ;'V' Return software version w2 u_data,0x30+SW_MAJOR ; putc(0x30+SW_MAJOR); putc u_data,0x30+SW_MINOR ; putc(0x30+SW_MINOR); putc waitcmd
;**** Return Hardware Version **** w2: cpi brne ldi rcall ldi rcall rjmp
u_data,0x76 ;'v' Return hardware version w3 u_data,0x30+HW_MAJOR ; putc(0x30+HW_MAJOR); putc u_data,0x30+HW_MINOR ; putc(0x30+HW_MINOR); putc waitcmd
;**** Show Supported Devices **** w3: cpi brne ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi
u_data,0x74 w4 u_data,S1200C putc u_data,S1200D putc u_data,S2313A putc u_data,S4414A putc u_data,S8515A putc u_data,S2323A putc u_data,S8252 putc u_data,0x00
; 't' Show supported devices ; putc(S1200C); ; putc(S1200D); ; putc(S2313A); ; putc(S4414A); ; putc(S8515A); ; putc(S2323A); ; putc(S8252); ; putc(0x00);
// end of
device list rcall rjmp
putc waitcmd
;**** Return Programmer Type **** w4: cpi brne ldi
u_data,0x70 w5 u_data,0x53
; 'p' Return programmer type ; putc('S');
// serial
programmer rcall rjmp
putc waitcmd
;**** Set LED **** w5: cpi brne rjmp
u_data,0x78 w6 put_ret
; 'x' Set LED (ignored)
;**** Clear LED **** w6: cpi brne rjmp
u_data,0x79 w7 put_ret
; 'y' Clear LED (ignored)
;**** Enter Programming Mode **** ; We require that the device code be selected before any of the other commands w7: cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq rjmp w72:
device,S1200C w72 device,S1200D w72 device,S8515A w72 device,S4414A w72 device,S2313A w72 device,S8252 w72 device,S01838C w72 device,S01838D w72 device,S2323A w72 put_err cpi
; if ((device != S1200C) && ;
(device != S1200D) &&
;
(device != S8515A) &&
;
(device != S4414A) &&
;
(device != S2313A) &&
;
(device != S8252) &&
;
(device != S01838C) &&
;
(device != S01838D) &&
;
(device != S2323A))
;
goto put_err();
u_data,0x50
; 'P' Enter
programming mode brne rcall rjmp
w8 spiinit put_ret
; spiinit();
;**** Wait Program Memory **** ;* USAGE ;* wait_pm(byte cmd, byte c_data); ;* ;* cmd : 0x28 - wait for high byte written ;* 0x20 - wait for low byte written ;* u_data : current data written ;wait_pm: ; ; mov (cmd); // SPI write (byte 1) ; rcall ; mov (addrh); // SPI write (byte 2) ; rcall ; mov (addrl); // SPI write (byte 3) ; rcall ; rcall (); // SPI read (byte 4) ; ; ;
cp brne ret
s_data,cmd
; do ; { ;
wrser
wrser s_data,addrh
;
wrser
wrser s_data,addrl
;
wrser
wrser rdser
;
s_data = rdser
s_data,u_data wait_pm
; } ; while(s_data != u_data);
;**** Write Program Memory, High Byte **** w8: cpi
u_data,0x43
; 'C' Write program memory,
high byte brne rcall cpi brne rjmp
w9 getc device,S8252 w81 put_err
; if (device == S8252) ; { ; goto err(); ; // (AT89 series
have byte wide program memory !)
(0x48);
w81: // SPI write (byte 1)
ldi
; } s_data,0x48
; wrser
rcall mov
wrser s_data,addrh
; wrser(addrh);
//
rcall mov
wrser s_data,addrl
; wrser(addrl);
//
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
SPI write (byte 2)
SPI write (byte 3)
C! brne com w81b: mov
w81b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq
w82 device,S01838D w82
ldi
temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
ldi
temp1,0x01
; Auto increment
clr add adc rjmp
temp2 addrl,temp1 addrh,temp2 put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w82: address
http://avr-asm.tripod.com/isp1200.html (1 of 3)1/20/2009 8:59:30 PM
!!!!
16 BIT MATH (AVR 202)
;**** Write Program Memory, Low Byte **** w9: cpi
u_data,0x63
; 'c' Write program memory,
low byte brne rcall
w12 getc
cpi breq ldi
device,S8252 w989 s_data,0x40
rcall mov rjmp
wrser s_data,addrh w91
; if (device != S8252) ; { ; wrser(0x40);
//
SPI write (byte 1)
w989: mov
s_data,addrh
; ; } ; else
s_data = addrh;
; { s_data = (addrh <<
;
3) | 0x02; rcall ori
shift_s_data3 s_data,0x02
w91: rcall
wrser
; } ; wrser(s_data);
mov
s_data,addrl
; wrser(addrl);
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
// //
SPI write (byte 2) SPI write (byte 3)
C! brne com w91b: mov
w91b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq ldi
w92 device,S01838D w92 temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w92: rjmp
;**** Read Program Memory **** w12:
cpi
u_data,0x52
; 'R' Read program
memory brne cpi breq ldi
w10 device,S8252 w1289 s_data,0x28
rcall mov rjmp
wrser s_data,addrh w121
; ; if (device != S8252) ; { ; wrser(0x28);
//
SPI write (byte 1)
w1289: mov
s_data,addrh
; ; } ; else
s_data = addrh;
; { s_data = (addrh <<
;
3) | 0x01; rcall ori w121: rcall
shift_s_data3 s_data,0x01 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall cpi brne rjmp
u_data,s_data putc device,S8252 w122 waitcmd
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
s_data,0x20
if (device == S8252) { goto waitcmd(); } else ; { ; wrser(0x20); //
rcall mov
wrser s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall rcall
wrser rdser
;
putc(rdser());
//
mov rcall
u_data,s_data putc
ldi
temp1,0x01
;
Auto increment
clr add adc
temp2 addrl,temp1 addrh,temp2
rjmp
waitcmd
; ; }
goto waitcmd();
w122: ldi
; ; ; ; ;
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
Send data (byte 4)
address
!!!!
shift_s_data3: lsl s_data lsl s_data lsl s_data ret ;**** Load Address **** w10: brne rcall mov rcall mov rjmp
cpi u_data,0x41 ; 'A' Load address w11 getc ; addrh = getc(); addrh,u_data getc ; addrl = getc(); addrl,u_data put_ret ; goto reply();
;**** Write Data Memory **** w11:
cpi
u_data,0x44
; 'D' Write data
memory brne rcall cpi breq
w13 getc device,S8252 w1189
ldi rcall mov rjmp
s_data,0xc0 wrser s_data,addrh w111
w1189: rcall ori
mov s_data,addrh shift_s_data3 s_data,0x06
w111: mov rcall mov rcall ldi rcall rjmp
rcall wrser s_data,addrl wrser s_data,u_data wrser temp1,0x20 delay put_ret
;;**** Read Data Memory **** w13:
cpi
u_data,0x64
; 'd' Read data
memory brne cpi breq ldi
w14 device,S8252 w1389 s_data,0xa0
rcall mov rjmp
wrser s_data,addrh w131
; if (device != S8252) ; { ; wrser(0xA0);
//
SPI write (byte 1)
w1389: mov
s_data,addrh
; ; } ; else
s_data = addrh;
; { s_data = (addrh <<
;
3) | 0x05; rcall ori w131: rcall
shift_s_data3 s_data,0x05 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall rjmp
u_data,s_data putc waitcmd
; goto waitcmd();
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
;**** Leave Programming Mode **** w14:
cpi
u_data,0x4c
; 'L' Leave
programming mode brne w15 ddrb_release cpi device,S8252 breq w141 set_reset rjmp put_ret w141: clr_reset rjmp put_ret
; set RESET = 1 ; set RESET = 0
;**** Chip Erase **** w15:
cpi
u_data,0x65 brne w16 ldi s_data,0xac rcall wrser cpi device,S8252 breq w1589 ldi s_data,0x80 rcall wrser w1589: ldi s_data,0x04 rcall wrser ldi s_data,0x00 rcall wrser ldi temp1,0x30 rcall delay rjmp put_ret
; 'e' Chip erase
;**** Write Lock Bits **** w16:
cpi
u_data,0x6c
; 'l' Write lock
bits brne rcall ldi rcall mov cpi breq andi ori rcall ldi rcall rjmp w1689: ori rcall w162: rcall ldi rcall rjmp
w17 getc s_data,0xac wrser s_data,u_data device,S8252 w1689 s_data,0x06 s_data,0xe0 wrser s_data,0x00 wrser w162 andi s_data,0xe0 s_data,0x07 wrser ldi s_data,0x00 wrser temp1,0x30 delay put_ret
;**** Read Signature Bytes **** w17:
cpi
u_data,0x73
brne cpi brne rjmp w17begin: ldi rcall ldi rcall ldi rcall rjmp
w18 device,S8252 w17begin put_err
w17call:ldi rcall ldi rcall mov rcall rcall mov rcall ret
s_data,0x30 wrser s_data,0x00 wrser s_data,param1 wrser rdser u_data,s_data putc
; 's' Read
signature bytes
param1,0x02 w17call param1,0x01 w17call param1,0x00 w17call waitcmd
;**** Write Program Memory Page **** w18:
cpi
u_data,0x6D
; 'm' Write Program
Memory Page brne
w19
ldi
s_data,0x4c
rcall
wrser
mov
;
wrser(0x4c);
//
s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall
wrser
ldi
s_data,0x00
;
wrser(0x00);
//
rcall ldi
wrser temp1,0xff
;
delay(0xFF);
//
rcall rjmp
delay put_ret
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
SPI write (byte 4)
0x20 = 24585 cycles delay
;**** Universal Command **** w19:
cpi
u_data,0x3A
; ':' Universal
Command brne
w99
rcall mov rcall mov rcall mov rcall ldi
getc cmd1,u_data getc cmd2,u_data getc cmd3,u_data universal temp1,0xff
rcall rjmp
delay put_ret
;
delay(0xFF);
//
0x20 = 24585 cycles delay
universal: mov rcall mov rcall mov rcall rcall mov rcall ret
s_data,cmd1 wrser s_data,cmd2 wrser s_data,cmd3 wrser rdser u_data,s_data putc
w99: ;**** Command Error **** put_err:ldi u_data,0x3f rcall putc rjmp waitcmd
; putc('?');
\\ send '?'
; putc(0x0D);
\\ send CR
;**** Reply Command **** put_ret:ldi u_data,0x0d rcall putc rjmp waitcmd ;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on http://avr-asm.tripod.com/isp1200.html (2 of 3)1/20/2009 8:59:30 PM
16 BIT MATH (AVR 202)
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/isp1200.html (3 of 3)1/20/2009 8:59:30 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR SPI PROTOCOL HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202
MATH YX DIV16 XX
FLOAT 128
MATH 202 DEC ASCII
COPY 102
UART 128
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
;*
interface routines, and do not inherently contain a
;*
structure; that is dictated by the connected SPI
;* ;*
Due to having separate Enable/Disable and Read/
;*
routines, larger blocks of data can be sent simply
;*
the RW_SPI routine multiple times before disabling /
These routines are low-
;* ;*
ena_spi:
forces SCK low, and activates /SS signal. No calling requirements, returns
;* ;*
disa_spi: brings /SS signal hi (inactive). No calling requirements, returns
;*
rw_spi:
nothing. sends/receives a an 8-bit or 16-bit data
word. ;*
Must set up data to be sent in
;*
prior to calling; it returns
;*
the same register pair (if 8-bit,
(spi_hi,spi_lo) received data in uses only ;* the spi_lo register). ;* ;* VARIABLES: ;* The spi_hi and spi_lo variables are the high and low data bytes. ;* ;* ;*
AVR SPI
I2C/TWI 128
store the new received bit.
nothing.
ISP 1200
I2C TWI26
;*
nothing.
AVR ISP
I2C 302
is shifted out (transmitted), the vacated bit
;* ;* MAJOR ROUTINES: ;* init_spi: initializes the port lines used for SPI. ;* No calling requirements, returns
USB 232
I2C 300
;*
SS.
UART BUFF
ISP 2313
registers is used both to send and to receive; i.
by calling
XMODEM REC
UART 305
;*
Data is sent and received MSB-first.
Write-Word
VFX MEM
UART 304
word format.
peripheral(s).
FLASH CARD
CRC 236
;*
command
SER EPROM
SORT 220
It simultaneously transmits and receives SPI data
level
EPROM 100
VFX SMIL
;*
position is used to
LPM 108
DFLASH AT45
DESCRIPTION This is a collection of 8/16-bit word, Mode 0,
e., when one bit
AVG8 222 FFT7
:[email protected]
One pair of
INT ASCII HX2ASC
Support E-mail
in 8- or 16-bit
SQRT16 MATH 202
Title : Software SPI Master Version : 1.0 Last updated : 98.04.21 Target : AT90S1200 Easily modified for : Any AVR microcontroller
Master SPI routines.
DIV 24 24 DIV 3216
A V R 3 2 0
*****************
ASM MATH
MATH 32X
N O T E
They can be located anywhere in the register file. The temp variable holds the bit count, and is also
used in timing ;*
the high/low minimum pulse width.
This must be
located in an ;*
upper register due to the use of an IMMEDIATE-mode
instruction. ;* ;* HISTORY ;* V1.0 98.04.21 (rgf) Created ;* ; ***************************************************************************
TEA ADC 128
;**** includes ****
ADC 10B ADC 400
.include "1200def.inc"
;you can change
this to any device
ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
; *************************************************************************** ;* ;* CONSTANTS ;* ; ***************************************************************************
KBD PS2
;**** Revision Codes ****
KBD PC/128 PS2 EMU
ALM CLK
; Major SW revision
.equ
SW_MINOR = 0
; Minor SW revision
.equ
HW_MAJOR = 0
; Major HW revision
.equ
HW_MINOR = 0
; Minor HW revision
number number
CLOCK 8564 90 DAYS
SW_MAJOR = 1
number
BOOT MG8 BOOT DR8
.equ
number
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
; *************************************************************************** ;* ;* PORT DEFINITIONS ;* ; *************************************************************************** .equ .equ .equ .equ
ATMEL CORP AVR BUTTERFLY
sck nss mosi miso
= = = =
0 1 2 3
;PB0 ;PB1 ;PB2 ;PB3
pin pin pin pin
AVR BOOK
; *************************************************************************** ;* ;* REGISTER DEFINITIONS ;* ; *************************************************************************** .def .def .def
spi_lo spi_hi temp
=r0 =r1 =r16
;change as needed ; " ;misc usage, must be in
upper regs for IMMED mode
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following macros if a port other than PORTB is used. ;* ; *************************************************************************** .macro cbi .endm
ss_active portb,nss
.macro sbi .endm
ss_inactive portb,nss
.macro sbi .endm
sck_hi portb,sck
.macro cbi .endm
sck_lo portb,sck
.macro sbi .endm
mosi_hi portb,mosi
.macro cbi .endm
mosi_lo portb,mosi
.macro subi
addi @0, -@1
;subtract the negative of
an immediate value .endm .macro
set_delay
;set up the time
delay amount, from 1 to 7 subi
@0, (@1 << 5)
;NOTE: THIS shift affects
INC macro (below)! .endm .macro
inc_delay
;bump the delay
counter subi
@0, -(1 << 5)
;shift value here must be
same as above! .endm
; *************************************************************************** ;* ;* SAMPLE APPLICATION, READY TO RUN ON AN AT90S1200 ;* ; *************************************************************************** .cseg .org Rvect:
0 rjmp
Reset
; *************************************************************************** ;* ;* FUNCTION ;* init_spi ;* ;* DESCRIPTION ;* Initialize our port pins for use as SPI master. ;* ;* CODE SIZE: ;* 8 words ;* ; *************************************************************************** init_spi: ss_inactive sbi ddrb,nss ; sck_lo sbi ddrb,sck ; mosi_lo sbi ddrb,mosi ; cbi ddrb,miso
;set latch bit hi (inactive) ;make it an output ;set clk line lo ;make it an output ;set data-out lo ;make it an output ;not really required, it
powers up clr'd! ret
; *************************************************************************** ;* ;* FUNCTION ;* ena_spi ;* ;* DESCRIPTION ;* Init data & clock lines, then assert /SS. Note that if more than ;* one slave is used, copies of this could be made that would each ;* reference a different /SS port pin (use SS_ACTIVE0, SS_ACTIVE1, ...) ;* ;* CODE SIZE: ;* 4 words ;* ; *************************************************************************** ena_spi: sck_lo
;(should already be
there...) mosi_lo ss_active ret
; *************************************************************************** ;* ;* FUNCTION ;* disa_spi ;* ;* DESCRIPTION ;* De-assert /SS. Since this routine is so short, it might be better ;* to use the SS_INACTIVE statement directly in higher level code. ;* Again, if multiple slaves exist, additional copies of this could ;* be created; or ONE routine that disabled ALL /ss signals could be ;* used instead to make the code less error-prone due to calling the ;* wrong Disable routine. ;* ;* CODE SIZE: ;* 2 words ;* ; *************************************************************************** disa_spi: ss_inactive ret
; *************************************************************************** ;* ;* FUNCTION ;* rw_spi ;* ;* DESCRIPTION ;* Write a word out on SPI while simultaneously reading in a word. ;* Data is sent MSB-first, and info read from SPI goes into ;* the same buffer that the write data is going out from. ;* Make sure data, clock and /SS are init'd before coming here. ;* SCK high time is ((delay * 3) + 1) AVR clock cycles. ;* ;* If 8-bit use is needed, change LDI TEMP,16 to ,8 and also ;* eliminate the ROL SPI_HI statement. ;* ;* CODE SIZE: ;* 21 words ;* NUMBER OF CYCLES: ;* Overhead = 8, loop = 16 * (16 + (2* (delay_value*3))) ; (With call + return + delay=4, it is about 648 cycles.) ;* ; *************************************************************************** rw_spi: ldi
temp,16
;init loop counter to 16
bits ;ldi temp,8
;use THIS line instead if 8-
bit desired ; spi_loop: lsl
spi_lo
;move 0 into D0, all other
spi_hi
; and C ends up being first
bits UP one slot, rol bit to be sent. ;If 8-bit desired, also comment out the preceding ROL SPI_HI statement ; brcc lo_mosi mosi_hi rjmp mosi_done
;this branch creates setup
time on MOSI lo_mosi: mosi_lo nop
;also create setup time on
MOSI mosi_done: ; sck_hi ; ;must now time the hi pulse - not much else we can do here but waste time ; set_delay temp,4
;(4 * 3) cycle delay; range
is from 1 to 7! time_hi: inc_delay temp
;inc upper nibble until it
rolls over; then, brcs
time_hi
; C gets CLEARED, & temp
has original value ; sck_lo ;drop clock line low ; ;must now delay before reading in SPI data on MISO ; set_delay temp,4 time_lo: inc_delay temp brcs time_lo ; sbic pinb,miso ;after delay, read in SPI bit & put into D0 inc
spi_lo
; dec brne ret
temp spi_loop
;we FORCED D0=0, so use INC
to set D0.
;************************
End of SPI routines
**************************** ;**** Application example **** Reset: ser out rjmp
rcall init_spi temp ;load w/ FF DDRD,temp Main
Main: mov
ldi R22,0xA3 ;misc data spi_lo,R22 ;set up information to be
sent mov
spi_hi,R22
;COMMENT THIS OUT IF 8-BIT
rcall rcall
ena_spi rw_spi
;activate /SS ;send/receive 16 bits (or 8
rcall rcall rjmp
disa_spi use_spi_rcv Main
;deactivate /SS ;go use whatever we received
MODE
bits)
Use_spi_rcv:
;just copy rcv'd
data to Port D pins out ret
PortD,R22
;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other http://avr-asm.tripod.com/avrspi.html (1 of 2)1/20/2009 9:00:10 PM
16 BIT MATH (AVR 202)
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avrspi.html (2 of 2)1/20/2009 9:00:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR I2C MASTER PROTOCOL (AVR 300) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
multimaster ability
DIV 24 24
implementation uses, by far,
DIV 3216 FLOAT 128 SQRT16
DEC ASCII INT ASCII
FLASH CARD
;*
"single" master implementation is limited to one
;*
I2C bus. Most applications do not need the
;*
the I2C bus provides. A single master
;* ;* ;* ;*
less resources and is less XTAL frequency dependent.
;* ;* ;* ;* ;* ;*
* Supports normal and fast mode. * Supports both 7-bit and 10-bit addressing. * Supports the entire AVR microcontroller family.
Some features : * All interrupts are free, and can be used for
Main I2C functions : 'i2c_start' -
Issues a start condition
'i2c_rep_start' -
and transfer direction. Issues a repeated start
condition and sends ;*
address and transfer
direction. ;*
'i2c_do_transfer' -
Sends or receives data
depending on ;*
SER EPROM DFLASH AT45
DESCRIPTION Basic routines for communicating with I2C slave
;* ;*
COPY 102
EPROM 100
: [email protected]
and sends address
AVG8 222
LPM 108
Support email
other activities.
MATH 202
FFT7
: I2C (Single) Master Implementation : 1.0 (BETA) : 97.08.27 : AT90Sxxxx (any AVR device)
bus master on the
DIV16 XX
HX2ASC
Title Version Last updated Target
devices. This
MATH YX
MATH 202
A V R 3 0 0
************************
ASM MATH
MATH 202
N O T E
direction given in address/
dir byte. ;*
'i2c_stop' -
Terminates the data
transfer by issue a ;* stop condition. ;* ;* USAGE ;* Transfer formats is described in the AVR300
VFX SMIL VFX MEM SORT 220 documentation. CRC 236
;* (An example is shown in the 'main' code). ;* ;* NOTES ;* The I2C routines can be called either from non-
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300
interrupt or ;* interrupt routines, not both. ;* ;* STATISTICS ;* Code Size : 81 words (maximum) ;* Register Usage : 4 High, 0 Low ;* Interrupt Usage : None ;* Other Usage : Uses two I/O pins on port D ;* XTAL Range : N/A ;* ; ***************************************************************************
I2C 302
;**** Includes ****
I2C TWI26 I2C/TWI 128
.include "1200def.inc"
; change if
an other device is used
I2C/TWI AT8
;**** Global I2C Constants ****
DALLAS-1W DALLAS CRC ETHNET 8019 TEA
SCLP
= 1
; SCL Pin
.equ
SDAP
= 0
; SDA Pin
.equ
b_dir
= 0
; transfer
.equ .equ
i2crd i2cwr
= 1 = 0
number (port D) number (port D)
ADC 128 ADC 10B
.equ
direction bit in i2cadr
ADC 400 ADC 401 THERM 232
;**** Global Register Variables ****
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
i2cdelay= r16
; Delay
.def
i2cdata = r17
; I2C data
.def
i2cadr
; I2C
.def
i2cstat = r19
loop variable transfer register
;**** Interrupt Vectors ****
PS2 EMU BOOT MG8 BOOT DR8
CLOCK 8564
; I2C bus
status register
KBD PC/128
ALM CLK
= r18
address and direction register
MUX 242 KBD PS2
.def
; ;
rjmp ( rjmp ( rjmp
RESET EXT_INT0 ) TIM0_OVF )
; Reset handle ; ( IRQ0 handle ) ; ( Timer 0
;
( rjmp
ANA_COMP )
; ( Analog
overflow handle ) comparator handle )
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* FUNCTION ;* i2c_hp_delay ;* i2c_qp_delay ;* ;* DESCRIPTION ;* hp - half i2c clock period delay (normal: 5.0us / fast: 1.3us) ;* qp - quarter i2c clock period delay (normal: 2.5us / fast: 0.6us) ;* ;* SEE DOCUMENTATION !!! ;* ;* USAGE ;* no parameters ;* ;* RETURN ;* none ;* ; *************************************************************************** i2c_hp_delay: ldi i2cdelay,2 i2c_hp_delay_loop: dec i2cdelay brne i2c_hp_delay_loop ret i2c_qp_delay: ldi i2cdelay,1 i2c_qp_delay_loop: dec i2cdelay brne i2c_qp_delay_loop ret
; *************************************************************************** ;* ;* FUNCTION ;* i2c_rep_start ;* ;* DESCRIPTION ;* Assert repeated start condition and sends slave address. ;* ;* USAGE ;* i2cadr - Contains the slave address and transfer direction. ;* ;* RETURN ;* Carry flag - Cleared if a slave responds to the address. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_start. ;* ; *************************************************************************** i2c_rep_start: sbi DDRD,SCLP cbi DDRD,SDAP rcall i2c_hp_delay cbi DDRD,SCLP rcall i2c_qp_delay
; ; ; ; ;
force SCL low release SDA half period delay release SCL quarter period
delay
; *************************************************************************** ;* ;* FUNCTION ;* i2c_start ;* ;* DESCRIPTION ;* Generates start condition and sends slave address. ;* ;* USAGE ;* i2cadr - Contains the slave address and transfer direction. ;* ;* RETURN ;* Carry flag - Cleared if a slave responds to the address. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_write. ;* ; *************************************************************************** i2c_start: mov
i2cdata,i2cadr
; copy address to
DDRD,SDAP i2c_qp_delay
; force SDA low ; quarter period
transmitt register sbi rcall delay
; *************************************************************************** ;* ;* FUNCTION ;* i2c_write ;* ;* DESCRIPTION ;* Writes data (one byte) to the I2C bus. Also used for sending ;* the address. ;* ;* USAGE ;* i2cdata - Contains data to be transmitted. ;* ;* RETURN ;* Carry flag - Set if the slave respond transfer. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_get_ack. ;* ; *************************************************************************** i2c_write: sec rol
; set carry flag ; shift in carry
i2cdata
and out bit one rjmp i2c_write_first i2c_write_bit: lsl i2cdata
; if transmit
i2c_write_first: breq i2c_get_ack
;
register empty goto get
acknowledge sbi
DDRD,SCLP
; force SCL low
brcc nop
i2c_write_low
; if bit high ; (equalize
number of cycles) cbi DDRD,SDAP rjmp i2c_write_high i2c_write_low: sbi DDRD,SDAP
;
release SDA
;
; else force SDA
;
(equalize
low rjmp
i2c_write_high
number of cycles) i2c_write_high: rcall i2c_hp_delay cbi DDRD,SCLP rcall i2c_hp_delay rjmp
; half period delay ; release SCL ; half period delay
i2c_write_bit
; *************************************************************************** ;* ;* FUNCTION ;* i2c_get_ack ;* ;* DESCRIPTION ;* Get slave acknowledge response. ;* ;* USAGE ;* (used only by i2c_write in this version) ;* ;* RETURN ;* Carry flag - Cleared if a slave responds to a request. ;* ; *************************************************************************** i2c_get_ack: sbi DDRD,SCLP cbi DDRD,SDAP rcall i2c_hp_delay cbi DDRD,SCLP i2c_get_ack_wait: sbis PIND,SCLP
; ; ; ;
force SCL low release SDA half period delay release SCL
; wait SCL high ;(In case wait
states are inserted) rjmp clc sbic sec
i2c_get_ack_wait
PIND,SDAP
; clear carry flag ; if SDA is high ; set carry
i2c_hp_delay
; half period delay
flag rcall ret
; *************************************************************************** ;* ;* FUNCTION ;* i2c_do_transfer ;* ;* DESCRIPTION ;* Executes a transfer on bus. This is only a combination of i2c_read ;* and i2c_write for convenience. ;* ;* USAGE ;* i2cadr - Must have the same direction as when i2c_start was called. ;* see i2c_read and i2c_write for more information. ;* ;* RETURN ;* (depends on type of transfer, read or write) ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_read. ;* ; *************************************************************************** i2c_do_transfer: sbrs i2cadr,b_dir rjmp i2c_write
; if dir = write ; goto write
data
; *************************************************************************** ;* ;* FUNCTION ;* i2c_read ;* ;* DESCRIPTION ;* Reads data (one byte) from the I2C bus. ;* ;* USAGE ;* Carry flag If set no acknowledge is given to the slave ;* indicating last read operation before a STOP. ;* If cleared acknowledge is given to the slave ;* indicating more data. ;* ;* RETURN ;* i2cdata - Contains received data. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_put_ack. ;* ; *************************************************************************** i2c_read: rol
i2cstat
; store acknowledge ; (used by
i2c_put_ack) ldi i2cdata,0x01 i2c_read_bit: sbi DDRD,SCLP
; data = 0x01 ; do ; force SCL
low rcall
i2c_hp_delay
;
half period
cbi rcall
DDRD,SCLP i2c_hp_delay
; ;
release SCL half period
;
clear carry
;
if SDA is
delay
delay clc flag sbic
PIND,SDAP
high sec
;
set
carry flag rol
i2cdata
;
store data
brcc
i2c_read_bit
; while receive
bit register not full
; *************************************************************************** ;* ;* FUNCTION ;* i2c_put_ack ;* ;* DESCRIPTION ;* Put acknowledge. ;* ;* USAGE ;* (used only by i2c_read in this version) ;* ;* RETURN ;* none ;* ; *************************************************************************** i2c_put_ack: sbi DDRD,SCLP ror brcc
i2cstat i2c_put_ack_low
; force SCL low ; get status bit ; if bit low goto
assert low cbi DDRD,SDAP rjmp i2c_put_ack_high i2c_put_ack_low: sbi DDRD,SDAP
;
release SDA
; else ;
force SDA
low i2c_put_ack_high: rcall i2c_hp_delay cbi DDRD,SCLP i2c_put_ack_wait: sbis PIND,SCLP rjmp i2c_put_ack_wait rcall i2c_hp_delay ret
; half period delay ; release SCL ; wait SCL high ; half period delay
; *************************************************************************** ;* ;* FUNCTION ;* i2c_stop ;* ;* DESCRIPTION ;* Assert stop condition. ;* ;* USAGE ;* No parameters. ;* ;* RETURN ;* None. ;* ; *************************************************************************** i2c_stop: sbi sbi rcall cbi rcall
DDRD,SCLP DDRD,SDAP i2c_hp_delay DDRD,SCLP i2c_qp_delay
; ; ; ; ;
force SCL low force SDA low half period delay release SCL quarter period
DDRD,SDAP i2c_hp_delay
; release SDA ; half period delay
delay cbi rcall ret
; *************************************************************************** ;* ;* FUNCTION ;* i2c_init ;* ;* DESCRIPTION ;* Initialization of the I2C bus interface. ;* ;* USAGE ;* Call this function once to initialize the I2C bus. No parameters ;* are required. ;* ;* RETURN ;* None ;* ;* NOTE ;* PORTD and DDRD pins not used by the I2C bus interface will be ;* set to Hi-Z (!). ;* ;* COMMENT ;* This function can be combined with other PORTD initializations. ;* ; *************************************************************************** i2c_init: clr
i2cstat
; clear I2C status
register (used ; as a temporary register) out
PORTD,i2cstat
out ret
DDRD,i2cstat
; set I2C pins to
open colector
; *************************************************************************** ;* ;* PROGRAM ;* main - Test of I2C master implementation ;* ;* DESCRIPTION ;* Initializes I2C interface and shows an example of using it. ;* ; *************************************************************************** RESET: main:
rcall
i2c_init
;
initialize I2C interface ;**** Write data => Adr(00) = 0x55 **** ldi
i2cadr,$A0+i2cwr
; Set device
rcall
i2c_start
; Send start
ldi
i2cdata,$00
; Write word
rcall
i2c_do_transfer
; Execute transfer
ldi
i2cdata,$55
; Set write data to
rcall
i2c_do_transfer
; Execute transfer
rcall
i2c_stop
; Send stop
address and write condition and address
address (0x00)
01010101b
condition ;**** Read data => i2cdata = Adr(00) **** ldi
i2cadr,$A0+i2cwr
; Set device
rcall
i2c_start
; Send start
ldi rcall
i2cdata,$00 i2c_do_transfer
; Write word address ; Execute transfer
ldi
i2cadr,$A0+i2crd
; Set device
rcall
i2c_rep_start
; Send repeated
address and write condition and address
address and read start condition and address sec acknowledge (read is followed by a stop condition) rcall i2c_do_transfer (read)
; Set no ; Execute transfer
rcall
i2c_stop
; Send stop
rjmp
main
; Loop forewer
condition - releases bus
;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 http://avr-asm.tripod.com/avr300.html (1 of 2)1/20/2009 9:00:50 PM
16 BIT MATH (AVR 202)
have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr300.html (2 of 2)1/20/2009 9:00:50 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR I2C SLAVE PROTOCOL (AVR 302) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
FLOAT 128
INT ASCII
: [email protected]
Code Size : 160 words Low Register Usage : 0 High Register Usage : 5 Interrupt Usage : External Interrupt0, Timer/Counter0 overflow interrupt DESCRIPTION This application note shows how to implement an AVR
;*
as an I2C slave peripheral. For use with other
;*
I/O pins might have to be used, and the stack
;* ;*
initialized. Received data is stored in r0 and r0 is transmitted
;*
read transfer. This simple protocol is implemented
;* ;* ;* ;* ;*
purposes only.
;* ;* ;* ;* ;* ;*
* * * *
during a master for demonstration
AVG8 222 FFT7
Some features : * Interrupt based (using INT0 and TIM0). * The device can be given any 7-bit address.
(Expandable to 10bit).
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD
Support email
pointer might have to be
HX2ASC
COPY 102
: I2C Slave Implementation : 1.2 : 97.07.17 : AT90Sxxxx (All AVR Device) Fast Mode: AT90S1200 only
AT90S AVR devices, other
MATH 202 DEC ASCII
Title Version Last updated Target
AT90S1200 device
SQRT16 MATH 202
A V R 3 0 2
************************
ASM MATH
DIV 3216
N O T E
Supports normal and fast mode. Easy insertion of "wait states". Size and speed optimized. Supports wake-up from idle mode.
Refers to the application note AVR302 documentation
for more ;* detailed description. ;* ;* USAGE ;* Insert user code in the two locations marked
VFX SMIL VFX MEM SORT 220 "insert user code here". CRC 236
;* ;* NOTES ;* Minimum one instruction will be executed between
XMODEM REC UART 304 UART 305
each interrupt.
AVR SPI
;* ;* STATISTICS ;* Code Size : 160 ;* Register Usage : 5 High, 0 Low ;* Interrupt Usage : EXT_INT0 and TIM0_OVF ;* Port Usage : PD4(T0) and PD2(INT0) ;* XTAL : - I2C Fast Mode : min 16.0MHz ;* - I2C Standard Mode : min 3.0MHz ;* ; ***************************************************************************
I2C 300
;**** Includes ****
UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200
I2C 302 .include "1200def.inc"
I2C TWI26 I2C/TWI 128
;**** Global I2C Constants ****
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
.equ
devadr
= 0x50
; Slave device
.equ
devadrm = 0x7F
; Slave multi
.equ
pinmask = 0x14
; <=> (1<
address address mask
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
Programming the AVR Microcontrollers in Machine Language
KBD 240 MUX 242
AVR << Prev | Ring Hub | Join | Rate| Next >>
KBD PS2 KBD PC/128 PS2 EMU
© WebRing Inc.
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BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr302.html (1 of 2)1/20/2009 9:01:29 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr302.html (2 of 2)1/20/2009 9:01:29 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
I2C/TWI PROTOCOL FOR ATINY26 HOME RETRO_DAN ASM FORUM
.include "tn26def.inc"
ASM MATH TUTORIAL #1 TUTORIAL #2
.org $0000 rjmp reset ;.org INT0addr ;rjmp EXT_INT0 .org OC1Aaddr rjmp TIMER1_CMPA ;.org OVF0addr ;rjmp TIMER0_OVF0 .org USI_STARTaddr rjmp USI_STRT .org USI_OVFaddr rjmp USI_OVF
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX
;(1) ;(2) ;(4) ;(7) ;(8) ;(9)
DIV 24 24 ;Cal=0x99
DIV 3216 FLOAT 128
.equ OwnTWIAddress
=11;16
SQRT16 .equ .equ .equ .equ .equ .equ .equ .equ .equ
MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222
UserRAM USI_State AddressAndWR USI_ByteReceivedPointerLow USI_ByteReceivedPointerHigh USI_Byte0 USI_Byte1 USI_Byte2 USI_Byte3
=$0060 =UserRAM =UserRAM+1 =UserRAM+2 =UserRAM+3 =UserRAM+4 =UserRAM+5 =UserRAM+6 =UserRAM+7
FFT7 COPY 102 reset:
LPM 108 EPROM 100
;*** Init at startup ***
SER EPROM ;Clear RAM at startup clr r16 sts USI_State,r16 sts USI_Byte0,r16 sts USI_Byte1,r16 sts USI_Byte2,r16 sts USI_Byte3,r16
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236
ldi r16,RAMEND out SP,
XMODEM REC UART 304
r16
UART 305
;*** MCUCR *** ;MCU Control Register MCUCR ;Bit1,Bit0=ISC01,ISC00: Interrupt Sense Control (11=rising edge) ldi r16,(1< 40 kHz) ;xxx ldi
UART 128 UART BUFF USB 232 AVR ISP
;Setting stackpointer to RAM end
r16,255 xxx
;
ISP 2313
out OCR1C,r16
ISP 1200
;*** USI *** ;USI Control Register: USICR ;Bit7=USISIE: Start Condition Interrupt Enable ;Bit6=USIOIE: Counter Overflow Interrupt Enable ;Bit5,Bit4=USIWM1,USIWM0: Wire Mode (11=TWI) ;Bit3,Bit2=USICS1,USICS0: Clock Source Select (110=Negative edge External,
AVR SPI I2C 300 I2C 302 I2C TWI26
TWI)
I2C/TWI 128
;Bit1=USICLK: Clock Strobe ;Bit0=USITC: Toggle Clock Port Pin ldi r16,(1<
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
Programming the AVR Microcontrollers in Machine Language
LCD HD44
AVR << Prev | Ring Hub | Join | Rate| Next >>
LCD 2313 LCD44 2313 KBD 240 © WebRing Inc.
MUX 242
Search
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/ O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/ O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/twi26.html (1 of 2)1/20/2009 9:02:06 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/twi26.html (2 of 2)1/20/2009 9:02:06 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
I2C/TWI PROTOCOL FOR 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
; *************************************************************************** ; ; File Name :'twi.asm" ; Title : I2C (TWI) Hardware ; Date :2003.04.29. Lastmod.:[2003.04.29.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.04.29 VFX Creation ; ; *************************************************************************** ; ; ; ;Hardware ; *************************************************************************** ;*
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF
; ************************************************************************** ;* Const Def ; ;Bit Rate Generator in Master Mode ;TWBR = Value of the TWI Bit Rate Register ;TWPS = Value of the prescaler bits in the TWI Status Register ; ;Note: TWBR should be 10 or higher if the TWI operates in Master mode. ; If TWBR is lower than 10, the master may produce an incorrect output on SDA ; and SCL for the reminder of the byte. ; ; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255 ; ; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
USB 232 AVR ISP
.EQU .EQU
SCL_Freq = 100000 TWI_SlaveAddress = 0xFE
;Hz ;Slave Address is FECO :)
.equ .equ .equ .equ
TWI_WriteByte = 0x00 TWI_WriteRAW = 0x01 TWI_ReadByte = 0x02 TWI_ReadRAW = 0x03
;Send ;Send ;Read ;Read
ISP 2313 ISP 1200 AVR SPI I2C 300
Byte Blokk of data Byte Block of data
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; *************************************************************************** .DSEG
DALLAS-1W
TWI_CTL: TWI_Count: TWI_Slave: TWI_ADR: TWI_Flag: TWI_SADR:
DALLAS CRC ETHNET 8019 TEA ADC 128
.byte .byte .byte .byte .byte .byte
2 1 1 1 1 2
;Address of TWI IO Control Blokk ;Byte counter for TWI ;Slave Address ;Slave internal Address ;0. = 1 TWI in use ;TWI State Machin Address
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
; ************************************************************************* ;* Code ;* .CSEG
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; ************************************************************************* ;* Init TWI Device, Clear TWI_CTL ; TWI_Init: ldi R16,Low(TWIRET) sts TWI_SADR+0,R16 ldi R16,High(TWIRET) sts TWI_SADR+1,R16
PS2 EMU BOOT MG8
DELAYS CALL ID
;TWI Bit Rate
sts ldi
TWBR,R16 R16,0b00000101
;TWI Control
sts
TWCR,R16
;7 – TWINT: TWI
Register – TWCR
CLOCK 8564 90 DAYS
R16,SYSCLK/(2*SCL_Freq)-8
Register - TWBR
BOOT DR8 ALM CLK
ldi
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition
DTMF 314
;4 – TWSTO: TWI
PWM 6CH
STOP Condition
PWM 10K
Write Collision Flag
;3 - TWWC: TWI ;2 – TWEN: TWI
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
Enable ;1 – Res: Reserved Bit ;0 – TWIE: TWI Interrupt Enable
AVR BOOK
ldi
R16,0b11111000
;TWI Status
sts
TWSR,R16
;7..3 – TWS: TWI
Register – TWSR Status ;2 – Res: Reserved Bit ;1..0 – TWPS: TWI Prescaler Bits ldi
R16,TWI_SlaveAddress
sts clr sts ret
TWAR,R16 R16 TWI_Flag,R16
;TWI (Slave)
Address Register
; ************************************************************************* ;* Start TWI Comunication in Master Mode ; In: X - Address of IO_CTR Block ; ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartRead: rcall WaitToTWI ldi
R16,Low(RBlock0) sts TWI_SADR+0,R16 ldi R16,High(RBlock0) sts TWI_SADR+1,R16
sts sts sts sts sts
TWI_CTL+0,XL TWI_CTL+1,XH TWI_Count,R17 TWI_Slave,R18 TWI_ADR,R19
lds ori andi sts
R16,TWI_Flag R16,1 R16,0b11111101 TWI_Flag,R16
ldi sts
R16,0b11100101 TWCR,R16
TWI_Common:
;TWI in use! ;TWI no error
;7 – TWINT: TWI
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition ;4 – TWSTO: TWI STOP Condition ;3 – TWWC: TWI Write Collision ;2 – TWEN: TWI Enable ;1 – Res: Reserved ;0 – TWIE: TWI Interrupt Enable TWIRET: ret ; ************************************************************************* ;* Start TWI Comunication in Master Mode - Write! ; In: X - Address of IO_CTR Block ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartWrite: rcall WaitToTWI ldi
rjmp
R16,Low(WBlock0) sts TWI_SADR+0,R16 ldi R16,High(WBlock0) sts TWI_SADR+1,R16 TWI_Common
; ************************************************************************* ;* TWI interrupt ;* TWI: Interrupt Handler push ZL push ZH in ZL,SREG reg. push ZL push R16 push R0 push R17 in ZL,RAMPZ push ZL
; Two-wire Serial Interface
;preserve main OS status
lds andi
R16,TWSR R16,0b11111000
;Load TWI Status ;csak a status marad
lds
ZL,TWI_SADR+0 lds ZH,TWI_SADR+1
icall pop out pop POP POP POP OUT POP POP RETI
ZL RAMPZ,ZL R17 R0 R16 ZL SREG,ZL ZH ZL
; ************************************************************************************************************ ;*** R E A D B L O C K ;*** ; ;*********************** ; Read Block of data - State 0 ; Start bit sended RBlock0: cpi R16,0x08 ;A START condition has been transmitted breq Rbl0 cpi R16,0x10 ;A Repeated START condition has been transmitted breq Rbl0 rjmp TWI_ReadError Rbl0: lds R16,TWI_Slave andi R16,0b11111110 ;Write SLA sts TWDR,R16 ;Send Slave Address ldi
R16,Low(RBlock1) sts TWI_SADR+0,R16 ldi R16,High(RBlock1) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
RBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq RBl1 TWI_ReadError
lds sts
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(RBlock2) sts TWI_SADR+0,R16 ldi R16,High(RBlock2) sts TWI_SADR+1,R16 R16,(1< Repeated Satrt send
cpi
R16,0x28
rjmp
breq Rbl21 TWI_ReadError
RBl1: ;Send Slave
Internal Address
RBlock2: ;
SlaveAddress sended + ACK received
Rbl21: ldi
R16,Low(RBlock3) sts TWI_SADR+0,R16 ldi R16,High(RBlock3) sts TWI_SADR+1,R16
ldi
R16,(1< Send SLA+R
cpi
R16,0x10
rjmp
breq RBl31 TWI_ReadError
lds ori sts
R16,TWI_Slave R16,1 TWDR,R16
ldi
R16,Low(RBlock4) sts TWI_SADR+0,R16 ldi R16,High(RBlock4) sts TWI_SADR+1,R16
ldi
R16,(1< Read data byte
cpi
R16,0x40
RBlock3: ;Repeated
Start sended + ACK received
RBl31: ;Write SLA+R ;Send Slave
Address
RBlock4: ;SLA+R send
+ ACK received brne
TWI_ReadError
lds cpi breq
R16,TWI_Count R16,1 TWILAstByte
ldi
R16,Low(RBlock5) sts TWI_SADR+0,R16 ldi R16,High(RBlock5) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
WBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq WBl1 TWI_WriteError
lds sts
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(WBlock2) sts TWI_SADR+0,R16 ldi R16,High(WBlock2) sts TWI_SADR+1,R16 R16,(1< Write data
cpi
R16,0x28
breq rjmp
WB12 TWI_WriteError
WBl1: ;Send Slave
Internal Address
WBlock2: ;Data byte
has been transmitted + ACK received
WB12:
;
Send data byte continous lds lds ld sts
ZL,TWI_CTL+0 ZH,TWI_CTL+1 R0,Z+ TWDR,R0
sts sts
TWI_CTL+0,ZL TWI_CTL+1,ZH
lds cpi breq dec sts
R16,TWI_Count R16,1 TWI_WriteLastByte R16 TWI_Count,R16
ldi
R16,(1<
;next data
byte
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with http://avr-asm.tripod.com/twi128.html (1 of 2)1/20/2009 9:02:45 PM
16 BIT MATH (AVR 202)
multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/twi128.html (2 of 2)1/20/2009 9:02:45 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
I2C/TWI PROTOCOL FOR ATEMGA8 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
; *************************************************************************** ; ; File Name :'twi.asm" ; Title : I2C (TWI) Hardware ; Date :2003.04.29. Lastmod.:[2003.04.29.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga8 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.04.29 VFX Creation ; ; *************************************************************************** ; ; ; ;Hardware ; *************************************************************************** ;*
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF
; ************************************************************************** ;* Const Def ; ;Bit Rate Generator in Master Mode ;TWBR = Value of the TWI Bit Rate Register ;TWPS = Value of the prescaler bits in the TWI Status Register ; ;Note: TWBR should be 10 or higher if the TWI operates in Master mode. ; If TWBR is lower than 10, the master may produce an incorrect output on SDA ; and SCL for the reminder of the byte. ; ; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255 ; ; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
USB 232 AVR ISP
.EQU .EQU
SCL_Freq = 100000 TWI_SlaveAddress = 0xFE
;Hz ;Slave Address is FECO :)
.equ .equ .equ .equ
TWI_WriteByte = 0x00 TWI_WriteRAW = 0x01 TWI_ReadByte = 0x02 TWI_ReadRAW = 0x03
;Send ;Send ;Read ;Read
ISP 2313 ISP 1200 AVR SPI I2C 300
Byte Blokk of data Byte Block of data
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; *************************************************************************** .DSEG
DALLAS-1W
TWI_CTL: TWI_Count: TWI_Slave: TWI_ADR: TWI_Flag: TWI_SADR:
DALLAS CRC ETHNET 8019 TEA ADC 128
.byte .byte .byte .byte .byte .byte
2 1 1 1 1 2
;Address of TWI IO Control Blokk ;Byte counter for TWI ;Slave Address ;Slave internal Address ;0. = 1 TWI in use ;TWI State Machin Address
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
; ************************************************************************* ;* Code ;* .CSEG
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; ************************************************************************* ;* Init TWI Device, Clear TWI_CTL ; TWI_Init: ldi R16,Low(TWIRET) sts TWI_SADR+0,R16 ldi R16,High(TWIRET) sts TWI_SADR+1,R16
PS2 EMU BOOT MG8
DELAYS CALL ID
;TWI Bit Rate
out ldi
TWBR,R16 R16,0b00000101
;TWI Control
out
TWCR,R16
;7 – TWINT: TWI
Register – TWCR
CLOCK 8564 90 DAYS
R16,SYSCLK/(2*SCL_Freq)-8
Register - TWBR
BOOT DR8 ALM CLK
ldi
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition
DTMF 314
;4 – TWSTO: TWI
PWM 6CH
STOP Condition
PWM 10K
Write Collision Flag
;3 - TWWC: TWI ;2 – TWEN: TWI
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
Enable ;1 – Res: Reserved Bit ;0 – TWIE: TWI Interrupt Enable
AVR BOOK
ldi
R16,0b11111000
;TWI Status
out
TWSR,R16
;7..3 – TWS: TWI
Register – TWSR Status ;2 – Res: Reserved Bit ;1..0 – TWPS: TWI Prescaler Bits ldi
R16,TWI_SlaveAddress
out clr sts ret
TWAR,R16 R16 TWI_Flag,R16
;TWI (Slave)
Address Register
; ************************************************************************* ;* Start TWI Comunication in Master Mode ; In: X - Address of IO_CTR Block ; ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartRead: rcall WaitToTWI ldi R16,Low(RBlock0) sts TWI_SADR+0,R16 ldi R16,High(RBlock0) sts TWI_SADR+1,R16 TWI_Common: sts TWI_CTL+0,XL sts TWI_CTL+1,XH sts TWI_Count,R17 sts TWI_Slave,R18 sts TWI_ADR,R19 lds ori andi sts
R16,TWI_Flag R16,1 R16,0b11111101 TWI_Flag,R16
ldi out
R16,0b11100101 TWCR,R16
;TWI in use! ;TWI no error
;7 – TWINT: TWI
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition ;4 – TWSTO: TWI STOP Condition ;3 – TWWC: TWI Write Collision ;2 – TWEN: TWI Enable ;1 – Res: Reserved ;0 – TWIE: TWI Interrupt Enable TWIRET: ret ; ************************************************************************* ;* Start TWI Comunication in Master Mode - Write! ; In: X - Address of IO_CTR Block ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartWrite: rcall WaitToTWI ldi
rjmp
R16,Low(WBlock0) sts TWI_SADR+0,R16 ldi R16,High(WBlock0) sts TWI_SADR+1,R16 TWI_Common
; ************************************************************************* ;* TWI interrupt ;* TWI: Interrupt Handler push ZL push ZH in ZL,SREG reg. push ZL push R16 push R0 push R17
;
; Two-wire Serial Interface
;preserve main OS status
cbi
GreenLED_PORT,GreenLED
;LED
in andi
R16,TWSR R16,0b11111000
;Load TWI Status ;csak a status marad
lds
ZL,TWI_SADR+0 lds ZH,TWI_SADR+1
icall pop POP POP POP OUT POP POP RETI
R17 R0 R16 ZL SREG,ZL ZH ZL
; ************************************************************************************************************ ;*** R E A D B L O C K ;*** ; ;*********************** ; Read Block of data - State 0 ; Start bit sended RBlock0: cpi R16,0x08 ;A START condition has been transmitted breq Rbl0 cpi R16,0x10 ;A Repeated START condition has been transmitted breq Rbl0 rjmp TWI_ReadError Rbl0: lds R16,TWI_Slave andi R16,0b11111110 ;Write SLA out TWDR,R16 ;Send Slave Address ldi
R16,Low(RBlock1) sts TWI_SADR+0,R16 ldi R16,High(RBlock1) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
RBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq RBl1 TWI_ReadError
lds out
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(RBlock2) sts TWI_SADR+0,R16 ldi R16,High(RBlock2) sts TWI_SADR+1,R16 R16,(1< Repeated Satrt send
cpi
R16,0x28
rjmp
breq Rbl21 TWI_ReadError
RBl1: ;Send Slave
Internal Address
RBlock2: ;
SlaveAddress sended + ACK received
Rbl21: ldi
R16,Low(RBlock3) sts TWI_SADR+0,R16 ldi R16,High(RBlock3) sts TWI_SADR+1,R16
ldi
R16,(1< Send SLA+R
cpi
R16,0x10
rjmp
breq RBl31 TWI_ReadError
lds ori out
R16,TWI_Slave R16,1 TWDR,R16
ldi
R16,Low(RBlock4) sts TWI_SADR+0,R16 ldi R16,High(RBlock4) sts TWI_SADR+1,R16
ldi
R16,(1< Read data byte
cpi
R16,0x40
RBlock3: ;Repeated
Start sended + ACK received
RBl31: ;Write SLA+R ;Send Slave
Address
RBlock4: ;SLA+R send
+ ACK received brne
TWI_ReadError
lds cpi breq
R16,TWI_Count R16,1 TWILAstByte
ldi
R16,Low(RBlock5) sts TWI_SADR+0,R16 ldi R16,High(RBlock5) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
WBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq WBl1 TWI_WriteError
lds out
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(WBlock2) sts TWI_SADR+0,R16 ldi R16,High(WBlock2) sts TWI_SADR+1,R16 R16,(1< Write data
cpi
R16,0x28
breq rjmp
WB12 TWI_WriteError
WBl1: ;Send Slave
Internal Address
WBlock2: ;Data byte
has been transmitted + ACK received
WB12:
;
Send data byte continous lds lds ld out
ZL,TWI_CTL+0 ZH,TWI_CTL+1 R0,Z+ TWDR,R0
sts sts
TWI_CTL+0,ZL TWI_CTL+1,ZH
lds cpi breq dec sts
R16,TWI_Count R16,1 TWI_WriteLastByte R16 TWI_Count,R16
ldi
R16,(1<
;next data
byte
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer http://avr-asm.tripod.com/twi8.html (1 of 2)1/20/2009 9:03:20 PM
16 BIT MATH (AVR 202)
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/twi8.html (2 of 2)1/20/2009 9:03:20 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DALLAS 1 WIRE PROTOCOL HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII
;*********************************************************************** ;* ;* Number :Dallas 1-wire ;* File Name :"ds1wire.asm" ;* Title :Dallas 1-wire rutinok ;* Date :2000.10.15. ;* Version :0.0 ;* Support telephone :+36-70-333-4034, Old: +36-30-9541-658 ;* Support fax : ;* Support E-mail :[email protected] ;* Target MCU :AVR ;* ; ************************************************************************** ;* DESCRIPTION ;* - DS1990A security unit ;* ;* SYSCLK=3686400 Hz (T=271.267 ns) ;* ;* DS119A - Family Code (0x01) ;* 48-bit Serial Number ;* 8-bit CRC ;* ;* ; ************************************************************************** ;* Hardware Def.
INT ASCII HX2ASC AVG8 222
.EQU .equ .equ .EQU
DS1wire_PORT =PORTB DS1wire_DIR = DDRB DS1wire_PIN = PINB DS1wire = 0
.equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
DSReadROM = 0x33 DSMatchROM = 0x55 DSSkipROM = 0xCC DSSearchROM = 0xF0 DSAlarmSearch = 0xEC DSWriteScratchpad= 0x4E DSReadScratchpad = 0xBE DSCopyScratchpad = 0x48 DSConvertTemp = 0x44 DSRecall = 0xB8
.equ .equ
DSDev1990A DSDev1920
;Dallas 1-Wire bus
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC
= 0x01 = 0x10
UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
; ****************************************************************************** ;**** VARIABLES .DSEG CRC: .BYTE 1 ;DS1990A CRC GENERATOR HASZNALJA DSRD: .BYTE 9 ;Ide olvassa be a DS Chipet DSRDMem:.byte 9 ;Scrach Pad tartalma BadCRC: .BYTE 1 ;Bad CRC szamlalo
ISP 1200 AVR SPI I2C 300
; ***************************************************************************** .CSEG
I2C 302 I2C TWI26 I2C/TWI 128 ;************************************************************************ ;*********************** 1-Wire Bus ************************************* ;************************************************************************
I2C/TWI AT8 DALLAS-1W DALLAS CRC
DS1Wire_Init: clr sts sts
ETHNET 8019 TEA ADC 128 ADC 10B
cbi cbi ret
R16, CRC,R16 BadCRC,R16
ADC 400
DS1wire_PORT,DS1wire DS1wire_DIR,DS1wire
ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP
; ******************************************************************************* ;****** T O U C H R E S E T ; ******************************************************************************* ; ;Inicialization procedure "Reset and PreSence Pulses" ; ; Ez a rutin egy Reset jelet general a mikrovrzerlo ketiranyu DS_BIT nevu laban, ;a Touch Memory fele es figyeli a visszajovo PreSence jelet. ;Ha a PreSence jel megerkezett, akkor C=1 kulonben C=0 (nincs eszkoz a buszon) ; ; |-Master Rx "Presence Pulse"-| ; |---Master Reset Tx Pulse---| |----t(RSTH)---------------| ; __ t(RSTL) _____ _____ \\ ___ ; \ / \ / \ ; \_________________________/ \______/ \__ ... ; |-----|-------| ; t(PDH) t(PDL) ; t(R) <-- |-| ; ; 480us<=t(RSTL)< . t(RSTL)+t(R)<960us ; 480us<=t(RSTH)< ; 15us<=t(PDH)<=60us ; 60us<=t(PDL)<=240us ; ; C-flag = 1 DS1990A a buszon van ; = 0 DS1990A nincs a buszon ; ; R16, X
AVR BUTTERFLY
TouchReset:
AVR BOOK
SBI
DS1wire_DIR,DS1wire
ldi ldi
YL,low((480*SYSCLK)/(1000000*4)) YH,high((480*SYSCLK)/(1000000*4));loop cycle = 4 sbiw YL,1 ;[2] TR0 ;[1/2] 480us wait with data
;
1-wire = Master LOW ,
Start the reset pulse
TR0: brne low
SBI nop nop CBI CBI nop nop
DS1wire_PORT,DS1wire
;[2] ;[1]
1-wire =Active Hi
DS1wire_DIR,DS1wire DS1wire_PORT,DS1wire
;[2] ;[2] ;[1]
1-wire HI (felengedve) 1-wire = Tri-state
SBIS RJMP
DS1wire_PIN,DS1wire Short
;[1/2] ;[2]
ldi ldi RJMP sbiw BRNE
YL,low((60*SYSCLK)/(1000000*6)) YH,high((60*SYSCLK)/(1000000*6));loop cycle = 6 SBIS DS1wire_PIN,DS1wire ;[1/2] WL ;[2] Exit loop if line low YL,1 ;[2] TR1 ;[1/2] 60 us wait with data
RJMP
SHORT
ldi ldi
YL,low((240*SYSCLK)/(1000000*6)) YH,high((240*SYSCLK)/(1000000*6));loop cycle = 6 SBIC DS1wire_PIN,DS1wire ;[1/2] WH ;[2] Exit loop if line hi YL,1 ;[2] TR3 ;[1/2] us wait with data low
TR1:
ha egybol Low az rossz
low ;[2]
Line could not go low
WL:
TR3: RJMP sbiw BRNE SHORT: RET
CLC
;[1] Error ;[4]
WH: ldi ldi TR4: BRNE
YL,low((480*SYSCLK)/(1000000*4)) YH,high((480*SYSCLK)/(1000000*4)) sbiw YL,1 ;[2] TR4 ;[1/2] us wait with data low
SEC RET
;[1] RESET OK. ;[4]
; **************************************************************************** ;******* TOUCHBYTE ; **************************************************************************** ;R0-ban megadott byte-ot kikuldi a touchmemory-nak ;es szimultan beolvas egy byte-ot onnan az R1-be ;Hasznalja a R17, R16 R3, R2, X ; TouchByte: LDI BIT_LOOP: ROR RCALL ROR DEC BRNE RET TOUCHBIT: sbi
R17,8
;[1]
R1 TOUCHBIT R0 R17 BIT_LOOP
;[1] ;[3] ;[1] ;[1] ;[1/2] ;[1]
DS1wire_DIR,DS1wire
;[2] Start Window line = L,
1us <= Tlowr <= 15us ldi ldi BRNE
YL,low((2*SYSCLK)/(1000000*4)) ;[1] 2us YH,high((2*SYSCLK)/(1000000*4)) ;[1] loop cycle = 4 sbiw YL,1 ;[2] BW0 ;[1/2] eddig
SBRC CBI
R0,0 DS1wire_DIR,DS1wire
ldi ldi BRNE
YL,low((13*SYSCLK)/(1000000*4)) ;[1] 13us YH,high((13*SYSCLK)/(1000000*4)) ;[1] loop cycle = 4 sbiw YL,1 ;[2] BW1 ;[1/2]
IN BST BLD
R2,DS1wire_PIN R2,DS1wire R1,7
BW0:
BW1:
ldi ldi TCHL: BRNE CBI RET
;[1/2] ;[2]
;[1] ;[1] ;[1]
YL,low((45*SYSCLK)/(1000000*4)) ;[1] 45us YH,high((45*SYSCLK)/(1000000*4));[1] loop cycle = 4 sbiw YL,1 ;[2] TCHL ;[1/2] DS1wire_DIR,DS1wire ;[2] ;[4]
;*********************************************************************** ;....................................................................... ;Read ROM ; In: X = address ; Out: ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvas egy chippet az X-ban megadott cimre) ; ;Hasznalja a R18, R17, R16, R3, R2, R0; ;....................................................................... ReadDS: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet clr sts rcall BRCS CLC RET RDS1: LDI MOV LDI RCALL RDS2: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST ldi ldi RDS3: brne SEC RET
R16 CRC,R16 TouchReset RDS1
;CRC=0 ;ESZKOZ A BUSZON VAN
R16,DSReadROM ;SEARCH ROM COMMAND R0,R16 R19,7 ;7-SZER OLVASUNK BE TouchByte LDI R16,0xFF ;BEOLVASUNK 8 BITET R0,R16 TouchByte X+,R1 CRCGEN R19 RDS2 R16,0xFF ;BEOLVASSUK A CRC-t R0,R16 TouchByte X+,R1 YL,low((480*SYSCLK)/4000000) YH,high((480*SYSCLK)/4000000) sbiw YL,1 RDS3 ;CHIP RENDBEN
;*********************************************************************** ;....................................................................... ;Read Scratchpad ; In: X = address ; Out: ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvassa a Scratchpadot az X-ban megadott cimre) ; ;Hasznalja a R19, R18, R17, R16, R3, R2, R0; X ;....................................................................... ReadScratchpadMem: LDI XL,LOW(DSRDMem) LDI XH,HIGH(DSRDMem) ;ide olvassa DS Chipet LDI MOV RCALL
R16,DSSkipROM R0,R16 TouchByte
ldi mov RCALL clr sts
R16,DSReadScratchpad R0,R16 TouchByte R16 CRC,R16 ;CRC=0
LDI RDS2s: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST ldi ldi RDS3s: brne RET
;Skip ROM Command
R19,8 ;Read 8 byte LDI R16,0xFF R0,R16 TouchByte X+,R1 CRCGEN R19 RDS2s R16,0xFF R0,R16 TouchByte X+,R1
;BEOLVASSUK A CRC-t
YL,low((480*SYSCLK)/4000000) YH,high((480*SYSCLK)/4000000) sbiw YL,1 RDS3s
;*********************************************************************** ;....................................................................... ;Convert Temperature to digital ; In: ; Out: ;c=1 Chip convert ok ;c=0 Chip none ; ;Hasznalja a R18, R17, R16, R3, R2, R0; SWTmr0 ;....................................................................... ConvTemp: LDI R16,DSConvertTemp ;Convert T Command MOV R0,R16 RCALL TouchByte sbi sbi
DS1wire_PORT,DS1wire DS1wire_DIR,DS1wire
ldi
R16,(SYSTACK/4)*3
;1-wire port ACTIVE 'H' during convert
;most 0.75s a gyari 0.5s
helyett sts sei W1sec: sleep nop lds cpi brne
SWTmr0,R16 ;interrupt enabled!!!
R16,SWTmr0 R16,0 W1sec
cbi
DS1wire_PORT,DS1wire
cbi nop rcall ret
DS1wire_DIR,DS1wire
;1-wire port tre-stated,
external pullup
TouchReset
;************************************************************************* ;......................................................................... ; DS1990A CRC GENERATOR ;IN: R1 ;USE: R21,R20, R4,R3, R0, R18 ;......................................................................... CRCGEN: PUSH R1 LDI R20,8 LDI R18,0x18 PUSH R1 CRC_L: EOR ROR MOV BRCC EOR ZERO: sts POP SEC SBRS CLC ROR PUSH DEC BRNE POP POP RET
lds R1,R3 R1 R1,R3 ZERO R1,R18 ROR CRC,R1 R1
R3,CRC
;CRC
R1
R1,0 R1 R1 R20 CRC_L R1 R1
;************************************************************************* ;......................................................................... ; wait until Dallas 1-wire device is on bus ;IN: ;USE: ;......................................................................... EszkVan: CLI rcall TouchReset rcall ReadDS SEI brcs EszkVan ;mig eszkoz van a buszon, addig nem megy tovabb ldi
YL,low(1285)
ldi
YH,high(1285) push YL YH
;legalabb 1785 ciklusig ne legyenek a
buszon Cikl1:
push CLI rcall ReadDS SEI pop YH pop YL brcs EszkVan sbiw YL,1 brne Cikl1 ret
;ha ismet eszkoz van kezdjuk elolrol!!
;************************************************************************* ;......................................................................... ; Extend DS1920 & DS1820 temperature ;IN: ; out R23:R22 - temperature ;USE: ; ;Tc=8T-2+(8*Count-8*Remainder)/8Count ;......................................................................... ComuteT: LDI ZL,LOW(DSRDMem) LDI ZH,HIGH(DSRDMem) ;ide olvassa DS Chipet LDD LDI
dd16uL,Z+7 dd16uH,0
;CPC
LDD LDI
R22,Z+6 R23,0
;CRM
LSL ROL LSL ROL LSL ROL
dd16uL dd16uH dd16uL dd16uH dd16uL dd16uH
;8*CPC
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*CRM
SUB SBC
dd16uL,R22 dd16uH,R23
LDD LDI
dv16uL,Z+7 dv16uH,0
MOV OR BRNE LDI LDI RJMP
R0,dv16uL r0,dv16uH DIV1 R16,0 R17,0 LKI1
;CPC
;0-VAL NEM OSZTUNK
DIV1:
RCALL
div16u
;OSZTAS eredmeny az
LKI1: SBCI SBCI
CLC dres16uL,2 dres16uH,0
LDD LDD CBR
R22,Z+0 R23,Z+1 R22,1
;Temperature
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*T
ADD
R22,dres16uL
;R22,R23 a korigalt
ADC ret
R23,dres16uH
R16,R17-ben
;eredmeny-2
;Truncate 0.5C
homerseklet
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in http://avr-asm.tripod.com/dallas1.html (1 of 2)1/20/2009 9:03:56 PM
16 BIT MATH (AVR 202)
length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dallas1.html (2 of 2)1/20/2009 9:03:56 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DALLAS 1 WIRE CRC CHECK HOME RETRO_DAN ASM FORUM
I've implemented the 1-wire CRC with both calculation and table lookup.
ASM MATH
I haven't actually used it with 1-wire stuff, but for
TUTORIAL #1
some other communication.
TUTORIAL #2
These routines do 1 byte at a time, so you need to put input data into the register crc_in, and the register crc is used for the crc value. So what you typically do is the set crc to whatever init value it should have (I think it's 0 for 1-wire), and run one of these routines for each byte. And in the end register crc will contain the crc value calulated.
TUTORIAL #3 MATH 200 MATH 200b MATH 201
Calculated: dow_crc: ldi crc_bitcnt, 8 crc_loop: mov crc_data, crc_in eor crc_data, crc ror crc_data mov crc_data, crc brcc crc_zero ldi crc_temp, 0x18 eor crc_data, crc_temp crc_zero: ror crc_data mov crc, crc_data lsr crc_in dec crc_bitcnt brne crc_loop ret
MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7
Table lookup: dow_crc: ldi ZL, low(crc_tab * 2) ldi ZH, high(crc_tab * 2) eor r0, crc_in add ZL, r0 brcc crc_b1 inc ZH crc_b1: lpm ret
COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM
crc_tab: .db 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126,
SORT 220 32, 163, 253, 31, 65 CRC 236 XMODEM REC UART 304
.db 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220 .db 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98
UART 305 UART 128 UART BUFF USB 232
.db 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255 .db 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7 .db 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154
AVR ISP ISP 2313 ISP 1200
.db 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36 .db 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185 .db 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242,
AVR SPI I2C 300 I2C 302 I2C TWI26
172, 47, 113, 147, 205 .db 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80 .db 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238
I2C/TWI 128
.db 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76,
I2C/TWI AT8
18, 145, 207, 45, 115
DALLAS-1W
234, 105, 55, 213, 139
.db 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, .db 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41,
DALLAS CRC ETHNET 8019 TEA ADC 128
119, 244, 170, 72, 22 .db 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168 .db 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 Programming the AVR Microcontrollers in Machine Language
KBD PC/128 PS2 EMU
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dalcrc.html (1 of 2)1/20/2009 9:04:29 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/dalcrc.html (2 of 2)1/20/2009 9:04:29 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
ETHERNET DRIVER FOR RTL8019 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102
; *************************************************************************** ; ; File Name :"RTL8019.asm" ; Title :RTL8019AS Ethernet Controller driver ; Date :2002.11.22. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; EGZ-03002-v1 Ethernet Driver ; ; Support Devices ; RTL8019AS Ethernet Controller Card ; ; Provides functions to initialize the Realtek 8019AS, and send and retreive ; packets ; ;Ethernet Frame Header ; ; +--------------------------------------+ ; | Destination | Source | Frame | ; | Address | Address | Type | ; | (6 octets) | (6 octets) |(2 octets)| ; +--------------------------------------+ ;
LPM 108 EPROM 100
.EQU NICBASE = 0x4300h ; IRQ = 0 ; BOOTROM = none
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; ****************************************************************** ;* REALTEK CONTROL REGISTER OFFSETS ;* All offsets in Page 0 unless otherwise specified ;* All functions accessing CR must leave CR in page 0 upon exit ; ****************************************************************** ; RTL8019AS Register Def
UART 305 UART 128 UART BUFF USB 232
.EQU
NICCR
= 0x00
;Command Register R/
W ;This register is used to select register pages, ;enable or disable remote DMA operation and
AVR ISP
;issue commands.
ISP 2313 ISP 1200
.EQU
NICISR
= 0x07
;Interrupt Status
Register, R/W in Page0 ;This register reflects the
AVR SPI I2C 300 I2C 302 I2C TWI26
NIC status. The host ;reads it to determine the cause of an interrupt ;Individual bits are cleared by writing a "1"
I2C/TWI 128 I2C/TWI AT8
;into the corresponding bit. ;It must be cleared after power up.
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128
.EQU Register, W in Page0, Type=R in Page2
NICIMR
= 0x0F
;Interrupt Mask ;All bits correspond to the
bits in the ISR register ;POWER UP=all 0s. Setting individual bits will
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44
;enable the corresponding interrupts. .EQU Register, Type=W in Page0, Type=R in Page2
KBD 240 MUX 242 KBD PS2
.EQU
= 0x04
;Transmit Status
the status of a packet transmission .EQU NICRCR = 0x0C Configuration Register, Type=W in Page0, Type=R in Page2 .EQU
NICRSR
.EQU .EQU
NICCLDA0 = 0x01 NICCLDA1 = 0x02
;Receive
= 0x0C
;Receive Status
Register, Type=R in Page0
BOOT DR8
CLOCK 8564
NICTSR
;Transmit
;This register indicates
BOOT MG8
ALM CLK
;Data Configuration
Register, Type=R in Page0
KBD PC/128 PS2 EMU
= 0x0E
.EQU NICTCR = 0x0D Configuration Register, Type=W in Page0, Type=R in Page2
LCD 2313 LCD44 2313
NICDCR
;Current Local DMA
Registers Type=R in Page0 ;These two registers can be read to get the ;current local DMA address.
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
.EQU Register, Type=W in Page0, Type=R in Page 2
NICPSTART = 0x01
;Page Start ;The Page Start register
sets the start page ;address of the receive buffer ring
PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
.EQU Register, Type=W in Page0, Type=R in Page2
NICPSTOP = 0x02
;Page Stop ;The Page Stop register
sets the stop page ;address of the receive buffer ring. In 8 bit ;mode the PSTOP register should not exceed ;to 0x60, in 16 bit mode the PSTOP register ;should not exceed to 0x80. .EQU
NICBNRY = 0x03
;Boundary Register,
Type=R/W in Page0 ;This register is used to prevent overwrite ;of the receive buffer ring. It is typically ;used as a pointer indicating the last receive ;buffer page the host has read. .EQU
NICTPSR = 0x04
;Transmit Page
Start Register, Type=W in Page0 ;This register sets the start page address of the ;packet to the transmitted .EQU .EQU
NICTBCR0 = 0x05 NICTBCR1 = 0x06
;Transmit Byte
Count Registers, Type=W in Page0 ;These two registers set the byte counts of the ;packet to be transmitted. .EQU
NICNCR
= 0x05
;Number of
Collisions Register, Type=R in Page0 ;The register records the number of collisions ;a node experiences during a packet transmission. .EQU
NICFIFO = 0x06
;First In First Out
Register, Type=R in Page0 ;This register allows the host to examine ;the contents of the FIFO after loopback. .EQU .EQU
NICCRDA0 = 0x08 NICCRDA1 = 0x09
;Current Remote DMA
Address registers, Type=R in Page0 ;These two registers contain the current address of remote DMA. .EQU .EQU
NICRSAR0 = 0x08 NICRSAR1 = 0x09
;Remote Start
Address Registers, Type=W in Page0 ;These two registers set the start address of ;remote DMA. .EQU .EQU
NICRBCR0 = 0x0A NICRBCR1 = 0x0B
;Remote Byte Count
Registers, Type=W in Page0 ;These two registers se the data byte counts of ;remote DMA. .EQU Error Tally Counter Register, Type=R in Page0
NICCNTR0 = 0x0D
;Frame Alignment
.EQU
NICCNTR1 = 0x0E
;CRC Error Tally
.EQU Tally Counter Register, Type=R in Page0
NICCNTR2 = 0x0F
;Missed Packet
NICPAR0 NICPAR1 NICPAR2 NICPAR3 NICPAR4 NICPAR5
;Physical Address
Counter Register, Type=R in Page0
.EQU .EQU .EQU .EQU .EQU .EQU
= = = = = =
0x01 0x02 0x03 0x04 0x05 0x06
Registers, Type=R/W in Page1 ;These registers contain my Ethernet node address ;and are used to compare the destination adderss ;of incoming packets for acceptation or rejection .EQU
NICCURR = 0x07
;Current Page
Register, Type=R/W in Page1 ;This register points to the page address of ;the first receive buffer page to be used for ;a packet reception. .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU
NICMAR0 NICMAR1 NICMAR2 NICMAR3 NICMAR4 NICMAR5 NICMAR6 NICMAR7
= = = = = = = =
0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
;Multicast Address
Register, Type=R/W in Page1 ;These registers provide filtering bits of ;multicast addresses hashed by the CRC logic .EQU .EQU .EQU
NICCR9346 = 0x01 NICRDMAPORT = 0x10 NICRSTPORT = 0x18
;Page 3
; ***************************************************************************** ; ; RTL ISR Register Bits ; ; ****************************************************************************/ .EQU ISR_RST = 7 .EQU ISR_RDC = 6 .EQU ISR_OVW = 4 .EQU ISR_PTX = 1 .EQU ISR_PRX = 0
; ***************************************************************************** ; ; RTL Register Initialization Values ; ; **************************************************************************** ;RCR : accept broadcast packets and packets destined to this MAC ; drop short frames and receive errors .equ RCR_INIT = 0x04 ;TCR : default transmit operation - CRC is generated .equ
TCR_INIT = 0x00 ;DCR : allows send packet
to be used for packet retreival ;
FIFO threshold: 8-
;
8-bit transfer mode
bits (works) .equ
DCR_INIT = 0x58 ;IMR : interrupt enabled
for receive and overrun events .equ
IMR_INIT = 0x11 ;buffer boundaries -
transmit has 6 256-byte pages ;
receive has 26 256-byte
;
entire available packet
pages buffer space is allocated .equ .equ .equ
TXSTART_INIT = 0x40 RXSTART_INIT = 0x46 RXSTOP_INIT = 0x60
; ********************************************************* ;* Receive RTL8019's Ring Buffer Page Header Layout ;* This is the 4-byte header that resides infront of the ;* data packet in the receive buffer. ; ********************************************************* .equ enetpacketstatus= 0x00 .equ nextblock_ptr = 0x01 .equ enetpacketLenL = 0x02 .equ enetpacketLenH = 0x03
; LANBUFSIZE: The size of the buffer that holds incoming and outgoing packets. .equ
LANBUFSIZE = 1564
; ***************************************************************************** ; ; Ethernet constants ; ; **************************************************************************** .equ ETHERNET_MIN_PACKET_LENGTH = 0x3C .equ ETHERNET_HEADER_LENGTH = 0x0E .equ .equ
IP_TCP_HEADER_LENGTH = 40 TOTAL_HEADER_LENGTH = IP_TCP_HEADER_LENGTH
+ETHERNET_HEADER_LENGTH
; *************************************************************************** .ESEG ; ETHADDR: The Ethernet address ; 48 bit IEEE OUI (Organizationally Unique Identifier) EETHADDR:
.db
"DEDO",0x00,0x01
; *************************************************************************** .DSEG ; packet[LANBUFSIZE] ; ; The packet array is used to hold incoming and outgoing packets. ; The device driver fills this with incoming packets. pageheader: .byte 4
;Rx RTL8019's page
header packet: nextPage:
.byte LANBUFSIZE .byte 1
;RTL8019's page
header -> next page currentRetreiveAddress:
.byte 2
;innen kell
a kilvasast folytatni (pointer)
;pointers to locations in the RTL8019 receive buffer uip_len: .byte 2 ETHADDR:
.byte 6
; *************************************************************************** .CSEG ;***************************************************** ;** SetLANToActive ;** ;** IN: ;** ;** Out: ;* ;* Alt: R16 ;* ;* Description: Sets LAN to Active & SRAM to Inactive ;* ; SetLANToActive: SBI RAMCS_PORT,RAMCS nop CBI LANCS_PORT,LANCS nop ret ;***************************************************** ;** SetLANToInactive ;** ;** IN: ;** ;** Out: ;* ;* Alt: R16 ;* ;* Description: Sets LAN to Inactive LANCS=H ;* ; SetLANToInactive: SBI LANCS_PORT,LANCS nop ret
;***************************************************** ;** SetISAReset ;** ;** IN: R0 -> 1 ISA Reset, 0 Normal mode ;** ;** Out: ;* ;* Alt: ;* ;* Description: Sets ISA RESET Line to R0; 0 = low, 1 = hi ;* ; SetISAReset: sbrs sbrc
R0,0 CBI R0,0 SBI
LANRES_PORT,LANRES LANRES_PORT,LANRES
nop ret ;***************************************************** ;** Wait1ms ;** ;** In: R16 - 16*1ms varakozas ;** ;** Out: ;** ;** ;** Alt R16, XL,XH ;** ;** Description: wating for R16 * 1 ms ;* Wait1ms: ldi XL,low(SYSCLK/(5*1000)) ldi Xh,high(SYSCLK/(5*1000)) Waitx1: sbiw XL,1 ;[2] \ nop ;[1] - 5 cycles in loop brne dec brne ret
Waitx1 R16 Wait1ms
;[2] /
;****************************************************** ;** RTLHW_Reset ;** ;** In: ;** ;** Out: ;** ;** ALt: R0, R16, XL, XH ;** ;** Description: Power-up initialization of the RTL8019 and ISA ;* RTLHW_Reset: rcall clr inc rcall ldi rcall
SetLANToInactive R0 R0 SetISAReset R16,10 Wait1ms
clr rcall ret
R0 SetISAReset
;10ms
warakozas
; ***************************************************************************** ;** RTLreadReg ;** ;** IN: R16 - RTL_ADDRESS offset ;** ;** Out: R17 - register data ;** ;** Alt: ;** ;** Description: Reads byte from RTL8019 register ;* RTLReadReg: rcall SetLANToActive push XL push XH ldi XL,low(NICBASE) add XL,R16 ldi XH,high(NICBASE) ldi R17,0 adc XH,R17 = NIC real address to ISA ld R17,X rcall SetLANToInactive pop XH pop XL ret ; ***************************************************************************** ;** RTLWriteReg ;** ;** IN: R16 - RTL_ADDRESS offset ;** R17 - RTL_DATA ;** ;** Out: ;** ;** Alt: R0 ;** ;** Description: Writes byte to RTL8019 register. ;* RTLWriteReg: rcall SetLANToActive push XL push XH clr R0 ldi XL,low(NICBASE) add XL,R16 ldi XH,high(NICBASE) adc XH,R0 = NIC real address to ISA st X,R17 rcall SetLANToInactive pop XH pop XL ret
;X
;X
; *********************************************************************** ;** RTL8019_Init ;** ;** IN: ;** ;** Out: ;** ;** ALt: R0, R16, XL, XH ;** ;* Description: Sets up the RTL8019 NIC hardware interface, and initializes ;* the buffers and configuration of the NIC ; RTL8019_Init: rcall RTLHW_Reset ;do soft reset & clear pending interrupt ldi R16,NICISR ;clear Interrupt register rcall RTLReadReg ldi R16,NICISR rcall RTLWriteReg ldi
R16,50
;50ms
rcall
Wait1ms
ldi
R16,NICCR
;stop the
ldi rcall ldi rcall
R17,0x21 RTLWriteReg R16,2 Wait1ms
;Delay 2ms ;make sure
ldi ldi
R16,NICCR R17,0xC0
;select
rcall
RTLWriteReg
ldi
R16,NICCR9346
ldi rcall
R17,0xC0 RTLWriteReg
ldi ldi
R16,0x04 R17,0b10000000
rcall
RTLWriteReg
ldi ldi
R16,0x05 R17,0b00100000
rcall
RTLWriteReg
ldi ldi
R16,0x06 R17,0b00010000
rcall
RTLWriteReg
ldi ldi rcall
R16,0x0D R17,0x00 RTLWriteReg
ldi ldi rcall
R16,NICCR9346 R17,0x00 RTLWriteReg
;End Config
ldi
R16,NICCR
;stop the
ldi rcall
R17,0x01 RTLWriteReg
varakozas
NIC, abort DMA, page 0
nothing is coming in or going out
;
CONFIGx
Page3
;Enable SW
Config
;IRQ0, Base
0x300
;
AutoDetect, ROM Disabled
;
Halfduplex, LED0 - link, LED1 - RX led2 - TX
; !!!!
NIC, page 0
ldi ldi Normal Operation, FIFO Treshold, Auto Init Remote rcall
R16,NICDCR R17,DCR_INIT
ldi ldi rcall ldi rcall
R16,NICRBCR0 R17,0x00 RTLWriteReg R16,NICRBCR1 RTLWriteReg
;Remote DMA
ldi ldi
R16,NICRCR R17,0x04
;only
rcall
RTLWriteReg
;
ldi ldi
R16,NICTPSR R17,TXSTART_INIT
;Transmit
rcall
RTLWriteReg
ldi ldi
R16,NICTCR R17,0x02
rcall
RTLWriteReg
ldi ldi
R16,NICPSTART R17,RXSTART_INIT
;page
rcall ldi
RTLWriteReg R16,NICBNRY
;utolso
rcall
RTLWriteReg
ldi ldi
R16,NICPSTOP R17,RXSTOP_INIT
rcall
RTLWriteReg
ldi ldi
R16,NICCR R17,0x61
;Stop &
rcall ldi
RTLWriteReg R16,2
;2ms
rcall
Wait1ms
ldi ldi
R16,NICCURR R17,RXSTART_INIT
rcall
RTLWriteReg
ldi
ZL,low(EETHADDR)
;MAC
ldi call sts mov ldi
ZH,high(EETHADDR) EERead ETHADDR+0,R0 R17,R0 R16,NICPAR0
;Setup our
rcall
RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+1,R0 R17,R0 R16,NICPAR1 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+2,R0 R17,R0 R16,NICPAR2 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+3,R0 R17,R0 R16,NICPAR3 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+4,R0 R17,R0 R16,NICPAR4 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+5,R0 R17,R0 R16,NICPAR5 RTLWriteReg
ldi ldi
R16,NICCR R17,0x21
rcall
RTLWriteReg
ldi ldi
R16,NICDCR R17,DCR_INIT
rcall
RTLWriteReg
ldi ldi
R16,NICCR R17,0x22
rcall
RTLWriteReg
ldi ldi rcall
R16,NICISR R17,0xFF RTLWriteReg
;Clear
ldi ldi
R16,NICIMR R17,IMR_INIT
;11,
rcall
RTLWriteReg
;packet
;0x58
RTLWriteReg
Byte Count =0x0000
packets with broadcast destination address are accepted
Page Start Register=40
;Internal
loopback
address of the receive buffer ring = 46
olvasott page = 46
;stop page
address of the receive buffer ring = 60
Abort DMA
varakozas
;Rx Page =
46
address from EEPROM
MAC Address
;Stop NIC,
Abort DMA
;58 Normal
operation...
;Start
Command, DMA abort
pending Interrupt
Interrupt Enable received with no errors ;receive buffer has been exhausted ldi ldi
R16,NICTCR R17,TCR_INIT
rcall
RTLWriteReg
ldi ldi rcall
R16,NICCR R17,0x22 RTLWriteReg
;00 -
Normal operation
;start the
NIC ret
; *********************************************************************** ;** RTL8019endPacketSend ;** ;** In : ;** ;** ;** Alt : ;** ;* Description: Ends a packet send operation and instructs the NIC to transmit ;* the frame over the network ; RTL8019endPacketSend: ldi R16,NICCR ;send the contents of the transmit buffer onto the network ldi R17,0x24 rcall RTLWriteReg ;clear the remote DMA interrupt ldi R16,NICISR ldi R17,(1< sendPacketLength push R16 ;R17:R16 - > packetLength ldi ldi rcall
packf: transmitting a packet - wait for it to finish
R16,NICCR R17,0x22 RTLWriteReg
ldi
;start the NIC
R16,NICCR
rcall
RTLReadReg
andi brne
R17,0x04 packf
;still
;while( readRTL(CR)
& 0x04 );
;load beginning page for transmit buffer ldi ldi rcall
R16,NICTPSR R17,TXSTART_INIT RTLWriteReg ;set start address
for remote DMA operation ldi ldi rcall ldi ldi rcall
R16,NICRSAR0 R17,0x00 RTLWriteReg R16,NICRSAR1 R17,0x40 RTLWriteReg ;clear the packet
stored interrupt ldi ldi
R16,NICISR R17,(1<= RXSTOP_INIT) || (bnry <
ldi ldi rcall ldi ldi rcall ldi ldi rcall ldi ldi rcall clc ret
R16,NICBNRY R17,RXSTART_INIT RTLWriteReg R16,NICCR R17,0x62 RTLWriteReg R16,NICCURR R17,RXSTART_INIT RTLWriteReg R16,NICCR R17,0x22 RTLWriteReg
ldi
R16,NICRBCR0
;initiate
ldi rcall ldi ldi rcall
R17,0x04 RTLWriteReg R16,NICRBCR1 R17,0x00 RTLWriteReg
;Remote
ldi ldi rcall ldi mov rcall
R16,NICRSAR0 R17,0x00 RTLWriteReg R16,NICRSAR1 R17,R20 RTLWriteReg
;Remote
ldi ldi rcall
R16,NICCR R17,0x0A RTLWriteReg
;Start
ldi
R18,4
;4 byte-ot
ldi ldi
XL,Low(pageheader) XH,high(pageheader)
;ide
rcall st dec brne
ldi R16,NICRDMAPORT RTLReadReg X+,R17 R18 Getph
ldi
R16,NICCR
ldi rcall
R17,0x22 RTLWriteReg
rcall
WaitToDMA
lds lds
ZL,pageheader+enetpacketLenL ZH,pageheader+enetpacketLenH
;
lds
R16,pageheader+nextblock_ptr
;
sts
nextPage,R16
;
ldi sts sts
R17,4 currentRetreiveAddress+0,R17 currentRetreiveAddress+1,R20
;
RXSTART_INIT)) invpointer:
;Z= meg
mindig 0!! jopointer: DMA to transfer the RTL8019 packet header
Byte Count = 4
start address= Start boundary page
Remote Read DMA
olvasunk be
Getph:
;end the
DMA operation
Z=rxlen
nextPage eltaroljuk ,aborthoz kell
innen folytatjuk majd a kiolvasast (offset cim) ;if the nextPage pointer is invalid, the packet is not ready yet - exit ldi cp brsh ldi cp brcs
R18,RXSTOP_INIT R16,R18 pageErr1 R18,RXSTART_INIT R16,R18 pageErr1 ;if((nextPage >=
clr sub sbc sec ret
R18 ZL,R17 ZH,R18
clr clr clc ret
Zl ZH
RXSTOP_INIT) || (nextPage < RXSTART_INIT))
pageErr1:
;rxlen-4
; ***************************************************************************** ; Device Manager ; A foprogrambol ezek hivhatoak ; ***************************************************************************** ;* RTL8019dev_send ;* ;* In: ;* ;* Out:
http://avr-asm.tripod.com/ethnet8019.html (1 of 2)1/20/2009 9:05:10 PM
16 BIT MATH (AVR 202)
;* ;* Alt: ;* ;* Description:
Sends the packet contained in
packet over the network ; RTL8019dev_send: ldi ldi RTL8019dev_sendA: push push rcall
R16,low(LANBUFSIZE) R17,high(LANBUFSIZE) R16 R17 RTL8019beginPacketSend
;send packet, using data in ip_appdata if over the IP+TCP header size ldi ldi pop pop rcall
XL,Low(packet) XH,high(packet) ZH ZL RTL8019sendPacketData
rcall ret
RTL8019endPacketSend
; ***************************************************************************** ;* RTL8019dev_poll ;* ;* In: ;* ;* Out: Z = Length of the packet retreived, or zero if no packet retreived ;* Y = Address of retreived packet ;* c flag = 0, no packet ;* ;* Description: Polls the RTL8019 looking for an overflow condition or a new ;* packet in the receive buffer. If a new packet exists and will ;* fit in packet, it is retreived, and the length is returned. ;* A packet bigger than the buffer is discarded ; *****************************************************************************/ ; RTL8019dev_poll: rcall RTL8019beginPacketRetreive ;Z = packetLength brcs Vanpacket2 ;if there's no packet or an error ;exit without ending the operation ret Vanpacket2: cpi ZL,low(LANBUFSIZE+1) ldi R16,high(LANBUFSIZE+1) ;drop anything too big for the buffer cpc ZH,R16 brcs PacketSizejo ;Ezt el kell dobni, tul nagy rcall RTL8019endPacketRetreive clr ZL clr ZH clc ret PacketSizejo: push packet data into the IP packet buffer push ldi ldi rcall rcall pop pop sts sts ldi ldi sec ret
ZL
;copy the
ZH XL,low(packet) XH,high(packet) RTL8019retreivePacketData RTL8019endPacketRetreive ZH ZL pageheader+enetpacketLenL,ZL pageheader+enetpacketLenH,ZH YL,low(packet) YH,high(packet)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/ethnet8019.html (2 of 2)1/20/2009 9:05:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
TEA PROTOCOL HOME RETRO_DAN ;(C)2005 wek http://www.efton.sk ;free for personal use ;for commercial use, please contact [email protected]
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2
;implementation of original TEA algorithm by Needham&Wheeler for AVR ;
TUTORIAL #3 MATH 200 MATH 200b
;uses 8 bytes of SRAM (input/output data) and 14 registers ;!!! uses reordered key !!! ;;!!! reordered key !!! k[1]k[0]k[3]k[2]
MATH 201 MATH 202 MATH 32X
;6861 cycles ;5E=94 words = 188 bytes, excl. key ;no stack
MATH YX DIV16 XX DIV 24 24 DIV 3216
;key can be easily placed into SRAM - replace lpm xxx,Z + by ld xxx,Z+
FLOAT 128 SQRT16
;for devices which don't support lpm xxx,Z+ replace it by lpm; mov xxx,r0
MATH 202 .dseg
MATH 202 DEC ASCII
ydata: zdata:
INT ASCII HX2ASC
.byte .byte
4 4
;register definitions .def ZL .def ZH .def YL = r28 .def YH = r29
AVG8 222 FFT7 COPY 102
= r30 = r31
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
.def .def .def .def .def .def .def .def .def
tmp0 tmp1 tmp2 tmp3 tmp4 tmp5 tmp6 tmp7 tmp8
= = = = = = = = =
r1 r2 r3 r4 r5 r6 r7 r8 r9
.def .def .def .def
sum0 sum1 sum2 sum3
= = = =
r16 r17 r18 r19
.def
RoundCnt
= r20
UART 305 UART 128 UART BUFF
.cseg
USB 232
Tea:
AVR ISP
ldi RoundCnt,2*32 clr sum0 clr sum1 clr sum2 clr sum3 ldi YL,LOW(zdata) ldi YH,HIGH(zdata) ldd tmp0,Y+0 ldd tmp1,Y+1 ldd tmp2,Y+2 ldd tmp3,Y+3 TeaRound: ldi ZL,LOW(Key*2) ldi ZH,HIGH(Key*2) subi sum0,$47 sbci sum1,$86 sbci sum2,$C8 sbci sum3,$61 TeaSubRound: clr tmp4 ;z>>5 but as (z<<3)>>8
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B
(simultaneously preparing for z<<4) lsl rol rol rol rol lsl rol rol rol rol lsl rol rol rol rol
tmp0 tmp1 tmp2 tmp3 tmp4 tmp0 tmp1 tmp2 tmp3 tmp4 tmp0 tmp1 tmp2 tmp3 tmp4
lpm
tmp5,Z+
add lpm adc lpm adc lpm adc
tmp5,tmp1 tmp6,Z+ tmp6,tmp2 tmp7,Z+ tmp7,tmp3 tmp8,Z+ tmp8,tmp4
lsl rol rol rol lpm add lpm adc lpm adc lpm adc
tmp0 ;last shift for z<<4 tmp1 tmp2 tmp3 tmp4,Z+ ;z<<4 + key[0] tmp0,tmp4 tmp4,Z+ tmp1,tmp4 tmp4,Z+ tmp2,tmp4 tmp4,Z+ tmp3,tmp4
eor eor eor eor
tmp5,tmp0 tmp6,tmp1 tmp7,tmp2 tmp8,tmp3
;xor the first two parts
ldd ldd ldd ldd add adc adc adc
tmp0,Y+0 tmp1,Y+1 tmp2,Y+2 tmp3,Y+3 tmp0,sum0 tmp1,sum1 tmp2,sum2 tmp3,sum3
;z+sum
eor eor eor eor
tmp0,tmp5 tmp1,tmp6 tmp2,tmp7 tmp3,tmp8
ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
;!!! reordered key !!! k[1]k[0]k[3]k
[2]
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS
;z>>5 + key[1]
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
sbrc RoundCnt,0 increment sum (AVR: decrement by its neg) rjmp TeaRoundX3 ldi YL,LOW(ydata) add the calculated value in tmp (and it remains valid for the subround, too) ldi YH,HIGH(ydata) rjmp TeaRoundX4 TeaRoundX3: ldi YL,LOW(zdata) set pointer to zdata ldi YH,HIGH(zdata) TeaRoundX4: ldd
tmp4,Y+0
add std ldd adc std ldd adc std ldd adc std
tmp0,tmp4 Y+0,tmp0 tmp4,Y+1 tmp1,tmp4 Y+1,tmp1 tmp4,Y+2 tmp2,tmp4 Y+2,tmp2 tmp4,Y+3 tmp3,tmp4 Y+3,tmp3
;in the first subround
;and set pointer to ydata to next
;in the second subround only
;add the calculated value to
y or z
dec RoundCnt brne TeaRoundA ret TeaRoundA: sbrs RoundCnt,0 rjmp TeaRound rjmp TeaSubRound
Key: ;
.db .db .db .db .db
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 $0f,$1e,$2d,$3c $4b,$5a,$69,$78 $87,$96,$a5,$b4 $c3,$d2,$e1,$f0
Programming the AVR Microcontrollers in Machine Language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/tea.html (1 of 2)1/20/2009 9:05:44 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/tea.html (2 of 2)1/20/2009 9:05:44 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
ANALOG TO DIGITAL COMPARATOR (AVR 128) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2
MATH 201 MATH 202 some features of the
;* AVR's on-board precision Analog Comparator. ;* ;* The Application note is written as a program example
MATH YX performing the
DIV 24 24
;* following tasks: ;* ;* - Wait for a positive output edge by polling the
DIV 3216 FLOAT 128
comparator output ;* - Wait for a positive output edge by polling the
SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
Setup and Use the Analog Comparator 1.1 97.07.04 AT90Sxxxx (Devices with Analog
;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION: ;* This Application note shows how to enable and use
MATH 200b
DIV16 XX
Title: Version: Last updated: Target:
Comparator)
MATH 200
MATH 32X
A V R 1 2 8
************************
ASM MATH
TUTORIAL #3
N O T E
interrupt flag ;* - Enable interrupt on comparator output toggle. The interrupt routine ;*
increments a 16 bit register counter each time it
is executed ;* ; ***************************************************************************
AVG8 222 .include "1200def.inc"
FFT7 COPY 102
;***** Global Register Variables
LPM 108 EPROM 100
FLASH CARD
temp
=r16
;temporary storage
.def
cntL
=r17
;register counter
.def
cntH
=r18
;register counter
register
SER EPROM DFLASH AT45
.def
low byte high byte
VFX SMIL
;***** Interrupt Vectors
VFX MEM rjmp
SORT 220 CRC 236
;Reset Handle
ACIaddr ANA_COMP
;Analog Comparator Handle
.org
RESET
rjmp
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
; *************************************************************************** ;* ;* "ANA_COMP" ;* ;* This interrupt routine is served each time ACI in the ACSR register is ;* set, provided that the Analog Comparator interrupt is enabled (ACIE is ;* set). The routine increments a 16-bit counter each time it is run ;* ;* Number of words :5 ;* Number of cycles :8 ;* Low registers used :1 (ac_tmp) ;* High registers used :2 (cntL,cntH) ;* ; ***************************************************************************
DALLAS CRC ;***** Interrupt Routine Register Variables
ETHNET 8019
.def
TEA ADC 128
ac_tmp
=r0
;temporary storage
register for SREG
ADC 10B
;***** Code
ADC 400
ANA_COMP:
ADC 401 THERM 232
in
ac_tmp,SREG
;temporarily store the
subi sbci out reti
cntL,low(-1) cntH,high(-1) SREG,ac_tmp
;counter = counter + 1 ;restore Status register
Status register
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
; *************************************************************************** ;* ;* PROGRAM EXECUTION STARTS HERE ;* ; ***************************************************************************
BOOT DR8 RESET:
ALM CLK CLOCK 8564
;***** Include if used on device with RAM ; ldi temp,low(RAMEND) ; out SPL,temp ; ldi temp,high(RAMEND) ; out SPH,temp
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* "wait_edge1" ;* ;* This piece of code waits until the output of the comparator (the ACO-bit ;* in ACSR) goes high. This way of doing it requires no setup, however, ;* extremely short pulses can be missed, since the program runs three clock ;* cycles between each time the comparator is checked. Another disadvantage ;* is that the program has to wait for the output to be come negative first, ;* in case the output is positive when polling starts. ;* ;* Number of words :4 ;* Number of cycles :4 per loop. Response time: 3 - 5 clock cycles ;* Low registers used :None ;* High registers used :None ;* ; *************************************************************************** ;***** Code wait_edge1: sbic rjmp we1_1: rjmp
ACSR,ACO ;if output is high wait_edge1 ; wait sbis ACSR,ACO ;if output is low we1_1 ; wait
; *************************************************************************** ;* ;* "wait_edge2" ;* ;* This piece of code waits until the output of the comparator (the ACO-bit ;* in ACSR) goes high. This is a more secure solution, since the interrupt ;* flag is polled. This allows the user to insert code within the wait loop ;* because hardware "remembers" pulses of shorter duration than the polling ;* interval. Another positive feature is that there is no need to wait for ;* a preceeding negative edge. ;* ;* Number of words :5 ;* Number of cycles :Inital setup :2 ;* Flag clearing:1 ;* Loop :4 ;* Response time:3 - 5 ;* Low registers used :None ;* High registers used :None ;* ; *************************************************************************** ;***** Code wait_edge2: ;***** Initial Hardware setup (assumes ACIE = 0 from reset) sbi sbi
ACSR,ACIS0 ACSR,ACIS1
;enable interrupt on rising
ACSR,ACI
;write a "1" to the ACI
output edge ;***** Wait sbi flag to clear it we2_1: sbis rjmp
;----------------------- user code goes here ACSR,ACI ;if ACI is low we2_1 ; wait more
; *************************************************************************** ;* ;* "ana_init" ;* ;* This code segment enables Analog Comparator Interrupt on output toggle. ;* The program then enters an infinite loop. ;* The 16-bit counter is cleared prior to enabling the interrupt. ;* ;* Performance figures apply to interrupt initialization only. ;* ;* Number of words :4 ;* Number of cycles :5 ;* Low registers used :None ;* High registers used :1 (temp) ;* ; *************************************************************************** ;***** Register Variables .def
temp
=r16
;temporary register
;***** Code ana_init: ;***** Clear 16-bit counter clr clr
cntL cntH
;***** Enable Interrupt (assumes ACIE = 0 from reset) ldi
temp,(ACI<<1)
;clear interrupt flag and
out
ACSR,temp
;...to select interrupt on
sei sbi
ACSR,ACIE
;enable global interrupts ;enable Analog Comparator
ACIS1/ACIS0... toggle
interrupt forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr128.html (1 of 2)1/20/2009 9:06:20 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr128.html (2 of 2)1/20/2009 9:06:20 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
10 BIT ANALOG TO DIGITAL COMPARATOR FOR 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236
; *************************************************************************** ; ; File Name :'adc.asm" ; Title :ATmega128 internal 10-bit ADC Driver ; Date :2003.08.03. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AVR ; ; *************************************************************************** ; D E S C R I P T I O N ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.08.03 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ; ; ************************************************************************** ;* Hardware Def. ; ; *************************************************************************** ;**** VARIABLES .DSEG
XMODEM REC ;egymas utan kell aljanak!!!! ADCCH0: .byte 2 ADCCH1: .byte 2 ADCCH2: .byte 2 ADCCH3: .byte 2 ADCCH4: .byte 2 ADCCH5: .byte 2 ADCCH6: .byte 2 ADCCH7: .byte 2
UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302
; *************************************************************************** .ESEG
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG
TEA ADC_Init:
ADC 128 ADC 10B ADC 400
clr ldi
R16 R17,16
ldi ldi dec brne
ZL,low(ADCCH0) ZH,high(ADCCH0) st Z+,R16 R17 ADCI1
ldi out
R16,0b00000000 ADMUX,R16
;2*8 csatorna
valtozoterulet = 0
ADC 401 ADCI1:
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
Reference Selection Bits ; REFS1 REFS0 Vref Selection
BOOT MG8
CLOCK 8564 90 DAYS
; 0
1
; 1
0
; 1
1
Reserved Internal 2.56V Voltage Reference with external capacitor at AREF pin ;[5] - ADLAR: ADC Left Adjust Result ;[4:0] - MUX4:0: Analog Channel and Gain Selection Bits
DELAYS CALL ID
0
AVCC with external capacitor at AREF pin
BOOT DR8 ALM CLK
; 0 AREF, Internal Vref turned off
KBD PC/128 PS2 EMU
;[7:6] - REFS1:0:
; MUX4..0 Single Ended Input ; ; ; ; ; ; ; ;
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
00000 00001 00010 00011 00100 00101 00110 00111
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
ATMEL CORP AVR BUTTERFLY
ldi out
R16,0b00011111 ADCSRA,R16
;[7] - ADEN: ADC
Enable ;[6] - ADSC: ADC
AVR BOOK Start Conversion
;[5] - ADFR: ADC Free Running Select ;[4] - ADIF: ADC Interrupt Flag ;[3] - ADIE: ADC Interrupt Enable ;[2:0] - ADPS2:0: ADC Prescaler Select Bits ;ADPS2 ADPS1 ADPS0 Division Factor 0 1 0 1 0 1 0 1
;
0
0
;
0
0
;
0
1
;
0
1
;
1
0
;
1
0
;
1
1
;
1
1
2 2 4 8 16 32 64 128 ret
StartADC: in ori out ret
ZL,ADCSRA ZL,0b11011000 ADCSRA,ZL
;**************************************** ;ADC Conversion Complete Handler ; ; ADC: PUSH ZL PUSH ZH IN ZL,SREG PUSH ZL push R0 in push in push
ZL,ADCL ZL R0,ADCH R0
cbi
ADCSRA,ADEN
;ADC Stop
in inc andi out
ZL,ADMUX ZL ZL,7 ADMUX,ZL
;kovetkezo
clr dec andi add ldi add ldi adc pop st pop st
R0 ZL ZL,7 ZL,ZL ZH,Low(ADCCH0+2) ZL,ZH ZH,high(ADCCH0+2) ZH,R0 R0 -Z,R0 R0 -Z,R0
pop POP OUT POP POP RETI
R0 ZL SREG,ZL ZH ZL
csatorna kivalasztva
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/adc10b.html (1 of 2)1/20/2009 9:06:54 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/adc10b.html (2 of 2)1/20/2009 9:06:54 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
CHEAP ANALOG DIGITAL COMPARATOR (AVR 400) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
MATH 202
EPROM 100
FLASH CARD VFX SMIL
This application note shows how you can make a A/D
the MCU while ;* conversion is taking place. ;* ;* To minimize the usage of external components, this A/ D converter uses ;* the charging of a capacitor (controlled by port D pin 2)through a ;* resistor while converting. ;* The voltage across the capacitor will follow an exponential curve of ;* voltage versus time. By constricting the voltage range of ;* the converter to 2/5Vdd, the exponential curve is a good approximation ;* of a straight line. This makes it possible to simply measure the time ;* it takes before the voltage across the capacitor equals the voltage which
VFX MEM SORT 220
DESCRIPTION
;* comparator interrupt. The usage of interrupts free's
SER EPROM DFLASH AT45
Code Size :37 words Low Register Usage :0 High Register Usage :2 Status Flag Usage :1 (t flag) Interrupt usage :Timer/Counter0 overflow interrupt, Analog comparator interrupt
addition to the Analog
COPY 102 LPM 108
[email protected]
;* uses the Timer/Counter0 overflow interrupt in
AVG8 222 FFT7
Support E-mail:
capacitor. This solution
INT ASCII HX2ASC
Low Cost A/D Converter 1.0 97.07.18 AT90Sxxxx (All AVR Devices)
;* device, one external resistor and one external
MATH 202 DEC ASCII
Title: Version: Last updated: Target:
converter using a AVR
FLOAT 128 SQRT16
A V R 4 0 0
************************
ASM MATH
DIV 3216
N O T E
;* is to be converted. To do this we use the analog comparator. The ;* comparator will give an interrupt when the voltage
CRC 236
across the capacitor ;* rises above the measurement voltage. The output is
XMODEM REC UART 304
divided into 64 ;* different levels. ;* ;* To ensure correct timing the time constant of the RC-
UART 305 UART 128
network must
UART BUFF USB 232
;* satisfie 512*(1/f)=-R*C*ln(1-2/5). ;* For the A/D converter to operate properly, the capacitor must be
AVR ISP ISP 2313
;* completly discharged between each conversion. This is done by allowing ;* the discharging to take a minimum of 200us. ;* ;* ;* *** Initialization ;* ;* 1. Call convert_init ;* 2. Enable global interrupts (with sei) ;* ;* *** A/D conversion ;* ;* 1. Call AD_convert ;* 2. Wait for conversion complete (t to be set) (less
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
than 521 cycles)
ETHNET 8019
;* 3. Read data from result ; **************************************************************************
TEA ADC 128 ADC 10B
.include "1200def.inc"
ADC 400
;***** Constants
ADC 401 THERM 232
.equ
preset=192
;T/C0
Preset constant (256-64)
IRD 410 LCD HD44
;***** A/D converter Global Registers
LCD 2313
.def
result=r16
;Result and
.def
temp=r17
;Scratch
LCD44 2313 KBD 240
intermediate data register
MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS
; ************************************************************************** ;* ;* PROGRAM START - EXECUTION STARTS HERE ;* ; ************************************************************************** .cseg
DELAYS .org rjmp .org rjmp .org rjmp
CALL ID DTMF 314 PWM 6CH PWM 10K
$0000 RESET OVF0addr ANA_COMP ACIaddr ANA_COMP
;Reset handle ;Timer0 overflow handle ;Analog comparator handle
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ************************************************************************** ;* ;* ANA_COMP - Analog comparator interrupt routine ;* ;* ;* DESCRIPTION ;* This routine is executed when one of two events occur: ;* 1. Timer/counter0 overflow interrupt ;* 2. Analog Comparator interrupt ;* Both events signals the end of a conversion. Timer overflow if the signal ;* is out of range, and analog comparator if it is in range. ;* The offset will be corrected, and the t'flag will be set. ;* Due to the cycles needed for interruption handling, it is necessary ;* to subtract 1 more than was added previously. ;* ;* ;* Total numbers of words : 7 ;* Total number of cycles : 10 ;* Low register usage : 0 ;* High register usage : 2 (result, temp) ;* Status flags : 1 (t flag) ;* ; ************************************************************************** ANA_COMP: in result,TCNT0 ;Load timer value clr out
temp TCCR0,temp
;Stop timer0
subi
result,preset+1 ;Rescale A/D output
cbi set
PORTD,PD2
;Start discharge ;Set conversion
complete flag reti
;Return from
interrupt
; ************************************************************************** ;* ;* convert_init - Subroutine for A/D converter initialization ;* ;* ;* DESCRIPTION ;* This routine initializes the A/D converter. It sets the timer and the ;* analog comparator. The analog comparator interrupt is being initiated by ;* a rising edge on AC0. To enable the A/D converter the global interurrupt ;* flag must be set (with SEI). ;* ;* The conversion complete flag (t) is cleared. ;* ;* Total number of words : 6 ;* Total number of cycles : 10 ;* Low register usage : 0 ;* High register usage : 1 (result) ;* Status flag usage : 0 ;* ; ************************************************************************** convert_init: ldi result,$0B ;Initiate comparator out ACSR,result ;and enable comparator interrupt
ldi
result,$02
out
TIMSK,result
sbi
PORTD,PD2
;Enable timer
interrupt
;Set converter
charge/discharge ;as output ret
;Return from
subroutine
; ************************************************************************** ;* ;* AD_convert - Subroutine to start an A/D conversion ;* ;* DESCRIPTION ;* This routine starts the conversion. It loads the offset value into the ;* timer0 and starts the timer. It also starts the charging of the ;* capacitor. ;* ;* ;* Total number of words : 7 ;* Total number of cycles : 10 ;* Low register usage : 0 ;* High register usage : 1 (result) ;* Status flag usage : 1 (t flag) ;* ; ************************************************************************** AD_convert: ldi result,preset ;Clear counter out TCNT0,result ;and load offset value clt
;Clear conversion
complete flag (t) ldi
result,$02
;Start timer0 with
out sbi
TCCR0,result PORTB,PB2
;Start charging of
prescaling f/8
capacitor
ret
;Return from
subroutine
; ************************************************************************** ;* ;* Example program ;* ;* This program can be used as an example on how to set up the A/D ;* converter properly. ;* NOTE! To ensure proper operation, make sure the discharging period ;* of the capacitor is longer than 200us in front of each conversion. ;* The results of the conversion is presented on port B. ;* To ensure proper discharging we have added a delay loop. This loop is ;* 11 thousand cycles. This will give a 550us delay with a 20MHz oscillator ;* (11ms with a 1MHz oscillator). ;* ; ************************************************************************** RESET: rcall
convert_init
;Initialize A/D
converter sei
;Enable global
interrupt ldi
result,$ff
;set port B as
out
DDRB,result clr result
output Delay:
;Clear temp
counter 1 ldi
temp,$f0
;Reset temp counter
2 loop1:
inc
result
;Count up
temp counter 1 brne
loop1
;Check if inner
inc
temp
;Count up temp
brne
loop1
;Check if delay is
rcall
AD_convert brtc Wait
;Start conversion ;Wait until
out
PORTB,result
;Write result on
rjmp
Delay
;Repeat conversion
loop is finished counter 2 finished
Wait: conversion is complete port B
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K Inhttp://avr-asm.tripod.com/avr400.html (1 of 2)1/20/2009 9:07:27 PM
16 BIT MATH (AVR 202)
System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr400.html (2 of 2)1/20/2009 9:07:27 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
PRECISION 8 BIT ADC (AVR 401) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2
MATH 201 MATH 202
DIV16 XX
slope-alike ;* A/D conversion utilizing the on-chip analog comparator and a few ;* external components. Included is a test program that performs
DIV 24 24 DIV 3216 FLOAT 128 SQRT16
8-bit precision A/D converter 1.03 97.07.17 AT90Sxxxx (All AVR Devices with
;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application note shows how to perform dual-
MATH 200b
MATH YX
Title: Version: Last Updated: Target:
analog comparator)
MATH 200
MATH 32X
A V R 4 0 1
************************
ASM MATH
TUTORIAL #3
N O T E
;* conversions in a eternal loop, outputting the result to eight LEDs. ;* ; ***************************************************************************
MATH 202
;***** Registers used by mpy9u multiplication routine
MATH 202 DEC ASCII
mc9u
=r0
;multiplicand used by
.def
mp9u
=r1
;multiplier used by
.def .def
m9uL m9uH
=r1 =r2
;result Low byte ;result High byte
multiplication routine
INT ASCII HX2ASC
.def
multiplication routine
AVG8 222 FFT7
;***** Registers used by div17u division routine
COPY 102 LPM 108 EPROM 100 SER EPROM
didL didH dresL
=r1 =r2 =r1
;Dividend
.def .def .def .def
dresH divL divH remL
=r2 =r3 =r4 =r5
.def
remH
=r6
.def .def .def
TinH TinL Tref
=r14 =r15 =r16
;Time to reach input voltage
.def
TH
=r17
;Timer variable
.def
Vref
=r18
;Computed Vref
.def .def
temp temp2
=r19 =r20
;Holds the result of the
division
DFLASH AT45 FLASH CARD VFX SMIL
.def .def .def
;Divisor ;Reminder variables used by
division routine
VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
;Time to reach reference
voltage
UART 305 UART 128 UART BUFF USB 232 AVR ISP ;Port B pins .equ AIN0 .equ AIN1 .equ Ref1 .equ Ref2 .equ LED .equ T
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
.equ .equ
I2C/TWI 128
=0 =1 =2 =3 =4 =7
PRESC =2 VrefAddr=0
;Timer clocked at CK/8 ;EEPROM Address holding Vref
I2C/TWI AT8 DALLAS-1W
.include "1200def.inc"
DALLAS CRC .cseg .org 0
ETHNET 8019
rjmp reset reti
TEA ADC 128 ADC 10B ADC 400
.org OVF0addr ;** Timer/counter 0 overflow interrupt ******************************
ADC 401 THERM 232
;Reset handler
T0_int:
inc TH
;Increase
timer high-byte reti
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
;*** Reset handler ************************************************** reset: sbi DDRB,LED ser temp used to out DDRD,temp
KBD PS2
;drive LEDs
ldi temp,(1< multiplier ldi temp,128 ;128
KBD PC/128 PS2 EMU
;PB4 and ;Port D as output,
->
multiplicand ( = 2.5 volts)
BOOT MG8
mov mc9u,temp rcall mpy9u
;Tref x 128
clr divH mov divL,TinL rcall div17u
;(Tref x 128) ; ----------; Tcal
ldi out out sbi
;Store Vref
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
temp,VrefAddr EEAR,temp EEDR,dresL EECR,EEWE
DTMF 314 calibrate1: sbic EECR,EEWE rjmp calibrate1
PWM 6CH PWM 10K ENCODE STH-11
;Main program main:
ATMEL CORP AVR BUTTERFLY AVR BOOK
cbi PORTB,T
;Turn off
pull-up on T-pin ldi temp,VrefAddr
;Read Vref from
EEPROM out EEAR,temp sbi EECR,EERE in Vref,EEDR
loop:
rcall reference
;Measure
Tref rcall delay
;A small delay to
let ;
the capacitor
discharge, rcall input
;Measure Tin
brts error
;If Vin > Vcc
calc:
lsr TinH
;TinH -> C
(multiplier) mov mp9u,TinL mov mc9u,Vref
;TinL -> multiplier ;Tref ->
rcall mpy9u
;Tin x Tref
clr divH mov divL,Tref rcall div17u
;(Tin x Vref) ;-----------; Tref
multiplicand
tst dresH breq write error:
ldi temp,255
;
Vin
= 255 mov dresL,temp
write:
com dresL
;Show the
value on the LEDs rcall long_delay rcall long_delay rcall long_delay out PORTD,dresL rol dresL brcs wr1 cbi PORTB,LED rjmp loop wr1:
sbi PORTB,LED rjmp loop
;*** Subroutine delay ****************************************************** delay: ldi temp,$FF d1: dec temp brne d1 ret
long_delay: ser temp2 ld1: rcall delay dec temp2 brne ld1 ret
;*** Subroutine reference ************************************************** ;* Measures Tref reference:
sbi DDRB,AIN0
;Discharge the
sbi DDRB,Ref1 sbi PORTB,Ref1 sbi DDRB,Ref2
;Turn on Vref
rcall delay
;Let the capacitor
clr TH out TCNT0,TH
;Reset timer
cbi DDRB,AIN0
;AIN0 as input
ldi temp,PRESC out TCCR0,temp
;Start timer
sbi DDRB,T
;Turn on the
sbic ACSR,ACO
;If Capacitor
rjmp ref_ok
;
cpi TH,1
;Continue if timer
capacitor
discharge completely
transistor
ref_wait: voltage > reference voltage
conversion
conplete overflow brlo ref_wait ref_ok:
in Tref,TCNT0
;Store Tref
clr temp out TCCR0,temp
;Stop timer
cbi DDRB,T sbi DDRB,AIN0
;Turn off transistor ;Discharge capacitor
cbi PORTB,Ref1 cbi DDRB,Ref1 cbi DDRB,Ref2
;Turn off Vref
ret
;*** subroutine input ************************************************** ;* Measures Tin ;* Returns with the T-flag set if timer overflow (i.e. Vin > Vcc) input:
cbi DDRB,AIN0
;Tri-state
AIN0 clt clr TH out TCNT0,TH
;Clear error flag ;Clear timer
ldi temp,PRESC out TCCR0,temp
;Start timer
sbi DDRB,T
;Turn on transistor
input_wait: sbic ACSR,ACO
;If Capacitor
voltage > Vin rjmp input_ok
;
charging
cpi TH,2 brlo input_wait set
;T=1 indicates Vin
complete
> Vcc input_ok:
in TinL,TCNT0 mov TinH,TH
;Store Tin
input_exit: clr temp out TCCR0,temp
;Stop timer
cbi DDRB,T sbi DDRB,AIN0
;Turn off transistor ;Discharge capacitor
ret
; ******************************************************************** ;* ;* This routine divides a 17 bit number (carry:didH: didLL) on ;* a 16 bit number (divH:divL). ;* The result is placed in (dresH:dresL) ;* ;* The carry flag must contain the 17th bit of the divident before ;* the routine is executed. ;* ;* The routine is based on the div16u - 16/16 Bit Unsigned Division ;* routine found in the avr200.asm application note file ;* ; ********************************************************************
div17u:
clr remL
;clear
remainder Low byte clr remH
;clear remainder
ldi temp,17
;init loop counter
High byte
d17u_1:
rol remL
;shift
dividend into remainder rol remH sub remL,divL
;remainder = remainder -
divisor sbc remH,divH brcc d17u_2 add remL,divL adc remH,divH clc
; ;
;if result negative restore remainder ;
clear carry to
be shifted into result rjmp d17u_3 d17u_2: d17u_3:
;else
sec rol didL
;shift left
dividend rol didH dec temp brne d17u_1 ret
;decrement counter ;if done ; return with
value in didL
; *************************************************************************** ;* ;* "mpy9u" - 9x8 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two register variables (carry:mp9u) and mc9u. ;* The result is placed (carry:m8uH:m8uL) ;* ;* Number of words :11 (return included) ;* Number of cycles : (return included) ;* Low registers used :3 (mp9u,mc9/m9uL,m9uH) ;* High registers used :1 (temp) ;* ;* Note: Result Low byte and the multiplier share the same register. ;* This causes the multiplier to be overwritten by the result. ;* ; *************************************************************************** mpy9u:
clr m9uH
;clear
result High byte ldi temp,9 ror mp9u m9u_1:
;init loop counter
brcc m9u_2
;if bit 0
of multiplier set add m9uH,mc9u
;
add
multiplicand to result High byte m9u_2:
dec temp
;decrement
loop counter brne m9u_3
;if not done, loop
more ret m9u_3:
ror m9uH
;shift
right result High byte ror m9uL
;rotate right
result L byte and multiplier rjmp m9u_1
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. http://avr-asm.tripod.com/avr401.html (1 of 2)1/20/2009 9:08:03 PM
16 BIT MATH (AVR 202)
The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr401.html (2 of 2)1/20/2009 9:08:03 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
THERMOMETER DS1820 VIA RS232 PROGRAM HOME RETRO_DAN ;*********************************************************************** ;* ;* Number :DS1820 ;* File Name :"DS1820.asm" ;* Title :AVR alapu DS1820 thermometer + RS232 interface ;* - LM16x21A Driver via Lattice ispLSI2032 ;* ;* Date :2000.06.12. ;* Version :1.0 ;* Support telephone :+36-70-333-4034 ;* Support fax : ;* Support E-mail :[email protected] ;* Target MCU :AT90S2313 ;* ;* DESCRIPTION ;* kezeli a következõ eszközöket: ;* - DS1820 Thermometer unit ;* - Fulduplex RS232 port ;* - SS0=0 & SS1=0 akkor az LCD port az SPI target ;* ;* AT90S2313 lábkiosztás ;* ;* RESET 1. 20. VCC ;* * RxD (PD0) 2. 19. (PB7) SCK * ;* * TxD (PD1) 3. 18. (PB6) MISO * ;* XTAL2 4. 17. (PB5) MOSI * ;* XTAL1 5. 16. (PB4) SS0 * ;* INT0 (PD2) 6. 15. (PB3 OC1) LED0 ;* INT1 (PD3) 7. 14. (PB2) SS1 * ;* (T0 PD4) 8. 13. PB1 {AIN1} AT45D CS ;* DS1820 T1 (PD5) 9. 12. PB0 {AIN0} ;* GND 10. 11. {PD6 ICP} ;* ;* Kristályfrekvencia: f=1.8432 MHz (T=0.54253 us) ;* ;* * a csillagos IO labak fix huzalozasuak, masra nem hasznalhatok fel!!! ;*********************************************************************** .include "2313def.inc"
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
; ************************************************************************** ;* Hardware Def.
VFX MEM SORT 220
.EQU .EQU
DS1820_BIT = 5 DS1820_PORT =DDRD
;Dallas 1-Wire bus ;Dallas Port cime
.EQU .EQU
LEDPORT LED = 3
;A LED bitcime
.EQU .EQU .EQU .EQU
;SPI selector SS0PORT= DDRB SS0= BP4 SS1PORT= DDRB SS1= BP2
CRC 236 XMODEM REC UART 304
= DDRB
UART 305 UART 128 UART BUFF USB 232
00 LCD
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
; ************************************************************************** ;* UART Def .EQU BaudRate=11 ;11 - 9600 ;7 - 14400 ;5 - 19200 ;1 - 57600
I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
; *************************************************************************** ;***** Divide Subroutine Register Variables
ETHNET 8019
.def .def .def .def .def .def .def .def
TEA ADC 128 ADC 10B ADC 400 ADC 401
drem16uL=r14 drem16uH=r15 dres16uL=r16 dres16uH=r17 dd16uL =r16 dd16uH =r17 dv16uL =r18 dv16uH =r19
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS
; *************************************************************************** ;* SPI Master, Mode 0, MSB-first ;* ;* MAJOR ROUTINES: ;* init_spi: initializes the port lines used for SPI. ;* No calling requirements, returns nothing. ;* ena_AT: forces SCK low, and activates /SS signal. ;* No calling requirements, returns nothing. ;* disa_AT: brings /SS signal hi (inactive). ;* No calling requirements, returns nothing. ;* rw_spi: sends/receives an 8-bit data. ;* Must set up data to be sent in (spi_lo) ;* prior to calling; it returns received data in ;* the same register (spi_lo register). ;* ;* .equ sck = 7 ;PB7 pin .equ miso = 6 ;PB6 pin .equ mosi = 5 ;PB5 pin
CALL ID
.equ
ATss
= 1
;PB4=1 , PB2=0 pin AT45D041 CS
???????
.def .def
spi_lo temp
= R0 = R16
;change as needed ;misc usage, must be in upper regs for IMMED
ATMEL CORP
.def .def .def .def
ATComm ATPoint ATPageL ATPageH
= = = =
;AT45Dxxx ;AT45Dxxx ;AT45Dxxx ;AT45Dxxx
AVR BUTTERFLY
.def .def
LCDLo LCDHi
= R20 = R21
;LCD Low byte ;
.equ
BFSeg
= 32
;32 byte r/w
.macro CBI cbi .endm
Select_LCD SS0PORT+1,SS0 SS1PORT+1,SS1
DTMF 314 PWM 6CH PWM 10K
mode
ENCODE STH-11
R20 R21 R21 R22
command parameter register Buffer Pointer register Page Address low Page Address hi
AVR BOOK
; *************************************************************************** ;* ;* SPI MACROS ;* Program Macros .macro cbi .endm
AT_active portb,ATss
.macro sbi .endm
AT_inactive portb,ATss
.macro sbi .endm
sck_hi portb,sck
.macro cbi .endm
sck_lo portb,sck
.macro sbi .endm
mosi_hi portb,mosi
.macro cbi .endm
mosi_lo portb,mosi
;.macro ; subi ;.endm
addi @0, -@1
.macro
set_delay
subi .endm
@0, (@1 << 5)
;NOTE: THIS shift affects INC macro (below)!
.macro subi .endm
inc_delay @0, -(1 << 5)
;bump the delay counter ;shift value here must be same as above!
;subtract the negative of an immediate value
;set up the time delay amount, from 1
to 7
; ****************************************************************************** ;**** CONST ;;;;.EQU .EQU
RPMFACT = 17280 T0Freq=220
;RPM= RPMFACT/IMP*100 ;1.8432MHz = 50Hz
;FLAGS .EQU
Active
;Imo Active bit
= 2
; ****************************************************************************** ;**** VARIABLES .DSEG DS1: .BYTE 1 ;Flagbitek ; 0. = 1 RPM overflow ; 1. = 1 Velocity overflow ; 2. = 1 Immo. Active ; 4. = 1 LED kijelzo frissites kell CNT1: DS3: DS4: DS5: DS6: DS7: DS8: DS9: DS10: DS11: CRC: DSRD: DS12: IOBuff:
.BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE
2 4 2 2 2 2 2 2 2 1 1 10 1 BFSeg
;Interupt COUNTER ;RealTime Clock ;UART Transmit Interrupt rutin cime ;UART Receive Interrupt rutin cime ;UART Transmit Buffer Address ;Fordulatszam binaris ;Sebesseg bin ;Fordulatszamalalo start ;SebessegSZAMLALO start ;TEMP az UART RX-hez ;DS1820 CRC GENERATOR HASZNALJA ;Ide olvassa be a DS Chipet ;Bad CRC szamlalo ;AT45Dxxx IO munkaterulet
;*Variables Offset to Y .EQU .EQU .EQU
FLAGS RTC UTx
= DS1-DS1 = DS3-DS1 = DS4-DS1
;Z+0 ;RealTime Clock ;UART Transmit Interrupt
.EQU
URx
= DS5-DS1
;UART Receive Interrupt rutin
.EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU
TXT = DS6-DS1 RPMB = DS7-DS1 VELB = DS8-DS1 RPMC = DS9-DS1 VELC = DS10-DS1 TEMP = DS11-DS1 CRCoff = CRC-DS1 CNT1L = CNT1-DS1 CNT1H = CNT1-DS1+1 BadCRC = DS12-DS1
rutin cime cime ;UART Transmit Buffer Address ;Fordulatszam binaris ;Sebesseg bin ;Fordulatszamalalo start ;SebessegSZAMLALO start ;TEMP az UART RX-hez ;CRC ;CNT1 ;
; ************************************************************************************** .ESEG KEY1: .DB 0x01 .DB 0x88 .DB 0xDD .DB 0x07 .DB 0x02 .DB 0x00 .DB 0x00 KEY2: .DB 0x01 .DB 0x6D .DB 0xB9 .DB 0x07 .DB 0x02 .DB 0x00 .DB 0x00
; ***************************************************************************** ;**** I N T E R R U P T S ;**** ; ***************************************************************************** .CSEG rjmp RESET ;Reset Handle rjmp EXT_INTO ;IRQ0 Handle rjmp EXT_INT1 ;IRQ1 Handle rjmp TIM_CAPT1 ;Timer1 capture Handle rjmp TIM_COMP1 ;Timer1 compare Handle rjmp TIM_OVF1 ;Timer1 overflow Handle rjmp TIM_OVF0 ;Timer0 overflow Handle rjmp UART_RXC ;UART RX Complete Handle rjmp UART_DRE ;UDR Empty Handle rjmp UART_TXC ;UART TX Complete Handle rjmp ANA_COMP ;Analog Comparator Handle ;*********** ;* RESET ;*********** RESET: CLI
;GLOBAL INTERRUP DIS.
LDI
R16,42
;Sleep enable, Idle mode,INT0, INT1 fall-edge
OUT
MCUCR,R16
LDI OUT
R16,RAMEND SPL,R16
LDI OUT
R16,0 GIMSK,R16
LDI OUT
R16,2 TIMSK,R16
LDI OUT LDI OUT
R16,0 TCCR1A,R16 R16,3 TCCR1B,R16
LDI OUT LDI OUT
R16,T0Freq TCNT0,R16 R16,5 TCCR0,R16
LDI LDI
YL,LOW(DS1) YH,HIGH(DS1)
LDI
R16,0
STD
Y+CRCoff,R16
;CRC=0
STD STD
Y+CNT1L,R16 Y+CNT1H,R16
;CNT1=0
STD STD STD STD STD
Y+RTC+0,R16 Y+RTC+1,R16 Y+RTC+2,R16 Y+RTC+3,R16 Y+BadCRC,R16
LDI
R16,(1< ADIW MOV STD STD CPI BRNE
sens.
LDI STD LDI STD
;STACK A BELSO RAM VEGETOL INDUL LEFELE ;INT0, INT1 Disabled ;7. = 1 EXT INT1 ACTIVE ;6. = 1 EXT INT0 ACTIVE
;7. ;6. ;3. ;1.
= = = =
1 1 1 1
TC1 TC1 TC1 TC0
OWRF EN. * COMP MATCH EN. INP CAPTURE EN. OWRF EN. *
;TC1 Disconected from OC1 pin, PWM Dis. ;Input Capture Dis., f=CLK/64
;50Hz ;f(TC1)=CLK/1024
;BAZIS 'X' +0
;RealTime Clock=1970\01\01
;BadCRC=0
R0 ZL,1 R16,R0 Y+TXT+0,ZL Y+TXT+1,ZH R16,0 MoreTXT
;VAN MEG SZOVEG
R16,low(UReti) Y+UTx+0,R16 R16,high(UReti) Y+UTx+1,R16 CPSE R16,R16
;UART TX INT. ADDR ;AZERT, HOGY
AKOVETKEZO SOR KIMARADJON MoreTXT:
OUT
UDR,R16 POP R0 POP R16 POP ZL OUT SREG,ZL POP ZH POP ZL RETI
;************************************************************************* ;* Text Const ;* Copyr: .DB "(C) 2000, DS1820 Thermometer V1.0 ", 10,13 Ready: .DB "Ready>>",0 Hiba: .DB "Error..",10,13,0
;*********************************************************************** ;*********************************************************************** ;******** M A I N ******** ;******** ******** ;*********************************************************************** Main: LDI R16,10 STD Y+CNT1L,R16 LDI R16,0 STD Y+CNT1H,R16 ;CNT1=25 0.5s
wait:
;SLEEP ldd CPI BREQ CPI BREQ
R16,Y+TEMP R16,'R' WHTROM R16,'r' WHTROM
CPI BREQ CPI BREQ
R16,'T' RDTH R16,'t' RDTH
rjmp
Csokkent
RDTH: rcall sei brcc
cli ReadTh CMDsEND
;ha nincs eszkoz a buszon, akkor
rcall
ComuteT
;R22,R23 a korigalt hom
MOV rcall MOV rcall
R0,R23 TOUART R0,R22 TOUART
kihagy
Wt6:
SBIS
USR,UDRE
;a kovetkezo kimarad, ha a TX
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures RJMP LDI OUT Wt7:
Wt6 R16,' ' UDR,R16 SBIS
reg ures
WHTROM:
RJMP LDI OUT
Wt7 R16,' ' UDR,R17
LDI LDI LDI rjmp
XL,LOW(DSRD) XH,HIGH(DSRD) R19,8 WHTR1
CLI rcall ReadROM SEI brcc CMDsEND
;ide olvasta a DS Chipet ;8 byteot kuldunk ki
;ha nincs eszkoz a buszon, akkor
kihagy
LDI LDI LDI
R19,8 XL,LOW(DSRD) XH,HIGH(DSRD)
MOV rcall
LD R0,R16 TOUART SBIS
WHTR1:
Wt4:
;8 byteot kuldunk ki ;ide olvasta a DS Chipet
R16,X+
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures
CMDsEND:
RJMP LDI OUT dec BRNE
Wt4 R16,' ' UDR,R16 R19 WHTR1
SBIS RJMP LDI OUT
USR,UDRE CMDsEND R16,13 UDR,R16
Wt9:
SBIS
;a kovetkezo kimarad, ha a TX reg ures
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures
Csokkent:
RJMP LDI OUT LDI std
Wt9 R16,10 UDR,R16 R16,0 Y+TEMP,R15
LDD LDD OR BRNE
R24,Y+CNT1L R25,Y+CNT1H R24,R25 wait
;a parancssort kinullazzuk
;Kell-e villogni? LDD R16,Y+FLAGS SBRS R16,Active rjmp Main ;
;a kovetkezo kimarad ha az Active=1
Led villogtato
LEDvil: RJMP CBI RJMP Led_be: RJMP
;CRC-t ellenorzi ; LD ; LDD ; CP ; BREQ
SBIS LEDPORT+1,LED ;kihagy, ha LED=1 Led_be LEDPORT+1,LED ;LED eg Main SBI LEDPORT+1,LED ;LED nem eg Main
R1,X+ R0,Y+CRCOff R1,R0 CRCOK
;olvasott CRC ;szamolt CRC ;GoodCRC
;R0-ban levo byte kiirasa az uartra (HEX) TOUART: LDI Wt1:
LDI R18,7
R17,48
SBIS
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures RJMP MOV SWAP ANDI CPI BRCS ADD Kicsi1: OUT
Wt2:
Wt1 R16,R0 R16 R16,0x0F R16,10 Kicsi1 R16,R18 ADD R16,R17 UDR,R16
SBIS
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures RJMP MOV ANDI CPI BRCS ADD Kicsi0: OUT
Wt2 R16,R0 R16,0x0F R16,10 Kicsi0 R16,R18 ADD R16,R17 UDR,R16
ret
.include .include
"div16.asm" "SPI.asm"
;************************************************************************ ;*********************** 1-Wire Bus ************************************* ;************************************************************************ ;-----------------------------------------------------------------------;Kiolvasott DS chip tartalmat osszehasonlitja az EEpromban taroltakkal ; ; R14 a KEY Offsetcime ; ;C=0 Nem jo ;C=1 Kulcs jo DScomp: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet OUT EEAR,R24 ;EEPROM address LDI
R16,7
Cikl2: LD SUB BRNE DEC BRNE SEC RET Rossz: RET
RCALL R1,X+ R1,R0 Rossz R16 Cikl2
;CRC-vel egyutt 8 byte comp. EERead_seq
;EEPrombol akovetkezo elem R0-ba
CLC
;*********************************************************************** ;....................................................................... ;Read DS1820 ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvas egy chippet az Y-ban megadott cimre) ; ;Hasznalja a R18, R17, R16, R3, R2, R0; ;....................................................................... ReadROM: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet LDI R16,0 STD Y+CRCoff,R16 ;CRC=0 ; RCALL TouchReset BRCS RDS1 ;ESZKOZ A BUSZON VAN CLC RET RDS1: MOV LDI RCALL RDS2: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST LDI RDS3: BRNE SEC RET
LDI R16,0x33 ;SEARCH ROM COMMAND R0,R16 R19,7 ;7-SZER OLVASUNK BE TouchByte LDI R16,0xFF ;BEOLVASUNK 8 BITET R0,R16 TouchByte X+,R1 CRCGEN R19 RDS2 R16,0xFF R0,R16 TouchByte X+,R1
;BEOLVASSUK A CRCT
R19,0xFF DEC R19 RDS3 ;CHIP RENDBEN
; **************************************************************************** ;******* TOUCHBYTE ; **************************************************************************** ; ;R0-ban megadott byte-ot kiküldi a touchmemory-nak ;és szimultán beolvas egy byte-ot onnan az R1-be ;Hasznalja a R17, R16 R3, R2 ; TouchByte: LDI R17,8 ;[1] BIT_LOOP: ROR R1 ;[1] RCALL TOUCHBIT ;[3] ROR R0 ;[1] DEC R17 ;[1] BRNE BIT_LOOP ;[1/2] RET ;[1] TOUCHBIT: SBI DS1820_PORT,DS1820_BIT ;[2] LDI R16,3 ;[1] BW0: DEC R16 BRNE BW0 ;[1/2] SBRC R0,0 ;[1/2] CBI DS1820_PORT,DS1820_BIT ;[2] LDI R16,8 ;[1] BW1: DEC R16 BRNE BW1 ;[1/2] IN R2,DS1820_PORT-1 ;[1] BST R2,DS1820_BIT ;[1] BLD R1,7 ;[1] LDI R16,26 ;[1] TCHL: DEC R16 BRNE TCHL ;[1/2] CBI DS1820_PORT,DS1820_BIT ;[2] RET ;[4]
;[1]
;[1]
;[1]
; ******************************************************************************* ;****** T O U C H R E S E T ; ******************************************************************************* ; ;Inicialization procedure "Reset and PreSence Pulses" ; ; Ez a rutin egy Reset jelet general a mikrovrzerlo ketiranyu DS_BIT nevu laban, ;a Touch Memory fele es figyeli a visszajovo PreSence jelet. ;Ha a PreSence jel megerkezett, akkor C=1 kulonben C=0 (nincs eszkoz a buszon) ; ; |-Master Rx "Presence Pulse"-| ; |---Master Reset Tx Pulse---| |----t(RSTH)---------------| ; __ t(RSTL) _____ _____ \\ ___ ; \ / \ / \ ; \_________________________/ \______/ \__ ... ; |-----|-------| ; t(PDH) t(PDL) ; t(R) <-- |-| ; ; 480us<=t(RSTL)< . t(RSTL)+t(R)<960us ; 480us<=t(RSTH)< ; 15us<=t(PDH)<=60us ; 60us<=t(PDL)<=240us ; ; C-flag = 1 DS1990A a buszon van ; = 0 DS1990A nincs a buszon ; ; R16 ; Testelt jol mukodik ; Cyc: TouchReset: SBI DS1820_PORT,DS1820_BIT
;[2]
1-wire = Master LOW , Start
the reset pulse LDI TR0: DEC BRNE
R16,222 NOP R16 TR0
;[1] ;[1] ;[1] ;[1/2] 480us wait with data
low SBI nop CBI CBI nop SBIS RJMP LDI TR1: RJMP DEC BRNE RJMP WL: LDI TR3: RJMP DEC BRNE SHORT: RET WH: SEC RET
DS1820_PORT+1,DS1820_BIT
;[2] 1-wire =Active Hi ;[1] DS1820_PORT,DS1820_BIT ;[2] 1-wire HI (felengedve) DS1820_PORT+1,DS1820_BIT ;[2] 1-wire = Tri-state ;[1] DS1820_PORT-1,DS1820_BIT ;[1/2] Short ;[2] ha egybol Low az rossz R16,21 ;[1] SBIS DS1820_PORT-1,DS1820_BIT ;[1/2] WL ;[2] Exit loop if line low R16 ;[1] TR1 ;[1/2] us wait with data low SHORT ;[2] Line could not go low R16,87 ;[1] SBIC DS1820_PORT-1,DS1820_BIT ;[1/2] WH ;[2] Exit loop if line hi R16 ;[1] TR3 ;[1/2] us wait with data low CLC ;[1] Error ;[4] ;[1] RESET OK. ;[4]
;************************************************************************* ;......................................................................... ; DS1990A CRC GENERATOR ;IN: R1 ;USE: R21,R20, R4,R3, R0, R18 ;......................................................................... CRCGEN: PUSH R1 LDI R20,8 LDI R18,0x18 PUSH R1 CRC_L: EOR ROR MOV BRCC EOR ZERO: STD POP SEC SBRS CLC ROR PUSH DEC BRNE POP POP RET
LDD R3,Y+CRCoff R1,R3 R1 R1,R3 ZERO R1,R18 ROR R1 Y+CRCoff,R1 R1
;CRC
R1,0 R1 R1 R20 CRC_L R1 R1
;*********************************************************************** ;....................................................................... ;Read DS1820 ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvas egy chippet az Y-ban megadott cimre) ; ;Hasznalja a R18, R17, R16, R3, R2, R0; ;....................................................................... ReadTh: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet LDI R16,0 STD Y+CRCoff,R16 ;CRC=0 RCALL TouchReset BRCS DSVAN ;ESZKOZ A BUSZON VAN CLC RET DSVAN: MOV RCALL
LDI MOV RCALL
LDI R16,0xCC R0,R16 TouchByte
R16,0x44 R0,R16 TouchByte
;Skip ROM Command
;Convert T Command
nop nop nop nop nop nop nop
DSW1:
SBIS
DS1820_PORT-1,DS1820_BIT
;ha 1 akkor a
kovetkezo kimarad RJMP
DSW1
;varunk mig a komvertalas vege nincs
nop nop LDI STD RCALL BRCS CLC RET
R16,0 Y+CRCoff,R16 TouchReset DS2VAN
;CRC=0
;
;ESZKOZ A BUSZON VAN
DS2VAN: LDI
;Skip ROM Command
MOV RCALL
R16,0xCC R0,R16 TouchByte
LDI MOV RCALL
R16,0xBE R0,R16 TouchByte
;Read Scratchpad command.
nop nop LDI DS2T: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST LDI DS3T: BRNE RCALL SEC RET
R19,8 ;8-SZOR OLVASUNK BE LDI R16,0xFF ;BEOLVASUNK 8 BITET R0,R16 TouchByte X+,R1 CRCGEN R19 DS2T R16,0xFF R0,R16 TouchByte X+,R1
;BEOLVASSUK A CRCT
R19,0xFF DEC R19 DS3T TouchReset ;CHIP RENDBEN
;Tc=8T-2+(8*Count-8*Remainder)/8Count
ComuteT:
http://avr-asm.tripod.com/therm232.html (1 of 2)1/20/2009 9:08:49 PM
LDI LDI
ZL,LOW(DSRD) ZH,HIGH(DSRD)
LDD LDI
dd16uL,Z+7 dd16uH,0
;CPC
LDD LDI
R22,Z+6 R23,0
;CRM
LSL ROL LSL ROL LSL ROL
dd16uL dd16uH dd16uL dd16uH dd16uL dd16uH
;8*CPC
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*CRM
SUB SBC
dd16uL,R22 dd16uH,R23
LDD LDI
dv16uL,Z+7 dv16uH,0
;ide olvassa DS Chipet
;CPC
16 BIT MATH (AVR 202)
MOV OR BRNE LDI LDI RJMP
R0,dv16uL r0,dv16uH DIV1 R16,0 R17,0 LKI1
;0-VAL NEM OSZTUNK
DIV1:
RCALL
div16u
;OSZTAS eredmeny az
LKI1: SBCI SBCI
CLC dres16uL,2 dres16uH,0
LDD LDD CBR
R22,Z+0 R23,Z+1 R22,1
;Temperature
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*T
ADD
R22,dres16uL
;R22,R23 a korigalt
ADC ret
R23,dres16uH
R16,R17-ben
;eredmeny-2
;Truncate 0.5C
homerseklet
; *************************************************************************** ;* ;* EERead_seq ;* ;* This subroutine increments the address stored in EEAR and reads the ;* EEPROM into the register variable "EEdrd_s". ;* ;* Number of words :8515 ; 7 + return ;* Number of cycles :8515 ; 11 + return (if EEPROM is ready) ;* Low Registers used :R0 ;* High Registers used: :R24 ;* ; *************************************************************************** EERead_seq: sbic EECR,EEWE ;if EEWE not clear rjmp EERead_seq ; wait more ;The above sequence for EEWE = 0 ;can be skipped if no write is initiated. in R24,EEAR ;get address low 8515 inc R24 ;increment address 8515 out EEAR,R24 ;output address 8515 sbi
EECR,EERE
in ret
R0,EEDR
;set EEPROM Read strobe ;This instruction takes 4 clock cycles since ;it halts the CPU for two clock cycles ;get data
; *************************************************************************** ;* ;* FUNCTION ;* ena_LCD ;* ;* DESCRIPTION ;* Init data & clock lines, then assert /CS for LCD. ;* ;* CODE SIZE: ;* 4 words ;* ; *************************************************************************** ena_LCD: sck_lo mosi_lo Select_LCD ret
;(should already be there...)
;* LCDlo, LCDHi - kikuldese RW_LCD: mov spi_lo,LCDHi rcall ena_LCD rcall rw_spi mov spi_lo,LCDLo rcall rw_spi ret ;**** A P P L I C A T I O N
;Mov Command byte ;activate /CS ;send Command byte ;Mov Command byte ;send Command byte N O T E
A V R 2 0 0
************************ ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
Title: Version: Last updated: Target:
Multiply and Divide Routines 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This Application Note lists subroutines for the following Divide applications. Routines are straight-line implementations optimized for speed: 16 / 16 = 16 + 16 bit unsigned
; ***************************************************************************
; *************************************************************************** ;* ;* "div16u" - 16/16 Bit Unsigned Division ;* ;* This subroutine divides the two 16-bit numbers ;* "dd16uH:dd16uL" (dividend) and "dv16uH:dv16uL" (divisor). ;* The result is placed in "dres16uH:dres16uL" and the remainder in ;* "drem16uH:drem16uL". ;* ;* Number of words :196 + return ;* Number of cycles :148/173/196 (Min/Avg/Max) ;* Low registers used :2 (drem16uL,drem16uH) ;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH,dv16uL,dv16uH) ;* ; ***************************************************************************
;***** Code div16u: sub
clr drem16uL ;clear remainder Low byte drem16uH,drem16uH;clear remainder High byte and carry
rol rol rol rol sub sbc brcc add adc clc rjmp d16u_1:
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_1 drem16uL,dv16uL drem16uH,dv16uH
d16u_2: rol rol rol sub sbc brcc add adc clc rjmp d16u_3:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_3 drem16uL,dv16uL drem16uH,dv16uH
d16u_4: rol rol rol sub sbc brcc add adc clc rjmp d16u_5:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_5 drem16uL,dv16uL drem16uH,dv16uH
d16u_6: rol rol rol sub sbc brcc add adc clc rjmp d16u_7:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_7 drem16uL,dv16uL drem16uH,dv16uH
d16u_8: rol rol rol sub sbc brcc add adc clc rjmp d16u_9:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_9 drem16uL,dv16uL drem16uH,dv16uH
d16u_10:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_11:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_11 drem16uL,dv16uL drem16uH,dv16uH
d16u_12:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_13:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_13 drem16uL,dv16uL drem16uH,dv16uH
d16u_14:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_15:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_15 drem16uL,dv16uL drem16uH,dv16uH
d16u_16:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_17:
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_17 drem16uL,dv16uL drem16uH,dv16uH
d16u_18:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_19:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_19 drem16uL,dv16uL drem16uH,dv16uH
d16u_20:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_21:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_21 drem16uL,dv16uL drem16uH,dv16uH
d16u_22:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_23:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_23 drem16uL,dv16uL drem16uH,dv16uH
d16u_24:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_25:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_25 drem16uL,dv16uL drem16uH,dv16uH
d16u_26:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_27:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_27 drem16uL,dv16uL drem16uH,dv16uH
d16u_28:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_29:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_29 drem16uL,dv16uL drem16uH,dv16uH
d16u_30:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_31:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_31 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_2 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_4 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_6 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_8 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_10 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_12
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_14
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_16
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_18 sec
result
;remainder = remainder - divisor ; ;if result negative ; restore remainder
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_22
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_24
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_26
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_28
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_30
d16u_32:rol dd16uL rol dd16uH ret
;shift dividend into remainder
; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_20
d16u_32
;shift left dividend
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result ;shift left dividend
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/therm232.html (2 of 2)1/20/2009 9:08:49 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
INFARED REMOTE DECODER (AVR 410) HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16
; *************************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR410 ;* File Name :"rc5.asm" ;* Title :RC5 IR Remote Control Decoder ;* Date :97.08.15 ;* Version :1.0 ;* Target MCU :AT90S1200 ;* ;* DESCRIPTION ;* This Application note describes how to decode the frequently used ;* RC5 IR remote control protocol. ;* ;* The timing is adapted for 4 MHz crystal ;* ; *************************************************************************** .include "1200def.inc" .device AT90S1200
MATH 202 .equ .equ
INPUT SYS_ADDR
FFT7
.def .def .def .def
S inttemp ref1 ref2
=R0 =R1 =R2 =R3
COPY 102
.def
temp
=R16
.def .def
timerL timerH
=R17 =R16
.def .def
system =R19 command =R20
.def
bitcnt
=R21
rjmp
reset
MATH 202 DEC ASCII
=2 =0
;PD2 ;The system address
INT ASCII HX2ASC AVG8 222
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM .cseg .org 0
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; ******************************************************************** ;* "TIM0_OVF" - Timer/counter overflow interrupt handler ;* ;* The overflow interrupt increments the "timerL" and "timerH" ;* every 64us and 16,384us. ;* ;* Number of words: 7 ;* Number of cycles: 6 + reti ;* Low registers used: 1 ;* High registers used: 3 ;* Pointers used: 0 ; ******************************************************************** .org OVF0addr TIM0_OVF: in S,sreg inc timerL ;Updated every 64us inc inttemp brne TIM0_OVF_exit
DALLAS-1W
inc
timerH
DALLAS CRC TIM0_OVF_exit: reti
ETHNET 8019
out
sreg,S
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; ******************************************************************** ;* Example program ;* ;* Initializes timer, ports and interrupts. ;* ;* Calls "detect" in an endless loop and puts the result out on ;* port B. ;* ;* Number of words: 16 ;* Low registers used: 0 ;* High registers used: 3 ;* Pointers used: 0 ; ********************************************************************
PS2 EMU BOOT MG8
reset:
;ldi
temp,low(RAMEND)
;
Initialize stackpointer ;out ;ldi
SPL,temp temp,high(RAMEND)
;out
SPH,temp
ldi
temp,1
out
TCCR0,temp
PWM 6CH
ldi brge
temp,1< 3/4 bit time fault ; exit
PWM 10K
sbic
PIND,INPUT
rjmp
start3
clr ldi clr clr
timerL bitcnt,12 command system
BOOT DR8 ALM CLK
out since 1200 does not hae SRAM
CLOCK 8564 90 DAYS DELAYS
;Timer/Counter 0
clocked at CK
CALL ID DTMF 314
ENCODE
; Commented
;Wait for falling
edge start bit 2
STH-11 ATMEL CORP AVR BUTTERFLY
;Receive 12 bits
AVR BOOK sample:
cp
timerL,ref1
;Sample
INPUT at 1/4 bit time brlo
sample
sbic rjmp
PIND,INPUT bit_is_a_1
bit_is_a_0: clc rol rol
;Jump if line high
;Store a '0' command system
bit_is_a_0a:
cp
;Synchronize timing timerL,ref2 ;If no edge
within 3/4 bit time brge sbis
fault PIND,INPUT
; exit ;Wait for rising
rjmp
bit_is_a_0a
;in the middle of
clr rjmp
timerL nextbit
edge the bit
bit_is_a_1: sec rol rol
;Store a '1' command system
bit_is_a_1a:
cp
;Synchronize timing timerL,ref2 ;If no edge
within 3/4 bit time brge sbic
fault PIND,INPUT
; exit ;Wait for falling
rjmp
bit_is_a_1a
;in the middle of
clr
timerL
dec brne
bitcnt sample
edge the bit
nextbit:
;If bitcnt > 0 ; get next bit
;All bits sucessfully received! mov temp,command
;Place system bits
in "system" rol rol rol rol
temp system temp system
bst bld
system,5 command,6
;Move toggle bit ;to "command" ;Clear remaining
bits andi andi
command,0b01111111 system,0x1F
ret fault:
ser
command
;Both
"command" and "system" ser
system
;0xFF indicates
failure ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/ird410.html (1 of 2)1/20/2009 9:09:24 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/ird410.html (2 of 2)1/20/2009 9:09:24 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LCD DRIVER FOR HD44xx HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; *************************************************************************** ; ; File Name :'lcd4.asm" ; Title :HD44xx kompatibilis LCD Driver (I/O Port) ; Date :2003.10.28. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; http://home.iae.nl/users/pouweha/lcd/lcd.shtml ; ; Support 2x16 char LCD ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.10.28 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ; ; ************************************************************************** ;* Hardware Def. ; ; ***************************************************************************
UART 305 .equ .equ
LCDRS_PORT=PORTD LCDRS_DIR=DDRD
USB 232
.equ
LCDRS=0
AVR ISP
.equ .equ
LCDRW_PORT=PORTD LCDRW_DIR=DDRD
.equ
LCDRW=1
.equ .equ
LCDEN_PORT=PORTD LCDEN_DIR=DDRD
.equ
LCDEN=4
.equ
LCDDAT_PORT=PORTF
.equ .equ .equ
LCDDAT_DIR=DDRF LCDDAT_PIN=PINF LCDDAT_Mask=0b00001111
UART 128 UART BUFF
1=data 0=command
ISP 2313 ISP 1200
;LCD Register Select ;Register Select
;LCD Read/Write ;0=write to
display, 1= read from display
AVR SPI I2C 300 I2C 302
clocked on falling edge
I2C TWI26 I2C/TWI 128 I2C/TWI AT8
;LCD Enable ;Enable - data
;LCD Data PortF
[3..0]
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400
; *************************************************************************** ;**** VARIABLES .DSEG
ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
; *************************************************************************** .ESEG
LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG
PS2 EMU BOOT MG8
;***************************************************** ;** Wait1ms ;** ;** In: R16 - 16*1ms varakozas ;** ;** Out: ;** ;** ;** Alt R16 ;** ;** Description: wating for R16 * 1 ms ;* Wait1ms: ldi XL,low(SYSCLK/(5*1000)) ldi XH,high(SYSCLK/(5*1000)) Waitx1: sbiw XL,1 ;[2] \ nop ;[1] - 5 cycles in
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP
loop brne dec brne ret
AVR BUTTERFLY AVR BOOK
Waitx1 R16 Wait1ms
;[2] /
;***************************************************** ;** LCD_pulseE ;** ;** In: ;** ;** Out: R0 - Data on LCDDat pin ;** ;** ;** Alt ;** ;** Description: Generate ENABLE signal to LCD ;* LCD_pulseE: sbi LCDEN_PORT,LCDEN ;Enable high nop ;Wait 500ns @16MHz nop nop nop nop nop nop nop in cbi
R0,LCDDAT_PIN LCDEN_PORT,LCDEN
;Enable
low, latch data ret
;***************************************************** ;** LCD_Init ;** ;** In: ;** ;** Out: ;** ;** ;** Alt: ;** ;** Description: Initialize LCD in 4 bit mode ;* LCD_Init: sbi LCDEN_DIR,LCDEN ;LCD I/O Disabled cbi
LCDEN_PORT,LCDEN
sbi
LCDRS_DIR,LCDRS
cbi
LCDRS_PORT,LCDRS
sbi
LCDRW_DIR,LCDRW
cbi
LCDRW_PORT,LCDRW
ldi
R16,LCDDAT_Mask
;LCD Data
sts ldi sts
LCDDAT_DIR,R16 R16,0 LCDDAT_PORT,R16
;All zeros
ldi
R16,15
;Wait at
rcall
Wait1ms
;powerup
;Sel. LCD
Command Register
;LCD Write
mode
lines outputs
least 15msec after before writing to display ;tuti ami tuti legyen 250ms
; Put the LCD in 8-bit mode.
Even though
we want the display to ; operate in 4-bit mode, the only way to guarantee that our commands ; are aligned properly is to initialize in 8-bit.
(The user might have ; hit reset between nibbles of a dual 4-bit
cycle.) lds andi ori
R16,LCDDAT_PORT R16,255-LCDDAT_PORT R16,0b00000011
sts nop nop cbi
LCDDAT_PORT,R16
LCDRS_PORT,LCDRS
;Set to
cbi rcall ldi rcall
LCDRW_PORT,LCDRW LCD_pulseE R16,15 Wait1ms
;read ;1
cbi
LCDRS_PORT,LCDRS
;Set to
cbi rcall ldi rcall
LCDRW_PORT,LCDRW LCD_pulseE R16,5 Wait1ms
;read ;2
cbi
LCDRS_PORT,LCDRS
;Set to
cbi rcall ldi rcall
LCDRW_PORT,LCDRW LCD_pulseE R16,5 Wait1ms
;read ;3
;3x
probalkozunk 8 bit mode-ba rakni
Command Reg.
;wait 5ms
Command Reg.
;wait 5ms
Command Reg.
;wait 5ms
; Now it's safe to go into 4-bit mode. lds andi ori
R16,LCDDAT_PORT R16,255-LCDDAT_PORT R16,0b00000010
;4bit bus
sts rcall ldi rcall
LCDDAT_PORT,R16 LCD_pulseE R16,5 Wait1ms
;wait 5ms
mode
; *** Send the 'FUNCTION SET' command ; +------ Data: 0 = 4-bit; 1 = 8-bit ; ;
|+----- Lines: 0 = 1; 1 = 2 ||+---- Font: 0 = 5x8; 1
= 5x11 ldi rcall
R16,0b00101000 LCD_SendCmd
; *** Send the 'CURSOR/DISPLAY SHIFT' command ;
+----- S/C:
0 = cursor;
;
|+---- R/L:
0 = left; 1
1 = display = right ldi rcall
R16,0b00010100 LCD_SendCmd
; *** Send the 'ENTRY MODE' command ; +--- Direction: 0 = left; 1 = right ;
|+-- Shift Dislay: 0 =
off; 1 = on ldi rcall
R16,0b00000110 LCD_SendCmd
; *** Send the 'DISPLAY ON/OFF' command ; +---- Display: 0 = off; 1 = on ;
|+--- Cursor: 0 = off; 1
;
||+-- Blink: 0 = off; 1
= on = on ldi rcall
R16,0b00001100 LCD_SendCmd
rcall ret
LCD_Clear
;***************************************************** ;** LCD_Clear ;** ;** In: ;** ;** Out: ;** ;** ;** Alt: ;** ;** Description: ;** Clears the display and sends the cursor home. ; LCD_Clear: ldi R16,0b00000001 ;Clear LCD rcall LCD_SendCmd ldi R16,0b00000010 ;Send the cursor home rcall ret
LCD_SendCmd
;***************************************************** ;** LCD_WaitBusy ;** ;** In: ;** ;** Out: ;** ;** ;** Alt: R0, R16 ;** ;** Description: ;** Waits for the busy flag to go low. Since we're in 4-bit mode, ;** the register has to be read twice (for a total of 8 bits). ;* LCD_WaitBusy: push
R16
lds andi
R16,LCDDAT_DIR R16,255-LCDDAT_Mask
sts
LCDDAT_DIR,R16
lds ori sts rjmp
R16,LCDDAT_PORT R16,LCDDAT_Mask LCDDAT_PORT,R16 LCDWait1
ldi
R16,2
nop dec brne
R16 LCDWait01
cbi
LCDRS_PORT,LCDRS
;Set to
sbi rcall
LCDRW_PORT,LCDRW LCD_pulseE
;read ;Busy Flag
mov rcall
R16,R0 LCD_pulseE
;lower
sbrc
R16,3
;Check busy
;LCD data
bits going to input
;pull-up
LCDWait0: ;Wait min.
~1us LCDWait01:
LCDWait1: Command Reg.
read bit 7.
nibble must read flag rjmp
LCDWait0
lds
R16,LCDDAT_DIR
ori sts lds andi sts pop ret
R16,LCDDAT_Mask LCDDAT_DIR,R16 R16,LCDDAT_PORT R16,255-LCDDAT_Mask LCDDAT_PORT,R16 R16
;LCD Data
lines outputs
;All zero
;***************************************************** ;** LCD_SendCmd ;** ;** In: R16 - Command byte ;** ;** Out: ;** ;** ;** Alt: R0, R1, R16, R17 ;** ;** Description: ;** Routine to write a command to the instruction register. ; LCD_SendCmd: rcall mov swap andi
LCD_WaitBusy R1,R16 R16 R16,LCDDAT_Mask
;send upper
lds andi or sts cbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
mov andi
R16,R1 R16,LCDDAT_Mask
;send lower
lds andi or sts cbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
nibble first
Command Reg.
upper nibble
nibble
Command Reg.
lower nibble ret
;***************************************************** ;** LCD_SendChar ;** ;** In: R16 - character code ;** ;** Out: ;** ;** ;** Alt: R0,R1, R16, R17 ;** ;** Description: ;** Routine to write a character to the data register. ; LCD_SendChar: rcall LCD_WaitBusy mov R1,R16 swap R16 andi R16,LCDDAT_Mask ;send upper nibble first lds andi or sts sbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
mov andi
R16,R1 R16,LCDDAT_Mask
;send lower
lds andi or sts sbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
data Reg.
upper nibble
nibble
Data Reg.
lower nibble ret
;***************************************************** ;** LCD_Goto ;** ;** In: R16 - position ;** 0x00 - 1.row, 1.col ;** 0x40 - 1.row, 2.col ;** ;** Out: ;** ;** ;** Alt: R0, R1, R16, R17 ;** ;** Description: ;** ; LCD_Goto: ori R16,0b10000000 ;Set address Command rcall ret
LCD_SendCmd
;***************************************************** ;** LCD_PrnFLASHStr ;** ;** In: Z+RAMP - start address of string ;** ;** Out: ;** ;** ;** Alt: R0, R1, R16, R17 ;** ;** Description: ;** Print a null terminated string to LCD ; LCD_PrnFLASHStr: elpm R16,Z+ tst R16 breq LCD_PrnFLSH0 rcall LCD_SendChar rjmp LCD_PrnFLASHStr LCD_PrnFLSH0: ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) http://avr-asm.tripod.com/lcdhd44.html (1 of 2)1/20/2009 9:10:19 PM
16 BIT MATH (AVR 202)
Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/lcdhd44.html (2 of 2)1/20/2009 9:10:19 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LCD DRIVER FOR HD44780 AND 2313 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
; *************************************************************** ;Programm LCD.ASM ;Das Programm demonstriert, wie man eine LCD-Anzeige mit ;16 Zeichen x 2 Zeilen an einen AT90S2313 anschliesst. ;Es wird vorausgesetzt, dass die Anzeige einen HD44780 oder ;kompatiblen Controller verwendet. ;AT90S2313 mit 4 MHz Takt ; ***************************************************************
MATH 202 .device AT90S2313 .include "2313def.inc" ;muss im selben ;Verzeichnis stehen
MATH 32X MATH YX DIV16 XX DIV 24 24
;Definition der Steuerleitungen .equ E = PD0 ;E an Pin PD0 .equ RW = PD1 ;RW an Pin PD1 .equ RS = PD2 ;RS an Pin PD2 ;.equ LCD_cntr = PORTD ;PORTD ist Kontroll-Port ;.equ LCD_data = PORTB ;PORTB ist Daten-Port .equ BF = PB7 ;Busy flag
DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII
;LCD .equ .equ .equ .equ .equ
INT ASCII HX2ASC AVG8 222 FFT7
Befehle clear_LCD = 0b00000001 ;loesche Anzeige home_LCD = 0b00000010 ;return home set_LCD = 0b00111000 ;8 bits,2 Zeilen,5x7dots LCD_on = 0b00001110 ;schalte LCD ein entry_mode = 0b00000110 ;setze Cursor
COPY 102 ;Variablendefinition
LPM 108 EPROM 100
.def .def .def .def
SER EPROM DFLASH AT45
zeichen = r0 ;Zeichen aus der Tabelle buffer = r16 ;RX/TX Daten von/zu LCD counter = r17 ;Zaehler fuer den Text temp = r18
FLASH CARD VFX SMIL
.CSEG .ORG 0x00 ; Programm beginnt bei 0 rjmp main ; Starte Hauptprogramm
VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128
; ************************************************************** ; Subroutine init ; Initialisiere PORTD ; **************************************************************
UART BUFF
init: ldi temp,0b11111111 ;PORTD ist Ausgang out DDRD,temp cbi PORTD,E ;E initialisieren cbi PORTD,RS cbi PORTD,RW ret
USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
; *************************************************************** ; Subroutine busy_flag ; Diese Routine testet, ob die LCD-Anzeige bereit ist, einen ; neuen Befehl oder weitere Daten zu empfangen. ; ***************************************************************
DALLAS CRC busy_flag: ldi temp,0b00000000 ;PORTB ist Eingang out DDRB,temp cbi PORTD,RS ;Befehl wird gesendet sbi PORTD,RW ;setze LCD in Lesemodus sbi PORTD,E ;spreche LCD an nop nop sbic PINB,BF ;LCD bereit? rjmp busy_flag ;nein, wiederhole cbi PORTD,E ;disable LCD ret ;LCD bereit
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
; *************************************************************** ; Subroutine write_data ; Diese Routine sendet Daten zur LCD-Anzeige. ; Die Daten muessen im Register buffer uebergeben werden. ; ***************************************************************
KBD PC/128 write_data: rcall busy_flag ;LCD bereit? ldi temp,0b11111111 ;PORTB ist Ausgang out DDRB,temp sbi PORTD,RS ;Daten werden gesendet cbi PORTD,RW ;LCD in Schreibmodus sbi PORTD,E ;spreche LCD an out PORTB,buffer ;sende Daten cbi PORTD,E ;disable LCD ret
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
; *************************************************************** ; Subroutine write_instr ; Diese Routine sendet Befehle zur LCD-Anzeige. ; Der Befehl muss im Register buffer uebergeben werden. ; *************************************************************** write_instr: rcall busy_flag ;LCD bereit? ldi temp,0b11111111 ;RB ist Ausgang out DDRB,temp cbi PORTD,RS ;Befehl wird gesendet cbi PORTD,RW ;LCD in Schreibmodus sbi PORTD,E ;spreche LCD an out PORTB,buffer ;sende Befehl cbi PORTD,E ;disable LCD ret
ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************** ; Hauptprogramm ; Schreibt "AT90S2313" in die erste Zeile und "LCDRoutine" ; in die zweite Zeile des LCDs. ; *************************************************************** main: ldi temp,RAMEND ; setze Stack-Pointer out SPL,temp ; an das SRAM-Ende rcall init ; PORTD initialisieren ldi buffer,set_LCD ;setze LCD Funktion rcall write_instr ldi buffer,LCD_on ;schalte LCD ein rcall write_instr ldi buffer,clear_LCD ;loesche Anzeige rcall write_instr ldi buffer,entry_mode ;Eingabemodus rcall write_instr
;Holt den Text 'AT90S2313' aus der Tabelle und schreibt diesen in ;die erste Zeile der Anzeige ldi counter,9 ;Zeichenzaehler ldi ZL,LOW(Tabelle1*2) ;Low-Zeiger auf Tabellenanfang ldi ZH,HIGH(Tabelle1*2) ;High-Zeiger auf Tabellenanfang loop_msg1: lpm ;hole Zeichen aus Tabelle mov buffer,zeichen ;Zeichen uebergeben rcall write_data ;schreibe Zeichen in LCD adiw ZL+1 ;16-Bit Zeiger erhoehen dec counter ;alle Zeichen gesendet? brne loop_msg1 ;Nein! Sende naechstes Zeichen
;Holt den Text 'LCD-Routine' aus der Tabelle und schreibt diesen ;in die zweite Zeile der Anzeige ldi buffer,0b11000000 ;LCD-Startadresse 2.Zeile rcall write_instr ;sende Befehl ldi counter,11 ;Zeichenzaehler ldi ZL,LOW(Tabelle2*2) ;Low-Zeiger auf Tabellenanfang ldi ZH,HIGH(Tabelle2*2) ;High-Zeiger auf Tabellenanfang loop_msg2: lpm ;hole Zeichen aus Tabelle mov buffer,zeichen ;Zeichen uebergeben rcall write_data ;schreibe Zeichen in LCD adiw ZL+1 ;16-Bit Zeiger erhoehen no_carry2: dec counter ;alle Zeichen gesendet? brne loop_msg2 ;Nein! Sende naechstes Zeichen
;Endlosschleife. AVR zuruecksetzen, um Programm erneut zu starten loop: rjmp loop
;Tabelle 1 mit dem Text "AT90S2313", der in die 1.Zeile geschrieben ;werden soll Tabelle1: .DB "AT90S2313"
;Tabelle 2 mit dem Text "LCD-Routine", der in die 2. Zeile geschrieben ;werden soll Tabelle2: .DB "LCD-Routine"
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
Search
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/lcd2313.html (1 of 2)1/20/2009 9:10:53 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/lcd2313.html (2 of 2)1/20/2009 9:10:53 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LCD DRIVER II FOR HD44780 AND 2313 HOME RETRO_DAN ASM FORUM
The attached code shows how to connect, initialise and drive a 44780-based LCD in 4-bit mode.
ASM MATH TUTORIAL #1
The 2 additional pins are probably reserved for a backlight option - they were on my display from Dontronics.
TUTORIAL #2 ;----------------------------------------------------------------; ; Name: LCDMain.asm ; Title: Main routine for driving Hitach LCD display ; Version: 1.0 ; Last updated: 2001.06.04 ; Target: AT90S2313 ; ;----------------------------------------------------------------; ; DESCRIPTION ; ; Driver for Hitachi HD44780-based LCD display ; ; Display is wired to Port B. Each individual pin on the display ; is wired as follows: ; ; Pin 1 - Vss GND Supply ground ; Pin 2 - Vdd VTG Supply +ve ; Pin 3 - Vee GND Contrast adjust = maximum ; Pin 4 - RS PB4 Command/data ; Pin 5 - R/W PB5 Read/write ; Pin 6 - EN PB6 Enable ; Pin 7 - DB0 GND Data bit 0 = 0 ; Pin 8 - DB1 GND Data bit 1 = 0 ; Pin 9 - DB2 GND Data bit 2 = 0 ; Pin 10- DB3 VTG Data bit 3 = 1 to indicate 2-line display at
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7
startup
COPY 102
; Pin 11- DB4 PB0 Data bit 4 = PortB:0 ; Pin 12- DB5 PB1 Data bit 5 = PortB:1 ; Pin 13- DB6 PB2 Data bit 6 = PortB:2 ; Pin 14- DB7 PB3 Data bit 7 = PortB:3 ; Pin 15- (if present) No connection ; Pin 16- (if present) No connection ; ;-----------------------------------------------------------------
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
.nolist .include "2313def.inc" .list
VFX MEM SORT 220 CRC 236
;----------------------------------------------------------------; ; General purpose registers
XMODEM REC UART 304 UART 305
.def rRETURN =r0 ; return value from functions
UART 128
.def rZERO =r1
UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300
.def .def .def .def
rSCRATCH =r7 rSCRATCH2 =r8 rSCRATCH3 =r9 rSCRATCH4 =r10
.def .def .def .def
rISCRATCH =r11 ; for use in interrupt routines rISCRATCH2 =r12 ; ditto rISCRATCH3 =r13 ; ditto rISCRATCH4 =r14 ; ditto
I2C 302 .def rISREGSAVE =r15 ; sreg saved here in interrupts
I2C TWI26 I2C/TWI 128
.def rTEMP =r16 .def rTEMP2 =r17
I2C/TWI AT8 DALLAS-1W
.def rITICK =r18 ; Decreasing tick, used for delays .def rITEMP =r19
DALLAS CRC ETHNET 8019
.def rPARAM1 =r20 .def rPARAM2 =r21
TEA ADC 128
.def rLOOPI =r22 ; loop counters .def rLOOPJ =r23
ADC 10B ADC 400
;----------------------------------------------------------------; ; Equates
ADC 401 THERM 232 IRD 410
;----------------------------------------------------------------; ; IO Port Bits
LCD HD44 LCD 2313
.equ .equ .equ .equ
LCD44 2313 KBD 240 MUX 242 KBD PS2
mDATA =0x0F bRS =4 bRW =5 bEN =6
;----------------------------------------------------------------; ; Timings ; ; We need a multiple of 100Hz for the clock tick, so for 4MHz ; this equates to 40,000 clock cycles, and for a 3.6864MHz clock, ; this is 36,864 cycles. Given the prescaler values available ; on counter/timer 0, we get the following: ; ; Divider Counts 4MHz Counts 3.7MHz In range? ; Clk/8 5000 4608 No (greater than 255) ; Clk/64 625 576 No (greater than 255) ; Clk/64 125 for 500Hz 144 for 400Hz Yes ; ; The actual values loaded into the registers are these values ; subtracted from 256, since we are counting up, and the clock ; interrupt happens when the clock register overflows to 256.
KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K
.equ TIMERSCALE =$03 ; Clk/64
ENCODE STH-11
; Timer value for 3.6864 MHz clock .equ TIMERVALUE = (256-144) .equ TICKVALUE = 4 ; 4 x 400Hz ticks = 100Hz clock
ATMEL CORP AVR BUTTERFLY
; Timer value for 4 MHz clock ; .equ TIMERVALUE = (256-125) ; .equ TICKVALUE = 5 ; 5 x 500Hz ticks = 100Hz clock
AVR BOOK
;----------------------------------------------------------------; ; Variables .dseg tickcount: .byte 1 ; clock count to 4 or 5 for centiseconds centi: .byte 1 ; centisecond count second: .byte 1 ; second count minute: .byte 1 ; minute hour: .byte 1 ; hour day: .byte 1 ; day ;----------------------------------------------------------------; ; Interrupt service vectors .cseg .org 0 rjmp Reset ; Reset vector .org OVF0addr rjmp Timer0 ; Timer tick
;----------------------------------------------------------------; ; Start of actual code. ; ;----------------------------------------------------------------; ; Timer 0 overflow - decreases tick count in tickcount until it ; reaches 0, then ripples the count along to the next biggest ; counter, all the way up to the "days" count. Timer0: in rISREGSAVE,SREG ; store status register ldi rITEMP,TIMERVALUE ; reset counter out TCNT0,rITEMP ; to start counting again mov rISCRATCH,YL ; store Y register mov rISCRATCH2,YH ; since we will be using it dec rITICK ; decrease register tick count ldi YL,low(tickcount) ; Y points to tick count clr YH ld rITEMP,Y ; get tick count inc rITEMP ; increment it cpi rITEMP,TICKVALUE ; is it the target value yet? brne Timer0_Done ; no... exit immediately clr rITEMP ; yes - clear it and store it again st Y+,rITEMP ; increment Y to point to centiseconds ; ; We get through to here once every 4 or 5 timer ticks, in ; other words, 100 times every second. ; ld rITEMP,Y ; load centiseconds inc rITEMP ; increment cpi rITEMP,100 ; and check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to seconds ld rITEMP,Y ; load seconds inc rITEMP ; increment cpi rITEMP,60 ; check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to minutes ld rITEMP,Y ; load minutes inc rITEMP ; increment cpi rITEMP,60 ; check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to hours ld rITEMP,Y ; load hours inc rITEMP ; increment cpi rITEMP,24 ; check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to days ld rITEMP,Y ; load days inc rITEMP ; and increment ; ; However we get here, the most recently incremented value is in rITEMP, ; and Y points to where we got it from. ; Timer0_Done: st Y,rITEMP ; store valid value back again mov YL,rISCRATCH ; restore saved Y pointer mov YH,rISCRATCH2 out SREG,rISREGSAVE ; restore status register reti ; and return from interrupt, done. ;----------------------------------------------------------------; ; WaitTick ; Waits for between rPARAM1 and rPARAM1+1 timer ticks, depending ; on exactly when the next tick is about to happen. Each tick takes ; 20ms on a 4MHz clock, or 25ms on a 3.6864MHz clock. This is enough ; to act as a timed delay for those commands which take more than ; the 40us "standard" delay. WaitTick: inc rPARAM1 mov rITICK,rPARAM1 WaitTick_Loop: and rITICK,rITICK brne WaitTick_Loop ret
;----------------------------------------------------------------; ; Reset vector - generic system. Reset: ldi rTEMP,RAMEND-1 ; Set stack to end of RAM out SPL,rTEMP ; Get the timer going ldi rTEMP,(1< out TIMSK,rTEMP ldi rTEMP,TIMERVALUE ; timer value out TCNT0,rTEMP ldi rTEMP,TIMERSCALE ; clock prescaler for Timer 0 out TCCR0,rTEMP ; ; And allow timer interrupts ; sei ; Set port B to all output, all 0. ldi rTEMP,$00 out PORTB,rTEMP ldi rTEMP,$FF out DDRB,rTEMP ; ; Now initialize the display ; rcall InitDisplay ; ; And reset the displayed time to 00 00:00:00.00 ; clr sts sts sts sts sts sts
rTEMP tickcount,rTEMP centi,rTEMP second,rTEMP minute,rTEMP hour,rTEMP day, rTEMP
ldi rPARAM1,0x00 rcall LCDGoto ; go to display position 0 ldi ZL,low(String*2) ldi ZH,high(String*2) rcall LCDString ; and send string Loop: ldi rPARAM1,0x40 rcall LCDGoto ; go to display position 0x40 (2nd line) lds rPARAM1,day ; get the day rcall LCDNumber ; output as a 2-digit number ldi rPARAM1,' ' ; followed by a space, rcall WriteData lds rPARAM1,hour ; then the hour rcall LCDNumber ; as a 2 digit number ldi rPARAM1,':' ; followed by a colon rcall WriteData lds rPARAM1,minute ; then the minute rcall LCDNumber ; as a 2 digit number ldi rPARAM1,':' ; followed by a colon rcall WriteData lds rPARAM1,second ; then the second rcall LCDNumber ; as a 2 digit number ldi rPARAM1,'.' ; followed by a decimal point rcall WriteData lds rPARAM1,centi ; and finally the 1/100ths of a second rcall LCDNumber ; yes, as a 2 digit number. lds rTEMP,centi ; get the centiseconds "then" Wait: lds rTEMP2,centi ; get the centiseconds "now" cp rTEMP,rTEMP2 ; same? breq Wait ; yes... go round again and wait till it changes rjmp Loop ; then display all over again, for ever
;----------------------------------------------------------------; ; InitDisplay ; Initialize display as shown in data sheet. InitDisplay: ; Initial power-up delay ; Wait for 15ms or more (100-125ms in fact) ldi rPARAM1,5 rcall WaitTick ; Send 8-bit mode command ldi rTEMP2,0x03 ; 8 bit mode indicator rcall Strobe ; and strobe it out ; Wait again ldi rPARAM1,1 ; min 20ms delay (4ms + leeway) rcall WaitTick ; until ready to receive ; Send 8-bit mode command again ldi rTEMP2,0x03 ; 8 bit mode indicator rcall Strobe ; and strobe it out ; Wait again ldi rPARAM1,100 ; 100us rcall WaitMicro ; until ready to receive ; Now 4-bit mode command to actually place us in 4-bit mode ; as originally required. ldi rTEMP2,0x02 ; 4 bit mode indicator rcall Strobe ; and strobe it out ; Wait ldi rPARAM1,100 ; 100us rcall WaitMicro ; until ready to receive ; ; We can now use the normal functions for writing data, ; which are designed to work with 4-bit mode data timings ; ; Function set ldi rPARAM1,0x28 ; 4 bit, dual line rcall WriteInstruction ; Display on ldi rPARAM1,0x0E ; display on, cursor on, no blink. rcall WriteInstruction ; Display clear ldi rPARAM1,0x01 rcall WriteInstruction ldi rPARAM1,1 ; min 20ms delay (4ms + leeway) rcall WaitTick ; until ready to receive
; Entry mode set ldi rPARAM1,0x06 ; Advance cursor, no shift rcall WriteInstruction ret ;----------------------------------------------------------------; ; LCDGoto ; Go to character position rPARAM1 LCDGoto: ori rPARAM1,0x80 rjmp WriteInstruction ;----------------------------------------------------------------; ; LCDNumber ; Write number from 00 to 99 at current position LCDNumber: mov rPARAM2,rPARAM1 ldi rTEMP,'0' LCD10s: subi rPARAM2,10 brmi LCD1s inc rTEMP rjmp LCD10s LCD1s: mov rPARAM1,rTEMP rcall WriteData subi rPARAM2,-(0x3A) mov rPARAM1,rPARAM2 rjmp WriteData ;----------------------------------------------------------------; ; LCDString ; Write string at Z from flash to LCD at current position LCDString: lpm and r0,r0 breq LCDString_End adiw ZL,1 mov rPARAM1,r0 rcall WriteData rjmp LCDString LCDString_End: ret
;----------------------------------------------------------------; ; WriteData ; Write rPARAM1 as data WriteData: ldi rTEMP,(1< rjmp Write ;----------------------------------------------------------------; ; WriteInstruction ; Write rPARAM1 as instruction WriteInstruction: ldi rTEMP,0 Write: mov rTEMP2,rPARAM1 swap rTEMP2 andi rTEMP2,$0F or rTEMP2,rTEMP rcall Strobe mov rTEMP2,rPARAM1 andi rTEMP2,$0F or rTEMP2,rTEMP rcall Strobe rjmp Wait40 ;----------------------------------------------------------------; ; Strobe ; Output rTEMP2 to PortB and then strobe the enable line Strobe: out PORTB,rTEMP2 nop nop nop sbi PORTB,bEN nop nop nop cbi PORTB,bEN ret ;----------------------------------------------------------------; ; Wait40, WaitMicro ; Wait 40 (or rPARAM1) microseconds Wait40: ldi rPARAM1,40 ; 40uS WaitMicro: ; 4 cycles nop ; per loop dec rPARAM1 ; at 4 MHz brne WaitMicro ; = 1 uS per loop ret ;----------------------------------------------------------------; ; ReadStatus ; Read Status into rReturn. ReadStatus: ldi rTEMP,(1< rjmp Read ;----------------------------------------------------------------; ; ReadData ; Read Data into rReturn ReadData: ldi rTEMP,(1< Read: out PORTB,rTEMP nop sbi PORTB,bEN nop nop in rTEMP,PINB cbi PORTB,bEN andi rTEMP,0x0F swap rTEMP sbi PORTB,bEN mov rRETURN,rTEMP nop in rTEMP,PINB cbi PORTB,bEN andi rTEMP,0x0F or rRETURN,rTEMP rjmp Wait40 ;----------------------------------------------------------------; ; WaitBusy ; Waits until device is not busy WaitBusy: rcall ReadStatus and rRETURN,rRETURN brmi WaitBusy ; if bit 7 still set, go round again ret ;----------------------------------------------------------------; ; Strings to display String: .db "Time since start:", 0 ;-----------------------------------------------------------------
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead http://avr-asm.tripod.com/lcd44.html (1 of 2)1/20/2009 9:11:30 PM
16 BIT MATH (AVR 202)
CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/lcd44.html (2 of 2)1/20/2009 9:11:30 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
KEYPAD WAKE UP (AVR 240) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
[email protected]
DESCRIPTION This Application note scans a 4 x 4 keypad and uses The design
;* external components. Included is a test program that
DIV 24 24
flashes one of two LEDs
;* and performs a scan when a key is pressed and ;* the number of the key pressed.
The external
interrupt line is used for
FLOAT 128
;* wake-up.
The example runs on the AT90S1200 but can
be any AVR with suitable ;* changes in vectors, EEPROM and stack pointer. The timing assumes a 4 MHz clock. ;* A look up table is used in EEPROM to enable the same
MATH 202 DEC ASCII
Support E-mail:
uses a minimum of wakes up the AVR
MATH 202
4x4 keypad, wake-up on keypress 1.2 2004.11.11 All AVR Devices
;* causing the AVR to wake up on keypress.
DIV16 XX
SQRT16
Title: Version: Last Updated: Target:
sleep mode
MATH YX
DIV 3216
A V R 2 4 0
************************
ASM MATH
MATH 202
N O T E
structure to be used ;* with more advanced programs e.g ASCII output to
INT ASCII
displays.
HX2ASC
; ***************************************************************************
AVG8 222 ;***** Register used by all programs ;******Global variable used by all routines
FFT7 COPY 102
.def
LPM 108 EPROM 100
temp
=r16
;general scratch space
=3 =2 =1 =0 =7 =6 =5 =4
;keypad input rows
=0 =1 =2
;green LED ;red LED ;interrupt input
;Port B pins
SER EPROM .equ .equ .equ .equ .equ .equ .equ .equ
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220
ROW1 ROW2 ROW3 ROW4 COL1 COL2 COL3 COL4
;keypad output columns
CRC 236 ;Port D pins
XMODEM REC UART 304
.equ .equ .equ
UART 305 UART 128 UART BUFF
GREEN RED INTR
.include "1200def.inc"
USB 232
;***** Registers used by interrupt service routine
AVR ISP ISP 2313 .def .def
ISP 1200
key status
=r17 =r21
;key pointer for EEPROM ;preserve sreg here
AVR SPI ;***** Registers used by delay subroutine ;***** as local variables
I2C 300 I2C 302
.def .def .def
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
fine medium coarse
=r18 =r19 =r20
;loop delay counters
;*****Look up table for key conversion****************************** .eseg segment .org 0
;EEPROM
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
.db 1,2,3,15,4,5,6,14,7,8,9,13,10,0,11,12 ;****Source code*************************************************** .cseg ;CODE segment .org 0 rjmp reset ;Reset handler rjmp scan ;interrupt service routine reti ;unused timer interrupt reti ;unused analogue interrupt ;*** Reset handler ************************************************** reset:
KBD PC/128 PS2 EMU BOOT MG8
ldi temp,0xFB
;initialise port D
out DDRD,temp
;all OUT except PD2
ldi temp,0x30
;turn on sleep mode
out MCUCR,temp
;down plus
ldi temp,0x40
;enable external
out GIMSK,temp sbi ACSR,ACD
;shut down
as O/I ext.int.
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS
and power interrupt on low level. interrupts
DELAYS CALL ID
comparator to save power
DTMF 314
main:
PWM 6CH
global interrupts
PWM 10K
as I/O
cli ldi temp,0xF0
;initialise port B
out DDRB,temp ldi temp,0x0F
; 4 OUT 4 IN ;key columns all
out PORTB,temp
;active pull ups on
ldi temp,0x07
;enable pull up on
out PORTD,temp sei
;turn off LEDs ;enable global
sleep rcall flash
;fall asleep ;flash LEDs for
ldi temp,0x40 out GIMSK,temp
;enable external
rjmp main
;go back to sleep
ENCODE STH-11
low and
ATMEL CORP AVR BUTTERFLY
;disable
rows enabled PD2 and
AVR BOOK interrupts ready
example usage
interrupt after keyscan ;****Interrupt service routine*************************************** scan: in status,SREG register sbis PINB,ROW1 keypress ldi key,0 sbis PINB,ROW2 ldi key,4 sbis PINB,ROW3 ldi key,8 sbis PINB,ROW4 ldi key,12 ldi temp,0x0F to out DDRB,temp ldi temp,0xF0 out PORTB,temp rcall settle port to settle sbis PINB,COL1 keypress ldi temp,0 sbis PINB,COL2 ldi temp,1 sbis PINB,COL3 ldi temp,2 sbis PINB,COL4 ldi temp,3 add key,temp for pointer ldi temp,0xF0 B as I/O out DDRB,temp ldi temp,0x0F low and out PORTB,temp rows enabled out SREG,status register
;preserve status ;find row of ;and set ROW pointer
;change port B I/O ;find column press ;enable pull ups and ;write 0s to rows ;allow time for ;find column of ;and set COL pointer
;merge ROW and COL ;reinitialise port ; 4 OUT 4 IN ;key columns all ;active pull ups on ;restore status
ldi temp,0x00 out GIMSK,temp
;disable external
interrupt ;have to do this, because we're ;using a leveltriggered interrupt reti
;go back to main
for example program ;***Example test program to flash LEDs using key press data************ flash:
out EEAR,key
;address
EEPROM sbi EECR,EERE in temp,EEDR
;strobe EEPROM ;set number of
tst temp breq zero
;is it zero? ;do RED LED
flashes
green_flash: cbi PORTD,GREEN ;flash green LED 'temp' times rcall delay sbi PORTD,GREEN rcall delay dec temp brne green_flash ret ldi temp,10 cbi PORTD,RED
exit: zero: flash_again:
;flash red
LED ten times rcall delay sbi PORTD,RED rcall delay dec temp brne flash_again rjmp exit
;****Time Delay Subroutine for LED flash********************************* delay: ldi coarse,8 ;triple nested FOR loop cagain: ldi medium,255 ;giving about 1/2 second magain: ldi fine,255 ;delay on 4 MHz clock fagain: dec fine brne fagain dec medium brne magain dec coarse brne cagain ret ;***Settling time delay for port to stabilise****************************** settle: ldi temp,255 tagain: dec temp brne tagain ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/kbd240.html (1 of 2)1/20/2009 9:12:04 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/kbd240.html (2 of 2)1/20/2009 9:12:04 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
KEYPAD LED MUX (AVR 242) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* Title: ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202
MATH YX DIV16 XX
;* four digit LED display and two ON/OFF outputs to ;* interface circuitry.
Tactile feedback is provided ;* on every key press by a piezo sounder which beeps when a key is pressed. ;* Included is a main program that allows clock setting via the keypad
INT ASCII
;* and one ON/OFF time setting per 24 hours for each load, functions for the ;* real time clock, key scanning, and adjustment routines. The example runs on ;* the AT90S1200 to demonstrate how limited I/O
EPROM 100
;* be any AVR with suitable changes in vectors, EEPROM and stack pointer. ;* The timing assumes a 4.096 MHz crystal is employed (a 4 MHz crystal produces ;* an error of -0.16% if 178 instead of 176 used in the
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
timer load sequence, but this ;* could be adjusted in software at regular intervals). Look up tables are ;* used in EEPROM to decode the display data, with additional characters provided
VFX MEM SORT 220
can be
overcome, but can
COPY 102 LPM 108
LED loads are driven in this
;* any load with the addition of suitable components.
SQRT16
FFT7
DESCRIPTION This Application note covers a program to provide a
multiplexed
example but it could drive
AVG8 222
[email protected]
;* With input via a 4 x 4 matrix keypad, output to a
FLOAT 128
HX2ASC
Support E-mail:
functions.
drive loads via additional
DEC ASCII
1.0 98.07.24 All AVR Devices
;* timer or real-time clock using I/O pins for dual
DIV 3216
MATH 202
Version: Last Updated: Target:
24 hr Industrial
DIV 24 24
MATH 202
Multiplexing LED drive and 4x4
keypad sampling
TUTORIAL #2
MATH 32X
A V R ???
************************
ASM MATH TUTORIAL #1
N O T E
;* for time and ON/OFF setting displays and a key pad conversion table. ;* If the EEPROM is needed for your application the
CRC 236 XMODEM REC UART 304
tables could be moved ;* to ROM in the larger AVR devices. ; ***************************************************************************
UART 305 ;***** Registers used by all programs ;******Global variables used by routines
UART 128 UART BUFF
.def .def
loset hiset
.def
ld1minon=r3
;storage for load on and
.def .def
ld1hron =r4 ld1minoff=r5
;set from keypad entry ;and tested in the
.def
ld1hroff=r6
;and stores on or off times
.def .def .def .def
ld2minon=r7 ld2hron =r8 ld2minoff=r9 ld2hroff=r10
.def .def
temp second
=r16 =r17
;general scratch space ;storage for RTC second
.def
minute
=r18
;storage for RTC minute
.def .def
hour mask
=r19 =r20
;storage for RTC hour count ;flash mask for digits
.def .def .def .def
blink bounce flash lobyte
=r21 =r22 =r23 =r24
;colon blink rate counter ;keypad debounce counter ;flash delay counter ;storage for display
.def
hibyte
=r25
;storage for display
.def
key
=r26
;key number from scan
USB 232 AVR ISP
off times
AVR SPI I2C 300 I2C 302
housekeeping function for the loads
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA
count count
ADC 128 ADC 10B
flashing
ADC 400 ADC 401 THERM 232
function minutes digits
IRD 410 LCD HD44
function hours digits
LCD 2313
;***'key' values returned by
LCD44 2313 KBD 240 MUX 242 KBD PS2
'keyscan'*************************** 11 9
12 13 D
14
A
0
15 B
C
90 DAYS
1
2
3
4
5
6
7
8
9
;KEY
1
2
3
F
4
5
6
E
7
8
;FUNC
1
2
3 LD1ON 4
5
6 LD1OFF 7
8
.def .def
tock flags
=r27 =r28
2
1
;5 ms pulse ;flag byte for keypad
;
7
6
;
5ms
5
4
3
0 keyok ld2off ld2on ld1off
ld1on ld2 ld1 .equ
ms5
; tick =7
0 = off, 1 = on ;ticks at 5 ms intervals
.equ
keyok
=6
;sets when key is
.equ
ld2off
=5
;set by load ON/OFF key
.equ .equ .equ .equ
ld2on ld1off ld1on ld2
=4 =3 =2 =1
;up the need for action ;in the housekeeping routine
.equ
ld1
=0
;check load on/off times.
for display time
DTMF 314 PWM 6CH
debounced, must be cleared again
PWM 10K
press and flags
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
9
command keys
DELAYS CALL ID
10
LD2ON SET 0 CLEAR LD2OFF
BOOT DR8
CLOCK 8564
0
NONE
BOOT MG8
ALM CLK
;VALUE 16
KBD PC/128 PS2 EMU
;storage for timeset minutes ;storage for timeset
hours
ISP 2313 ISP 1200
=r1 =r2
;when set tells the
housekeeping routine to
;***the T flag in the status register is used as a SET
AVR BOOK flag for time set
.equ
clear
=0
;RTC modification demand
=0 =1 =2 =3 =4 =5 =6 =7
;LED ;LED ;LED ;LED ;LED ;LED ;LED ;LED
flag
;Port B pins .equ .equ .equ .equ .equ .equ .equ .equ
col1 col2 col3 col4 row1 row2 row3 row4
a segment/keypad col b segment/keypad col c segment/keypad col d segment/keypad col e segment/keypad row f segment/keypad row g segment/keypad row decimal point/keypad
1 2 3 4 1 2 3
row 4 ;Port D pins .equ
A1
=0
;common anode drives
.equ .equ .equ .equ .equ .equ
A2 A3 A4 LOAD1 LOAD2 PZ
=1 =2 =3 =4 =5 =6
; ; ; ;Load 1 output (active low) ;Load 2 output (active low) ;Piezo sounder output
(active low)
(active low) .include "1200def.inc" ;***** Registers used by timer overflow interrupt service routine
.def
timer
=r31
;scratch space for timer
.def
status
=r0
;low register to preserve
loading status register ;*****Look up table for LED display decoding ********************** .eseg
;EEPROM
segment .org 0 table1: .db 0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90 ;digit 0 8 9 .db ;digit
1
2
3
4
5
6
7
0x86,0x8E,0xA3,0xAB,0XFF,0XFF E f o n BLANK
special
characters ;****Look up table for key value conversion into useful numbers**** ;key 0
B
1
2
3
F
4
5
6
E
7
8
9
D
A
C table2:
.db
1, 2, 3,15, 4, 5, 6,14, 7, 8, 9,
13, 10, 0, 11, 12 ;value 13
14
0
1
2
3
4
5
6
7
8
9
10
11
12
15
;****Source code*************************************************** .cseg segment .org 0 rjmp reset nop interrupt rjmp tick overflow (5 ms) nop interrupt
;CODE
;Reset handler ;unused ext. ;timer counter ;unused analogue
;*** Reset handler ************************************************** ;*** to provide initial port, timer and interrupt setting up reset: ser temp out DDRB,temp
; ;initialize port B
out DDRD,temp
;initialize port D
out PORTB,temp
;key columns all
out PORTD,temp
;turn off LEDs and
ldi temp,0x04
;timer
out TCCR0,temp ldi timer,176 out TCNT0,timer
;load timer for 5 ms ;(256 - n)
ldi temp,0x02
;enable timer
out clr clr clr
;clear control flags ;clear 5 ms tick ;clear key bounce
as all Outputs as all Outputs high/LEDs off loads off prescalar /256
*256*0.2441 us interrupts TIMSK,temp flags tock bounce
counter clr flash clr blink sei
;enable global
interrupts ;****Flash EEEE on LEDS as test and power down warning************** ;****repeats until SET key is pressed on keypad
timesetting:
ldi hibyte,0xaa
;show
"EEEE" on LED ldi lobyte,0xaa ser mask
;display and ;set flashing
display notyet:
rcall display
;display
until time set brtc notyet
;repeat until SET
rcall setrtc
;and reset
mov hour,hiset
;and reload
mov minute,loset clt
;and minutes ;clear T flag
key pressed time hours
;*****Main clock house keeping loop***************************** do: clr mask cpi blink,100 brne nohalf clr blink com flash
;do housekeeping ;is half second up
cpi second,60 brne nochange clr second
;is one minute up? ;no ;yes clear seconds
inc minute mov temp,minute andi temp,0x0f cpi temp,10 brne nochange andi minute,0xf0 ldi temp,0x10 add minute,temp
;add one to minutes
cpi minute,0x60 brne nochange clr minute
;is it 60 minutes? ;no ;yes, clear minutes
inc hour mov temp,hour andi temp,0x0f cpi temp,10 brne nochange andi hour,0xf0 ldi temp,0x10 add hour,temp
;add one to hours
cpi hour,0x24
;is it 24
brne sameday clr hour
;no, ;yes, clear time
clr minute clr second
;to start new day
;invert flash
nohalf:
and
;mask high minute ;is it ten minutes? ;no ;clear low minutes ;increment high
minutes
and
;mask high hour ;is 10 hours up? ;no ;yes, increment ;high hours
nochange: hours?
variables
sameday:
;update times mov lobyte,minute mov hibyte,hour rcall display brtc case1 rcall setrtc
;show time for 20 ms ;if not SET ;and reset
mov hour,hiset
;and reload
mov minute,loset clt
;and minutes ;else, clear T
time hours
flag case1:
sbrc flags,ld1
;is load 1
case2:
rjmp chkload1 sbrc flags,ld2
;yes, check load 1 ;is load 2
case3:
rjmp chkload2 ;yes, check load 2 sbrc flags,ld1on ;is load 1
case4:
rjmp setld1on ;yes reset on time sbrc flags,ld1off ;is load 1
case5:
rjmp setld1off ;yes reset off time sbrc flags,ld2on ;is load 2
case6:
rjmp setld2on ;yes reset on time sbrc flags,ld2off ;is load 2
case7:
rjmp setld2off rjmp do
active?
active
on time reset
off time reset
on time reset
on time reset ;yes reset on time ;repeat
housekeeping loop ;****case routines to service load times and key presses********
chkload1:
cp hour,ld1hroff
;is load 1 off time
brne onload1 cp minute,ld1minoff brne onload1 sbi PORTD,LOAD1
;yes, turn load 1
cp hour,ld1hron
;is load 1 on time
brne case2 cp minute,ld1minon brne case2 cbi PORTD,LOAD1 rjmp case2
;yes,turn load 1 on ;repeat with load on
cp hour,ld2hroff
;is load 2 off time
brne onload2 cp minute,ld2minoff brne onload2 sbi PORTD,LOAD2
;yes, turn load 2
cp hour,ld2hron
;is load 2 on time
brne case3 cp minute,ld2minon brne case3 cbi PORTD,LOAD2 rjmp case3
;yes,turn load 2 on ;repeat with load on
reached?
off onload1: reached?
chkload2: reached?
off onload2: reached?
setld1on: sbr flags,0x01 rcall setrtc mov ld1hron,hiset mov ld1minon,loset cbr flags,0x04 rjmp case4
;make load 1 active ;pickup new on time ;and store
rcall setrtc mov ld1hroff,hiset mov ld1minoff,loset cbr flags,0x08 rjmp case5
;pickup new off time ;and store
sbr flags,0x02 rcall setrtc mov ld2hron,hiset mov ld2minon,loset cbr flags,0x10 rjmp case6
;make load 2 active ;pickup new on time ;and store
rcall setrtc mov ld2hroff,hiset mov ld2minoff,loset cbr flags,0x20 rjmp case7
;pickup new on time ;and store
;clear ld1on flag
setld1off:
;clear ld1off flag
setld2on:
;clear ld2on flag
setld2off:
;clear ld2off flag
;****Multiplexing routine to display time and scan keypad every***** ;****second pass,used by all routines taking digits from hibyte ;****and lobyte locations with each digit on for 5 ms display:
ser temp ;clear display out PORTB,temp ;****Keypad scanning routine to update key flags******************* keyscan:
cbr flags,0x40 ldi key,0x10
;clear keyok flag ;set no key pressed
ser temp
;set keypad port
out PORTB,temp
;reinitializing the
in temp,PORTD
;turn off LEDs and
ori temp,0x0f out PORTD,temp ldi temp,0x0f
;untouched prior to ;key scan ;set columns output
out DDRB,temp
;rows input with
ldi temp,0xf0
;enabled and all
out PORTB,temp ldi temp,20 dec temp brne tagain1 sbis PINB,ROW1
;low ready for scan ;short settling time
ldi key,0 sbis PINB,ROW2 ldi key,4 sbis PINB,ROW3 ldi key,8 sbis PINB,ROW4 ldi key,12 ldi temp,0xF0
;and set ROW pointer
out DDRB,temp ldi temp,0x0F out PORTB,temp ldi temp,20 dec temp brne tagain2
;find column press ;enable pull ups and ;write 0s to rows ;short settling time
value high prior to port leave loads
and pull-ups columns
tagain1:
;find row of
keypress
;change port B I/O
to
tagain2:
;allow time for
port to settle clr temp sbis PINB,COL1
;find column of
keypress ldi temp,0 sbis PINB,COL2 ldi temp,1 sbis PINB,COL3 ldi temp,2 sbis PINB,COL4 ldi temp,3 add key,temp
;and set COL pointer
cpi key,0x10 breq nokey
;if no key pressed ;escape routine,
ldi temp,0x10 add key,temp out EEAR,key
;change to table 2 ;send address to
sbi EECR,EERE in key,EEDR
;strobe EEPROM ;read decoded
cpi key,10 brne notset set
;is it SET key ? ;no check next key ;yes set T flag in
;merge ROW and COL
for pointer
else
EEPROM (0 - 15)
number for true key convert:
status register notset:
cpi key,11
;is key
CLEAR? brne notclear sbi PORTD,LOAD1
;no, check next key ;yes, shut down all
sbi PORTD,LOAD2 cbr flags,0x03
;deactivate both
cpi key,15 brne notld1on sbr flags,0x04 cpi key,14 brne notld1off sbr flags,0x08
;is key LD1ON? ;no, check next key ;yes, set LD1ON flag ;is key LD1OFF? ;no, check next key ;yes, set LD1OFF
cpi key,13 brne notld2on sbr flags,0x10 cpi key,12 brne notld2off sbr flags,0x20
;is key LD2ON? ;no, check next key ;yes, set LD2ON flag ;is key LD2OFF? ;no, check next key ;yes, set LD2OFF
loads
loads notclear:
notld1on:
flag notld1off:
notld2on:
flag notld2off: ;***Tactile feedback note generation routine***************** ;***provides a 4 kHz TONE to the piezo sounder for 5 ms***** tactile:
t1again:
t2again:
notok:
nokey:
cbr flags,0x80 cbi PORTD,PZ ldi temp,125 dec temp brne t1again sbi PORTD,PZ ldi temp,125 dec temp brne t2again sbrs flags,ms5 rjmp tactile cpi bounce,40 brlo nokey sbr flags,0x40 ser temp out DDRB,temp
;turn on piezo ;for a short time
;turn on piezo ;for a short time
;repeat for 5ms
;set bounce flag ;reinitialize port
B as all Outputs out PORTB,temp
;and clear LEDs
;***Display routine to multiplex all four LED digits**************** cbi PORTD,A1 mov temp,lobyte
;turn digit 1 on ;find low minute
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash every 1/2
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
digit1: flag of digit EEPROM (0 - 15)
second needed ms led1:
sbrs flags,ms5
;5 ms
finished? rjmp led1 sbi PORTD,A1 ser temp out PORTB,temp cbi PORTD,A2 mov temp,lobyte swap temp
;no, check again ;turn digit 1 off ;clear display
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash every 1/2
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
; ;find high minute
digit2: flag of digit EEPROM (0 - 15)
second needed ms led2:
sbrs flags,ms5
;5 ms
finished? rjmp led2 sbi PORTD,A2 ser temp out PORTB,temp cbi PORTD,A3 mov temp,hibyte
;no, check again ; ;clear display
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs second,clear andi temp,0x7f sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash colon
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
;
digit3: flag of digit EEPROM (0 - 15)
;flash every 1/2
second needed ms led3:
sbrs flags,ms5
;5 ms
finished? rjmp led3 sbi PORTD,A3 ser temp out PORTB,temp cbi PORTD,A4 mov temp,hibyte swap temp andi temp,0x0f brne digit4 ldi temp,0xff
;no, check again
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash every 1/2
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
;clear display ;
;is hi hour zero? ;yes,blank hi hour
digit4: flag of digit EEPROM (0 - 15)
second needed ms led4:
sbrs flags,ms5
;5 ms
finished? rjmp led4 sbi PORTD,A4 ser temp out PORTB,temp tst mask breq outled cpi blink,50 brlo outled clr blink
;no, check again
com flash
;and invert flash
;clear display ;is flash complete? ;yes, exit ;is blink time done? ;no, exit ;yes, clear blink
rate counter byte outled:
ret
;****Function to Set RTC/on-off hours and minutes from keypad ;****returns with minutes in 'loset' and hours in'hiset' setrtc:
ser mask
;set
flashing display ldi hibyte,0xdf
;place 'n' in hi
ser lobyte
;and blank in lo hr
clr bounce rcall display
;display and check
hour & minutes hihrus: bounce1: keypad sbrs flags,keyok rjmp bounce1 cbr flags,0x40 cpi key,0x03 brsh hihrus hihrok:
;clear keyok flag ;is high hour > 2 ;yes, read key again ;no, valid
entry swap key
;move hihour to hi
mov hiset,key ldi hibyte,0x0d
;and store in hours ;place 'n' in lo
add hibyte,hiset
;merge hihour and
clr bounce rcall display
;display and check
sbrs flags,keyok rjmp bounce2 cbr flags,0x40
;is key stable? ;no try again ;yes, clear keyok
mov temp,hibyte
;check that total
andi temp,0xf0 add temp,key cpi temp,0x24 brsh lohrus add hiset,key
;are not > 24
mov hibyte,hiset
;display hours as
ldi lobyte,0xdf
;place 'n' in hi
clr bounce rcall display
;display and check
sbrs flags,keyok rjmp bounce3 cbr flags,0x40 cpi key,6 brsh himinus
;clear keyok flag ;is hi minutes >5 ;no, read key again
swap key
;move himin to hi
mov loset,key
;and store in
ldi lobyte,0x0d
;place 'n' in lo
add lobyte,loset
;merge with hi
clr bounce rcall display
;display and check
sbrs flags,keyok rjmp bounce4 cbr flags,0x40 cpi key,10 brsh lominus add loset,key
;clear keyok flag ;is key >9 ;no, read key again ;yes, merge hi and
clr mask ret
;clear digits flash ;and return with
nibble
hour 'n' lohrus: bounce2: keypad
flag hours
;is hour>24? ;yes, read key again ;no, merge hi and
lo hours lohrok: set minutes himinus: bounce3: keypad
lominok: nibble minutes minutes minute lominus: bounce4: keypad
lo minutes
time set ;****Timer Overflow Interrupt service routine****************************** ;****Updates 5 ms, flash and debounce counter to provide RTC time reference tick: in status,SREG
;preserve status
inc tock
;add one to 5 ms
inc blink
;and blink rate
inc bounce
;and bounce rate
sbr flags,0x80
;set 5 ms flag for
cpi tock,200 breq onesec
;is one second up? ;yes, add one to
nop
;balance interrupt
rjmp nosecond inc second
;no, escape ;add one to
clr ldi out out
;clear 5 ms counter ;reload timer
register 'tock' counter counter delay display time
seconds time onesec: seconds nosecond:
tock timer,176 TCNT0,timer SREG,status
;restore status
register reti
;return to main
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due http://avr-asm.tripod.com/mux242.html (1 of 2)1/20/2009 9:12:40 PM
16 BIT MATH (AVR 202)
to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/mux242.html (2 of 2)1/20/2009 9:12:40 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AT/PS2 KEYBOARD PROGRAM HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
; *************************************************************************** ; ; File Name :"PS2Drv.asm" ; Title :PS/2 target communication protocoll ; Date :2001.10.06. ; Date (Last) :2002.12.15. ; Version :1.10 ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; - PS/2 style communication from AT keyboard or MARGOR HI01 to MAGOR CP01-1v2 ; ; CLK & DATA = H -> Two way communication ; DATA = L -> PC (MAGOR) sends to Keyb ; CLK = L -> PC (MAGOR) inhibits communiaction ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2001.10.06 VFX Creation ; 1.02 2001.12.27 VFX Modify for MAGOR CP01-1v2 ; 1.10 2002.12.15 VFX Fixed Sendig Command to keyboard, time out added ; ; ; ************************************************************************** ;* Hardware Abstraction Layer
VFX MEM
PS2_CLKPort = PORTD PS2_CLKDIR = DDRD PS2_CLKPIN = PIND KCLK = 2
.EQU .EQU .EQU .EQU
PS2_DATPort = PORTB PS2_DATDIR = DDRB PS2_DATPIN = PINB KDATA = 0
SORT 220
.EQU .EQU .EQU .EQU
CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; *************************************************************************** ;* Const Def
ISP 2313 ISP 1200
.equ
wait100us = SYSCLK/10000
;ennyi ciklus
.EQU
Kb_ScData_Lenght = 6
;Received
100us
AVR SPI I2C 300
ScanCode buffer
I2C 302 ;-------------------------------;Define commands to the keyboard. ; .equ SET_KEYBOARD_INDICATORS = 0xED .equ KEYBOARD_ECHO = 0xEE .equ SELECT_SCAN_CODE_SET = 0xF0 .equ READ_KEYBOARD_ID = 0xF2 .equ SET_KEYBOARD_TYPEMATIC = 0xF3 .equ KBD_ENABLE = 0xF4 .equ KBD_DISABLE = 0xF5 .equ SET_ALL_TYPEMATIC_MAKE_BREAK = 0xFA .equ KEYBOARD_RESET = 0xFF
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B
;--------------------------------; Define the keyboard responses. ; .equ ACKNOWLEDGE = 0xFA .equ RESEND = 0xFE .equ KEYBOARD_COMPLETE_SUCCESS .equ KEYBOARD_COMPLETE_FAILURE .equ KEYBOARD_BREAK_CODE = 0xF0 .equ KEYBOARD_DEBUG_HOTKEY_ENH
ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
= 0xAA = 0xFC
;BAT complete
= 0x37
;SysReq scan
= 0x54
;SysReq scan
code for Enhanced Keyboard .equ KEYBOARD_DEBUG_HOTKEY_AT code for 84-key Keyboard
MUX 242 KBD PS2 KBD PC/128 PS2 EMU
.equ
ST_Success
= 0x80
;a parancs
.equ
ST_Unsuccess
= 0x81
;a parancs
.equ
ST_ResendError
= 0x82
;3-szor probltuk
sikeres volt sikertelen
BOOT MG8 BOOT DR8 ALM CLK
kuldeni a keyboard fele, de nem ment .equ
ST_ACKnotreseived=0x83
;ACK-t vartunk
de nem az jott...
CLOCK 8564 90 DAYS DELAYS CALL ID
; *************************************************************************** ;**** VARIABLES .DSEG
DTMF 314 PWM 6CH
PtrINT0:
.BYTE 2
;INT0 Keyboard interrupt
aktualis cime ;int0 eseten ide ugrik
PWM 10K Kb_BitCounter:
ENCODE STH-11
;hany bitet olvasott
ResevedBits: .byte 1 ;received Kb_bits Kb_Paritas: .byte 1 ;Vett paritas bit
ATMEL CORP AVR BUTTERFLY AVR BOOK
.BYTE 1
eddig be
Kb_ScHead:
.byte 1
;Dekodolatlan Scankod buffer
Kb_ScTail: Kb_ScData:
.byte 1 .byte Kb_ScData_Lenght
Head mutato
kb_SendByte:
.byte 1
;send this data to
keyboard kb_ComStat: .byte 1
;=0 szabadon megallithato a
komunikacio
kb_lastAction:
;=1 komunikacio megallitasa tilos ;=3 kuldes folyamatban .byte 1 ;utolso muvelet mi volt ;=255 normal mukodes ;=0,1,2,3,4,5 command/parameter
kb_CmdBuffer:
.byte 3
kuldes volt ACK-ot varunk vissza ;1 CMD + 3 data bytenak
van hely kb_ResendCnt: .byte 1 elkuldeni, ha tobb mint 3 akkor error kb_Status: .byte 2 jumptabla: .byte 2 kb_SWStatus:
.byte 1
;hanyszor probaltuk
;keyboard status ; [7:6] = 00 Standard PS/2
keyboard ; = 01 MAGOR HI-01 keyboard ; = 1x future ; [5:0] = CAPS,NUM, SCROLL lock & future LEDs ; *************************************************************************** .ESEG
; *************************************************************************** .CSEG ; *************************************************************************** ; PS/2 Billentyuzet inicializalasa ; Init_PS2: CBI PS2_CLKPort,KCLK CBI PS2_CLKDIR,KCLK stated external pull-up res!! CBI PS2_DATPort,KDATA CBI PS2_DATDIR,KDATA stated external pull-up res!!
;CLK pin tre-
;DATA pin tre-
ldi
R16,Low(Kb_Rec_Start)
;Most csak adat
sts ldi sts
PtrINT0+0,R16 R16,High(Kb_Rec_Start) PtrINT0+1,R16
clr sts
R16 Kb_ScHead,R16
;ScanCode
sts sts sts sts sts ldi sts
Kb_ScTail,R16 kb_ComStat,R16 kb_ResendCnt,R16 kb_Status,R16 kb_SWStatus,R16 R16,255 kb_lastAction,R16
;normal mukodes
ldi
R16,11
;1 start +8 adat
sts
Kb_BitCounter,R16
ldi ldi sts sts
ZL,low(NormalUzem) ZH,high(NormalUzem) jumptabla+0,ZL jumptabla+1,ZH
in cbr
R16,MCUCR R16,0b00000011
;mask for 1,0
sbr
R16,0b00000010
;set for falling
OUT
MCUCR,R16
;1:0 = Inerrupt
vetele van!
Pointer Head = 0
+1 par +1 stop
bits edge Sense Control for INT0 ; 00 -> Low Level INT0 ; 01 -> Reserved ; 10 -> Falling Edge INT0 ; 11 -> Rising Edge INT0 ldi
R16,64
;INT0,1 IRQ flag
out
GIFR,R16
in ori OUT
R16,GIMSK R16,64 GIMSK,R16
;INT0 enabled ;6. = 1 EXT INT0
ldi
R16,250
;varunk 2500ms-
sts
SWTmr0,R16
;ha kozben
lds tst breq
R16,SWTmr0 R16 WTCTO
;ha innen ugrik,
sleep nop rcall brcs
Get_ScanC WTC0
rcall rcall brcs cpi brne
kb_CMD_Reset WaitToComplete KeybErr R16,KEYBOARD_COMPLETE_SUCCESS KeybErr
rcall rcall brcs
kb_CMD_ReadID WaitToComplete KeybErr
ldi cpi brne cpi
R18,64 R16,0xDE nonPS2 R17,0xD0
;0x83AB
breq
storeType
;0x9EAB -
torlese
ACTIVE
ig, hogy a power-up reset befejezodjon megjon az 0xAA, akkor jo. WTC0:
szinte biztos hogy hiba lesz
WTCTO:
nem tudom mi lehet minden billentyu vel ter vissza ;0xDED0 csak MAGOR HI-01 lehet nonPS2:
ldi
R18,04
;
Itt csak szabvany billentyu lehet storeType: sts
kb_SWStatus,R18
rcall rcall brcs cpi brne
kb_CMD_ALLMakeBrake WaitToComplete KeybErr R16,ST_Success KeybErr
ldi
R17,0
rcall rcall brcs cpi brne
kb_CMD_SetSpeed WaitToComplete KeybErr R16,ST_Success KeybErr
ldi rcall
R17,0 kb_CMD_SetLEDs
rcall brcs cpi brne
WaitToComplete KeybErr R16,ST_Success KeybErr
ldi ldi lds andi
R16,low(ps2stszov*2) R17,high(ps2stszov*2) R18,kb_SWStatus R18,0b11000000
breq ldi ldi rjmp
kszoveg R16,low(magorszov*2) R17,high(magorszov*2) kszoveg
ldi ldi rcall ret
R16,Low(kbTimeOutErr*2) R17,High(kbTimeOutErr*2) SendMSG
;
keyboard tipus eltarolva, majd kesobb kell meg
;30char/
s, 250ms rep. time
;LEDek
kikapcsolva
;csak a
bill tipusa kell
KeybErr:
kszoveg:
;************************************************ ;* WaitToComplete ;* kivarja egy billentyuparancs vegrehajtasat vagy time-out ;* R17:R16 ststus kod (redszerint csak az R16 kell) ; c=1 error WaitToComplete: ldi R16,40 ;ha 400ms-ig nincs valasz hiba @100Hz rendszermegwszakitas mellett sts SWTmr0,R16 WTC1: lds R16,SWTmr0 tst R16 breq WTCTimeOut lds R16,kb_Status+0 cpi R16,0x33 breq WTC1 ldi R17,kb_Status+1 clc ret WTCTimeOut: sec ret
; ****************************************************************************** ;* INERRUPT: R E C E I V E ;* ;* External generated clock & data - host changes the Data line only when ;* the Clock line is low, and data is latched on the falling edge of the clock pulse ;* Host may abort transmission at time before the 11th clock pulse (acknowledge bit) ;* by holding Clock low for at least 100 microseconds. ;* ;* EXT_INT0: push ZL push ZH in ZL,SREG ; preserve main OS status reg. push ZL push R16 push R2 in bst
R2,PS2_DATPIN R2,KDATA
lds lds icall
ZL,PtrINT0+0 ZH,PtrINT0+1
ldi
R16,64
;INT0
out
GIFR,R16
;lehet,
pop pop pop out
R2 R16 ZL SREG,ZL
;
pop pop reti
ZH ZL
;T-ben a
vett bit
;Int0
vegrehajto rutin meghivasa IRQ flag torlese hogy ez nem kell majd!!!!
restore previous status reg
;***************************************** ; Receive 11 keyboard bit ; Kb_Rec_Start: lds R16,Kb_BitCounter dec R16 sts Kb_BitCounter,R16 cpi R16,10 ;start bitnel tartunk breq
JaStartbit cpi R16,1 breq JaParitasJon cpi R16,0 breq JaStopJon
;Paritasbit jon? ;Stopbit jon?
;**************************************
;8
adatbit vetele ;* 8 DATA BIT Kb_Rec_Dat: lds
R16,ResevedBits
;az eddig
lsr bld
R16 R16,7
;rota 7. -> 0. ;az ujbitet a 7.
sts clr bld
ResevedBits,R16 R2 R2,0
;tarolas
lds add sts
R16,Kb_Paritas R16,R2 Kb_Paritas,R16
;uj paritas
lds
R16,Kb_BitCounter
;ha tobb mint 9
beolvasott bitek
pos-on taroljuk
;a paritas
generalashoz kell
eltarolva
bit jott eddig, ;akor mar nem lehet megallitani ;a vetelt. Be kell fejezni! cpi brsh
R16,4 kb_Rec_end1 ldi R16,1 sts kb_ComStat,R16 kb_Rec_end1:
ret
;************************************** ;* START BIT JaStartbit: clr sts
R16 Kb_Paritas,R16
;Paritas = 0,
bld
R16,0
;Received Start
tst brne ret
R16 Kb_StartErr
most meg :) bit in pos. 0
Kb_StartErr: ;ide jon az az eset, ha a start bit = 1 ,azaz hiba van!!!! ;de Vigyazat! Meg interrupt rutinban vagyuk!!!! ret ;************************************** ; PARITAS BIT JaParitasJon: bld
clr R16,0
R16 ;Paritasbit
tarolasa a 0. bitben lds
R2,Kb_Paritas
;R2 vett adat
inc
R2
;paratlan
par, R16 vett paritas bit paritas kell! eor R2,R16
;R2 = parity xor
parity bit ror
R2
;C-flagben a
brcs ret
Kb_RxParErr
parity
Kb_RxParErr:
;ide jon majd a paritas hiba lekezelese ;De figyelem, meg mindig interruptban
vagyuk!!!!!! ret
;************************************ ;* STOP BIT JaStopJon:
bld
R16,0
;itt mar R16=0,
tst breq
R16 Kb_StopErr ldi R16,11
R16=stop bit
;1 start
+8 adat +1 par +1 stop sts
Kb_BitCounter,R16
lds cpi breq
R16,kb_lastAction R16,255 NemParancsvolt
lds cpi brne
R16,ResevedBits R16,RESEND nemresend
lds inc sts cpi
R16,kb_ResendCnt R16 kb_ResendCnt,R16 R16,4
;a kovetkezo
adat vetelehez
;ha mar
haromszor probaltuk elkuldeni, de nem ment ;akkor resend error brne ldi sts
Mehettovabb R16,255 kb_lastAction,R16
ldi sts ret
R16,ST_ResendError kb_Status,R16
;vissza anormal
mukodesre
Mehettovabb: NextComdData
lds lds ijmp
ZL,jumptabla+0 ZH,jumptabla+1
nemresend:
rcall ret
NemParancsvolt: rcall
Put_ScanC
;Scankod a
R16 kb_ComStat,R16
;Stop tilalom
bufferbe clr sts feloldva! ret Kb_StopErr: ;ide jon majd a hibas stop bit lekezelese ;Meg mindig INTERRUPTBAN vagyunk!!!! clr sts
R16 kb_ComStat,R16
;Stop tilalom
feloldva! ret
;************************************************ ;* The Put_ScanC FIFO manager * ;* in: * ;* out c=1 hiba * ;************************************************ Put_ScanC: lds R16,Kb_ScHead ldi ZL,Kb_ScData_Lenght lds R2,Kb_ScTail sub R2,R16 breq PSC4 ;T=H, akkor Kb_ScData_Lenght hely van brcs clr dec cpi
PSC2 ZL add ZL ZL,1
brcs
PSCExitwError
;ha <1 nincs elg
clr ldi
R2 ZL,low(Kb_ScData)
;Pointer to the
ldi add adc
ZH,high(Kb_ScData) ZL,R16 ZH,R2
;add address
lds
R2,ResevedBits
;ez elobb vet 8
st
Z,R2
;eltarolva a
inc cpi brcs clr
R16 R16,Kb_ScData_Lenght PSC3 R16
PSC2: PSC4:
ZL,R2 ;ZL = hely a
bufferben hely! Hiba!
buffer (FIFO)
offset.. kb_data bit scankod bufferben ;Pointer>Len ;ha igen
Pointer=0, atfordult PSC3: ScanCexit:
sts
Kb_ScHead,R16
clc ret
; Nincs hiba
PSCExitwError:
;ide jon az, ha a scankod bufferben
nincs hely! ;de mi van ha nincs hely, es meg mindig megszakitasban vagyunk!! sec ret
;Hiba!!
;************************************** ; FIFO Manager folytatasa ; mar nem interruptbol megy!!!! ; Out: c=0, R0 = scankod ; Get_ScanC: clr R0 lds R18,Kb_ScTail lds R19,Kb_ScHead cp R19,R18 breq ScanErrExit
;nincs adat a
bufferben ldi
ZL,low(Kb_ScData)
;Pointer to the
ldi add adc
ZH,high(Kb_ScData) ZL,R18 ZH,R0
;add address
ld inc cpi brlo clr
R0,Z R18 R18,Kb_ScData_Lenght ScanCbx R18
;Circle around
sts clc ret
Kb_ScTail,R18
rxbuffer (FIFO)
offset...
to the first buffer pos. ScanCbx:
;Valid Char
ScanErrExit:
sec
;no char
in buff, or error ret
;*************************************************** ;* Send data to keyboard ;* start bit sending ; Kb_StartSend: lds R16,Kb_BitCounter dec R16 sts Kb_BitCounter,R16 cpi R16,2 breq SendParitas cpi R16,1 breq SendStopbit cpi R16,0 breq GetAckBit
lds lds ror sts brcs CBI
R16,kb_SendByte R2,Kb_Paritas R16 kb_SendByte,R16 send1bit PS2_DATPort,KDATA
inc rjmp
R2 kb_sendbitx
SBI
PS2_DATPort,KDATA
;send
bit 0
send1bit: ;send
bit 1 kb_sendbitx:
;
uj adatbit a porton sts
Kb_Paritas,R2
;uj
paritas eltarolasa ret
;************************************** ;* Paritas bit kuldese SendParitas: lds R16,Kb_Paritas ror R16 brcc send1paritas CBI PS2_DATPort,KDATA
;send
ret send1paritas: SBI
;paritas
bit 0
PS2_DATPort,KDATA
bit = 1 ret
;*************************************** ;* Stop bit kuldese ; SendStopbit: CBI PS2_DATPort,KDATA CBI PS2_DATDIR,KDATA
;DATA pin tre-
stated external pull-up!! ret
;************************************** ;* Get Ack bit from keyboard ; GetAckBit: ldi R16,11
;1 start
+8 adat +1 par +1 stop sts
Kb_BitCounter,R16
;a kovetkezo
ldi
R16,Low(Kb_Rec_Start)
;Vissza allunk
sts ldi sts
PtrINT0+0,R16 R16,High(Kb_Rec_Start) PtrINT0+1,R16
adat vetelehez
adat vetelre
bld R16,0 ;R16=ack bit tst R16 brne Kb_SendAckErr ret Kb_SendAckErr: ;ide jon az az eset amikor nem kuldott ack-ot ;es amost mit kezdjek vele, kuldjem ujra az egeszet??? ret
;*************************************************** ;** Parancskuldes kezdemenyezese a keyboard fele ;** In : R0 data to keyboard ;** Out: c=0 sikeres kuldes meginidtasa ;** c=1 sikertelen kuldes TrySendCmd: lds
R2,kb_ComStat
;Stop tilalom
van-e? tst breq sec NormalUzem: ret
R2 TrySend
TrySend: sts sts sts sts sts
jumptabla+0,ZL jumptabla+1,ZH kb_CmdBuffer+0,R16 kb_CmdBuffer+1,R17 kb_CmdBuffer+2,R18
ldi sts clr sts
R16,0x33 kb_Status,R16 R16 kb_lastAction,R16
clr sts
R16 kb_ResendCnt,R16
NextComdData: clr lds
R16 R2,kb_lastAction
;0. byte kuldese
lesz NewParam:
;a kovetkezo
byte kuldese ldi ldi add adc
ZL,low(kb_CmdBuffer) ZH,high(kb_CmdBuffer) ZL,R2 ZH,R16
ld sts
R0,Z kb_SendByte,R0
in andi OUT
R16,GIMSK R16,0b10111111 GIMSK,R16
;6. = 0 EXT INT0
inactive ;hogy ne okozzunk megszakitas ;mikor leallitjuk a CLK vonalat SBI
PS2_CLKDIR,KCLK
;CLK push-pull
ldi ldi
ZL,low(wait100us/5) ZH,high(wait100us/5)
;100us idozito
sbiw brne
nop ZL,1 w100us
Low nop
konstans w100us:
nop
;[1] ;[2] ;[2] ;itt mart eszre
kellett vegye ;hogy adni akarunk ldi
R16,Low(Kb_StartSend)
;Most parancs
sts ldi sts
PtrINT0+0,R16 R16,High(Kb_StartSend) PtrINT0+1,R16
ldi sts
R16,3 kb_ComStat,R16
;Stop tilalom
ldi
R16,11
;1 start +8 adat
sts
Kb_BitCounter,R16
clr sts
R16 Kb_Paritas,R16
;paritas
SBI
PS2_DATDIR,KDATA
;DATA pin push-
nop CBI
PS2_CLKDIR,KCLK
;CLK tre-state
ldi
R16,64
;INT0 IRQ flag
out
GIFR,R16
in ori OUT
R16,GIMSK R16,64 GIMSK,R16
kuldes lesz
lesz az adas allat...
+1 par +1 stop +1 ack
szamolashoz kell
pull low
ismet
torlese
;6. = 1 EXT INT0
ujra aktive clc ret
;jump tablak ;********************** ;* Reset keyboard ;* In: R17,R18,R19 parameter ahol kell ;* Out: status ; kb_CMD_Reset: ldi R16,KEYBOARD_RESET kb_CMD_single: ldi ZL,low(Egyvalasz) ldi ZH,high(Egyvalasz) rjmp TrySendCmd
kb_CMD_ALLMakeBrake: ldi R16,SET_ALL_TYPEMATIC_MAKE_BREAK ldi ZL,low(CsakACKkell) ldi ZH,high(CsakACKkell) rjmp TrySendCmd kb_CMD_Echo: ldi ldi ldi rjmp kb_CMD_SetLEDs: andi
R16,KEYBOARD_ECHO ZL,low(StoreResult) ZH,high(StoreResult) TrySendCmd
R17,0b00111111
;csak az
also 6 bit kell -> 6 LEDek lds andi or sts ldi param1: ldi rjmp
R16,kb_SWStatus R16,0b11000000 R16,R17 kb_SWStatus,R16 R16,SET_KEYBOARD_INDICATORS ldi ZL,low(EgyParameter) ZH,high(EgyParameter) TrySendCmd
kb_CMD_SetSpeed: ldi rjmp
R16,SET_KEYBOARD_TYPEMATIC param1
kb_CMD_ReadID: ldi ldi ldi rjmp
R16,READ_KEYBOARD_ID ZL,low(ketparamjon) ZH,high(ketparamjon) TrySendCmd
; ************************************************************* ;* subrutinok a keyboard parancsok vegrehajtasahoz ; CsakACKkell: cpi R16,ACKNOWLEDGE ldi R16,ST_Success breq StoreResult ldi R16,ST_Unsuccess rjmp StoreResult
Egyvalasz:
cpi breq
R16,ACKNOWLEDGE nyugtamegjott
ldi
R16,ST_ACKnotreseived
StoreResult: ldi ldi sts sts Alaphelyzebe: ldi sts
ZL,low(NormalUzem) ZH,high(NormalUzem) jumptabla+0,ZL jumptabla+1,ZH sts kb_Status,R16 R16,255 kb_lastAction,R16
;vissza anormal
R16 kb_ComStat,R16
;Stop tilalom
mukodesre clr sts feloldva! ret nyugtamegjott: ldi ldi sts sts ret
EgyParameter: cpi breq ldi rjmp Elsonyugtaok: lds
ZL,low(StoreResult) ZH,high(StoreResult) jumptabla+0,ZL jumptabla+1,ZH
R16,ACKNOWLEDGE Elsonyugtaok R16,ST_ACKnotreseived StoreResult R16,kb_lastAction
byte kuldese inc sts ldi ldi sts sts rjmp
R16 kb_lastAction,R16 ZL,low(CsakACKkell) ZH,high(CsakACKkell) jumptabla+0,ZL jumptabla+1,ZH NewParam
ketparamjon: sts rjmp
http://avr-asm.tripod.com/kbdps2.html (1 of 2)1/20/2009 9:13:24 PM
kb_Status+1,R16 nyugtamegjott
;a kovetkezo
16 BIT MATH (AVR 202)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/kbdps2.html (2 of 2)1/20/2009 9:13:24 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AT KEYBOARD PROGRAM 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1
Below is some assembly code I wrote for the mega128 last fall. It worked but has not been tested extensively. I did a look-up table to give me a ASCII character for the corresponding keyboard scan code.
TUTORIAL #2 ; ; ; ; ;
TUTORIAL #3 MATH 200 MATH 200b MATH 201
\keyboard4a\keyboard4a.asm ; Clock frequency:
MATH 202 MATH 32X
; ; ; The purpose of this project is to: ; 1. Read a keyboard scan code using the keyboard
DIV16 XX
DIV 3216
SCL and SDA lines
SQRT16
MATH 202 DEC ASCII
COPY 102
SER EPROM
VFX SMIL
;
transmit the equivalent ASCII code for that key
;
if the key is held down it will keep
;
If it is 0xF0 then it will transmit the word
"Break" and then wait for ; ;
the next scan code 4. Only the alphabet and number keys are decoded in
this code. The Ctrl, Alt, ;
Shift, Enter, Function, etc. keys are not
;
will result in a capital letter or a "?" being
;
look at the table at the end of the code and get
decoded. Hitting one of those keys sent via the USART0. You can an idea of what I mean. ; ; This project will use code from previous projects as
DFLASH AT45 FLASH CARD
"Basic Assurance Test complete" via USART0 3. Determine if the scan code is 0xF0, if it is not
transmitting that ASCII character).
LPM 108 EPROM 100
; ;
(in other words,
AVG8 222 FFT7
2. Determine if the scan code is 0xAA in which case
it will look up and
INT ASCII HX2ASC
; it will transmit
FLOAT 128
MATH 202
3.6864MHz (via STK500 onboard
oscillator)
MATH YX
DIV 24 24
Date: 9/26/03 By: Stephen L. Nuttall Hardware platform; STK500/STK501 Software platform: Atmel Studio 4.07 File location: C:\My Documents\AVR Projects
well as code ; from keyboard5.asm, keyboard5a.asm and keyboard5b. asm.
VFX MEM
ISP 2313
; .nolist .include "m128def.inc" .list ; .def temp = R16 .def bitcntr = R17 .def keydata = R18 .def temphi = R19 .def templo = R20 .def flags = R21 .def parity = R22 ; .org 0x0000 jmp RESET
ISP 1200
.org
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; Reset Handler
0x0046
AVR SPI I2C 300 I2C 302
I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
ADC 10B ADC 400
out ldi out ser out out ldi
SPH,temp temp, low(RAMEND) SPL,temp temp ; PortB = DDRB,temp ; all outputs PORTB,temp ; PortB LED's = off temp,0b11111100 ; PortD0 and PortD1 =
inputs, all
TEA ADC 128
; Main program start temp, high(RAMEND) ; Stack pointer = top
of internal SRAM
I2C TWI26
ETHNET 8019
RESET: ldi
out com
DDRD,temp temp
; other pins = output ; temp now becomes
out
PORTD,temp
0b00000011 ; PortD0 and PortD1 have
pullups ;
enabled, remaining pins
output 0's
ADC 401 THERM 232
LCD HD44
MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP
ldi sts
templo,0x17 UBRR0H,temphi
; "sts" is used because
UBRR0L,templo
; of "out" ; UBRR0L is within reach
out of "out"
; *********************************************************************************** ; USART ; Frame format = 1 start bit, 8 data bits, no parity bit, 1 stop bit (8,N,1) ; ; Registers UCSR0B and UCSR0C are already setup for this Frame format at RESET. ; ; No programming action is required for the above registers...if any settings need ; to be changed I need to remember that UCSR0C cannot be accessed via the OUT ; instruction, use STS instead. ; ; *********************************************************************************** ; init: clr bitcntr ; initialize appropriate registers clr keydata clr parity clr flags
AVR BUTTERFLY AVR BOOK
; setup BAUD rate for
UBRR0H is not within reach
LCD44 2313 KBD 240
temphi,0x00
9600 @ 3.6864MHz
IRD 410
LCD 2313
ldi
main: call
sclhi
; make sure SCL is high to
call inc cpi breq cpi brlt breq
scllo bitcntr bitcntr,0x01 startbit bitcntr,0x0A databit paritybit
; look for SCL going low
cpi breq
bitcntr,0x0B stopbit
start off
; is this a Start bit? ; yes, go check Start bit ; is this a Data bit? ; yes, go get Data bit ; no, go get and calculate
parity ; is this a Stop bit ; yes, go check Stop bit
startbit: sbic PIND,PD1 rjmp starterr rjmp main
; Start bit = 0? ; no...go send error message ; yes..go look for data bits
databit: bclr sbic bset brbc
; pre-clear Carry flag ; SDA = 0? ; no, then set Carry flag ; now check status of Carry
0 PIND,PD1 0 0,rotate
flag for parity chk in push inc pop out rotate: ror
flags,SREG flags parity flags SREG,flags
; save ; status register ; for parity check later ; restore ; status register
keydata
; rotate contents of
Carry flag into keydata rjmp
main
; go get another bit
; ; Parity checking..... ; this routine is based on Odd Parity; meaning if there are an even number of 1's ; in the data byte the Parity bit will be 1 so that an odd number of 1's now exist, ; if there are already an odd number of 1's then the Parity bit will be 0. ; ; I will keep track of Parity by incrementing the parity register once for every 1 ; that is received on the data line. If there are an odd number of 1's the lsb of ; parity register will always be 1 ; ; Therefore, if the lsb of the parity register = 1 (odd number of 1's) then the ; Parity bit should be 0 (there were an odd number of 1's already. This condition ; can be checked by exclusive ORing those 2 bits. As long as they are opposite ; the parity checks out good. ; paritybit: in flags,PIND ; SDA = PD1 ror flags ; rotate SDA into bit 0 position andi
flags,0x01
andi
parity,0x01
; clear all but bit 0
position ; again, clear all but
bit 0 eor
flags,parity
; exclusive-or to find
out if lsb's of flags ; breq
parerr
rjmp
main
and parity the same ; report error if they are
the same
stopbit: sbis rjmp cpi
; return and get stop bit now
PIND,PD1 stoperr keydata,0xAA
; SDA = 1? ; no, go report error ; BAT message from
keyboard? brne
chkforbrkcode
; no, check for next code
of interest ldi
ZH,high(2*batmsg)
; pre-load BAT message
address ldi call rjmp
ZL,low(2*batmsg) sendmsg ; go send message init ; go look for another key
press chkforbrkcode: cpi keydata,0xF0 brne sendkeychar
; Break code (0xF0):? ; no, go send ASCII key
code ldi
ZH,high(2*brkmsg)
; yes, now pre-load
Break message address ldi call rjmp
ZL,low(2*brkmsg) sendmsg ; go send message init ; look for another keypress
starterr: ldi
ZH,high(2*sterrmsg)
ldi
ZL,low(2*sterrmsg)
; load high part of
message address in ZH ; load low part of
message address in ZL call
senderrmsg
parerr: ldi
ZH,high(2*parerrmsg); load high part of
message address in ZH ldi
ZL,low(2*parerrmsg)
; load low part of
message address in ZL call
senderrmsg
stoperr: ldi
ZH,high(2*sperrmsg)
; load high part of
message address in ZH ldi
ZL,low(2*sperrmsg)
; load low part of
message address in ZL call
senderrmsg
;********* Subroutines ************** scllo: sbic rjmp ret
PIND,PD0 scllo
; PD0(SCL) = 0? ; no...continue checking SCL ; yes...return main program
sclhi: sbis rjmp ret
PIND,PD0 sclhi
; PD0(SCL) = 1? ; no...continue checking SCL ; yes..return to main
getsda: bclr sbic bset ret
0 PIND,PD1 0
; pre-clear the Carry flag ; check state of SDA ; if SDA = 1, set Carry flag ; if SDA = 0. Carry flag is
program
already cleared ; ****************************************************************************** senderrmsg: ; the calling program will have to load ZH and ZL with the appropriate message ; address sbi
UCSR0B,TXEN0
; enable transmitter,
TXEN = 1 getmsg: lpm
R0,Z+
; retrieve character from
tst
R0
; is it the last
breq out
loop UDR0,R0
call
chkxmitend
rjmp
getmsg
program memory character? ; yes..then loop forever ; no...transmit
character ; wait for transmit to
finish
loop: cbi rjmp
; get next character
UCSR0B,TXEN0 loop
; disable transmitter ; program stops here when
error occurs, user ;
will have to reset the
STK500 and try again ; ****************************************************************************** sendmsg: ; the calling program will have to load ZH and ZL with the appropriate message ; address sbi
UCSR0B,TXEN0
; enable transmitter,
TXEN = 1 getmsg1: lpm
R0,Z+
; retrieve character from
R0
; is it the last
program memory tst character? breq out
continue UDR0,R0
call
chkxmitend
; yes..then loop forever ; no...transmit
character ; wait for transmit to
finish rjmp getmsg1 continue: cbi UCSR0B,TXEN0 ret
; get next character ; disable transmitter
; ****************************************************************************** sendkeychar: sbi
UCSR0B,TXEN0
; enable transmitter,
ldi
ZH,high(2*ascii)
ldi
ZL,low(2*ascii)
add
ZL,keydata
TXEN = 1 ; load high part of key
character address in ZH ; load low part of key
character address in ZL ; add keydata offset to
ZL register brcc
getchar
inc
ZH
; if no carry, load key
character in R0 ; if there is a carry,
increment ZH register getchar: lpm
; load appropriate key
character into R0 out
UDR0,R0
call
chkxmitend
; no...transmit
character ; wait for transmit to
finish cbi ret
UCSR0B,TXEN0
; disable transmitter
; ****************************************************************************** chkxmitend: sbis UCSR0A,UDRE0
; data register empty flag
= 1 rjmp ret
chkxmitend
; no...keep checking ; yes..continue with program
;************* MESSAGES ****************************************************** batmsg: .db
"
brkmsg: .db
"
Basic Assurance Test complete
Break
",0
",0
; ************* ERROR MESSAGES ************************************************ sterrmsg: .db "Start Bit Error",0 parerrmsg: .db "Parity Bit Error" .db 0,0 sperrmsg: .db "Stop Bit Error" .db 0,0 ; ************ KEY CHARACTERS ************************************************ ascii: ; 0x00 - 0x0F .db '?','F','?','F','F','F','F','F','?','F','F','F','F','T','`','?' ; 0x10 - 0x1F .db '?','L','L','?','L','q','1','?','?','?','z','s','a','w','2','?' ; 0x20 - 0x2F .db '?','c','x','d','e','4','3','?','?','S','v','f','t','r','5','?' ; 0x30 - 0x3F .db '?','n','b','h','g','y','6','?','?','?','m','j','u','7','8','?' ; 0x40 - 0x4F .db '?',',','k','i','o','0','9','?','?','.','/','l',';','p','-','?' ; 0x50 - 0x5F .db '?','?',''','?','[','=','?','?','C','R','E',']','?','\','?','?' ; 0x60 - 0x6F .db '?','?','?','?','?','?','B','?','?','1','?','4','7','?','?','?' ; 0x70 - 0x7F .db '0','.','2','5','6','8','E','N','F','+','3','-','*','9','S','?' ; 0x80 - 0x83 .db '?','?','?','F'
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is http://avr-asm.tripod.com/kbd128.html (1 of 2)1/20/2009 9:13:59 PM
16 BIT MATH (AVR 202)
indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/kbd128.html (2 of 2)1/20/2009 9:13:59 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
PS2 KEYBOARD EMULATOR FOR 8515 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; *********************************************************************** ;* ;* Number : **.** ;* File Name :"Main.asm" ;* Title :Keymatrix interface to AT PS/2 ;* ;* Date (Orig.) :2001.09.13. ;* Date (Last) :2001.10.14. ;* Version :1.1.0 ;* Support telephone :+36-30-9541-658 ;* Support fax :+36-30-9809-372 ;* Support E-mail :[email protected] ;* Target MCU :AT90S8515 ;* ;* DESCRIPTION ;* kezeli a kovetkezo eszkozoket: ;* - 84 key ;* - 6 LED ;* - 16,11,11x Jacksly?? ;* - PS/2 style interface to AT or MARGOR CP-01 ;* ;* AT90S8515 PLCC Pin discriptions ;* ;* ROW0 T0 (PB0) VCC ;* ROW1 T1 (PB1) (PA0) AD0 D0 ;* ROW2 AIN0 (PB2) (PA1) AD1 D1 ;* ROW3 AIN1 (PB3) (PA2) AD2 D2 ;* ROW4 SS (PB4) (PA3) AD3 D3 ;* LED3 * MOSI (PB5) (PA4) AD4 D4 ;* LED4 * MISO (PB6) (PA5) AD5 D5 ;* LED5 * SCK (PB7) (PA6) AD6 D6 ;* RESET (PA7) AD7 D7 ;* LED0 RxD (PD0) ICP ;* LED1 TxD (PD1) ALE ;* KCLK INT0 (PD2) OC1B ;* KDATA INT1 (PD3) (PC7) A15 D8 ;* LED2 (PD4) (PC6) A14 D9 ;* ROW5 OC1A (PD5) (PC5) A13 D10 ;* ROW6 WR (PD6) (PC4) A12 D11 ;* ROW7 RD (PD7) (PC3) A11 D12 ;* XTAL2 (PC2) A10 D13 ;* XTAL1 (PC1) A9 D14 ;* GND (PC0) A8 D15 ;* ;* Quarc: f=3.6864 MHz (T=0.27126 us) ;* ; *********************************************************************** .include "8515def.inc"
UART 305 UART 128 UART BUFF
;**********************!!!!!!!!!!!!!!!!!!!!!! ***************************
USB 232
;* R15 regisztert modositani tilos! ;* Atjaro az interrupt rutinok es a foprogram kozott!!!! ; 0. = 1 ismetles kell a
AVR ISP ISP 2313 ISP 1200
bill.nyomas utan, Timer lejart
AVR SPI I2C 300
;**********************!!!!!!!!!!!!!!!!!!!!!! ***************************
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
; ************************************************************************** ;* Const Def .EQU BaudRate=23 ;23 - 9600 @3.6864MHz
ETHNET 8019 TEA
.EQU
T0Freq=227
;220
@1.8432MHz/1024 = 50Hz ;184 @3.6864MHz/1024 = 50Hz ;220 @7.3728MHz/1024 = 200Hz ;227 @7.3728MHz/64 =
ADC 128 ADC 10B ADC 400
4000Hz/250us
ADC 401 ;238 @3.6864MHz/1024 = 200Hz ;250 @3.6864MHz/1024 = 600Hz
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
.EQU
ONESEC=200
;for 1s
.EQU
FlashPeriod=1000
;LEDek villogasi
periodusa ~250us egysegekben
MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;***** Hardware Abstraction Layer
PS2 EMU
.EQU DTLo_PORT = DDRA .EQU DTHi_PORT = ;2x8 bit adat port Pull-upos kell
BOOT MG8 BOOT DR8
DDRC
ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
LED3
PWM 10K
LED4
ENCODE STH-11
.EQU .EQU .EQU .EQU .EQU .EQU
Row0 = 0 Row1 = 1 Row2 = 2 Row3 = 3 Row4 = 4 LED3 = 5
;PortB kiosztasa
.EQU
LED4 = 6
;
.EQU
LED5 = 7
;
.EQU .EQU
LED345 = PORTB Row01234 = PORTB
.EQU
LED0
= 0
.EQU
LED1
= 1
;
.EQU
LED2
= 4
;
.EQU .EQU .EQU
Row5 Row6 Row7
= 5 = 6 = 7
.EQU .EQU
LED012 = PORTD Row567 = PORTD
;
LED5
ATMEL CORP AVR BUTTERFLY AVR BOOK
;PortD kiosztasa
LED0 LED1 LED2
; ****************************************************************************** ;**** VARIABLES .DSEG Flag1: .BYTE 1 ;Flagbitek ;2 = paros/paratlan szamlalo led villogtatashoz ;1:0 = scan mode 01 = scan1, 10 = scan2, 11 = scan3 CNT1L: CNT1H:
.BYTE 1 .BYTE 1
;software Timer
CNT2L: CNT2H:
.BYTE 1 .BYTE 1
;LED villogtatas
freki
KeyHead: .BYTE 1 KeyTrail:.BYTE 1
;Bill. puffer eleje ;Bill. puffer vege
WTime:
.BYTE 2
;Bill.nyomas utan a
WRep:
.BYTE 2
;Bill.nyomas utan a
varakozas ido ismetlesi ido PS2Flag: .BYTE 1
;PS2 flag csak az int.
rutin hasznalhatja ;3. = 1 Parameterre var, komunikacio kozben vagyunk ;2. = 1 Request resend ;1. = 1 Resend last data to host ;0. = 1 Send ACK PS2NextA:.BYTE 2
;PS2 program cim, ahova a
LastSend:.BYTE 1 RepChar: .BYTE 1
;PS2 Utoljara kuldott kod ;karakter sorszama amit
StatLEDs:.BYTE 2
;STAUS LEDek
kovetkezo int ugrik
ismetelni kell
allapota eg /
nem eg ;masodik byte a villogas mask byte-ja
ParamErr:.BYTE 1
;parameterre max 4ms ideig
var utana hiba
.EQU KeyBuff:
KeyBuffLen = 17 .BYTE KeyBuffLen
.EQU bill.,de csak 119 db billenyut kell kezelni Matrix: allapota
;Transmit key-buffer
KeyCount = 128
;max 128
.BYTE KeyCount
;Keys
; ************************************************************************************** .ESEG .db "MAGOR HI-01 Keyboard-matrix Controller by VFX. V1.1.0 [orig. 2001.09.16] " .db "Last Upd. [2001.10.14] Info: [email protected] Data area>>" ; ***************************************************************************** ;**** I N T E R R U P T S ;**** ; ***************************************************************************** .CSEG rjmp RESET ; Reset Handler rjmp EXT_INT0 ; IRQ0 Handler rjmp EXT_INT1 ; IRQ1 Handler rjmp TIM1_CAPT ; Timer1 Capture Handler rjmp TIM1_COMPA ; Timer1 CompareA Handler rjmp TIM1_COMPB ; Timer1 CompareB Handler rjmp TIM1_OVF ; Timer1 Overflow Handler rjmp TIM0_OVF ; Timer0 Overflow Handler rjmp SPI_INT ; SPI Transfer Complete Handler rjmp UART_RXC ; UART RX Complete Handler rjmp UART_DRE ; UDR Empty Handler rjmp UART_TXC ; UART TX Complete Handler rjmp ACI_INT ; Analog Comparator Handler
;********************* EXT_INT0: RETI EXT_INT1: RETI TIM1_CAPT: RETI ;************************ ;* Key Deleay & Rep Time ;************************ TIM1_COMPA: PUSH ZL IN ZL,SREG PUSH ZL ldd out ldd out
ZL,Y+WRep+1-RAMSTRT OCR1AH,ZL ZL,Y+WRep+0-RAMSTRT OCR1AL,ZL
;rep. timer
ldi or
ZL,1 R15,Zl
;timer
POP OUT POP RETI
ZL SREG,ZL ZL
beallitasa
lejart ismetles mehet Flag
;** TIM1_COMPB: RETI TIM1_OVF: RETI ;********************* ;* RealTime Clock Int ;********************* ;* TIM0_OVF: PUSH ZL PUSH ZH IN ZL,SREG PUSH ZL LDI OUT
ZL,T0Freq TCNT0,ZL
LDD LDD OR BREQ LDD SBIW STD STD
ZL,Y+CNT1L-RAMSTRT ZH,Y+CNT1H-RAMSTRT ZL,ZH TIM_01 ZL,Y+CNT1L-RAMSTRT ZL,1 Y+CNT1L-RAMSTRT,ZL Y+CNT1H-RAMSTRT,ZH
LDD LDD OR BREQ LDD SBIW STD STD
ZL,Y+CNT2L-RAMSTRT ZH,Y+CNT2H-RAMSTRT ZL,ZH TIM_02 ZL,Y+CNT2L-RAMSTRT ZL,1 Y+CNT2L-RAMSTRT,ZL Y+CNT2H-RAMSTRT,ZH
;Reload
Timer
TIM_01:
TIM_02: OUT POP POP RETI
POP ZL SREG,ZL ZH ZL
;******************** ;* SPI Int Handle ;******************** SPI_INT: RETI UART_RXC: RETI UART_DRE: RETI UART_TXC: RETI EPR_INT: RETI ACI_INT: RETI
; ********************************************************************** ;* Iclude files .include .include .include
"keyb.asm" "ps2.asm" "EEprom.asm"
; ********************************************************************** ;* RESET ; ********************************************************************** RESET: CLI ;GLOBAL INTERRUP DIS. clr R15 ;Flags!!!
ldi out ldi out
r16, high(RAMEND) SPH,r16 r16, low(RAMEND) SPL,r16
;setup stack
LDI
R16,0b00101010
;Sleep enable, Idle mode,
OUT
MCUCR,R16
;7. =1 SRE External SARAM
INT0, INT1 fall-edge sens. Enabled, Alternate Function ;6. =1 SRW External SRAM WaitStates Enabled ;5. = 1 Sleep Enable ;4. = 0 SLEEP => Idle Mode ; 1 SLEEP => Power Down Mode ;3:2 = Inerrupt Sense Control for INT1 ; 00 ; 01 ; 10 ; 11 ;1:0
-> Low Level INT1 -> Reserved -> Falling Edge INT1 -> Rising Edge INT1 = Inerrupt Sense
; ; ; ;
-> -> -> ->
Control for INT0 00 01 10 11
Low Level INT0 Reserved Falling Edge INT0 Rising Edge INT0
LDI OUT
R16,0b00000000 GIMSK,R16
;INT0, INT1 Disabled ;7. = 1 EXT INT1 ACTIVE ;6. = 1 EXT INT0 ACTIVE
LDI OUT
R16,0b01000010 TIMSK,R16
LDI LDI
YL,LOW(RAMSTRT) YH,HIGH(RAMSTRT) ;BAZIS 'Y' +0
;7. ;6. ;3. ;1.
= = = =
1 1 1 1
TC1 TC1 TC1 TC0
OWRF EN. * COMP MATCH EN. INP CAPTURE EN. OWRF EN. *
; ************************************************************************ ;*Prot/Keymatrix and Hardware Init ;* ldi STD
R16,255 Y+RepChar-RAMSTRT,R16
clr
R17
out out
DTLo_PORT,R17 DTLo_PORT+1,R16
;Lower 8
out out
DTHi_PORT,R17 DTHi_PORT+1,R16
;Higher 8
out out
DDRB,R16 DDRB+1,R16
;Row0..4
ldi
R17,255-(1< OC1 not connected
;
;
ismetelhetettlen karakter sorszam
data bit Input & Pull up
data bit Input & Pull up
output & H, LED3,4,5 Nem vilagit
Disconnect OC1A connected PWM
;
01 => OC1 not
;
10 => OC1 non-inv
;
11 => OC1 inverted
; Togle OC1A
PWM
; Clear OC1A ; Set OC1A ;5:4 00 => OC1 not
connected
""
connected PWM
OC1B ;
01 => OC1 not
;
10 => OC1 non-inverted
;
11 => OC1 inverted
;1:0 ; ; ;
00 01 10 11
""
""
PWM
""
LDI OUT
R17,0b00001000 TCCR1B,R17
=> PWM Disabled => 8 bit PWM => 9 bit PWM => 10 bit PWM
;7. = 0 Input Capture Noise
Canceller Disabled ;6. = 0 InputCapture ICP Falling edge ;3. = 1 Reset TC1 when copare match ;2:0 Clock ; 000 => ; 001 => ; 010 => ; 011 => ; 100 => ; 101 => ; 110 =>
select TC1 Stop Ck Ck/8 Ck/64 Ck/256 Ck/1024 External T1
Falling Edge ;
111 => External T1
rising Edge
;************************************ ;** Timer0 Init ***** ;** LDI R16,T0Freq OUT TCNT0,R16 ;megszakitas frekvenciaja LDI OUT
R16,0b00000011 TCCR0,R16
;TC0 Control Register ;2:0 Clock Select ; 000 -> Stop ; 001 -> CK ; 010 -> CK/8 ; 011 -> CK/64 ; 100 -> CK/256 ; 101 -> CK/1024 ; 110 -> External pin T0
falling edge ; 111 -> External pin T0 risinrg edge
SEI
;SET GLOBAL
INT EN.
CBI
LED012,LED0
;LEDx
CBI CBI CBI CBI CBI
LED012,LED1 LED012,LED2 LED345,LED3 LED345,LED4 LED345,LED5
ldi STD
R16,Low(ONESEC) Y+CNT1L-RAMSTRT,R16
ldi STD
R16,High(ONESEC) Y+CNT1H-RAMSTRT,R16
LDD or brne
LDD R16,Y+CNT1L-RAMSTRT R17,Y+CNT1H-RAMSTRT R16,R17 wait1
SBI
LED012,LED0
SBI SBI SBI SBI SBI
LED012,LED1 LED012,LED2 LED345,LED3 LED345,LED4 LED345,LED5
ldi
ZL,low(0)
STD ldi STD
Y+CNT2L-RAMSTRT,ZL ZH,high(0) Y+CNT2H-RAMSTRT,ZH
vilagit
;software
down counter, wait for 1s
wait1:
;LEDx nem
vilagit
;
led villogtatas kb 0.5s
; *********************************************************************** ; *********************************************************************** ;******** M A I N ******** ; ******** ******** ; *********************************************************************** WWW: ldi ZL,low(40) STD Y+CNT1L-RAMSTRT,ZL ldi ZH,high(40) STD Y+CNT1H-RAMSTRT,ZH Main: rcall
SLEEP PS2_Com
LDD LDD OR BRNE
ZL,Y+CNT2L-RAMSTRT ZH,Y+CNT2H-RAMSTRT ZL,ZH LEDkihagy
(FlashPeriod)
ldi ZL,low ;led villogtatas kb 0.5s STD Y+CNT2L-RAMSTRT,ZL ldi ZH,high(FlashPeriod) STD Y+CNT2H-RAMSTRT,ZH LDD ldi eor STD
R16,Y+Flag1-RAMSTRT R17,0b0000100 R16,R17 Y+Flag1-RAMSTRT,R16
rcall
Puts_LEDs
LDD cpi brne
R16,Y+CNT1L-RAMSTRT R16,0 Main
rcall
ScanMatrix
rcall rjmp
MakeScanC WWW
;
paros/paratlan bit valtas
LEDkihagy:
;
keymatrix beolvasasa a memoriaba
;* LEd 7 ;*
6
Puts_LEDs:
5 4 3 2 1 0 3P 2P 1P 3Z 2Z 1Z LDD andi
R16,Y+Flag1-RAMSTRT R16,4
;D0
ldi
R18,0b00000111
;
breq ldi
paros R18,0b00111000
;
= Paros/paratlan bit csak zoldek villognak
csak pirosak villognak paros:
LDD
R16,Y+StatLEDs+1-
RAMSTRT ;villogas mask = 1 villog and
R18,R16
LDD
R16,Y+StatLEDs+0-RAMSTRT
;
or com andi
R16,R18 R16 R16,0b00111111
;
mov rol rol andi mov andi or
R17,R16 R17 R17 R17,0b00010000 R18,R16 R18,0b00000011 R17,R18
;ez
in andi or out
R18,LED012 R18,0b11101100 R18,R17 LED012,R18
;
rol rol andi in andi or out
R16 R16 R16,0b11100000 R17,LED345 R17,0b00011111 R17,R16 LED345,R17
;
LED data = 1 villagit
inv. kell mert kozos anodosak a ledek
megy ki a PD portra, zold ledek
LED0,1,2 kikuldve
LED3,4,5 kikuldve ret
; *********************************************************************** ;* ;* File Name :"PS2.asm" ;* Title :PS/2 communication protocoll ;* ;* Date (Orig.) :2001.10.06. ;* Date (Last) :2001.10.12. ;* Version :1.0.10 ;* Support telephone :+36-30-9541-658 ;* Support fax :+36-30-9809-372 ;* Support E-mail :[email protected] ;* Target MCU :AT90S8515 ;* ;* DESCRIPTION ;* - PS/2 style communication to AT or MARGOR CP-01 ;* ;* CLK & DATA = H -> Two way communication ;* DATA = L -> PC (MAGOR) sends to Keyb ;* CLK = L -> PC (MAGOR) inhibits communiaction ; ************************************************************************** ;* Const Def
; *************************************************************************** ;***** Hardware Abstraction Layer .EQU .EQU
PS2_CLKPort = DDRD PS2_DATPort = DDRD
.EQU .EQU
KCLK = 2 KDATA = 3
; ****************************************************************************** ;**** VARIABLES .DSEG .EQU .EQU .EQU .EQU
NoError = RxF_Abort = TxBreak = Parity_Err=
0 2 3 4
;No Error ;Abort communication ;Abort Transmit ;Parity Error
; ****************************************************************************** .ESEG
; ****************************************************************************** .CSEG Init_PS2: CBI
CBI PS2_CLKPort,KCLK PS2_CLKPort+1,KCLK ;CLK pin tre-stated
external pull-up res!!
CBI
CBI PS2_DATPort,KDATA PS2_DATPort+1,KDATA ;DATA pin tre-
stated external pull-up res!! ldi STD STD
R16,0 Y+PS2NextA+0-RAMSTRT,R16 Y+PS2NextA+1-RAMSTRT,R16 ;nincs
STD
Y+PS2Flag-RAMSTRT,R16
aktiv komunikacio folyamatban
ret
; ****************************************************************************** ;** Communication between Host and Keyboard ;** ; ****************************************************************************** PS2_Com: sbis PS2_CLKPort-1,KCLK ret ;if clk pin low, comm. inhibit sbis PS2_DATPort-1,KDATA rjmp RxCommand ;if data pin low, HOST sends command/data
LDD
R16,Y+PS2Flag-RAMSTRT
;Request
andi breq ldi
R16,0b00000100 Ps2_C2 R16,0xFE
;RESEND
mov rcall
R1,R16 SendByte
;keres
brcs LDD
ResSendERR R16,Y+PS2Flag-RAMSTRT
;Request
andi STD ret
R16,0b11111011 Y+PS2Flag-RAMSTRT,R16
Resend?
Command
elkuldese
Resend flag torlese
Ps2_C2:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Resend last data? andi breq ldd
R16,0b00000010 Ps2_C0 R1,Y+LastSend-RAMSTRT
rcall brcs LDD
SendByte ResSendERR R16,Y+PS2Flag-RAMSTRT
;utoljara
kuldott karakter ismetleshez ;ujrakuldes ;Resend
flag torlese andi STD ResSendERR: ret
R16,0b11111101 Y+PS2Flag-RAMSTRT,R16
Ps2_C0:
LDD
;ha hiba
volt ujra kuldjuk R16,Y+PS2Flag-RAMSTRT
;
Send ACK flag active? andi breq ldi
R16,0b00000001 Ps2_C1 R16,0xFA
;Send ACK
mov rcall brcs
R1,R16 SendByte ResSendERR
;ha hiba
LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11111110
;Host Abort ;ACK flag
STD
Y+PS2Flag-RAMSTRT,R16
;
to HOST
van ujrakuldes lesz
torlove sikeresen elment komunikacio nincs ret Ps2_C1:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Parameterre var? andi breq
R16,0b00001000 Ps2_C3
;ha nem,
LDD
R16,Y+ParamErr-RAMSTRT
;parameterr
cpi
R16,20
;20*250us
brcs
Megidovan
;
LDD
R16,Y+PS2Flag-RAMSTRT
;
andi STD clr STD STD
R16,0b11110111 Y+PS2Flag-RAMSTRT,R16 R16 Y+PS2NextA+0-RAMSTRT,R16 Y+PS2NextA+1-RAMSTRT,R16 ;
STD ret
Y+ParamErr-RAMSTRT,R16
akkor hadmenjen
error counter>4ms -> igen, hiba inc R16 ido ~4..5ms idotullepes!!
Parameterre var bit torlese, nem varunk tovabb!
alapallapotba hozas! Megidovan:
Ps2_C3: LDD mov or
LDD ZL,Y+PS2NextA+0-RAMSTRT ZH,Y+PS2NextA+1-RAMSTRT R16,ZL R16,ZH ;ha nincs
breq
SendScan
komunikacio folyamatban ;akkor
kuldjunk scan kodot ijmp
;ugras a
komunikacios rutinra ;******************************************** ;** Send scan/fifo ;******************************************** SendScan: ldi ZL,Low(KeyBuff) ldi ZH,High(KeyBuff) LDD R0,Y+KeyHead-RAMSTRT LDD R16,Y+KeyTrail-RAMSTRT cp R0,R16 brne SendScn1 ret SendScn1: clr R0 add Zl,R16 adc ZH,R0 ld R1,Z inc R16 cpi R16,KeyBuffLen brcs SendScn2 clr R16 SendScn2: STD Y+KeyTrail-RAMSTRT,R16 ;uj pointer elmentve rcall brcc
SendByte NoSendErr
;nincs hiba
LDD
R16,Y+PS2Flag-RAMSTRT
;Resend
ori STD ret
R16,0b00000010 Y+PS2Flag-RAMSTRT,R16
siman elment flag beallitasa
NoSendErr:
;***************************************** ;** Send R1 to Host ;** C=1 hiba tortent R17= hibakod ;***************************************** SendByte: sbis PS2_CLKPort-1,KCLK rjmp SendByte
;wait for
clk=hi rcall rcall sbis rjmp
Delay45us Delay5us PS2_CLKPort-1,KCLK SendByte
sec std
Y+LastSend-RAMSTRT,R1
;utoljara
ldi
R17,TxBreak
;R17=
sbis
PS2_DATPort-1,KDATA
;Is Data
;wait 50us ;wait for
clk=hi
kuldott karakter Transmit break still hi? ret
;ha nem,
vissza R17 hibakod! rcall clr
Delay40us R0
rcall brcs
SendBit SendAborted
ldi mov mov clr rcall brcs dec brne
R16,8 R3,R16 R0,R1 R2 SendBit SendAborted R3 SendLoop ;paratlan paritas
mov rcall clr dec
R0,R2 SendBit R0 R0
rcall rcall rcall ldi
SendBit Delay15us Delay15us R17,NoError
;R0=0 start
bit
SendLoop:
inc R2 kell!!!!!???
;R0=255
stop bit =H
clc ret SendAborted:
ldi
R17,TxBreak
;
R17= Transmit break sec ret ;* C=1 break, C=0 normal transmit SendBit: ror R0 ;0. bit -> C brcc bit0 bit1: CBI PS2_DATPort,KDATA ; DATA pin H inc
R2
rjmp
bitn SBI
;paritas no
egyel bit0:
PS2_DATPort,KDATA
;
DATA pin L bitn: SBI rcall CBI rcall clc sbis sec
rcall Delay20us PS2_CLKPort,KCLK Delay40us PS2_CLKPort,KCLK Delay20us PS2_CLKPort-1,KCLK
;clk = L ;clk = H
;Clock=high? ;if no ->
C=1 ret
; ****************************************************************************** ;* R E C E I V E ;* ;* 80 us/bit device generated clock - host changes the Data line only when ;* the Clock line is low, and data is latched on the rising edge of the clock pulse ;* Host may abort transmission at time before the 11th clock pulse (acknowledge bit) ;* by holding Clock low for at least 100 microseconds. ;* ;* Uses:R1,R2,R17,R18 RxStream:
sbis
PS2_CLKPort-1,KCLK
;Wait for
Clock=high rjmp sbic
RxStream PS2_DATPort-1,KDATA
;Is Data
RxErr
;ha nem,
still low? rjmp akkor hiba! ;Read each bit (8 data bits, parity bit, and stop bit) as follows:
RxBitLoop:
clr clr ldi
R1 R2 R17,8
;data reg. ;parity reg. ;8 bit
rcall
RxBit
;R18-ban a
add
R2,R18
bit
http://avr-asm.tripod.com/ps2emu.html (1 of 4)1/20/2009 9:14:56 PM
16 BIT MATH (AVR 202)
ror
R18
;adatbit a
ror sbis rjmp
R1 PS2_CLKPort-1,KCLK RxAbort
;Clock=high? ;if no then
dec brne
R17 RxBitLoop
C flagben
Abort
;Read parity bit rcall
RxBit
;R18-ban a
inc
R2
;paratlan
sbis rjmp
;R2 = parity xor parity bit PS2_CLKPort-1,KCLK RxAbort
bit paritas kell!!??!!!????? eor R2,R18
;Read stop bit rcall
RxBit
;R18-ban a
bit sbis rjmp
PS2_CLKPort-1,KCLK RxAbort
sbis
PS2_DATPort-1,KDATA
;Is Data
RxErr1
;Data still
still low? rjmp equals 0? ;Output Acknowledge bit rcall
SendAckBit
;
rcall
Delay45us
;Delay 45
Acknowledge bit microseconds ;(to give host time to inhibit ;next transmission.) ldi
R17,0
;no error
ror
R2
;C-flagben
brcs ret
RxParErr
ldi
R17,Parity_Err
flag a parity ;R1 =
reseived data
RxParErr:
;Parity
Error sec ret RxAbort:
;C flag =0
ldi sec ret
R17,RxF_Abort
;Abort ;C flag =0
;*Keep clocking until Data=1 then generate an error RxErr1:
rcall RxBit PS2_DATPort-1,KDATA
sbis
;Is Data
still low? rjmp akkor hiba! until Data=1 then generate an error
RxErr1 ;ha nem, ;Data still equals 0? Keep clocking
RxErr: ret ;Read a bit RxBit: SBI rcall CBI rcall clr sbic ldi
rcall Delay20us PS2_CLKPort,KCLK Delay40us PS2_CLKPort,KCLK Delay20us R18 PS2_DATPort-1,KDATA R18,1
;clk = L ;clk = H
;R18 a
beolvasott adatbit ret ;Send the acknowledge bit SendAckBit: rcall Delay15us SBI PS2_DATPort,KDATA rcall Delay5us SBI PS2_CLKPort,KCLK rcall Delay40us CBI PS2_CLKPort,KCLK rcall Delay5us CBI PS2_DATPort,KDATA ret
;data = L ;clk = L ;clk = H ;data = H
; ****************************************************************************** ;* Delayxxus ;* ;*rcall [3] + wait [xx] +ret [4] = Delay ;* @7.3728MHz ;* 45 us [332cycl ;* 40 us [296cycl ;* 20 us [148cycl ;* 10 us [74cycl] ;* 5 us [37cycl] Delay45us: ldi R16,104 ;[1] 104*3+10 cycl rjmp DelayLoop ;[2] Delay5us: ldi R16,9 ;[1] 9*3+10 cycl rjmp DelayLoop ;[2] Delay15us: ldi R16,34 ;[1] 34*3+10 cycl rjmp DelayLoop ;[2] Delay20us: ldi R16,46 ;[1] 46*3+10 cycl rjmp DelayLoop ;[2] Delay40us: ldi R16,96 ;[1] 96*3 cycl DelayLoop: dec R16 ;[1] brne DelayLoop ;[1/2] ret ;[4]
;******************************************* ;** Host request to send... receive data ;** ;******************************************* RxCommand: LDD ZL,Y+PS2NextA+0-RAMSTRT LDD ZH,Y+PS2NextA+1-RAMSTRT mov R16,Zl or R16,ZH breq NewCommand ijmp ;ha nem uj, akkor ugras a vegrehajtasra NewCommand: rcall
RxStream
;Read data
R1, C=1 hiba, R17 hibakod brcc
RxComNoErr
LDD
R16,Y+PS2Flag-RAMSTRT
ori STD NoValidComm:
R16,0b00000100 Y+PS2Flag-RAMSTRT,R16 ret
RxComNoErr: ldi
ZL,Low(2*ComTab)
ReqResend:
;Host read
error Resend needed
;uj parancs
jott ldi
ZH,High
(2*ComTab) RxCommLoop: lpm tst
R0
;ha a tabla
breq cp breq adiw
NoValidComm R0,R1 HitComm ZL,2*(ComNex-ComTab)
;kovetkezo
rjmp
RxCommLoop
adiw
ZL,2
;pointerre
R1,R0 ZL,1
;low byte
ZH,R0 ZL,R1
;hi byte
vege es nincs parancs kihagyjuk
parancs
HitComm: mutat
lpm mov adiw lpm mov mov ijmp
;ugras a
parancs vegrehajtasara ComTab:
.dw
0xED,STATUS_IND ;Turns on/
ComNex: .dw .dw .dw .dw .dw .dw
.dw 0xEE,ECHO ;Echo 0xF0,ALT_SCAN ;Set Scan Code Set 0xF3,TYPE_RATE ;Set repeat rate 0xF4,KEN ;Enables keysacnning 0xF5,KDIS ;Disable keyscanning 0xF6,SET_DEF ;Set Default Value 0xF7,ALL_TYPE ;Set all keys -
.dw
0xF8,ALL_BREAK
;Set all keys -
.dw .dw
0xF9,ALL_MAKE 0xFA,ALL_MTB
;Set all keys - Make ;Set all keys -
.dw
0xFB,KEY_TYPE
;Set ket type -
.dw
0xFC,KEY_BREAK
;Set ket type -
.dw .dw .dw .dw .dw
0xFD,KEY_MAKE 0xFE,RESEND 0xFF,KRES 0xF2,READID 0x00
;Set ket type - Make ;Resend ;Reset Command ;Read ID Command ;ez az utolso sor!
rcall
RxStream
brcs ret
RD_Err
off LEDs
Typematic Make/Break
Typematic/Make/Break Typematic Make/Break
Read_Data:
;Read data
R1, C=1 hiba, R17 hibakod
RD_Err:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Host read error Resend needed ori STD sec ret
R16,0b00000100 Y+PS2Flag-RAMSTRT,R16
; ****************************************************************************** ;* C O M M A N D S from host ;* ; ****************************************************************************** ;*Set/reset status indicators. A '1' bit turns the indicator ON. ;* 0. Scrollock,LED0 Green ;* 1. Numlock, LED0 Red ;* 2. Capslock, LED1 Green ;* 3. LED1 Red ;* 4. LED2 Green ;* 5. LED2 Red ;* 6. =1 Flash ;* 7. =0 ;******************************************************* STATUS_IND: ldi ZL,Low(StatInd1) ldi ZH,High(StatInd1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active ori R16,0b00001001 STD Y+PS2Flag-RAMSTRT,R16 ret StatInd1: rcall Read_Data brcc SatInd2 ret SatInd2: mov R16,R1 andi R16,0b01000000 ; flash bit active? ldi R16,0b00111111 breq noflash and R16,R1 STD Y+StatLEDs+1-RAMSTRT,R16 rjmp SatInd3 noflash: and R16,R1 STD Y+StatLEDs+0-RAMSTRT,R16 SatInd3: LDD R16,Y+PS2Flag-RAMSTRT andi R16,0b11110111 ; parameter renben megjott, torolve a bit ori R16,0b00000001 ; ACK kuldes kell STD Y+PS2Flag-RAMSTRT,R16 rcall Puts_LEDs ;uj led allapot kikuldese rjmp EndBack ;******************************************************* ECHO: ldi ZL,Low(Echo1) ldi ZH,High(Echo1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH ret Echo1: ldi ;Echo valasz a parancsra mov R1,R16 rcall SendByte ;
R16,0xEE
Send rjmp
EndBack
;******************************************************* ALT_SCAN:
ldi ldi STD STD LDD
ZL,Low(Altscan1) ZH,High(Altscan1) Y+PS2NextA+0-RAMSTRT,ZL Y+PS2NextA+1-RAMSTRT,ZH R16,Y+PS2Flag-RAMSTRT
ori STD ret rcall brcc ret LDD andi
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD
Y+PS2Flag-RAMSTRT,R16
mov
R16,R1
;
andi
R16,3
;
cpi breq ldd andi
R16,0 Lekerdezes R17,Y+Flag1-RAMSTRT R17,0b11111100
;
or STD
R17,R16 Y+Flag1-RAMSTRT,R17
;uj
rjmp
EndBack
;
Make ACK & Parameter bit flag active
Altscan1:
Altscan2:
Read_Data Altscan2
parameter renben megjott, torolve a bit ACK kuldes kell
parameter byte csak az alo 2 bit kell
scan mode maskolasa
scan mode mentese
Lekerdezes: ldi ldi STD STD ret
ZL,Low(Scanlek) ZH,High(Scanlek) Y+PS2NextA+0-RAMSTRT,ZL Y+PS2NextA+1-RAMSTRT,ZH
Scanlek:
ldd andi
R16,Y+Flag1-RAMSTRT R16,0b00000011
;
inc
R16
;
mov rcall
R1,R16 SendByte
;
rjmp
EndBack
scan mode maskolasa igy lesz 1,2,3 kodtabla
Send scan tab kod
;******************************************************* TYPE_RATE: ldi ZL,Low(TYPE_RATE1) ldi ZH,High(TYPE_RATE1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active ori STD ret TYPE_RATE1: rcall brcc ret
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data TR1 ;ha
hiba volt: request to resend
;
rcall
SetWait
;
mov swap andi rcall LDD
R16,R1 R16 R16,0b00000011 SetRep R16,Y+PS2Flag-RAMSTRT
;
ori STD rjmp
R16,0b00000001 Y+PS2Flag-RAMSTRT,R16 EndBack
R1
TR1: mov R16, ;Bit 7 is unimplemented. andi R16,0b00011111
Bits 6:5 - Repeat Delay Bits 4:0 - Repeat Rate
Make ACK flag active
;******************************************************* KEN: ;Make ACK flag active
RAMSTRT
LDD
R16,Y+PS2Flag-
ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a enables code rjmp EndBack ;*******************************************************
RAMSTRT
KDIS: ;Make ACK flag active
LDD
R16,Y+PS2Flag-
ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon disables code rjmp EndBack ;******************************************************* SET_DEF:
LDD
R16,Y+PS2Flag-RAMSTRT
;
ori STD rcall
R16,0b00000001 Y+PS2Flag-RAMSTRT,R16 Scan_Init
;
rjmp
EndBack
Make ACK flag active
Default Scantable
;******************************************************* ALL_TYPE:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* ALL_BREAK:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* ALL_MAKE:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* ALL_MTB:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* KEY_TYPE: ldi ZL,Low(Ktype1) ldi ZH,High(Ktype1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active
Ktype1:
Ktype2:
ori STD ret rcall brcc ret mov
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data Ktype2 R16,R1
;
parameter byte
;ide jon az feldolgozas!! LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD rjmp
Y+PS2Flag-RAMSTRT,R16 EndBack
parameter renben megjott, torolve a bit ACK kuldes kell
;******************************************************* KEY_BREAK: ldi ZL,Low(Kbreak1) ldi ZH,High(Kbreak1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active
Kbreak1:
Kbreak2:
ori STD ret rcall brcc ret mov
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data Kbreak2 R16,R1
;
parameter byte
;ide jon a feldolgozas!! LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD rjmp
Y+PS2Flag-RAMSTRT,R16 EndBack
parameter renben megjott, torolve a bit ACK kuldes kell
;******************************************************* KEY_MAKE: ldi ZL,Low(Kmake1) ldi ZH,High(Kmake1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active
Kmake1:
Kmake2:
ori STD ret rcall brcc ret mov
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data Kmake2 R16,R1
;
parameter byte
;ide jon a feldolgozas!! LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD rjmp
Y+PS2Flag-RAMSTRT,R16 EndBack
parameter renben megjott, torolve a bit ACK kuldes kell
;******************************************************* RESEND: LDD R16,Y+PS2FlagRAMSTRT
;Resend last data! ori STD rjmp
R16,0b00000010 Y+PS2Flag-RAMSTRT,R16 EndBack
;******************************************************* ;* Keyboard RESET ;******************************************************* KRES: ldi ZL,Low(KRES1) ldi ZH,High(KRES1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK flag active ori STD ret
R16,0b00000001 Y+PS2Flag-RAMSTRT,R16
R16,0xAA
KRES1: ldi ;Basic Assurance Test Result mov R1,R16 rcall SendByte
;
Send Result of BAT rcall
Scan_Init
;Re-
ldi STD
R16,0 Y+PS2Flag-RAMSTRT,R16
;
STD
Y+StatLEDs+0-RAMSTRT,R16
;
STD
Y+StatLEDs+1-RAMSTRT,R16
;
rjmp
EndBack
init Scantable
Calears Flags LED nem villagit LED nem villog
;******************************************************* READID: ldi ZL,Low(READID1) ldi ZH,High(READID1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK flag active
READID1:
ldi
ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ret ldi ZL,Low(READID2) ldi ZH,High(READID2) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH R16,0xD0 ;Eredeti:
0xAB mov rcall
R1,R16 SendByte
;
ret ldi
R16,0xDE
;
Send Result of BAT READID2: Eredeti: 0x83 mov rcall EndBack:
R1,R16 SendByte ldi R16,0 Y+PS2NextA+0-RAMSTRT,R16 Y+PS2NextA+1-RAMSTRT,R16
STD STD ret ;******************************************************* ; ************************************************************************************** .ESEG ;************************************** ;* Scan kod tabla Scan1 & Scan2 kodokkal ;* ;Keys allapota ;7. = 1 Enabled ;6. = 1 Ismetleses mod (Typematic) ;5. = 1 Break mode (felengedeskor scan kod kell) ;4. = 1 Make mode (lenyomaskor scan kod kell) ;3. = 1 Utolso ervenyes allapot ;2:1 = > counter prellegesmentesiteshez ;0. = 1 Utolso allapot ; ; 6..4 = 1 Typematic/make/break mode ; 5..4 = 1 Make/break mode ; 4 = 1 Olny Make mode
MatrixTab:
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;0. ;1. ;2. ;3. ;4. ;5. ;6. ;7. ;8. ;9.
P L E A B % Space Bar 7 Menu Up Menu Ok
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;10. ;11. ;12. ;13. ;14. ;15. ;16. ;17. ;18. ;19.
+C +Z +Y Used 9 8 D H R I
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xB0 0xB0 0xB0 0xB0
;20. ;21. ;22. ;23. ;24. ;25. ;26. ;27. ;28. ;29.
J K O 4 Menu Menu Cancel Used +X Gyorsmenet -X
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;30. ;31. ;32. ;33. ;34. ;35. ;36. ;37. ;38. ;39.
6 5 N G M F S T Q 1
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xB0 0xB0 0xB0 0xB0 0xF0 0xF0 0xF0 0xF0
;40. ;41. ;42. ;43. ;44. ;45. ;46. ;47. ;48. ;49.
Menu Down MODE -C Used -Y -Z 3 2 X Y
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xB0
;50. ;51. ;52. ;53. ;54. ;55. ;56. ;57. ;58. ;59.
Z U V W C . End Up Arrow Home Rotate Right
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xB0
;60. ;61. ;62. ;63. ;64. ;65. ;66. ;67. ;68. ;69.
Rotate stop Rotate Left 0 S1 S2 S3 S4 S5 START
.db .db .db .db .db .db .db .db .db .db
0xB0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;70. ;71. ;72. ;73. ;74. ;75. ;76. ;77. ;78. ;79.
STOP DEL R Arrow Dn Arrow L Arrow ENTER CTRL SHIFT Backspace INS
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0
;80. ;81. ;82. ;83. ;84. ;85. ;86. ;87. ;88. ;89.
Yac-16[0] Yac-16[1] Yac-16[2] Yac-16[3] Yac-16[4] Yac-16[5] Yac-16[6] Yac-16[7] Yac-16[8] Yac-16[9]
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0
;90. ;91. ;92. ;93. ;94. ;95. ;96. ;97. ;98. ;99.
Yac-16[10] Yac-16[11] Yac-16[12] Yac-16[13] Yac-16[14] Yac-16[15] Yac-11[0] Yac-11[1] Yac-11[2] Yac-11[3]
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0
;100. ;101. ;102. ;103. ;104. ;105. ;106. ;107. ;108. ;109.
.db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db
0xB0 ;110. 0xF0 ;111. 0xB0 ;112. 0xB0 ;113. 0xB0 ;114. 0xB0 ;115. 0xB0 ;116. 0xB0 ;117. 0xB0 ;118. 0xB0 ;119. 0xB0 ;120. 0xB0 ;121. 0xB0 ;122. 0xB0 ;123. 0xF0 ;124. 0xF0 ;125. 0xF0 ;126. 0xF0 ;127. 0x01,0x0C
;10.
;20.
;30.
;40.
;50.
;60.
;70.
;80.
;90.
;100 Yac-11[4] Yac-11[5] Yac-11[6] Yac-11[7] Yac-11[8] Yac-11[9] Yac-11[10] 3 allasu kapcs1A 3 allasu kapcs1B 3 allasu kapcs2A
;110
DeleayT:
3 allasu kapcs2B Not used Yac-12[0] Yac-12[1] Yac-12[2] Yac-12[3] Yac-12[4] Yac-12[5] Yac-12[6] Yac-12[7] Yac-12[8] Yac-12[9] Yac-12[10] Yac-12[11] Not used Not used Not used Not used ;Set 500ms
rep., 10 char/s
; ************************************************************************************** .CSEG Scan_Init:
ldi ldi ldi ldi out
XL,Low(Matrix) XH,High(Matrix) ZL,Low(MatrixTab) ZH,High(MatrixTab) EEARH,ZH
;output
out
EEARL,ZL
;output
ldi rcall
R17,KeyCount EERead_seq
;get EEPROM
ST dec brne
X+,R0 R17 GetMatrix
;Scan
ldi ldi out out rcall
ZL,Low(DeleayT) ZH,High(DeleayT) EEARH,ZH EEARL,ZL EERead_seq
;get Dleay
rcall rcall
SetWait EERead_seq
;get Rep.
rcall clr STD ret
SetRep R16 Y+ParamErr-RAMSTRT,R16
address high for 8515 address low for 8515 GetMatrix: data
filter torlese
mov R16,R0
Time mov R16,R0
;********************************** ;* Beolvas a Keymatrixrol egy teljes matrixot a memoriaba ;* ScanMatrix: CBI ldi ldi
Row01234,Row0 ZL,Low(Matrix) ZH,High(Matrix)
;a
billentyu parametertabla cime
Row0w: var mig a pin fizikailag nem lesz alacsony
SBIC
Row01234-2,Row0
;
rjmp Row0w IN R0,DTLo_PORT-1
;Lower 8
HalfRow IN R0,DTHi_PORT-1
;Higher 8
bit rcall bit SBI CBI Row0u: var mig a pin fizikailag nem lesz magas
Row01234,Row0 Row01234,Row1 rcall HalfRow SBIS Row01234-2,Row0
;
rjmp Row0u
Row1w:
SBIC Row01234-2,Row1 rjmp Row1w IN R0,DTLo_PORT-1 ;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row1u:
Row2w:
Row01234,Row1 Row01234,Row2 rcall HalfRow SBIS Row01234-2,Row1 rjmp Row1u
SBIC Row01234-2,Row2 rjmp Row2w IN R0,DTLo_PORT-1 ;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row2u:
Row3w:
Row01234,Row2 Row01234,Row3 rcall HalfRow SBIS Row01234-2,Row2 rjmp Row2u
SBIC Row01234-2,Row3 rjmp Row3w IN R0,DTLo_PORT-1 ;Lower 8
bit rcall HalfRow R0,DTHi_PORT-1
IN
;Higher 8
bit SBI CBI Row3u:
Row4w:
Row01234,Row3 Row01234,Row4 rcall HalfRow SBIS Row01234-2,Row3 rjmp Row3u
SBIC Row01234-2,Row4 rjmp Row4w IN R0,DTLo_PORT-1 ;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row4u:
Row5w:
Row01234,Row4 Row567,Row5 rcall HalfRow SBIS Row01234-2,Row4 rjmp Row4u
SBIC Row567-2,Row5 rjmp Row5w IN R0,DTLo_PORT-1
;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row5u:
Row6w:
Row567,Row5 Row567,Row6 rcall HalfRow SBIS Row567-2,Row5 rjmp Row5u
SBIC Row567-2,Row6 rjmp Row6w IN R0,DTLo_PORT-1
;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row6u:
Row7w:
Row567,Row6 Row567,Row7 rcall HalfRow SBIS Row567-2,Row6 rjmp Row6u
SBIC Row567-2,Row7 rjmp Row7w IN R0,DTLo_PORT-1
;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI Row7u:
Row567,Row7 rcall HalfRow SBIS Row567-2,Row7 rjmp Row7u
ret
;filter
bufferben a beolvasott matrix
;***************************** ;xx. sor feldolgozasa HalfRow:
com
R0
;inv, ekkor
ldi
R16,8
ld
R1,Z
;R1-ban a
mov ror andi
R19,R1 R19 R19,3
;a szamlalo
cpi breq inc andi
R19,3 kc1 R19 mov R17,1
mov andi
R18,R0 R18,1
;0. bit
eor breq
R17,R18 kc2
;azonos? ;ha igen
clr
R19
;szamlalo
rol andi
ror R19 R19,7
mov
R17,R1
0 = nincs lenyomas, 1 = lenyomva
KeyCycl: bill. parameter
allapota
kc1:
;szamlalo+1 R17,R1 ;0. bit az
elozo allapot
mostani allapot
ugras torlese, ha nem azonos kc2:
szamlalot es az uj allapotbit kell
http://avr-asm.tripod.com/ps2emu.html (2 of 4)1/20/2009 9:14:56 PM
R0 ;csak a
16 BIT MATH (AVR 202)
andi
R17,0b11111000
;a
or
R19,R17
;counter es
st
Z+,R19
dec brne ret
R16 KeyCycl
parameter byte also 3 bitje nem kell uj allapot bemasolasa
;***************************************************** ;* Eloallitja a scankodokat a bill.matrix allapota alapjan ;* ;***************************************************** MakeScanC: ldi ZL,Low(2*ScanTabl) ldi ZH,High(2*ScanTabl) ; Scancode table ldi ldi
XL,Low(Matrix) XH,High(Matrix)
;a
clr ldd andi
R1 R16,Y+Flag1-RAMSTRT R16,3
;
cpi breq
R16,1 scanjo
;ha
billentyu parametertabla cime
scan mode kinyerese
1, akkor scan mode1 adiw ZL,2
;scan mode2 cpi breq
R16,2 scanjo
;ha
adiw
ZL,2
;
2, akkor scan mode2 scan mode3 scanjo:
ldi
KeyCount table cime
R20, ;Z-ben az aktualis scan
keyloop:
lpm adiw mov
ZL,1 R4,R0
;R4
lpm mov adiw
R5,R0 ZL,5
;
ld
R1,X
mov
R17,R1
low, R5 hi part
kovetkezo kod cime
;allapot
byte andi
R17,1
;
R17 0. bit az uj allapot mov ror mov ror ror andi
R18,R1 R18 R19,R18 R19 R19 R19,1
;R19 elozo
andi
R18,3
;counter
cpi
R18,3
;counter<>3
breq rjmp
kl1 nextkey eor R19,R17
allapot erteke nem tortenik semmi
kl1:
;
ket allapot azonos? brne
diffrent
;ha nem,
cpi
R17,1
;lenyomott
breq rjmp
kl2 nextkey
;ha nem,
akkor make scan/break kod allapot?
akkor nem tortenik semmi kl2:
LDD
R9,Y+RepChar-RAMSTRT
;
ismetelendo karakter sorszama cp
R20,R9
;itt
brne
nextkey
;ha nem
mov andi breq
R17,R15 R17,1 nextkey
;ismetles
ldi and
R17,0b11111110 R15,R17
;flag
mov andi
R16,R1 R16,0b01000000
;
breq
nextkey
;ha
ldi
R17,2
mov mov rjmp
R1,R5 R2,R4 mb2
mov andi mov lsl lsl lsl or ST
R18,R1 R18,0b11110111 R2,R17 R2 R2 R2 R2,R18 X,R2
mov
R16,R1
;a gomb
andi breq
R16,0b10000000 nextkey
;ha
cpi
R17,1
;ha az uj
breq
lenyom
tartunk? kimarad
meg nem kell
torolve
typematic mode? igen ugras
;ismetles
mehet
diffrent:
aktiv? kell figyelni?
inaktiv, jon a kovetkezo bit 1, akkor lenyomas
feleng:
LDD
R16,Y+RepChar-RAMSTRT
;
ismetelendo karakter sorszama cp
R20,R16
;itt
brne
Fel1
;ha nem
rcall
RepTimerStop
andi
mov R16,R1 R16,0b00100000
breq
nextkey
ldd andi
R16,Y+Flag1-RAMSTRT R16,3
;
cpi breq
R16,1 scantab1
;ha
ldi
R17,0xF0
;
mov mov mov ldi rjmp
R1,R5 R2,R17 R3,R4 R17,3 mb2
tartunk? kimarad
Fel1:
;kell break
kodot generalni?
scan mode kinyerese
1, akkor scan mode1
scantab2 & 3
scantab1:
ldi R17,0x80
;
use scantable 1 or
R4,R17
;7.
mov mov ldi rjmp
R1,R5 R2,R4 R17,2 mb2
andi
mov R16,R1 R16,0b00010000
breq
nextkey
ldi
R17,2
mov mov rcall
R1,R5 R2,R4 RepTimerStart
brne mov mov dec
tst mb3 R1,R2 R2,R3 R17 rcall
bit =1 break
lenyom:
;
kell make kodot generalni?
;
make code 0xE0xx 2 byte
mb2:
mb3:
nextkey:
R1
PutScanCodes
adiw
XL,1
;
dec
R20
;
breq rjmp ret
keyextit keyloop
kovetkezo matrix elem kovetkezo scan kod cime
keyextit:
;************************************************ ;* Put Scan code into FIFO ;* in: R17 - mennyi hely kell, R1,R2,R3 parameterek ami a pufferbe kerul ;* out C=1 hiba ;************************************************ PutScanCodes: push ZL push ZH ldd ldd sub breq
R18,Y+KeyTrail-RAMSTRT R19,Y+KeyHead-RAMSTRT R18,R19 Sntolc1
;R18=txtail ;R19=txhead
brsh
Sndjoc1
Sntolc1:
subi
R18,(-1*KeyBuffLen)
;(T-H)+32
Sndjoc1:
cp
R18,R17
;R18 hely a
brcs
SendchrExit1
;ha <1
clr ldi
R18 zl,low(KeyBuff)
;R18=0 ;Pointer to
ldi add adc
zh,high(KeyBuff) zl,R19 zh,R18
; add
st
z+,R1
;Store
inc cpi brcs
R19 R19,KeyBuffLen Snd2c
;TxHead<32
clr ldi
R19 zl,low(KeyBuff)
;TxHead=0 ;Pointer to
ldi
zh,high(KeyBuff)
breq st
dec stend z+,R2
inc cpi brcs clr ldi
R19 R19,KeyBuffLen Snd3c R19 zl,low(KeyBuff)
ldi breq
zh,high(KeyBuff) dec R17 stend
st
z+,R3
;Store 3.
inc cpi brcs clr
R19 R19,KeyBuffLen stend R19
;TxHead=0
;T=H, akkor
TXbuffSize hely van
pufferben nincs elg hely! Hiba!
the txbuffer (FIFO)
address offset...
z = @Buf[txhead]
first data
akkor jo
the txbuffer (FIFO)
Snd2c:
R17 ;Store 2.
data
;TxHead=0 ;Pointer to
the txbuffer (FIFO) Snd3c:
data
stend:
std clc
Y+KeyHead-RAMSTRT,R19 ; Nincs
hiba Addr eltarolva, kuldes folya,atban rjmp SendChrExit1:
putend sec
;
Return with error clr ldi
R18 zl,low(KeyBuff)
;R18=0 ;Pointer to
ldi add adc
zh,high(KeyBuff) zl,R19 zh,R18
; add
st
z+,R18
;Store
the txbuffer (FIFO)
address offset...
z = @Buf[txhead]
error marker (0) putend:
pop ZL
pop ret
ZH
;************************************** ;* Scan kod tabla Scan1 & Scan2 kodokkal ;* ScanTabl: .dw 0x0019,0x004d,0x004d .dw 0x0026,0x004b,0x004b .dw 0x0012,0x0024,0x0024 .dw 0x001E,0x001C,0x001C .dw 0x0030,0x0032,0x0032 .dw 0x0029,0x000E,0x000E .dw 0x0039,0x0029,0x0029
;0. ;1. ;2. ;3. ;4. ;5. ;6.
P L E A B % Space
Bar .dw .dw .dw
0x0008,0x003D,0x003D 0xE049,0xE07D,0x006F 0x0041,0x0083,0x0037
;7. 7 ;8. Menu Up ;9. Menu Ok
.dw .dw .dw .dw .dw .dw .dw .dw .dw .dw
0x004E,0x0079,0x0079 0x0049,0x007D,0x007D 0x0048,0x0075,0x0077 0x0047,0x006C,0x006C 0x000A,0x0046,0x0046 0x0009,0x003E,0x003E 0x0020,0x0023,0x0023 0x0023,0x0033,0x0033 0x0013,0x002D,0x002D 0x0017,0x0043,0x0043
;10. ;11. ;12. ;13. ;14. ;15. ;16. ;17. ;18. ;19.
+C +Z +Y Used 9 8 D H R I
.dw .dw .dw .dw .dw .dw
0x0024,0x003B,0x003B 0x0025,0x0042,0x0042 0x0018,0x0044,0x0044 0x0005,0x0025,0x0025 0x0043,0x0001,0x0047 0x0040,0x000B,0x002F
;20. ;21. ;22. ;23. ;24. ;25.
J K O 4 Menu Menu
.dw .dw .dw
0x0053,0x0071,0x0071 0x004D,0x0074,0x0074 0x0038,0x0011,0x0019
;26. Used ;27. +X ;28.
.dw
0x004B,0x006B,0x006B
;29. -X
.dw .dw .dw .dw .dw .dw .dw .dw .dw .dw
0x0007,0x0036,0x0036 0x0006,0x002E,0x002E 0x0031,0x0031,0x0031 0x0022,0x0034,0x0034 0x0032,0x003A,0x003A 0x0021,0x002B,0x002B 0x001F,0x001B,0x001B 0x0014,0x002C,0x002C 0x0010,0x0015,0x0015 0x0002,0x0016,0x0016
;30. ;31. ;32. ;33. ;34. ;35. ;36. ;37. ;38. ;39.
.dw
0xE051,0xE07A,0x006D
;40. Menu
.dw .dw .dw .dw .dw .dw .dw .dw .dw
0x000F,0x000D,0x000D 0x004A,0x007B,0x0084 0x0051,0x007A,0x007A 0x0050,0x0072,0x0072 0x004F,0x0069,0x0069 0x0004,0x0026,0x0026 0x0003,0x001E,0x001E 0x002D,0x0022,0x0022 0x0015,0x0035,0x0035
;41. ;42. ;43. ;44. ;45. ;46. ;47. ;48. ;49.
MODE -C Used -Y -Z 3 2 X Y
.dw .dw .dw .dw .dw .dw .dw .dw
0x002C,0x001A,0x001A 0x0016,0x003C,0x003C 0x002F,0x002A,0x002A 0x0011,0x001D,0x001D 0x002E,0x0021,0x0021 0x0034,0x0049,0x0049 0xE04F,0xE069,0x0065 0xE048,0xE075,0x0063
;50. ;51. ;52. ;53. ;54. ;55. ;56. ;57.
Z U V W C . End Up
.dw .dw
0xE047,0xE06C,0x006E 0x0058,0x0007,0x005E
;58. Home ;59. Rotate
.dw
0x0001,0x0076,0x0008
;60. Rotate
.dw
0x0044,0x0009,0x004F
;61. Rotate
.dw .dw .dw .dw .dw .dw .dw .dw
0x000B,0x0045,0x0045 0x000C,0x004E,0x004E 0x003B,0x0005,0x0007 0x003C,0x0006,0x000F 0x003D,0x0004,0x0017 0x003E,0x000C,0x001F 0x003F,0x0003,0x0027 0xE065,0xE010,0xE010
;62. ;63. ;64. ;65. ;66. ;67. ;68. ;69.
0 S1 S2 S3 S4 S5 START
.dw .dw .dw .dw
0xE064,0xE008,0xE008 0xE053,0xE071,0x0064 0xE04D,0xE074,0x006A 0xE050,0xE072,0x0060
;70. ;71. ;72. ;73.
STOP DEL R Arrow Dn
.dw .dw .dw .dw .dw
0xE04B,0xE06B,0x0061 0x001C,0x005A,0x005A 0x001D,0x0014,0x0011 0x002A,0x0012,0x0012 0x000E,0x0066,0x0066
;74. ;75. ;76. ;77. ;78.
L Arrow ENTER CTRL SHIFT
.dw
0xE052,0xE070,0x0067
;79. INS
.dw
0xE066,0xE018,0xE018
;80. Yac-16
.dw
0xE067,0xE020,0xE020
;81. Yac-16
.dw
0xE068,0xE028,0xE028
;82. Yac-16
.dw
0xE069,0xE030,0xE030
;83. Yac-16
.dw
0xE06A,0xE038,0xE038
;84. Yac-16
.dw
0xE06B,0xE040,0xE040
;85. Yac-16
.dw
0xE06C,0xE048,0xE048
;86. Yac-16
.dw
0xE06D,0xE050,0xE050
;87. Yac-16
.dw
0xE06E,0xE057,0xE057
;88. Yac-16
.dw
0xE06F,0xE06F,0xE06F
;89. Yac-16
.dw
0xE070,0xE013,0xE013
;90. Yac-16
.dw
0xE071,0xE019,0xE019
;91. Yac-16
.dw
0xE072,0xE039,0xE039
;92. Yac-16
.dw
0xE074,0xE053,0xE053
;93. Yac-16
.dw
0xE075,0xE05C,0xE05C
;94. Yac-16
.dw
0xE076,0xE05F,0xE05F
;95. Yac-16
.dw
0xE056,0xE061,0x0061
;96. Yac-11
.dw
0xE02C,0xE01A,0x001A
;97. Yac-11
.dw
0xE02D,0xE022,0x0022
;98. Yac-11
.dw
0xE02E,0xE021,0x0021
;99. Yac-11
.dw
0xE02F,0xE02A,0x002A
;100. Yac-11
.dw
0xE030,0xE032,0x0032
;101. Yac-11
.dw
0xE031,0xE031,0x0031
;102. Yac-11
.dw
0xE032,0xE03A,0x003A
;103. Yac-11
.dw
0xE033,0xE041,0x0041
;104. Yac-11
.dw
0xE034,0xE049,0x0049
;105. Yac-11
.dw
0xE035,0xE04A,0x004A
;106. Yac-11
.dw
0x0000,0x0000,0x0000
;107. Kapcs
.dw
0x0000,0x0000,0x0000
;108. Kapcs
.dw
0x0000,0x0000,0x0000
;109. Kapcs
.dw
0x0000,0x0000,0x0000
;110. Kapcs
.dw
0x0000,0x0000,0x0000
;111. Not
.dw
0xE03A,0xE058,0xE058
;112. Yac-12
.dw
0xE01E,0xE01C,0xE01C
;113. Yac-12
.dw
0xE01F,0xE01B,0xE01B
;114. Yac-12
.dw
0xE020,0xE023,0xE023
;115. Yac-12
.dw
0xE021,0xE02B,0xE02B
;116. Yac-12
.dw
0xE022,0xE034,0xE034
;117. Yac-12
.dw
0xE023,0xE033,0xE033
;118. Yac-12
.dw
0xE024,0xE03B,0xE03B
;119. Yac-12
.dw
0xE025,0xE042,0xE042
;120. Yac-12
.dw
0xE026,0xE04B,0xE04B
;121. Yac-12
.dw
0xE027,0xE04C,0xE04C
;122. Yac-12
.dw
0xE028,0xE052,0xE052
;123. Yac-12
.dw
0x0000,0x0000,0x0000
;124. Not
.dw
0x0000,0x0000,0x0000
;125. Not
.dw
0x0000,0x0000,0x0000
;126. Not
.dw
0x0000,0x0000,0x0000
;127. Not
;10.
;20.
Cancel
Gyorsmenet ;30. 6 5 N G M F S T Q 1
;40. Down
;50.
Arrow
Right ;60. stop Left
;70.
Arrow
Backspace ;80. [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] ;90. [10] [11] [12] [13] [14] [15] [0] [1] [2] [3] ;100 [4] [5] [6] [7] [8] [9] [10] 1A 1B 2A ;110 2B used [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] used used used used
;************** ;** Kivarasi idotablazat ;** ;** f=3.6864MHz, fc=f/256 = ;** WaitTime: .dw 0x0E10 .dw 0x1C20 .dw 0x2A30 .dw 0x3840
14400Hz => 69.44us ;250ms ;500ms ;750ms ;1000ms
;**ismetlesi ido idotablazat RepTime:
.dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw
0x01E0 0x021B 0x0258 0x0295 0x02D0 0x030A 0x034A 0x0384 0x03C0 0x043A 0x04B0 0x0529 0x05A0 0x061D 0x068A 0x0708 0x0780 0x0865 0x0960 0x0A3A 0x0B40 0x0C3A 0x0D14 0x0E10 0x0F33 0x110B 0x12C0 0x14D5 0x1680 0x1874 0x1AC9 0x1C20
;00000 ;00001 ;00010 ;00011 ;00100 ;00101 ;00110 ;00111 ;01000 ;01001 ;01010 ;01011 ;01100 ;01101 ;01110 ;01111 ;10000 ;10001 ;10010 ;10011 ;10100 ;10101 ;10110 ;10111 ;11000 ;11001 ;11010 ;11011 ;11100 ;11101 ;11110 ;11111
30.0 26.7 24.0 21.8 20.0 18.5 17.1 16.0 15.0 13.3 12.0 10.9 10.0 9.2 8.6 8.0 7.5 6.7 6.0 5.5 5.0 4.6 4.3 4.0 3.7 3.3 3.0 2.7 2.5 2.3 2.1 2.0
char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s
;************************************************ ;* Set Deleay Time ;* in: R16 Wait time selector 0..3 ;* ;************************************************ SetWait: ldi ZL,Low(2*WaitTime) ldi ZH,High(2*WaitTime) clr R0 andi R16,3 add R16,R16 add ZL,R16 adc ZH,R0 LDI OUT
R16,0b00001000 TCCR1B,R16
;Timer Stop ;7. = 0 Input
Capture Noise Canceller Disabled ;6. = 0 InputCapture ICP Falling edge ;3. = 1 Reset TC1 when copare match ;2:0 Clock ; 000 => ; 001 => ; 010 => ; 011 => ; 100 => ; 101 => ; 110 =>
select TC1 Stop Ck Ck/8 Ck/64 Ck/256 Ck/1024 External
T1 Falling Edge ;
111 => External
T1 rising Edge lpm adiw add csak 3.68MHz-re keszult mi meg 7.37MHz-en ketyegunk std lpm adc std ret
ZL,1 R0,R0
;mert a tablazat
Y+WTime+0-RAMSTRT,R0 R0,R0 Y+WTime+1-RAMSTRT,R0
;************************************************ ;* Set Repeat Time ;* in: R16 rep time selector 0..31 ;* ;************************************************ SetRep: andi R16,0b00011111 add R16,R16 ;mert word meretu adatok kellenek ldi ldi clr add adc
ZL,Low(2*RepTime) ZH,High(2*RepTime) R0 ZL,R16 ZH,R0
LDI OUT
R16,0b00001000 TCCR1B,R16
;Timer Stop ;7. = 0 Input
Capture Noise Canceller Disabled ;6. = 0 InputCapture ICP Falling edge ;3. = 1 Reset TC1 when copare match ;2:0 Clock ; 000 => ; 001 => ; 010 => ; 011 => ; 100 => ; 101 => ; 110 =>
select TC1 Stop Ck Ck/8 Ck/64 Ck/256 Ck/1024 External
T1 Falling Edge ;
111 => External
T1 rising Edge lpm adiw add csak 3.68MHz-re keszult mi meg 7.37MHz-en ketyegunk std lpm adc std ret
ZL,1 R0,R0
;mert a tablazat
Y+WRep+0-RAMSTRT,R0 R0,R0 Y+WRep+1-RAMSTRT,R0
;**************************************************** ;* Billentyu nyomas utani elso ismetles timer inditas ;* R20 - ismetlendo billentyu sorszama ;**************************************************** RepTimerStart: STD Y+RepChar-RAMSTRT,R20 ; ismetelendo karakter sorszama LDI OUT OUT OUT
R16,0b00000000 TCCR1B,R16 TCNT1H,R16 TCNT1L,R16
in andi
R16,TIFR R16,255-(1< TC1 Stop
;Timer Stop
;Counter
torlese
;
001 =>
;
010 =>
;
011 =>
;
100 =>
;
101 =>
;
110 =>
;
111 =>
Ck Ck/8 Ck/64 Ck/256 Ck/1024 External T1 Falling Edge External T1 rising Edge ret
RepTimerStop:
LDI
R16,0b00000000
;
Timer Stop OUT in andi
TCCR1B,R16 R16,TIFR R16,255-(1<
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 http://avr-asm.tripod.com/ps2emu.html (3 of 4)1/20/2009 9:14:56 PM
16 BIT MATH (AVR 202)
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/ps2emu.html (4 of 4)1/20/2009 9:14:56 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
MEGA 8 BOOTLOADER HOME RETRO_DAN ;---------------------------------------------------------------------------------------; ; Program: Bootloader_Mega8.asm ; ; Writer: Herbert Dingfelder, DL5NEG ; for contact information visit WWW.DL5NEG.DE ; ; Based on: AVR-Freaks Design Note #32 ; ; Function: Bootloader for ATmega8, works via the UART with the normal ; AVRProg PC-Software ; ; Hardware: ATmega8 with a 7.3728MHz crystal ; ; History: ; ; 13.07.2004 - Source code adapted for Mega8, assembles without errors ; ; 15.07.2004 - Used crystal is not 7.3 but 3.686 MHz -> UART setting adapted ; - Red LED on PORTB 0 is switched on within the boot section, ; tested in Hardware and works -> processor starts correctly ; within the boot section ; ; 18.07.2004 - Problem how to download the bootloader is solved: Simply use ; the AVRProg in the "mega8" mode, not in "mega8boot" mode. ; Since the Intel-Hex Format contains the address for the code ; in each line, the programmers recognizes that the code has to ; go to the bootrom part of the flash (provided that the ; ".org MY_BOOTSTART" is put at the beginning of the source
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
code) - UART communication between bootloader and host PC works (echo mode and character recognition tested and works) - Crystal changed to 7.3728MHz in an attempt to fight "flushing" problems in AVRProg (without success), UART setting adapted - AVRProg is able to read the flash correctly (tested, works) - Reading and writing to EEPROM on host commands 'D' and 'd'
; ; ; ; ;
- Flash erase did not work in the NRWR section (the last 1024 words of the flash) The original version from DesignNote #32 was for ATmega163 which does not have RWR/NRWR sections. Problem solved by implementing the wait_for_spm function that makes sure that a new SPM does only start when the previous
; ; ;
is completed. (tested, works now) - function to reenable the RWW section implemented -> loading data into the application section tested and works
AVG8 222
; ; ; ; ; ;
FFT7 COPY 102 LPM 108 EPROM 100
works.
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
one
VFX MEM SORT 220 fine CRC 236 XMODEM REC UART 304
;
(Still some problems with sync on the interface between
;
and the boot loader, messagebox "flushing" appears, fuse bits
; ;
read differently many times and software download needs to be started twice sometimes. As it is known that AVRProg is very
;
command/answer sync, this does not point towards real
AVRProg are
UART 305 UART 128
sensible
UART BUFF USB 232
bootloader problems. ; ; ;
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300
on. If ;
no ASCII(27) is received via UART within that time, the
;
If the application section is empty (all cells are $FF) e.g.
;
after uploading the bootloader itself, then software will
application starts. directly
I2C 302 I2C TWI26
wait forever ; ; ;
for a ESC via the UART to start the bootloader software (while waiting for the ESC the LED blinks) - Function pause implemented for delays in steps of 10ms
;
- Command 'E' implemented for leaving the bootloader mode and
; ;
application - With that entry end exit function the bootloader is fully
; ; ;
the downloaded application is tested and works perfectly -> Version 1.1 released - Still known problem: the above mentioned sync problem in
; ;
with AVRProg have to be identified and solved. - Only 2 Words are left in the bootloader memory. If Bugfixing
I2C/TWI 128 I2C/TWI AT8
(tested works)
DALLAS-1W DALLAS CRC
start the
ETHNET 8019 TEA
usable, starting
ADC 128 ADC 10B ADC 400
combination
ADC 401 THERM 232
needs more, ; ; ;
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
KBD PC/128 PS2 EMU
ALM CLK
DELAYS CALL ID
;
- Command 'v' for Hardware Version was not implemented ->
;
- Command ':' for tranparent command setting was not
Window. fixed implemented ; ;
By monitoring the PC/AVR interface it was found that
;
not use the defined commands r/F/N for reading the lock and
;
but uses the universal command ':' to send the programming
;
directly. Additionally the calibration byte is read by the
;
- Command 'b' is send by AVRProg1.37 but is not implemented.
;
it is fatal for the programming mode to implement 'b' to
;
To simply leave it out (returns ? for unknow command) works
AVRProg1.37 does fuse bits, instructions ':' command. It was found that return 'Y'. perfectly. ; ;
PWM 10K ENCODE STH-11
25.07.2004
- To implement all improvements found on 24.07.2004 without skipping
lots of ;
of other code made it necessary to increase the boot loader
; ; ;
(=1kByte). Code adapted. - Command ':' enlarged to map r/F/N functionality - Tested, current status: Works well in AVRProg both for flash
size to 512words
ATMEL CORP AVR BUTTERFLY
-> is now implemented in simple version, always
returning \0
DTMF 314 PWM 6CH
- Debug Session with Andy, DG9NDZ to find why AVRProg 1.37 still has problems with the bootloader, especially in the "Advanced"
CLOCK 8564 90 DAYS
24.07.2004
;
BOOT MG8 BOOT DR8
the erease counter within the EEPROM can be skipped
some
MUX 242 KBD PS2
It has to be tracked on the interface.) -> Good enough to work with temporarily, Version 1.0 released. - Startup-function implemented for 10 second wait after power-
reading and writing ;
and also in the Advance window the lock and fuse bits are
;
Only week point remaining to press "write" in advance window,
;
loose of sync between host and bootloader. No harm is done to
; ; ;
-> Version 1.2 released.
AVR BOOK display correctly. that causes a the target device.
26.07.2004
- Monitoring of interface from host reveals the root cause of the sync
problem when ;
writing the the lock and fuse bits. AVRProg1.37 uses the "new
;
which is "." + 4 data bytes. This command was not
;
fuse bits is dangerous when the device is remote (one could
;
forever), the command is now implemented simply to ignore the
;
serve the interface to the host to avoid sync problems.
; ; ;
-> Version 1.3 released
universal command" implemented. As changing the lock himself out inputs but correctly Tested and works perfectly.
07.04.2005
- The code contained the "call" command, which is not supported by
ATmega8. Obviously ;
the AVR implementation is in a way that lets the software
;
commands are now replaced by the supported "rcall" command
;
- The definition of E2END was missing in the mega8 definition
;
assembler, so it was included within this source file. Now
;
available in the include file, so it is taken out of this
; ; ;
- Intended Assembler Version is now: AVR macro assembler 2.0.28 (build 121 Jan 11 2005 10:28:51) - Configuration block implemented for easier user-defining of
; ; ;
the number of wait cycles at power on or the LED pin. - Code and Comments clean up - Version 1.4 decleared which will be used for testing on
work anyhow. All "call" now. file of the old the definition is file.
parameters like
hardware together with ; ; ;
AVRProg Version 1.40. 09.04.2005
- Goodbye-Message implemented to inform user via UART that bootloader
is left ; ; ; ; ; ; ; ; ; ; ;
when command 'E' was sent - Tests on hardware successful -> Version 2.0 released
Before or after programming a new ATmega8 with this Boot Loader the fuse bits must be set like this: The ATmega8 Fuse High bits must be programmed to configure the Boot size to 512
words ; ; ; ; ; ;
and to move the Reset Vector to word address 0xE00. (BOOTSZ1=0, BOOTSZ0=1)
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
(Settings can be checked now or later with "read").
I.e. set the check box for BOOTRST in AVR-Prog-Advanced and set the selector to 512 words, then press "write". It is important that this selected size of the bootrom fits to the .org command within this source code, otherwise the processor will not correctly start at the first line of this code after
reset.
Optional: The Lock bits can be programmed to 0xEF to protect the Boot Flash Section from unintentional changes and to allow accessing the Application Flash Section. I.e. the setting for BLB0 and BLB1 in AVR-Prog-Advance: BLB0 (sets the protection for the application section) must be set to Mode 1 (no protection) to allow full access of LPM and SPM commands within the application section. BLB1 (sets the protection for the boot loader section) can be set to Mode 2 (SPM cannot write to boot section) or can be left to Mode 1 (no protection). The Fuse bits must be programmed before programming the Lock bits.
AVRProg Commands as defined by Atmel Host Writes
Host Reads ; Data
ID
Data
; Enter Programming Mode (implemented to ignore) ; Auto Increment Address dd (fully implemented) ; Set Address 13d (fully implemented) ; Write Program Memory, Low Byte 'c' 13d (fully implemented) ; Write Program Memory, High Byte 'C' 13d (fully implemented) ; Issue Page Write 'm' 13d (fully implemented) ; Read Lock Bits dd (fully implemented) ; Read Program Memory 2*dd (fully implemented) ; Read EEPROM Memory dd (fully implemented) ; Write EEPROM Memory dd 13d (fully implemented) ; Chip Erase 'e' 13d (implemented, erases appl. area ; Write Lock Bits dd 13d (implemented to ignore) ; Read Fuse Bits dd (fully implemented) ; Read High Fuse Bits dd (fully implemented) ; Read Extended Fuse Bits dd (not implemented) ; Leave Programming Mode 13d (implemented to ignore) ; Select Device Type dd 13d (implemented to ignore) ; Read Signature Bytes 3*dd (fully implemented) ; Return Supported Device Codes 't' (implemented, returns only Mega8) ; Return Software Identifier [7] (fully implemented) ; Return Software Version dd (fully implemented) ; Return Hardware Version 'v' (fully implemented) ; Return Programmer Type dd (fully implemented) ; Set LED dd 13d (implemented to ignore) ; Clear LED dd 13d (implemented to ignore) ; Exit Bootloader 'E' {13d} (implemented 'E' is not confirmed) ; Check Block Support 2*dd (implemented to return no) ; Start Block Flash Load 13d (not implemented) ; n*dd ; Start Block EEPROM Load 13d (not implemented) ; n*dd ; Start Block Flash Read (not implemented) ; Start Block EEPROM Read (not implemented) ; Universal Command (3 data bytes) ':' 13d (implemented to ignore) ; New Universal Command (4 data bytes)'.' (implemented to ignore) ;
'P'
13d
'a' 'A'
ah al
dd dd
'r' 'R' 'd' 'D'
only) 'l' 'F' 'N' 'Q' 'L' 'T' 's' n*dd
00d
'S'
s
'V'
dd
'p' 'x' 'y'
'b'
'Y'
'B'
2*dd 'F'
'B'
2*dd 'E'
'g'
2*dd 'F'
n*dd
'g'
2*dd 'E'
n*dd
3*dd 4*dd
dd
dd
13d
;------------------------------- definition and includes -------------------------------.INCLUDE "m8def.inc"
; Include Register/Bit Definitions for
.def dummy = r18 .def pa_10ms = r19
; Use Reg. R18 for temporary stuff ; used for selecting the pause time in
.def uni_cmd1 = r20
; Universal command ':' send three
.def uni_cmd2 = r21
; are stored for futher usage in r20,
the mega8
steps of 10ms
bytes. These r21, r28 .def uni_cmd3 = r10 .equ VER_H = '2'
; bootloader software version higher
.equ VER_L = '0'
; bootloader software version lower
.equ VERH_H = '1'
; bootloader hardware version higher
.equ VERH_L = '0'
; bootloader hardware version lower
.equ DT
; Device Type = 0x76 (ATmega8)
number number
number number = 0x76
.equ SB1 = 0x07 .equ SB2 = 0x93 .equ SB3 = 0x1e
; Signature byte 1 ; Signature byte 2 ; Signature byte 3
.equ UBR = 23
; Baud rate = 19.2 kbps with
.equ ESC = 27
; Ascii 27 = Escape
fCK = 7.3728 MHz
;
.equ E2END = 1FF
; This definition is missing in the
m8def.inc file ; that came with the older Assembler. In "Assembler2" ; it is correct, so it is not required any more. .equ MY_BOOTSTART = THIRDBOOTSTART
; here we define where the bootloader starts in the
flash ;------------------------------ configuration parameters -------------------------------.equ STUP_WT_CKL
= 10
; number of waiting loops (LED flashes) at
power on ; before the main application starts automatically .equ LED_PORT .equ LED_DIR
= PORTB = DDRB
.equ LED_PIN
= 1
; Port B is used for the LED ; Direction register for LED Port is
DDRB ; LED is connected to pin 1 of
Port B
;------------------------------------- here we go --------------------------------------.org MY_BOOTSTART
; The code of this bootloader has to be
located in ; the bootloader area at the end of the flash. With ; this .org it can be loaded into the device just ; like any other software (normal ATmega8 setting). ; ------------------------------- init stackpointer ------------------------------------ldi ldi out out
R24, R25, SPL, SPH,
low(RAMEND) high(RAMEND) R24 R25
; SP = RAMEND
; ---------------------------------- init UART -----------------------------------------ldi R24, UBR out UBRRL, R24
; Baud rate = 19.2 bps
ldi R24,(1<
; Enable receiver & transmitter, 8-bit mode
-------------------------- check for action on UART ----------------------------------After power-on, the processor starts with the bootloader section. Ususally the user want the application to start automatircally. Only in special cases, a software update is required. So if no ESC (ASCII(27)) is received within the defined number of wait cycles after power-on, the application starts.
sbi LED_PORT, LED_PIN
; Switch PortB to output to drive an LED
ldi R17, STUP_WT_CKL
; Preset the number of LED-flashes (=number of
(active low) loops) ; for the waiting periode start_wait: sbi LED_PORT, LED_PIN ldi pa_10ms, 20 rcall pause
; switch off the LED
cbi LED_PORT, LED_PIN ldi pa_10ms, 20 rcall pause
; switch on the LED
; wait a moment
; wait a moment
sbis UCSRA,RXC rjmp Lwait
; check for incoming data (if RXC==1) ; if not, continue at Lwait
;--- some character was received --in R16, UDR
; fetch received character and put it
into R16 cpi R16, ESC breq bootload_start
; if the received character was ESC ; start the bootloader main loop ; LED stays switched on
(all other incomming characters ; are simply ignored) Lwait: dec R17 brne start_wait
; decrement the loop counter ; and leave loop if counter has reached
zero sbi LED_PORT, LED_PIN
; switch off the LED
rjmp FLASHEND+1
; Start the application program ; (flashend+1) =
Address 0
;------------------- here starts the real bootloader functionality ---------------------bootload_start: ; To indicate to the user that the attemt to start the bootloader functionality ; was successful, we send a message back on the UART. ldi ZL,low( 2*uart_msg) ldi ZH,high(2*uart_msg)
; load the start-address of the startup message ; into the Z-Register
str_output: lpm R16,Z+
; read one character of the
string and increment ; string pointer (the Zregister) tst R16 breq L10
; exit the character output
loop if character was '\0' rcall uartSend
; send the read character via the UART
rjmp str_output
; go to start of loop for next character
;---------------------------------- start of main loop ----------------------------------
;-------------------- wait for a character from UART other than ESC --------------------L10: rcall uartGet ; repeat (R16 = uartGet) cpi R16, ESC ; while (R16 == ESCAPE) breq L10 ;--------- Command 'E' leaves the bootloader mode and starts the application -----------cpi R16, 'E' brne L11
; if(R16=='E') 'E' = Exit bootloader
; Send goodbye-message on UART ldi ZL,low( 2*goodbye_msg) ldi ZH,high(2*goodbye_msg)
; load the start-address of the startup message ; into the Z-Register
goodbye_output: lpm R16,Z+
; read one character of the
string and increment ; string pointer (the Zregister) tst R16 breq leave_bootloader
; exit the character output loop if character
was '\0' rcall uartSend
; send the read character via the UART
rjmp goodbye_output
; go to start of loop for next character
leave_bootloader: sbi LED_PORT, LED_PIN
; switch off the LED
rjmp FLASHEND+1
; Start the application program ; (flashend+1) =
Address 0
;--------- Command 'a' is question from host for autoimcrement capability---------------; simple anser is 'Y' for yes, autoincrement is done L11: cpi R16, 'a' brne L12
; if(R16=='a') 'a' = Autoincrement?
ldi R16,'Y' rjmp L70
; Yes, autoincrement is quicker ; uartSend(R16) Send the 'Y'
and go up for next command
;--------- Command 'A' is setting the address for the next operation -------------------; two bytes (in total) for high and low address are sent from the host L12: cpi R16,'A' brne L14
; else if(R16=='A') write address
rcall uartGet mov R27,R16
; address high byte is stored in R27
rcall uartGet mov R26,R16
; address low byte is stored in R26
lsl R26 rol R27
; address=address<<1 ; convert from byte address to
rjmp L68
; uartSend('\r') send CR and go
word address
up for next command
;--------- Command 'c' is write low byte to program memory -----------------------------; the low byte is simply stored in a register, the actual writing to the flashes ; page-buffer is done later, after the high byte was received L14: cpi R16,'c' ; else if(R16=='c') write program memory, low byte brne L16 rcall uartGet
; read the byte to be written from host
mov R22,R16
; store data low byte in R22
rjmp L68
; uartSend('\r') send CR and go
up for next command
;--------- Command 'C' is write high byte to program memory ----------------------------; together with the (already received) low byte, the highbyte is writen to the flashes ; page buffer. When the page buffer is completely written, it can be transfered into ; the real flash by the "page write" command. ; ; If only SPMEN is written, the following SPM instruction will store the value in R1:R0 ; in the temporary page buffer addressed by the Z pointer. L16: cpi R16,'C'
; else if(R16=='C') write program
memory,high byte brne L18 rcall uartGet mov R23,R16
; read the high byte from the host ; store the data high byte in R23
movw ZL,R26
; load the Z pointer with the current
movw R0,R22
; transfer the data word (data high and
address
low byte) ; into registers R0 and R1 rcall wait_for_spm
; make sure SPM is ready to accept a
ldi R24, (1<<SPMEN) out SPMCR,R24
; set SPMEN in SPMCR ; page load (fill temporary buffer)
new task
spm
; Store program memory
adiw R26,2 rjmp L68
; address=address+2 ; uartSend('\r') send CR and go
up for next command
;-------------------------- Command 'e' is chip erase ----------------------------------; "chip erase" for the boot loader means to erase all flash pages othen than the ; boot loader sector itself L18: cpi R16,'e' brne L28
; else if(R16=='e') Chip erase
; the loop that has to be performed to clear the application section is: ; for(address=0; address < (2*MY_BOOTSTART); address += (2*PAGESIZE)) ; the "address" variable to be used are the registers R26 and R27 clr R26 clr R27
; start with address 0
rjmp L24
; continue the loop at the
check for ; "end-criteria reached" ;......... beginning of erase loop ............ L20: ; If the PGERS bit is written to one at the same time as SPMEN, the next SPM ; instruction within four clock cycles executes page erase. The page address ; is taken from the high part of the Z pointer. rcall wait_for_spm
; make sure SPM is ready to accept a
movw ZL,R26
; load the Z-pointer with the address
new task
of the ; page to be erased ldi R24, (1<
; Store program memory
subi R26,low(-2*PAGESIZE) sbci R27,high(-2*PAGESIZE)
; increment the address by the size of a page
; this is the check for end-criteria reached, i.e. has the address already ; reached the beginning of the boot-loader section L24: ldi R24,low( 2*MY_BOOTSTART) ldi R25,high(2*MY_BOOTSTART)
; load R24, R25 with the address where the boot-loader ; section starts
cp R26,R24
; do a word-compare to check if
cpc R27,R25
; smaller than the address
brlo L20
; if that is the case, go to
the address is still where the bootloader starts
the beginning of the erase loop ; ..... remember the number of flash-erases in the EEPROM ..... ldi R26,low( E2END -1) ; increment Chip Erase Counter located ldi R27,high(E2END -1) ; at address E2END-1 movw R22,R26 ; Save Chip Erase Counter Address in R22 ldi R17,1 ; read EEPROM rcall EepromTalk mov R24,R16 ; R24 = Chip Erase Counter low byte rcall EepromTalk mov R25,R16 ; R25 = Chip Erase Counter high byte adiw R24,1 ; counter ++ out EEDR,R24 ; EEDR = R24 Chip Erase Counter low byte movw R26,R22 ; R26 = Chip Erase Counter Address ldi R17,6 ; write EEPROM rcall EepromTalk out EEDR,R25 ; EEDR = R25 Chip Erase Counter high byte rcall EepromTalk ; .......................................................... rcall wait_for_spm
; make sure SPM is ready to accept a
rcall enable_rww
; reenable the RWW section so it can be
new task
accessed again rjmp L68
; uartSend('\r') send CR and go
up for next command ;---------------------------- Command 'm' is write page --------------------------------; To execute page write, set up the address in the Z pointer, write 'X0000101' to SPMCR ; and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 ; is ignored. The page address must be written to PCPAGE. Other bits in the Z pointer will ; be ignored during this operation. L28: cpi R16,'m' ; else if(R16== 'm') Write page brne L34 rcall wait_for_spm
; make sure SPM is ready to accept a
movw ZL,R26
; load Z-pointer with address
new task
ldi R24, (1<
; Store program memory
nop rcall enable_rww
; reenable the RWW section so it can be
accessed again L32: rjmp L68
; uartSend('\r') send CR and go
up for next command
;--------------------- Command 'P' is enter programming mode ---------------------------; nothing is done here, only the command is confirmed to host by sending CR L34: cpi R16,'P' ; else if(R16=='P') Enter programming mode breq L32
; uartSend('\r') Send CR to
host and go up for next command
;--------------------- Command 'L' is leave programming mode ---------------------------; nothing is done here, only the command is confirmed to host by sending CR cpi R16,'L' ; else if(R16=='L') Leave programming mode breq L32
; uartSend('\r') Send CR to
host and go up for next command
;--------------------- Command 'p' is Return programmer type ---------------------------; simply return an 'S' to indicate to host that this is a serial programmer cpi R16,'p'
; else if (R16=='p') return programmer
type brne L38 ldi R16,'S' rjmp L70
; uartSend('S') for type is serial ; uartSend(R16) and go up for
next command
;--------------------- Command 'R' is "Read one word from program memory" --------------; reads one word from the 'current' address that is stored in R26 and increments R26 L38: cpi R16,'R' ; else if(R16=='R') Read program memory brne L40 movw ZL,R26
; load Z-pointer with address of memory
to be read lpm R24,Z+
; read program memory LSB;
lpm R16,Z+
; read program memory MSB;
store LSB in R24 and Z pointer ++ store MSB in R16 and Z pointer ++ rcall uartSend
; uartSend(R16) write back MSB to host
movw R26,ZL
; increment the 'current' address += 2
mov R16,R24
; LSB stored in R16
rjmp L70
; uartSend(R16) write back the
LSB to host and go ; up for next command ;--------------------- Command 'D' is "write data to EEPROM" ---------------------------L40: cpi R16,'D' ; else if (R16=='D') Write data to EEPROM brne L41 rcall uartGet out EEDR,R16 ldi R17,6 rcall EepromTalk rjmp L68
; fetch the data to write from the UART ; EEDR = uartGet() ; write EEPROM ; uartSend('\r') Confirm the
command to host with CR
;--------- Command 'b' is question from host for block mode capability------------------; simple anser is 'N', no bootloader does not support blockmode L41: cpi R16, 'b' brne L42
; if(R16=='b') 'b' = Blockmode?
ldi R16,'N' rcall uartSend
; send 'N'
ldi R16,'N' rjmp L70
; send 'N' ; uartSend(R16) Send the 'N'
and go up for next command ;--------------------- Command 'd' is "read data from EEPROM ---------------------------L42: cpi R16,'d' ; else if (R16=='d') Read data from EEPROM brne L43 ldi R17,1 rcall EepromTalk rjmp L70
; read EEPROM ; R16 = EEPROM data ; uartSend(R16)
;-------------------------- Command ':' is universal command ---------------------------; Host sends 3 more bytes which must be used to determine the required action. AVRProg ; uses the ':' with parameters to do things that could simply be done by r/F/N. ; We have to map recognized parameters to the refering action. L43: cpi R16,':' brne L44
; else if(R16==':') Universal Command
;.............. read in the parameters ............................... rcall uartGet mov uni_cmd1, r16
; R16 = uartGet() ; store the read byte
rcall uartGet mov uni_cmd2, r16
; R16 = uartGet() ; store the read byte
rcall uartGet mov uni_cmd3, r16
; R16 = uartGet() ; store the read byte
;..................................................................... clr r16
; preset r16 with zero, if
parameters are not ; recognized, zero will be returned to host ;..................................................................... cpi uni_cmd1, 0x58 brne cmd1_not_0x58
; check if 1st paramter is 0x58
cpi uni_cmd2, 0x00 brne cmd2_not_0x00_1
; check if 2nd paramter is 0x00
; -> 58 00 is read lock bits, ldi ZL,1
; Z pointer = 0001 (->
readFuseAndLock will read lock) rcall readFuseAndLock
; go get the requested bits
cmd2_not_0x00_1: cpi uni_cmd2, 0x08 brne cmd2_not_0x08 ; -> 58 08 is read fuse high bits, ldi ZL,3
; check if 2nd paramter is 0x08
; Z pointer = 0003 (->
readFuseAndLock will read high fuse) rcall readFuseAndLock
; go get the requested bits
cmd2_not_0x08: cmd1_not_0x58: cpi uni_cmd1, 0x50 brne cmd1_not_0x50
; check if 1st paramter is 0x50
cpi uni_cmd2, 0x00 brne cmd2_not_0x00_2
; check if 2nd paramter is 0x00
; -> 50 00 is read fuse bits, clr ZL
; Z-pointer = 0000 (->
readFuseAndLock will read fuse) rcall readFuseAndLock
; go get the requested bits
cmd2_not_0x00_2: cmd1_not_0x50: rcall uartSend
; uartSend(bits) send the read lock/
fuse bits rjmp L68
; uartSend('\r') and go up for
next command
;--------------------- Command 'F' is "read fuse bits" ---------------------------------L44: cpi R16,'F' ; else if(R16=='F') Read fuse bits brne L46 clr ZL ; Z-pointer = 0000 (-> readFuseAndLock will read fuse) rjmp L50
; rcall readFuseAndLock
;--------------------- Command 'r' is "read lock bits" ---------------------------------L46: cpi R16,'r' ; else if(R16=='r') Read lock bits brne L48 ldi ZL,1 ; Z pointer = 0001 (-> readFuseAndLock will read lock) rjmp L50
; rcall readFuseAndLock
;--------------------- Command 'N' is "read fuse high bits" ----------------------------L48: cpi R16,'N' ; else if(R16=='N') Read high fuse bits brne L52 ldi ZL,3 ; Z-pointer = 0003 (-> readFuseAndLock will read high fuse)
;-------- for all previous commands F,r,N hear we rcall the readFuseAndLock -------------; function that will read the bits that are indicated by the Z-register L50: rcall readFuseAndLock rjmp L70 ; uartSend(R16)
;--------------------- Command 't' is Return supported devices code --------------------; obviously we return only the device code of the mega8 here L52: cpi R16,'t' ; else if(R16=='t') Return supported devices code brne L54 ldi R16,DT rcall uartSend clr R16
; Device Type ; uartSend(DT) send Device Type of Mega8 ; command set of AVRProg
requires the termination of ; the t-command with a \0 not with a CR as other commands rjmp L70
; uartSend(0) and go up for
next command ; ---------------- ignored commands that are not sensible for boot loader --------------; The following 4 commands only make sense for a general programmer, not for a bootloader. ; As theres commands come with an additional byte as parameter, with have to fetch that ; byte from the UART to avoid messing up the UART reading. L54:
http://avr-asm.tripod.com/mg8boot.html (1 of 2)1/20/2009 9:15:38 PM
cpi R16,'l' breq L56
; 'l' = Write Boot Loader lockbits
cpi R16,'x' breq L56
; 'x' = Set LED
16 BIT MATH (AVR 202)
cpi R16,'y' breq L56
; 'y' = Clear LED
cpi R16,'T' brne L60
; 'T' = Select device type
L56: rcall uartGet rjmp L68
; R16 = uartGet() ; uartSend('\r') and go up for
next command
;--------------------- Command 'S' is Return software identifier -----------------------L60: cpi R16,'S' ; else if(R16=='S') Return software identifier brne L62 ldi ZL,low(2*Soft_Id) ldi ZH,high(2*Soft_Id)
; load address of String into Z-Register
L61: lpm R16,Z+
; read one character of the
tst R16 breq L72
; exit the character output
string and increment string pointer
loop charcter was '\0' rcall uartSend
; send the read character via the UART
rjmp L61
; go to start of loop for next
character
;--------------------- Command 'V' is Return software Version --------------------------L62: cpi R16,'V' ; else if (R16=='V') Return Software Version brne L63 ldi R16, VER_H
; send bootloader software version
higher number rcall uartSend ldi R16, VER_L
; send bootloader software version
lower number rjmp L70
; uartSend and go up for next
command ;--------------------- Command 'v' is Return hardware Version --------------------------L63: cpi R16,'v' ; else if (R16=='v') Return hardware Version brne L64 ldi R16, VERH_H
; send bootloader software version
higher number rcall uartSend ldi R16, VERH_L
; send bootloader software version
lower number rjmp L70
; uartSend and go up for next
command
;--------------------- Command 's' is Return Signature Byte ----------------------------L64: cpi R16,'s' ; else if (R16=='s') Return Signature Byte brne L65 ldi R16,SB1 rcall uartSend
; uartSend(SB1) Signature Byte 1
ldi R16,SB2 rcall uartSend
; uartSend(SB2) Signature Byte 2
ldi R16,SB3 rjmp L70
; uartSend(SB3) Signature Byte 3 ; uartSend and go up for next
command
;--------------------- Command '.' is new universal command ----------------------------; this command will be ignored, only the inteface will be handled correctly L65: cpi R16,'.' ; else if (R16=='.') New Universal Command brne L66 ;.............. read in the 4 parameters ............................... rcall rcall rcall rcall
uartGet uartGet uartGet uartGet
; ; ; ;
R16 R16 R16 R16
= = = =
uartGet() uartGet() uartGet() uartGet()
; ...................................................................... clr R16 rcall uartSend
; uartSend(/0)
rjmp L68
; uartSend('\r') and go up for
next command
;++++++++++++++ handling the different commands is done till here +++++++++++++++++++++++ ; only general completion for all commands below
;---------------------- failed commands can end up here --------------------------------; an '?' is send via the UART to indicate fail host, then main loop starts again L66: ldi R16,'?' rjmp L70
; else uartSend('?') ; uartSend(R16)
;--------- successfully completed commands without return value can end up here --------; an CR is sent via the UART to confirm execution to host, then main loop starts again L68: ldi R16,13
; uartSend('\r')
;------------ successfully completed commands with return value can end up here --------; the return value is sent via the UART to confirm execution to host ; then main loop starts again L70: rcall uartSend ; uartSend(R16) L72: rjmp L10
; jump up to beginning of main
loop ;-------------------------- end of main loop --------------------------------------------
;================= end of main program, only subroutines from here on ===================
;------------------ reads fuse or lock bits (depending on Z-Reg.) ------------readFuseAndLock: ; An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR ; Register, will read either the Lock bits or the Fuse bits ; (depending on Z0 in the Z pointer) into the destination register. rcall wait_for_spm
; make sure SPM is ready to accept a
new task clr ZH
; Z pointer high byte = 0
ldi R24,(1<
; set BLBSET and SPMEN in SPMCR ; read fuse and lock ; read program memory
ret ;------------- does an read or write on the EEPROM (depending on R17) --------; if R17 == 6 then Write, if R17 == 1 then Read EepromTalk: out EEARL,R26 ; EEARL = address low out EEARH,R27 ; EEARH = address high adiw R26,1 ; address++ sbrc R17,1 ; skip if R17 == 1 (read Eeprom) sbi EECR,EEMWE ; EEMWE = 1 (write Eeprom) out EECR,R17 ; EECR = R17 (6 write, 1 read) L90: sbic EECR,EEWE rjmp L90 in R16,EEDR
; wait until EEWE == 0 ; R16 = EEDR
ret ;---------------- send one character via UART (parameter is r16) -------------uartSend: sbis UCSRA,UDRE ; wait for empty transmit buffer (until UDRE==1) rjmp uartSend out UDR,R16
; UDR = R16, start transmission
ret ;---------------- read one character from UART (returned in r16) -------------uartGet: sbis UCSRA,RXC rjmp uartGet in R16,UDR
; wait for incoming data (until RXC==1) ; return received data in R16
ret ;-------------------- wait for SPM to be ready for new tasks -----------------; while( SPMCR_REG & (1<<SPMEN) ) wait_for_spm: in r16, SPMCR
; read the content of SPMCR into
register andi r16, (1<<SPMEN) brne wait_for_spm
; check if bit SPMEN is set ; and do more loops if bit not yet
cleared Wait_ee: sbic EECR, EEWE
; check that no EEPROM write access is
present rjmp Wait_ee ret
; ---------------------------- re-enable the RWW section ---------------------; When programming (page erase or page write) to the RWW section, the RWW section ; is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW ; section, the user software must wait until the programming is completed (SPMEN will be ; cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the ; next SPM instruction within four clock cycles re-enables the RWW section. ; If this is not done, all addresses will read $FF even if they contain other values. enable_rww: rcall wait_for_spm
; make sure SPM is ready to accept a
new task ldi r16, (1<
; set rwwsre and spmen in SPMCR to prepare ; for reenabling the rww section
spm
; initiate the
reenabling ret ;---------------------------------- Pause ------------------------------------; Delays the CPU the selected periode, parameter pa_10ms is in 10ms steps pause: ldi dummy, 0b00000101 out TCCR0, dummy
; set prescaler to 1024
ldi dummy, 184 out TCNT0, dummy
; preset the counter for 72 remaining ; cycles till overflow
in dummy, TIFR sbr dummy, (1<
; reset the overflow flag
pw: in dummy, TIFR sbrs dummy, TOV0 rjmp pw
; check if overflow flag is set ; if not, wait more
;--- do this 10ms as often as requested in parameter pa_10ms dec pa_10ms ; decrement the counter brne pause ; and do the loop again if not zero yet ret ;-------------------------- data for identifier string ---------------------------------Soft_Id: .db "AVRB_M8", 0 ;--------------- data for message on UART when bootloader starts -----------------------uart_msg: .db .db .db .db .db .db
"+--------------------------------------------------+",10,13 "| Bootloader for ATmega8, Version ", VER_H, '.',VER_L, " by DL5NEG "| Use AVRProg to download new software. |",10,13 "| Press E to leave the bootloader and to start the |",10,13 "| application software from the flash memory. |",10,13 "+--------------------------------------------------+ ",10,13,10,13,0
|",10,13
;------------- data for message on UART when leaving the bootloader --------------------goodbye_msg: .db "Thanks for using DL5NEGs bootloader. ",10,13,10,13,0
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have ondie EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R, $FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have ondie EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/mg8boot.html (2 of 2)1/20/2009 9:15:38 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
PAGED BOOTLOADER HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; **************************************************************************** ;* Simple page-oriented boot loader for AVR parts with boot block. ;* (c) 2005 Mike Dvorsky ;* ;* Target: Any AVR with boot loader capability. ;* ;* Function: Accepts serial commands to erase, write, or read FLASH memory, ;* or to transfer control to a specified address. ;* ;* Supported commands: ;* 1. Erase page at address AAAA ;* command: "eAAAA\n" ;* response: "." ;* 2. Read page at address AAAA; response is 1 page (32 words) of data ;* command: "rAAAA\n" ;* response: "DDDD...DDDD." ;* 3. Write page at address AAAA with 1 page of data DDDD...DDDD ;* command: "wAAAA\nDDDD...DDDD\n" (\n = carriage return) ;* response: "." ;* 4. Transfer control to address AAAA. ;* command: "gAAAA\n" ;* response: none ;* ;* "AAAA" = 2-byte address in hex ;* "DDDD...DDDD" = page of data in hex = 32 words = 64 bytes = 128 hex digits ;* "\n" = carriage return = ASCII 0x0D ;* ;* Received characters are not echoed. Any line feeds (ASCII 0x0A) are ;* ignored. The command bytes MUST be lower case. The hex address and ;* data characters MUST be upper case. Any incorrect character will ;* cause the command to be terminated. ;* ;* Communication parameters = 8 data bits, 1 stop bit, no parity. Baud ;* rate is platform dependent, but will be 115.2 kBaud if that rate is ;* supported by the platform. ;* ;* At any time, the following sequence will terminate any partially ;* entered command and restore the boot loader to the state where it is ;* waiting for a new command. The sequence is ".\n" (a period character ;* followed by a carriage return). ;* ;* The order of data bytes for a page read or page write is LSB first. ;* ;* Following a page erase or page write command, the processor will be ;* unavailable for several milliseconds while the FLASH is being ;* modified. The device sending the data must account for this in one ;* of the following ways: ;* 1. Wait for receipt of the '.' character indicating the erase/write ;* command is complete. At this time the processor will be ready ;* to receive and process another command. ;* 2. Delay at least 5 milliseconds following the erase/write command ;* before starting the next command. ;* 3. Send enough "fill" bytes to ensure at least a 5 millisecond delay. ;* The fill byte must not be a valid command byte. Examples of valid ;* fill bytes are carriage return, line feed, space, '.', etc. The ;* fill bytes will be ignored, and should be terminated with a ;* carriage return. 60 fill bytes will be sufficient to ensure the ;* required delay at all Baud rates up to and including 115.2 kBaud. ;* ;* There are no restrictions on which pages can be read or written, but ;* in order to prevent accidental corruption of the boot section, it is ;* recommended that the boot lock bits be set to disallow SPM to write ;* to the boot loader section. ;* ;* In addition to the serial commands described above, the boot loader ;* makes two services available to the application: ;* 1. Jump to boot. If the application jumps to the last location in ;* FLASH, the boot loader will be started This allows the flash ;* process to be started without the need to install a jumper. ;* 2. Modify FLASH memory. If the application calls the next ;* to last location in FLASH, the boot loader will spin until any ;* previous SPM instruction completes, load the value in R16 into ;* SPMCR, and then execute an SPM instruction. (The SPM instruction ;* can only be used in the boot section, so this is the only way for ;* the application to modify FLASH memory.) ;* ;* When the SPM service is called, interrupts must be disabled and ;* there must be no EEPROM write in progress. It is the application's ;* responsibility to ensure this. Also, if the function being ;* performed is a write to the page buffer, then R0, R1, and Z must ;* be set to the appropriate values. ;* ;* Normally, after reset, the boot loader will branch to the reset vector ;* in the application section (unless it finds the reset vector erased). ;* There is a method to force the boot loader to remain in boot, which ;* varies with different platforms. Usually there will be one or more I/O ;* pins that can be jumpered or driven in a special way that indicates to ;* the boot loader that it should remain in boot and not jump to the ;* application. This is useful for recovering from a defective application. ; **************************************************************************** .include "m8def.inc"
;*
Processor-specific defines ; **************************************************************************** ;* Global constants ; **************************************************************************** .equ
BAUD_DIVISOR = 7
;* 14.7456
;.equ
BAUD_DIVISOR = 12
;* 4 MHz,
.equ
ASCII_LF = 10
;* ASCII
.equ
ASCII_CR = 13
;* ASCII
.equ .equ
PAGESIZEW = PAGESIZE PAGESIZEB = PAGESIZE*2
MHz, 115.2k 19.2k, for testing on STK200
carriage return line feed
; **************************************************************************** ;* Global register definitions ; **************************************************************************** .def .def .def .def .def .def
zeroreg imm1 imm2 imm3 counter command
= = = = = =
R2 R16 R17 R18 R19 R20
; **************************************************************************** ;* Start of code. Interrupts will be disabled for all boot loader ;* operations, so no interrupt vector table is needed. The code starts at ;* the reset vector address. ; **************************************************************************** .cseg .org SMALLBOOTSTART ;* Init a register with the value 0 clr zeroreg ; **************************************************************************** ;* Determine whether the boot loader should remain in boot or jump to the ;* application. There are two parts to this test: ;* 1. Check the first word of the application section (the reset ;* vector). If it is erased (i.e. 0xFFFF), assume there is not a ;* valid application and remain in boot. Otherwise continue with the ;* next test. ;* 2. Test the I/O pins for the presence of a jumper or other signal that ;* the code should remain in the boot loader. This is useful for ;* recovery from a run-away application. The specific I/O pins and the ;* test performed are platform specific. ;* ;* Also, before jumping to the application, it is necessary to set the vector ;* table to the application section. This can be done at any time, since the ;* boot loader does not use interrupts. ;* ;* The operations of setting the vector table and testing the first word of ;* the application are interspersed with the I/O pin test. They are used ;* to introduce delays after the pins are set up, in order to allow the ;* signals time to settle. ; **************************************************************************** ;* For the SSC-32 platform, pins PD3 and PD4 are normally left open or ;* jumpered to GND in order to select one of 4 Baud rates. If PD3 and PD4 ;* are jumpered together, this indicates to the boot loader that it should ;* remain in boot and not automatically jump to the application. ; **************************************************************************** ;* Test Baud Select pins (PD3, PD4); if jumpered together stay in boot ;* loader. ;* First, set PD4 for input w/o pullup, and PD3 for input w/pullup. out
DDRD, zeroreg
ldi
imm1, 0x08
out
PORTD, imm1
;* PORTD =
input ;*
Pullup on PD3
;************* ;* The next few instructions are placed here rather than separately, ;* in order to allow them to be used for doubleduty as delay instructions ;* to allow the input value to settle before the pin is read. ;* ;* Set vector table to app section ldi imm1, (1<
If it is erased (i.e. 0xFFFF), stay in
boot. ldi ZL, 0 ldi ZH, 0 lpm R28, Z+ lpm R29, Z adiw R28, 1 breq bootmain ;************* ;* Now the input value should have settled. Check PD3.
If the ;* PD3 value is 0, then the "stay in boot" jumper
is not ;* installed, so jump to the app.
If the PD3 value
is 1, then ;* we need to continue testing to determine whether the jumper ;* is installed. sbis PIND, PD3 rjmp $000
;* Jump to
app reset vector ;* Next, set PD4 for output with value 0. PD3.
Check
If the PD3 ;* value is 0, then the "stay in boot" jumper is
installed, so fall ;* through to boot.
If the PD3 value is 1, then
the "stay in boot" ;* jumper is not installed, so jump to the app. sbi DDRD, DDD4 ;* PD4 = output lpm
imm1, Z
;*
3 cycle delay for input to settle sbic rjmp
PIND, PD3 $000
;* Go to
the app reset vector ; **************************************************************************** ;* Bootloader main code. ; **************************************************************************** bootmain: ;* Clear zeroreg again in case of jump to boot from app clr zeroreg ;* Initialize the UART to 1 stop bit, no parity, interrupts ;* disabled, and the baud rate set by BAUD_DIVISOR. out UBRRH, zeroreg ldi imm1, low(BAUD_DIVISOR) out UBRRL, imm1 out UCSRA, zeroreg ldi imm1, (1<
UCSRC, imm1
;* Branch back to this point if an invalid command is received. wait_for_command_byte: ;* Set stack pointer to a known location in RAM. ;* NOTE: prior to this point, the stack pointer is invalid, so no ;* instructions may be used that depend on the stack (i.e. rcall, ;* ret, push, pop). ;* NOTE: the stack pointer is re-initialized at the end of every ;* command.
This allows subroutines to "bail out"
in case of error, ;* without needing to worry about fixing the stack. out SPH, zeroreg ldi imm1, 0xFF out SPL, imm1 ;* Receive and process a command byte.
Ignore any
unrecognized bytes. command_loop: rcall rx_byte cpi imm1, ASCII_CR
;* Get command ;* If carriage
return, discard breq mov rcall
wait_for_command_byte command, imm1 get_addr
;* Get address for
command ;* Check for Go command cpi command, 'g' breq go_command ;* Check for Read Page command cpi command, 'r' breq read_page ;* Check for Write Page command cpi command, 'w' breq write_page ;* Check for Erase Page command cpi command, 'e' brne command_loop ; **************************************************************************** ;* Process the Erase command. ; **************************************************************************** erase_page: ;* Page erase. Address is in Z. ldi imm1, ( 1 << PGERS ) | ( 1 << SPMEN ) rcall do_spm ;* Enable the RWW section.
Needed following a page
erase or page write. ;* The call to do_spm will not return until the read or write is ;* complete, so the '.' character will not be transmitted until the ;* read/write is complete. enable_rww: ldi imm1, ( 1 << RWWSRE ) | ( 1 << SPMEN ) rcall
do_spm
;* Send a '.' character to the UART to indicate previous command (if ;* any) is complete.
Branch back to this point if
a valid command ;* has been received and processed. tx_command_complete: ldi imm1, '.' rcall tx_byte rjmp wait_for_command_byte ; **************************************************************************** ;* Process the Read command. ; **************************************************************************** read_page: ;* Interate through the page, sending bytes. Starting address is in Z. ldi counter, PAGESIZEB read_page_loop: lpm imm1, Z+ rcall tx_hex_2 dec counter brne read_page_loop ;* Transmit "command complete" byte and Resume command processing rjmp
tx_command_complete
; **************************************************************************** ;* Process the Write command. ; **************************************************************************** write_page: ;* Read and store 1 page worth of data. Starting address is in Z. ldi counter, PAGESIZEW write_page_loop: rcall rx_hex_4 ;* Data into imm2: imm1 mov R0, imm2 mov R1, imm1 ldi imm1, ( 1 << SPMEN ) rcall do_spm adiw ZL, 2 dec counter brne write_page_loop ;* Wait for carriage return, bail out if any other character received rcall
wait_cr
;* Complete page of data received without error; write page subi sbci ldi
ZL, low ( PAGESIZEB ) ZH, high ( PAGESIZEB ) imm1, ( 1 << PGWRT ) | ( 1 <<
rcall
do_spm
SPMEN )
;* Transmit "command complete" byte and Resume command processing rjmp
enable_rww
; **************************************************************************** ;* Wait for a carriage return. If any other character is received, jump ;* to the error routine. ; **************************************************************************** wait_cr: rcall rx_byte cpi imm1, ASCII_CR brne wait_for_command_byte ret ; **************************************************************************** ;* Read a hex digit from the UART. If the value is '0' - '9' or 'A' - 'F', ;* convert to an integer 0-15 in register 'imm1'. Otherwise jump to the ;* error routine. ; **************************************************************************** rx_hex_1: rcall rx_byte ;* Test subi brcs cpi brcs
for '0' - '9' imm1, '0' wait_for_command_byte imm1, 10 rx_hex_1_end
;* Byte subi brcs cpi brcc
was greater than '9', test for 'A' - 'F' imm1, ( 'A' - '0' - 10 ) wait_for_command_byte imm1, 16 wait_for_command_byte
rx_hex_1_end: ret ; **************************************************************************** ;* Process the Go command. Jump to the address specified (in Z). ; **************************************************************************** go_command: ijmp ; **************************************************************************** ;* Read a 2-byte (4 hex digits) address from the UART and store it in Z. ;* Wait for carriage return after address is received. ; **************************************************************************** get_addr: rcall rx_hex_4 movw ZL, imm1 ;* Store address in Z rjmp wait_cr ;* Wait for carriage return
; **************************************************************************** ;* Read 4 hex digits from the UART. Return the value in 'imm2:imm1'. ; **************************************************************************** rx_hex_4: rcall rx_hex_2 mov imm2, imm1 ; Fall through to rx_hex_2 ; **************************************************************************** ;* Read 2 hex digits from the UART. Return the value in 'imm1'. ; **************************************************************************** rx_hex_2: rcall rx_hex_1 swap imm1 mov imm3, imm1 rcall rx_hex_1 or imm1, imm3 ret ; **************************************************************************** ;* Read a byte from the UART. Return the byte in register 'imm1'. ;* This function will spin until a byte has been received by the UART. ; **************************************************************************** rx_byte: sbis UCSRA, RXC rjmp rx_byte in imm1, UDR cpi imm1, ASCII_LF ;* Discard line feeds breq rx_byte ret ; **************************************************************************** ;* Send 2 hex digits to the UART. The byte to be sent must be in register ;* 'imm1'. ; **************************************************************************** tx_hex_2: mov imm2, imm1 swap imm1 ;* Send high order nibble first rcall tx_hex_1 mov imm1, imm2 ;* Send low order nibble next ; Fall through to tx_hex_1 ; **************************************************************************** ;* Send a hex digit to the UART. The digit to be sent will be the low ;* nibble of register 'imm1'. The high nibble will be ignored. ; **************************************************************************** tx_hex_1: andi imm1, 0x0F subi imm1, ( - '0' ) ;* Convert 0-9 to ASCII cpi imm1, ( '0' + 10 ) ;* Was it >9 ? brcs tx_byte subi imm1, ( '0' - 'A' + 10 ) ;* Convert A-F to ASCII ; Fall through to tx_byte ; **************************************************************************** ;* Send a byte to the UART. The byte to be sent must be in register 'imm1'. ;* This function will spin until the UART is ready to transmit. ; **************************************************************************** tx_byte: sbis UCSRA, UDRE rjmp tx_byte out UDR, imm1 ret ; **************************************************************************** ;* Issue the SPM instruction. The SPM command register value must be in ;* 'imm1'. Interrupts must be disabled, and no EEPROM write may be in ;* process. For a write to the page buffer, R0, R1, and Z must be set up ;* prior to calling do_spm. ; **************************************************************************** do_spm: ;* Wait for previous SPM to complete in imm2, SPMCR sbrc imm2, SPMEN rjmp do_spm ;* Write the SPMCR value from 'imm1' and issue the SPM instruction out spm
SPMCR, imm1
ret ; **************************************************************************** ;* Application services table. This is a jump table for services that ;* are made available to the application. The entry points for these ;* services are fixed addresses at the end of FLASH memory. ; **************************************************************************** ; **************************************************************************** ;* Write to program memory. This function will wait for any previous SPM ;* instruction to complete, then load SPMCR with the value in R16 and ;* issue the SPM instruction. R0, R1, and Z must be set up appropriately ;* for the function being performed. ;* Note: no EEPROM access may in in process, and interrupts must be disabled ; **************************************************************************** .org FLASHEND-1 appsrv_spm: rjmp do_spm
; **************************************************************************** ;* Start the boot loader. ; **************************************************************************** .org FLASHEND appsrv_go_boot: rjmp bootmain
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian http://avr-asm.tripod.com/bootdr8.html (1 of 2)1/20/2009 9:16:15 PM
16 BIT MATH (AVR 202)
Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/bootdr8.html (2 of 2)1/20/2009 9:16:15 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
ALARM CLOCK HOME RETRO_DAN ;-------------------------------------------------------; ; Developed by Claes Sundman , [email protected] ; ; Version 0.1 ; ; Alarmclock with calender and temp. and humidity sensor ; ; AT90S4433 PIN Project
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b
PIN
Project ; ; RESET
MATH 201 MATH 202 MATH 32X
PC5
26
DIV 24 24
25
PC3
24
PC2
INT ASCII HX2ASC
23
PC0
21
AREF
20
; PD1
3
RS
; PD2
4
R/W
; PD3
5
E
; PD4
6
D4
; VCC
7
; GND
8
; X1
9
; X2
10
; PD5
11
D5
; PD6
12
D6
; PD7
13
D7
; PB0
14
I/0
COPY 102
17
LED
PB5 PB4
I2C_SDA
PB3
I2C_SCL
16
PB2
PB1
SCLK DS1302 TST
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 direction bit in TWIadr
UART BUFF
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
.equ
SDAP
= 4
; SDA Pin number
.def .def
TWIdelay TWIdata
= r22 = r23
; Delay loop variable ; TWI data transfer
.def
TWIadr
= r24
; TWI address and
.def
TWIstat
= r25
; TWI bus status register
; SHT11 needs 11ms of delay after power up! ; SoftReset then wait 11ms
I2C/TWI 128
ETHNET 8019
; write bit ; write bit ; SCL Pin number
direction register
I2C TWI26
DALLAS CRC
= 1 = 0 = 3
register
I2C 302
DALLAS-1W
TWIrd TWIwr SCLP
(port B)
ISP 1200
I2C/TWI AT8
.equ .equ .equ (port B)
AVR ISP
I2C 300
15
; ;-------------------------------------------------------.include "4433def.inc" ;.include "i2c.inc" ;-------------------------------------------------------.DSEG .def tmp1 = r16 .def tmp2 = r17 .def tmp3 = r18 .def tmp4 = r19 .def tmp5 = r20 .def tmp6 = r21 ; Delay loop variable .equ b_dir = 0 ; transfer
FLASH CARD
AVR SPI
DS1302
DS1302
DFLASH AT45
ISP 2313
22
+5.0V
LPM 108
USB 232
PC4
AVCC
19 18
UART 128
27
AGND
FFT7
SER EPROM
-
PC1
AVG8 222
EPROM 100
2
Button4
MATH 202 DEC ASCII
; PD0
Button3
FLOAT 128
MATH 202
28
Button2
DIV16 XX
SQRT16
Resetbutton
Button1
MATH YX
DIV 3216
1
; .equ ADDR_SHT11_temp (00000011) ; .equ ADDR_SHT11_humi address byte Humidity read (00000101) ; .equ ADDR_SHT11_status_read = 0x03 byte Status read (00000111) ; .equ ADDR_SHT11_status_write = 0x07 byte Status write (00000110) ; .equ ADDR_SHT11_softreset = 0x0F byte SoftReset write(00011110) ; .equ ADDR_24LC16 24LC16, EEPROM address (10100000) ; .equ 24LC16_memsize EEPROM size
= 0x01
; SHT11
= 0x02
; SHT11
address byte Temp. read
; SHT11 address ; SHT11 address ; SHT11 address = 0x50
;
= 16384 ; 2048x8,
IRD 410 ; M24C16B Microchip max 400khz and 5ms to write. ; Address: 000 - 7FF = 24LC26B ;-------------------------------------------------------.cseg .org $000 rjmp reset ;rjmp INT_0 ; Ext. Interrupt 0 ;rjmp INT_1 ; Ext. Interrupt 1 ;reti TIMER1_CAPT ; Timer/Counter1
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
Capture
ALM CLK
DELAYS
;reti
TIMER1_OVF
; Timer/Counter1
;reti
TIMER0_OVF
; Timer/Counter0
;reti
SPI_STC
; SPI Transfer
;rjmp
UART_RX
; UART Receive,
;reti ;reti ;reti ;reti ;reti
UART_UDRE UART_TX ADAC EEE_RDY ANA_COMP
; ; ; ; ;
Overflow Complete serial data in
CALL ID DTMF 314 PWM 6CH PWM 10K
; Timer/Counter1
Overflow
CLOCK 8564 90 DAYS
TIMER1_COMP
Overflow
BOOT MG8 BOOT DR8
;reti
UART empty UART Transmit ADC Ready EE2 Ready Analog
comparator ;-------------------------------------------------------; Program memory starts here reset: ldi tmp1, low(RAMEND) out SPL, tmp1 ldi tmp1, 0xFF ; Init keys out PORTC, tmp1 ; -"out DDRC, tmp1 ; -"out DDRB, tmp1 ldi tmp1, 0x00 out PORTB, tmp1 CLR tmp1 CLR tmp2 CLR tmp3 ;-------------------------------------------------------main: rcall init_port rcall lcd_init ; rcall lcd_ready ; rcall alarm_led_off rcall ds1302_init ; rcall i2c rcall loop
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
loop: ;rcall rcall rcall ;rcall rjmp
keys ds1302_read_to_lcd ds1302_days_to_lcd temp loop
;-------------------------------------------------------alarm_led_on: sbi portc, 0 ret alarm_led_off: cbi portc, 0 ret ;-------------------------------------------------------keys: push tmp1 in tmp1, PORTC pop tmp1 ret ;-------------------------------------------------------temp: ldi tmp1, 0x8E rcall lcd_cmd ldi tmp1, 0b11011111 rcall lcd_char ldi tmp1, 'C' rcall lcd_char ret ;-------------------------------------------------------; Initial date/time code for lcd stored in format mon_day: .db "Monday *C";,0xA9 tues_day: .db "Tuesday *C";,0xA9 wednes_day: .db "Wednesday *C";,0xA9 thurs_day: .db "Thursday *C";,0xA9 fri_day: .db "Friday *C";,0xA9 satur_day: .db "Saturday *C";,0xA9 sun_day: .db "Sunday *C";,0xA9 ds1302_days_to_lcd: ldi tmp1, rcall lcd_cmd ldi tmp1,
0x80
; first line
$8B
; read
days rcall ldi cp breq ldi cp breq ldi cp breq ldi cp breq ldi cp breq ldi cp breq ldi cp breq
RdCmd tmp2, tmp1,
0b00000001 tmp2
tmp2, tmp1,
0b00000010 tmp2
tmp2, tmp1, wednesday tmp2, tmp1, thursday tmp2, tmp1, friday tmp2, tmp1, saturday tmp2, tmp1, sunday
0b00000011 tmp2
; test days...
monday
tuesday
0b00000100 tmp2 0b00000101 tmp2 0b00000110 tmp2 0b00000111 tmp2
ret monday: ldi rcall ldi ldi ldi rcall ret tuesday: ldi ldi ldi rcall ret wednesday: ldi ldi ldi rcall ret thursday: ldi ldi ldi rcall ret friday: ldi ldi ldi rcall ret saturday: ldi ldi ldi rcall ret sunday: ldi ldi ldi rcall ret
tmp1,
0x00
lcd_cmd r30, r31, tmp2, LCD_PrintPM
low (mon_day*2) high(mon_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (tues_day*2) high(tues_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (wednes_day*2) high(wednes_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (thurs_day*2) high(thurs_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (fri_day*2) high(fri_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (satur_day*2) high(satur_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (sun_day*2) high(sun_day*2) 16
;-------------------------------------------------------; Init the LCD in 4-bit mode BEGINNING lcd_init: push tmp1 ldi tmp1, 0x30 out portd, tmp1 rcall enable rcall wait rcall wait ldi out rcall rcall
tmp1, portd,
0x30 tmp1
ldi out rcall rcall
tmp1, portd,
0x30 tmp1
tmp1,
0x20
tmp1,
0x28
tmp1,
0x14
tmp1,
0x0c
tmp1,
0x06
tmp1,
0x01
tmp1,
0x80
enable wait
ldi rcall
enable wait
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall pop
lcd_cmd
lcd_cmd tmp1
ret ;-------------------------------------; Init the LCD in 4-bit mode READY lcd_ready: ldi tmp1, 'L' rcall lcd_char ldi tmp1, 'C' rcall lcd_char ldi tmp1, 'D' rcall lcd_char ldi tmp1, ' ' rcall lcd_char ldi tmp1, 'T' rcall lcd_char ldi tmp1, 'e' rcall lcd_char ldi tmp1, 's' rcall lcd_char ldi tmp1, 't' rcall lcd_char ldi tmp1, '!' rcall lcd_char ret ;-------------------------------------------------------init_port: ldi tmp1, 0xff out ddrd, tmp1 ret ;-------------------------------------------------------lcd_cmd: push tmp1 push tmp2 rcall lcd_busyread mov tmp2, tmp1 ;Load the value to the tmp2 also. andi
tmp2,
0xf0
;select the upper 4bits of the
tmp2, portd,
0x00 tmp2
tmp2, 0x0f
tmp1 ;load sent value to tmp2 ;select the 4 lower bits ;swap the lower D3-D0
tmp2, portd,
0x00 tmp2
sent byte ori out rcall mov andi swap
;mask the tmp2 RS=0 ;put result out to portc
enable tmp2, tmp2
bits to D7-D4 ori out rcall pop pop rcall
;mask the tmp2 RS=0 ;put result out to portc
enable tmp2 tmp1 wait_short
ret ;-------------------------------------------------------lcd_char: push tmp1 push tmp2 rcall lcd_busyread mov tmp2, tmp1 ;Load the value to the tmp2 also. andi
tmp2,
0xf0
;select the upper 4bits of the
tmp2, portd,
0x02 tmp2
tmp2, 0x0f
tmp1 ;load sent value to tmp2 ;select the 4 lower bits ;swap the lower D3-D0
tmp2, portd,
0x02 tmp2
sent byte ori out rcall mov andi swap
;mask the tmp2 RS=1 ;put result out to portc
enable tmp2, tmp2
bits to D7-D4 ori out rcall pop pop
;mask the tmp2 and RS=1 ;put result out to portc
enable tmp2 tmp1
ret ;-------------------------------------------------------lcd_busyread: push tmp1 ldi tmp1, 0x00 ;clear portC out portd, tmp1 ;make it happen ldi tmp1, 0x0f ;turn D7-D4 to inputs out ddrd, tmp1 ;make it happen lcd_busyread_wait: sbi portd, 2 ;R/W = 1 sbi portd, 3 ;Enable = 1 nop nop nop nop nop nop nop in tmp1, pind ;read from LCD cbi portd, 3 ;Enable = 0 nop nop nop nop rcall enable ;to complete reading the byte andi cpi brne ldi out pop
tmp1,
0x80 ;want only D7 tmp1, 0x00 ;is it zero ? lcd_busyread_wait ;jump if not equal to zero tmp1, 0xff ;make portC to output ddrd, tmp1 ;make it happen tmp1
ret ;-------------------------------------------------------; Toggle the Enable on the LCD enable: sbi portd, 3 ;pin D3 = 1 push tmp1 ldi tmp1, 10 enable_loop: dec tmp1 brne enable_loop pop tmp1 cbi portd, 3 ;pin D3 = 0 ret ;-------------------------------------------------------wait_short: push tmp1 ldi tmp1, 0x80 wait_short_loop: dec tmp1 brne wait_short_loop pop tmp1 ret wait: push tmp2 ldi tmp2, 0xff wait_loop: rcall wait_short dec tmp2 brne wait_loop pop tmp2 ret ;-------------------------------------------------------; LCD_PrintMem. Prints from memory. Put the starting, ; memory location in Z (r31:r30). Put the number of ; characters to print in tmp2. After execution, ; Z is at the character AFTER the last to be ; printed and tmp2 is zero. This function will ; not wrap if you the string is bigger than the LCD. LCD_PrintMem: push tmp1 LCD_MemRead: ld tmp1, Z+ rcall lcd_char dec tmp2 brne LCD_MemRead pop tmp1 ret ;-------------------------------------------------------; LCD_PrintPM. Prints from program memory LCD_PrintPM: push r0 push tmp1 LCD_PMRead: lpm mov tmp1, r0 rcall lcd_char adiw r30, 1 dec tmp2 brne LCD_PMRead pop tmp1 pop r0 ret ;-------------------------------------------------------; Macros, delay 0.125 x 40 = 5us 200khz and max are 400khz ;.MACRO rtc_delay: push tmp1 ldi tmp1, 0xFF;40 Load with 4 to generate 2MHz to DS1302 rtc_delay_2: dec tmp1 brne rtc_delay_2 pop tmp1 ret ;.ENDMACRO ;-------------------------------------------------------; DS1302 macro .MACRO IO_in cbi DDRB, 0 ; Make I/O line input. .ENDMACRO .MACRO
IO_out sbi
DDRB,
0
; Make I/O line
2
; Set SCLK output.
output. .ENDMACRO .MACRO
SCLK_high nop nop nop nop nop sbi nop
PORTB, nop nop nop nop
.ENDMACRO .MACRO
SCLK_low nop nop nop nop nop cbi nop nop
PORTB,
2
PORTB,
0
PORTB,
0
PORTB,
1
PORTB,
1
nop nop nop .ENDMACRO .MACRO
IO_high sbi .ENDMACRO .MACRO
IO_low cbi .ENDMACRO .MACRO
RST_high nop nop nop nop nop sbi nop nop nop nop nop .ENDMACRO .MACRO
RST_low nop nop nop nop nop cbi nop nop nop nop nop .ENDMACRO
;-------------------------------------------------------; Write a cmd / data combo from tmp1 / tmp2 to the RTC. WrtCmd: RST_high mov tmp3, tmp1 ; write command to RTC rcall WrtByte mov tmp3, tmp2 ; write data to RTC rcall WrtByte RST_low ret ; Clock out the byte in tmp3 to the RTC. ; Data is clocked out starting with bit 0. ; Data is clocked into the RTC on the rising edge. WrtByte: ldi tmp1, 8 WrtByte1: lsr tmp3 brcc WrtByte2 IO_high rjmp WrtByte3 WrtByte2: IO_low WrtByte3: SCLK_high dec tmp1 breq WrtByte4 SCLK_low rjmp WrtByte1 WrtByte4: IO_high SCLK_low applicable). @@ Claes , last bit is still here after last clock clc ret
; 8 bits to clock out. ; rotate.............bit 0 into C ; skip if bit = 0
; Clock it out. ; Do all the bits. ; turn on pull up. ; Clock data in (if
; Read a byte following write of command byte. RdCmd: RST_high IO_out mov tmp3, tmp1 rcall WrtByte IO_in rcall RdByte mov tmp1, tmp3 RST_low IO_out ret ; Clock in a byte from the RTC to tmp3 RdByte: ldi tmp3, 0
; Empty register
for data ldi
tmp1,
8
; 8 bits to clock
in. RdByte1: clc
; Clear
carry. sbic sec
PINB,
ror
tmp3
0
; Jump if I/O = 0. ; Set
Carry Flag ; Rotate data
into bit. SCLK_high
; clock in next
SCLK_low dec tmp1 brne RdByte1
; more bits ?
bit.
ret ;-------------------------------------------------------ds1302_init: ldi tmp1, $8E ; remove write protection ldi rcall ldi ldi rcall ldi ldi rcall ldi ldi rcall ldi ldi rcall
WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd
ldi ldi rcall ldi ldi rcall ldi ldi rcall
tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd
tmp2,
$00
;
$80 0x55
; write seconds ; 00; 0xxx xxxx
$82 0x59
; write minutes ; 00; 0xxx xxxx
$84 0x23
; write hours, 24h mode ; 00xx xxxx
$8A 0x01
; write day ; monday 01 - 07
$86 0x27
; write date for day ; 00xx xxxx
$88 0x02
; write month ; 000x xxxx
$8C 0x03
; write year ; xxxx xxxx
ret ; Info: ; sec. ; min. ; hour ; days
0xxx 0xxx 00xx 0000
BCD xxxx xxxx xxxx 0xxx
BCD
ds1302_read_to_lcd: ldi tmp1, 0xC0 rcall lcd_cmd ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $85 ; read 10 hour. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $85 ; read 1 hour. rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, 0xC2 ; colon rcall lcd_cmd ldi tmp1, ':' rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $83 ; read 10 minutes. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $83 ; read 1 minutes. rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, 0xC5 ; colon rcall lcd_cmd ldi tmp1, ':' rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $81 ; read seconds. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $81 rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, 0xCB ; date@lcd rcall lcd_cmd ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $87 ; read date. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $87 rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, '/' rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $89 ; read month. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi rcall andi ori rcall
$89
0x3F tmp1,
0x30
RdCmd tmp1,
tmp1,
lcd_char
ret ; *************************************************************************** ;* Supports both 7-bit and 10-bit addressing. ;* TWI functions : ;* 'TWI_start' Issues a start condition and sends address ;* and transfer direction. ;* 'TWI_rep_start' Issues a repeated start condition and sends ;* address and transfer direction. ;* 'TWI_do_transfer' Sends or receives data depending on ;* direction given in address/dir byte. ;* 'TWI_stop' Terminates the data transfer by issue a ;* stop condition. ;* Code Size : 81 words (maximum) ;* Register Usage : 4 High, 0 Low ;* ;* TWI_hp_delay: ;* TWI_qp_delay ;* hp - half TWI clock period delay (normal: 5.0us / fast: 1.3us) ;* qp - quarter TWI clock period delay (normal: 2.5us / fast: 0.6us) ; *************************************************************************** TWI_hp_delay: ldi TWIdelay, 2 TWI_hp_delay_loop: dec TWIdelay brne TWI_hp_delay_loop ret TWI_qp_delay: ldi TWIdelay, 1 TWI_qp_delay_loop: dec TWIdelay brne TWI_qp_delay_loop ret ; *************************************************************************** ;* TWI_rep_start Assert repeated start condition and sends slave address. ;* TWIadr - Contains the slave address and transfer direction. ;* Carry flag - Cleared if a slave responds to the address. ;* This funtion must be directly followed by TWI_start. ; *************************************************************************** TWI_rep_start: sbi DDRB, SCLP ; force SCL low cbi DDRB, SDAP ; release SDA rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL rcall TWI_qp_delay ; quarter period delay ; *************************************************************************** ;* FUNCTION ;* TWI_start ;* DESCRIPTION ;* Generates start condition and sends slave address. ;* USAGE ;* TWIadr - Contains the slave address and transfer direction. ;* RETURN ;* Carry flag - Cleared if a slave responds to the address. ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by TWI_write. ; *************************************************************************** TWI_start: mov TWIdata,TWIadr ; copy address to transmitt register sbi DDRB, SDAP ; force SDA low rcall TWI_qp_delay ; quarter period delay ; *************************************************************************** ;* FUNCTION ;* TWI_write ;* DESCRIPTION ;* Writes data (one byte) to the TWI bus. Also used for sending ;* the address. ;* USAGE ;* TWIdata - Contains data to be transmitted. ;* RETURN ;* Carry flag - Set if the slave respond transfer. ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by TWI_get_ack. ; *************************************************************************** TWI_write: sec ; set carry flag rol TWIdata ; shift in carry and out bit one rjmp TWI_write_first TWI_write_bit: lsl TWIdata ; if transmit register empty TWI_write_first: breq TWI_get_ack ; goto get acknowledge sbi DDRB, SCLP ; force SCL low brcc TWI_write_low ; if bit high nop ; (equalize number of cycles) cbi DDRB, SDAP ; release SDA rjmp TWI_write_high TWI_write_low: ; else sbi DDRD, SDAP ; force SDA low rjmp TWI_write_high ; (equalize number of cycles) TWI_write_high: rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL rcall TWI_hp_delay ; half period delay rjmp TWI_write_bit ; *************************************************************************** ;* FUNCTION ;* TWI_get_ack ;* DESCRIPTION ;* Get slave acknowledge response. ;* USAGE ;* (used only by TWI_write in this version) ;* RETURN ;* Carry flag - Cleared if a slave responds to a request. ; *************************************************************************** TWI_get_ack: sbi DDRB, SCLP ; force SCL low cbi DDRB, SDAP ; release SDA rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL TWI_get_ack_wait: sbis PINB, SCLP ; wait SCL high(In case wait states are inserted) rjmp TWI_get_ack_wait clc ; clear carry flag sbic PINB,SDAP ; if SDA is high sec ; set carry flag rcall TWI_hp_delay ; half period delay ret ; *************************************************************************** ;* FUNCTION ;* TWI_do_transfer ;* DESCRIPTION ;* Executes a transfer on bus. This is only a combination of TWI_read ;* and TWI_write for convenience. ;* USAGE ;* TWIadr - Must have the same direction as when TWI_start was called. ;* see TWI_read and TWI_write for more information. ;* RETURN ;* (depends on type of transfer, read or write) ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by TWI_read. ; *************************************************************************** TWI_do_transfer: sbrs TWIadr, b_dir ; if dir = write rjmp TWI_write ; goto write data
http://avr-asm.tripod.com/almclk.html (1 of 2)1/20/2009 9:16:58 PM
16 BIT MATH (AVR 202)
; *************************************************************************** ;* TWI_reads data (one byte) from the TWI bus. ;* USAGE ;* Carry flag If set no acknowledge is given to the slave ;* indicating last read operation before a STOP. ;* If cleared acknowledge is given to the slave ;* indicating more data. ;* TWIdata Contains received data. ;* This funtion must be directly followed by TWI_put_ack. ; *************************************************************************** TWI_read: rol TWIstat ; store acknowledge (used by TWI_put_ack) ldi TWIdata, 0x01 ; data = 0x01 TWI_read_bit: ; do sbi DDRD, SCLP ; force SCL low rcall TWI_hp_delay ; half period delay cbi DDRD, SCLP ; release SCL rcall TWI_hp_delay ; half period delay clc ; clear carry flag sbic PIND,SDAP ; if SDA is high sec ; set carry flag rol TWIdata ; store data bit brcc TWI_read_bit ; while receive register not full ; *************************************************************************** ;* TWI_put_ack Put acknowledge.(used only by TWI_read in this version) ; *************************************************************************** TWI_put_ack: sbi DDRD, SCLP ; force SCL low ror TWIstat ; get status bit brcc TWI_put_ack_low ; if bit low goto assert low cbi DDRD, SDAP ; release SDA rjmp TWI_put_ack_high TWI_put_ack_low: ; else sbi DDRD, SDAP ; force SDA low TWI_put_ack_high: rcall TWI_hp_delay ; half period delay cbi DDRD, SCLP ; release SCL TWI_put_ack_wait: sbis PIND, SCLP ; wait SCL high rjmp TWI_put_ack_wait rcall TWI_hp_delay ; half period delay ret ; *************************************************************************** ;* TWI_stop Assert stop condition. ; *************************************************************************** TWI_stop: sbi DDRB, SCLP ; force SCL low sbi DDRB, SDAP ; force SDA low rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL rcall TWI_qp_delay ; quarter period delay cbi DDRD, SDAP ; release SDA rcall TWI_hp_delay ; half period delay ret ; *************************************************************************** ;* TWI_init Initialization of the TWI bus interface. ;* Call this function once to initialize the TWI bus. No parameters ;* are required. PORTD and DDRD pins not used by the TWI bus interface will be ;* set to Hi-Z (!). This function can be combined with other PORTD initializations. ; *************************************************************************** TWI_init: clr TWIstat ; clear TWI status register (used as a temporary register) out PORTB, TWIstat ; set TWI pins to open colector out DDRB, TWIstat ret ; *************************************************************************** ;* main - Test of TWI master implementation ;* Initializes TWI interface and shows an example of using it. ; ; .equ ADDR_SHT11_temp = 0x01 ; (00000011) ; .equ ADDR_SHT11_humi = 0x02 ; (00000101) ; .equ ADDR_SHT11_status_read = 0x03 ; (00000111) ; .equ ADDR_SHT11_status_write = 0x07 ; (00000110) ; .equ ADDR_SHT11_softreset = 0x0F ; (00011110) ; .equ ADDR_24LC16 = 0x50 ; (10100000) ; .equ 24LC16_memsize = 16384 ; 2048x8, EEPROM size ; ; *************************************************************************** i2c: rcall TWI_init ; initialize ldi TWIadr,$A0+TWIwr ; Set device Adr (00) = 0x55 and write rcall TWI_start ; start ldi TWIdata,$00 ; Write word address (0x00) rcall TWI_do_transfer ; transfer ldi TWIdata,$55 ; Set write data to 01010101b rcall TWI_do_transfer ; transfer rcall TWI_stop ; stop ldi TWIadr,$A0+TWIwr ; Set device TWIdata = Adr(00) and write rcall TWI_start ; start ldi TWIdata,$00 ; Write word address rcall TWI_do_transfer ; transfer ldi TWIadr,$A0+TWIrd ; Set device address and read rcall TWI_rep_start ; repeated start sec ; Set no acknowledge (read is followed by a stop condition) rcall TWI_do_transfer ; transfer (read) rcall TWI_stop ; stop - releases bus ret ;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/almclk.html (2 of 2)1/20/2009 9:16:58 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
REAL TIME CLOCK FOR EPSON 8564 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45
; *************************************************************************** ; ; File Name :'RTC8564.asm" ; Title :Epson RTC8564JE Driver ; Date :2003.04.30. Lastmod.: [2003.04.30.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; Real Time Clock Modul Driver ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.04.30 VFX Creation ; ; *************************************************************************** ; ; ; ;Hardware ; *************************************************************************** ;*
FLASH CARD VFX SMIL VFX MEM SORT 220
; ************************************************************************** ;* Const Def ;
CRC 236
.equ
RTC_SlaveAddr = 0b10100010
XMODEM REC UART 304
; RTC internal Registers ; All data address 0x02 through 05 & 0x08 through 0x0B
UART 305 UART 128
is in BCD format .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
RTC_Control1 = 0x00 RTC_Control2 = 0x01 RTC_Seconds = 0x02 RTC_Minutes = 0x03 RTC_Hours = 0x04 RTC_Days = 0x05 RTC_WeekDays = 0x06 RTC_Months = 0x07 RTC_Years = 0x08 RTC_MinuteAlarm = 0x09 RTC_HourAlarm = 0x0A RTC_DayAlarm = 0x0B RTC_WeekdayAlarm= 0x0C RTC_CLKOUT_Freq = 0x0D RTC_TimerControl= 0x0E RTC_Timer = 0x0F
DALLAS-1W ;RTC Commands ;Control Register 1 .equ RTC_StopRunning = 0b00100000 .equ RTC_ContRunning = 0b00000000
DALLAS CRC ETHNET 8019 TEA ADC 128
;Control Register 2 .equ RTC_AlarmIntEnable = .equ RTC_AlarmIntDisable=
ADC 10B ADC 400 ADC 401
0b00000010 0b00000000
;Seconds [addr 0x02] .equ RTC_LowBat = 0b10000000
THERM 232 IRD 410
;century [Addr 0x07] .equ RTC_Cetury
LCD HD44
= 0b10000000
LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
; *************************************************************************** .DSEG
KBD PC/128
IO_CTR_RTC: .byte 17
PS2 EMU
controll
BOOT MG8
Line end
;IO buffer for RTC ;Time -> 00:00:00 + ;Date -> 2000-01-01
BOOT DR8 ALM CLK
+ Line end
CLOCK 8564 90 DAYS DELAYS CALL ID
; ************************************************************************* ;* Text Const ;* .CSEG
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ************************************************************************* ;* Read RTC All dataa ;* RTC_ReadALL: ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R17,16 ;reads 16 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,0 ;Begining fo read rcall TWI_StartRead ret ; ************************************************************************* ;* Start RTC ;* RTC_Start: rcall WaitToTWI ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R16,RTC_ContRunning st X,R16 ldi R17,1 ;write 16 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,0 ;Begining of write rcall TWI_StartWrite ret ; ************************************************************************* ;* Stop RTC ;* RTC_Stop: rcall WaitToTWI ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R16,RTC_StopRunning st X,R16 ldi R17,1 ;write 1 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,0 ;Begining of write rcall TWI_StartWrite ret ; ****************************************************************** ;* RTC Low Battery detector ; ; Out: ; z = 1 TWI Error ; z = 0 No error and ; c=1 Battery Low ; c=0 Battery Ok RTC_BatLow: ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R17,1 ;read 1 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19, RTC_Seconds ;Begining of read rcall TWI_StartRead rcall WaitToTWI brcs RTC_BatLow1 ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ld R16,X rol R16 ;csak a c=VL bit marad clz ret RTC_BatLow1: sez ;TWI Error ret LowBatS:
.db
"RTC Battery is Low - Check Date/
Time",CR,0 noRTC:
.db
"RTC not found - setup date/
time manualy ",CR,0 ; *************************************************************************** ; RTC Get Time ; ; In: ; Out: var X -> IO_CTR_RTC (00:00:00+zero byte) ASCCI ; R4:R3:R2 - hh:mm:ss BCD ; Used: RTC_GetTime:
R17,3 RTC_SlaveAddr
+0
+1
+2
rcall ldi ldi ldi
RTC_Stop XL,Low(IO_CTR_RTC+1) XH,High(IO_CTR_RTC+1)
ldi
R18,
ldi rcall rcall
R19,RTC_Seconds TWI_StartRead RTC_Start
ldi ldi ldd
ZL,Low(IO_CTR_RTC+1) ZH,High(IO_CTR_RTC+1) R16,Z
andi mov ldd
R16,0b01111111 R2,R16 R16,Z
andi mov ldd
R16,0b01111111 R3,R16 R16,Z
andi mov mov rcall std std ldi std mov rcall std std std mov rcall std std clr std movw ret
R16,0b00111111 R0,R16 R4,R16 BCDToASCII Z+0,R1 Z+1,R0 R17,':' Z+2,R17 R0,R3 BCDToASCII Z+3,R1 Z+4,R0 Z+5,R17 R0,R2 BCDToASCII Z+6,R1 Z+7,R0 R16 Z+8,R16 XL,ZL
;noumber of byte ;Slave Address
;sec
;min
;hrs
; *************************************************************************** ; RTC Set Time ; ; In: R4:R3:R2 -> hh:mm:ss BCD ; Out: c = 0 sucess ; c = 1 error ; Used: ; RTC_SetTime: rcall RTC_Stop ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) rcall WaitToTWI st X+,R2 st X+,R3 st X,R4 ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R17,3 ;noumber of byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,RTC_Seconds rcall TWI_StartWrite rcall RTC_Start ret ; *************************************************************************** ; RTC Set Date ; ; In: R4:R3:R2 -> yy:mm:dd BCD ; R5 - Century bit 0/1 ; Out: c = 0 sucess ; c = 1 error ; Used: ; RTC_SetDate: clr R16 ror R5 ror R16 or R3,R16 rcall RTC_Stop ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) rcall WaitToTWI st X+,R3 st X,R4 sbiw XL,1 ldi R17,2 ;noumber of byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,RTC_Months rcall TWI_StartWrite rcall WaitToTWI ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) st X,R2 ldi R17,1 ;noumber of byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,RTC_Days rcall TWI_StartWrite rcall RTC_Start ret ; *************************************************************************** ; RTC Get Date ; ; In: ; Out: var X -> IO_CTR_RTC (yyyy-mm-dd+zero byte) ASCCI ; R4:R3:R2 - yy-mm-dd BCD ; R5 - Century bit ; Used: RTC_GetDate:
R17,4 RTC_SlaveAddr
+0
rcall ldi ldi ldi
RTC_Stop XL,Low(IO_CTR_RTC+1) XH,High(IO_CTR_RTC+1)
ldi
R18,
ldi rcall rcall
R19,RTC_Days TWI_StartRead RTC_Start
ldi ldi ldd
ZL,Low(IO_CTR_RTC+1) ZH,High(IO_CTR_RTC+1) R16,Z
andi mov ldd mov andi mov rol clr rol tst brne ldi std ldi rjmp
R16,0b00111111 R2,R16 R16,Z+2 R5,R16 R16,0b00011111 R3,R16 R5 R5 R5 R5 XXICentury R16,'1' Z+0,R16 R16,'9' CenturyOk
ldi std ldi
R16,'2' Z+0,R16 R16,'0'
std
Z+1,R16
ldd
R16,Z
mov mov rcall std std ldi std mov rcall std std std mov rcall std std clr std movw ret
R0,R16 R4,R16 BCDToASCII Z+2,R1 Z+3,R0 R17,'-' Z+4,R17 R0,R3 BCDToASCII Z+5,R1 Z+6,R0 Z+7,R17 R0,R2 BCDToASCII Z+8,R1 Z+9,R0 R16 Z+10,R16 XL,ZL
;noumber of byte ;Slave Address
;days
XXICentury:
CenturyOk:
+3
;years
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two http://avr-asm.tripod.com/clock8564.html (1 of 2)1/20/2009 9:17:33 PM
16 BIT MATH (AVR 202)
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/clock8564.html (2 of 2)1/20/2009 9:17:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
90 DAY TIMER HOME RETRO_DAN ASM FORUM
; A 90 Day timer with 4 LEDs based on the AVR 90S2343 or Tiny22
ASM MATH
; Inputs - RESET button - pulls to ground when
TUTORIAL #1
pressed.
TUTORIAL #2
timer is running
TUTORIAL #3
; Outputs -
MATH 201
MATH YX
This design
improves on the App ; ; ; ;
note by: 1) Using timer0 and sleep mode to use less power. 2) Using a possibly lower cost AVR part. 3) Offering blinking LEDs to reduce power
consumption. (Future implementation) ; A constant-on mode is also available. ; Written 8/12/99 by Brian Hammill (hammill@ipass. net)
This code is ; copyright (C) 1999 by Brian Hammill.
Please give
credit to the ; author whenever using or distributing this code. Otherwise, you
INT ASCII HX2ASC
90 Day LED - Blinks when 90
; Note for the ACE1101 processor.
SQRT16
DEC ASCII
;
; This is based on an idea from a Fairchild
FLOAT 128
MATH 202
60 Day LED - Blinks when 60
Semiconductor Application
DIV 24 24
MATH 202
;
days have passed
DIV16 XX
DIV 3216
30 Day LED - Blinks when 30
days have passed
MATH 202 MATH 32X
; days have passed
MATH 200 MATH 200b
Status LED - Blinks to show the
; are free to use and make changes to this code.
If
you make ; an improvement, be nice and send a copy to me.
AVG8 222 FFT7
; Using the 1 MHz Internal OSC and a timer prescaler of CK/1024
COPY 102
; Timer0 will overflow approximately every 250 mS. ; We start up, init the timer, and put the chip to
LPM 108 EPROM 100 SER EPROM
sleep. ; When the timer overflows the chip wakes up, increments the 1 mS ; counter and goes back to sleep. ; When the 250 mS counter reaches 240 (1 Minute ),
DFLASH AT45 FLASH CARD
then the 1 min. counter is ; incremented and the 250 mS counter is reset to 0. ; When the 1 minute counter reached 60 (1 hour) then
VFX SMIL VFX MEM
we increment ; the 1 hour counter and reset the 1 minute counter
SORT 220 to 0 CRC 236 XMODEM REC UART 304
; when the 1 hour counter reaches 240 (10 days) increment the ; 10 day counter and reset the 1 hour counter. The 1 hour and 10 day count
UART 305 UART 128
; is stored in EEPROM so that if the power fails, at most an hour's count ; is lost. ; The timer ISR will check the EEPROM to see when the
UART BUFF USB 232
elapsed
AVR ISP
blink the
; time reaches 30, 60, and 90 days and set a flag to ; appropriate LED.
ISP 2313 ISP 1200
timer values and the ; EEPROM location and start counting from 0 again. ; Blinking the LEDs is handled in the 250 mS timer
AVR SPI I2C 300
ISR.
A low duty cycle is ; used to flash the LEDs so that power can be reduced. ; ; Written for the Atmel AVR Assembler version 1.30. ; This code illustrates a way to generate extremely
I2C 302 I2C TWI26 I2C/TWI 128
long delays. ; It also shows how to read/write the AVR EEPROM and ; how to use timer0 with interrupts. This program
I2C/TWI AT8 DALLAS-1W
uses 6 registers ; and 2 EEPROM locations.
DALLAS CRC ETHNET 8019
needed.
No SRAM is used or
It is approximately ; 123 words of code space. ; ; The external interrupt for reset operation is not
TEA ADC 128
The reset button will clear all
yet active.
ADC 10B ADC 400
; For some reason the hour location in EEPROM gets incremented
ADC 401 THERM 232 IRD 410
; about 4 times as often as it should. timer is
; running faster than CK/1024 or CK is faster than 1MHz (internal RC) ; So I changed the hour counter to 240 minutes
LCD HD44 LCD 2313 LCD44 2313
instead of 60 minutes. ; Can trim the minute and hour count compare values to improve the ; timer accuracy.
KBD 240 MUX 242 KBD PS2
I think the
; Make sure to set the RCEN flag when programming the 2343.
KBD PC/128
.include "2343def.inc"
PS2 EMU BOOT MG8 .def .def .def .def .def .def
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS
times through ISR.
CALL ID
.equ .equ
reset_pin = 1 status_led = 0
; PB1 is the reset (INPUT) ; PB0 is the status LED
.equ
days30_led = 2
; PB2 is the 30 day LED
.equ
days60_led = 3
; PB3 is the 60 day LED
DTMF 314 PWM 6CH
indicator. (OUTPUT)
PWM 10K
indicator. (OUTPUT)
ENCODE STH-11 ATMEL CORP
count_250ms = r16 count_10s = r17 count_1m = r18 temp = r19 led_mask = r20 led_counter = r21 ; used to flash the LEDs every n
indicator. (OUTPUT) .equ
days90_led = 4
; PB4 is the 90 day LED
indicator. (OUTPUT)
AVR BUTTERFLY
; There are no more I/O pins on the 2343. ; the Interrupt Vector table
AVR BOOK
.org 0x00 ; Power up reset rjmp POWER_ON ; External HW Int ;rjmp reset_button reti ; Internal Timer0 Overflow rjmp Timer0
POWER_ON: ; Initialize the Stack Pointer, WDT, Interrupts, I/ O Pins, and Timer0 cli
; Make sure
interrupts are disabled for now. ldi
temp, 14
;15 = 2048 mS, 14 = 1024, 13 =
out
WDTCR, temp ; Watchdog timer is a good idea
ldi out clr out
ZL,low(RAMEND) SPL,ZL ;init Stack Pointer temp GIMSK, temp ; don't allow
512 mS here.
External INT0 ldi out
temp, 2 TIMSK, temp
; allow
ldi out
temp,0b11111111 DDRB, temp
; all
ldi out
temp, 0b101 TCCR0, temp
; timer
ldi out
temp, 0b00100000 MCUCR, temp
; sleep
Timer0 overflow interrupts.
outputs except for PB1
prescaler = CK/1024
mode enabled, Idle mode selected ;ldi ;out
temp,$80 ACSR,temp
; ; Comparator
Disabled to save power
; All LEDs OFF ser led_mask out PORTB, led_mask clr
led_counter
zero_timer: clr out
temp TCNT0, temp
; start
timer at 0 sleep_and_wait: ; check the 10 days location in EEPROM to see if we need to light any LEDs ldi
temp, 1 ; put address 0 in the EEPROM
address register
enable bit until it is cleared.
out EEAR, temp sbi EECR, EERE Get_READ_POLL: ; this will poll the EECR read Then sbic EECR, EERE ; the EEPROM data will be available
at the EEPROM data register. rjmp Get_READ_POLL in temp, EEDR ; copy the contents to our local variable. ; Now the 10 days value is in temp. cpi temp, 3 ; 30 days brlt done_setting_bits ;cbr led_mask, days30_led cbi PORTB, days30_led cpi temp, 6 ; 60 days brlo done_setting_bits ;cbr led_mask, days60_led cbi PORTB, days60_led cpi temp, 9 ; 90 days brlo done_setting_bits ;cbr led_mask, days90_led cbi PORTB, days90_led done_setting_bits: sei make sure interrupts are enabled at this time. sleep CPU in idle mode. The Timer0 still runs. nop nop rjmp sleep_and_wait
; ; put the
;The following is the Timer0 ISR where all the work gets done. ;At 1 MHz the timer will overflow approximately every 250 mS. Timer0: cli We have 250 mS to do all this. inc sbis rjmp rjmp
in case.
; disable further interrupts just led_counter PORTB, status_led led_now_on led_now_off
led_now_off: ; we want to turn it on when count gets to 8 cpi led_counter, 8 ;rjmp turn_on_status_led breq turn_on_status_led rjmp skip_over turn_on_status_led: cbi PORTB, status_led clr led_counter rjmp skip_over led_now_on: ; it is on, so turn it off sbi PORTB, status_led skip_over: ;cpi led_counter, 30 ;brlt dont_clear ;clr led_counter dont_clear: ; com led_mask ; temp test code. ;out PORTB, led_mask ; turn on the LEDs for number of days. ms250_handler: wdr
;
don't forget to reset the WDT inc cpi reached 1 minute?
count_250ms count_250ms, 240
; has the count
Adjust for accuracy. breq one_minute ; flash the LED's in this section. rjmp exit_interrupt one_minute: clr count_250ms inc count_1m cpi count_1m, 240 breq hour_handler rjmp exit_interrupt
; has 1 hour passed?
hour_handler: ; this routine has to write the EEPROM.
Put in the
checks in the 100ms section ; to flash the corresponding LEDs when EEPROM value reaches specific numbers. clr count_1m ; set aside two EEPROM locations. Location 0 counts the hours up to 240 hours (10 days). ; then location 1 is incremented to count tens of days. When location 0 reaches 240 ; hours, then we increment location 1 and clear location 0. ; start by getting the value of location 0. is less than 240 increment it.
If it
Else ; clear and increment location 1. ldi
temp, 0 ; put address 0 in the EEPROM
address register
enable bit until it is cleared.
out EEAR, temp ldi temp, 1 ; enable EEPROM read out EECR, temp EE_READ_POLL: ; this will poll the EECR read Then sbic EECR, 0 ; the EEPROM data will be available at
the EEPROM data register. rjmp EE_READ_POLL in temp, EEDR
; copy the contents to our local
variable. cpi temp, 240 ; see if 10 days have passed breq TEN_DAYS inc temp ; if not 10 days, then increment the hour counter and write back to EEPROM out EEDR, temp sbi EECR, EEMWE ; set the EEPROM master write enable sbi EECR, EEWE ; set the EEPROM write enable bit EE_WRITE_POLL: sbic EECR, EEWE ; this will poll on the write enable bit until it clears (write complete) rjmp EE_WRITE_POLL cbi EECR, EEMWE ; clear the master write enable bit to prevent any further write. rjmp exit_interrupt
hours).
TEN_DAYS: ; ten days has passed if we reach here (240 If we get here, then we need to clear ; EEPROM location 0 and increment EEPROM location 1. ldi temp, 1
; put address 1 in the EEPROM data
register out EEAR, temp sbi EECR, EERE ; set the read enable bit READ_POLL: sbic EECR, EERE ; poll the read bit rjmp READ_POLL in temp, EEDR
; get the EEPROM data into local
variable temp. inc temp
; add 1 to the temp
register. ; need to set flags for LEDs here, now that we have the number of 10 day periods in temp out EEDR, temp ; get ready to write back to EEPROM. sbi EECR, EEMWE ; set master write enable sbi EECR, EEWE WRITE_POLL: sbic EECR, EEWE ; poll the write bit rjmp WRITE_POLL ; now we have to clear the hours location in EEPROM to start over. clr out out sbi
temp EEAR, temp ; set EEPROM address to 0. EEDR, temp ; set data register to 0. EECR, EEMWE ; set the master write
enable. sbi EECR, EEWE
; set the write bit strobe.
POLL_WRITE: sbic EECR, EEWE ; poll the write bit rjmp POLL_WRITE cbi EECR, EEMWE ; clear the master write enable bit
updated.
; now the 10 day location in EEPROM has been Next we reset the counter re-enable ; interrupts, and return from the interrupt. exit_interrupt: ;sbi PORTB, status_led
; turn off the status LED
before we leave. ;sbi PORTB, days30_led ;sbi PORTB, days60_led ;sbi PORTB, days90_led
; turn off the day count
LEDs. clr temp out TCNT0, temp sei reti
reset_button: ; if the reset button is pressed, we will come here. Reset the EEPROM locations ; reset the register counters, and jump back to the beginning.
ldi
temp, 0 ; put address 0 in the EEPROM
address register out EEAR, temp out EEDR, temp sbi EECR, EEMWE ; set the EEPROM master write enable sbi EECR, EEWE ; set the EEPROM write enable bit CLEAR_LOCATION_ZERO: sbic EECR, EEWE ; this will poll on the write enable bit until it clears (write complete) rjmp CLEAR_LOCATION_ZERO out EEDR, temp inc temp out EEAR, temp sbi EECR, EEMWE sbi EECR, EEWE CLEAR_LOCATION_ONE: sbic EECR, EEWE rjmp CLEAR_LOCATION_ONE cbi EECR, EEMWE ; clear the master write enable bit to prevent any furthe rjmp
POWER_ON
; start over.
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed http://avr-asm.tripod.com/90days.html (1 of 2)1/20/2009 9:18:08 PM
16 BIT MATH (AVR 202)
using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/90days.html (2 of 2)1/20/2009 9:18:08 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DELAYS PACKAGE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
; ****************************************************************************** ;_Delays.asm Version 0.0a ; ****************************************************************************** ; ;Written for : Atmel "AVR Assembler" and "AVR Assembler 2" ; when : 2005 November 20 ; where: BRUSSELS - BELGIUM - EUROPE ; who : Jan Huygh ; E-mail: [email protected]
MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
; ****************************************************************************** ;A WORD FROM THE AUTHOR : ; ;I would find it motivating to find out that people use this code. ; ;On regular base (every 10 to 12 weeks) I gather the comments on the code I ;posted and use the comments to improve my code. If you have constructive ;comment then let me know. ; * Give me an evaluation. ; * Send me a mail ([email protected]) subject "I use your _Delays.asm". ; * Send me a mail ([email protected]) subject "Comment on your _Delays.asm" ; ****************************************************************************** ;ABOUT VERSION 0.0a ; ;This is the first posted version. ; ; KNOWN BUGS : ; * None so far ; OPPORTUNITIES FOR IMPROVEMENT : ; * a version that can be used as a subroutine taking in to acount the time ; for the call and for the return. ; * a version that takes the input from the stack so it can take a variable ; for the input. ; * a version that is less precise but takes less bytes of program memory ; ; ****************************************************************************** ;.INCLUDE "_Delays.asm" enables you to use the following macro in your code ; ; _Waiste_us n ; With (1.000.000/F_CPU) <= n <= 25769803779/ Your_CPU_frequency_in_MHz ; ; This macro will generate a wait loop from 1 µs to 25.769.803.779 µs ; Depending on the CPU-speed set in F_CPU here below you will need to ; respect a minimum value for n. (n_minimum) = 1.000.000/F_CPU). ; This is needed because we can not loop for less then 1 ; instruction cycle. ; 25.769.803.779 µs, that's over 3h30 when you use a CPU running at 20 MHz. ; _Waiste_us is absolutely exact down to (1/ Your_CPU_frequency_in_MHz) µs ; _Waiste_us will pick the smallest code for your delay (Maximum 13 words)
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ****************************************************************************** ;How to use this in your code : ; ; A) Pick the correct ".equ F_CPU = x" statement ; AND ; save this file to your disk ; ; B) Make sure it is in the same folder as the other files of your current project ; OR ; Make sure the folder where you saved this file is referenced in the ; assembler options (Project=>Assembler Options=>Additional include path) ; ; C) Include the statement .INCLUDE "_Delays.asm" at the top of your program ; ; D) Use the statement _Waiste_us n, in your code ; ;Here is a code example : ; ; .INCLUDE "_Waiste.asm" ;Make the macro _Waiste_us n available in your code ; _Waiste_us 100 ;loop for 100 µs (that's 0,1 ms) ; _Waiste_us 16000 ;loop for 16.000 µs (that's 16 ms) ; _Waiste_us 7000000 ;loop for 7.000.000 µs (that's 7 s ) ; ; ****************************************************************************** ;The CPU-speed needs to be set before you can use _Waiste_us. ;Find your CPU-speed in the list here below and uncomment it (remove the ";") ;then press Ctrl^S to save to disk otherwise the include file used by AVR studio ;will be the unchanged version on your disk. ; ; ; .equ F_CPU = 1000000 ;Hz ; .equ F_CPU = 2000000 ;Hz .equ F_CPU = 3579545 ;Hz ; .equ F_CPU = 3686400 ;Hz ; .equ F_CPU = 4000000 ;Hz ; .equ F_CPU = 4032000 ;Hz ; .equ F_CPU = 4096000 ;Hz ; .equ F_CPU = 4194304 ;Hz ; .equ F_CPU = 4433619 ;Hz ; .equ F_CPU = 4915200 ;Hz ; .equ F_CPU = 5000000 ;Hz ; .equ F_CPU = 5068800 ;Hz ; .equ F_CPU = 5990400 ;Hz ; .equ F_CPU = 6000000 ;Hz ; .equ F_CPU = 6144000 ;Hz ; .equ F_CPU = 6500000 ;Hz ; .equ F_CPU = 7372800 ;Hz ; .equ F_CPU = 7680000 ;Hz ; .equ F_CPU = 8000000 ;Hz ; .equ F_CPU = 9000000 ;Hz ; .equ F_CPU = 9216000 ;Hz ; .equ F_CPU = 9830400 ;Hz ; .equ F_CPU = 10000000 ;Hz ; .equ F_CPU = 10240000 ;Hz ; .equ F_CPU = 11000000 ;Hz ; .equ F_CPU = 11059200 ;Hz ; .equ F_CPU = 11520000 ;Hz ; .equ F_CPU = 12000000 ;Hz ; .equ F_CPU = 12000393 ;Hz ; .equ F_CPU = 12288000 ;Hz ; .equ F_CPU = 13500000 ;Hz ; .equ F_CPU = 14318180 ;Hz ; .equ F_CPU = 14745600 ;Hz ; .equ F_CPU = 15000000 ;Hz ; .equ F_CPU = 15360000 ;Hz ; .equ F_CPU = 16000000 ;Hz ; .equ F_CPU = 16000312 ;Hz ; .equ F_CPU = 16257000 ;Hz ; .equ F_CPU = 16384000 ;Hz ; .equ F_CPU = 17734475 ;Hz ; .equ F_CPU = 18000000 ;Hz ; .equ F_CPU = 18432000 ;Hz ; .equ F_CPU = 19660800 ;Hz ; .equ F_CPU = 20000000 ;Hz
.Macro _Waiste_us ;n ; Calculate the number of CPU-cycles needed to generate the requested delay ;
taking in to account the frequency you are using
;
You can simplify the next 9 lines of code before
;
to "Cycles_Needed = @0 * F_CPU / 1000000". If you
;
generate the exact delay you requested or the delay
;
number of cpu-cycles that brings just less then the
;
This might be a good option if you need a certain
;
you never have a delay that is even a fraction of a
; ;
delay you requested. The 9 lines of code here below do NOT use any space
; ;
memory of your AVR. The code here below will actually pick the number
;
generate EXACTLY the delay you requested and when
;
it will select the number of cycles that generate
;
approximation for the delay you requested even if
;
delay you requested. .set Fraction = ; .set Fraction = Fraction * 100 .set Fraction = @0*F_CPU/10000 - Fraction .if Fraction >= 50 .equ Cycles_Needed = (@0 *
for your CPU. "_Cycle_Waister Cycles_Needed" do so _Waist_us will obtained by executing the delay you requested. delay but need to be sure CPU-cycle longer than the
in the actual program
of CPU-cycles needed to that can not be achieved the delay that is the best that is just above the
@0*F_CPU/1000000
F_CPU /1000000)+1 .endif .if .equ
Fraction < 50 Cycles_Needed = (@0 *
F_CPU /1000000) .endif _Cycle_Waister Cycles_Needed .endmacro .macro _Cycle_Waister .If @0 == 1 nop .EndIf .If @0 == 2 nop nop .EndIf .If ((@0 > 2) && (@0 < 769)) ;C=3n ;769=(3 * (2^8)) + 1 .set Loops_Needed = @0/3 ldi R16,Low(Loops_Needed) Loop: dec R16 brne Loop .set Cycles_Left_To_Do = @0 (3*Loops_Needed) _Cycle_Waister Cycles_Left_To_Do .EndIf .If (@0 > 768) && (@0 < 262146) ;C=1+4n ;262146 = 1 + (4 * 2^16) + 1 .set Loops_Needed = (@0 - 1)/4 ldi ZL,Low(Loops_Needed) ldi ZH,High(Loops_Needed) Loop: sbiw ZL,1 brne Loop .set Cycles_Left_To_Do = (@0 (4*Loops_Needed))-1 _Cycle_Waister Cycles_Left_To_Do .EndIf .If (@0 > 262145) && (@0 < 83886083) ;C=2+5n ;83.886.083 = 2 + (5 * 2^24) +1 .set Loops_Needed = (@0 - 2)/5 ldi R16,Low(Loops_Needed) ldi ZL,Byte2(Loops_Needed) ldi ZH,Byte3(Loops_Needed) Loop: subi R16,1 sbci ZL,0 sbci ZH,0 brne Loop .set Cycles_Left_To_Do = (@0 (5*Loops_Needed))-2 _Cycle_Waister Cycles_Left_To_Do .EndIf .If (@0 > 83886082) && (@0 < 25769803780) ;C=3+6n ;25769803780 = 3 + (6 * 2^32) +1 .set Loops_Needed = (@0 - 3)6 ldi XL,Low(Loops_Needed) ldi XH,Byte2(Loops_Needed) ldi ZL,Byte3(Loops_Needed) ldi ZH,Byte4(Loops_Needed) Loop: sbiw Xl sbci ZL,0 sbci ZH,0 brne Loop .set Cycles_Left_To_Do = (@0 (6*Loops_Needed)) - 3 _Cycle_Waister Cycles_Left_To_Do .endif .endmacro
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB http://avr-asm.tripod.com/delays.html (1 of 2)1/20/2009 9:18:41 PM
16 BIT MATH (AVR 202)
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/delays.html (2 of 2)1/20/2009 9:18:41 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
CALLER ID HOME RETRO_DAN ;callerID.asm ; ;neil barnes / nailed_barnacle 2003
ASM FORUM ASM MATH TUTORIAL #1
;this is intended to run on the AVRMega8 at 16MHz
TUTORIAL #2 TUTORIAL #3
.include "m8def.inc"
MATH 200 MATH 200b ;*************************************************************************** ;* most variables live in the registers full time ;***************************************************************************
MATH 201 MATH 202 MATH 32X
.CSEG
MATH YX ;r1 ;r0 ;r2 ;r3
DIV16 XX DIV 24 24 DIV 3216
and r0 are needed by multiply has low byte, r1 high byte used as temp store for 16*16 mul used as temp store
FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
.def .def .def .def
result0 result1 result2 result3
.def .def .def .def
main0 main1 main2 main3
= = = =
;partial result for 16*16 mult summed here ;also accumulator for fir filter ; ;high byte
r20 r21 r22 r23
;Temp variable used by main program ; " " " " " ; " " " " " ; " " " " "
= = = =
r16 r17 r18 r19
AVG8 222 FFT7 COPY 102
;*************************************************************************** ;* Port Pin Assignements ;***************************************************************************
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD
;*************************************************************************** ;* Interrupt vectors ;***************************************************************************
VFX SMIL VFX MEM SORT 220 CRC 236
.org 0 rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
RESET RESET RESET RESET RESET RESET sample RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET
;reset ;external int 0 ;external int 1 ;timer 2 compare ;timer 2 overflow ;timer 1 capture ;timer 1 compare a ;timer 1 compare b ;timer 1 overflow ;timer 0 overflow ;serial xfer complete ;usart rx complete ;usart data register empty ;usart tx complete ;adc conversion complete ;eeprom ready ;analogue comparator ;two-wire serial ;store program memory ready
I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
.equ length = 21
;size of buffer
DALLAS CRC ; bit defines for the UART status register .equ idle = 1 .equ rxflag = 2 .equ start = 3 .equ run = 4 .equ framerr = 5 .equ stop = 6
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
.dseg
THERM 232
input: .byte 2 output: .byte 2 result: .byte 1 rx: .byte 1 status: .byte 1 clock: .byte 1 bit: .byte 1 q: .byte 1
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
buffer: delay: ;offset: nextwrite:
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
.byte .byte .byte .byte
(length*2) ; room here for 21 samples 10 2 ; this says where we're reading the data offset 2 ; and this is where the next write occurs
.cseg
BOOT DR8 ALM CLK
;*************************************************************************** ;* ;* MAIN PROGRAM ;* ;*************************************************************************** ;* INITAILIZATION ;***************************************************************************
CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
RESET:
PWM 10K ;we need to set the stack pointer to top of ram Main1,$04 SPH, Main1 Main1,$5f SPL, Main1 ;top of ram is $045f
ENCODE ldi out ldi out
STH-11 ATMEL CORP AVR BUTTERFLY
;*************************************************************************** ;* MAIN LOOP ;***************************************************************************
AVR BOOK
; ; ; ; ; ;
set up an interrupt to look at a port so we can use a pre-fudged test data suite in the real world we will read the adc port using a 16MHz clock and with a 9600 per second sample rate it needs an interrupt every 1667 clocks (strictly 1666.6666...) so we will use timer 1 with no prescale
ldi out ldi out ldi out ldi out
main1,0b11111111 DDRD,main1 main1,0b00000000 PortD,main1 main1,0b00000000 DDRB,main1 main1,0b11111111 PortB,main1
;set port D bits to outputs
ldi ldi out out
main0,low(1667) main1,high(1667) ocr1ah,main1 ocr1al,main0
;set timer values for 9600
ldi out
main0,0b00001001 TCCR1B,main0
;don't use timer prescaler, use CTC mode
ldi out
main0,0b00010000 TIMSK,main0
;M8 uses bit 5 to ;enable comparator a interrupt
;preset
output state
;set port B to inputs ;turn on pullups on inputs
;clear the delay and main buffer ldi main0,10 ldi ZH,high(delay) ldi ZL,low(delay) clr main1 init_01: st Z+,main1 dec main0 brne init_01 ldi ldi ldi init_02: st dec brne
main0,42 ZH,high(buffer) ZL,low(buffer) Z+,main1 main0 init_02
sei
;and allow interrupts
;setup stuff for the software uart ;it occurs to me that one could pass the data out ;on a pin and back to the usart as an input ;but where's the fun in that? clr sts sts sts
main0 nextwrite,main0 nextwrite+1,main0 result,main0
clr r15 sts sts ldi sts FOREVER:
bit,main0 clock,main0 main0,exp2(idle) status,main0
lds andi breq lds out forever_1: lds andi brne
r24,status r24,exp2(rxflag) forever r24,rx portd,r24
jmp
;watch for the rxflag to be set ;output the data
r24,status r24,exp2(rxflag) forever_1
;wait for rxflag to reset
FOREVER
sample:
;loop forever
;we get here when there's a timer1 tick ;every 104uS or thereabouts ;read the B port and feed it to the filter ;routine ;the main program will look after what's happening ;to the data itself
in rcall inc reti
main1,pinb filter r15
filter: ; this is translated from C code ; it can probably be improved :) ; ; called every time a new sample is taken ; i.e. every 9600th second ; ; other frequencies could be used; but the sample ; rate must be chosen to give an even whole number of ; samples per bit period e.g. 7200, 9600, 12000 ; ; 7200 samples/sec = 6 samples/bit and is the lowest that ; will reliably work ; ; 'thingy' is the sample received from the ADC, though we could ; get the sample directly in finished code ; ; the system decodes the codec tones by delaying ; each sample by half a bit length, multiplying the ; delayed sample by the inverse of the current sample, ; and low-pass filtering the result
;
input = ((((short)thingy)-0x80)<<8); ; ; ; ;
this assumes 8-bit unipolar data is being received i.e. maximum negative is 0, maximum positive is 0xff, and zero is 0x80 the data is expected to arrive in the main1 register
ldi sub clr sts sts ; ; ; ;
main0,0x80 main1,main0 r2 input,r2 input+1,main1
; and save the result
// we delay the input samples_per_bit/2 samples (4 samples) for (q=0; q<5; q++) delay[q] = delay[q+1]; ldi
main0,4
ldi ldi ldi ldi
r30,low(delay) r31,high(delay) r28,low(delay+2) r29,high(delay+2)
fi_0001: ld st ld st dec brne ; ; ;
// upscale the sample
;point Z at delay[0]
r0,Y+ Z+,r0 r0,Y+ Z+,r0 main0 fi_0001
;point Y at delay[1]
;copy one word ;and repeat four times
// save new sample delay[spb/2] = input; ;Z should be pointing at delay[4] lds r0,input lds r1,input+1 st Z+,r0 st Z+,r1
; ; ;
// now we multiply todays sample with the delayed one ac = (int)delay[0]*(int)input*-1; movw lds lds movw rcall ldi ldi eor eor eor eor inc inc add adc adc adc
; ; ;
main1:main0,r1:r0 r0,delay r1,delay+1 main3:main2,r1:r0 mul16 main0,0xff main1,0 result0,main0 result1,main0 result2,main0 result3,main0 main0 main0 result0,main0 result1,main1 result2,main1 result3,main1
;result in result0-3
;now multiply by -1 ;the fast way
;should be a touch quicker than ;calling mul16 again
// and finally, low pass filter the result b[0] = ac>>15; ; ; ; ;
if it we so
we look at the result of a 16*16 signed multiply turns out there are two sign bits only want one of them we'll shift up one rather than down 15
rol rol rol
result1 result2 result3
;our result is in result2,3
; work out where to put it ; see below - we're emulating a circular buffer ; we are trying to synchronise two buffers here ; the buffer itself is in ram ; the coefficients are in program rom ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
what we are implementing is this: a standard FIR filter sums the products of the filter coefficients and the data, and then shifts the data along one place the next item of data gets added in at the beginning of the data buffer we don't want to do the shift if we can avoid it as it costs 11uS and we don't have time to spare a real DSP chip would have a circular buffer, we emulate it we have two copies of the filter coefficients butted to each other P
Q
R
S
T
P' Q' R' S' T'
and one copy of the data buffer A
B
C
D
E
we start with a pointer to P', and do the summation AP'+BQ'+CR'+DS'+ET' next time we add new data to replace A F
B
C
D
E
decrement the pointer to T, and do the summation FT+BP'+CQ'+DR'+ES' and so on. When the coefficient filter passes P we aim it at P' and in this way need not move any data
; buffer[nextwrite] = ac>>15; lds main0,nextwrite clr main1
;will always be 0
push push
main1 main0
;save nextwrite
ldi ldi add adc
YL,low(buffer) YH,high(buffer) YL,main0 YH,main1
;Y points to buffer[nextwrite]
st st
Y+,result2 Y+,result3
; offset = 21-nextwrite; ldi ZL,42 clr ZH sub ZL,main0 sbc ZH,main1
;21 words
;Z now has offset
; ac = 0; clr result0 clr result1 clr result2 clr result3 ; for (q=0; q<21; q++) ldi main3,20 mov r3,main3 ; ldi ldi ldi ldi add adc
ac+= (int)buffer[q]*(int)hi1k2[q+offset]; YL,low(buffer) YH,high(buffer) main2,low(hi1k2*2) main3,high(hi1k2*2) ZL,main2 ZH,main3
clr
r2
fi_0002: ld ld lpm lpm
;this needs to be zero ;for the multiply
main0,Y+ main1,Y+ main2,Z+ main3,Z+
;buffer[q]
;hi1k2[q+offset] ;and both pointers incremented ; 16*16->32 bit multiply and accumulate ; result0-3 += main0,1 * main2,3 ; inlined for speed muls add adc mul add adc adc adc mulsu sbc add adc adc mulsu sbc add adc adc
main3,main1 result2,r0 result3,r1 main2,main0 result0,r0 result1,r1 result2,r2 result3,r2 main3,main0 result3,r2 result1,r0 result2,r1 result3,r2 main1,main2 result3,r2 result1,r0 result2,r1 result3,r2
dec brge
r3 fi_0002
;and do this 21 times
; nextwrite++; pop main0 pop main1 inc main0 inc main0
;get it back ;increment to next word - won't roll over
; if (nextwrite > 20) cpi main0,42 brne PC+2 ; clr sts ;sts
nextwrite = 0; main0 nextwrite,main0 nextwrite+1,main1
; if (ac>0) ; result = 1; ;else ; result = 0; ; at this point, r2 is still cleared ; ; we need to do a 16-bit compare to set the final result
subi sbc brlt
result2,1 result3,r2 PC+2
inc
r2
;then make r2 positive
; from here r2 holds the output of the filter stage fi_0002a: ; ; ; ; ; ; ; ;
// // // // // // // //
now we can build a uart the data is delivered in ten bit chunks... in order, start bit (0) bit 0 ... bit 7 stop bit (1)
; some register assignments .def r_clock = r20 .def r_rx = r21 .def r_bit = r22 .def r_status = r23 ; ; ; // see what our state is lds lds lds lds ;
; ;
r_clock,clock r_rx,rx r_bit,bit r_status,status
;get clock and status and such
if (status & IDLE) sbrs r_status,idle jmp fi_0003 { status &= ~RXFLAG; cbr r_status,EXP2(rxflag)
// we're idling ;skip if clear
;clear rxflag bit
;
if (!result) // falling edge of start bit tst r2 ;result is still in r2 breq fi_0004 ; { ; status &= ~IDLE; // so we idle no longer cbr r_status,EXP2(idle) ; status |= START; // we're started sbr r_status,EXP2(start) ; bit = 0; // reset bit counter clr r_bit ; clock = 0; // and the clock count clr r_clock ; } fi_0004: ; // else we're still waiting for end of stop bit ; } jmp fi_0005 ; else fi_0003: ; { ; if (status & START) // aha, we got the falling edge sbrs r_status,start jmp fi_0005 ; { ; if ((clock <= spb/2) && (result)) // oops, false trigger...noise perhaps cpi r_clock,5 brge fi_0014 tst r2 brne fi_0014 ; { ; status &= ~START; cbr r_status,EXP2(start) ; status |= IDLE; // so drop back to idle mode sbr r_status,EXP2(idle) jmp fi_0007 ; } ; else fi_0014: ; { ; clock++; // otherwise, one more clock inc r_clock ; } fi_0007: ; if (clock == spb/2) // or are we now in mid start-bit cpi r_clock,4 brne fi_0006: ; { ; status &= ~START; cbr r_status,EXP2(start) ; status &= ~IDLE; cbr r_status,EXP2(idle) ; status |= RUN; // so now we're hot to trot sbr r_status,EXP2(run) ; clock = 0; // reset counter clr r_clock; ; } ; } fi_0006: jmp fi_0008 ; else fi_0005: ; { ; if (status & RUN) // we're reading data (allegedly) ; { sbrs r_status,run jmp fi_0009 ; if (clock < spb-1) // time for a sample? cpi r_clock,7 breq fi_0010 ; clock++; // not yet inc r_clock jmp fi_0011 ; else fi_0010: ; { ; if (bit != 8) // normal read cpi r_bit,8 breq fi_0012 ; { ; clock = 0; clr r_clock ; ; ; ; ;
rx = rx>>1; if (result) rx |= 0x80; else rx &= 0x7f; clc sbrc sec ror
;
r2,0
;skip if output was '1' ;else set carry ;and slide it into the rx byte
r_rx
bit ++; inc r_bit jmp fi_0013
; ; fi_0012: ; ; ; ; ; ; ; ; ;
} else { if (! result) // frame error { status |= FRAMERR; } else { status &= ~FRAMERR; } sbr r_status,EXP2(framerr) tst r2 brne PC+1 cbr r_status,EXP2(framerr)
;
bit = 0 clr r_bit status |= IDLE; sbr r_status,exp2(idle)
;
;
status |= RXFLAG; sbr r_status,exp2(rxflag)
;
status &= ~RUN; cbr r_status,exp2(run)
;
status &= ~START; cbr r_status,exp2(start)
; } ; } fi_0013: ; } fi_0011: ; } fi_0009: ; } fi_0008: ; ; output = (status<<8)+rx; ; return(output); sts sts sts sts ret
status,r_status clock,r_clock bit,r_bit rx,r_rx
;} break mul16: ; 16*16->32 bit multiply, signed ; code from Atmel appnote AVR201 ; multiplicands are in main1/2 and main3/4 clr muls movw mul movw mulsu sbc add adc adc mulsu sbc add adc adc
r2 main3,main1 result3:result2, r1:r0 main2,main0 result1:result0, r1:r0 main3,main0 result3,r2 result1,r0 result2,r1 result3,r2 main1,main2 result3,r2 result1,r0 result2,r1 result3,r2
; which should leave a nice 32-bit product in result ret mac16: ; 16*16->32 bit multiply and accumulate ; result0-3 += main0,1 * main2,3 clr r2 muls main3,main1 add result2,r0 adc result3,r1 mul main2,main0 add result0,r0 adc result1,r1 adc result2,r2 adc result3,r2 mulsu main3,main0 sbc result3,r2 add result1,r0 adc result2,r1 adc result3,r2 mulsu main1,main2 sbc result3,r2 add result1,r0 adc result2,r1 adc result3,r2 ret ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; the static data for the filter coefficients ; ; these are 16-bit binary fractions of the coefficients for a low pass filter ; there are two copies of the filter so we can emulate a circular buffer ; without having to test for end conditions hi1k2: .dw
0,84,0,-284,-691,-796,0,1992,4756,7209,8191,7209,4756,1992,0,-796,-691,-
.dw
0,84,0,-284,-691,-796,0,1992,4756,7209,8191,7209,4756,1992,0,-796,-691,-
284,0,84,0 284,0,84,0
;// a dll to decode an 8 bit audio data stream into its fsk ;// data symbols assuming 1200Hz = 0, 2200Hz = 1, 1200 bps ;// and a sample rate of either 7200 or 9600 ; ;// definitions of calls ;int filter (unsigned char thingy, int spb); ;#include "nbfsk.h" ;// uart variables ;#define IDLE 1 ;#define START 2 ;#define RUN 4 ;#define RXFLAG 8 ;#define FRAMERR 16 ;#define STOP 32 ; ;static int lo1k2[21] = { ; 0, // -0.00000010 ; 0, // -0.00000010 ; 189, // 0.00578410 ; 347, // 0.01061810 ; 0, // 0.00000010 ; -975, // -0.02977210 ; -1540, // -0.04701110 ; 0, // -0.00000010 ; 4119, // 0.12572310 ; 8829, // 0.26945810 ; 10922, // 0.33333310 ; 8829, // 0.26945810 ; 4119, // 0.12572310 ; 0, // -0.00000010 ; -1540, // -0.04701110 ; -975, // -0.02977210 ; 0, // 0.00000010 ; 347, // 0.01061810 ; 189, // 0.00578410 ; 0, // -0.00000010 ; 0}; // -0.00000010 ; ;static int hi1k2[21] = { ; 0, // 0.00000010 ; 84, // 0.00256410 ; 0, // 0.00000010 ; -284, // -0.00866910 ; -691, // -0.02110710 ; -796, // -0.02430910 ; 0, // -0.00000010 ; 1992, // 0.06080010 ; 4756, // 0.14517310 ; 7209, // 0.22001210 ; 8191, // 0.25000010 ; 7209, // 0.22001210 ; 4756, // 0.14517310 ; 1992, // 0.06080010 ; 0, // -0.00000010 ; -796, // -0.02430910 ; -691, // -0.02110710 ; -284, // -0.00866910 ; 0, // 0.00000010 ; 84, // 0.00256410 ; 0}; // 0.00000010 ; ;int filter (unsigned char thingy, int spb) ;{ ;int ac; ;short input; ;short output; ;char result; ; ;static short delay[5]; ;static short b[22]; ; ;static char rx = 0; ;static short status = 1; ;static int clock = 0; // counter for sample ;static int bit = 0; // bit counter ;int q; ; ; input = ((((short)thingy)-0x80)<<8); // upscale the sample ; ; // we delay the input samples_per_bit/2 samples... ; for (q=0; q<(spb/2+1); q++) ; delay[q] = delay[q+1]; ; ; // save new sample ; delay[spb/2] = input; ; ; // now we multiply todays sample with the delayed one ; ac = (int)delay[0]*(int)input*-1; ; ; // and finally, low pass filter the result ; // select filter depending on sample rate ; b[0] = ac>>15; ; ac = 0; ; if (spb < 7) ; { ; for (q=21; q>=0; q--) ; { ; ac += (int)b[q]*(int)lo1k2[q]; ; b[q+1] = b[q]; ; } ; } ; else ; { ; for (q=21; q>=0; q--) ; { ; ac += (int)b[q]*(int)hi1k2[q]; ; b[q+1] = b[q]; ; } ; } ; if (ac>0) ; result = 1; ; else ; result = 0; ; ; // now we can build a uart ; // the data is delivered in ten bit chunks... ; // in order, ; // start bit (0) ; // bit 0 ; // ... ; // bit 7 ; // stop bit (1) ; ; ; // see what our state is ; if (status & IDLE) // we're idling ; { ; status &= ~RXFLAG; ; if (!result) // falling edge of start bit ; { ; status &= ~IDLE; // so we idle no longer ; status |= START; // we're started ; bit = 0; // reset bit counter ; ; ; ; ; ; ; ; ;
clock = 0;
// and the clock count
} // else we're still waiting for end of stop bit } else { if (status & START) // aha, we got the falling edge { if ((clock <= spb/2) && (result)) // oops, false
trigger...noise perhaps ; ; ; ; ; ;
{
;
if (clock == spb/2)
; ; ; ; ; ; ; ; ; ;
{
status &= ~START; status |= IDLE;
// so drop back to idle mode
} else clock++;
//
otherwise, one more clock // or are we now in mid
start-bit status &= ~START; status &= ~IDLE; status |= RUN; clock = 0;
// so now we're hot to trot // reset counter
} } else { if (status & RUN)
// we're reading data
(allegedly) ; ; ;
{ if (clock < spb-1) clock++;
// time for a sample? // not
yet ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
http://avr-asm.tripod.com/callid.html (1 of 2)1/20/2009 9:19:20 PM
else { if (bit != 8) // normal read { clock = 0; rx = rx>>1; if (result) rx |= 0x80; else rx &= 0x7f; bit ++; } else { if (! result) // frame error { status |= FRAMERR; } else { status &= ~FRAMERR; } status |= IDLE; status |= RXFLAG; status &= ~RUN; status &= ~START; } } } } } output = (status<<8)+rx;
16 BIT MATH (AVR 202)
; return(output); ;} ; ;int _stdcall NbFskDecodeBytes (unsigned char * audio, ; long length, ; unsigned char * decode, ; int samples_per_bit) ;{ ; // this routine takes a block of 8 bit audio data and decodes it ; // using the bel202 fsk standard ; // only bytes which decode without a frame error are saved in 'decode' ; // the calling routine is responsible for ensuring that the decode ; // buffer is sufficiently large - there are about 60-80 samples per ; // byte of output ; // if 'clear' is set then the filter buffer is cleared before use ; ; ;int q; ;int bytes = 0; ;struct rec1 { ; char rx; ; char status; ;} rec; ;union { ; short rex; ; rec1 rec; ;} r; ; ; for (q=0; q
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/callid.html (2 of 2)1/20/2009 9:19:20 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DTMF GENERATOR (AVR 314) HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
; *************************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR314 ;* File Name : "dtmf.asm" ;* Title : DTMF Generator ;* Date : 00.06.27 ;* Version : 1.1 ;* Target MCU : Any AVR with SRAM, 8 I/O pins and PWM ;* ;* DESCRIPTION ;* This Application note describes how to generate DTMF tones using a single ;* 8 bit PWM output. ;* ; ***************************************************************************
DIV 3216
.include "4414def.inc"
FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII
; ************************************************************************** ; REGISTERS ; ************************************************************************** .def XL_Tmp = r1 ; low part temporary register .def XH_Tmp = r2 ; high part temporary register
HX2ASC AVG8 222 FFT7
; Number of Element (Position) in LUT in Extended format .def XL_LUTbExt = r3 ; number of LUT-Element of frequency a (low byte)
COPY 102 LPM 108 EPROM 100
.def XH_LUTbExt = r4 ; number of LUT-Element of frequency a (high byte) .def XL_LUTaExt = r5 ; number of LUT-Element of frequency b (low byte) .def XH_LUTaExt = r6 ; number of LUT-Element of
SER EPROM DFLASH AT45
frequency b (high byte)
FLASH CARD
.def OCR_RelValb = r7 ; low frequency reload value to
VFX SMIL
be written to OCR
VFX MEM
be written to OCR
.def OCR_RelVala = r8 ; High frequency reload value to
SORT 220 .def x_SWa = r9 ; step width in LUT to get high CRC 236
frequency .def x_SWb = r10 ; step width in LUT to get low
XMODEM REC UART 304
frequency
UART 305
.def count = r18 ; temporary counter register .def tmp = r16 ; temp register
UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128
.def input = r17 ; input from portB ; ************************************************************************** ; ************************************************************************** .equ Xtal = 8000000 ; system clock frequency .equ prescaler = 1 ; timer1 prescaler .equ N_samples = 128 ; Number of samples in lookup table .equ Fck = Xtal/prescaler ; timer1 working frequency .equ delaycyc = 10 ; port B setup delay cycles ; ************************************************************************** ; PROGRAM START - EXECUTION STARTS HERE ; ************************************************************************** .cseg .org $0 rjmp start ; Reset handler .org OVF1addr rjmp tim1_ovf ; Timer1 overflow Handle
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
; ************************************************************************** ; Interrupt timer1 ; ************************************************************************** tim1_ovf: push tmp ; Store temporary register in tmp,SREG push tmp ; Store status register push ZL push ZH ; Store Z-Pointer push r0 ; Store R0 Register
MUX 242 ;high frequency mov XL_Tmp,XL_LUTaExt mov XH_Tmp,XH_LUTaExt add XL_LUTaExt,x_SWa clr tmp ; (tmp is cleared, but not the carry flag) adc XH_LUTaExt,tmp ; Refresh pointer for the next
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8
sample rcall getsample ; read from Sin Wave Sample Table mov OCR_RelVala,r0 ; OCR_RelVala = high frequency value
ALM CLK CLOCK 8564
;low frequency mov XL_Tmp,XL_LUTbExt mov XH_Tmp,XH_LUTbExt add XL_LUTbExt,x_SWb clr tmp ; (tmp is cleared, but not the carry flag) adc XH_LUTbExt,tmp ; refresh pointer for the next
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
sample rcall getsample ; read from Sin Wave Sample Table mov OCR_RelValb,r0 ; OCR_RelValb = low frequency value
PWM 10K ENCODE
; scale amplitude ldi tmp,2 add OCR_RelValb,tmp lsr OCR_RelValb lsr OCR_RelValb ; divide 4 and round off sub r0,OCR_RelValb ; 4/4 - 1/4 = 3/4 mov OCR_RelValb,r0 ; now OCR_RelValb has the right
STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK amplitude
clr out mov add out
tmp OCR1AH,tmp tmp,OCR_RelVala tmp,OCR_RelValb OCR1AL,tmp ; send the sum of the two amplitudes to
PWM pop r0 ; Restore R0 Register pop ZH pop ZL ; Restore Z-Pointer pop tmp out SREG,tmp ; Restore SREG pop tmp ; Restore temporary register; reti ;********************************* ; RESET Interrupt ;********************************* start: sbi DDRD,PD5 ; Set pin PD5 as output ldi tmp,low(RAMEND) out SPL,tmp ldi tmp,high(RAMEND) out SPH,tmp ; Initialize Stackpointer ;Initialization of the registers clr XL_LUTaExt clr XH_LUTaExt clr XL_LUTbExt clr XH_LUTbExt ; Set both table ponters to 0x0000 ;enable timer1 interrupt ldi tmp,(1< out TIMSK,tmp ; Enable Timer1_ovf interrupt ;set timer1 PWM mode ldi tmp,(1< out TCCR1A,tmp ; 8 bit PWM not reverse (Fck/510) ldi tmp,(1< out TCCR1B,tmp ; prescaler = 1 sei ; Enable interrupts ; ************************************************************************** ; MAIN ; Read from portB (eg: using evaluation board switch) which ; tone to generate, extract mixing high frequency ; (column) and low frequency (row), and then ; fix x_SWa and x_SWb ; row -> PINB high nibble ; column -> PINB low nibble ; ************************************************************************** main: ;high frequency (Esteem only high nibble that is row) ;PB_High_Nibble: ldi tmp,0x0F out DDRB,tmp ; High nibble Input / Low nibble. Outp. ldi tmp,0xF0 out PORTB,tmp ; High nibble PullUp / Low nibble Zero Outp. rcall delay clr count in input,PINB main10: inc count lsl input brcc main20 ldi tmp,4 cp count,tmp brne main10 clr x_SWb clr count rjmp main30 main20: dec count ldi ZL,low(frequencyL*2) ldi ZH,high(frequencyL*2) add ZL,count clr tmp adc ZH,tmp lpm mov x_SWb,r0 ; this is low frequency x_SW clr count ;low frequency ;PB_Low_Nibble: main30: ldi tmp,0xF0 out DDRB,tmp ; High nibble. Outp. / Low nibble Input ldi tmp,0x0F out PORTB,tmp ; High nibble Zero Outp. / Low nibble PullUp rcall delay in input,PINB swap input main40: inc count lsl input brcc main50 ldi tmp,4 cp count,tmp brne main40 clr x_SWa rjmp main main50: ; there is a zero bit in count-1 position dec count ldi ZL,low(frequencyH*2) ldi ZH,high(frequencyH*2) add ZL,count clr tmp adc ZH,tmp lpm mov x_SWa,r0 ; this is high frequency x_SW rjmp main
;****************** DELAY *********************************** ; **************************************************************** delay: ldi tmp,delaycyc loop: dec tmp brne loop ret
;****************** GET SAMPLE ****************************** ; **************************************************************** getsample: ldi tmp,0x0f and XH_Tmp,tmp ; ROUND - add four ldi tmp,4 add XL_Tmp,tmp clr tmp adc XH_Tmp,tmp ; shift (divide by eight): lsr XH_Tmp ror XL_Tmp lsr XH_Tmp ror XL_Tmp lsr XH_Tmp ror XL_Tmp ldi tmp,0x7f and XL_Tmp,tmp ; module 128 (samples number sine table) ldi ZL,low(sine_tbl*2) ldi ZH,high(sine_tbl*2) add ZL,XL_Tmp clr tmp adc ZH,tmp ; Z is a pointer to the correct ; sine_tbl value lpm ret ;*************************** SIN TABLE ************************************* ; Samples table : one period sampled on 128 samples and ; quantized on 7 bit ; ****************************************************************************** sine_tbl: .db 64,67 .db 70,73 .db 76,79 .db 82,85 .db 88,91 .db 94,96 .db 99,102 .db 104,106 .db 109,111 .db 113,115 .db 117,118 .db 120,121 .db 123,124 .db 125,126 .db 126,127 .db 127,127 .db 127,127 .db 127,127 .db 126,126 .db 125,124 .db 123,121 .db 120,118 .db 117,115 .db 113,111 .db 109,106 .db 104,102 .db 99,96 .db 94,91 .db 88,85 .db 82,79 .db 76,73 .db 70,67 .db 64,60 .db 57,54 .db 51,48 .db 45,42 .db 39,36 .db 33,31 .db 28,25 .db 23,21 .db 18,16 .db 14,12 .db 10,9 .db 7,6 .db 4,3 .db 2,1 .db 1,0 .db 0,0 .db 0,0 .db 0,0 .db 1,1 .db 2,3 .db 4,6 .db 7,9 .db 10,12 .db 14,16 .db 18,21 .db 23,25 .db 28,31 .db 33,36 .db 39,42 .db 45,48 .db 51,54 .db 57,60 ;******************************* x_SW *********************************** ;Table of x_SW (excess : x_SW = ROUND(8*N_samples*f*510/ Fck) ; ************************************************************************** ;high frequency (coloun) ;1209hz ---> x_SW = 79 ;1336hz ---> x_SW = 87 ;1477hz ---> x_SW = 96 ;1633hz ---> x_SW = 107 frequencyH: .db 107,96 .db 87,79 ;low frequency (row) ;697hz ---> x_SW = 46 ;770hz ---> x_SW = 50 ;852hz ---> x_SW = 56 ;941hz ---> x_SW = 61 frequencyL: .db 61,56 .db 50,46
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will http://avr-asm.tripod.com/dtmf314.html (1 of 2)1/20/2009 9:20:00 PM
16 BIT MATH (AVR 202)
occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dtmf314.html (2 of 2)1/20/2009 9:20:00 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SIX CHANNEL PWM FOR 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD
; *************************************************************************** ; ; File Name :'pwm6.asm" ; Title :6 chanel Phase and Frequency Correct PWM ; Date :2003.11.15. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.11.15 VFX Creation ; ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* Oscillator: f=external, 16.0000 MHz (T=62.5ns) == SYSCLK ;* ; *************************************************************************** ;* Const Def
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC
; ************************************************************************** ;* Hardware Def. ;
UART 304 UART 305 UART 128 UART BUFF
; *************************************************************************** ;**** VARIABLES .DSEG
USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128
; *************************************************************************** .ESEG ; *************************************************************************** ;**** I N T E R R U P T S ;**** ; *************************************************************************** .CSEG
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
; ************************************************************************ ; ************************************************************************ ;** PWM6_Init ;** ;** Timer1 & Timer3 setup ; PWM6_Init: ; ldi R16,0b00010000 ICES3 – WGM33 WGM32 CS32 CS31 CS30 ; out TCCR1B,R16 ; sts TCCR3B,R16
;ICNC3 ;Timers Stop
IRD 410 clr sts sts out out sts
R16 TCNT3H,R16 TCNT3L,R16 TCNT1H,R16 TCNT1L,R16 TCCR3C,R16
KBD PS2
sts
TCCR1C,R16
KBD PC/128
out out out out sts sts
OCR1AH,R16 OCR1AL,R16 OCR1BH,R16 OCR1BL,R16 OCR1CH,R16 OCR1CL,R16
sts sts sts sts sts sts
OCR3AH,R16 OCR3AL,R16 OCR3BH,R16 OCR3BL,R16 OCR3CH,R16 OCR3CL,R16
in andi out
R16,PORTB R16,0b00011111 PORTB,R16
in ori out
R16,DDRB R16,0b11100000 DDRB,R16
in andi out
R16,PORTE R16,0b11000111 PORTE,R16
in ori out
R16,DDRE R16,0b00111000 DDRE,R16
;PWM3..5 as
ldi
R16,0x03
;PWM width
sts ldi sts
ICR3H,R16 R16,0xFF ICR3L,R16
ldi out ldi out
R16,0x03 ICR1H,R16 R16,0xFF ICR1L,R16
in andi out
R16,TIMSK R16,0b11000011 TIMSK,R16
;Interrupt
ldi
R16,0b00000000
;TICIE3
sts
ETIMSK,R16
ldi out
R16,0b10101000 TCCR1A,R16
;COM1A1
sts
TCCR3A,R16
;COM3A1
ldi out sts
R16,0b00010001 TCCR1B,R16 TCCR3B,R16
;Start PWM
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
;Counter=0
;FOC3A
FOC3B FOC3C
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
;PWM = 0%
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
;PWM0..2 as
output
AVR BOOK
output
= 10 bit
disabled
OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C
COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30
ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/pmw6ch.html (1 of 2)1/20/2009 9:20:33 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/pmw6ch.html (2 of 2)1/20/2009 9:20:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
10K POT AND PWM ROUTINE FOR 8535 HOME RETRO_DAN ASM FORUM
A 10K Ohm potentiometer. The ADC directly controls the PWM function.
ASM MATH TUTORIAL #1
;----------------------------------; PWM FOR 8535 ;----------------------------------.include "m8535def.inc"
TUTORIAL #2 TUTORIAL #3 MATH 200
; Set the assembler program counter to point to program
MATH 200b MATH 201
code space .org 0x0000
;CSEG
MATH 202 MATH 32X
; Set the assembler program counter to point to PWM intrrupt handler
MATH YX
.org ADCCaddr
DIV16 XX
; Set the ADC intrrupt vector rjmp load_PWM ; ADCaddr also Defined as 0x00E
DIV 24 24 DIV 3216
; Set the reset vector rjmp INIT_MCU
FLOAT 128 SQRT16
; Microcontroller initialization sequence INIT_MCU: ldi r16, low(RAMEND) out SPL, r16 ldi r16, high(RAMEND) out SPH, r16
MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
; Initialize the ADC A_D: ; Set up Analog to Digital ldi r16, 0b01000001 ; AVCC REF, ADC channel 1 out ADMUX, r16 ldi r16, 0b10101111 ; ENA ADC, Auto Trigger, ADC
AVG8 222 FFT7 COPY 102 LPM 108
INT ENA, Clock div by 128 out ADCSRA, r16 sbi ADCSRA, ADSC
EPROM 100
; Start ADC conversions
SER EPROM Set_IO_PORTS: ; Set up PORTB for PWM output control ldi r16, 0b00100000 ; Sets PORTB for all inputs,
DFLASH AT45 FLASH CARD
OC1A (PORTB, Pin 5) out DDRB, r16 ldi r16, 0b00000000
VFX SMIL VFX MEM
resistors out PORTB, r16
SORT 220 CRC 236
; Initialize timer/counter 1 for 10 bit FAST PWM ; 10 bit "Fast PWM" (Mode 7), TOP = 0x3FF, Update OCR1A
XMODEM REC UART 304 UART 305
when TCNT = TOP ldi r16, 0b10000011 ; Clear AC1A on comp. match, WGM11 = 1, WGM10 = 1 out TCCR1A, r16 ldi r16, 0b00001001
UART 128 UART BUFF
; Disable internal pull up
; WGM13 = 0, WGM12 = 1, No CLK
prescaling
USB 232
out TCCR1B, r16
AVR ISP
sei
; Enable global intrrupts
ISP 2313 ; Main program loop. -----> Just a very tight loop main: ; Get the current ADC conversion data rjmp main
ISP 1200 AVR SPI I2C 300 I2C 302
; PWM control intrrupt handler load_PWM: ; Get the current ADC conversion data in r17, ADCL ; Must be read first!!! in r18, ADCH ; Output the current ADC conversion in TCNT1 for
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
PWM out OCR1AH, r18 out OCR1AL, r17 reti
DALLAS CRC ETHNET 8019
; Must be written first
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
Programming the AVR Microcontrollers in Machine Language
MUX 242 KBD PS2
AVR << Prev | Ring Hub | Join | Rate| Next >>
KBD PC/128 PS2 EMU © WebRing Inc.
BOOT MG8
Search
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/pwm10k.html (1 of 2)1/20/2009 9:21:05 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/pwm10k.html (2 of 2)1/20/2009 9:21:05 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ASM ENCODER HOME RETRO_DAN I've been using this routine for ages, slight modification depending on the number of encoders and values I assign changed like a keyscan routine which is passed on to another routine to deal with.
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2
It has every condition of the encoder accounted for, including invalid switch patterns which I happen from time to time.
TUTORIAL #3 MATH 200
It also can be polled from a main subroutine at a frequency of around 1ms but accuracy of timing is not important and never stays in there looping under any condition so fits well into a multitasking environment, so far I've never had any problems with it.
MATH 200b MATH 201 MATH 202 MATH 32X MATH YX
Ax, Bx and so on I use for R16, R17 change them to whatever you like, the variables used are below
DIV16 XX DIV 24 24
;;variables local Ax,Bx,Cx,Dx ; ;; global encoder1,scansqn,debounceon ; ;; encoder2,encoder3
DIV 3216 FLOAT 128
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; clr Bx ;;encoder1 left/right clr cx sbic PINC,PC_En1a ldi Bx,0x01 sbic PINC,PC_En1b ldi Cx,0x01 lds Ax,Encoder1 rcall EncoderSub brcs StoreEn1 ;;encoder 1 activated sts Encoder1,Ax
SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
clr clr sbic ldi sbic ldi lds rcall brcs sts
Bx cx PINC,PC_En2a Bx,0x01 PINC,PC_En2b Cx,0x01 Ax,Encoder2 EncoderSub StoreEn2 Encoder2,Ax
;;encoder2 left/right
clr clr sbic ldi sbic ldi lds rcall brcs sts
Bx cx PINC,PC_En3a Bx,0x01 PINC,PC_En3b Cx,0x01 Ax,Encoder3 EncoderSub StoreEn3 Encoder3,Ax
;;encoder3 left/right
clr clr sbic ldi sbic ldi lds rcall brcs sts
Bx cx PINC,PC_En4a Bx,0x01 PINC,PC_En4b Cx,0x01 Ax,Encoder4 EncoderSub StoreEn4 Encoder4,Ax
;;encoder3 left/right
rjmp
PushButtons
;;encoder 2 activated
VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
;;encoder 3 activated
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
;;encoder 3 activated
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
StoreEn1: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x29 Bx,0 Ax,0x28 Bx Encoder1,Bx KeyRegister
StoreEn2: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x2B ;;left value Bx,0 Ax,0x2A ;;right value Bx Encoder2,Bx KeyRegister
StoreEn3: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x2D ;;left value Bx,0 Ax,0x2C ;;right value Bx Encoder3,Bx KeyRegister
StoreEn4: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x2F ;;left value Bx,0 Ax,0x2E ;;right value Bx Encoder4,Bx KeyRegister
;;left value ;;right value
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 Encodersub: ldi ldi add clr adc ijmp EncoderTable: rjmp rjmp rjmp rjmp rjmp
PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Zl,low(EncoderTable) Zh,High(EncoderTable) Zl,ax Dx Zh,Dx
Encoder_1 Encoder_2 Encoder_3 Encoder_4 Encoder_5
;;from idle ;;clock wise point 1 ;;clockwise point 2 ;;anticlockwise point 1 ;;anticlockwise point 2
Encoder_1: sbrs rjmp sbrc rjmp ldi rjmp
Bx,0 test_cw Cx,0 NoEncoderChange Ax,0x01 ;;clockwise point 1 StoreEncoder
test_cw: sbrs rjmp ldi rjmp
Cx,0 NoEncoderChange Ax,0x03 ;;anti clockwise point 1 StoreEncoder
Encoder_2: sbrs rjmp sbrs rjmp Invalid_Switch: ldi rjmp
Encoder_2a: sbrc rjmp ldi rjmp Encoder_3: sbrs rjmp sbrs rjmp
Bx,0 Encoder_2a Cx,0 NoEncoderChange
;;no change
Ax,0x00 StoreEncoder
Cx,0 Invalid_Switch Ax,0x02 StoreEncoder
;;move to point 2
Bx,0 NoEncoderChange Cx,0 NoEncoderChange ;;;;valid clockwise turn Bx,0x01 EncoderActivate
ldi rjmp ;;;;;;;;;; Encoder_4: sbrs Cx,0 rjmp Encoder_4a sbrs Bx,0 rjmp NoEncoderChange rjmp Invalid_Switch Encoder_4a: sbrc Bx,0 rjmp Invalid_Switch ldi Ax,0x04 rjmp StoreEncoder
;;no change
;;move to point 2
Encoder_5: sbrs rjmp sbrs rjmp
Bx,0 NoEncoderChange Cx,0 NoEncoderChange ;;;;valid anticlockwise turn clr Bx rjmp EncoderActivate ;;;;;;;;;;;;;;;;;;;;;;;;;;;; StoreEncoder: clc ret NoEncoderChange: clc ret EncoderActivate: sec ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/encode.html (1 of 2)1/20/2009 9:21:38 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/encode.html (2 of 2)1/20/2009 9:21:38 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
STH-11 CONVERSION ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
; *************************************************************************** ; ; File Name :'conv.asm" ; Title :STH-11 konverzios rutinok ; Date :2002.11.27. ; Version :1.0.0 ; Support telephone :+36-70-333-4034 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2002.11.27. VFX Creation ; ; ; ***************************************************************************
AVG8 222 ;********************************************** .DSEG Temperature: .byte 2 Humidity: .byte 2
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
.CSEG ; *************************************************************************** ; Public Parts: ; ; CaltTemp - Homerseklet kiszamitasa A valtozat ; Calc_Temp B valtozat ; CalcHum - Paratartalom kiszamitasa ; ; *************************************************************************** ;* Const Def ; ; ; ; ; ************************************************************************** ;* Hardware Def.
ISP 2313 ISP 1200
.include "mat32.asm" .include "8515DEF.INC"
AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA
; ************************************************************************** ;** Homersekletet ASCIIban kiirja a ASCIIBuf-ba, 0-val lezarva ; PrintTemp: lds mant1,Temperature+0 lds mant1m,Temperature+1 clr mant1h clr mant1hh rcall ULTOA ret
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
; ************************************************************************** ;* Y = mx+b fugveny, konstansok a programmemoriaban m,b sorrenden ;* Z - konstans tabla elso eleme ;* ACC1 = eredmeny ; LinearF: lpm adiw ZL,1 mov mant2,R0 lpm adiw ZL,1 mov mant2m,R0 lpm adiw ZL,1 mov mant2h,R0 lpm adiw ZL,1 mov mant2hh,R0 push ZL push ZH rcall UMUL pop ZH pop ZL
90 DAYS
lpm adiw mov lpm adiw mov lpm adiw mov lpm adiw mov push push rcall pop pop ret
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
ZL,1 mant2,R0 ZL,1 mant2m,R0 ZL,1 mant2h,R0 ZL,1 mant2hh,R0 ZL ZH ADD32 ZH ZL
; ************************************************************************** ;* Homerseklet szamitas ;* ;* ;* Y = m * x + b ;* 10T = 0.1 * x - 400 /*65536
TRC:
.db 0x9A,0x19,0x00,0x00 ;m =
0x00001999 vagy 199A .db 0x00,0x00,0x70,0xFF ;b = 0xFF700000 Calc_Temp: clr clr
mant1h mant1hh
ldi ldi
ZL,Low(TRC*2) ZH,High(TRC*2)
rcall sts sts ret
LinearF Temperature+0,mant1h Temperature+1,mant1hh
;ACC1 = ADC
value 0..16383
YCalcEnd:
;konstansok
; ************************************************************************** ;* Paratartalom szamitas ;* ;* Adatlap alpjan 12 bitre ;* x - paratartalom binaris erteke (ADC) 0..4095 ;* T - homerseklet kiszamolt erteke C-ban ;* ; RHlin = -2.8*10^-6*x^2 + 4.05*10^-2 * x -4 ; RHtrue= (T-25)*(10^-2 + 8*10^-5*x) +RHlin ; ;mindket egyenletet 10zel felszorozzuk a kijelzes miatt (T erteket nem az eleve 10T) ; ;Resz szamitasok: ; a, (T-250) - sub32 ; b, ((10^-1 + 8*10^-4*x)) - linf ; c, 4.05*10^-1 * x - 40 - linf ; d, -2.8*10^-5*x^2 - negyzet eftedi ; ; e, a*b ; ; RHtrue=a*b+c+d ; ; ;* ;* ;* ;*
Y = m * x + b 'B' = 0.0008 * x + 0.1
PartB: 0x00000034
.db 0x34,0x00,0x00,0x00 ;m =
0.0008 *65536 .db 0x9A,0x19,0x00,0x00 ;b = 0x0000199A
0.1 * 65536 ;* ;*
Y = m * x + b 'C' = 0.405 * x - 40
PartC: 0x000067AE
.db 0xAE,0x67,0x00,0x00 ;m =
0.405 *65536 .db 0x00,0x00,0xD8,0xFF ;b = 0xFFD80000
-
40 * 65536
CalcHum: mov mov
R6,mant1 R7,mant1m
;
paratartalmat elmentjuk ; homerseklet mar kiszamolva memoriban van clr clr
mant1h mant1hh
;ACC1 = ADC
ldi
ZL,Low(PartB*2)
;konstansok
ldi rcall
ZH,High(PartB*2) LinearF
;ACC1-ben a
value 0..4095
a 'B' szamitashoz
'B' szamitas eredmenye ;itt az 'A' szamitasa jon ; T-250 lds lds clr clr
mant2,Temperature+0 mant2m,Temperature+1 mant2h mant2hh
;ACC2
subi sbci sbci sbci
mant2,250 mant2m,0 mant2h,0 mant2hh,0
;levontunk
rcall
UMUL
;acc1 = E =
push push push push
mant1 mant1m mant1h mant1hh
mov mov clr clr ldi
mant1,R6 mant1m,R7 mant1h mant1hh ZL,Low(PartC*2)
ldi rcall
ZH,High(PartC*2) LinearF
pop pop pop pop rcall
mant2hh mant2h mant2m mant2 add32
push push push push
mant1 mant1m mant1h mant1hh
mov mov clr clr
mant1,R6 mant1m,R7 mant1h mant1hh
mov mov clr clr rcall
mant2,R6 mant2m,R7 mant2h mant2hh UMUL
ldi ldi ldi ldi
mant2,0xD6 mant2m,0x01 mant2h,0x00 mant2hh,0x00
rcall
UMUL
clr mov mov mov
mant2hh mant2h,mant1hh mant2m,mant1h mant2,mant1m
pop pop pop pop rcall
mant1hh mant1h mant1m mant1 sub32
homerseklet
250-t
A * B
/*65536
;x erteke
;konstansok
a 'C' szamitashoz ;ACC1-ben a
'C' szamitas eredmenye
;x erteke
;x erteke
;ACC1 = X^2
;2.8*10^-5
* 65536*256
;256-tal
osztjuk az eredmenyt
;ACC1-ben a vegeredmeny sts sts
Humidity+0,mant1h Humidity+1,mant1hh
;65536 valo
szorzas miatt csak ; a felo 16 bit kell ret
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
Search
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K Inhttp://avr-asm.tripod.com/sth11.html (1 of 2)1/20/2009 9:22:12 PM
16 BIT MATH (AVR 202)
System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/sth11.html (2 of 2)1/20/2009 9:22:12 PM
The AVR Assembler Site HOME RETRO_DAN ASM FORUM ASM MATH
Welcome to AVR Assembler Site ASSEMBLY LANGUAGE:
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
The Mnemonic Representation of Machine Code. Assembly Language remains in use because of its close relationship to the underlying machine. It is used by those who need to compress programs into the smallest memory space and have it excecute as fast and efficiently as possible. It can be a difficult medium in which to work. Many can forget that whether done by man or compiler, all computer languages must be translated into machine code before they can run in hardware.
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
Submit New Routines, Updates, Bug Reports to AVR Assembler Forum at: http://avr.x. am
The AVR is a family of RISC microcontrollers from Atmel. The AVR architecture, first conceived by two electronic engineering students at the Norwegian Institute of Technology (NTH), has been refined and developed by Atmel Norway, in a division founded by the chip's architects.
The AVR architects, Vergard Wollan and Alf-Egil Bogen. Bogen's 1992 NTH thesis was titled: High Speed Analog to Digital Converters in CMOS.
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
Most high-level languages for the AVR core accomplish this by translating programs into Assembler Instructions first. The resultant Assembler Program is then converted to machinecode instructions. The process may be automated and appear transparent to the programmer. This is how the C compilers work.
A RetroDan (HWMNBN) Site
THE TWO-PASS ASSEMBLER
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
Since assembly language statements have a one-to-one correspondence with binary instructions it seems only logical to simply translate assembly instructions directly into binary machine code, one-ata-time. This method does not work due to forward references and jumps to lables that have not been defined yet. This is the reason most assemblers are the two-pass type.
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
The primary function of pass-one is to build up a symbol table that contain all the constants and labels along with their values. The second-pass then uses this symbol table to create the binary machine code.
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK Programming the AVR Microcontrollers in Machine Language
CLOCK 8564 90 DAYS DELAYS CALL ID
AVR << Prev | Ring Hub | Join | Rate| Next >>
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal
http://avr-asm.tripod.com/ (1 of 2)1/20/2009 8:32:57 PM
The AVR Assembler Site
architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
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The AVR Assembler Site
The AVR Assembler Site HOME RETRO_DAN ASM FORUM ASM MATH
Welcome to AVR Assembler Site ASSEMBLY LANGUAGE:
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
The Mnemonic Representation of Machine Code. Assembly Language remains in use because of its close relationship to the underlying machine. It is used by those who need to compress programs into the smallest memory space and have it excecute as fast and efficiently as possible. It can be a difficult medium in which to work. Many can forget that whether done by man or compiler, all computer languages must be translated into machine code before they can run in hardware.
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
Submit New Routines, Updates, Bug Reports to AVR Assembler Forum at: http://avr.x. am
The AVR is a family of RISC microcontrollers from Atmel. The AVR architecture, first conceived by two electronic engineering students at the Norwegian Institute of Technology (NTH), has been refined and developed by Atmel Norway, in a division founded by the chip's architects.
The AVR architects, Vergard Wollan and Alf-Egil Bogen. Bogen's 1992 NTH thesis was titled: High Speed Analog to Digital Converters in CMOS.
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
Most high-level languages for the AVR core accomplish this by translating programs into Assembler Instructions first. The resultant Assembler Program is then converted to machinecode instructions. The process may be automated and appear transparent to the programmer. This is how the C compilers work.
A RetroDan (HWMNBN) Site
THE TWO-PASS ASSEMBLER
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
Since assembly language statements have a one-to-one correspondence with binary instructions it seems only logical to simply translate assembly instructions directly into binary machine code, one-ata-time. This method does not work due to forward references and jumps to lables that have not been defined yet. This is the reason most assemblers are the two-pass type.
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
The primary function of pass-one is to build up a symbol table that contain all the constants and labels along with their values. The second-pass then uses this symbol table to create the binary machine code.
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK Programming the AVR Microcontrollers in Machine Language
CLOCK 8564 90 DAYS DELAYS CALL ID
AVR << Prev | Ring Hub | Join | Rate| Next >>
DTMF 314 PWM 6CH PWM 10K
© WebRing Inc.
Search
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal
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The AVR Assembler Site
architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/ O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
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MULTIPLY & DIVIDE (AVR 200)
The AVR Assembler Site
MULTIPLY & DIVIDE (AVR 200) HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202
;**** A P P L I C A T I O N
N O T E
A V R 2 0 0
************************ ;* ;* Title: Multiply and Divide Routines ;* Version: 1.1 ;* Last updated: 97.07.04 ;* Target: AT90Sxxxx (All AVR Devices) ;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application Note lists subroutines for the following ;* Muliply/Divide applications: ;* ;* 8x8 bit unsigned ;* 8x8 bit signed ;* 16x16 bit unsigned ;* 16x16 bit signed ;* 8/8 bit unsigned ;* 8/8 bit signed ;* 16/16 bit unsigned ;* 16/16 bit signed ;* ;* All routines are Code Size optimized implementations ;*; *************************************************************************** .include "1200def.inc"
DEC ASCII
rjmp
RESET
;reset handle
INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; *************************************************************************** ;* ;* "mpy8u" - 8x8 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two register variables mp8u and mc8u. ;* The result is placed in registers m8uH, m8uL ;* ;* Number of words :9 + return ;* Number of cycles :58 + return ;* Low registers used :None ;* High registers used :4 (mp8u,mc8u/m8uL,m8uH,mcnt8u) ;* ;* Note: Result Low byte and the multiplier share the same register. ;* This causes the multiplier to be overwritten by the result. ;* ; *************************************************************************** ;***** Subroutine Register Variables
UART 305 UART 128
.def .def .def .def .def
UART BUFF USB 232 AVR ISP ISP 2313
mc8u mp8u m8uL m8uH mcnt8u
=r16 =r17 =r17 =r18 =r19
;multiplicand ;multiplier ;result Low byte ;result High byte ;loop counter
;***** Code
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
byte
DALLAS-1W
byte
mpy8u: ldi lsr
clr m8uH mcnt8u,8 mp8u
m8u_1: add
brcc m8u_2 m8uH,mc8u
m8u_2:
ror
;
;carry set add multiplicand to result High
m8uH
;rotate right result High
ror
m8uL
;rotate right result L byte and
dec brne ret
mcnt8u m8u_1
;decrement loop counter ;if not done, loop more
DALLAS CRC ETHNET 8019
;clear result High byte ;init loop counter ;rotate multiplier
multiplier
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; *************************************************************************** ;* ;* "mpy8s" - 8x8 Bit Signed Multiplication ;* ;* This subroutine multiplies signed the two register variables mp8s and ;* mc8s. The result is placed in registers m8sH, m8sL ;* The routine is an implementation of Booth's algorithm. If all 16 bits ;* in the result are needed, avoid calling the routine with ;* -128 ($80) as multiplicand ;* ;* Number of words :10 + return ;* Number of cycles :73 + return ;* Low registers used :None ;* High registers used :4 (mc8s,mp8s/m8sL,m8sH,mcnt8s) ;* ; ***************************************************************************
CLOCK 8564 ;***** Subroutine Register Variables
90 DAYS DELAYS
PWM 6CH
.def .def .def .def .def
PWM 10K
;***** Code
CALL ID DTMF 314
mc8s mp8s m8sL m8sH mcnt8s
=r16 =r17 =r17 =r18 =r19
;multiplicand ;multiplier ;result Low byte ;result High byte ;loop counter
mpy8s:
sub
m8sH,m8sH
;clear result High byte and
ldi m8s_1: add
mcnt8s,8 brcc m8s_2 m8sH,mc8s
;init loop counter ;if carry (previous bit) set ; add multiplicand to result
m8s_2: sub
sbrc mp8s,0 m8sH,mc8s
;
;if current bit set subtract multiplicand from
asr ror
m8sH m8sL
;shift right result High byte ;shift right result L byte and
dec brne ret
mcnt8s m8s_1
;decrement loop counter ;if not done, loop more
ENCODE STH-11
carry
ATMEL CORP AVR BUTTERFLY
High byte
AVR BOOK result High
multiplier
; *************************************************************************** ;* ;* "mpy16u" - 16x16 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two 16-bit register variables ;* mp16uH:mp16uL and mc16uH:mc16uL. ;* The result is placed in m16u3:m16u2:m16u1:m16u0. ;* ;* Number of words :14 + return ;* Number of cycles :153 + return ;* Low registers used :None ;* High registers used :7 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/ m16u1,m16u2, ;* m16u3,mcnt16u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def .def
mc16uL mc16uH mp16uL mp16uH m16u0 m16u1 m16u2 m16u3 mcnt16u
=r16 =r17 =r18 =r19 =r18 =r19 =r20 =r21 =r22
;multiplicand low byte ;multiplicand high byte ;multiplier low byte ;multiplier high byte ;result byte 0 (LSB) ;result byte 1 ;result byte 2 ;result byte 3 (MSB) ;loop counter
clr
m16u3
;clear 2 highest bytes of
;***** Code mpy16u: result clr ldi lsr ror m16u_1: add
m16u2 mcnt16u,16 mp16uH mp16uL
;init loop counter
brcc noad8 m16u2,mc16uL
;if bit 0 of multiplier set ;add multiplicand Low to byte 2 of
m16u3,mc16uH
;add multiplicand high to byte 3 of
noad8: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
dec brne ret
mcnt16u m16u_1
;decrement loop counter ;if not done, loop more
res adc res m16u3
multiplier High multiplier Low
; *************************************************************************** ;* ;* "mpy16s" - 16x16 Bit Signed Multiplication ;* ;* This subroutine multiplies signed the two 16-bit register variables ;* mp16sH:mp16sL and mc16sH:mc16sL. ;* The result is placed in m16s3:m16s2:m16s1:m16s0. ;* The routine is an implementation of Booth's algorithm. If all 32 bits ;* in the result are needed, avoid calling the routine with ;* -32768 ($8000) as multiplicand ;* ;* Number of words :16 + return ;* Number of cycles :210/226 (Min/Max) + return ;* Low registers used :None ;* High registers used :7 (mp16sL,mp16sH,mc16sL/m16s0,mc16sH/ m16s1, ;* m16s2,m16s3,mcnt16s) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def .def
mc16sL mc16sH mp16sL mp16sH m16s0 m16s1 m16s2 m16s3 mcnt16s
=r16 =r17 =r18 =r19 =r18 =r19 =r20 =r21 =r22
;multiplicand low byte ;multiplicand high byte ;multiplier low byte ;multiplier high byte ;result byte 0 (LSB) ;result byte 1 ;result byte 2 ;result byte 3 (MSB) ;loop counter
;***** Code mpy16s: sub ldi m16s_1: add
clr m16s3 m16s2,m16s2 mcnt16s,16 brcc m16s_2 m16s2,mc16sL
;clear result byte 3 ;clear result byte 2 and carry ;init loop counter ;if carry (previous bit) set ; add multiplicand Low to result
m16s3,mc16sH
;
byte 2 adc
add multiplicand High to
result byte 3 m16s_2: sub
sbrc mp16sL,0 m16s2,mc16sL ;
;if current bit set sub multiplicand Low from
result byte 2 sbrc sbc
mp16sL,0 m16s3,mc16sH
;if current bit set ; sub multiplicand High from
asr ror ror ror dec brne ret
m16s3 m16s2 m16s1 m16s0 mcnt16s m16s_1
;shift right result and multiplier
result byte 3
;decrement counter ;if not done, loop more
; *************************************************************************** ;* ;* "div8u" - 8/8 Bit Unsigned Division ;* ;* This subroutine divides the two register variables "dd8u" (dividend) and ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in ;* "drem8u". ;* ;* Number of words :14 ;* Number of cycles :97 ;* Low registers used :1 (drem8u) ;* High registers used :3 (dres8u/dd8u,dv8u,dcnt8u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def
drem8u dres8u dd8u dv8u dcnt8u
=r15 =r16 =r16 =r17 =r18
;remainder ;result ;dividend ;divisor ;loop counter
;***** Code div8u: ldi d8u_1: dec brne ret d8u_2:
sub drem8u,drem8u ;clear remainder and carry dcnt8u,9 ;init loop counter rol dd8u ;shift left dividend dcnt8u ;decrement counter d8u_2 ;if done ; return rol drem8u ;shift dividend into
remainder sub brcc add clc
drem8u,dv8u d8u_3 drem8u,dv8u
;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_3:
d8u_1 sec
;else
rjmp
d8u_1
result ;
set carry to be
shifted into result
; *************************************************************************** ;* ;* "div8s" - 8/8 Bit Signed Division ;* ;* This subroutine divides the two register variables "dd8s" (dividend) and ;* "dv8s" (divisor). The result is placed in "dres8s" and the remainder in ;* "drem8s". ;* ;* Number of words :27 ;* Number of cycles :107/108 ;* Low registers used :2 (d8s,drem8s) ;* High registers used :3 (dres8s/dd8s,dv8s,dcnt8s) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def
d8s drem8s dres8s dd8s dv8s dcnt8s
=r14 =r15 =r16 =r16 =r17 =r18
;sign register ;remainder ;result ;dividend ;divisor ;loop counter
mov
d8s,dd8s
;move dividend to sign
;***** Code div8s: register eor
;xor sign with divisor
dv8s,7 dv8s dd8s,7 dd8s drem8s,drem8s dcnt8s,9 rol dd8s dcnt8s d8s_2 d8s,7 dres8s
;if MSB of divisor set ; change sign of divisor ;if MSB of dividend set ; change sign of divisor ;clear remainder and carry ;init loop counter ;shift left dividend ;decrement counter ;if done ; if MSB of sign register set ; change sign of result
sbrc neg sbrc neg sub ldi d8s_1: dec brne sbrc neg
d8s,dv8s
ret d8s_2:
; rol
drem8s
return ;shift dividend into
remainder sub brcc add clc
drem8u,dv8s d8s_3 drem8u,dv8s
;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8s_3:
d8s_1 sec
;else
rjmp
d8s_1
result ;
set carry to be
shifted into result
; *************************************************************************** ;* ;* "div16u" - 16/16 Bit Unsigned Division ;* ;* This subroutine divides the two 16-bit numbers ;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor). ;* The result is placed in "dres16uH:dres16uL" and the remainder in ;* "drem16uH:drem16uL". ;* ;* Number of words :19 ;* Number of cycles :235/251 (Min/Max) ;* Low registers used :2 (drem16uL,drem16uH) ;* High registers used :5 (dres16uL/dd16uL,dres16uH/dd16uH, dv16uL,dv16uH, ;* dcnt16u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def .def
drem16uL=r14 drem16uH=r15 dres16uL=r16 dres16uH=r17 dd16uL =r16 dd16uH =r17 dv16uL =r18 dv16uH =r19 dcnt16u =r20
;***** Code div16u: sub
clr drem16uL ;clear remainder Low byte drem16uH,drem16uH;clear remainder High byte and
ldi d16u_1: rol dec brne ret d16u_2:
dcnt16u,17 rol dd16uL dd16uH dcnt16u d16u_2
carry ;init loop counter ;shift left dividend
;decrement counter ;if done ; return drem16uL ;shift dividend into
rol
remainder rol sub sbc brcc add adc clc
drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_3 drem16uL,dv16uL drem16uH,dv16uH
;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_3:
d16u_1 sec
rjmp
d16u_1
;else ;
set carry to be
shifted into result
; *************************************************************************** ;* ;* "div16s" - 16/16 Bit Signed Division ;* ;* This subroutine divides signed the two 16 bit numbers ;* "dd16sH:dd16sL" (dividend) and "dv16sH:dv16sL" (divisor). ;* The result is placed in "dres16sH:dres16sL" and the remainder in ;* "drem16sH:drem16sL". ;* ;* Number of words :45 ;* Number of cycles :252/268 (Min/Max) ;* Low registers used :3 (d16s,drem16sL,drem16sH) ;* High registers used :7 (dres16sL/dd16sL,dres16sH/dd16sH, dv16sL,dv16sH, ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def
d16s =r13 drem16sL=r14
;sign register ;remainder low
.def .def .def .def .def .def .def .def
drem16sH=r15 dres16sL=r16 dres16sH=r17 dd16sL =r16 dd16sH =r17 dv16sL =r18 dv16sH =r19 dcnt16s =r20
;remainder high byte ;result low byte ;result high byte ;dividend low byte ;dividend high byte ;divisor low byte ;divisor high byte ;loop counter
mov
;move dividend High to sign
byte
;***** Code div16s:
d16s,dd16sH
register eor sbrs rjmp com com subi sbci d16s_1: rjmp com com subi sbci d16s_2: sub
d16s,dv16sH
;xor divisor High with sign register
dd16sH,7 ;if MSB in dividend set d16s_1 dd16sH ; change sign of dividend dd16sL dd16sL,low(-1) dd16sL,high(-1) sbrs dv16sH,7 ;if MSB in divisor set d16s_2 dv16sH ; change sign of divisor dv16sL dv16sL,low(-1) dv16sL,high(-1) clr drem16sL ;clear remainder Low byte drem16sH,drem16sH;clear remainder High byte and
carry ldi d16s_3: rol dec brne sbrs rjmp com com subi sbci
dcnt16s,17
;init loop counter
d16s_4: ret d16s_5:
rol dd16sL ;shift left dividend dd16sH dcnt16s ;decrement counter d16s_5 ;if done d16s,7 ; if MSB in sign register set d16s_4 dres16sH ; change sign of result dres16sL dres16sL,low(-1) dres16sH,high(-1)
; rol
drem16sL
return ;shift dividend into
remainder rol sub sbc brcc add adc clc
drem16sH drem16sL,dv16sL drem16sH,dv16sH d16s_6 drem16sL,dv16sL drem16sH,dv16sH
;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16s_6:
d16s_3 sec
rjmp
d16s_3
;else ;
set carry to be
shifted into result
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct verification. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ;--------------------------------------------------------------;Include these lines for devices with SRAM ; ldi temp,low(RAMEND) ; out SPL,temp ; ldi temp,high(RAMEND) ; out SPH,temp ;init Stack Pointer ;--------------------------------------------------------------;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4) ldi ldi rcall
mc8u,250 mp8u,4 mpy8u
;result: m8uH:m8uL = $03e8 (1000)
;***** Multiply Two Signed 8-Bit Numbers (-99 * 88) ldi mc8s,-99 ldi mp8s,88 rcall mpy8s ;result: m8sH:m8sL = $ddf8 (-8712) ;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000) ldi mc16uL,low(5050) ldi mc16uH,high(5050) ldi mp16uL,low(10000) ldi mp16uH,high(10000) rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0 ;=030291a0 (50,500,000) ;***** Multiply Two Signed 16-Bit Numbers (-12345*(-4321)) ldi mc16sL,low(-12345) ldi mc16sH,high(-12345) ldi mp16sL,low(-4321) ldi mp16sH,high(-4321) rcall mpy16s ;result: m16s3:m16s2:m16s1:m16s0 ;=$032df219 (53,342,745) ;***** Divide Two Unsigned 8-Bit Numbers (100/3) ldi dd8u,100 ldi dv8u,3 rcall div8u ;result: $21 (33) ;remainder: $01 (1) ;***** Divide Two Signed 8-Bit Numbers (-110/-11) ldi dd8s,-110 ldi dv8s,-11 rcall div8s ;result: $0a (10) ;remainder $00 (0)
;***** Divide Two Unsigned 16-Bit Numbers (50,000/60,000) ldi dd16uL,low(50000) ldi dd16uH,high(50000) ldi dv16uL,low(60000) ldi dv16uH,high(60000) rcall div16u ;result: $0000 (0) ;remainder: $c350 (50,000)
;***** Divide Two Signed 16-Bit Numbers (-22,222/10) ldi dd16sL,low(-22222) ldi dd16sH,high(-22222) ldi dv16sL,low(10) ldi dv16sH,high(10) rcall div16s ;result: $f752 (-2222) ;remainder: $0002 (2) forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have http://avr-asm.tripod.com/avr200.html (1 of 2)1/20/2009 8:34:09 PM
MULTIPLY & DIVIDE (AVR 200)
different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr200.html (2 of 2)1/20/2009 8:34:09 PM
MULTIPLY & DIVIDE (AVR 200)
The AVR Assembler Site
FAST MULTIPLY & DIVIDE (AVR 200b) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202
MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16
A V R 2 0 0 b
************************
ASM MATH
MATH 32X
N O T E
Title: Version: Last updated: Target:
Multiply and Divide Routines 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This Application Note lists subroutines for the following Muliply/Divide applications. Routines are straight-line
implementations ;* optimized for speed: ;* ;* 8 x 8 = 16 bit unsigned ;* 16 x 16 = 32 bit unsigned ;* 8 / 8 = 8 + 8 bit unsigned ;* 16 / 16 = 16 + 16 bit unsigned ;* ; ***************************************************************************
MATH 202
.include "1200def.inc"
MATH 202 rjmp
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236
RESET
;reset handle
; *************************************************************************** ;* ;* "mpy8u" - 8x8 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two register variables mp8u and mc8u. ;* The result is placed in registers m8uH, m8uL ;* ;* Number of words :34 + return ;* Number of cycles :34 + return ;* Low registers used :None ;* High registers used :3 (mc8u,mp8u/m8uL,m8uH) ;* ;* Note: Result Low byte and the multiplier share the same register. ;* This causes the multiplier to be overwritten by the result. ;* ; ***************************************************************************
XMODEM REC ;***** Subroutine Register Variables
UART 304
.def .def .def .def
UART 305 UART 128 UART BUFF USB 232
mc8u mp8u m8uL m8uH
=r16 =r17 =r17 =r18
clr mp8u
m8uH
;multiplicand ;multiplier ;result Low byte ;result High byte
;***** Code
AVR ISP mpy8u: lsr
ISP 2313
;clear result High byte ;shift multiplier
ISP 1200 brcc add
AVR SPI I2C 300
I2C/TWI 128
noad80:
;rotate right result L byte and
brcc add
noad81 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
High byte noad81:
IRD 410
m8uH
;shift right result High
ror
m8uL
;rotate right result L byte and
brcc add
noad82 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
High byte
ADC 401 THERM 232
ror
byte
ADC 10B ADC 400
;shift right result High
m8uL
TEA ADC 128
m8uH
ror
DALLAS-1W
ETHNET 8019
ror
byte
I2C/TWI AT8
DALLAS CRC
;if carry set ; add multiplicand to result
High byte
I2C 302 I2C TWI26
noad80 m8uH,mc8u
noad82:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
brcc add
noad83 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
LCD HD44 LCD 2313 LCD44 2313 KBD 240
High byte noad83:
m8uL
;rotate right result L byte and
brcc add
noad84 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
High byte
BOOT MG8 BOOT DR8 ALM CLK
;shift right result High
ror
KBD PC/128 PS2 EMU
m8uH
byte
MUX 242 KBD PS2
ror
noad84:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
brcc add
noad85 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
CLOCK 8564 90 DAYS DELAYS CALL ID
High byte noad85:
m8uL
;rotate right result L byte and
brcc add
noad86 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
ENCODE
ATMEL CORP AVR BUTTERFLY
;shift right result High
ror
PWM 10K
STH-11
m8uH
byte
DTMF 314 PWM 6CH
ror
High byte noad86:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
brcc add
noad87 m8uH,mc8u
;if carry set ; add multiplicand to result
multiplier
AVR BOOK High byte
noad87:
ror
m8uH
;shift right result High
byte ror
m8uL
;rotate right result L byte and
multiplier ret
; *************************************************************************** ;* ;* "mpy16u" - 16x16 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two 16-bit register variables ;* mp16uH:mp16uL and mc16uH:mc16uL. ;* The result is placed in m16u3:m16u2:m16u1:m16u0. ;* ;* Number of words :105 + return ;* Number of cycles :105 + return ;* Low registers used :None ;* High registers used :6 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/ m16u1,m16u2, ;* m16u3) ;* ; *************************************************************************** ;***** Subroutine Register Variables
.def .def .def .def .def .def .def .def
mc16uL mc16uH mp16uL mp16uH m16u0 m16u1 m16u2 m16u3
=r16 =r17 =r18 =r19 =r18 =r19 =r20 =r21
;multiplicand low byte ;multiplicand high byte ;multiplier low byte ;multiplier high byte ;result byte 0 (LSB) ;result byte 1 ;result byte 2 ;result byte 3 (MSB)
clr
m16u3
;clear 2 highest bytes of
;***** Code mpy16u: result clr lsr ror
m16u2 mp16uH mp16uL
;rotate multiplier Low ;rotate multiplier High
brcc add
noadd0 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd0: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd1 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd1: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd2 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd2: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd3 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd3: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd4 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd4: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd5 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd5: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd6 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd6: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd7 m16u2,mc16uL
;if carry sett ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd7: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd8 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd8: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noadd9 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noadd9: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad10 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad10: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad11 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad11: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad12 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad12: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad13 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad13: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad14 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad14: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
;rotate result byte 0 and
brcc add
noad15 m16u2,mc16uL
;if carry set ; add multiplicand Low to byte 2
adc
m16u3,mc16uH
;
noad15: ror ror
ror m16u2 m16u1
;shift right result byte 3 ;rotate right result byte 2 ;rotate result byte 1 and
ror
m16u0
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High multiplier Low
of res add multiplicand high to byte
3 of res m16u3
multiplier High ;rotate result byte 0 and
multiplier Low ret
; *************************************************************************** ;* ;* "div8u" - 8/8 Bit Unsigned Division ;* ;* This subroutine divides the two register variables "dd8u" (dividend) and ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in ;* "drem8u". ;* ;* Number of words :66 + return ;* Number of cycles :50/58/66 (Min/Avg/Max) + return ;* Low registers used :1 (drem8u) ;* High registers used :2 (dres8u/dd8u,dv8u) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def
drem8u dres8u dd8u dv8u
=r15 =r16 =r16 =r17
;remainder ;result ;dividend ;divisor
sub
drem8u,drem8u
;clear remainder and carry
;***** Code div8u: rol rol sub brcc add clc
dd8u drem8u drem8u,dv8u d8u_1 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_1:
d8u_2 sec
;else
d8u_2: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_3 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_3:
d8u_4 sec
;else
d8u_4: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_5 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_5:
d8u_6 sec
;else
d8u_6: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_7 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_7:
d8u_8 sec
;else
d8u_8: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_9 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_9:
d8u_10 sec
;else
d8u_10: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_11 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_11:
d8u_12 sec
;else
d8u_12: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_13 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_13:
d8u_14 sec
;else
d8u_14: rol sub brcc add clc
rol dd8u drem8u drem8u,dv8u d8u_15 drem8u,dv8u
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ;if result negative ; restore remainder ; clear carry to be shifted into
rjmp d8u_15:
d8u_16 sec
;else
d8u_16: ret
rol
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result
result ;
set carry to be
shifted into result dd8u
;shift left dividend
; *************************************************************************** ;* ;* "div16u" - 16/16 Bit Unsigned Division ;* ;* This subroutine divides the two 16-bit numbers ;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor). ;* The result is placed in "dres16uH:dres16uL" and the remainder in ;* "drem16uH:drem16uL". ;* ;* Number of words :196 + return ;* Number of cycles :148/173/196 (Min/Avg/Max) ;* Low registers used :2 (drem16uL,drem16uH) ;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH, dv16uL,dv16uH) ;* ; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def .def .def .def .def
drem16uL=r14 drem16uH=r15 dres16uL=r16 dres16uH=r17 dd16uL =r16 dd16uH =r17 dv16uL =r18 dv16uH =r19
;***** Code div16u: sub
clr drem16uL ;clear remainder Low byte drem16uH,drem16uH;clear remainder High byte and
carry rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_1 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_1:
d16u_2 sec
;else
d16u_2: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_3 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_3:
d16u_4 sec
d16u_4: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_5 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_5:
d16u_6 sec
d16u_6: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_7 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_7:
d16u_8 sec
d16u_8: rol rol rol sub sbc brcc add adc clc
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_9 drem16uL,dv16uL drem16uH,dv16uH
rjmp d16u_9:
d16u_10 sec
;else
d16u_10:rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_11 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend
;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;else ;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;else ;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;else ;
set carry to be
shifted into result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;
set carry to be
shifted into result
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_12 d16u_11:sec
;else ; set carry to be shifted into
d16u_12:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_13 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_14 d16u_13:sec
;else ; set carry to be shifted into
d16u_14:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_15 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_16 d16u_15:sec
;else ; set carry to be shifted into
d16u_16:rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_17 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend
rjmp d16u_17:
d16u_18 sec
;else
d16u_18:rol rol rol rol sub sbc brcc add adc clc
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_19 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend
result
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result ;
set carry to be
shifted into result
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_20 d16u_19:sec
;else ; set carry to be shifted into
d16u_20:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_21 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_22 d16u_21:sec
;else ; set carry to be shifted into
d16u_22:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_23 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_24 d16u_23:sec
;else ; set carry to be shifted into
d16u_24:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_25 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_26 d16u_25:sec
;else ; set carry to be shifted into
d16u_26:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_27 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_28 d16u_27:sec
;else ; set carry to be shifted into
d16u_28:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_29 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_30 d16u_29:sec
;else ; set carry to be shifted into
d16u_30:rol rol rol rol sub sbc brcc add adc clc
;shift left dividend
result dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_31 drem16uL,dv16uL drem16uH,dv16uH
;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ;
clear carry to be shifted into
result rjmp d16u_32 d16u_31:sec
;else ; set carry to be shifted into
d16u_32:rol dd16uL rol dd16uH ret
;shift left dividend
result
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct verification. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ;--------------------------------------------------------------;Include these lines for devices with SRAM ; ldi temp,low(RAMEND) ; out SPL,temp ; ldi temp,high(RAMEND) ; out SPH,temp ;init Stack Pointer ;--------------------------------------------------------------;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4) ldi ldi rcall
mc8u,250 mp8u,4 mpy8u
;result: m8uH:m8uL = $03e8 (1000)
;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000) ldi mc16uL,low(5050) ldi mc16uH,high(5050) ldi mp16uL,low(10000) ldi mp16uH,high(10000) rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0 ;=$030291a0 (50,500,000) ;***** Divide Two Unsigned 8-Bit Numbers (100/3) ldi dd8u,100 ldi dv8u,3 rcall div8u ;result: $21 (33) ;remainder: $01 (1) ;***** Divide Two Unsigned 16-Bit Numbers (50,000/24,995) ldi dd16uL,low(50000) ldi dd16uH,high(50000) ldi dv16uL,low(24995) ldi dv16uH,high(24995) rcall div16u ;result: $0002 (2) ;remainder: $000a (10) forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The http://avr-asm.tripod.com/avr200b.html (1 of 2)1/20/2009 8:35:39 PM
MULTIPLY & DIVIDE (AVR 200)
AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr200b.html (2 of 2)1/20/2009 8:35:39 PM
16 BIT MULTIPLY (AVR 201)
The AVR Assembler Site
16 BIT MULTIPLY (AVR 201) HOME RETRO_DAN ;
ASM FORUM ASM MATH TUTORIAL #1
;* ;* Title ;* ;* ;* ;* ;* ;* ;* ;*
MATH 201 MATH 202 MATH 32X
Support email
: [email protected]
: 5 Apr, 1999 : ATmega83/161/163
DESCRIPTION This application note shows a number of examples of
;*
16bit multiplication using hardware multiplier.
;*
funtions headers for details. The functions
;* ;* ;*
are : mul16x16_16
- Multiply of two 16bits numbers
;*
mul16x16_32
- Unsigned multiply of two 16bits
muls16x16_32
result. - Signed multiply of two 16bits
mac16x16_32
result. - Signed multiply accumulate of two
fmuls16x16_32
with a 32bits result. - Signed fractional multiply of two
fmac16x16_32
with 32bits result. - Signed fractional multiply
;* ;* numbers with 32bits ;* ;* 16bits numbers ;* ;*
FFT7 COPY 102
: V1.0
numbers with 32bits
HX2ASC AVG8 222
Version Last updated Target
with 16bits result.
DEC ASCII INT ASCII
: 16bit multiply routines using
included in this file
SQRT16
MATH 202
A V R 2 0 1
Refer to each of the
FLOAT 128
MATH 202
N O T E
how to implement
DIV 24 24 DIV 3216
1:34 pm
hardware multiplier
MATH 200b
DIV16 XX
21 Jul 99
***************************
MATH 200
MATH YX
MWL
;**** A P P L I C A T I O N
TUTORIAL #2 TUTORIAL #3
Last change:
16bits numbers ;* ;*
LPM 108 EPROM 100
accumulate of two 16bits
SER EPROM
;* numbers with a 32bits result. ;* ; ******************************************************************************
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
; ****************************************************************************** ;* ;* FUNCTION ;* mul16x16_16 ;* DECRIPTION ;* Multiply of two 16bits numbers with 16bits result. ;* USAGE ;* r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 9 + ret ;* Words : 6 + ret ;* Register usage: r0, r1 and r16 to r23 (8 registers) ;* NOTE ;* Full orthogonality i.e. any register pair can be used as long as ;* the result and the two operands does not share register pairs. ;* The routine is non-destructive to the operands. ;* ; ******************************************************************************
I2C/TWI 128
mul16x16_16: mul r22, r20 movw r17:r16, r1:r0 mul r23, r20 add r17, r0 mul r21, r22 add r17, r0 ret
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA
; al * bl ; ah * bl ; bh * al
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
; ****************************************************************************** ;* ;* FUNCTION ;* mul16x16_32 ;* DECRIPTION ;* Unsigned multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 17 + ret ;* Words : 13 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* NOTE ;* Full orthogonality i.e. any register pair can be used as long as ;* the 32bit result and the two operands does not share register pairs. ;* The routine is non-destructive to the operands. ;* ; ******************************************************************************
90 DAYS
mul16x16_32: clr r2 mul r23, r21 movw r19:r18, r1:r0 mul r22, r20 movw r17:r16, r1:r0 mul r23, r20 add r17, r0 adc r18, r1 adc r19, r2 mul r21, r22 add r17, r0 adc r18, r1 adc r19, r2 ret
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
; ah * bh ; al * bl ; ah * bl
; bh * al
AVR BOOK ; ****************************************************************************** ;* ;* FUNCTION ;* muls16x16_32 ;* DECRIPTION ;* Signed multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 19 + ret ;* Words : 15 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* NOTE ;* The routine is non-destructive to the operands. ;* ; ****************************************************************************** muls16x16_32: clr r2 muls r23, r21
; (signed)ah *
(signed)bh movw mul movw mulsu sbc add adc adc mulsu sbc add adc adc ret
r19:r18, r1:r0 r22, r20 r17:r16, r1:r0 r23, r20 r19, r2 r17, r0 r18, r1 r19, r2 r21, r22 r19, r2 r17, r0 r18, r1 r19, r2
; al * bl ; (signed)ah * bl
; (signed)bh * al
; ****************************************************************************** ;* ;* FUNCTION ;* mac16x16_32 ;* DECRIPTION ;* Signed multiply accumulate of two 16bits numbers with ;* a 32bits result. ;* USAGE ;* r19:r18:r17:r16 += r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 23 + ret ;* Words : 19 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* ; ****************************************************************************** mac16x16_32: clr r2 muls
r23, r21
; (signed)ah *
add adc
r18, r0 r19, r1
mul add adc adc adc
r22, r16, r17, r18, r19,
r20 r0 r1 r2 r2
; al * bl
mulsu sbc add adc adc
r23, r19, r17, r18, r19,
r20 r2 r0 r1 r2
; (signed)ah * bl
mulsu sbc add adc adc
r21, r19, r17, r18, r19,
r22 r2 r0 r1 r2
; (signed)bh * al
(signed)bh
ret mac16x16_32_method_B:
; uses two
temporary registers ; (r4,r5), but reduces cycles/words ; by 1 clr
r2
muls
r23, r21
movw
r5:r4,r1:r0
mul
r22, r20
add adc adc adc
r16, r17, r18, r19,
r0 r1 r4 r5
mulsu sbc add adc adc
r23, r19, r17, r18, r19,
r20 r2 r0 r1 r2
; (signed)ah * bl
mulsu sbc add adc adc
r21, r19, r17, r18, r19,
r22 r2 r0 r1 r2
; (signed)bh * al
; (signed)ah *
(signed)bh
; al * bl
ret
; ****************************************************************************** ;* ;* FUNCTION ;* fmuls16x16_32 ;* DECRIPTION ;* Signed fractional multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1 ;* STATISTICS ;* Cycles : 20 + ret ;* Words : 16 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* NOTE ;* The routine is non-destructive to the operands. ;* ; ****************************************************************************** fmuls16x16_32: clr r2 fmuls r23, r21
; ( (signed)ah *
(signed)bh ) << 1 movw fmul adc movw fmulsu
r19:r18, r1:r0 r22, r20 r18, r2 r17:r16, r1:r0 r23, r20
sbc add adc adc fmulsu
r19, r17, r18, r19, r21,
r2 r0 r1 r2 r22
sbc add adc adc ret
r19, r17, r18, r19,
r2 r0 r1 r2
; ( al * bl ) << 1
; ( (signed)ah *
bl ) << 1
; ( (signed)bh *
al ) << 1
; ****************************************************************************** ;* ;* FUNCTION ;* fmac16x16_32 ;* DECRIPTION ;* Signed fractional multiply accumulate of two 16bits numbers with ;* a 32bits result. ;* USAGE ;* r19:r18:r17:r16 += (r23:r22 * r21:r20) << 1 ;* STATISTICS ;* Cycles : 25 + ret ;* Words : 21 + ret ;* Register usage: r0 to r2 and r16 to r23 (11 registers) ;* ; ****************************************************************************** fmac16x16_32: clr r2 fmuls
r23, r21
add adc
r18, r0 r19, r1
fmul adc adc add adc adc adc
r22, r18, r19, r16, r17, r18, r19,
fmulsu
r23, r20
sbc add adc adc
r19, r17, r18, r19,
fmulsu
r21, r22
sbc add adc adc
r19, r17, r18, r19,
; ( (signed)ah *
(signed)bh ) << 1
r20 r2 r2 r0 r1 r2 r2
; ( al * bl ) << 1
; ( (signed)ah *
bl ) << 1 r2 r0 r1 r2 ; ( (signed)bh *
al ) << 1 r2 r0 r1 r2
ret fmac16x16_32_method_B:
; uses two
temporary registers ; (r4,r5), but reduces cycles/words ; by 2 clr
r2
fmuls
r23, r21
; ( (signed)ah *
movw fmul adc
r5:r4,r1:r0 r22, r20 r4, r2
; ( al * bl ) << 1
add adc adc adc
r16, r17, r18, r19,
fmulsu
r23, r20
; ( (signed)ah *
sbc add adc adc fmulsu
r19, r17, r18, r19, r21,
r2 r0 r1 r2 r22
; ( (signed)bh *
sbc add adc adc
r19, r17, r18, r19,
r2 r0 r1 r2
(signed)bh ) << 1
r0 r1 r4 r5
bl ) << 1
al ) << 1
ret
;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even http://avr-asm.tripod.com/avr201.html (1 of 2)1/20/2009 8:36:15 PM
16 BIT MULTIPLY (AVR 201)
after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr201.html (2 of 2)1/20/2009 8:36:15 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
16 BIT MATH (AVR 202) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202
A V R 2 0 2
************************
ASM MATH
MATH 202
N O T E
Title: Version: Last updated: Target:
16-bit Arithmetics 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This application note lists applications for the
following ;* Add/Subtract/Compare operations: ;* ;* "add16" ADD 16+16 ;* "adddi16" ADD 16+Immediate(16) ;* "sub16" SUB 16-16 ;* "subi16" SUB 16-Immediate(16) ;* "cp16" COMPARE 16/16 ;* "cpi16" COMPARE 16/Immediate ;* "neg16" NEGATION 16 ;* ; ***************************************************************************
MATH 202 DEC ASCII INT ASCII
r16,0x12
;Set up some registers to
ldi ldi
r17,0x34 r18,0x56
;the subroutines below. ;All expected results are
ldi
r19,0x78
;comments
show usage of
HX2ASC AVG8 222
.cseg ldi
presented as
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
; *************************************************************************** ;* ;* "add16" - Adding 16-bit registers ;* ;* This example adds the two pairs of register variables (add1l,add1h) ;* and (add2l,add2h) The result is placed in (add1l, add1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
AVR ISP
;**** Register Variables .def add1l = r16 .def add1h = r17 .def add2l = r18 .def add2h = r19
ISP 2313 ISP 1200 AVR SPI I2C 300
;***** Code add16: add
I2C 302 I2C TWI26 I2C/TWI 128
add1l, add2l
;Add low
bytes adc
add1h, add2h
;Add high bytes
with carry ;Expected result is 0xAC68
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;* ;* "addi16" - Adding 16-bit register with immediate ;* ;* This example adds a register variable (addi1l, addi1h) with an ;* immediate 16-bit number defined with .equstatement. The result is ;* placed in (addi1l, addi1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
PS2 EMU
;***** Register Variables .def addi1l = r16 .def addi1h = r17
BOOT MG8 BOOT DR8 ALM CLK
;***** Immediate 16-bit number .equ addi2 = 0x1234
CLOCK 8564 90 DAYS
;***** Code addi16: subi
DELAYS CALL ID DTMF 314
add1l, low(-addi2)
;Add low
byte ( x -(-y)) = x + y sbci
add1h, high(-addi2)
;Add high byte with
carry ;Expected result is 0xBE9C
PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* "sub16" - Subtracting 16-bit registers ;* ;* This example subtracts two pairs of register variables (sub1l,sub1h) ;* from (sub2l, sub2h) The result is stored in registers sub1l, sub1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The result and "sub1" share the same register. This causes "sub1" ;* to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def sub1l = r16 .def sub1h = r17 .def sub2l = r18 .def sub2h = r19 ;***** Code sub16: sub
sub1l,sub2l
;Subtract
low bytes sbc
sub1h,sub2h
;Add high byte with
carry ;Expected result is 0x4646
; *************************************************************************** ;* ;* "subi16" - Subtracting immediate 16-bit number from a 16-bit register ;* ;* This example subtracts the immediate 16-bit number subi2 from the ;* 16-bit register (subi1l,subi1h) The result is placed in registers ;* subi1l, subi1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The result and "subi1" share the same register. This causes ;* "subi1" to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def subi1l = r16 .def subi1h = r17 ;***** Immediate 16-bit number .equ subi2 = 0x1234 ;***** Code subi16: subi
subi1l,low(subi2)
;Subtract
low bytes sbci
subi1h,high(subi2)
;Subtract high byte
with carry ;Expected result is 0x3412
; *************************************************************************** ;* ;* "cp16" - Comparing two 16-bit numbers ;* ;* This example compares the register pairs (cp1l,cp1h) with the register ;* pairs (cp2l,cp2h) If they are equal the zero flag is set(one) ;* otherwise it is cleared(zero) ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The contents of "cp1" will be overwritten. ;* ; *************************************************************************** ;***** Register Variables .def cp1l = r16 .def cp1h = r17 .def cp2l = r18 .def cp2h = r19 ;***** Code cp16: cp cp1l,cp2l ;Compare low byte cpc cp1h,cp2h ;Compare high byte with carry from ;previous operation ncp16: ;Expected result is Z=0
; *************************************************************************** ;* ;* "cpi16" - Comparing 16-bit register with 16-bit immediate ;* ;* This example compares the register pairs (cpi1l, cpi1h) with the value ;* cpi2. If they are equal the zero flag is set(one), otherwise it is ;* cleared(zero). This is enabled by the AVR's zero propagation. Carry is ;* also set if the result is negative. This means that all conditional ;* branch instructions can be used after the comparison. ;* ;* Number of words :3 ;* Number of cycles :3 ;* Low registers used :None ;* High registers used :3 ;* ;* ; *************************************************************************** ;***** Register Variables .def cp1l =r16 .def cp1h =r17 .def c_tmp=r18 .equ cp2 = 0x3412
;Immediate to compare with
;***** Code cpi16: cpi cp1l,low(cp2) ;Compare low byte ldi c_tmp,high(cp2) ; cpc cp1h,c_tmp ;Compare high byte ;Expected result is Z=1, C=
; *************************************************************************** ;* ;* "neg16" - Negating 16-bit register ;* ;* This example negates the register pair (ng1l,ng1h) The result will ;* overwrite the register pair. ;* ;* Number of words :4 ;* Number of cycles :4 ;* Low registers used :None ;* High registers used :2 ;* ; *************************************************************************** ;***** Register Variables .def ng1l = r16 .def ng1h = r17 ;***** Code ng16: com ng1l
;Invert low byte
;
Calculated by com
ng1h
;Invert high byte
;
subi
ng1l,low(-1)
;Add 0x0001, low byte
;
sbci
ng1h,high(-1)
;Add high byte
;
incverting all bits then adding one (0x0001) ;Expected result is 0xCBEE
; *************************************************************************** ;* ;* End of examples. ;* ; ***************************************************************************
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, http://avr-asm.tripod.com/avr202.html (1 of 2)1/20/2009 8:37:09 PM
16 BIT MATH (AVR 202)
the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr202.html (2 of 2)1/20/2009 8:37:09 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
32 BIT MATH (AVR XXX) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N
TUTORIAL #3 MATH 200 MATH 200b
MATH 202 MATH 32X
FLOAT 128
MATH 202 DEC ASCII
;*
;* INTERPRETATION ;* This package of assembler subprograms is developed for integer arithmetic ;* with tracing of sign bit in 32 bits calculations and data reloads. ;* It is based on microcontroller register file to the maximum. ;* In real users projects available abundant digit capacity allows to avoid ;* overflow and reduces inaccuracy of rounding errors in chain calculations. ;* Included macro definitions will increase readability
AVG8 222
AVR software model
;* at bit by bit and multibyte data operations inside ;* ;* DESCRIPTION ;* This Application Note lists: ;* i) Math32 subroutines for the following: ;* Add/Subtract/Multiply/Divide/Complement 32 bits
FFT7 COPY 102 LPM 108 operands,
;* ;* ;* ;* ;*
SER EPROM DFLASH AT45 FLASH CARD
;* iii) useful general macroinstructions for the AVR 8Bit RISC family
CRC 236
UART 304
UART BUFF USB 232
I2C/TWI AT8 DALLAS-1W
DELAYS CALL ID
;* ;* ;* ;* ;*
"BCD2bin" "BCD3bin" "Bin2BCD" "Bin3BCD" "Bin4BCD"
BCD to BCD to Binary Binary Binary
Rd16 Rd24 Rd24 Rd32 Rd40
;* ;* ;* ;* ;* ;*
"MathMem" "MathLoad" "MathSave"
Init Data Memory Load Registers Store Registers
Binary 16 Binary 24 16 to BCD 24 to BCD 32 to BCD
= = = = =
Rd24|Rr24 Rd32|Rr32 Rd16|Rr16 Rd24|Rr24 Rd32|
(MA) = 0x00|0xff Rd32|Rr32 = (MA) (MA) = Rd32|Rd64
Rd64: destination registers (8) in the register file Rd32: destination (and source) registers (4) in the
so Rd64=r20:r27, Rd32=r20:r23, Rd24=r20:r22, Rd40=r20:r24, Rr32=r16:r19, Rr24=r16:r18, Rr16=r16:
c o
;* "ADD32" ;* "SUB32" ;* "MUL32"
6 16 24
4|5 6|15 460|556
Size of Add32sign Size of Sub32sign Size of Mul32b, based on
;* "DIV32"
28
528|688
Size of Div32b, based on
;* "COM32" ;* "NEG32" ;* "BCD2bin"
5 9 26
4|4 8|8 86|89
Part of Sub32 Part of Sub32 Equivalent of AVR204, but
;* "BCD3bin"
43
38|402
Different from BCD2bin
;* "Bin2BCD"
22
19|177
Equivalent of AVR204, but
;* "Bin3BCD"
21
36|366
In the form of preamble for
;* "Bin3BCD"
40
36|333
All-sufficient expansion of
;* "Bin4BCD"
37
515|671
Based on AVR204 16-bit Bin
;* "Bin4BCD"
48
874|878
All-sufficient transform
;* "MathMem"
10
7|645
;* "MathLoad"
15
41|46
Size and max cycle for Rr32
;* "MathSave"
14
13|78
Size and max cycle for Rd64
AVR200 16x16 unsigned AVR200 16/16 unsigned
smaller & quicker translation algorithm smaller & much faster Bin2BCD Bin2BCD to BCD conversion instead of pre-Bin4BCD cycle for 128 bytes
PWM 10K
load
ENCODE
AVR BUTTERFLY
Rd32 =
m m e n t s
PWM 6CH
ATMEL CORP
Two's Complement
;* ;* Number of words & cycles (Min|Max)
DTMF 314
STH-11
;* "NEG32"
r17, MA=0:511
CLOCK 8564 90 DAYS
Rd32 =
;*
BOOT MG8
ALM CLK
One's Complement
;*
KBD PS2
BOOT DR8
;* "COM32"
Rd16=r20:r21,
MUX 242
PS2 EMU
Rd32 = Rd32 /
bytes of data space,
LCD 2313
KBD PC/128
Divide Unsigned
;* Note: Math32 use high registers, r0 and lower 512
LCD HD44
KBD 240
;* "DIV32"
memory (SRAM)
THERM 232
LCD44 2313
Rd64 = Rd32 *
;* Rr32: source registers (4) in the register file ;* (MA): address for access to variable in the internal
ADC 10B
IRD 410
Multiply Unsigned
register file
ETHNET 8019
ADC 401
;* "MUL32"
Rr32 || hwrd(Rr32)&Rd16
I2C/TWI 128
ADC 400
Rd32 = Rd32 -
0x00000000 - Rd32
I2C TWI26
ADC 128
Subtract without Carry
0xffffffff - Rd32
I2C 300
TEA
;* "SUB32"
Rr32 (Rd64)
AVR SPI
DALLAS CRC
Rd32 = Rd32 +
Rr32
ISP 1200
I2C 302
Add without Carry
Rr32
AVR ISP ISP 2313
;* ;* "ADD32" Rr32
UART 305 UART 128
Binary 16 & 24 bits operand to/back BCD conversion, Binary 32 bits operand to BCD conversion, Initialization of data memory on a pattern, Load/Store group of registers from/to data space; ii) macro definitions call mathematical and data
transfer subroutines;
VFX MEM
XMODEM REC
This Application Note absolutely
free in use anybody
HX2ASC
SORT 220
(C) 1999-2003 Andre Birua
(mailto:[email protected])
of assembler source
VFX SMIL
(C) ATMEL Corporation (mailto:
;* Originator:
INT ASCII
EPROM 100
Math32 2.3 2003.09.15 1999.10.25 AT90S8515 (as well as
Project: Version: Last updated: Create Date: Target MCU:
[email protected])
SQRT16 MATH 202
;* ;* ;* ;* ;* ;*
DIV 24 24 DIV 3216
32-bit Arithmetic Routines with
others AVR uC)
MATH YX DIV16 XX
;* ;* Title: Macrolibrary
TUTORIAL #2
MATH 201
A V R ? ? ?
************************
ASM MATH TUTORIAL #1
N O T E
Size of MathMemLimit, max
save ;* In total:
350 words
Usually +7 cycles: rcall &
ret ;* ;* All routines are Code Size` optimized implementations and debugged with ;* macrocode for AVR macro assembler version 1.30 (Jan
AVR BOOK 27 1999 01:30:00) &
;*
AVR32 macro assembler version 1.30 (Sep
8
1999 01:30:00). ;*
However, AVR32 macro assembler version 1.54 (Nov
14 2001 14:05:48) & ;*
AVR32 macro assembler version 1.56 (May
6
2002 14:54:01) ;* generate dummy warnings: Register already defined by the .DEF directive ;* (command option for disable this kind of warning as yet is absent...) ;* CheckIt with AVR Studio ! ;* NOTE ;* ` Bin4BCD transformations has partial loop optimization for speed-up ;* While using Math32, it is important to consider the allocation of the ;* microcontroller resources available for the program. It is required: ;* - to use r0,r16..r31 with Math32; ;* - to allocate variables used in calculation in the bottom of the memory; ;* - to use T flag as a sign bit (input, output and temporary), ;*
if you need to operate negative numbers or up-down
overflow error ;* ;* VERSION ;* 1.0 Original version (in use starting with 1999.12.22) ;* 1.1 Fixed precedence bugs if macroparameter is an assembler expression ;* 1.2 Modify CBF & SBF & IBF macrocalls ;* 1.3 Full modification mathematical and data transfer macronotation ;* 1.4 Optimaze for speed and code size Mul32 & Div32 & BCD2bin & Bin2BCD ;* 2.0 Version for publication (added description, note and demo sections) ;* 2.1 Updated Bin2BCD, added Bin4BCD conversion & XCH macrocall ;* 2.2 Added functionally closed modifications of Bin3&4BCD translation ;* 2.3 Added BCD3bin conversion, normalize the comment of Bin3&4BCD ;* ;* DEMO ;* section below is a sample of macrocalls and not an ordinary Math32 usage ;* ; *************************************************************************** .include "8515def.inc" .listmac
;split Toggle_mode
at AVR
Studio .cseg
;press Step_Over
etceteras of rjmp
Demo
;trace Registers
and
Memory ;Words *** general macrocode for the AVR 8-Bit RISC microcontroller *** ;2 "CLF" ;2 "SEF" ;2 "CBF"
CLear bit Flag in register via T flag SEt bit Flag in register via T flag Clear Bit(s) Flag(s) in register via
;2 "SBF"
Set Bit(s) Flag(s) in register via temporary
;2 "IBF"
Invert Bit(s) Flag(s) in register via
temporary register register temporary register ;2 "OUTI" OUT port Immediate via temporary register ;4 "OUTIW" OUT port Immediate Word via temporary register ;2 "OUTW" ;2 "INW" ;3 "XCH"
OUT port Word from register pair IN port Word to register pair data eXCHange between a two registers as
;2 "MVW" ;2 "MVI" ;4 "MOVS"
MoVe register pair as Word MoVe temporary register loaded Immediate MOVe direct in data Space via temporary
exclusive OR only
register ;8 "MOVSW" MOVe direct in data Space Word via temporary register ;3 "STSI"
STore direct to data Space Immediate via
temporary register ;4 "STSIW" STore direct to data Space Immediate Word via temporary register ;4 "LDSW"
LoaD direct from data Space Word to register
;4 "STSW"
STore direct to data Space Word from
;2 "LDIW" ;2 "LDDW"
LoaD Immediate Word to register pair LoaD indirect with Displacement from data
;2 "STDW"
STore indirect with Displacement to data
pair register pair
space Word to register pair space Word from register pair ;2 "PUSHW" PUSH register pair (Word) on stack ;2 "POPW" POP register pair (Word) from stack .macro CLF ; Register,Bit# clt bld @0,@1 .endmacro .macro SEF ; Register,Bit# set bld @0,@1 .endmacro .macro CBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][, Bit#][,Bit#][,Bit#][,Bit#][,Bit#] ldi @1,~(exp2(@2)|(-@3-1<0)*exp2(@3-0)| (-@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@81<0)*exp2(@8-0)|(-@9-1<0)*exp2(@9-0)) and @0,@1 .endmacro .macro SBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][, Bit#][,Bit#][,Bit#][,Bit#][,Bit#] ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0) *exp2(@8-0)|(-@9-1<0)*exp2(@9-0) or @0,@1 .endmacro .macro IBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][, Bit#][,Bit#][,Bit#][,Bit#][,Bit#] ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0) *exp2(@8-0)|(-@9-1<0)*exp2(@9-0) eor @0,@1 .endmacro .macro OUTI ; Port,RegisterH,ConstantB ldi @1,@2 out @0,@1 .endmacro .macro OUTIW ; PortHL,RegisterH,ConstantW ldi @1,high(@2) out @0h,@1 ldi @1,low(@2) out @0l,@1 .endmacro .macro OUTW ; PortHL,RegisterHL out @0h,@1h out @0l,@1l .endmacro .macro INW ; RegisterHL,PortHL in @0l,@1l in @0h,@1h .endmacro .macro XCH ; Register,Register eor @0,@1 eor @1,@0 eor @0,@1 .endmacro .macro MVW ; RegisterHL,RegisterHL mov @0h,@1h mov @0l,@1l .endmacro .macro MVI ; RegisterL,RegisterH,ConstantB ldi @1,@2 mov @0,@1 .endmacro .macro MOVS ; Address,Register,Address lds @1,@2 sts @0,@1 .endmacro .macro MOVSW ; Address,Register,Address lds @1,@2 sts @0,@1 lds @1,(@2)+1 sts (@0)+1,@1 .endmacro .macro STSI ; Address,RegisterH,ConstantB ldi @1,@2 sts @0,@1 .endmacro .macro STSIW ; Address,RegisterH,ConstantW ldi @1,low(@2) sts @0,@1 ldi @1,high(@2) sts (@0)+1,@1 .endmacro .macro LDSW ; RegisterHL,Address lds @0l,@1 lds @0h,(@1)+1 .endmacro .macro STSW ; Address,RegisterHL sts (@0)+1,@1h sts @0,@1l .endmacro .macro LDIW ; RegisterHL,ConstantW ldi @0l,low(@1) ldi @0h,high(@1) .endmacro .macro LDDW ; RegisterHL,RegisterPair+Displacement ldd @0l,@1 ldd @0h,@1+1 .endmacro .macro STDW ; RegisterPair+Displacement,RegisterHL std @0+1,@1h std @0,@1l .endmacro .macro PUSHW ; RegisterHL push @0l push @0h .endmacro .macro POPW ; RegisterHL pop @0h pop @0l .endmacro ;Words ***** mathematical and data transfer macrocalls ***** ;3 "INITMEM" INITialize math data space (MEMory variable) in 0|0xff ;3 "MATHR16" load from MATH data space to Registers r16, r17,r18,r19 ;3 "MATHR20" load from MATH data space to Registers r20, r21,r22,r23 ;3 "OPERAND" load registers as mathematical OPERAND from math data space ;3 "RESULT2" store registers as mathematical RESULT to math data space (call) ;3 "RESULT3" store registers as mathematical RESULT to math data space (jump) ;1 "CNST16B" load immediate CoNSTant to r16 as Byte ;2 "CNST16W" load immediate CoNSTant to r16,r17 as Word ;3 "CNST16T" load immediate CoNSTant to r16,r17,r18 as Three bytes ;4 "CONST16" load immediate CONSTant to r16,r17,r18,r19 as double word ;4 "CONST20" load immediate CONSTant to r20,r21,r22,r23 as double word .macro INITMEM ; Address[,Counter(1-128)[,0|1|limit]] ldi ZL,@0 ldi ZH,@1-1<<1|high(@0)&1 rcall MathMem@2 .endmacro .macro MATHR16 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
R16MathLoad
.endmacro .macro MATHR20 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
R20MathLoad
.endmacro .macro OPERAND ; Address[,[Bitmap][,r16|r20]] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
@2MathLoad
.endmacro .macro RESULT2 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rcall
MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f) .endmacro .macro RESULT3 ; Address[,Bitmap] ldi ZL,@0 ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high (@0)&1 rjmp
MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f) .endmacro .macro CNST16B ; ldi .endmacro .macro CNST16W ; ldi ldi .endmacro .macro CNST16T ; ldi ldi ldi .endmacro .macro CONST16 ; ldi ldi ldi ldi .endmacro .macro CONST20 ; ldi ldi ldi ldi .endmacro
ConstantB (8 bits) r16,byte1(@0) ConstantW (16 bits) r16,byte1(@0) r17,byte2(@0) ConstantT (24 bits) r16,byte1(@0) r17,byte2(@0) r18,byte3(@0) ConstantD (32 bits) r16,byte1(@0) r17,byte2(@0) r18,byte3(@0) r19,byte4(@0) ConstantD (32 bits) r20,byte1(@0) r21,byte2(@0) r22,byte3(@0) r23,byte4(@0)
; *************************************************************************** ;# # # # # # # # # Assign Math32 Symbol and Notation # # # # # # # # # ; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ;* ;* Add32[sign], Sub32[sign], Mul32[b|w|t], Div32[b|w| t] : ;* operand1 operand2 result ;* r20r21r22r23 +|-|*|/ r16r17r18r19 = r20r21r22r23[r24r25r26r27] ;* ;* Com32, Neg32 : Bin2BCD20, BCD2bin20 : ;* operand result operand result ;* r20r21r22r23 >>> r20r21r22r23 r20r21[r22] >>> r20r21[r22] ;* ;* BCD3bin, Bin3BCD, Bin4BCD : Bin2BCD16, BCD2bin16 : ;* operand result operand result ;* r16...r23 >>> r20r21r22[r23[r24]] r16r17 [r18] >>> r20r21[r22] ;* ; *************************************************************************** .set ObXXXX=0b1111 ;default load & store memory variable bitmap upon ;little-endian format of numbers, i.e. abs.address(LSB) < abs.address(MSB) ; *************************************************************************** ;* ;* Initialize Memory in Math Data Space ;* ;* First 512+127 bytes of data space can be initialize in 0 or 0xff ;* Limit: if Flag T==1 then EachMemoryByte=0 else EachMemoryByte=0xff ;* ; *************************************************************************** .def MathPattern=r28 ;YL .def MathCounter=r29 ;YH MathMemLimit: MathMem0x1: ser cpse
brts MathMem0x0 ; MathPattern ; ZH,ZH ;skip next
MathMem0x0: clr mov cbr
MathPattern MathCounter,ZH ZH,0xfe
NextMemByte:
st Z+,MathPattern MathCounter,2 ; NextMemByte ;while
instruction ; ;copy counter ;Z points to math
data space subi brcc
;
MathCounter>=0 ret ; .equ MathMem=MathMem0x0 ;default initialize memory call ; *************************************************************************** ;* ;* Registers Load from Math Data Space ;* ;* Load: r16r17r18r19r20r21r22r23 from first 512+3 bytes of data space ;* operand2 operand1 (max starting address: 0x1ff) ;* ; *************************************************************************** .def MathBmp=r26 ;only XL,XH from high registers .def MathTmp=r27 ;do not keep useful data or not used below R16MathLoad:
ldi
YL,16
;Y points
to operand2 LSB cpse
ZH,ZH
;skip next
instruction R20MathLoad:
ldi
YL,20
;Y points
to operand1 LSB clr mov cbr
YH MathBmp,ZH ZH,0xfe
; ;copy bitmap ;Z points to math
sbr
MathBmp,0xe0
;it is possible in
data space each macrocall MathLoadNext: clr
lsr MathBmp ; MathTmp ;load 0 to temp
register sbrc
MathBmp,0
;if bit 0 bitmap
ld
MathTmp,Z+
;
st
Y+,MathTmp
;store temp to math
sbrc rjmp
MathBmp,4 MathLoadNext
; ;while bit 4 of
not clear load operand
from memory to temp register
bitmap not clear ret ; .equ MathLoad=R20MathLoad ;default registers load call ; *************************************************************************** ;* ;* Registers Save to Math Data Space ;* ;* Save: r20r21r22r23r24r25r26r27 to first 512 +7 bytes of data space ;* result (remainder) (max starting address: 0x1ff) ;* ; *************************************************************************** .def MathBmp=r0 ;all high registers keep useful data or used below sec cpse
ZH,ZH
; ;skip next
mov cbr
clc MathBmp,ZH ZH,0xfe
; ;copy bitmap ;Z points to math
ror
MathBmp
;now bitmap have
ldi
YL,20
;Y points to result
instruction R20MathSave:
data space all 8 bits LSB MathSaveNext: ld
clr YH,Y+
YH
; ;in order to not
use other registers sbrc
MathBmp,0
;if bit 0 bitmap
st
Z+,YH
;
lsr brne
MathBmp MathSaveNext
; ;while not empty
not clear store
result byte to memory
bitmap ret ; .equ MathSave=R20MathSave ;default registers save call ; *************************************************************************** ;* ;* Add32 == 32+32 Bit Unsigned Addition ;* ;* add1L::add1H + add2L::add2H = add1L::add1H ;* item item sum ;* r20r21r22r23 + r16r17r18r19 = r20r21r22r23 ;* ; *************************************************************************** .def add20 = r16 ; item 2 byte 0 (LSB) .def add21 = r17 ; item 2 byte 1 .def add22 = r18 ; item 2 byte 2 .def add23 = r19 ; item 2 byte 3 (MSB) .def add10 = r20 ; item 1 byte 0 (LSB) .def add11 = r21 ; item 1 byte 1 .def add12 = r22 ; item 1 byte 2 .def add13 = r23 ; item 1 byte 3 (MSB) Add32sign: Add32:
brts
Sub32sign ; add add10,add20
;Add low
bytes adc
add11,add21
;Add higher bytes
adc adc ret
add12,add22 add13,add23
; ; ;
with carry
; *************************************************************************** ;* ;* Sub32 == 32-32 Bit Unsigned Subtraction ;* ;* sub1L::sub1H - sub2L::sub2H = sub1L::sub1H ;* minuend subtrahend difference ;* r20r21r22r23 - r16r17r18r19 = r20r21r22r23 ;* ; *************************************************************************** .def sub20 = r16 ; subtrahend byte 0 (LSB) .def sub21 = r17 ; subtrahend byte 1 .def sub22 = r18 ; subtrahend byte 2 .def sub23 = r19 ; subtrahend byte 3 (MSB) .def sub10 = r20 ; minuend byte 0 (LSB) .def sub11 = r21 ; minuend byte 1 .def sub12 = r22 ; minuend byte 2 .def sub13 = r23 ; minuend byte 3 (MSB) Sub32sign: Sub32:
clt sub
;sign + sub10,sub20 ;Subtract
low bytes sbc
sub11,sub21
;Subtract higher
sbc sbc brcc
sub12,sub22 sub13,sub23 Return32u
; ; ;return clear carry
bytes with carry
if result>=0 set Neg32:
;sign -
com com com
subi sub10,1 sub11,0 ; sub12,0 ; sub13,0 ; com sub10 sub11 ; sub12 ; sub13 ;
ret
;
sbci sbci sbci Com32:
;if result<0 neg result (dec result) ; & (com result) return set
carry after com Return32u:
; *************************************************************************** ;* ;* Mul32 == 32x32 Bit Unsigned Multiplication ;* ;* mp32uL::mp32uH x mc32uL::mc32uH = m32uL::m32uH ;* multiplier multiplicand result ;* r20r21r22r23 x r16r17r18r19 = r20r21r22r23r24r25r26r27 ;* ; *************************************************************************** .def mc32u0 =r16 ; multiplicand byte 0 (LSB) .def mc32u1 =r17 ; multiplicand byte 1 .def mc32u2 =r18 ; multiplicand byte 2 .def mc32u3 =r19 ; multiplicand byte 3 (MSB) .def mp32u0 =r20 ; multiplier byte 0 (LSB) .def mp32u1 =r21 ; multiplier byte 1 .def mp32u2 =r22 ; multiplier byte 2 .def mp32u3 =r23 ; multiplier byte 3 (MSB) .def m32u0 =r20 ; result byte 0 (LSB) .def m32u1 =r21 ; result byte 1 .def m32u2 =r22 ; result byte 2 .def m32u3 =r23 ; result byte 3 .def m32u4 =r24 ; result byte 4 .def m32u5 =r25 ; result byte 5 .def m32u6 =r26 ; result byte 6 .def m32u7 =r27 ; result byte 7 (MSB) .def mcnt32u =r28 ; loop counter Mul32b:
clr
mc32u1
;multiplicand is
Mul32w:
clr
mc32u2
;
Mul32t:
clr
mc32u3
;
one byte two bytes three bytes Mul32:
clr
m32u7
;clear 4
highest bytes of result
m32u_loop:
clr clr sub ldi ror
m32u6 m32u5 m32u4,m32u4 mcnt32u,33 m32u3
; ; ;and carry ;init loop counter ;rotate result and
ror ror ror dec
m32u2 m32u1 m32u0 mcnt32u
; ; ; ;decrement loop
breq
Return32u
;if counter zero
brcc
m32u_skip
;if bit 0 of
add
m32u4,mc32u0
;
adc adc adc ror
m32u5,mc32u1 m32u6,mc32u2 m32u7,mc32u3 m32u7
; ; ; ;shift right result
ror ror ror rjmp
m32u6 m32u5 m32u4 m32u_loop
;rotate right result ; ; ;
multiplier
counter return multiplier set add
multiplicand to result
m32u_skip: byte 7
; *************************************************************************** ;* ;* Div32 == 32/32 Bit Unsigned Division ;* ;* dd32uL::dd32uH / dv32uL::dv32uH = dres32uL::dres32uH (drem32uL::drem32uH) ;* dividend divisor result remainder ;* r20r21r22r23 / r16r17r18r19 = r20r21r22r23 r24r25r26r27 ;* ; *************************************************************************** .def dv32u0 =r16 ; divisor byte 0 (LSB) .def dv32u1 =r17 ; divisor byte 1 .def dv32u2 =r18 ; divisor byte 2 .def dv32u3 =r19 ; divisor byte 3 (MSB) .def dres32u0 =r20 ; result byte 0 (LSB) .def dres32u1 =r21 ; result byte 1 .def dres32u2 =r22 ; result byte 2 .def dres32u3 =r23 ; result byte 3 (MSB) .def dd32u0 =r20 ; dividend byte 0 (LSB) .def dd32u1 =r21 ; dividend byte 1 .def dd32u2 =r22 ; dividend byte 2 .def dd32u3 =r23 ; dividend byte 3 (MSB) .def drem32u0 =r24 ; remainder byte 0 (LSB) .def drem32u1 =r25 ; remainder byte 1 .def drem32u2 =r26 ; remainder byte 2 .def drem32u3 =r27 ; remainder byte 3 (MSB) .def dcnt32u =r28 ; loop counter Div32b: Div32w:
clr clr
dv32u1 dv32u2
;divisor is one byte ; two
Div32t:
clr
dv32u3
;
bytes three
bytes Div32:
clr
drem32u0
;clear 4
lower remainde byte
d32u_loop:
clr clr sub ldi rol rol rol rol dec
drem32u1 ; drem32u2 ; drem32u3,drem32u3;and carry dcnt32u,33 ;init loop counter dd32u0 ;shift left dividend dd32u1 ; dd32u2 ; dd32u3 ; dcnt32u ;decrement loop
breq
Com32
;if counter zero
rol
drem32u0
;shift dividend
rol rol rol sub
drem32u1 drem32u2 drem32u3 drem32u0,dv32u0
; ; ; ;remainder =
sbc sbc sbc brcc
drem32u1,dv32u1 drem32u2,dv32u2 drem32u3,dv32u3 d32u_loop
; ; ; ;clear carry to be
add adc
drem32u0,dv32u0 ;if result negative drem32u1,dv32u1 ; restore
adc adc rjmp
drem32u2,dv32u2 ; drem32u3,dv32u3 ; d32u_loop ;
counter invert result into remainder
remainder - divisor
shifted into res
remainder
set carry to be
shifted into res ; *************************************************************************** ;* ;* BCD2bin == BCD to 16-Bit Binary Conversion ;* ;* fBCD0:fBCD1:fBCD2 >>> tbinL:tbinH ;* dec hex ;* r16r17r18 >>> r20r21 ;* ; *************************************************************************** .def fBCD0 =r16 ; BCD value digits 0 and 1 .def fBCD1 =r17 ; BCD value digits 2 and 3 .def fBCD2 =r18 ; BCD value digit 4 (MSD is lowermost nibble) .def mp10L =r20 : Low byte of number to be multiplied by 10 .def mp10H =r21 ; High byte of number to be multiplied by 10 .def tbinL =r20 ; Low byte of binary result (same as mp10L) .def tbinH =r21 ; High byte of binary result (same as mp10H) .def copyL =r22 ; temporary register .def copyH =r23 ; temporary register BCD2bin20:
mov
r16,r20
;for compatibility
BCD2bin16:
mov mov cbr
r17,r21 r18,r22 fBCD2,0xf0
; ; ;mask away upper
mov clr clr
mp10L,fBCD2 mp10H fBCD2
;mp10L:mp10H = MSD ; ;for adci mp10H,0
with Math32
nibble of fBCD2
below rcall mul10bcd ;fBCDX = fBCD1 mov fBCD1,fBCD0 ;fBCDX = fBCD0 mul10bcd: ;mp10L:mp10H=10(10*mp10L:mp10H+highnibble (fBCDX))+lownibble(fBCDX) rcall
mul10add
;10*mp10L:mp10H
+highnibble(fBCDX) mul10add: ;mp10L:mp10H = 10*mp10L:mp10H+lownibble(fBCDX) lsl mp10L ;multiply original by 2 rol mov mov lsl
mp10H copyL,mp10L copyH,mp10H copyL
; ;make copy (x2) ; ;multiply copy by 2
rol lsl
copyH copyL
; ;multiply copy by 2
rol add
copyH mp10L,copyL
; ;add copy to
adc swap
mp10H,copyH fBCD1
; ;fBCDX
mov andi
copyL,fBCD1 copyL,0x0f
; ;mask away upper
add adc
mp10L,copyL mp10H,fBCD2
;add lower nibble ;high byte of
(x4)
(x8)
original (x10)
upper<=>lower nibble
nibble
result + carry ret ; .equ BCD2bin=BCD2bin20 ;default registers BCD to BIN call ; *************************************************************************** ;* ;* BCD3bin == BCD to 24-Bit Binary Conversion ;* ;* fBCD0:fBCD1:fBCD2:fBCD3 >>> tbin0:tbin1:tbin2 ;* dec hex ;* r16r17r18r19 >>> r20r21r22 ;* ; *************************************************************************** .def fBCD0 =r16 ; BCD value digits 0 and 1 .def fBCD1 =r17 ; BCD value digits 2 and 3 .def fBCD2 =r18 ; BCD value digits 4 and 5 .def fBCD3 =r19 ; BCD value digits 6 and 7 (MSD is 0|1) .def tbin0 =r20 ; binary value byte 0 (LSB) .def tbin1 =r21 ; binary value byte 1 .def tbin2 =r22 ; binary value byte 2 (MSB) BCD3bin20:
mov
r16,r20
;for compatibility
r17,r21 r18,r22 r19,r23 tbin0,0xca
; ; ;
BCD3bin16:
mov mov mov ldi ldi
tbin1,0x1b
;-
ldi ;0xff1bca=0xef0bba-0xefeff0 sbrc
fBCD3,4
; delete
subi
fBCD3,6
; if
with Math32
;digit-to-
digit presetting 1111110=0xef0bba tbin2,0xff decimal correction NUMBER<10000000 always bcdbin_106: subi
tbin0,byte1(-1000*1000) ;addit
sbci sbci subi brcc bcdbin_105: subi
tbin1,byte2(-1000*1000) tbin2,byte3(-1000*1000) fBCD3,0x01 bcdbin_106 tbin0,byte1(-100*1000)
; ; ; ; ;addit
sbci sbci subi brcc bcdbin_104: subi
tbin1,byte2(-100*1000) tbin2,byte3(-100*1000) fBCD2,0x10 bcdbin_105 tbin0,byte1(-10*1000)
; ; ; ; ;addit
sbci sbci subi brhc bcdbin_103: subi
tbin1,byte2(-10*1000) tbin2,byte3(-10*1000) fBCD2,0x01 bcdbin_104 tbin0,byte1(-1000)
; ; ; ; ;addit
sbci sbci subi brcc bcdbin_102: subi
tbin1,byte2(-1000) tbin2,byte3(-1000) fBCD1,0x10 bcdbin_103 tbin0,byte1(-100)
; ; ; ; ;addit
sbci sbci subi brhc bcdbin_101: subi
tbin1,byte2(-100) tbin2,byte3(-100) fBCD1,0x01 bcdbin_102 tbin0,byte1(-10)
; ; ; ; ;addit
sbci sbci subi brcc
tbin1,byte2(-10) tbin2,byte3(-10) fBCD0,0x10 bcdbin_101
; ; ; ;addit
add
tbin0,fBCD0
; addend of
adc
tbin1,fBCD1
;
adc
tbin2,fBCD2
; (pre take
tbin,10^6
tbin,10^5
tbin,10^4
tbin,10^3
tbin,10^2
tbin,10^1
tbin,0xefeff0+LSD tbin1 & tbin2 is arbitrarily chosen const off from tbin) ret
http://avr-asm.tripod.com/math32x.html (1 of 3)1/20/2009 8:37:55 PM
16 BIT MATH (AVR 202)
.equ BCD3bin=BCD3bin20 ;default registers BCD to BIN call ; *************************************************************************** ;* ;* Bin2BCD == 16-bit Binary to BCD conversion ;* ;* fbinL:fbinH >>> tBCD0:tBCD1:tBCD2 ;* hex dec ;* r16r17 >>> r20r21r22 ;* ; *************************************************************************** .def fbinL =r16 ; binary value Low byte .def fbinH =r17 ; binary value High byte .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digit 4 (MSD is lowermost nibble) Bin2BCD20:
mov
r16,r20
;for compatibility
mov ldi inc subi sbci brcc ldi
r17,r21 ; tBCD2,0xff ;initialize digit 4 tBCD2 ; fbinL,low(10000);subiw fbin,10000 fbinH,high(10000) binbcd_4 ; tBCD1,0x9f ;initialize digits
subi subi sbci brcs inc subi sbci brcc ldi
tBCD1,0x10 ; fbinL,low(-1000);addiw fbin,1000 fbinH,high(-1000) binbcd_3 ; tBCD1 ; fbinL,low(100) ;subiw fbin,100 fbinH,high(100) ; binbcd_2 ; tBCD0,0xa0 ;initialize digits
with Math32 Bin2BCD16: binbcd_4:
3 and 2 binbcd_3:
binbcd_2:
1 and 0 binbcd_1:
subi tBCD0,0x10 ; subi fbinL,-10 ;addi fbin,10 brcs binbcd_1 ; add tBCD0,fbinL ;LSD binbcd_ret: ret ; .equ Bin2BCD=Bin2BCD20 ;default registers BIN to BCD call ; *************************************************************************** ;* ;* Bin4BCD == 32-bit Binary to BCD conversion [ together with Bin2BCD ] ;* ;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2: tBCD3:tBCD4 ;* hex dec ;* r18r19r20r21 >>> r20r21r22r23r24 ;* ; *************************************************************************** .def fbin0 =r18 ; binary value byte 0 (LSB) .def fbin1 =r19 ; binary value byte 1 .def fbin2 =r20 ; binary value byte 2 .def fbin3 =r21 ; binary value byte 3 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 (same as fbin2) .def tBCD1 =r21 ; BCD value digits 2 and 3 (same as fbin3) .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 .def tBCD4 =r24 ; BCD value digits 8 and 9 (MSD) Bin4BCD:
rcall clr
Bin2BCD20 tBCD3
; ;initial highest
ldi
tBCD4,0xfe ; subi tBCD0,-0x33
bytes of result binbcd_loop:
;add 0x33
to digits 1 and 0 sbrs subi sbrs subi subi
tBCD0,3 tBCD0,0x03 tBCD0,7 tBCD0,0x30 tBCD1,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi subi
tBCD1,3 tBCD1,0x03 tBCD1,7 tBCD1,0x30 tBCD2,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi lsl rol rol rol rol rol rol brmi
tBCD2,3 tBCD2,0x03 tBCD2,7 tBCD2,0x30 fbin0 fbin1 tBCD0 tBCD1 tBCD2 tBCD3 tBCD4 binbcd_loop
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ; ;shift lower word ;through all bytes ; ; ; ; ;7 shifts w/o
rol
fbinH
;since Bin2BCD
brcc
binbcd_ret
;
subi
tBCD3,-0x33
;add 0x33 to digits
sbrs subi sbrs subi subi
tBCD3,3 tBCD3,0x03 tBCD3,7 tBCD3,0x30 tBCD4,-0x03
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x03 to digit
sbrs subi rjmp
tBCD4,3 tBCD4,0x03 binbcd_loop
;if bit 3 clear ; sub 3 ;
3 and 2
5 and 4
correction of MSD fbinH = 0xff so as to do
16_lsl in total 7 and 6
8 only
; *************************************************************************** ;* ;* Bin4BCD == 32-bit Binary to BCD conversion ;* ;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2: tBCD3:tBCD4 ;* hex dec ;* r16r17r18r19 >>> r20r21r22r23r24 ;* ; *************************************************************************** .def fbin0 =r16 ; binary value byte 0 (LSB) .def fbin1 =r17 ; binary value byte 1 .def fbin2 =r18 ; binary value byte 2 .def fbin3 =r19 ; binary value byte 3 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 .def tBCD4 =r24 ; BCD value digits 8 and 9 (MSD) Bin4BCD20:
mov
r16,r20
;for compatibility
Bin4BCD16:
mov mov mov clr
r17,r21 r18,r22 r19,r23 tBCD0
; ; ; ;initial result (5
clr clr ldi
tBCD1 tBCD2 tBCD3,0xfe
; ; ;
rjmp
binbcd_jump
;for speed-up and
binbcd_876: subi
tBCD4,-0x03
;add 0x03 to digit
sbrs subi subi
tBCD4,3 tBCD4,0x03 tBCD3,-0x33
;if bit 3 clear ; sub 3 ;add 0x33 to digits
sbrs subi sbrs subi subi
tBCD3,3 tBCD3,0x03 tBCD3,7 tBCD3,0x30 tBCD2,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi
tBCD2,3 ;if bit 3 clear tBCD2,0x03 ; sub 3 tBCD2,7 ;if bit 7 clear tBCD2,0x30 ; sub $30 subi tBCD1,-0x33 ;add 0x33
with Math32
bytes) & shift loop
counter ldi tBCD4,0xff
;
too
skip of MSD corr 8 only
7 and 6
binbcd_54: 5 and 4
binbcd_3210: to digits 3 and 2 sbrs subi sbrs subi subi
tBCD1,3 tBCD1,0x03 tBCD1,7 tBCD1,0x30 tBCD0,-0x33
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ;add 0x33 to digits
sbrs subi sbrs subi rol rol rol rol rol rol rol rol brcs
tBCD0,3 tBCD0,0x03 tBCD0,7 tBCD0,0x30 lsl fbin0 fbin1 fbin2 fbin3 tBCD0 tBCD1 tBCD2 tBCD3 tBCD4 binbcd_3210
;if bit 3 clear ; sub 3 ;if bit 7 clear ; sub $30 ; ; ; ;shift input value ;through all bytes ; ; ; ; ;16_lsl w/o
inc brpl
fbin0 binbcd_54
; ;+7_lsl w/o
sbrs rjmp
fbin2,0 binbcd_876
; ;32_lsl in total
1 and 0
binbcd_jump:
correction of dig_87654
correction of dig_876
(fbin = 0x1ffff) ret
;
; *************************************************************************** ;* ;* Bin3BCD == 24-bit Binary to BCD conversion [ together with Bin2BCD ] ;* ;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3 ;* hex dec ;* r16r17r18 >>> r20r21r22r23 ;* ; *************************************************************************** .def fbin0 =r16 ; binary value byte 0 (LSB) .def fbin1 =r17 ; binary value byte 1 .def fbin2 =r18 ; binary value byte 2 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 (MSD) Bin3BCD:
ldi
tBCD3,0xff
;initialize
binbcd_7:
inc subi
tBCD3 fbin0,byte1(10000*100)
; ;subit
sbci sbci brcc subi
fbin1,byte2(10000*100) fbin2,byte3(10000*100) binbcd_7 tBCD3,-6
; ; ; ; delete
sbrs
tBCD3,4
; if
subi ldi
tBCD3,6 tBCD2,0x9f
; ;initialize
subi subi
tBCD2,0x10 fbin0,byte1(-10000*10)
; ;addit
sbci sbci brcs inc subi
fbin1,byte2(-10000*10) fbin2,byte3(-10000*10) binbcd_6 tBCD2 fbin0,byte1(10000)
; ; ; ; ;subit
sbci sbci brcc rjmp
fbin1,byte2(10000) fbin2,byte3(10000) binbcd_5 binbcd_3-1
; ; ; ;initialize
digits 7 and 6
fbin,1000000
decimal correction NUMBER<10000000 always
digits 5 and 4 binbcd_6: fbin,100000
binbcd_5: fbin,10000
digits 3 and 2 ; *************************************************************************** ;* ;* Bin3BCD == 24-bit Binary to BCD conversion ;* ;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3 ;* hex dec ;* r16r17r18 >>> r20r21r22r23 ;* ; *************************************************************************** .def fbin0 =r16 ; binary value byte 0 (LSB) .def fbin1 =r17 ; binary value byte 1 .def fbin2 =r18 ; binary value byte 2 (MSB) .def tBCD0 =r20 ; BCD value digits 0 and 1 .def tBCD1 =r21 ; BCD value digits 2 and 3 .def tBCD2 =r22 ; BCD value digits 4 and 5 .def tBCD3 =r23 ; BCD value digits 6 and 7 (MSD) Bin3BCD20:
mov
r16,r20
;for compatibility
r17,r21 r18,r22 tBCD3,0xfa
; ;
Bin3BCD16:
mov mov ldi
with Math32
;initialize
digits 7 and 6 binbcd_107: subi subi
tBCD3,-0x10 ; fbin0,byte1(10000*1000) ;subit
sbci sbci brcc binbcd_106: dec subi
fbin1,byte2(10000*1000) fbin2,byte3(10000*1000) binbcd_107 tBCD3 fbin0,byte1(-10000*100)
; ; ; ; ;addit
sbci sbci brcs ldi
fbin1,byte2(-10000*100) fbin2,byte3(-10000*100) binbcd_106 tBCD2,0xfa
; ; ; ;initialize
binbcd_105: subi subi
tBCD2,-0x10 fbin0,byte1(10000*10)
; ;subit
sbci sbci brcc binbcd_104: dec subi
fbin1,byte2(10000*10) fbin2,byte3(10000*10) binbcd_105 tBCD2 fbin0,byte1(-10000)
; ; ; ; ;addit
fbin1,byte2(-10000) fbin2,byte3(-10000) binbcd_104 tBCD1,0xfa
; ; ; ;initialize
binbcd_103: subi subi
tBCD1,-0x10 fbin0,byte1(1000)
; ;subiw
sbci brcc binbcd_102: dec subi
fbin1,byte2(1000) binbcd_103 tBCD1 fbin0,byte1(-100)
; ; ; ;addiw
sbci brcs ldi
fbin1,byte2(-100) binbcd_102 tBCD0,0xfa
; ; ;initialize
binbcd_101: subi subi
tBCD0,-0x10 fbin0,10
; ;subi
brcc add ret
binbcd_101 tBCD0,fbin0
; ;LSD ;
fbin,10^7
fbin,10^6
digits 5 and 4
fbin,10^5
fbin,10^4 sbci sbci brcs ldi digits 3 and 2
fbin,10^3
fbin,10^2
digits 1 and 0
fbin,10^1
; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Demo: ;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-) (-:-)(-;-)(-:-)(-;-)(-:-) ; *************************************************************************** ;$ $ $ $ $ $ $ $ $ Illustrations with comments field $ $ $ $ $ $ $ $ $ ; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .dseg Variable: .byte 4 VarWord1: .byte 2 VarWord2: .byte 2 Result: .byte 8 .equ Address1 =VarWord1 .equ Address2 =VarWord2 .equ Address =Variable .set Constant =0x4321 .cseg .def Temp =r16 .def TempL =r16 .def TempH =r17 .def Flags =r15 .equ _Flag1 =1 .equ _Flag2 =2 .equ _Flag3 =3 .equ _signResult=0 ;*** OUTI, OUTIW, OUTW, INW outiw SP,Temp,RAMEND
;initialize 16-bit
Stack Pointer outi
TCNT0,Temp,0
;clear Timer/
inw
Temp,TCNT1
;read Timer/
outw
TCNT1,Temp
;write Timer/
Counter0 (8-bit) Counter1 (16-bit) Counter1 (16-bit) ;*** CLF, SEF, CBF, SBF, IBF clf Flags,_Flag1
;clear (0)
bit _Flag1 bld
Flags,_Flag2
;
and
cbf
Flags,Temp,_Flag1,_Flag2 ;clear
sef
Flags,_Flag1
;set (1)
bld
Flags,_Flag2
;
sbf
Flags,Temp,_Flag1,_Flag2 ;set both
ibf
Flags,Temp,_Flag1,_Flag2,_Flag3 ;
ibf
TempL,TempH,0,2,4,6
bit _Flag2 both at once bit _Flag1 and
bit _Flag2 at once invert of 3 flags ;invert
only even bits ;*** XCH, MVW, MVI, MOVS, MOVSW xch TempL,TempH
;swap in Temp
register pair xch
Temp,r0
;swap bytes r0 &
mvw
X,Y
;copy of Y register pair
mvw
Z,Temp
;copy of TempL&TempH into Z
mvi
Flags,Temp,exp2(_Flag1)|1<<_Flag2 ;
mvi
r0,Temp,Constant
;load to
movs
Address1,Temp,Address2
;copy of
movsw
Address1,Temp,Address2
;copy of
Temp into X pair register pair initialize flags low register (0-15) one memory byte two memory bytes ;*** STSI, STSIW, LDSW, STSW stsi Address,Temp,Constant
;initialize
of one memory byte stsiw
Address,Temp,Constant
;initialize
ldsw
Temp,Address1
;copy of two memory
stsw
Address2,Temp
;
of two memory bytes bytes via Temp
register pair ;*** LDIW, LDDW, STDW ldiw Temp,Constant
;initialize of
register pair ldiw
Z,Address
;initialize of
lddw
Temp,Z+(Address1-Address) ;copy of
stdw
Z+(Address2-Address),Temp ;
address pointer two memory bytes via
Temp register pair ;*** PUSHW, POPW pushw
Y
;copy of Y register
popw
X
;
ldiw pushw ret
Temp,Maths Temp
pair into X register
pair
;equ jmp Maths
Maths: ;***** INITMEM InitMem Address
;clear 128 bytes
(latest Address+127) InitMem Address,0 InitMem Address,0,0 InitMem Address,,1
;equ InitMem Address ;equ InitMem Address ;for 128 bytes each:
InitMem Address,1
;clear one byte at
=0xff Address InitMem Address1,Address2-Address1+2,Limit ;limitation: if bit_T=0 then 4_bytes:=0xff else 4_bytes:=0 ldi MathPattern,0xab InitMem Address,,+1 ;128_bytes:=0xab doubly, but possibly ;***** MATHR16, MATHR20, OPERAND Operand Address
;equ MathR20
Address,obXXXX MathR20 Address .set ObXXXX=0b11 MathR16 Address
;equ Operand Address ;equ Operand
Address,0b0011,r16 .set ObXXXX=0b1111 ;default Operand Address,,r16
;equ MathR16
Operand Address,,r20
;equ MathR20
Operand Address,0b11
;equ MathR20
Address,obXXXX Address,obXXXX Address,0b0011 Operand Address,0b11,r16;equ MathR16 Address,0b0011 ;load data with displacement (equ *256, *65536, *16777216) MathR20 Address,0b0110
;(data word)
MathR16 Address,0b1000
;(data byte)
<<8 <<24 ;***** CONST20, CONST16, CNST16T ; WARNING: AVRASM ver. 1.30 don't understand 32 bits constants, but all it ; expressions are internally 32 bits (the higher versions of assembler ; directly operate on value up to 0xffffffff) Const20 0x76543210 ;error v1.30 (0x00003210) Const20 1985229328
;error
Const16 0x7654<<16|0x3210
;ok
v1.30 (12816) (0x76543210) Cnst16t 0x7654*1024*1024+0x1234 ;ok (0x401234) ;***** CNST16B, CNST16W Cnst16b Constant
;equ Const16 byte1
(Constant) rcall
Div32b
;
rcall Div32 ;
but briefly Cnst16w Constant<<1
;non-equ Const16
rcall
;
Constant<<1 Mul32w
rcall
Mul32 ;word overflow ;***** RESULT2, RESULT3 Result2 Address
;equ Result2
Address,obXXXX ;store data with displacement (equ /256, /65536, /16777216 and more) Result2 Address,1<<7 ;(byte result)>>56 Result2 Address,0b111100 ;(double word result)>>16 Result2 Address,obXXXX<<4 ;(double word result)>>32 rjmp JointTail+3 JointTail: Result3 Address,0xff ;equ Result2 Address,0b11111111 rcall JointTail ;concluding RET inside Result call ;******* register pairs .def AL=r16 .def AH=r17 .def BL=r18 .def BH=r19 .def CL=r20 .def CH=r21 .def DL=r22 .def DH=r23 .def WL=r24 .def WH=r25 ldiw C,0 ldiw D,0x7654
;equ ; Const20
0x7654<<16 ldiw ldi mvw mvw adiw
A,0x3210 ;equ Cnst16w 0x3210 AL,0x10 ;equ Cnst16b 0x10 A,C ;copy of Const20 B,D ; into Const16 WL,1 ;as well as "adiw" for X,Y,
sbiw
WL,1
Z register pairs ;as well as "sbiw" for X,Y,
Z register pairs ;******* testing calculations InitMem Variable,4,1
;
0xffffffff to memory Operand Variable Const16 0xffff<<16|0xffff rcall Mul32
;
Result2 Result,0b11111111
;
Operand Variable Const16 0x1010<<16|0x1010 rcall Div32
;
Result2 Result,0b11111111
; 0xf
Operand Variable,0b111 Cnst16t 0x00ff<<16|0xffff rcall Div32t
;
Result2 Result
; 0x1 (0x0
Operand Variable,0b1100 Cnst16w 0xffff rcall Div32w
;
Result2 Result
; 0x10000
0xffffffff * 0xffffffff 0xfffffffe00000001
0xffffffff / 0x10101010 (0x0f0f0f0f)
0xffffff / 0xffffff no rollout)
0xffff0000 / 0xffff (0x0 no rollout) ;******* data translations 16-bit (overall maximum 65535=0xffff) ;result Rd16|24 Const20 rcall Cnst16t rcall Result2 rcall Cnst16w rcall
0x2748 BCD2bin 6<<16|0x5535 BCD2bin16 Address,0b11 Bin2BCD 0xabba Bin2BCD16
;02748 = 0x0abc ;65535 = 0xffff ;0xffff = 65535 ;0xabba = 43962
;******* data translations 32-bit (overall maximum 655359999=0x270fffff) ;BCD2Bin stsiw stsiw
Variable,Temp,0x5432 Variable+2,Temp,0x9876
; ;BCD
98765432 >>> Operand Variable,0b11 rcall BCD2bin pushw C
;temporary result
always is 2 bytes Operand Variable+2,0b11 ;or 0b111 if BCD have all 5 digits rcall ldiw Cnst16w rcall popw
BCD2bin D,0 10000 Mul32w A
;B pair by this
time =0 rcall Add32 Result2 Result,0b1111
;>>> HEX
stsiw stsiw
; ;HEX
0x05e30a78 ;Bin2BCD Variable,Temp,0xffff Variable+2,Temp,0x270f
0x270fffff >>> Operand Variable,0b1111 Cnst16w 10000 ;remainder always is 2 bytes rcall
Div32w
;
as
temporary result rcall Bin2BCD Result2 Result+2,0b111 mvw A,W
;W pair do not
changed beyond rcall Bin2BCD16 Result2 Result,0b11
;>>> BCD
655359999 ;******* 32-bit Bin4BCD conversion (overall maximum 4294967295=0xffffffff) ;result Rd40 ldi
YL,18
;one more dishonest
trick Operand Variable,0b1111,1+ rcall Bin4BCD ;0x270fffff >>> 655359999 Const20 0x1234<<16|0x5678 Result2 18 rcall Bin4BCD ;0x12345678 >>> 305419896 Const16 0xab98<<16|0xfedc mvw C,A rcall Bin4BCD ;0xfedcab98 >>> 4275874712 InitMem MathR20 MathR16 rcall
Variable,3,1 Variable,0b111 Variable,0b111 Mul32t
; 0xffffff to memory
;(0xffffff)^2 =
0xfffffe000001 Result2 18,0b111100
;
/65536 =
rcall
;0xfffffe00 >>>
0xfffffe00 Bin4BCD
4294966784 ;******* data translations 32-bit (overall maximum 4294967295=0xffffffff) ;Bin4BCD20 Operand Variable,0b1111 rcall Bin4BCD20 ;0x27ffffff >>> 671088639 Const20 0x1234<<16|0x5678 rcall Bin4BCD20 ;0x12345678 >>> 305419896 ldiw ldiw rcall
D,0 C,0xab Bin4BCD20
;
rcall
Bin4BCD16
;
0xab >>> 171
;Bin4BCD16 0x1ffff >>>
131071 Const16 0xfedc<<16|0xab98 rcall Bin4BCD16 ;0xfedcab98 >>> 4275874712 InitMem Variable,4,1 MathR16 Variable,0b1111 rcall Bin4BCD16 ;0xffffffff >>> 4294967295 ;******* data translations 24-bit (overall maximum 16777215=0xffffff) ;BCD3bin Const20 $1670<<16|$2650 rcall BCD3bin ;16702650 >>> 0xfedcba ldiw ldiw rcall
B,0 A,9 BCD3bin16
;00000009 >>>
ldiw ldiw rcall
D,0x1599 C,0x9990 BCD3bin20
;15999990 >>>
0x000009 (fastest)
0xf423f6 (slowest) ;Bin3BCD Const16 0x98<<16|0x967f rcall Bin3BCD ;0x98967f >>> 09999999 rcall
Bin3BCD
;0xffff09 >>>
16776969 Cnst16t $0d00*256+$df22 rcall Bin3BCD ;0x0ddf22 >>> 00909090 (fastest) Cnst16t $f500*256+$871d rcall Bin3BCD ;0xf5871d >>> 16090909 (slowest) ;Bin3BCD20 MathR20 Variable,0b111 rcall Bin3BCD20
;0xffffff >>>
rcall
;0x777215 >>>
16777215 Bin3BCD20
07827989 Const20 $a600*256+$75a2 rcall Bin3BCD20 ;0xa675a2 >>> 10909090 (slowest) ;Bin3BCD16 Cnst16t $8a00*256+$b75d rcall Bin3BCD16 ;0x8ab75d >>> 09090909 (fastest) ldi rcall ldi rcall
AH,0xff Bin3BCD16 AL,0 Bin3BCD16
;
0xffff >>> 65535
;0x000000 >>>
00000000 ;******* formula recalculation: Result=(VarWord10xfff)/7+VarWord2/0x100 ;VarWordX>=0 InitMem Variable,16
;clear
rcall
Formula
; -
ldiw
Temp,0xabcd
;these 2
stsw
VarWord1,Temp
;stsiw
stsw rcall
VarWord2,Temp Formula
; 0x16ed.
stsiw stsiw rcall
VarWord1,Temp,0x00ff VarWord2,Temp,0xff00 Formula
; -
stsiw stsiw rcall
VarWord1,Temp,0x0f0f VarWord2,Temp,0xf0f0 Formula
; 0x00ce.
VarWordX & Result 0x249.0000 as result
lines are not equ VarWord1,Temp,0xabcd
cd00 as result
0x125.9249 as result
a6dc as result InitMem VarWord1,4,1
;
ldiw pushw
Temp,Demo Temp
;getting
MathR20 Const16 rcall Cnst16b rcall Result2
VarWord1,0b1100 0xfff<<16 Sub32sign 7 Div32b 16 ;faster than call
0x2349.2392 at the end
into demo loop Formula:
MathR16 20 MathR16 20
;included for
comparison only MathR20 rcall bld Result3
VarWord2,0b110 Add32sign Flags,_signResult Result
.exit ; *************************************************************************** ;* ;* REMARK ;* Sometimes expression as macroparameter must be enclosed in parentheses, ;* because they not are always present in above macrocalls ;* (remember about the priority of AVR assembler operators). ;* Accommodate oneself to ATmega: MOVW instruction e. g., etc. ;* ; *************************************************************************** ;Feedback: please, include abbr."Math32" in Your e-mail subject line (!spam) ;from time to time it is possible mailbox overflow &| shut-down - I am sorry ;to make mention of http://www.i.com.ua/~birua when occasion offers - Thanks ;All the best & good luck!
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 http://avr-asm.tripod.com/math32x.html (2 of 3)1/20/2009 8:37:55 PM
16 BIT MATH (AVR 202)
have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/math32x.html (3 of 3)1/20/2009 8:37:55 PM
AVR MATH YX
The AVR Assembler Site
MATH YX PACKAGE HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202
A V R 2 0 2
************************
ASM MATH
MATH 202
N O T E
Title: Version: Last updated: Target:
16-bit Arithmetics 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This application note lists applications for the
following ;* Add/Subtract/Compare operations: ;* ;* "add16" ADD 16+16 ;* "adddi16" ADD 16+Immediate(16) ;* "sub16" SUB 16-16 ;* "subi16" SUB 16-Immediate(16) ;* "cp16" COMPARE 16/16 ;* "cpi16" COMPARE 16/Immediate ;* "neg16" NEGATION 16 ;* ; ***************************************************************************
MATH 202 DEC ASCII INT ASCII
r16,0x12
;Set up some registers to
ldi ldi
r17,0x34 r18,0x56
;the subroutines below. ;All expected results are
ldi
r19,0x78
;comments
show usage of
HX2ASC AVG8 222
.cseg ldi
presented as
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
; *************************************************************************** ;* ;* "add16" - Adding 16-bit registers ;* ;* This example adds the two pairs of register variables (add1l,add1h) ;* and (add2l,add2h) The result is placed in (add1l, add1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
AVR ISP
;**** Register Variables .def add1l = r16 .def add1h = r17 .def add2l = r18 .def add2h = r19
ISP 2313 ISP 1200 AVR SPI I2C 300
;***** Code add16: add
I2C 302 I2C TWI26 I2C/TWI 128
add1l, add2l
;Add low
bytes adc
add1h, add2h
;Add high bytes
with carry ;Expected result is 0xAC68
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;* ;* "addi16" - Adding 16-bit register with immediate ;* ;* This example adds a register variable (addi1l, addi1h) with an ;* immediate 16-bit number defined with .equstatement. The result is ;* placed in (addi1l, addi1h). ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The sum and the addend share the same register. This causes the ;* addend to be overwritten by the sum. ;* ; ***************************************************************************
PS2 EMU
;***** Register Variables .def addi1l = r16 .def addi1h = r17
BOOT MG8 BOOT DR8 ALM CLK
;***** Immediate 16-bit number .equ addi2 = 0x1234
CLOCK 8564 90 DAYS
;***** Code addi16: subi
DELAYS CALL ID DTMF 314
add1l, low(-addi2)
;Add low
byte ( x -(-y)) = x + y sbci
add1h, high(-addi2)
;Add high byte with
carry ;Expected result is 0xBE9C
PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* "sub16" - Subtracting 16-bit registers ;* ;* This example subtracts two pairs of register variables (sub1l,sub1h) ;* from (sub2l, sub2h) The result is stored in registers sub1l, sub1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The result and "sub1" share the same register. This causes "sub1" ;* to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def sub1l = r16 .def sub1h = r17 .def sub2l = r18 .def sub2h = r19 ;***** Code sub16: sub
sub1l,sub2l
;Subtract
low bytes sbc
sub1h,sub2h
;Add high byte with
carry ;Expected result is 0x4646
; *************************************************************************** ;* ;* "subi16" - Subtracting immediate 16-bit number from a 16-bit register ;* ;* This example subtracts the immediate 16-bit number subi2 from the ;* 16-bit register (subi1l,subi1h) The result is placed in registers ;* subi1l, subi1h. ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :2 ;* ;* Note: The result and "subi1" share the same register. This causes ;* "subi1" to be overwritten by the result. ;* ; *************************************************************************** ;***** Register Variables .def subi1l = r16 .def subi1h = r17 ;***** Immediate 16-bit number .equ subi2 = 0x1234 ;***** Code subi16: subi
subi1l,low(subi2)
;Subtract
low bytes sbci
subi1h,high(subi2)
;Subtract high byte
with carry ;Expected result is 0x3412
; *************************************************************************** ;* ;* "cp16" - Comparing two 16-bit numbers ;* ;* This example compares the register pairs (cp1l,cp1h) with the register ;* pairs (cp2l,cp2h) If they are equal the zero flag is set(one) ;* otherwise it is cleared(zero) ;* ;* Number of words :2 ;* Number of cycles :2 ;* Low registers used :None ;* High registers used :4 ;* ;* Note: The contents of "cp1" will be overwritten. ;* ; *************************************************************************** ;***** Register Variables .def cp1l = r16 .def cp1h = r17 .def cp2l = r18 .def cp2h = r19 ;***** Code cp16: cp cp1l,cp2l ;Compare low byte cpc cp1h,cp2h ;Compare high byte with carry from ;previous operation ncp16: ;Expected result is Z=0
; *************************************************************************** ;* ;* "cpi16" - Comparing 16-bit register with 16-bit immediate ;* ;* This example compares the register pairs (cpi1l, cpi1h) with the value ;* cpi2. If they are equal the zero flag is set(one), otherwise it is ;* cleared(zero). This is enabled by the AVR's zero propagation. Carry is ;* also set if the result is negative. This means that all conditional ;* branch instructions can be used after the comparison. ;* ;* Number of words :3 ;* Number of cycles :3 ;* Low registers used :None ;* High registers used :3 ;* ;* ; *************************************************************************** ;***** Register Variables .def cp1l =r16 .def cp1h =r17 .def c_tmp=r18 .equ cp2 = 0x3412
;Immediate to compare with
;***** Code cpi16: cpi cp1l,low(cp2) ;Compare low byte ldi c_tmp,high(cp2) ; cpc cp1h,c_tmp ;Compare high byte ;Expected result is Z=1, C=
; *************************************************************************** ;* ;* "neg16" - Negating 16-bit register ;* ;* This example negates the register pair (ng1l,ng1h) The result will ;* overwrite the register pair. ;* ;* Number of words :4 ;* Number of cycles :4 ;* Low registers used :None ;* High registers used :2 ;* ; *************************************************************************** ;***** Register Variables .def ng1l = r16 .def ng1h = r17 ;***** Code ng16: com ng1l
;Invert low byte
;
Calculated by com
ng1h
;Invert high byte
;
subi
ng1l,low(-1)
;Add 0x0001, low byte
;
sbci
ng1h,high(-1)
;Add high byte
;
incverting all bits then adding one (0x0001) ;Expected result is 0xCBEE
; *************************************************************************** ;* ;* End of examples. ;* ; ***************************************************************************
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, http://avr-asm.tripod.com/mathyx.html (1 of 2)1/20/2009 8:38:35 PM
AVR MATH YX
the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/mathyx.html (2 of 2)1/20/2009 8:38:35 PM
AVR MATH YX
The AVR Assembler Site
DIV16 XX PACKAGE HOME RETRO_DAN ASM FORUM
; DIVISION ROUTINES with scaled reciprocals for constants ; (all functions optimized for speed, ~ <36 cycles w/o push/pop)
ASM MATH TUTORIAL #1
; Target: AVR MCUs with hardware multiplier ("mul" instruction) ; Author: Andreas Lenze ([email protected]) ; Feb. 2003
TUTORIAL #2 TUTORIAL #3 MATH 200
;div. by n: n: scaled reciprocal:
shift count:
;Div16_3 ;Div16_5 ;Div16_6 ;Div16_7 ;Div16_7a
3 5 6 7 7
1010101010101011 AAAB 1100110011001101 CCCD 1010101010101011 AAAB 10010010010010011 1001001001001001 9249
17 18 18 19 -> 17 bits req'd,(MSB=1,rest 2493h) 18 -> needs correction for accurate
;Div16_9 ;Div16_10 ;Div16_11 ;Div16_12 ;Div16_13 ;Div16_14 ;Div16_15 ;Div16_17 ;Div16_18 ;Div16_19 ;Div16_20 ;Div16_21
9 10 11 12 13 14 15 17 18 19 20 21
1110001110001111 E38F 1100110011001101 CCCD 1011101000101111 BA2F 1010101010101011 AAAB 1001110110001010 9D8A 10010010010010011 1000100010001001 8889 1111000011110001 F0F1 1110001110001111 E38F 0110101111001011 6BCB 1100110011001101 CCCD 1100001100001011 C30B
19 19 19 19 19 20 -> 17 bits req'd,(MSB=1,rest 2493h) 19 20 20 19 20 20 -> needs correction for accurate
;Div16_22 ;Div16_23
22 1011101000101111 BA2F 23 1011001000010101 B215
MATH 200b MATH 201 MATH 202 MATH 32X MATH YX
result
DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII
result
HX2ASC AVG8 222
20 20 -> needs correction for accurate
result
FFT7
;D16_nn(by) 2-23 -> "C-style" function with macro 'Div16by' to perform a ; constants division with all divisors from 2 to 23. Price ; tag for the comfort is ~50 cycles / ~50 words overhead
COPY 102 LPM 108 EPROM 100
; NOTE: Other divisor constants like /24 etc. can easily be created by ; modifying the shift count in "Q = Q >> x": add 1 shift right for ; 'divisor x 2' (e.g. for "/24" we need a total of 20 instead of ; the 19 shifts needed for "/12")
SER EPROM DFLASH AT45 FLASH CARD
; ; ; ;
VFX SMIL VFX MEM SORT 220 CRC 236
r19:r18 now "Q" (= result >> xx)
; R = A - xx*Q (start removal ; ldi r16,xx ; .... ; sbc XH,YH (end removal) ; ; may be omitted to save another 9 cycles / 7 words ; (* not applicable for 'Div16_7a' - remainder is always needed *) ; ; "Div16_7a" and "Div16_21/3" demonstrate and use the 'approximate and
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
If the remainder of the division is not needed, the multiply/subtract operation after the comment
correct'
AVR ISP ISP 2313
; technique which may be necessary for some larger divisors (e.g. /21, /23) ;---------------------------------------------------------------------------
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
;*************************************************************************** ;* ;* Function "Div16_3" ;* Divides an unsigned 16 bit word (XH:XL) by 3 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xAAAB; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xAAAB) >> 17) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 10 words) ;* cycles: 48 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_3: push push push push
KBD PC/128
ldi ldi
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE
r2 r19 r18 r17 YH,0xAA YL,0xAB
; scaled reciprocal for /3
; Q = A * 0xAAAB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2
STH-11
; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 1 lsr r19 ; do the last shift ror r18
ATMEL CORP AVR BUTTERFLY
; r19:r18 now "Q" (= result >> 17) ; R = A - 3*Q; ldi r17,3 ; multiply r19:r18 by 3 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q
AVR BOOK
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_3 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_5" ;* Divides an unsigned 16 bit word (XH:XL) by 5 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xCCCD; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xCCCD) >> 18) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 54 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_5: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xCC YL,0xCD
; scaled reciprocal for /5
; Q = A * 0xCCCD ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 2 lsr r19 ; do the last 2 shifts ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 18) ; R = A - 5*Q; ldi r17,5 ; multiply r19:r18 by 5 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_5 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_6" ;* Divides an unsigned 16 bit word (XH:XL) by 6 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xAAAB; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xAAAB) >> 18) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 54 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_6: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xAA YL,0xAB
; scaled reciprocal for /6
; Q = A * 0xAAAB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 2 lsr r19 ; do the last 2 shifts ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 18) ; R = A - 6*Q; ldi r17,6 ; multiply r19:r18 by 6 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_6 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_7" ;* Divides an unsigned 16 bit word (XH:XL) by 7 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x2493; ;* unsigned int Q; /* the quotient */ ;* ;* Q = (((A * 0x2493) >> 16) + A) >> 3 -> 17 bits reciprocal! ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_7: push push push push
r2 r19 r18 r17
ldi ldi
YH,0x24 YL,0x93
; scaled reciprocal for /7
; Q = A * 0x2493 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q + A add r18,XL adc r19,XH ; Q = Q >> 3 ror r19 ror r18 lsr r19 ror r18 lsr r19 ror r18
; do the last 3 shifts, including ; carry (!) from previous addition
; r19:r18 now "Q" (= result >> 19) ; R = A - 7*Q; ldi r17,7 ; multiply r19:r18 by 7 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_7 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_7a" ;* Divides an unsigned 16 bit word (XH:XL) by 7 ;* Call with 16 bit number in XH:XL ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* (Equations partly by D. W. Jones) ;* ;* Reciprocal multiplication w. extra precision: ;* (This version uses correction to achieve the required precision) ;* unsigned int R; /* remainder */ ;* unsigned int long A; /* dividend */ ;* unsigned int long Q; /* quotient */ ;* ;* Q = ((A * 0x9249) >> 18) ;* ;* /* Q = A/7 or Q+1 = A/7 for all A <= 65535 */ ;* /* correct Q and calculate remainder */ ;* R = A - 7*Q ;* if (R >= 7) { ;* R = R - 7; ;* Q = Q + 1; ;* } ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 59 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_7a: push r2 push r19 push r18 push r17
; Tmp3 ; Tmp2
ldi ldi
; scaled reciprocal for /7 ; (16 bit only, 0/-1 error possible)
YH,0x92 YL,0x49
; Q = A * 0x9249 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 2 lsr r19 ; 2 shifts remaining ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 18) ; R = A - 7*Q; ldi r17,7 ; multiply r19:r18 by 7 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of current Q ; XH:XL ; if (R ; ; cpi brlo subi adiw
now "R": >= 7) R = R - 7; Q = Q + 1; XL,0x07 PC+3 XL,7 YL,1
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_7a -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_9" ;* Divides an unsigned 16 bit word (XH:XL) by 9 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xE38F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xE38F) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_9: push push push push ldi ldi
r2 r19 r18 r17 YH,0xE3 YL,0x8F
; scaled reciprocal for /9
; Q = A * 0xE38F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 9*Q; ldi r17,9 ; multiply r19:r18 by 9 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_9 ------------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_10" ;* Divides an unsigned 16 bit word (XH:XL) by 10 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xCCCD; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xCCCD) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_10: push push push push ldi ldi
r2 r19 r18 r17 YH,0xCC YL,0xCD
; scaled reciprocal for /10
; Q = A * 0xCCCD ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 10*Q; ldi r17,10 ; multiply r19:r18 by 10 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_10 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_11" ;* Divides an unsigned 16 bit word (XH:XL) by 11 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xBA2F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xBA2F) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_11: push push push push ldi ldi
r2 r19 r18 r17 YH,0xBA YL,0x2F
; scaled reciprocal for /11
; Q = A * 0xBA2F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 11*Q; ldi r17,11 ; multiply r19:r18 by 11 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_11 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_12" ;* Divides an unsigned 16 bit word (XH:XL) by 12 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xAAAB; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xAAAB) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_12: push push push push ldi ldi
r2 r19 r18 r17 YH,0xAA YL,0xAB
; scaled reciprocal for /12
; Q = A * 0xAAAB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 12*Q; ldi r17,12 ; multiply r19:r18 by 12 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_12 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_13" ;* Divides an unsigned 16 bit word (XH:XL) by 13 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x9D89; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0x9D8A) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_13: push push push push ldi ldi
r2 r19 r18 r17 YH,0x9D YL,0x8A
; scaled reciprocal for /13
; Q = A * 0x9D8A ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 13*Q; ldi r17,13 ; multiply r19:r18 by 13 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_13 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_14" ;* Divides an unsigned 16 bit word (XH:XL) by 14 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x2493; ;* unsigned int Q; /* the quotient */ ;* ;* Q = (((A * 0x2493) >> 16) + A) >> 4 -> 17 bits reciprocal! ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 40 (w. push/pop = 8 words) ;* cycles: 44 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_14: push push push push ldi ldi
r2 r19 r18 r17 YH,0x24 YL,0x93
; scaled reciprocal for /7, /14
; Q = A * 0x2493 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0
http://avr-asm.tripod.com/div16xx.html (1 of 3)1/20/2009 8:39:37 PM
AVR MATH YX
mul
XL, YL mov r17,r1 mul XH, YL add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL add r17, r0 adc r18, r1 adc r19, r2
; al * bl ; r0 to [rXX] is superfluous ; ah * bl
; bh * al
; Q = Q >> 16: use r19:r18 as word ; Q = Q + A add r18,XL adc r19,XH ; Q = Q >> 4 ror r19 ror r18 lsr r19 ror r18 lsr r19 ror r18 lsr r19 ror r18
; do the last 4 shifts, including ; carry (!) from previous addition
; r19:r18 now "Q" (= result >> 20) ; R = A - 14*Q; ldi r17,14 ; multiply r19:r18 by 14 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_14 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_15" ;* Divides an unsigned 16 bit word (XH:XL) by 15 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x8889; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0x8889) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_15: push push push push
r2 r19 r18 r17
ldi ldi
YH,0x88 YL,0x89
; scaled reciprocal for /15
; Q = A * 0x8889 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 15*Q; ldi r17,15 ; multiply r19:r18 by 15 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_15 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_17" ;* Divides an unsigned 16 bit word (XH:XL) by 17 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xF0F1; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xF0F1) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 44 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_17: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xF0 YL,0xF1
; scaled reciprocal for /17
; Q = A * 0xF0F1 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 17*Q; ldi r17,17 ; multiply r19:r18 by 17 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_17 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_18" ;* Divides an unsigned 16 bit word (XH:XL) by 18 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xE38F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xE38F) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 38 (w. push/pop = 10 words) ;* cycles: 44 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_18: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xE3 YL,0x8F
; scaled reciprocal for /9 /18
; Q = A * 0xE38F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 18*Q; ldi r17,18 ; multiply r19:r18 by 18 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_18 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_19" ;* Divides an unsigned 16 bit word (XH:XL) by 19 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0x6BCA; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0x6BCB) >> 19) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_19: push push push push
r2 r19 r18 r17
ldi ldi
YH,0x6B YL,0xCB
; scaled reciprocal for /19
; Q = A * 0x6BCB ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 3 lsr r19 ; do the last 3 shifts ror r18 lsr r19 ror r18 lsr r19 ror r18 ; r19:r18 now "Q" (= result >> 19) ; R = A - 19*Q; ldi r17,18 ; multiply r19:r18 by 18 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_19 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_20" ;* Divides an unsigned 16 bit word (XH:XL) by 20 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xCCCD; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xCCCD) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_20: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xCC YL,0xCD
; scaled reciprocal for /10, /20
; Q = A * 0xCCCD ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 20*Q; ldi r17,20 ; multiply r19:r18 by 20 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_20 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_21" ;* Divides an unsigned 16 bit word (XH:XL) by 21 ;* Call with 16 bit number in XH:XL ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* (Equations partly by D. W. Jones) ;* ;* Reciprocal multiplication w. extra precision: ;* (uses correction to achieve the required precision) ;* unsigned int R; /* remainder */ ;* unsigned int long A; /* dividend */ ;* unsigned int long Q; /* quotient */ ;* ;* Q = ((A * 0xC30B) >> 20) ;* ;* /* Q = A/21 or Q+1 = A/21 for all A <= 65535 */ ;* /* correct Q and calculate remainder */ ;* R = A - 21*Q ;* if (R >= 21) { ;* R = R - 21; ;* Q = Q + 1; ;* } ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 40 (w. push/pop = 8 words) ;* cycles: 52 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_21: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xC3 YL,0x0B
; scaled reciprocal for /21 ; (16 bit only, 0/-1 error possible)
; Q = A * 0xC30B ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 21*Q; ldi r17,21 ; multiply r19:r18 by 21 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of current Q ; XH:XL ; if (R ; ; cpi brlo subi adiw
now "R": >= 21) R = R - 21; Q = Q + 1; XL,0x15 PC+3 XL,21 YL,1
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_21 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_22" ;* Divides an unsigned 16 bit word (XH:XL) by 22 ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* Equations by D: W. Jones: ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = 0xBA2F; ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * 0xBA2F) >> 20) ;* ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 46 (w. push/pop = 16 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_22: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xBA YL,0x2F
; scaled reciprocal for /11, /22
; Q = A * 0xBA2F ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 22*Q; ldi r17,22 ; multiply r19:r18 by 22 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of Q ; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_22 -----------------------------------------****
;*************************************************************************** ;* ;* Function "Div16_23" ;* Divides an unsigned 16 bit word (XH:XL) by 23 ;* Call with 16 bit number in XH:XL ;* Returns quotient in YH:YL and remainder in XL ;* ;* Author: Andreas Lenze ([email protected]) ;* (Equations partly by D. W. Jones) ;* ;* Reciprocal multiplication w. extra precision: ;* (uses correction to achieve the required precision) ;* unsigned int R; /* remainder */ ;* unsigned int long A; /* dividend */ ;* unsigned int long Q; /* quotient */ ;* ;* Q = ((A * 0xB215) >> 20) ;* ;* /* Q = A/23 or Q+1 = A/23 for all A <= 65535 */ ;* /* correct Q and calculate remainder */ ;* R = A - 1*Q ;* if (R >= 23) { ;* R = R - 23; ;* Q = Q + 1; ;* } ;* Uses: high regs: 7 (r17, r18, r19, X, Y) ;* low regs: 3 (r0, r1, r2) ;* ;* words: 36 (w. push/pop = 8 words) ;* cycles: 59 (w. push/pop = 20 cycles) ;* ;* Note: Hardware multiplier required ("mul" instruction) ;* ;*************************************************************************** Div16_23: push push push push
r2 r19 r18 r17
ldi ldi
YH,0xB2 YL,0x15
; scaled reciprocal for /23 ; (16 bit only, 0/-1 error possible)
; Q = A * 0xB215 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL) clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to [rXX] is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; Q = Q >> 4 swap r18 ; do the last 4 shifts swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 ; r19:r18 now "Q" (= result >> 20) ; R = A - 23*Q; ldi r17,23 ; multiply r19:r18 by 23 mul r18, r17 ; al * bl sub XL,r0 clr XH movw YL,r18 ; make copy of currentQ ; XH:XL ; if (R ; ; cpi brlo subi adiw
now "R": >= 23) R = R - 23; Q = Q + 1; XL,0x17 PC+3 XL,23 YL,1
; XL holds "R" ; YH:YL holds "Q" pop r17 pop r18 pop r19 pop r2 ret ;**** End of function Div16_23 -----------------------------------------****
;*************************************************************************** ; macro definition to call/use "division by xx" - module (D16_nn) macro Div16by push r20 ldi r20,@0 call D16_nn pop r20 .endm ;***************************************************************************
;*************************************************************************** ;* ;* Function "D16_nn" ;* Divides an unsigned 16 bit word by [2] -> [23] ;* Note: divisor 2, 4, 8, 16 options are provided for remainder calculation ;* and (for ease-of-use) to cover the complete divisors range (2-23) ;* ;* Call with dividend loaded to XH:XL (high/low bytes) ;* Returns quotient in YH:YL and remainder in XL ;* ;* Usage: define the macro "Div16by" prior to using the function, ;* use macro with divisor as parameter, e.g. "Div16by 17" to ;* divide XH:XL by 17 decimal ;* ;* .macro Div16_by ;* push r20 ;* ldi r20,@0 ;* call D16_nn ;* pop r20 ;* .endm ;* ;* Author: Andreas Lenze ([email protected]) ;* Feb. 2003 ;* Equations mostly by D. W. Jones ;* ;* Reciprocal mul w. extra precision: ;* unsigned int A; ;* unsigned int scaled_reciprocal = xxxx ;* unsigned int Q; /* the quotient */ ;* ;* Q = ((A * scaled_reciprocal) >> 16) >> nn ;* or ;* Q = (((A * scaled_reciprocal) >> 16) + A) >> nn -> for /7 and /14 ;* ;* /* special case: use correction for Q (e.g. for /21, /23) */ ;* if (R >= divisor) ;* R = R - divisor; ;* Q = Q + 1; ;* ;* div. by n: scaled reciprocal: shift count: ;* ;* 2 1 ;* 3 1010101010101011 AAAB 17 ;* 4 2 ;* 5 1100110011001101 CCCD 18 ;* 6 1010101010101011 AAAB 18 ;* 7 10010010010010011 19 -> 17 bits req'd,(MSB=1,rest 2493h) ;* 8 3 ;* 9 1110001110001111 E38F 19 ;* 10 1100110011001101 CCCD 19 ;* 11 1011101000101111 BA2F 19 ;* 12 1010101010101011 AAAB 19 ;* 13 1001110110001010 9D8A 19 ;* 14 10010010010010011 20 -> 17 bits req'd,(MSB=1,rest 2493h) ;* 15 1000100010001001 8889 19 ;* 16 4 ;* 17 1111000011110001 F0F1 20 ;* 18 1110001110001111 E38F 20 ;* 19 0110101111001011 6BCB 19 ;* 20 1100110011001101 CCCD 20 ;* 21 1100001100001011 C30B 20 -> needs correction for accurate result ;* ;*
22 1011101000101111 BA2F 23 1011001000010101 B215
20 20 -> needs correction for accurate
result ;* ;* Uses: high regs: 11 (r16, r17, r18, r19, r20, X, Y, Z) ;* low regs: 3 (r0, r1, r2) ;* regs 16-20 saved, all others destroyed ;* T-flag destroyed (cleared) ;* ;* words: 97 (incl. 5 words for macro) ;* cycles: 85-111 (w. call/ret & macro), typically 102 ;* table bytes: 66 ;* ;* Target: AVR MCUs with hardware multiplier ("mul" instruction and ;* "lpm rd,Z/Z+" functionality required) ;* ;***************************************************************************
D16_nT: ; look-up table for D16_nn: 3 bytes per entry, range for divisor "2" to "23" ; data format: 2 bytes scaled reciprocal (word, high/low), 3rd byte "flags" .cseg .db 0x00, 0xFF, 0x01, 0xAA, 0xAB, 0x01, 0x00, 0xFF, 0x02, 0xCC, 0xCD, 0x02, 0xAA, 0xAB ; by /2
/3
/4
/5
/6
.db 0x02, 0x24, 0x93, 0x13, 0x00, 0xFF, 0x03, 0xE3, 0x8F, 0x03, 0xCC, 0xCD, 0x03, 0xBA ; by
/7
/8
/9
/10
/11
.db 0x2F, 0x03, 0xAA, 0xAB, 0x03, 0x9D, 0x8A, 0x03, 0x24, 0x93, 0x14, 0x88, 0x89, 0x03 ;by
/12
/13
/14
/15
.db 0x00, 0xFF, 0x04, 0xF0, 0xF1, 0x04, 0xE3, 0x8F, 0x04, 0x6B, 0xCB, 0x03, 0xCC, 0xCD ; by /16
/17
/18
/19
/20
.db 0x04, 0xC3, 0x0B, 0x04, 0xBA, 0x2F, 0x04, 0xB2, 0x15, 0x04 ;by /21 /22 /23 D16_nn: push push
r19
; save scrap regs
r18 push push
r17 r16
clt push cpi brsh subi brmi
r20 r20,24 D16_0 r20,2 D16_0
ldi ldi clr mov lsl add add adc
ZH,high(D16_nT*2) ZL,low(D16_nT*2) r2 r1,r20 r20 ; x2 (3 bytes per entry) r20,r1 ; + org value = x3 ZL,r20 ; point Z to divisor's data table position ZH,r2
lpm lpm cpi
YH,Z+ YL,Z+ YL,0xFF
brne mov mov rjmp
D16_1 r19,XH r18,XL D16_2
; ; ; ; ; ; ; ;
pop r20 D16_Err
; clean up stack before exit ; intermediate label (avoid "out of reach" for
D16_0: rjmp
; make sure T-flag is cleared ; save divisor ; exit if divisor > 23
; exit if divisor <= 1
scaled reciprocal for /xx Z now points at flags low byte "FFh" in the scaled_reciprocal data indicates divisor 2, 4, 8, 16 -> no 'mul' req. != FFh -> mul required FFh: no div., shifts only: move input to "result registers" and go to shifts directly (saves ~18 cycles)
brxx) ; Q = A * scaled_reciprocal ; (r19:r18:r17:r16 = XH:XL * YH:YL) D16_1: clr r2 mul XH, YH ; ah * bh movw r19:r18, r1:r0 mul XL, YL ; al * bl mov r17,r1 ; r0 to r16 is superfluous mul XH, YL ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul YH, XL ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ; Q = Q >> 16: use r19:r18 as word ; do the remaining shifts D16_2: lpm r20,Z ; fetch "flag" cpi breq
r20,3 D16_6
; flag = 3 -> 3 normal shifts required ; (div. 8, 9, 10, 11, 12, 13, 15, 19)
cpi breq
r20,4 D16_3
; flag = 4 -> 4 normal shifts required ; (div. 16, 17, 18, 20, 21, 22, 23)
cpi breq
r20,2 D16_7
; flag = 2 -> 2 normal shifts required ; (div. 4, 5, 6)
cpi breq
r20,1 D16_8
; flag = 1 -> 1 normal shift required ; (div. 2, 3)
cpi breq
r20,0x14 D16_5
; flag = 4spec -> 4 special shifts required ; (div. 14, extra addition, 1st shift w. carry)
cpi breq rjmp
r20,0x13 D16_4 D16_Err
; flag = 3spec -> 3 special shifts required ; (div. 7, extra addition, 1st shift w. carry) ; no valid flags, exit
; Q = Q >> 4 D16_3: swap r18 swap r19 andi r18,0x0F eor r18,r19 andi r19,0x0F eor r18,r19 rjmp D16_9
http://avr-asm.tripod.com/div16xx.html (2 of 3)1/20/2009 8:39:37 PM
; 4 normal shifts
AVR MATH YX
; Q = (Q + A) >> 3-4 D16_4: set D16_5: add r18,XL adc r19,XH ror r19 ror r18 D16_6: lsr r19 ror r18 D16_7: lsr r19 ror r18 brts D16_9 D16_8: lsr r19 ror r18
; (Q + A) ; 3-4 "special" shifts, include ; carry from previous addition into 1st shift
; if T-flag set, skip this shift
; r19:r18 now "Q" (= result >> yy) ; R = A - xx*Q; D16_9: pop r16 ; multiply r19:r18 by divisor mul sub clr movw
r18, r16 XL,r0 XH YL,r18
; al * bl
; make copy of Q
; XL = "R" (remainder) ; /* use correction - can be omitted if /21, /23 are not used */ ; if (R >= divisor) ; R = R - divisor; ; Q = Q + 1; cp XL,r16 brlo PC+3 sub XL,r16 adiw YL,1 ; YH:YL = "Q" (quotient, result) D16_Err:clt ; make sure T-flag is cleared pop r16 ; restore regs pop r17 pop r18 pop r19 ret ;**** End of function D16_nn -------------------------------------------****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/div16xx.html (3 of 3)1/20/2009 8:39:37 PM
AVR MATH YX
The AVR Assembler Site
24 BIT BY 24 BIT DIVISION ROUTINE HOME RETRO_DAN ;******** div24u *********** ;*Division 24/24 ;* Dividend(dvd) ;* Result = --------------;* Divisor(dvr) ;* ;*
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200
.def .def .def .def .def .def .def .def .def .def .def .def
MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128
rem24L =r3 rem24M =r4 rem24H =r5 result24L =r9 result24M =r10 result24H =r11 dvd24L =r9 dvd24M =r10 dvd24H =r11 dvr24L =r12 dvr24M =r13 dvr24H =r14
;*Unsigned* Division 24bit/24bit
SQRT16 div24u: clr rem24L ;clear remainder Low byte clr rem24M ;clear remainder mid byte sub rem24H,rem24H ;clear remainder High byte and
MATH 202 MATH 202 DEC ASCII
carry ldi rLoopCnt1,25 ;init loop counter
INT ASCII d16u_1: rol dvd24L ;shift left dividend rol dvd24M rol dvd24H dec rLoopCnt1 ;decrement counter brne d16u_2 ;if done ret ; return
HX2ASC AVG8 222 FFT7 COPY 102 LPM 108
d16u_2: rol rem24L ;shift dividend into remainder rol rem24M rol rem24H sub rem24L,dvr24L ;remainder = remainder - divisor sbc rem24M,dvr24M ; sbc rem24H,dvr24H brcc d16u_3 ;if result negative add rem24L,dvr24L ; restore remainder adc rem24M,dvr24M adc rem24H,dvr24H clc ; clear carry to be shifted into result rjmp d16u_1 ;else d16u_3: sec ; set carry to be shifted into result rjmp d16u_1
EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
ret
UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
Programming the AVR Microcontrollers in Machine Language
I2C/TWI 128 I2C/TWI AT8
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/div2424.html (1 of 2)1/20/2009 8:40:09 PM
AVR MATH YX
http://avr-asm.tripod.com/div2424.html (2 of 2)1/20/2009 8:40:09 PM
AVR MATH YX
The AVR Assembler Site
32 BIT BY 16 BIT DIVISION ROUTINE HOME RETRO_DAN ASM FORUM
;divide r21:r18/refH:refL result in XH: XL
ASM MATH
__DIVD21U: CLR XL CLR XH CLR R0 CLR R1 LDI R17,32 __DIVD21U1: LSL R18 ROL R19 ROL R20 ROL R21 ROL XL ROL XH ROL R0 ROL R1 SUB XL,scaleL SBC XH,scaleH SBC R0,zeroreg SBC R1,zeroreg BRCC __DIVD21U2 ADD XL,scaleL ADC XH,scaleH ADC R0,zeroreg ADC R1,zeroreg RJMP __DIVD21U3 __DIVD21U2: SBR R18,1 __DIVD21U3: DEC R17 BRNE __DIVD21U1 mov XL, r19 mov XH, r18 ; result in X
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102
ret
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
Programming the AVR Microcontrollers in Machine Language
UART 305
AVR << Prev | Ring Hub | Join | Rate| Next >>
UART 128 UART BUFF USB 232 © WebRing Inc.
AVR ISP
Search
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232, RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232, RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232, RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/div3216.html (1 of 2)1/20/2009 8:40:41 PM
AVR MATH YX
http://avr-asm.tripod.com/div3216.html (2 of 2)1/20/2009 8:40:41 PM
AVR MATH YX
The AVR Assembler Site
FLOATING POINT MATH HOME RETRO_DAN ;*************************************************************************** ; ; File Name :'Main.asm" ; Title :Matmatikai rutinok, test verzio ; Date :2003.07.16. ; Version :1.0.0 ; Support telephone :+36-70-333-4034 ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ;*************************************************************************** ; D E S C R I P T I O N ; ; ;*************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ------------------------------------; 0.01 2003.07.16 VFX Creation, mult ; 0.02 2004.03.30 VFX Add float add & sub ; ; ;*************************************************************************** ;Hardware ;*************************************************************************** ;* ;* f=external 16MHz (t=-.--ns) ;* ;*************************************************************************** ; ; ; .include "m128def.inc"
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
;*************************************************************************** ;* Const Def
SER EPROM DFLASH AT45 FLASH CARD
;************************************************************************** ;* Hardware Def. ;
VFX SMIL VFX MEM
;*************************************************************************** ;** VARIABLES .DSEG
SORT 220 CRC 236 XMODEM REC
;*************************************************************************** .ESEG
UART 304 UART 305
;*************************************************************************** ;**** I N T E R R U P T S ;**** ;*************************************************************************** .CSEG
UART 128 UART BUFF USB 232 AVR ISP
RESET:
ISP 2313
CLI
ISP 1200
ldi out ldi out
AVR SPI I2C 300
;GLOBAL INTERRUP DIS.
R16, high(RAMEND) SPH,R16 R16, low(RAMEND) SPL,R16
;setup stack
I2C 302 I2C TWI26
;PI/2 = 81 49 0F DA A2 ;1,570796326734125614166259765625
I2C/TWI 128 I2C/TWI AT8
ldi ldi ldi ldi ldi mov mov mov mov mov
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
R24,0x81 R23,0xC9 R22,0x0F R21,0xDA R20,0xA2 R6,R24 R5,R23 R4,R22 R3,R21 R2,R20
Sign bit!!!
;exponens ;mantissa
; const ;0,79411764699034392833709716796875
THERM 232 IRD 410
R24,0x80 R23,0x4b R22,0x4b R21,0x4b R20,0x4b
rcall
multiply
rcall
addition
LCD HD44
ldi ldi ldi ldi ldi
LCD 2313 LCD44 2313
;exponens ;mantissa
KBD 240 MUX 242
;
KBD PS2 KBD PC/128 veges:
PS2 EMU
rjmp veges
BOOT MG8 BOOT DR8 ; ; ; ; ; ; ; ; ; ; ; ; ;
ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
----------------------------Prepare to multiply or divide ----------------------------This routine is called in succession from multiply and divide to prepare two mantissas by setting the leftmost bit that is used for the sign. m1: R25, R24:R21 m2: R6, R5:R2 T flag = Sign of result R6,R24 corrected exponent R5,R23 restored sign bit of mantissa cycles +
(RET) =
Cycles
PREP_Mul_Div: mov eor bst
ATMEL CORP AVR BUTTERFLY
;T flag = result sign bit
ldi
R16,0xA0
;Binary point offset is 0x20 to
ldi
R17,0x80
;MSB sign bit
AVR BOOK
R16,R5 R16,R23 R16,7
integer number
tst brne add rjmp
R24 PREP_MD01 ;First number is floating point format R24,R16 PREP_MD02
PREP_MD01: or
R23,R17
;restore msb bit
PREP_MD02: tst brne add rjmp
R6 PREP_MD03 R6,R16 PREP_MD04
;Second number is floating point format
PREP_MD03: or
R5,R17
;restore msb bit
sub sub
R24,R17 R6,R17
;shift zero point by 0x80 (back
PREP_MD04:
to 2's complement) ret ; -----------------------------; THE 'MULTIPLICATION' OPERATION ; -----------------------------; (offset: $04 'multiply') ; ; m1: R6, R5:R2 ; m2: R24, R23:R20 ; ------------------; Res: R6, R5:R2 ; ; cycles + (RET) = Cycles ; multiply: rcall PREP_Mul_Div mov or or or breq mov or or or breq
R0,R2 R0,R3 R0,R4 R0,R5 Res_Zero R0,R20 R0,R21 R0,R22 R0,R23 Res_Zero
rcall clr rcall sub
mult32
brcs add brvs ldi sub
NumberTooBig R6,R24 NumberTooBig R16,0x80 R6,R16
rcall brcs
Round NumberTooBig
R7 Normalize R6,R16
;shift exponent by
normalized value
ldi bld and
;2^x *2^y = 2^(x+y)
;set offset by 0x80
R17,0xFF R17,7 R5,R17
;get result sign bit ;set result sign bit
clc ret NumberTooBig: sec ret Res_Zero: clr clr movw clr clc ret
R2 R3 R4,R2 R6
;*************************************************** ;* Mutiply 32x32 -> 64 bit ;* ;* R23:R20 x R5:R2 -> R15:R8 ;* ;* 86 cycles + 4 (RET) = 90 Cycles ;* mult32: clr R16 mul R20,R2 movw R8,R0 clr R10 clr R11 movw R12,R10 movw R14,R10 mul R21,R2 add R9,R0 adc R10,R1 mul R22,R2 add R10,R0 adc R11,R1 mul R23,R2 add R11,R0 adc R12,R1 mul add adc adc adc adc mul add adc adc adc mul add adc adc mul add adc
R20,R3 R9,R0 R10,R1 R11,R16 R12,R16 R13,R16 R21,R3 R10,R0 R11,R1 R12,R16 R13,R16 R22,R3 R11,R0 R12,R1 R13,R16 R23,R3 R12,R0 R13,R1
mul add adc adc adc adc mul add adc adc adc mul add adc adc mul add adc
R20,R4 R10,R0 R11,R1 R12,R16 R13,R16 R14,R16 R21,R4 R11,R0 R12,R1 R13,R16 R14,R16 R22,R4 R12,R0 R13,R1 R14,R16 R23,R4 R13,R0 R14,R1
mul add adc adc adc adc mul add adc adc adc mul add adc adc mul add adc ret
R20,R5 R11,R0 R12,R1 R13,R16 R14,R16 R15,R16 R21,R5 R12,R0 R13,R1 R14,R16 R15,R16 R22,R5 R13,R0 R14,R1 R15,R16 R23,R5 R14,R0 R15,R1
;********************************************************** ; R15:R8:R7 -> R15:R12 ; R16 - 64-exponent Normalize: ldi R17,64 ;max 64 bitet kell vegigrotalni Norm0: tst R15 brne Norm1 mov R15,R14 mov R14,R13 mov R13,R12 mov R12,R11 mov R11,R10 mov R10,R9 mov R9,R8 mov R8,R7 clr R7 subi R17,8 cpi R17,8 brne Norm0 Norm1: ;legnagyobb helyiertek felrotalasa bit7-ig sbrc rjmp lsl rol rol rol rol rol rol rol rol dec brne
R15,7 Norm2 R7 R8 R9 R10 R11 R12 R13 R14 R15 R17 Norm1
Norm2: ldi sub
R16,64 R16,R17 ;R16-ban az
exponens ret
; ------------------------------; THE 'PREPARE TO ADD' SUBROUTINE ; ------------------------------; This routine is called twice by addition to prepare the two numbers. ; The sign bit is tested before being set to the implied state. ; Negative numbers are twos complemented. ; ; m1: R6, R5:R2 -> R6, R7:R5:R2 ; m2: R24, R23:R20 -> R24, R25:R23:R20 ; R25,R7 -> sign ; PREP_ADD: clr R25 clr R7 ldi R16,0x80 tst brne mov
R24 Prep_Add1 R24,R16
;ide jon majd a normalas R23:R20 rjmp
M1Pos
Prep_Add1: bst or brtc
R23,7 R23,R16 M1Pos
;test the sign bit ;set it to implied state ;jump if positive number
NEG_M1: clr clr movw movw
R8 R9 R10,R8 R12,R8
;clear result regs
sub sbc
R8,R20 R9,R21
;complement ;add in initial carry
sbc sbc sbc movw movw mov
R10,R22 R11,R23 R12,R13
or from prev operation
R20,R8 R22,R10 R25,R12
M1Pos: tst brne mov
R6 Prep_Add2 R6,R16
;ide jon majd a normalas R5:R2 rjmp M2Pos Prep_Add2: bst or brtc
R5,7 R5,R16
;test the sign bit ;set it to implied state ;jump if positive number
M2Pos
NEG_M2: clr clr movw movw
R8 R9 R10,R8 R12,R8
;clear result regs
sub sbc
R8,R2 R9,R3
;complement ;add in initial carry
sbc sbc sbc movw movw mov
R10,R4 R11,R5 R12,R13
or from prev operation
R2,R8 R4,R10 R7,R12
M2Pos: ret
;return
; ------------------------; THE 'SHIFT FP Right' SUBROUTINE ; ------------------------; In: mantissa R7:R5:R2 ; Exponent : R6 ; Shift right by R16 ; ; Out: R17,R15,R14,R13,R12,R11,R10,R9,R8,R7 ; s s s s s m m m m SHIFT_FP: movw R12,R2 movw R14,R4 mov R17,R7 clr R7 clr R8 clr R9 movw R10,R8 tst brne ret
g
R16 Shift_fp1 ;diff
== 0 no rota Shift_fp1: cpi brcc
R16,0x21 ADDEND_0
cpi brcs mov mov mov mov mov mov mov mov mov bst
R16,8 ONE_SHIFT R7,R8 R8,R9 R9,R10 R10,R11 R11,R12 R12,R13 R13,R14 R14,R15 R15,R17 R17,7
clr brtc ser R16,8 rjmp
R17 SHIFT_FP2 R17
;diff>33 bit ;we add 0 to 1st param
EIGHT_SHIFT:
;negative
number?
SHIFT_FP2:
ONE_SHIFT:
subi
bst
EIGHT_SHIFT R17,7
lsr ror ror ror ror ror ror ror ror ror bld
;store sign bit R17 R15 R14 R13 R12 R11 R10 R9 R8 R7 R17,7
;set back to
sign bit dec brne ret
R16 ONE_SHIFT
ADDEND_0: clr clr clr movw movw movw movw ret
; ; ; ;
R7 R8 R9 R10,R8 R12,R8 R14,R8 R16,R8
--------------------------THE 'SUBTRACTION' OPERATION --------------------------(offset: $03 'subtract')
; m1: R6, R5:R2 ; m2: R24, R23:R20 ; ------------------; Res: R6, R5:R2 ; ; Subtraction is done by switching the sign byte/bit of the second ; number and continuing into addition. subtract: tst brne mov or or or brne ret
R24 Sub_NoZero R0,R20 R0,R21 R0,R22 R0,R23 addition ;x - 0 = x
Sub_NoZero: ori
R23,0x80
;make to negative
; -----------------------; THE 'ADDITION' OPERATION ; -----------------------; (offset: $0F 'addition') ; ; m1: R6, R5:R2 ; m2: R24, R23:R20 ; ------------------; Res: R6, R5:R2 ; ; cycles + (RET) = Cycles ; addition: rcall PREP_ADD cp R24,R6
;exp.
M1 < M2? brcc
SHIFT_LEN
;to SHIFT_LEN
movw
R8,R2
; exchange M1 &
movw movw
R2,R20 R20,R8
movw movw movw
R8,R4 R4,R22 R22,R8
movw movw movw
R8,R6 R6,R24 R24,R8
M2
SHIFT_LEN: mov sub R6
R16,R24 R16,
;length of shift mov rcall
R6,R24 SHIFT_FP ;
R17,R15,R14,R13,R12,R11,R10,R9,R8,
; ; +
s m m m m m R25,R23,R22,R21,R20 0
R7 m 0
m 0
m 0
g
0 ;--------------------------------------; R17,R15,R14,R13,R12,R11,R10,R9,R8, R7 add adc adc adc adc brlt
R12,R20 R13,R21 R14,R22 R15,R23 R17,R25 NoAdd_Overf1
inc brne rjmp
R6 Add_Rota Add_Rep_6
ldi rcall
R16,1 ONE_SHIFT
Add_Rota:
NoAdd_Overf1: mov bst
R20,R17 R17,7
;store sign ;sign =
positive? brtc clr clr movw sub mov movw sbc sbc movw
Add_Pos R0 R1
;negate
R2,R0 R0,R7 R7,R0 R0,R2 R0,R8 R1,R9 R8,R0
movw sbc sbc movw
R0,R2
movw sbc sbc movw
R0,R2
movw sbc sbc movw
R0,R2
R0,R10 R1,R11 R10,R0
R0,R12 R1,R13 R12,R0
R0,R14 R1,R15 R14,R0
mov sbc mov
R0,R2 R0,R17 R17,R0
tst breq inc brne rjmp
R17
Add_Pos: Add_Norm R6 Add_Rota1 Add_Rep_6
Add_Rota1: ldi rcall rjmp
R16,1 ONE_SHIFT Add_Pos
rcall
Normalize
bst brts
R15,7 Add_Norm1
rjmp
Res_Zero
sub breq brcs
R6,R16 Add_Rep_6 Add_Rep_6
rcall brcs
Round Add_Rep_6
bst brts ldi and
R20,7 Add_NegResult R16,0x7F R5,R16
Add_Norm:
;ha 7. =0 ,akkor nincs mit tenni
Add_Norm1:
;make pos sign
Add_NegResult: clc ret Add_Rep_6: sec
;
overflow error ret
Round: movw movw
R4,R14 R2,R12
;ide jon majd a kerekites mov or or or brne clr
R0,R2 R0,R3 R0,R4 R0,R5 Round1 R6
Round1: clc ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data http://avr-asm.tripod.com/float128.html (1 of 2)1/20/2009 8:41:21 PM
AVR MATH YX
address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/float128.html (2 of 2)1/20/2009 8:41:21 PM
AVR MATH YX
The AVR Assembler Site
16 SQUARE ROOT ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; ***************************************************************************** ;* ;* sqrt16 V 1.00 ;* ;* r16 - SQUARE LOW BYTE ;* r17 - SQUARE HIGH BYTE ;* ;* r18,19 - SQRT, returned in r16 ;* ;* Low registers used : None ;* High registers used : r16 - r19, r24, r25, r26 ;* ; ***************************************************************************** .area text _sqrt16:: st -y,r18 st -y,r19 st -y,r24 st -y,r25 st -y,r26 ldi r24,0 ; remainder low ldi r25,0 ; remainder high ldi r18,0 ; divisor low ldi r19,0 ; divisor high ldi r26,8 ; loop count sqrt16loop: lsl r18 ; divisor <<= 1 rol r19 lsl r16 ; shift two msb's into remainder rol r17 rol r24 rol r25 lsl r16 rol r17 rol r24 rol r25 cp r18,r24 ; divisor < remainder ? cpc r19,r25 brcc sqrt16bitdone inc r18 ; divisor++, lsb = 0 sub r24,r18 ; remainder -= divisor sbc r25,r19 inc r18 ; divisor++, bit_1 = 0 sqrt16bitdone: dec r26 ; decrement loop count brne sqrt16loop ; branch if not done lsr r19 ; root = divisor / 2 ror r18 mov r16,r18 ld r26,y+ ld r25,y+ ld r24,y+ ld r19,y+ ld r18,y+ ret
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
Programming the AVR Microcontrollers in Machine Language
ETHNET 8019 TEA
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ADC 128 ADC 10B © WebRing Inc.
ADC 400
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/ loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/ loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/ loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/sqrt16.html (1 of 2)1/20/2009 8:41:53 PM
AVR MATH YX
http://avr-asm.tripod.com/sqrt16.html (2 of 2)1/20/2009 8:41:53 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BCD MATH (AVR 204) HOME RETRO_DAN ;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************ ;* ;* Title: BCD Arithmetics ;* Version: 1.1 ;* Last updated: 97.07.04 ;* Target: AT90Sxxxx (All AVR Devices) ;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application Note lists subroutines for the following Binary Coded ;* Decimal arithmetic applications: ;* ;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x) ;* Binary 8 to BCD Conversion ;* BCD to Binary 16 Conversion ;* BCD to Binary 8 Conversion ;* 2-Digit BCD Addition ;* 2-Digit BCD Subtraction ;* ;***************************************************************************
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128
.include "8515def.inc"
SQRT16 MATH 202
rjmp
RESET
;reset handle
MATH 202 ;*************************************************************************** ;* ;* "bin2BCD16" - 16-bit Binary to BCD conversion ;* ;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0). ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2. ;* ;* Number of words :25 ;* Number of cycles :751/768 (Min/Max) ;* Low registers used :3 (tBCD0,tBCD1,tBCD2) ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a) ;* Pointers used :Z ;* ;***************************************************************************
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
;***** Subroutine Register Variables
VFX MEM
.equ .equ
AtBCD0 AtBCD2
=13 =15
;address of tBCD0 ;address of tBCD1
.def .def .def .def .def .def .def
tBCD0 tBCD1 tBCD2 fbinL fbinH cnt16a tmp16a
=r13 =r14 =r15 =r16 =r17 =r18 =r19
;BCD value digits 1 and 0 ;BCD value digits 3 and 2 ;BCD value digit 4 ;binary value Low byte ;binary value High byte ;loop counter ;temporary value
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
;***** Code
AVR ISP
bin2BCD16: ldi clr clr clr clr bBCDx_1:lsl rol rol rol rol dec brne ret
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
cnt16a,16 tBCD2 tBCD1 tBCD0 ZH fbinL fbinH tBCD0 tBCD1 tBCD2 cnt16a bBCDx_2
;Init loop counter ;clear result (3 bytes)
;clear ZH (not needed for AT90Sxx0x) ;shift input value ;through all bytes ;
;decrement loop counter ;if counter not zero ; return
DALLAS CRC bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1 bBCDx_3: ld tmp16a,-Z ;get (Z) with pre-decrement ;---------------------------------------------------------------;For AT90Sxx0x, substitute the above line with: ; ; dec ZL ; ld tmp16a,Z ; ;---------------------------------------------------------------subi tmp16a,-$03 ;add 0x03 sbrc tmp16a,3 ;if bit 3 not clear st Z,tmp16a ; store back ld tmp16a,Z ;get (Z) subi tmp16a,-$30 ;add 0x30 sbrc tmp16a,7 ;if bit 7 not clear st Z,tmp16a ; store back cpi ZL,AtBCD0 ;done all three? brne bBCDx_3 ;loop again if not rjmp bBCDx_1
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
;*************************************************************************** ;* ;* "bin2BCD8" - 8-bit Binary to BCD conversion ;* ;* This subroutine converts an 8-bit number (fbin) to a 2-digit ;* BCD number (tBCDH:tBCDL). ;* ;* Number of words :6 + return ;* Number of cycles :5/50 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (fbin/tBCDL,tBCDH) ;* ;* Included in the code are lines to add/replace for packed BCD output. ;* ;***************************************************************************
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE
;***** Subroutine Register Variables
STH-11
.def .def .def
ATMEL CORP AVR BUTTERFLY
fbin tBCDL tBCDH
=r16 =r16 =r17
;8-bit binary value ;BCD result MSD ;BCD result LSD
;***** Code
AVR BOOK
bin2bcd8: clr tBCDH ;clear result MSD bBCD8_1:subi fbin,10 ;input = input - 10 brcs bBCD8_2 ;abort if carry set inc tBCDH ;inc MSD ;--------------------------------------------------------------------------; ;Replace the above line with this one ; ;for packed BCD output ; subi tBCDH,-$10 ;tBCDH = tBCDH + 10 ;--------------------------------------------------------------------------rjmp bBCD8_1 ;loop again bBCD8_2:subi fbin,-10 ;compensate extra subtraction ;--------------------------------------------------------------------------; ;Add this line for packed BCD output ; add fbin,tBCDH ;--------------------------------------------------------------------------ret
;*************************************************************************** ;* ;* "BCD2bin16" - BCD to 16-Bit Binary Conversion ;* ;* This subroutine converts a 5-digit packed BCD number represented by ;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL). ;* MSD of the 5-digit number must be placed in the lowermost nibble of fBCD2. ;* ;* Let "abcde" denote the 5-digit number. The conversion is done by ;* computing the formula: 10(10(10(10a+b)+c)+d)+e. ;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation ;* which is repeated four times during the computation. ;* ;* Number of words :30 ;* Number of cycles :108 ;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH) ;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder) ;* ;*************************************************************************** ;***** "mul10a"/"mul10b" Subroutine Register Variables .def .def .def
copyL copyH mp10L
=r12 =r13 =r14
;temporary register ;temporary register ;Low byte of number to be multiplied by
.def
mp10H
=r15
;High byte of number to be multiplied
.def
adder
=r19
;value to add after multiplication
10 by 10
;***** Code mul10a:
;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high
swap mul10b:
adder ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
mov mov lsl rol lsl rol lsl rol lsl rol add adc andi add brcc inc m10_1:
copyL,mp10L copyH,mp10H mp10L mp10H copyL copyH copyL copyH copyL copyH mp10L,copyL mp10H,copyH adder,0x0f mp10L,adder m10_1 mp10H ret
nibble
nibble ;make copy ;multiply original by 2 ;multiply copy by 2 ;multiply copy by 2 (4) ;multiply copy by 2 (8) ;add copy to original ;mask away upper nibble of adder ;add lower nibble of adder ;if carry not cleared ; inc high byte
;***** Main Routine Register Variables .def
tbinL
=r14
;Low byte of binary result (same as
.def
tbinH
=r15
;High byte of binary result (same as
.def .def .def
fBCD0 fBCD1 fBCD2
=r16 =r17 =r18
;BCD value digits 1 and 0 ;BCD value digits 2 and 3 ;BCD value digit 5
mp10L) mp10H)
;***** Code BCD2bin16: andi clr mov mov rcall mov rcall mov rcall mov rcall ret
fBCD2,0x0f mp10H mp10L,fBCD2 adder,fBCD1 mul10a adder,fBCD1 mul10b adder,fBCD0 mul10a adder,fBCD0 mul10b
;mask away upper nibble of fBCD2 ;mp10H:mp10L = a ;mp10H:mp10L = 10a+b ;mp10H:mp10L = 10(10a+b)+c ;mp10H:mp10L = 10(10(10a+b)+c)+d ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
;*************************************************************************** ;* ;* "BCD2bin8" - BCD to 8-bit binary conversion ;* ;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an ;* 8-bit number (tbin). ;* ;* Number of words :4 + return ;* Number of cycles :3/48 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (tbin/fBCDL,fBCDH) ;* ;* Modifications to make the routine accept a packed BCD number is indicated ;* as comments in the code. If the modifications are used, fBCDH shall be ;* loaded with the BCD number to convert prior to calling the routine. ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
tbin fBCDL fBCDH
=r16 =r16 =r17
;binary result ;lower digit of BCD input ;higher digit of BCD input
;***** Code BCD2bin8: ;-------------------------------------------------------------------------;| ;For packed BCD input, add these two lines ;| mov tbin,fBCDH ;copy input to result ;| andi tbin,$0f ;clear higher nibble of result ;-------------------------------------------------------------------------BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1 brcs BCDb8_1 ;if carry not set ;-------------------------------------------------------------------------;| ;For packed BCD input, replace the above ;| ;two lines with these. ;| subi fBCDH,$10 ;MSD = MSD - 1 ;| brmi BCDb8_1 ;if Zero flag not set ;-------------------------------------------------------------------------subi tbin,-10 ; result = result + 10 rjmp BCDb8_0 ; loop again BCDb8_1:ret ;else return
;*************************************************************************** ;* ;* "BCDadd" - 2-digit packed BCD addition ;* ;* This subroutine adds the two unsigned 2-digit BCD numbers ;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow ;* carry in "BCD2". ;* ;* Number of words :19 ;* Number of cycles :17/20 (Min/Max) ;* Low registers used :None ;* High registers used :3 (BCD1,BCD2,tmpadd) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
BCD1 BCD2 tmpadd
=r16 =r17 =r18
;BCD input value #1 ;BCD input value #2 ;temporary register
;***** Code BCDadd: ldi add clr brcc ldi add_0: add brhs subi rjmp add_1: add_2: add brcs sbrs subi add_3: add_4: ret
tmpadd,6 ;value to be added later BCD1,BCD2 ;add the numbers binary BCD2 ;clear BCD carry add_0 ;if carry not clear BCD2,1 ; set BCD carry brhs add_1 ;if half carry not set BCD1,tmpadd ; add 6 to LSD add_2 ; if half carry not set (LSD <= 9) BCD1,6 ; restore value add_2 ;else add BCD1,tmpadd ; add 6 to LSD swap tmpadd BCD1,tmpadd ;add 6 to MSD add_4 ;if carry not set (MSD <= 9) BCD2,0 ; if previous carry not set BCD1,$60 ; restore value ret ;else ldi BCD2,1 ; set BCD carry
;*************************************************************************** ;* ;* "BCDsub" - 2-digit packed BCD subtraction ;* ;* This subroutine subtracts the two unsigned 2-digit BCD numbers ;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and ;* the underflow carry in "BCDb". ;* ;* Number of words :13 ;* Number of cycles :12/17 (Min/Max) ;* Low registers used :None ;* High registers used :2 (BCDa,BCDb) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def
BCDa BCDb
=r16 =r17
;BCD input value #1 ;BCD input value #2
;***** Code BCDsub: sub clr brcc ldi sub_0: subi sub_1: ret subi ldi brcc ldi sub_2:
BCDa,BCDb BCDb sub_0 BCDb,1 brhc sub_1 BCDa,$06 sbrs BCDb,0 BCDa,$60 BCDb,1 sub_2 BCDb,1 ret
;subtract the numbers binary ;if carry not clear ; store carry in BCDB1, bit 0 ;if half carry not clear ; LSD = LSD - 6 ;if previous carry not set ; return ;subtract 6 from MSD ;set underflow carry ;if carry not clear ; clear underflow carry
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct operation. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ldi out ldi out
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)
;***** Convert 54,321 to 2.5-byte packed BCD format ldi ldi rcall
fbinL,low(54321) fbinH,high(54321) bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321
;***** Convert 55 to 2-byte BCD ldi rcall
fbin,55 bin2BCD8
;result: tBCDH:tBCDL = 0505
;***** Convert $065535 to a 16-bit binary number ldi fBCD2,$06 ldi fBCD1,$55 ldi fBCD0,$35 rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535) ;***** Convert $0403 (43) to an 8-bit binary number ldi fBCDL,3 ldi fBCDH,4 rcall BCD2bin8 ;result: tbin = $2b (43) ;***** Add BCD numbers 51 and 79 ldi BCD1,$51 ldi BCD2,$79 rcall BCDadd ;result: BCD2:BCD1=$0130 ;***** Subtract BCD numbers 72 - 28 ldi BCDa,$72 ldi BCDb,$28 rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44 ;***** Subtract BCD numbers 0 - 90 ldi BCDa,$00 ldi BCDb,$90 rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that http://avr-asm.tripod.com/avr204.html (1 of 2)1/20/2009 8:42:33 PM
16 BIT MATH (AVR 202)
share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr204.html (2 of 2)1/20/2009 8:42:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BCD MATH (AVR 204) HOME RETRO_DAN ;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************ ;* ;* Title: BCD Arithmetics ;* Version: 1.1 ;* Last updated: 97.07.04 ;* Target: AT90Sxxxx (All AVR Devices) ;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application Note lists subroutines for the following Binary Coded ;* Decimal arithmetic applications: ;* ;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x) ;* Binary 8 to BCD Conversion ;* BCD to Binary 16 Conversion ;* BCD to Binary 8 Conversion ;* 2-Digit BCD Addition ;* 2-Digit BCD Subtraction ;* ;***************************************************************************
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128
.include "8515def.inc"
SQRT16 MATH 202
rjmp
RESET
;reset handle
MATH 202 ;*************************************************************************** ;* ;* "bin2BCD16" - 16-bit Binary to BCD conversion ;* ;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0). ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2. ;* ;* Number of words :25 ;* Number of cycles :751/768 (Min/Max) ;* Low registers used :3 (tBCD0,tBCD1,tBCD2) ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a) ;* Pointers used :Z ;* ;***************************************************************************
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
;***** Subroutine Register Variables
VFX MEM
.equ .equ
AtBCD0 AtBCD2
=13 =15
;address of tBCD0 ;address of tBCD1
.def .def .def .def .def .def .def
tBCD0 tBCD1 tBCD2 fbinL fbinH cnt16a tmp16a
=r13 =r14 =r15 =r16 =r17 =r18 =r19
;BCD value digits 1 and 0 ;BCD value digits 3 and 2 ;BCD value digit 4 ;binary value Low byte ;binary value High byte ;loop counter ;temporary value
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
;***** Code
AVR ISP
bin2BCD16: ldi clr clr clr clr bBCDx_1:lsl rol rol rol rol dec brne ret
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
cnt16a,16 tBCD2 tBCD1 tBCD0 ZH fbinL fbinH tBCD0 tBCD1 tBCD2 cnt16a bBCDx_2
;Init loop counter ;clear result (3 bytes)
;clear ZH (not needed for AT90Sxx0x) ;shift input value ;through all bytes ;
;decrement loop counter ;if counter not zero ; return
DALLAS CRC bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1 bBCDx_3: ld tmp16a,-Z ;get (Z) with pre-decrement ;---------------------------------------------------------------;For AT90Sxx0x, substitute the above line with: ; ; dec ZL ; ld tmp16a,Z ; ;---------------------------------------------------------------subi tmp16a,-$03 ;add 0x03 sbrc tmp16a,3 ;if bit 3 not clear st Z,tmp16a ; store back ld tmp16a,Z ;get (Z) subi tmp16a,-$30 ;add 0x30 sbrc tmp16a,7 ;if bit 7 not clear st Z,tmp16a ; store back cpi ZL,AtBCD0 ;done all three? brne bBCDx_3 ;loop again if not rjmp bBCDx_1
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
;*************************************************************************** ;* ;* "bin2BCD8" - 8-bit Binary to BCD conversion ;* ;* This subroutine converts an 8-bit number (fbin) to a 2-digit ;* BCD number (tBCDH:tBCDL). ;* ;* Number of words :6 + return ;* Number of cycles :5/50 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (fbin/tBCDL,tBCDH) ;* ;* Included in the code are lines to add/replace for packed BCD output. ;* ;***************************************************************************
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE
;***** Subroutine Register Variables
STH-11
.def .def .def
ATMEL CORP AVR BUTTERFLY
fbin tBCDL tBCDH
=r16 =r16 =r17
;8-bit binary value ;BCD result MSD ;BCD result LSD
;***** Code
AVR BOOK
bin2bcd8: clr tBCDH ;clear result MSD bBCD8_1:subi fbin,10 ;input = input - 10 brcs bBCD8_2 ;abort if carry set inc tBCDH ;inc MSD ;--------------------------------------------------------------------------; ;Replace the above line with this one ; ;for packed BCD output ; subi tBCDH,-$10 ;tBCDH = tBCDH + 10 ;--------------------------------------------------------------------------rjmp bBCD8_1 ;loop again bBCD8_2:subi fbin,-10 ;compensate extra subtraction ;--------------------------------------------------------------------------; ;Add this line for packed BCD output ; add fbin,tBCDH ;--------------------------------------------------------------------------ret
;*************************************************************************** ;* ;* "BCD2bin16" - BCD to 16-Bit Binary Conversion ;* ;* This subroutine converts a 5-digit packed BCD number represented by ;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL). ;* MSD of the 5-digit number must be placed in the lowermost nibble of fBCD2. ;* ;* Let "abcde" denote the 5-digit number. The conversion is done by ;* computing the formula: 10(10(10(10a+b)+c)+d)+e. ;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation ;* which is repeated four times during the computation. ;* ;* Number of words :30 ;* Number of cycles :108 ;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH) ;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder) ;* ;*************************************************************************** ;***** "mul10a"/"mul10b" Subroutine Register Variables .def .def .def
copyL copyH mp10L
=r12 =r13 =r14
;temporary register ;temporary register ;Low byte of number to be multiplied by
.def
mp10H
=r15
;High byte of number to be multiplied
.def
adder
=r19
;value to add after multiplication
10 by 10
;***** Code mul10a:
;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high
swap mul10b:
adder ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
mov mov lsl rol lsl rol lsl rol lsl rol add adc andi add brcc inc m10_1:
copyL,mp10L copyH,mp10H mp10L mp10H copyL copyH copyL copyH copyL copyH mp10L,copyL mp10H,copyH adder,0x0f mp10L,adder m10_1 mp10H ret
nibble
nibble ;make copy ;multiply original by 2 ;multiply copy by 2 ;multiply copy by 2 (4) ;multiply copy by 2 (8) ;add copy to original ;mask away upper nibble of adder ;add lower nibble of adder ;if carry not cleared ; inc high byte
;***** Main Routine Register Variables .def
tbinL
=r14
;Low byte of binary result (same as
.def
tbinH
=r15
;High byte of binary result (same as
.def .def .def
fBCD0 fBCD1 fBCD2
=r16 =r17 =r18
;BCD value digits 1 and 0 ;BCD value digits 2 and 3 ;BCD value digit 5
mp10L) mp10H)
;***** Code BCD2bin16: andi clr mov mov rcall mov rcall mov rcall mov rcall ret
fBCD2,0x0f mp10H mp10L,fBCD2 adder,fBCD1 mul10a adder,fBCD1 mul10b adder,fBCD0 mul10a adder,fBCD0 mul10b
;mask away upper nibble of fBCD2 ;mp10H:mp10L = a ;mp10H:mp10L = 10a+b ;mp10H:mp10L = 10(10a+b)+c ;mp10H:mp10L = 10(10(10a+b)+c)+d ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
;*************************************************************************** ;* ;* "BCD2bin8" - BCD to 8-bit binary conversion ;* ;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an ;* 8-bit number (tbin). ;* ;* Number of words :4 + return ;* Number of cycles :3/48 (Min/Max) + return ;* Low registers used :None ;* High registers used :2 (tbin/fBCDL,fBCDH) ;* ;* Modifications to make the routine accept a packed BCD number is indicated ;* as comments in the code. If the modifications are used, fBCDH shall be ;* loaded with the BCD number to convert prior to calling the routine. ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
tbin fBCDL fBCDH
=r16 =r16 =r17
;binary result ;lower digit of BCD input ;higher digit of BCD input
;***** Code BCD2bin8: ;-------------------------------------------------------------------------;| ;For packed BCD input, add these two lines ;| mov tbin,fBCDH ;copy input to result ;| andi tbin,$0f ;clear higher nibble of result ;-------------------------------------------------------------------------BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1 brcs BCDb8_1 ;if carry not set ;-------------------------------------------------------------------------;| ;For packed BCD input, replace the above ;| ;two lines with these. ;| subi fBCDH,$10 ;MSD = MSD - 1 ;| brmi BCDb8_1 ;if Zero flag not set ;-------------------------------------------------------------------------subi tbin,-10 ; result = result + 10 rjmp BCDb8_0 ; loop again BCDb8_1:ret ;else return
;*************************************************************************** ;* ;* "BCDadd" - 2-digit packed BCD addition ;* ;* This subroutine adds the two unsigned 2-digit BCD numbers ;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow ;* carry in "BCD2". ;* ;* Number of words :19 ;* Number of cycles :17/20 (Min/Max) ;* Low registers used :None ;* High registers used :3 (BCD1,BCD2,tmpadd) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def .def
BCD1 BCD2 tmpadd
=r16 =r17 =r18
;BCD input value #1 ;BCD input value #2 ;temporary register
;***** Code BCDadd: ldi add clr brcc ldi add_0: add brhs subi rjmp add_1: add_2: add brcs sbrs subi add_3: add_4: ret
tmpadd,6 ;value to be added later BCD1,BCD2 ;add the numbers binary BCD2 ;clear BCD carry add_0 ;if carry not clear BCD2,1 ; set BCD carry brhs add_1 ;if half carry not set BCD1,tmpadd ; add 6 to LSD add_2 ; if half carry not set (LSD <= 9) BCD1,6 ; restore value add_2 ;else add BCD1,tmpadd ; add 6 to LSD swap tmpadd BCD1,tmpadd ;add 6 to MSD add_4 ;if carry not set (MSD <= 9) BCD2,0 ; if previous carry not set BCD1,$60 ; restore value ret ;else ldi BCD2,1 ; set BCD carry
;*************************************************************************** ;* ;* "BCDsub" - 2-digit packed BCD subtraction ;* ;* This subroutine subtracts the two unsigned 2-digit BCD numbers ;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and ;* the underflow carry in "BCDb". ;* ;* Number of words :13 ;* Number of cycles :12/17 (Min/Max) ;* Low registers used :None ;* High registers used :2 (BCDa,BCDb) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def .def
BCDa BCDb
=r16 =r17
;BCD input value #1 ;BCD input value #2
;***** Code BCDsub: sub clr brcc ldi sub_0: subi sub_1: ret subi ldi brcc ldi sub_2:
BCDa,BCDb BCDb sub_0 BCDb,1 brhc sub_1 BCDa,$06 sbrs BCDb,0 BCDa,$60 BCDb,1 sub_2 BCDb,1 ret
;subtract the numbers binary ;if carry not clear ; store carry in BCDB1, bit 0 ;if half carry not clear ; LSD = LSD - 6 ;if previous carry not set ; return ;subtract 6 from MSD ;set underflow carry ;if carry not clear ; clear underflow carry
; **************************************************************************** ;* ;* Test Program ;* ;* This program calls all the subroutines as an example of usage and to ;* verify correct operation. ;* ; **************************************************************************** ;***** Main Program Register variables .def
temp
=r16
;temporary storage variable
;***** Code RESET: ldi out ldi out
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)
;***** Convert 54,321 to 2.5-byte packed BCD format ldi ldi rcall
fbinL,low(54321) fbinH,high(54321) bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321
;***** Convert 55 to 2-byte BCD ldi rcall
fbin,55 bin2BCD8
;result: tBCDH:tBCDL = 0505
;***** Convert $065535 to a 16-bit binary number ldi fBCD2,$06 ldi fBCD1,$55 ldi fBCD0,$35 rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535) ;***** Convert $0403 (43) to an 8-bit binary number ldi fBCDL,3 ldi fBCDH,4 rcall BCD2bin8 ;result: tbin = $2b (43) ;***** Add BCD numbers 51 and 79 ldi BCD1,$51 ldi BCD2,$79 rcall BCDadd ;result: BCD2:BCD1=$0130 ;***** Subtract BCD numbers 72 - 28 ldi BCDa,$72 ldi BCDb,$28 rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44 ;***** Subtract BCD numbers 0 - 90 ldi BCDa,$00 ldi BCDb,$90 rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10
forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that http://avr-asm.tripod.com/id77.html (1 of 2)1/20/2009 8:43:13 PM
16 BIT MATH (AVR 202)
share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/id77.html (2 of 2)1/20/2009 8:43:13 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DECIMAL TO ASCII ROUTINE HOME RETRO_DAN ASM FORUM
; universal signed, unsigned decimal number to ASCII convert
ASM MATH TUTORIAL #1
; MSB -> LSB = r23:r22 ZH:ZL _print24bit: ; Print unsigned 24 bit values
TUTORIAL #2 TUTORIAL #3
clr rjmp
MATH 200
_printsdecw:
MATH 200b
r23 _prnum ; Print signed decimal (16
bit) sbrs rjmp ser ser rjmp
MATH 201 MATH 202 MATH 32X
zh,7 _printdecw r22 r23 _printsdecdw
; Is the number < 0 ? ; No, print 0 to 32767
MATH YX DIV16 XX
_printdecb: clr zh
; Print (8 bit) value
_printdecw:
; Print unsigned decimal
DIV 24 24 DIV 3216
(16 bit)
FLOAT 128
clr clr
SQRT16 MATH 202 MATH 202
r22 r23
_printsdecdw:
; Print signed decimal (32
bit) sbrs rjmp com com com com subi sbci sbci sbci ldi rcall
DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
r23,7 _printdecdw zl zh r22 r23 zl,-1 zh,-1 r22,-1 r23,-1 r24,'-' _putchar
SER EPROM DFLASH AT45
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; convert to ASCII and
yl yh r1 r2 r3 r4 r5 r20,32 yl,1 yh r21,5 r25,51 r24,y r24,r25 r24,7 r25,15 r24,3 r25,240 r24,r25 y+,r24 r21 _prnum2 zl zh r22 r23 r1 r2 r3 r4 r5 r20 _prnum1 zl,6 zh r24,-z _prnum5 zl,2 _prnum3 _prnum4 r24,r1 _prnum6 yh yl
r24 r24 _prnum6 r24 r24,0x0f
subi r24,-'0' brts _putchar cpi r24,'0' brne _prnum7 ; if you want leading spaces for nice format, add
DELAYS CALL ID here "ldi r24, ' '
rjmp _putchar ret _prnum7: set _putchar: rjmp
PWM 6CH PWM 10K ENCODE STH-11
_prnum: push push clr clr clr clr clr ldi _prnum1: ldi clr ldi _prnum2: ldi ld add sbrc andi sbrc andi sub st dec brne lsl rol rol rol rol rol rol rol rol dec brne clt ldi clr _prnum3: ld rcall cpi brsh brts set mov rcall _prnum4: pop pop ret _prnum5: push swap rcall pop _prnum6: andi eliminate leading zeros
90 DAYS
DTMF 314
; Print unsigned decimal
(32 bit)
FLASH CARD
CLOCK 8564
_printdecdw:
_my_output_char_routine ; RS232, LCD, I2C
etc, etc...
ATMEL CORP AVR BUTTERFLY AVR BOOK
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/decascii.html (1 of 2)1/20/2009 8:44:04 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/decascii.html (2 of 2)1/20/2009 8:44:04 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
INTEGER TO ASCII ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7
; ****************************************************************************** ; Author : Nay Oo ; DESCRIPTION : ; - This program convert an integer number to ASCII ; AVR Newbie Learning program ; - The integer Range (0..127) ; - You can use AVRStudio 4 simulator to see the register ; contents (recommended) ; ; uController : AT90S8515 ; Development Board : STK500 ; ; ; ; AUTHOR NOTE: ; This file was written by me to educate myself in AVR ; Initial ideas was gathered from the http://www. avrbeginners.net/ ; Please do refer to them for more indept theroritical aspects. ; ; After the convertion is done, you can send these ASCII coded ; numbers to UART,USB, LCD interface, etc. ; ; If you have any thing to discuss about this file, you can contact ; me via my personal email : [email protected] ; ; ******************************************************************************
COPY 102 ;* Include Microcontroller Device specific file .include "8515def.inc"
LPM 108 EPROM 100 SER EPROM DFLASH AT45
.def
intval = r17
; the variable which
.def .def .def
HundredCounter = r18 TenthCounter = r19 OneCounter = r20
stores the integer value
VFX MEM SORT 220 CRC 236
; eg. 127 = '1' ; eg. 127 = '2' ; eg. 127 = '7'
;* Integer Value .equ Number=127
XMODEM REC UART 304
; temporary storage
register
FLASH CARD VFX SMIL
;* Register Variable Declaration Here .def temp = r16
; You can change
any number from 0 to 127
UART 305 .org 0x0000 rjmp RESET
UART 128
; program reset vector
UART BUFF USB 232
;* Integer to ASCII converter subrountine here IntToASCII: cpi intVal,100 brge DivideBy100
AVR ISP ISP 2313 ISP 1200
(intVal>=100) cpi brge
AVR SPI I2C 300
; jump if
mov add
OneCounter,IntVal HundredCounter,temp
; here, we got
add
TenthCounter,temp
; from that, we
add ret
OneCounter,temp
; ASCII values !!!
there single digits
I2C/TWI 128 I2C/TWI AT8
intVal,10 DivideBy10
(intVal>=10)
I2C 302 I2C TWI26
; ; jump if
convert them to
DALLAS-1W DALLAS CRC
DivideBy100: subi intVal,100 inc HundredCounter rjmp IntToASCII
ETHNET 8019 TEA ADC 128 ADC 10B
DivideBy10: subi intVal,10 inc TenthCounter rjmp IntToASCII
ADC 400 ADC 401 THERM 232 IRD 410
;* Main Program Starts here RESET: ldi temp,low(RAMEND)
LCD HD44 LCD 2313 LCD44 2313 KBD 240
BOOT DR8
CLOCK 8564 90 DAYS
; started
ldi out
temp,high(RAMEND) SPH,temp
; end of SRAM ; RAMEND
ldi
HundredCounter,0
; set counters
ldi ldi ldi
TenthCounter,0 OneCounter,0 temp,48
; ;
values to zero
BOOT MG8
ALM CLK
SPL,temp
is declared in 8515def.inc file
KBD PC/128 PS2 EMU
out from the
MUX 242 KBD PS2
; STACK pointer
location
; ASCII =
Number + 48 ; In ASCII table, we can see that '0' is 48 (0x30) ; therefore, need to add 48 to the single digits
DELAYS ldi rcall
CALL ID
intVal,Number IntToASCII
; subroutine call ;
DTMF 314 PWM 6CH
which convert integer value to
PWM 10K
ASCII value
;
ENCODE forever: rjmp
STH-11
forever
; infinite loop
ATMEL CORP AVR BUTTERFLY AVR BOOK
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
Search
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/intascii.html (1 of 2)1/20/2009 8:44:37 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/intascii.html (2 of 2)1/20/2009 8:44:37 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
TWO HEX TO ASCII ROUTINES HOME RETRO_DAN ASM FORUM
;----------------------------------------------; HEX TO ASCII ;----------------------------------------------;I think, this was the smallest (only 10 words).
ASM MATH TUTORIAL #1 TUTORIAL #2
;input: R16 = 8 bit value 0 ... 255 ;output: R18, R17, R16 = digits ;bytes: 20 ; bcd: ldi r18, -1 + '0' _bcd1: inc r18 subi r16, 100 brcc _bcd1 ldi r17, 10 + '0' _bcd2: dec r17 subi r16, -10 brcs _bcd2 sbci r16, -'0' ret
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45
; ********************************************************************************************** ;E. Seah ;03/24/01 ;HEX-TO-ASCII conversion subroutine ;"high" registers : 4 (3 if "value" can be "low" register) ;"low" registers : 0 (1 if "value" can be "low" register) ;program words : 22+1 (including return) ; ;description : convert 0x00<="value"<=0xff to 3 digits of ASCII in "hundreds","tens" and "ones" ; _h2a: ldi hundreds,200 ;init hundreds for hundreds cp loop ldi ones,2 ;init ones for hundreds cp loop
FLASH CARD a100: cp value,hundreds brlo sub100 ;if value=hundreds sub value,hundreds ;remove 100s from value subi ones,-0x30 ;?00<=x<=?99, 1st digit is '?' mov hundreds,ones ldi tens,90 ;init tens for tens cp loop ldi ones,9 ;init ones for tens cp loop a10: cp value,tens brlo sub10 ;if value=tens sub value,tens ;remove 10s from value subi ones,-0x30 ;?0<=x<=?9, 2nd digit is '?' mov tens,ones
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF
mov ones,value ;3rd digit is the remainder subi ones,-0x30 ;'ones' in ASCII
USB 232 AVR ISP ISP 2313
ret
ISP 1200
sub100: subi hundreds,100 ;for compare with value subi ones,1 ;use ones as temp storage for 1st digit rjmp a100
AVR SPI I2C 300 I2C 302
sub10: subi tens,10 ;for compare with value subi ones,1 ;use ones as temp storage for 2nd digit rjmp a10
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
Programming the AVR Microcontrollers in Machine Language
IRD 410 LCD HD44
AVR << Prev | Ring Hub | Join | Rate| Next >>
LCD 2313 LCD44 2313 © WebRing Inc.
KBD 240
Search
MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/hx2asc.html (1 of 2)1/20/2009 8:45:10 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/hx2asc.html (2 of 2)1/20/2009 8:45:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
8 POINT MOVING AVERAGE (AVR 222) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
[email protected]
DESCRIPTION This Application note shows an implementation of an
;* elements starting at T_START. The App. note contains
DIV 24 24
program memory to
MATH 202
Support E-mail:
array containing SIZE a test
SQRT16
8-Point Moving Average Filter 1.0 97.07.04 AT90Sxx1x (Devices with SRAM)
;* Average (MAV) filter. The program filters a data
DIV16 XX
FLOAT 128
Title: Version: Last updated: Target:
8-point Moving
MATH YX
DIV 3216
A V R 2 2 2
************************
ASM MATH
MATH 202
N O T E
;* program which copies a 60-byte block of data from ;* SRAM and filters the data. Note that the ends of the data array are not ;* filtered. ;* ; ***************************************************************************
MATH 202 .include "8515def.inc"
DEC ASCII INT ASCII HX2ASC
SIZE =60 TABLE_L =$60
;data array size ;Low SRAM address
.equ
TABLE_H =$00
;High SRAM address
of first data element
AVG8 222 FFT7
.equ .equ
of first data element
COPY 102
rjmp
RESET
;Reset Handle
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; *************************************************************************** ;* ;* "mav8" ;* ;* This subroutine filters SIZE bytes with the first element in SRAM ;* location T_START. The filter routine uses an 8-byte ring buffer which ;* occupies working registers r0-r7. As filtering progresses, this ring ;* buffer always contains the 8-byte window to be averaged. ;* ;* Number of words :31 + return ;* Number of cycles :59 + (SIZE-7)*75 + return ;* Low registers used :11 (r0-r7,mav_tmp,AL,AH) ;* High registers used :1 (t_size) ;* Pointers used :X,Y,Z ;* ; ***************************************************************************
ISP 2313
;***** Subroutine Register Variables
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
mav_tmp =r8
;temprary
.def
AL
=r9
;ring
.def
AH
=r10
;ring
.def
t_size
=r16
;size of
buffer sum, low byte buffer sum, high byte
I2C/TWI 128 I2C/TWI AT8
.def storage register
table
DALLAS-1W
;***** Code
DALLAS CRC mav8: clr clr clr clr
ETHNET 8019 TEA ADC 128
YH YL XH XL
;init pointers
ADC 10B ;***** Fill ring buffer with first-8 byte data segment
ADC 400 ADC 401 THERM 232
mav8_1:
mav_tmp,Z+
;get SRAM
data st cpi brne sbiw
Y+,mav_tmp YL,8 mav8_1 ZL,5
;store in register ;got all? ;if not, loop more ;Z points to first
average AH AL YL ld mav_tmp,Y+ AL,mav_tmp AH,XH
;Clear avg High byte ;Clear avg Low byte ;init Y-pointer ; ;add value to AL ;add carry to AH
cpi brne
YL,8 mav8_3
;added all ? ;if not, loop
lsr ror lsr ror lsr ror ldd
AH AL AH AL AH AL mav_tmp,Z+5
;divide by 8 ; ; ; ; ; ;get next value to
st andi
X+,mav_tmp XL,$07
;store to buffer ;mask away pointer
st dec cpi brne
Z+,AL t_size t_size,4 mav8_2
;store average
IRD 410 LCD HD44 LCD 2313
ld
value to filter
LCD44 2313 mav8_2: ;***** Find clr clr clr mav8_3: add adc
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
(XH is zero)
BOOT DR8 ALM CLK
again
CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
buffer
PWM 10K ENCODE
upper bits
STH-11 ATMEL CORP AVR BUTTERFLY
;end of array? ;if not, loop
more ret
AVR BOOK ; *************************************************************************** ;* ;* Test Program ;* ;* This program copies 60 bytes of data from Program memory to SRAM. It ;* then calls "mav8" to get the data filtered. ;* ; *************************************************************************** RESET: ;***** Main program Register variables .def
temp
=r16
;***** Code ldi out ldi out
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer
;***** Memory fill clr ldi
ZH ZL,tableend*2+1 ;Z-pointer <- ROM table end
ldi ldi
YL,low(256*TABLE_H+TABLE_L+SIZE) YH,high(256*TABLE_H+TABLE_L+SIZE) ;Y pointer <- SRAM table
+ 1
end + 1 loop: st
lpm -Y,r0
;get ROM constant ;store in SRAM and
ZL,1 YL,TABLE_L loop YH,TABLE_H loop
;decrement Z-pointer ;if not done ; loop more
decrement Y-pointer sbiw cpi brne cpi brne
;***** Filter data ldi ldi ldi rcall
ZL,TABLE_L ZH,TABLE_H T_size,SIZE mav8
forever:rjmp
forever
;***** 60 ROM Constants table: .db 120,196 .db 78,216 .db 78,100 .db 43,39 .db 241,43 .db 62,172 .db 109,69 .db 48,184 .db 215,231 .db 63,133 .db 216,8 .db 121,126 .db 188,98 .db 168,205 .db 157,172 .db 108,233 .db 80,255 .db 252,102 .db 198,0 .db 171,239 .db 107,114 .db 172,170 .db 17,45 .db 42,55 .db 34,174 .db 229,250 .db 12,179 .db 187,243 .db 44,231 tableend: .db 76,48
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr222.html (1 of 2)1/20/2009 8:45:45 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr222.html (2 of 2)1/20/2009 8:45:45 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
7 BIT FAST FOURIER TRANSFORMATION HOME RETRO_DAN ASM FORUM ASM MATH
This is an attempt to provide some FFT-math to the AVR community. Code has been tested with AVR-Studio4. Works fine! FFT-Output is about 7 bits accurate.
TUTORIAL #1
****************** Known limitations and problems: The code assumes input Data to be in the range -127
TUTORIAL #2 TUTORIAL #3
($81)...+127($FF).
MATH 200
MATH 202
Input-data is organized in SRAM as Data1LowByte,Data1HighByte, Data2LowByte,Data2HighByte, Data3LowByte,Data3HighByte,....
MATH 32X
The FFT uses "in-place" operations and produces the
MATH 200b MATH 201
MATH YX
following output:
DIV16 XX
Re(f0)LowByte,Re(f0HighByte), Im(f0)LowByte,Im(f0HighByte), Re(f1)LowByte,Re(f1HighByte), Im(f1)LowByte,Im(f1HighByte),....
DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII
Thus for n=128 data points (at the moment this is the maximum), we get 64 frequency Data points. CPU time for different FFT-lengths: n=32 T=4,05ms n=64 T=9,3ms n=128 T=20,95ms
INT ASCII ************************** Things to do: 1) I hope to find some inspiration on the scaling issue
HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM
(to allow greater input range). 2) The loop-counters are still 8bit only, so these would need to be 16bit to get longer FFTs working. At the moment 64 frequency bins represent maximum resolution. 3) Include amplitude calculation, because most people just want to know amplitude vs. frequency and nothing more.
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
; ************************************************************* ;* FFT-Programm für bis zu 128 Datenpunkte * ;* reelle Eingangsdaten werden "in place" transformiert * ;* 128 Datenpunkte ergeben 64 Real/ImaginärDatenpaare * ;* Programmiert von niels laugwitz für avrMikrocontroller * ; ************************************************************* ; ;.device ATmega8 .include "m8def.inc" ;Lade die Registerdefinitionen für AT-Mega8 .DEF temprL = r2 .def temprH = r3 .DEF tempiL = r4 .def tempiH = r5 .DEF i1 = r2 ;Benutzt in for_Schleife_i .def i2 = r3 ;Benutzt in for_Schleife_i .DEF i3 = r4 ;Benutzt in for_Schleife_i .def i4 = r5 ;Benutzt in for_Schleife_i .def sortierzeiger=r0; .def nullwert=r6 .def jjende=r7 .def data1 = R8 .def data2 =R9 .def data3 =R10 .def data4 =R11 .def wrL=r12 .def wrH=r13 .def wiL=r14 .def wiH=r15 .DEF temp =r16 .DEF ii =r17 .DEF jj =r18 .DEF mmax =r19 .DEF j =r20 .DEF istep=r21 .def i =r22 .DEF m =r23 .def zaehler=r24 .DEF tmp_lo =r18 ;Benutzt in for_Schleife_i .DEF tmp_hi =r19 ;Benutzt in for_Schleife_i
LCD44 2313 KBD 240
.set
nn2 =128
;Anzahl der Datenpunkte (FFT-
Länge)
MUX 242
;8 =< nn2 =< 128 .equ h1r_lo =$60 .equ h1r_hi =$61 .equ h1i_lo =$62 .equ h1i_hi =$63 .equ h2r_lo =$64 .equ h2r_hi =$65 .equ h2i_lo =$66 .equ h2i_hi =$67 .equ sramstart = $0080
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
.org $0000 rjmp main ;reset .include "avr201.asm"
90 DAYS DELAYS CALL ID
schleife_jj_body: ;Berechnung der Indexe i und j: mov i,m mul jj,istep ;r0 := jj*istep mov i,r0 add i,m ;i:=m+jj*istep mov temp,i add temp,mmax mov j,temp ;j:=i+mmax ;Hole data[j] und data[j+1] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,j adc XH,nullwert ;da das Array Data als 16bit-Werte
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK abgespeichert ist,
add XL,j ;muss der Index verdoppelt werden. adc XH,nullwert ld data1,X+ ;hole Data[j]low-byte ld data2,X+ ;hole Data[j]High-byte ld data3,X+ ;Hole Data[j+1]low-Byte ld data4,X ;hole Data[j+1]High-Byte ;Berechne tempr und tempi mehrere Multiplikationen erfordern ;etwas platz in den oberen registern. Im Moment brauchen wir die ; nicht: Also ab auf den Stack! push r23 push r22 push r21 push r20 push r19 push r18 push r17 push r16 ;Berechne tempr movw r21:r20,wrh:wrl movw r23:r22,data2:data1 rcall muls16x16_32 ;tempr:=wr*data[j] (16bit signed) MOV temprH,r18 ;we take just the middle-resultbytes MOV temprL,r17 movw r21:r20,wih:wil movw r23:r22,data4:data3 rcall muls16x16_32 ;tempi:=wi*data[j+1] (16bit signed) MOV tempiH,r18 ;we take just the middle-resultbytes MOV tempiL,r17 sub temprL,tempiL sbc temprH,tempiH
;tempr := wr*data[j]-wi*data[j
+1] ;Berechne tempi push temprL push temprH movw r21:r20,wrh:wrl movw r23:r22,data4:data3 rcall muls16x16_32 ;tempr:=wr*data[j+1] (16bit signed) MOV temprH,r18
;we take just the middle-result-
bytes MOV temprL,r17 movw r21:r20,wih:wil movw r23:r22,data2:data1 rcall muls16x16_32 ;tempi:=wi*data[j] (16bit signed) MOV tempiH,r18 ;we take just the middle-resultbytes MOV tempiL,r17 add tempiL,temprL adc tempiH,temprH
;tempi := wr*data[j+1]+wi*data
[j] pop temprH pop temprL pop r16 pop r17 pop r18 pop r19 pop r20 pop r21 pop r22 pop r23 ;multiplikationen beendet, Stack und Register wieder in Ordnung ;Hole data[i] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert ld data3,X+ ;hole Data[i]Low-Byte ld data4,X ;Hole Data[i]high-Byte ;data[j]:=data[i]-tempr movw data2:data1, data4:data3 sub data1,temprL sbc data2,temprH ldi XH,0 ldi XL,sramstart add XL,j adc XH,nullwert add XL,j adc XH,nullwert st X+,data1 st X,data2 ;Hole data[i+1] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert adiw XH:XL,2 ld data3,X+ ;hole Data[i+1]low-Byte ld data4,X ;Hole Data[i+1]high-Byte ;data[j+1]:=data[i+1]-tempi movw data2:data1, data4:data3 sub data1,tempiL sbc data2,tempiH ldi XH,0 ldi XL,sramstart add XL,j adc XH,nullwert add XL,j adc XH,nullwert adiw XH:XL,2 st X+,data1 st X,data2 ;data[i+1]:=data[i+1]+tempi add data3,tempiL adc data4,tempiH ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert adiw XH:XL,2 st X+,data3 st X,data4 ;Hole data[i] aus dem SRAM ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert ld data3,X+ ;hole Data[i]low-Byte ld data4,X ;Hole Data[i]high-Byte ;data[i]:=data[i]+tempr add data3,temprL adc data4,temprH ldi XH,0 ldi XL,sramstart add XL,i adc XH,nullwert add XL,i adc XH,nullwert st X+,data3 st X,data4 ret ;Rücksprung zur Schleife_jj ;**************************** ;****** HAUPTPROGRAMM ******* ;**************************** main: ;initialisieren des Stacks ldi r16,high(RAMEND) out spH,r16 ldi r16,low(RAMEND) out spl,r16 sei ;Kopieren der Test-Daten ins SRAM ;Testdaten werden als 16-bit-signed abgespeichert. ;Die FFT ergibt ebenfalls 16-bit Daten, ;davon sind aber nur ca. 7 bit relevant. ldi ZH,high(2*testdata) ldi ZL, low(2*testdata) clr i blockkopieren: ;Das Kopieren der Werte erspart mir eine ;butterfly-sort zu programmieren, simple stupid! LPM temp,Z+
;Lade Werte aus der Ursprungstabelle
testdata push ZH push ZL ldi ZH,high(2*speicherorte_128_werte) ldi ZL, low(2*speicherorte_128_werte) add ZL,i adc ZH,nullwert lpm sortierzeiger,Z pop ZL pop ZH ldi XH,0 ldi XL,sramstart add XL,sortierzeiger adc XH,nullwert add XL,sortierzeiger adc XH,nullwert sbrc temp,7 ;wenn temp negativ, dann dec nullwert ;setze register nullwert ausnahmsweise auf $FF st X+,temp st X,nullwert
;speichere lower-Byte zuerst ;Highbyte (enthält zunächst nur das
Vorzeichen) ;speichere alle Daten umsortiert im SRAM clr nullwert ;setze Nullwert wieder auf Null! inc i cpi i,nn2 brne blockkopieren ;nun sind die daten für die FFT umsortiert und stehen im SRAM ab ;Adresse (sramstart+2)=$0082. Für Eigene Anwendungen sollten die Daten ;von Anfang an nach der Sortiertabelle "speicherorte_XX_werte" geordnet ;werden. Die Werte sind im SRAM abgelegt als 16 bit signed integer! ;dw = LOW:HIGH = value:sign ;**************************************** ;hier beginnt die eigentliche FFT ldi mmax,2 while_schleife_start: cpi mmax,nn2 ;nn2=64 brlo while_schleife_body
;while nn2>mmax do
rjmp while_schleife_ende
;ende der while-Schleife
while_schleife_body erreicht while_schleife_body: mov istep,mmax lsl istep ;istep:=2*mmax clr ii ;ii:=0 for_schleife_ii_start: ;for ii=1 to (mmax div 2) inc ii mov m,ii lsl m ;m:=2*ii dec m ;m:=2*ii-1 ldi temp,nn2 ;nn2=64 sub temp,m ;nn2-m mov dd8u,temp mov dv8u,istep rcall div8u ;Divisionsroutine ;.def drem8u =r15 ;remainder ;.def dres8u =r24 ;result ;.def dd8u =r24 ;dividend ;.def dv8u =r25 ;divisor mov jjende,dres8u ;jjende:=nn2-m div istep clr jj ;jj:=0 Initialisierung für Schleife ;Nun holen wir die Cosinuswerte ldi ZH,high(2*cosinetab) ldi ZL, low(2*cosinetab) ldi zaehler,nn2 mov temp,mmax lsr temp pp: lsr zaehler lsr temp brne pp mov temp,ii dec temp mul temp,zaehler add ZL,r0 adc ZH,r1 add ZL,r0 ;addition des pointers doppelt wegen adc ZH,r1 ;2Byte pro Tabelleneintrag lpm wrL,Z+ ;jetzt haben wir wrL(ow) lpm wrH,Z ;jetzt haben wir wrH(igh) ;Nun holen wir die Sinuswerte ldi ZH,high(2*sinetab) ldi ZL, low(2*sinetab) ldi zaehler,nn2 mov temp,mmax lsr temp pq: lsr zaehler lsr temp brne pq mov temp,ii dec temp mul temp,zaehler add ZL,r0 adc ZH,r1 add ZL,r0 ;Addition des Pointer-Werts doppelt wegen adc ZH,r1 ;2Byte pro Tabelleneintrag lpm wiL,Z+ ;jetzt haben wir wiL(ow) lpm wiH,Z ;jetzt haben wir wiH(igh) for_schleife_jj_start: rcall Schleife_jj_body ;damit die Schleife mit einer branch-instruktion ;abgeschlossen werden kann, wird die eigentliche ;Abarbeitungsroutine mit rcall aufgerufen. ;(Problem ist die Sprungreichweite von brsh) inc jj cp jjende,jj brsh for_schleife_jj_start ;ende der jj-Schleife mov temp,mmax lsr temp ;iiende:=mmax div 2 cp ii,temp brlo for_schleife_ii_start ;hier ist das ende der for_schleife_ii mov mmax,istep rjmp while_schleife_start While_schleife_ende: ; Die FFTransformation ist geschafft! Jetzt muß nur noch richtig ; sortiert werden, da Inputdaten reelle Werte waren. ldi i,1 ;Initialisierung von i for_schleife_i_anfang: inc i ;for i:=2 to ((nn2 div 4)+1) ;Berechnung der Indizes i1..i4 mov i1,i lsl i1 dec i1 ; i1:=i+i-1 mov i2,i1 inc i2 ; i2:= i1+1 ldi temp,nn2 sub temp,i2 subi temp,-3 mov i3,temp ; i3:=nn2-i2+3 mov i4,i3 inc i4 ; i4:=i3+1 ;Nun holen wir die wr ldi ZH,high(2*cosinetab) ldi ZL, low(2*cosinetab) mov temp,i dec temp lsl temp add ZL,temp adc ZH,nullwert lpm wrL,Z+ ;jetzt haben wir wrL(ow) lpm wrH,Z ;jetzt haben wir wrH(igh) ;Nun holen wir die wi ldi ZH,high(2*sinetab) ldi ZL, low(2*sinetab) mov temp,i dec temp lsl temp add ZL,temp adc ZH,nullwert lpm wiL,Z+ ;jetzt haben wir wiL(ow) lpm wiH,Z ;jetzt haben wir wiH(igh) rcall for_schleife_calculus ;auch hier Unterprogramm, damit die ;Schleife mit brlo enden kann. ;test ob FOR_Schleife schon fertig ldi temp,nn2 lsr temp lsr temp inc temp cp i,temp brlo for_schleife_i_anfang for_schleife_i_exit: ;Umsortieren ist geschafft. nop ;here comes compensation for DC-Value. ; if DC is not important, then just skip the following routine rcall DC_compensation ; *********************************************************** ;now the fft is done. ;data contains real-part and imaginary-part as 16bit values ;arranged in pairs first real, then imaginary ; *********************************************************** ende: ;Das Werk ist vollbracht! rjmp ende ;SCHLUSS! ENDE! AUS! for_schleife_calculus: ;***** Berechnung von h1r und h2i ;hole Data[i1] in reg. data2:data1 ldi XH,0 ldi XL,sramstart add XL,i1 adc XH,nullwert add XL,i1 adc XH,nullwert ld data1,X+ ;lower-Byte zuerst ld data2,X ;Highbyte ;hole Data[i3] in register-pair data4:data3 ldi XH,0 ldi XL,sramstart add XL,i3 adc XH,nullwert add XL,i3 adc XH,nullwert ld data3,X+ ;lower-Byte zuerst ld data4,X ;Highbyte asr data2 ror data1 ;data[i1]:=data[i1]/2 asr data4 ror data3 ;data[i3]:=data[i3]/2 movw tmp_hi:tmp_lo,data2:data1 add tmp_lo,data3 adc tmp_hi,data4 ;h1r:=data[i1]+data[i3] sts h1r_lo,tmp_lo sts h1r_hi,tmp_hi ;save h1r to sram-location movw tmp_hi:tmp_lo,data2:data1 sub tmp_lo,data3 sbc tmp_hi,data4 ;h1r:=-1*(data[i1]-data[i3]) com tmp_lo com tmp_hi ldi temp,1 add tmp_lo,temp adc tmp_hi,nullwert sts h2i_lo,tmp_lo sts h2i_hi,tmp_hi ;save h1r to sram-location ;***** Berechnung von h1i und h2r ;hole Data[i2] in reg. data2:data1 ldi XH,0 ldi XL,sramstart add XL,i2 adc XH,nullwert add XL,i2 adc XH,nullwert ld data1,X+ ;lower-Byte zuerst ld data2,X ;Highbyte ;hole Data[i4] in register-pair data4:data3 ldi XH,0 ldi XL,sramstart add XL,i4 adc XH,nullwert add XL,i4 adc XH,nullwert ld data3,X+ ;lower-Byte zuerst ld data4,X ;Highbyte asr data2 ror data1 ;data[i2]:=data[i2]/2 asr data4 ror data3 ;data[i4]:=data[i4]/2 movw tmp_hi:tmp_lo,data2:data1 sub tmp_lo,data3 sbc tmp_hi,data4 sts h1i_lo,tmp_lo sts h1i_hi,tmp_hi ;save h1i to sram-location add data1,data3 adc data2,data4 sts h2r_lo,data1 sts h2r_hi,data2 ;save h2r to sram-location push r23 push r22 push r21 push r20 push r19 push r18 push r17 push r16 ; **** Data[i1]:=h1r+wr*h2r-wi*h2i movw R21:R20,wrh:wrl lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wih:wil lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 sub data1,r17 sbc data2,r18 lds r18,h1r_hi lds r17,h1r_lo add data1,r17 adc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i1 adc XH,nullwert add XL,i1 adc XH,nullwert st X+,data1 st X ,data2 ; **** Data[i2]:=h1i+wr*h2i+wi*h2r movw R21:R20,wrh:wrl lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wih:wil lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 add data1,r17 adc data2,r18 lds r18,h1i_hi lds r17,h1i_lo add data1,r17 adc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i2 adc XH,nullwert add XL,i2 adc XH,nullwert st X+,data1 st X ,data2 ; **** Data[i3]:=h1r-wr*h2r+wi*h2i movw R21:R20,wih:wil lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wrh:wrl lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 sub data1,r17 sbc data2,r18 lds r18,h1r_hi lds r17,h1r_lo add data1,r17 adc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i3 adc XH,nullwert add XL,i3 adc XH,nullwert st X+,data1 st X ,data2 ; **** Data[i4]:=-h1i+wr*h2i+wi*h2r movw R21:R20,wrh:wrl lds r23,h2i_hi lds r22,h2i_lo rcall muls16x16_32 mov data2,r18 mov data1,r17 movw R21:R20,wih:wil lds r23,h2r_hi lds r22,h2r_lo rcall muls16x16_32 add data1,r17 adc data2,r18 lds r18,h1i_hi lds r17,h1i_lo sub data1,r17 sbc data2,r18 ldi XH,0 ldi XL,sramstart add XL,i4 adc XH,nullwert add XL,i4 adc XH,nullwert st X+,data1 st X ,data2 pop r16 pop r17 pop r18 pop r19 pop r20 pop r21 pop r22 pop r23 ret ;ende der umfangreichen Berechnungen in For_schleife_i DC_compensation: lds data1,sramstart+2 lds data2,sramstart+3 lds data3,sramstart+4 lds data4,sramstart+5 movw tmp_hi:tmp_lo,data2:data1 add data1,data3 adc data2,data4 sub tmp_lo,data3 sbc tmp_hi,data4 sts sramstart+2,data1 sts sramstart+3,data2 sts sramstart+4,tmp_lo sts sramstart+5,tmp_hi ret ;ende DC-kompensation sinetab:
;Jede Tabelle 128 Werte = Anzahl
Datenpunkte .dw
0,
13,
25,
38,
50,
62,
74,
86,
98, 109,
121, 132, 142, 152, 162, 172 .dw
181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256 cosinetab:
;überlappt mit Sinustabelle um
Speicherplatz sparen .dw
256, 256, 255, 253, 251, 248, 245, 241, 237, 231,
.dw
181, 172, 162, 152, 142, 132, 121, 109,
226, 220, 213, 206, 198, 190 74,
62,
50,
38,
25,
98,
86,
13 .dw
0, -13, -25, -38, -50, -62, -74, -86, -98,-109,-
121,-132,-142,-152,-162,-172 .dw -181,-190,-198,-206,-213,-220,-226,-231,-237,-241,245,-248,-251,-253,-255,-256 .dw -256,-256,-255,-253,-251,-248,-245,-241,-237,-231,226,-220,-213,-206,-198,-190 .dw -181,-172,-162,-152,-142,-132,-121,-109, -98, -86, 74, -62, -50, -38, -25, -13 .dw
0,
13,
25,
38,
50,
62,
74,
86,
98, 109,
121, 132, 142, 152, 162, 172 .dw
181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256
sinetab_64:
;Jede Tabelle 64 Werte = Anzahl
Datenpunkte .dw 0, 25, 50, 74, 98, 121, 142,162 .dw 181,198,213,226,237,245,251,255 cosinetab_64: ;überlappt mit Sinustabelle um Speicherplatz sparen .dw 256, 255, 251, 245, 237, 226, 213, 198 .dw 181, 162, 142, 121, 98, 74, 50, 25 .dw 0, -25, -50, -74, -98,-121,-142,-162 .dw -181,-198,-213,-226,-237,-245,-251,-255 .dw -256,-255,-251,-245,-237,-226,-213,-198 .dw -181,-162,-142,-121, -98, -74, -50, -25 .dw 0, 25, 50, 74, 98, 121, 142,162 .dw 181,198,213,226,237,245,251,255 sinetab_32:
;Jede Tabelle 32 Werte = Anzahl
Datenpunkte .dw 0, 50, 98, 142 .dw 181, 213, 237, 251 cosinetab_32: ;überlappt mit Sinustabelle um Speicherplatz sparen .dw 256, 251, 237, 213 .dw 181, 142, 98, 50 .dw 0, -50, -98,-142 .dw -181,-213,-237,-251 .dw -256,-251,-237,-213 .dw -181,-142, -98, -50 .dw 0, 50, 98, 142 .dw 181, 213, 237, 251 testdata: ;128 Datenpunkte mit 7bit + sign !! .db 1,2,3,4,5,6,7,8 .db 9,10,11,12,13,14,15,16 .db 17,18,19,20,21,22,23,24 .db 25,25,27,28,29,30,31,32 .db 33,34,35,36,37,38,39,40 .db 41,42,43,44,45,46,47,48 .db 49,50,51,52,53,54,55,56 .db 57,58,59,60,61,62,63,64 .db 65,66,67,68,69,70,71,72 .db 73,74,75,76,77,78,79,80 .db 81,82,83,84,85,86,87,88 .db 89,90,91,92,93,94,95,96 .db 97,98,99,100,101,102,103,104 .db 105,106,107,108,109,110,111,112 .db 113,114,115,116,117,118,119,120 .db 121,122,123,124,125,126,127,0 speicherorte_128_werte: .db 1,2 .db 65,66 .db 33,34 .db 97,98 .db 17,18 .db 81,82 .db 49,50 .db 113,114 .db 9,10 .db 73,74 .db 41,42 .db 105,106 .db 25,26 .db 89,90 .db 57,58 .db 121,122 .db 5,6 .db 69,70 .db 37,38 .db 101,102 .db 21,22 .db 85,86 .db 53,54 .db 117,118 .db 13,14 .db 77,78 .db 45,46 .db 109,110 .db 29,30 .db 93,94 .db 61,62 .db 125,126 .db 3,4 .db 67,68 .db 35,36 .db 99,100 .db 19,20 .db 83,84 .db 51,52 .db 115,116 .db 11,12 .db 75,76 .db 43,44 .db 107,108 .db 27,28 .db 91,92 .db 59,60 .db 123,124 .db 7,8 .db 71,72 .db 39,40 .db 103,104 .db 23,24 .db 87,88 .db 55,56 .db 119,120 .db 15,16 .db 79,80 .db 47,48 .db 111,112 .db 31,32 .db 95,96 .db 63,64 .db 127,128 speicherorte_64_werte:
;Sortiertabelle für 64
Werte .db 1, 2, .db 17, 18, .db 9, 10, .db 25, 26, .db 5, 6, .db 21, 22, .db 13, 14, .db 29, 30, .db 3, 4, .db 19, 20, .db 11, 12, .db 27, 28, .db 7, 8, .db 23, 24, .db 15, 16, .db 31, 32, ;*********************
33, 49, 41, 57, 37, 53, 45, 61, 35, 51, 43, 59, 39, 55, 47, 63,
speicherorte_32_werte:
34 50 42 58 38 54 46 62 36 52 44 60 40 56 48 64
;Sortiertabelle für 32
Werte .db .db .db .db .db .db .db .db
1, 9, 5, 13, 3, 11, 7, 15,
2, 10, 6, 14, 4, 12, 8, 16,
17, 25, 21, 29, 19, 27, 23, 31,
18 26 22 30 20 28 24 32
; ****************************************************************************** ;* ;* FUNCTION ;* muls16x16_32 ;* DECRIPTION ;* Signed multiply of two 16bits numbers with 32bits result. ;* USAGE ;* r19:r18:r17:r16 = r23:r22 * r21:r20 ;* STATISTICS ;* Cycles : 19 + ret ;* Words : 15 + ret ;* Register usage: r0:r1 and r6 and r16 to r23 (11 registers) ;* NOTE ;* The routine is non-destructive to the operands. ;* ; ****************************************************************************** muls16x16_32: ; clr r6 muls r23, r21 ; (signed)ah * (signed)bh movw r19:r18, r1:r0 mul r22, r20 ; al * bl movw r17:r16, r1:r0 mulsu r23, r20 ; (signed)ah * bl sbc r19, r6 add r17, r0 adc r18, r1 adc r19, r6 mulsu r21, r22 ; (signed)bh * al sbc r19, r6 add r17, r0 adc r18, r1 adc r19, r6 ret ; *************************************************************************** ;* ;* "div8u" - 8/8 Bit Unsigned Division ;* ;* This subroutine divides the two register variables "dd8u" (dividend) and ;* "dv8u" (divisor). The result is placed in "dres8u" and the remainder in ;* "drem8u". ;* ;* Number of words :66 + return ;* Number of cycles :50/58/66 (Min/Avg/Max) + return ;* Low registers used :1 (drem8u) ;* High registers used :2 (dres8u/dd8u,dv8u) ;*
http://avr-asm.tripod.com/fft7.html (1 of 2)1/20/2009 8:46:26 PM
16 BIT MATH (AVR 202)
; *************************************************************************** ;***** Subroutine Register Variables .def .def .def .def
drem8u =r15 dres8u =r24 dd8u =r24 dv8u =r25
;remainder ;result ;dividend ;divisor
;***** Code div8u:
sub
drem8u,drem8u
;clear remainder and
carry rol rol sub brcc add clc
dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_1 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result rjmp d8u_1:
d8u_2 sec
;else ; set carry to be shifted into
d8u_2: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_3 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_3:
d8u_4 sec
d8u_4: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_5 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_5:
d8u_6 sec
d8u_6: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_7 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_7:
d8u_8 sec
d8u_8: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_9 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
rjmp d8u_9:
d8u_10 sec
d8u_10: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_11 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result ;else ; set carry to be shifted into
result
result rjmp d8u_11:
d8u_12 sec
;else ; set carry to be shifted into
result d8u_12: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_13 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result rjmp d8u_13:
d8u_14 sec
;else ; set carry to be shifted into
result d8u_14: rol sub brcc add clc
rol dd8u ;shift left dividend drem8u ;shift dividend into remainder drem8u,dv8u ;remainder = remainder - divisor d8u_15 ;if result negative drem8u,dv8u ; restore remainder ; clear carry to be shifted into
result rjmp d8u_15:
d8u_16 sec
d8u_16: ret
rol
;else ; set carry to be shifted into
result dd8u
;shift left dividend
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/fft7.html (2 of 2)1/20/2009 8:46:26 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BLOCK COPY (AVR 102) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X MATH YX DIV16 XX
A V R 1 0 2
************************
ASM MATH
MATH 202
N O T E
Title: Version: Last updated: Target:
Block Copy Routines 1.1 97.07.04 AT90Sxx1x (Devices with SRAM)
Support E-mail:
[email protected]
DESCRIPTION This Application Note shows how to copy a block of
data from Program ;* memory to SRAM and from one SRAM area to another ;* ; ***************************************************************************
DIV 24 24
.include "8515def.inc"
DIV 3216
rjmp
RESET
;reset handle
FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM
; *************************************************************************** ;* ;* "flash2ram" ;* ;* This subroutine copies a block of data from the Program memory (Flash) ;* to the internal SRAM. The following parameters must be set up prior to ;* calling the subroutine: ;* Z-pointer: Flash block start address x 2 (WORD oriented code segment) ;* Y-pointer: ram block start address ;* romsize: block size ;* ;* Number of words :5 + return ;* Number of cycles :10 x block size + return ;* Low Registers used :1 (r0) ;* High Registers used :1 (flashsize) ;* Pointers used :Y, Z ;* ; ***************************************************************************
SORT 220
;***** Subroutine Register variables
CRC 236 .def
XMODEM REC UART 304
;***** Code
UART 128
flash2ram: lpm st
UART BUFF
;get constant ;store in SRAM and
Y+,r0
increment Y-pointer
AVR ISP
adiw dec brne
ISP 2313 ISP 1200
;size of block to
be copied
UART 305
USB 232
flashsize=r16
ZL,1 flashsize flash2ram
;increment Z-pointer ;if not end of table, loop
more ret
AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
; *************************************************************************** ;* ;* "ram2ram" ;* ;* This subroutine copies one block of data from one SRAM area to another. ;* The following parameters must be set up prior to calling the subroutine: ;* ;* Z-pointer: start of RAM area to copy from ;* Y-pointer: start of RAM area to copy to ;* ramsize : size of block to copy ;* ;* Number of words :4 + return ;* Number of cycles :6 x block size + return ;* Low Registers used :1 (ramtemp) ;* High Registers used :1 (ramsize) ;* Pointers used :Y, Z ;* ; *************************************************************************** ;***** Subroutine Register variables
LCD44 2313 KBD 240 MUX 242 KBD PS2
.def
ramtemp =r1
;temporary storage
.def
ramsize =r16
;size of block to
register be copied
KBD PC/128 ;***** Code
PS2 EMU BOOT MG8
ram2ram: ld st dec brne ret
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
ramtemp,Z+ Y+,ramtemp ramsize ram2ram
;get data from BLOCK1 ;store data to BLOCK2 ; ;if not done, loop more
; **************************************************************************** ;* ;* Test Program ;* ;* This program copies 20 bytes of data from the Program memory to the SRAM ;* area beginning at location BLOCK1. It then makes a second copy to the ;* area beginning at location BLOCK2. ;* ; ****************************************************************************
AVR BOOK
.equ
BLOCK1
=$60
;start address of
.equ
BLOCK2
=$80
;start address of
SRAM array #1 SRAM array #2 ;***** Main Program Register variables .def
temp
=r16
;temporary storage
variable ;***** Code RESET: ldi out
temp,low(RAMEND) SPL,temp ;init Stack
Pointer ldi out
temp,high(RAMEND) SPH,temp
;***** Copy 20 bytes ROM -> RAM ldi ldi ldi ldi ldi rcall
ZH,high(F_TABLE*2) ZL,low(F_TABLE*2);init Z-pointer YH,high(BLOCK1) YL,low(BLOCK1) ;init Y-pointer flashsize,20 flash2ram ;copy 20 bytes
;***** Copy 20 bytes RAM -> RAM ldi ldi ldi
ZH,high(BLOCK1) ZL,low(BLOCK1) ;init Z-pointer YH,high(BLOCK2) ;(not necessary in this
ldi ldi rcall
YL,low(BLOCK2) ramsize,20 ram2ram
specific case)
forever:rjmp F_TABLE: .db .db .db .db .db .db .db .db .db .db
forever
0,1 2,3 4,5 6,7 8,9 10,11 12,13 14,15 16,17 18,19
;init Y-pointer ;copy 20 bytes ;eternal loop
;start of table (20 bytes)
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
Search
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr102.html (1 of 2)1/20/2009 8:47:00 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr102.html (2 of 2)1/20/2009 8:47:00 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LOAD PROGRAM MEMORY (AVR 108) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2
Title: Version: Last updated: Target:
Load Program Memory 1.0 98.02.27 AT90Sxx1x and higher (Devices with
SRAM)
MATH 200
;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application note shows how to use the Load
MATH 200b MATH 201 MATH 202 MATH 32X
A V R 1 0 8
************************
ASM MATH
TUTORIAL #3
N O T E
Program Memory (LPM) ;* instruction. The App. note loads the string "Hello
MATH YX
World" from
DIV16 XX
;* program memory byte by byte, and puts it onto port B. ;* ; ***************************************************************************
DIV 24 24 DIV 3216 FLOAT 128
.include "8515def.inc"
SQRT16 MATH 202
.device AT90S8515
; Specify device
MATH 202 DEC ASCII
.def
temp
=r16
; Define
start: out
ldi temp,low(RAMEND) SPL,temp ; Set stack pointer
temporary variable
INT ASCII HX2ASC AVG8 222 FFT7
to last internal RAM location
COPY 102
ldi out
temp,high(RAMEND) SPH,temp
ldi out
temp,$ff PORTB,temp
; Set all pins at
out
DDRB,temp
; Set port B as
LPM 108 EPROM 100 SER EPROM DFLASH AT45
port B high output
FLASH CARD VFX SMIL
; Load the address of 'message' into the Z register. Multiplies
VFX MEM SORT 220 CRC 236
; word address with 2 to achieve the byte address, and uses the ; functions high() and low() to calculate high and low address byte.
XMODEM REC UART 304
; Load high part of
ldi
ZL,low(2*message)
; Load low part of
byte address into ZL
UART BUFF USB 232
ZH,high(2*message)
byte address into ZH
UART 305 UART 128
ldi
loadbyte: lpm
; Load byte from
program memory into r0
AVR ISP ISP 2313
tst
r0
; Check if we've
breq
quit
; If so, quit
out
PORTB,r0
; Put the character
rcall
one_sec_delay
; A short delay
adiw
ZL,1
; Increase Z
rjmp
loadbyte
reached the end of the message
ISP 1200 AVR SPI I2C 300
onto Port B
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
registers
DALLAS-1W DALLAS CRC quit:
ETHNET 8019
rjmp quit
TEA one_sec_delay: ldi r20, 20 ldi r21, 255 ldi r22, 255 delay: dec r22 brne delay dec r21 brne delay dec r20 brne delay ret
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
message: .db "Hello World" .db 0
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314
Programming the AVR Microcontrollers in Machine Language
PWM 6CH PWM 10K
AVR << Prev | Ring Hub | Join | Rate| Next >>
ENCODE STH-11 ATMEL CORP
© WebRing Inc.
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AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr108.html (1 of 2)1/20/2009 8:47:33 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr108.html (2 of 2)1/20/2009 8:47:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
EPROM STORAGE (AVR 100) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
DEC ASCII INT ASCII
[email protected]
DESCRIPTION This Application note shows how to read data from
;* The code is written for 8515, to modify for 4414,2313,2323... apply the ;* following changes: ;* - Remove all entries to EEARH ;* - Rename EEARL to EEAR ;* ;* To modify for 1200, apply the changes above, and
FLOAT 128
MATH 202
Support E-mail:
routines are listed.
DIV 3216
MATH 202
Accessing the EEPROM 2.0 98.06.15 AT90Sxxxx (All AVR Devices)
;* EEPROM. Both random access and sequential access
DIV 24 24
SQRT16
Title: Version: Last updated: Target:
and write data to the
MATH YX DIV16 XX
A V R 1 0 0
************************
ASM MATH
MATH 202
N O T E
change the code ;* as commented inside the routines ;* ;* ; *************************************************************************** .include "8515def.inc"
HX2ASC
rjmp
RESET
;Reset Handle
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128
; *************************************************************************** ;* ;* EEWrite ;* ;* This subroutine waits until the EEPROM is ready to be programmed, then ;* programs the EEPROM with register variable "EEdwr" at address "EEawr:EEawr" ;* ;* Number of words :1200 ; 5 + return ;* :8515 ; 7 + return ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready) ;* :8515 ; 11 + return (if EEPROM is ready) ;* Low Registers used :None ;* High Registers used: ;3 (EEdwr,EEawr,EEawrh) ;* ; ***************************************************************************
UART BUFF
;***** Subroutine register variables
USB 232 AVR ISP ISP 2313
EEdwr
=r16
;data byte to write
.def
EEawr
=r17
;address low byte
.def
EEawrh
=r18
;address high byte
to EEPROM to write to
ISP 1200 AVR SPI
.def
to write to
I2C 300
;***** Code
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
EEWrite: sbic rjmp
EECR,EEWE EEWrite
;if EEWE not clear ; wait more
;
EEAR,EEawr
;output address for 1200,
out
commented out !
DALLAS CRC ETHNET 8019
; the two following lines must be replaced with the line above if 1200 is used out
EEARH,EEawrh
;output address high for
out
EEARL,EEawr
;output address low for 8515
out sbi
EEDR,EEdwr EECR,EEMWE
;output data ;set master write enable,
sbi
EECR,EEWE
;set EEPROM Write strobe ;This instruction takes 4
TEA ADC 128
8515
ADC 10B ADC 400 ADC 401 THERM 232
remove if 1200 is used
IRD 410 LCD HD44
clock cycles since
LCD 2313
clock cycles
;it halts the CPU for two ret
LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K
; *************************************************************************** ;* ;* EERead ;* ;* This subroutine waits until the EEPROM is ready to be programmed, then ;* reads the register variable "EEdrd" from address "EEardh:EEard" ;* ;* Number of words :1200 ; 5 + return ;* :8515 ; 6 + return ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready) ;* :8515 ; 9 + return (if EEPROM is ready) ;* Low Registers used :1 (EEdrd) ;* High Registers used: :2 (EEard,EEardh) ;* ; ***************************************************************************
ENCODE ;***** Subroutine register variables
STH-11 ATMEL CORP AVR BUTTERFLY
read from
AVR BOOK
read from
.def .def
EEdrd EEard
=r0 =r17
;result data byte ;address low to
.def
EEardh
=r18
;address high to
;***** Code EERead: sbic rjmp ; out
EECR,EEWE EERead EEAR,EEard
;if EEWE not clear ; wait more ;output address for 1200,
commented out ! ; the two following lines must be replaced with the line above if 1200 is used out
EEARH,EEardh
;output address high for
out
EEARL,EEard
;output address low for 8515
sbi
EECR,EERE
;set EEPROM Read strobe ;This instruction takes 4
8515
clock cycles since ;it halts the CPU for two clock cycles in ret
EEdrd,EEDR
;get data
; *************************************************************************** ;* ;* EEWrite_seq ;* ;* This subroutine increments the EEPROM address by one and waits until the ;* EEPROM is ready for programming. It then programs the EEPROM with ;* register variable "EEdwr_s". ;* Number of words :1200 ; 7 + return ;* :8515 ; 10 + return ;* Number of cycles :1200 ; 10 + return (if EEPROM is ready) ;*
:8515 ; 15 + return (if EEPROM is
ready) ;* Low Registers used :None ;* High Registers used: :3 (EEdwr_s,EEwtmp,EEwtmph) ;* ; *************************************************************************** ;***** Subroutine register variables .def
EEwtmp
=r24
;temporary storage
.def
EEwtmph =r25
;temporary storage
.def
EEdwr_s =r18
;data to write
of address low byte of address high byte
;***** Code EEWrite_seq: sbic EECR,EEWE rjmp EEWrite_seq
;if EEWE not clear ; wait more
; Write sequence for 1200 ; in EEwtmp,EEAR
;get address for 1200,
;
inc
EEwtmp
;increment address 1200,
;
out
EEAR,EEwtmp
;output address 1200
commented out ! commented out !
; Write sequence for 8515, must be replaced with the lines above if 1200 is used in in adiw out out
EEwtmp,EEARL EEwtmph,EEARH EEwtmp,0x01 EEARL,EEwtmp EEARH,EEwtmph
;get address low 8515 ;get address high 8515 ;increment address 8515 ;output address 8515 ;output address 8515
out sbi
EEDR,EEdwr_s EECR,EEMWE
;output data ;set master write enable,
sbi
EECR,EEWE
;set EEPROM Write strobe ;This instruction takes 4
remove if 1200 is used
clock cycles since ;it halts the CPU for two clock cycles ret ; *************************************************************************** ;* ;* EERead_seq ;* ;* This subroutine increments the address stored in EEAR and reads the ;* EEPROM into the register variable "EEdrd_s". ;* Number of words :1200 ; 5 + return ;* :8515 ; 7 + return ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready) ;*
:8515 ; 11 + return (if EEPROM is
ready) ;* Low Registers used :1 (EEdrd_s) ;* High Registers used: :2 (EErtmp,EErtmph) ;* ; *************************************************************************** ;***** Subroutine register variables .def
EErtmp
=r24
;temporary storage
.def
EErtmph =r25
;temporary storage
.def
EEdrd_s =r0
;result data byte
of low address of high address
;***** Code EERead_seq: sbic EECR,EEWE ;if EEWE not clear rjmp EERead_seq ; wait more ; The above sequence for EEWE = 0 can be skipped if no write is initiated. ; Read sequence for 1200 ; in EErtmp,EEAR
;get address for 1200,
;
inc
EErtmp
;increment address 1200,
;
out
EEAR,EErtmp
;output address 1200
commented out ! commented out !
; Read sequence for 8515, must be replaced with the lines above if 1200 is used in in adiw out out
EErtmp,EEARL EErtmph,EEARH EErtmp,0x01 EEARL,EErtmp EEARH,EErtmph
;get address low 8515 ;get address high 8515 ;increment address 8515 ;output address 8515 ;output address 8515
sbi
EECR,EERE
;set EEPROM Read strobe ;This instruction takes 4
clock cycles since ;it halts the CPU for two clock cycles in ret
EEdrd_s,EEDR
;get data
; **************************************************************************** ;* ;* Test/Example Program ;* ; **************************************************************************** ;***** Main Program Register variables .def .def
counter =r19 temp =r20
;***** Code RESET: ;***** Initialize stack pointer ;* Initialize stack pointer to highest address in internal SRAM ;* Comment out for devices without SRAM ldi
r16,high(RAMEND) ;High byte only required
out
SPH,r16
ldi out
r16,low(RAMEND) SPL,r16
if ;RAM is bigger than 256
Bytes
;***** Program a random location ldi ldi ldi rcall
EEdwr,$aa EEawrh,$00 EEawr,$10 EEWrite
;store $aa in EEPROM
location $0010 ;***** Read from a random locations ldi ldi rcall out
EEardh,$00 EEard,$10 EERead PORTB,EEdrd
;read address $10 ;output value to Port B
;***** Fill the EEPROM address 1..64 with bit pattern $55,$aa,$55,$aa,... ldi clr out clr out
counter,63 temp EEARH,temp temp EEARL,temp
;init loop counter ;EEARH <- $00 ;EEAR <- $00 (start address
- 1) loop1: rcall ldi rcall dec brne
ldi EEdwr_s,$55 EEWrite_seq ;program EEPROM with $55 EEdwr_s,$aa EEWrite_seq ;program EEPROM with $aa counter ;decrement counter loop1 ;and loop more if not done
;***** Copy 10 first bytes of EEPROM to r1-r11 clr out ldi out
temp EEARH,temp temp,$00 EEARL,temp
clr ldi
ZH ZL,1
;EEARH <- $00 ;EEAR <- $00 (start address
- 1)
loop2: st inc cpi brne
;Z-pointer points to r1
rcall EERead_seq ;get EEPROM data Z,EEdrd_s ;store to SRAM ZL ZL,12 ;reached the end? loop2 ;if not, loop more
forever:rjmp
forever
;eternal loop
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing http://avr-asm.tripod.com/avr100.html (1 of 2)1/20/2009 8:48:10 PM
16 BIT MATH (AVR 202)
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr100.html (2 of 2)1/20/2009 8:48:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SERIAL EPROM STORAGE HOME RETRO_DAN ;*****read/write spi( in/out temp ) ;caller is responsible for setting ss_inactive.. ;....after command completion
ASM FORUM ASM MATH TUTORIAL #1
rw_spi: cli cbi portd, nss ;ss-active, just in case ldi temp2, 8 ;load counter spi_loop: cbi portd, sck ;sck_lo lsl temp ;move 0 into D0, all other bits UP brcc
TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
lo_mosi ;msb into Carry sbi portd, mosi ;mosi_hi, Carry into output rjmp mosi_done lo_mosi: cbi portd, mosi ;mosi_lo, Carry into output mosi_done: sbic pinb, miso ;read in SPI bit & put into D0 inc temp;we FORCED D0=0, so use INC to set D0. sbi portd, sck ;sck_hi dec temp2 ;count bits brne spi_loop ret ;end of routine
MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
Programming the AVR Microcontrollers in Machine Language
SER EPROM
AVR << Prev | Ring Hub | Join | Rate| Next >>
DFLASH AT45 FLASH CARD VFX SMIL © WebRing Inc.
VFX MEM
Search
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two singlebyte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirtytwo memory spaces (000016-001F16) followed by the 64 I/ O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/sereprom.html (1 of 2)1/20/2009 8:48:42 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/sereprom.html (2 of 2)1/20/2009 8:48:42 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SPI INTERFACE FOR AT45 SERIAL DATAFLASH HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; *************************************************************************** ; ; File Name :'DFlash.asm" ; Title :SPI interface to Serial DataFlash ; Date :2003.06.01. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega8 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; SPI interface to AT45DBxxx Serial DataFlash ; ; Functions to access the Atmel AT45Dxxx dataflash series ; Supports 1Mbit - 128Mbit ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.06.01 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ; CS - Chip Select ; SCK - Serial Clock ; SI - Serial Input ; SO - Serial Output ; WP - Hardware Page Write Protect Pin ; RESET - Chip Reset ; RDY/BUSY - Ready/Busy ; ; To provide optimal flexibility, the memory array of the AT45DB081B is ;divided into three levels of granularity comprising of sectors, blocks, ;and pages. All program operations to the DataFlash occur on a page-by-page ;basis; however, the optional erase operations can be performed at the block ;or page level. ; ; ;The device operation is controlled by instructions from the host processor. ;The list of instructions and their associated opcodes are contained in ;Tables 1 through 4. A valid instruction starts with the falling edge of CS ;followed by the appropriate 8-bit opcode and the desired buffer or main memory ;address location. While the CS pin is low, tog-gling the SCK pin controls the ;loading of the opcode and the desired buffer or main memory address location ;through the SI (serial input) pin. All instructions, addresses and data are ;transferred with the most significant bit (MSB) first. ;Buffer addressing is referenced in the datasheet using the terminology ;BFA8 - BFA0 to denote the nine address bits required to designate a byte address ;within a buffer. Main memory addressing is referenced using the terminology ;PA11 - PA0 and BA8 - BA0 where PA11 - PA0 denotes the 12 address bits required ;to designate a page address and BA8 - BA0 denotes the nine address bits ;required to designate a byte address within the page. ; ; ;Status Register Format ;Bit 7 6 5 4 3 2 1 0 ; RDY/BUSY COMP 1 0 0 1 X X 45DB161 ; *************************************************************************** ;* Const Def ; ;Look-up table for these sizes ->
CLOCK 8564 90 DAYS DELAYS
512k, 1M, 2M, 4M,
8M, 16M, 32M, 64M 9,
10,
10,
;flash unsigned char DF_pagebits[] //index of internal page address bits
11};
={
9,
9,
9,
9,
CALL ID DTMF 314 ;Dataflash opcodes .equ MainMemPageRead
PWM 6CH PWM 10K
ATMEL CORP AVR BUTTERFLY AVR BOOK
0x52
;Main Memory Page
0x52
;Main memory page
.equ FlashToBuf1Transfer=
0x53
;Main memory page
.equ Buf1Read
=
0x54
.equ FlashToBuf2Transfer=
0x55
;Main memory page
.equ Buf2Read
=
0x56
;Buffer 2
.equ StatusReg
=
0x57
;Status
.equ StatusRegMode3 =
0xD7
;Status register
.equ AutoPageReWrBuf1
=
0x58
;Auto page
.equ AutoPageReWrBuf2
=
0x59
;Auto page
.equ FlashToBuf1Compare
=
0x60
;Main
.equ FlashToBuf2Compare
=
0x61
;Main
0x68
;Continuous Array
0x82
;Main memory page
0x83
;Buffer 1 to main
=
0x84
0x85
;Main memory page
0x86
;Buffer 2 to main
=
0x87
0x88
;Buffer 1 to main
0x89
;Buffer 2 to main
0xD2
;Main Memory Page
0xE8
;Continuous Array
Read Inactive Clk Pol Low or High .equ FlashPageRead
ENCODE STH-11
= =
read to buffer 1 transfer ;Buffer 1
read to buffer 2 transfer read register read SPI Mode 0 or 3 rewrite through buffer 1 rewrite through buffer 2 memory page to buffer 1 compare memory page to buffer 2 compare .equ ContArrayRead = Read (Note : Only A/B-parts supported) .equ FlashProgBuf1 = program through buffer 1 .equ Buf1ToFlashWE = memory page program with built-in erase .equ Buf1Write write .equ FlashProgBuf2 = program through buffer 2 .equ Buf2ToFlashWE = memory page program with built-in erase .equ Buf2Write write .equ Buf1ToFlash = memory page program without built-in erase .equ Buf2ToFlash = memory page program without built-in erase .equ MainMemPageReadSPI = Read SPI Mode 0 or 3 .equ ContArrayReadSPI = Read SPI Mode 0 or 3
;Buffer 1
;Buffer 2
;Table 2. Program and Erase Commands .equ Buffer1Write = 0x84 ;Buffer 1 Write .equ Buffer2Write = 0x87 ;Buffer 2 Write .equ Buffer1toMem = 0x88 ;Buffer 1 to Main Memory Page Program without Built-in Erase .equ Buffer2toMem
= 0x89 ;Buffer 2 to Main Memory
.equ DFPageErase .equ DFBlockErase .equ MemPageProgBuff1
= 0x81 ;Page Erase = 0x50 ;Block Erase = 0x82 ;Main Memory Page
.equ MemPageProgBuff2
= 0x85 ;Main Memory Page
Page Program without Built-in Erase
Program through Buffer 1 Program through Buffer 2
;Table 3. Additional Commands .equ MemPagetoBuff1 = 0x53 ;Main Memory Page to Buffer 1 Transfer .equ MemPagetoBuff2
= 0x55 ;Main Memory Page to
.equ MemPagetoBuff1Cmp
= 0x60 ;Main Memory Page to
.equ MemPagetoBuff2Cmp
= 0x61 ;Main Memory Page to
.equ PageRewriteBuff1
= 0x58 ;Auto Page Rewrite
.equ PageRewriteBuff2
= 0x59 ;Auto Page Rewrite
Buffer 2 Transfer Buffer 1 Compare Buffer 2 Compare through Buffer 1 through Buffer 2
; ************************************************************************** ;* Hardware Def. ; ; RDY/BUSY - Ready/Busy .equ DFRDY_PORT = PORTD .equ DFRDY_DIR = DDRD .equ DFRDY_PIN = PIND .equ DFRDY = 7 .equ .equ .equ
DFRES_PORT = PORTD DFRES_DIR = DDRD DFRES = 5
.equ .equ .equ
DFCS_PORT = PORTC DFCS_DIR = DDRC DFCs = 2
.equ .equ .equ
MOSI_DIR = DDRB MOSI_PORT = PORTB MOSI = 3
.equ .equ .equ .equ
MISO_DIR = DDRB MISO_PORT = PORTB MISO_PIN = PINB MISO = 4
.equ .equ .equ
SCLK_DIR = DDRB SCLK_PORT = PORTB SCLK = 5
.equ .equ .equ
DFSS_DIR = DDRB DFSS_PORT = PORTB DFSS = 2
; *************************************************************************** ;**** VARIABLES .DSEG DFSize: .byte 1 DFPageSize: .byte 1 DFPageBits: .byte 1 .equ
DFBuffer = AppData
;DFBuffer: .byte 128 ;Data buffer ; !!! use AppData buffer from user.asm --> save RAM Space !!! ; !!! Self update not supported in application !!! ; *************************************************************************** .ESEG
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG ;p,x,y,z,0 ;page bits = p ;page number = x * 256 ;page size = y * 256 (264) ;type = z ; AT45DBxxx: .db 9, 2,1,0b00001100 ;AT45DB011 1Mbit .db 9, 4,1,0b00010100 ;AT45DB021 2Mbit .db 9, 8,1,0b00011100 ;AT45DB041 4Mbit .db 9,16,1,0b00100100 ;AT45DB081 8Mbit .db 10,16,2,0b00101100 ;AT45DB161 16Mbit .db 10,32,2,0b00110100 ;AT45DB321 32Mbit .db 11,32,4,0b00111000 ;AT45DB642 64Mbit .db 11,64,4,0b00010000 ;AT45DB1282 128Mbit .dw 0,0
; **************************************************************************** ;*** S P I R U T I N S ;*** ; **************************************************************************** ;* SPI_init ;* ;* Initialize our port pins for use as SPI master. ;* ; *************************************************************************** ; SPI_init: sbi DFCS_PORT,DFCS ;DFlash CE pin is output for ATmega sbi DFCS_DIR,DFCS ;CS=1 sbi sbi
DFRES_PORT,DFRES DFRES_DIR,DFRES
;DFlash
cbi sbi
DFRDY_DIR,DFRDY DFRDY_PORT,DFRDY
;DFlash R/B
in andi ori out
R16,PORTB R16,0b11000011 R16,0b00101100 PORTB,R16
;SS, MOSI,
in andi ori out
R16,DDRB R16,0b11000011 R16,0b00101100 DDRB,R16
ldi out
R16,0b01011100 SPCR,R16
Reset = H
pullup input
SCK output; MISO input
;[7] - SPIE: SPI
Interrupt Enable ;[6] - SPE: SPI Enable ;[5] - DORD: Data Order ;[4] - MSTR: Master/ Slave Select ;[3] - CPOL: Clock Polarity ;[2] - CPHA: Clock Phase ;[1:0] - SPR1,SPR0: SPI Clock Rate Select ; SPI2X SPR1 SPR0 SCK Frequency 0
;
0
0
;
0
0
1
;
0
1
;
0
1
;
1
0
;
1
0
;
1
1
;
1
1
fosc/4
0
fosc/16 fosc/64
1
fosc/128
0
fosc/2
1 0
fosc/8
1
fosc/32 fosc/64 ldi out
R16,0b00000001 SPSR,R16
;[7] - SPIF: SPI
Interrupt Flag ;[6] - WCOL: Write COLlision flag ;[5:1] - Res: Reserved Bits ;[0] - SPI2X: Double SPI Speed Bit in in
R16,SPSR R16,SPDR
cbi
DFRES_PORT,DFRES
;Clear SPIF & WCOL
bits
;DFlash
Reset ;DFlash Reset>10us ldi ldi brne
ZL,low(SYSCLK/100000) ZH,High(SYSCLK/100000) sbiw ZL,1 W10us1
sbi
DFRES_PORT,DFRES
;DFlash
ldi
R16,50
;Reset
brne
dec W10us2
rcall cbr ldi
DF_ReadStatus R16,0b11000011 ZL,low(AT45DBxxx*2)
ldi lpm sts lpm sts lpm sts lpm cp breq tst brne
ZH,high(AT45DBxxx*2) R17,Z+ DFPageBits,R17 R18,Z+ DFSize,R18 R18,Z+ DFPageSize,R18 R2,Z+ R16,R2 DFHit R17 SearchDF
W10us1:
Reset = 1
Recoveri time = 1 us W10us2:
R16
;ATmega128 -
> set PAMPZ!! SearchDF:
DFHit: ret ; ***************************************************************************** ;*DF_SPI_RW ;* ;* Read and writes one byte from/to SPI master ;* ;* In: R16 - Byte to be written to SPI data register ;* ;* Out: R16 - Byte read from SPI data register ;* ; ****************************************************************************** ; DF_SPI_RW: out SPDR,R16 DF_SPI_RW0: sbis SPSR,spif rjmp DF_SPI_RW0 ;wait for transfer complete, poll SPIF-flag in R16,SPDR ret ; ***************************************************************************** ;*Read_DF_status ;* ;* Status info concerning the Dataflash is busy or not. ;* Status info concerning compare between buffer and flash page ;* Status info concerning size of actual device ;* ;* In: ;* ;* Out: R16 - status byte. Consult Dataflash datasheet for further decoding info ;* ; ****************************************************************************** ; DF_ReadStatus: sbi DFCS_PORT,DFCS ;DF CS inactive nop nop cbi DFCS_PORT,DFCS ;DF CS Active! ;to reset dataflash command decoder ldi R16,StatusRegMode3 rcall DF_SPI_RW ;send status register read op-code clr R16 rcall DF_SPI_RW ;dummy write to get result ret
; ***************************************************************************** ;* WaitToDF ;* ;* Wait for DataFlash to Ready ;* ;* In: ;* ;* Out: ;* ; ****************************************************************************** ; WaitToDF: rcall DF_ReadStatus cbr R16,0x7F Csak a Busy Flag marad meg breq WaitToDF monitor the status register, wait until busy-flag is high sbi DFCS_PORT,DFCS inactive nop cbi DFCS_PORT,DFCS Active! , reset dataflash command decoder ret
; ; ;DF CS
;DF CS
; ***************************************************************************** ;Page_To_Buffer ; ; Transfers a page from flash to dataflash SRAM buffer ; ; In: R0 = BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 = PageAdr -> Address of page to be transferred to buffer ; ; Out: ; ***************************************************************************** ; DF_PageToBuffer: rcall WaitToDF ldi R16,FlashToBuf1Transfer ;transfer to buffer 1 op-code tst R0 breq DF_PageToBuff01 ldi R16,FlashToBuf2Transfer ;transfer to buffer 2 op-code DF_PageToBuff01: rcall DF_SPI_RW ;send opcode lds R16,DFPageBits subi R16,8 DF_PageToBuff02: lsl R18 rol R19 dec R16 brne DF_PageToBuff02 mov rcall
R16,R19 DF_SPI_RW
;upper part of page
mov rcall
R16,R18 DF_SPI_RW
;lower part of page
clr rcall
R16 DF_SPI_RW
sbi
DFCS_PORT,DFCS
address
address
;DF CS
inactive ret
; ***************************************************************************** ;DF_BufferReadByte ; ; Reads one byte from one of the dataflash internal SRAM buffers ; ; In: R0 = BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 = IntPageAdr -> Internal page address ; ; Out: R16 - One read byte (any value) ; ; ***************************************************************************** ; DF_BufferReadByte: rcall WaitToDF ldi R16,Buf1Read ;read byte from buffer 1 tst R0 breq BufferReadByte01 ldi R16,Buf2Read ;read byte from buffer 2 BufferReadByte01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address clr R16 rcall DF_SPI_RW ;additional don't cares clr R16 rcall DF_SPI_RW ;read byte sbi DFCS_PORT,DFCS ;DF CS inactive ret
; ***************************************************************************** ;DF_BufferReadStr ; ; Reads one or more bytes from one of the dataflash internal SRAM buffers, ; and puts read bytes into buffer pointed to by X ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address ; R21:R20 -> Number of bytes to be read ; X -> address of buffer to be used for read bytes ; ; Out: ; ; ***************************************************************************** ; DF_BufferReadStr: rcall WaitToDF ldi R16,Buf1Read ;read byte from buffer 1 tst R0 breq DF_BufferReadStr01 ldi R16,Buf2Read ;read byte from buffer 2 DF_BufferReadStr01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address clr R16 rcall DF_SPI_RW ;additional don't cares push YL push YH movw YL,R20 ;Internal page address + Number of bytes to be read <= Page Size!!! DF_BufferReadStr02: clr R16 rcall DF_SPI_RW st X+,R16 ;Store DF data byte sbiw YL,1 brne DF_BufferReadStr02 pop YH pop YL sbi DFCS_PORT,DFCS ;DF CS inactive ret ; ***************************************************************************** ; DF_BufferWriteEnable ; ; Enables continous write functionality to one of the dataflash buffers ; NOTE : User must ensure that CS goes high to terminate this mode ; before accessing other dataflash functionalities ; ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address to start writing from ; ; Out: None ; ; ***************************************************************************** ; DF_BufferWriteEnable: rcall WaitToDF ldi R16,Buf1Write ;buffer 1 write op-code tst R0 breq DF_BufferWriteEnable01 ldi R16,Buf2Write ;buffer 2 write op-code DF_BufferWriteEnable01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address ret ; ***************************************************************************** ; DF_BufferWriteByte: ; ; Writes one byte to one of the dataflash internal SRAM buffers ; ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address to write byte to ; R16 -> Data byte to be written ; ; Out: None ; ; ***************************************************************************** ; DF_BufferWriteByte: push R16 rcall WaitToDF ldi R16,Buf1Write ;buffer 1 write op-code tst R0 breq DF_BufferWriteByte01 ldi R16,Buf2Write ;buffer 2 write op-code DF_BufferWriteByte01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address pop R16 rcall DF_SPI_RW ;write data byte DF_EndWrite: sbi DFCS_PORT,DFCS ;DF CS inactive ret ; ***************************************************************************** ; DF_BufferWriteStr ; ; Copies one or more bytes to one of the dataflash internal SRAM buffers ; from AVR SRAM buffer pointed to by X ; ; In: R0: BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 -> Internal page address ; R21:R20 -> Number of bytes to be read ; X -> address of buffer to be used for write bytes ; ; Out: None ; ; ***************************************************************************** ; DF_BufferWriteStr: rcall WaitToDF ldi R16,Buf1Write ;write byte to buffer 1 tst R0 breq DF_BufferWriteStr01 ldi R16,Buf2Write ;write byte to buffer 2 DF_BufferWriteStr01: rcall DF_SPI_RW ;send opcode clr R16 rcall DF_SPI_RW ;don't cares mov R16,R19 rcall DF_SPI_RW ;upper part of page address mov R16,R18 rcall DF_SPI_RW ;lower part of page address push YL push YH movw YL,R20 ;Internal page address + Number of bytes to be read <= Page Size!!! DF_BufferWriteStr02: ld R16,X+ ;Store DF data byte rcall DF_SPI_RW sbiw YL,1 brne DF_BufferWriteStr02 pop YH pop YL ret ; ***************************************************************************** ; DF_BufferToPage ; DF_BufferToPageWErase ; ; Transfers a page from dataflash SRAM buffer to flash ; ; In: R0 = BufferNo -> R0 = 0 usage Buffer 1 ; = non zero usage Buffer 2 ; R19:R18 = PageAdr -> Address of flash page to be programmed ; ; Out: None ; ; ***************************************************************************** ; DF_BufferToPage: rcall WaitToDF ldi R16,Buffer1toMem ;buffer 1 to flash without erase tst R0 breq DF_BufferToPage01 ldi R16,Buffer1toMem rjmp DF_BufferToPage01 DF_BufferToPageWErase: rcall WaitToDF ldi R16,Buf1ToFlashWE
;buffer 1
to flash with erase op-code tst breq ldi
R0 DF_BufferToPage01 R16,Buf2ToFlashWE
;buffer 2
DF_SPI_RW
;send op-
to flash with erase op-code DF_BufferToPage01: rcall code lds subi DF_BufferToPage02: lsl rol dec brne
R16,DFPageBits R16,8 R18 R19 R16 DF_BufferToPage02
mov rcall
R16,R19 DF_SPI_RW
;upper part of page
mov rcall
R16,R18 DF_SPI_RW
;lower part of page
clr rcall nop sbi
R16 DF_SPI_RW
address
address
DFCS_PORT,DFCS
;DF CS
inactive ret ; ***************************************************************************** ; DF_PageErase ; ; Erase Flash Page ; ; In: R19:R18 = PageAdr -> Address of flash page to be erased ; ; Out: None ; ; ***************************************************************************** ; DF_PageErase: rcall WaitToDF ldi R16,DFPageErase rcall DF_SPI_RW ;send opcode lds subi DF_PageErase01: lsl rol dec brne
R16,DFPageBits R16,8 R18 R19 R16 DF_PageErase01
mov rcall
R16,R19 DF_SPI_RW
;upper part
mov rcall
R16,R18 DF_SPI_RW
;lower part
clr rcall
R16 DF_SPI_RW
;dumpy part
nop sbi
DFCS_PORT,DFCS
;DF CS
of page address
of page address
of address!!!
inactive ret
; ***************************************************************************** ; DF_CheckErasedPage ; ; Test Erased Flash Page ; ; In: R19:R18 = PageAdr -> Address of flash page to be tested ; R0 = used buffer 0 = buffer0 other = buffer1 ; ; Out: c=0 no error ; c=1 Bad Page! Dont use!! ; ; ***************************************************************************** ; DF_CheckErasedPage: rcall WaitToDF push R0 rcall DF_PageToBuffer
ldi lds mul add adc
clr XL R16,8 XH,DFPageSize R16,XH XL,R0 XH,R1
lenght of page in byte pop
R0
push push push sbiw movw rcall pop pop pop cpi
R0 XL XH XL,1 R18,XL DF_BufferReadByte XH XL R0 R16,0xFF
DF_Check00:
http://avr-asm.tripod.com/dfat45.html (1 of 2)1/20/2009 8:49:19 PM
;X full
16 BIT MATH (AVR 202)
brne sbiw brne clc ret
DF_BadPage XL,1 DF_Check00 ;ok page
cleared well DF_BadPage: sec ret
;Bad Page!
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dfat45.html (2 of 2)1/20/2009 8:49:19 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
COMPACT FLASH CARD INTERFACE HOME RETRO_DAN ;*************************************************************************** ; ; File Name :'cf.asm" ; Title :Compact Flash Common Memory Mode Driver ; Date :2004.05.12. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AVR ; ;*************************************************************************** ; D E S C R I P T I O N ; ; Memory Interface to a compact flash card. ; Compact flash card is used in memory mapped mode. ; Registers are located at ADR_CFC in external RAM space of Mega128 ; ; ;*************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2004.05.12 VFX Creation ; ;*************************************************************************** ;Hardware ;*************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ;*************************************************************************** ; ; ;************************************************************************** ;* Hardware Def. ; ; CompactFlash hardware definitions ; Table 34: Memory Mapped Decoding ; -REG A10 A9-A4 A3 A2 A1 A0 Offset -OE=0 -WE=0 Notes ; 1 0 X 0 0 0 0 0 Even RD Data Even WR Data 1, 2 ; 1 0 X 0 0 0 1 1 Error Features 1, 2 ; 1 0 X 0 0 1 0 2 Sector Count Sector Count ; 1 0 X 0 0 1 1 3 Sector No. Sector No. ; 1 0 X 0 1 0 0 4 Cylinder Low Cylinder Low ; 1 0 X 0 1 0 1 5 Cylinder High Cylinder High ; 1 0 X 0 1 1 0 6 Select Card/Head Select Card/Head ; 1 0 X 0 1 1 1 7 Status Command ; 1 0 X 1 0 0 0 8 Dup. Even RD Data Dup. Even WR Data 2 ; 1 0 X 1 0 0 1 9 Dup. Odd RD Data Dup. Odd WR Data 2 ; 1 0 X 1 1 0 1 D Dup. Error Dup. Features 2 ; 1 0 X 1 1 1 0 E Alt Status Device Ctl ; 1 0 X 1 1 1 1 F Drive Address Reserved ; 1 1 X X X X 0 8 Even RD Data Even WR Data 3 ; 1 1 X X X X 1 9 Odd RD Data Odd WR Data 3
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
;Note: 1) Register 0 is accessed with -CE1 low and -CE2 low as a word register ;on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may ;also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and ;-CE2 high. Note that the address space of this word register overlaps ;the address space of the Error and Feature byte-wide registers that lie at ;offset 1. When accessed twice as byte register with -CE1 low, the first byte ;to be accessed is the even byte of the word and the second byte accessed ;is the odd byte of the equivalent word access. ;A byte access to address 0 with -CE1 high and -CE2 low accesses the error ;(read) or feature (write) register.
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
;2) Registers at offset 8, 9 and D are non-overlapping duplicates of the ;registers at offset 0 and 1. Register 8 is equivalent to register 0, ;while register 9 accesses the odd byte. Therefore, if the registers are byte ;accessed in the order 9 then 8 the data will be transferred odd byte then even ;byte. Repeated byte accesses to register 8 or 0 will access consecutive ;(even then odd) bytes from the data buffer. Repeated word accesses to register ;8, 9 or 0 will access consecutive words from the data buffer. Repeated byte ;accesses to register 9 are not supported. However, repeated alternating byte ;accesses to registers 8 then 9 will access consecutive (even then odd) bytes ;from the data buffer. Byte accesses to register 9 access only the odd byte of ;the data.
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
;3) Accesses to even addresses between 400h and 7FFh access register 8. ;Accesses to odd addresses between 400h and 7FFh access register 9. This ;1 Kbyte memory window to the data register is provided so that hosts can ;perform memory to memory block moves to the data register when the register ;lies in memory space. ;
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
; ;CF register addresses ; .equ CF_EvenData .equ CF_OddData .equ CF_Error .equ CF_SECCOUNT .equ CF_LBA0 .equ CF_LBA1 .equ CF_LBA2 .equ CF_LBA3 .equ CF_STACOM .equ CF_DecCont
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
= = = = = = = = = =
ADR_CFC+0x08 ADR_CFC+0x09 ADR_CFC+0x0D ADR_CFC+0x02 ADR_CFC+0x03 ADR_CFC+0x04 ADR_CFC+0x05 ADR_CFC+0x06 ADR_CFC+0x07 ADR_CFC+0x0E
;Dupl. DAta ;Dupl. Data ;Dupl. Errors / Features ;Sectorcount ;LBA 0-7 ;LBA 8-15 ;LBA 16-23 ;LBA 24-27 ;Status / Command ;
90 DAYS DELAYS ;Class 1 ;Upon receipt of a Class 1 command, the CompactFlash Storage Card sets BSY ;within 400 nsec.
CALL ID DTMF 314 PWM 6CH PWM 10K
;Class 2 ;Upon receipt of a Class 2 command, the CompactFlash Storage Card sets BSY ;within 400 nsec, sets up the sector buffer for a write operation, sets DRQ ;within 700 usec, and clears BSY within 400 nsec of setting DRQ.
ENCODE STH-11 ATMEL CORP
;Class 3 ;Upon receipt of a Class 3 command, the CompactFlash Storage Card sets BSY ;within 400 nsec, sets up the sector buffer for a write operation, sets DRQ ;within 20 msec (assuming no re-assignments), and clears BSY within 400 nsec ;of setting DRQ.
AVR BUTTERFLY AVR BOOK
;Table 37: CF-ATA Command Set ; ;Class COMMAND Code FR SC SN CY DH LBA ;1 Check Power Mode E5h or 98h - - - - D ;1 Execute Drive Diagnostic 90h - - - - D ;1 Erase Sector(s) C0h - Y Y Y Y Y ;1 Flush Cache E7h - - - - D ;2 Format Track 50h - Y - Y Y Y ;1 Identify Drive ECh - - - - D ;1 Idle E3h or 97h - Y - - D ;1 Idle Immediate E1h or 95h - - - - D ;1 Initialize Drive Parameters 91h - Y - - Y ;1 Key Management Structure Read B9 Feature 0-127 C C C C D C ;1 Key Management Read Keying Material B9 Feature 80 C C C C D C ;2 Key Management Change Key Management Value B9 Feature 81 C C C C D C ;1 NOP 00h - - - - D ;1 Read Buffer E4h - - - - D ;1 Read Long Sector 22h or 23h - - Y Y Y Y ;1 Read Multiple C4h - Y Y Y Y Y ;1 Read Sector(s) 20h or 21h - Y Y Y Y Y ;1 Read Verify Sector(s) 40h or 41h - Y Y Y Y Y ;1 Recalibrate 1Xh - - - - D ;1 Request Sense 03h - - - - D ;1 Security Disable Password F6h - - - - D ;1 Security Erase Prepare F3h - - - - D ;1 Security Erase Unit F4h - - - - D ;1 Security Freeze Lock F5h - - - - D ;1 Security Set Password F1h - - - - D ;1 Security Unlock F2h - - - - D ;1 Seek 7Xh - - Y Y Y Y ;1 Set Features EFh Y - - - D ;1 Set Multiple Mode C6h - Y - - D ;1 Set Sleep Mode E6h or 99h - - - - D ;1 Standby E2h or 96h - - - - D ;1 Standby Immediate E0h or 94h - - - - D ;1 Translate Sector 87h - Y Y Y Y Y ;1 Wear Level F5h - - - - Y ;2 Write Buffer E8h - - - - D ;2 Write Long Sector 32h or 33h - - Y Y Y Y ;3 Write Multiple C5h - Y Y Y Y Y ;3 Write Multiple w/o Erase CDh - Y Y Y Y Y ;2 Write Sector(s) 30h or 31h - Y Y Y Y Y ;2 Write Sector(s) w/o Erase 38h - Y Y Y Y Y ;3 Write Verify 3Ch - Y Y Y Y Y ; ;Definitions: ;FR = Features Register ;SC = Sector Count Register ;SN = Sector Number Register ;CY = Cylinder Registers ;DH = Card/Drive/Head Register ;LBA = Logical Block Address Mode Supported (see command descriptions for use). ;Y - The register contains a valid parameter for this command. For the Drive/Head Register Y ;means both the CompactFlash Storage Card and head parameters are used; D - only the ;CompactFlash Storage Card parameter is valid and not the head parameter; C - The register ;contains command specific data (see command descriptions for use). ; ;CF-ATA Command Set .equ CF_CMD_READ_SEC = 0x20 .equ CF_CMD_WRITE_SEC = 0x30 .equ CF_CMD_IDENTIFY = 0xEC
.equ .equ
CFRDY CFVS1
= 2 = 3
;bit 2 = 1 CF ready ;bit 3 = 0 CF in slot
; *************************************************************************************** ;*** Definition of the status register bits ;*** ;*** Bit7 Bit0 ;*** BSY DRDY DWF DSC DRQ CORR IDX ERR ; *************************************************************************************** .equ CFC_STATUS_BSY = 0x80 ;Busy flag .equ CFC_STATUS_DRDY = 0x40 ;Drive ready .equ CFC_STATUS_DWF = 0x20 ;Drive write fault .equ CFC_STATUS_DSC = 0x10 ;Drive seek complete .equ CFC_STATUS_DRQ = 0x08 ;Data request .equ CFC_STATUS_CORR = 0x04 ;Corrected data .equ CFC_STATUS_IDX = 0x02 ;Index .equ CFC_STATUS_ERR = 0x01 ;Error
; ;*************************************************************************** ;**** VARIABLES .DSEG ;*************************************************************************** .ESEG
;*************************************************************************** ;**** CODE SEG ;*************************************************************************** .CSEG
;******************************************************** ;CFRdy ; ; Wait until CF not busy ; ; Out: c= 0 no error ; 1 error ; ; Alt: R16,R17 ; CFHWRdy: lds R16,ADR_CFST bst R16,CFVS1 ;CF inserted? brtc CFHWRdy0 rjmp CFDrvError CFHWRdy0: lds R16,ADR_CFST bst R16,CFRDY ;CF ready? brtc CFHWRdy clc ret ;******************************************************** ;CFWaitDRQ ; ; Wait until Data will available ; ; Out: c= 0 no error ; 1 error ; ; Alt: R16,R17 ; CFWaitDRQ: rcall CFHWRdy brcc CFWaitDRQ00 ret CFWaitDRQ00: lds R16,CF_STACOM bst R16,0 brtc CFWaitDRQ0 CFWaitErr: ldi R16,low(0xFFF0) ;Error in last command ldi R17,high(0xFFF0) ;ide keresunk egy error kodot!!! sec ret CFWaitDRQ0: andi cpi brne clc ret
R16,0xF8 R16,0x58 CFWaitDRQ
;******************************************************** ;CFWaitReady ; ; Wait until CF will ready ; ; Out: c= 0 no error ; 1 error ; ; Alt: R16,R17 ; CFWaitReady: rcall CFHWRdy brcc CFWaitRdy0 ret CFWaitRdy0: lds R16,CF_STACOM bst R16,0 brts CFWaitErr CFWaitReady01: andi R16,0xF0 cpi R16,0x50 brne CFWaitReady clc ret ;******************************************************** ;CFReadSector ; ; In: R13:R12:R11:R10 - LBA sector number ; Page: Y - Pointer to Data Buffer [512 byte] ; Z - Phis. Drive Descriptor ; ; Out: c= 0 no error ; 1 error ; CFReadSector: ldd R0,Z+MaxSector+0 ldd R1,Z+MaxSector+1 ldd R2,Z+MaxSector+2 ldd R3,Z+MaxSector+3 cp R10,R0 cpc R11,R1 cpc R12,R2 cpc R13,R3 brcs CFReadSec00 ldi ldi sec ret
R16,low(ERROR_SECTOR_NOT_FOUND) ;Sector number too big R17,high(ERROR_SECTOR_NOT_FOUND)
CFReadSec00: std std std std
Z+CurrentSector+0,R10 Z+CurrentSector+1,R11 Z+CurrentSector+2,R12 Z+CurrentSector+3,R13
rcall brcc ret
CFWaitReady CFReadSec01 ;Error in last command
CFReadSec01: ldi sts nop sts nop sts nop sts ldi and ori sts
R16,1 CF_SECCOUNT,R16
ldi sts
R16,CF_CMD_READ_SEC CF_STACOM,R16
;Set Read Sector Command
ldi ldi
XL,0 XH,1
;if X==0 -> X=256 word;
movw
R0,YL
;save Y reg.
rcall brcc ret
CFWaitDrq CFReadSec02
CF_LBA0,R10
;D7..D0
CF_LBA1,R11
;D15..D8
CF_LBA2,R12 R16,0x0F R16,R13 R16,0xE0 CF_LBA3,R16
;D23..D16
;set LBA mode ;D27..D24 + LBA mode + Drive0
;Drive error
CFReadSec02: lds bst brts bst brtc
R16,ADR_CFST R16,CFVS1 CFDrvError R16,CFRDY CFReadSec02
lds st lds st sbiw brne
R16,CF_EvenData Y+,R16 R16,CF_OddData Y+,R16 XL,1 CFReadSec02
movw clc ret
YL,R0
ldi ldi sec ret
R16,low(ERROR_BAD_UNIT) R17,high(ERROR_BAD_UNIT) ;Drive not present
;CF inserted? ;CF ready?
;restore Y reg.
CFDrvError:
;******************************************************** ;CFWriteSector ; ; In: R13:R12:R11:R10 - LBA sector number ; Page: Y - Pointer to Data Buffer [512 byte] ; Z - Phis. Drive Descriptor ; ; Out: c= 0 no error ; 1 error ; CFWriteSector: ldd R0,Z+MaxSector+0 ldd R1,Z+MaxSector+1 ldd R2,Z+MaxSector+2 ldd R3,Z+MaxSector+3 cp R10,R0 cpc R11,R1 cpc R12,R2 cpc R13,R3 brcs CFWriteSec00 ldi ldi sec ret CFWriteSec00: rcall brcc ret CFWriteSec01: ldi sts nop sts nop sts nop sts ldi and ori sts ldi sts
R16,low(ERROR_SECTOR_NOT_FOUND) ;Sector number too big R17,high(ERROR_SECTOR_NOT_FOUND)
CFWaitReady CFWriteSec01 ;Error in last command R16,1 CF_SECCOUNT,R16 CF_LBA0,R10
;D7..D0
CF_LBA1,R11
;D15..D8
CF_LBA2,R12 R16,0x0F R16,R13 R16,0xE0 CF_LBA3,R16 R16,CF_CMD_WRITE_SEC CF_STACOM,R16
;D23..D16
ldi ldi
XL,0 XH,1
movw
R0,YL
rcall brcc ret CFWriteSec02: lds bst brts bst brtc
;set LBA mode ;D27..D24 + LBA mode + Drive0 ;Write sector command
;if X==0 -> X=256 word;
CFWaitDrq CFWriteSec02 ;Drive error R16,ADR_CFST R16,CFVS1 CFDrvError R16,CFRDY CFWriteSec02
ld sts ld sts sbiw brne
R16,Y+ CF_EvenData,R16 R16,Y+ CF_OddData,R16 XL,1 CFWriteSec02
movw clc ret
YL,R0
;CF inserted? ;CF ready?
;******************************************************** ;CFResetDevice ; ; In: ; ; Out: c= 0 no error ; 1 error R17:R16 error code ; CFResetDevice: ldi R16,0b00000100 ;Force SW reset sts ADR_CFC+0x0E,R16 ;Device Control Register ldi R16,64 CFRes0: dec R17 brne CFRes0 dec R16 brne CFRes0 clr R16 sts ADR_CFC+0x0E,R16 ;Device Control Register rcall CFWaitReady ret
;******************************************************** ;CFIdentify ; ; In: Z - Phis. Drive Descriptor ; Page: Y - Pointer to temporary Data Buffer [512 byte] ; ; Out: c= 0 no error ; 1 error ; CFIdentify: rcall CFWaitReady brcc CFIdent01 ret ;Error code in R17:R16 CFIdent01: ldi R16,1 sts CF_SECCOUNT,R16 clr R16 sts CF_LBA0,R16 nop sts CF_LBA1,R16 nop sts CF_LBA2,R16 ldi R16,0xE0 sts CF_LBA3,R16 ldi R16,CF_CMD_IDENTIFY sts CF_STACOM,R16 ldi ldi movw
XL,0 XH,1 R0,YL
;read fixed 256 word
call brcc ret
CFWaitDRQ CFIdent02
lds st nop lds st sbiw brne
R16,CF_EvenData Y+,R16
movw
YL,R0
clr ldd cpi brne ldd cpi brne inc
R0 R16,Y+0 R16,0x8A CFIDs0 R16,Y+1 R16,0x84 CFIDs0 R0
std
Z+MediaFlag,R0
ldi std
R16,RemovableMedia Z+MediaType,R16
ldi std
R16,0x80 Z+DiskNumber,R16
ldd ldd std std
R16,Y+2 R17,Y+3 Z+Cylinders+0,R16 Z+Cylinders+1,R17
;Drive error
CFIdent02:
R16,CF_OddData Y+,R16 XL,1 CFIdent02
;CF IDs: 848Ah
CFIDs0:
std
ldd R16,Y+6 Z+Heads,R16
;Store CF ID
;First HDD => HDD0
;Default tracks/cylinders
;Default Heads
ldd std
R16,Y+12 Z+SectorsPerTrack,R16
;default Sectors per track
ldd std ldd std ldd std ldd std
R16,Y+14 Z+MaxSector+2,R16 R16,Y+15 Z+MaxSector+3,R16 R16,Y+16 Z+MaxSector+0,R16 R16,Y+17 Z+MaxSector+1,R16
;Number of Sectors per Card ;MSW -LSW !!!
clc ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout http://avr-asm.tripod.com/flashcard.html (1 of 2)1/20/2009 8:49:58 PM
16 BIT MATH (AVR 202)
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/flashcard.html (2 of 2)1/20/2009 8:49:58 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SMART MEDIA MANAGER FOR SMIL HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ; ; File Name :'SmartM.asm" ; Title :SmartMedia Driver for External SMIL Controller ; Date :2003.05.05. ; Version :1.11.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; VFX SMIL Smart Media Manager ; ;Why is FTL needed? ; • Flash are not 100% perfect . It needs bad block management. ; • Flash is erased in blocks(typical 16KB) larger than disk sectors(512Byte) ; • Flash has a limited number of erase cycles (1M Cycles). So it needs wear-leveling algorithm. ; • Flash is essentially non-writable (must be erased before it can be written) ; ; · Converts the sector addresses addressed by the host to physical addresses of Flash Memory ; · Converts host requests into the programming/ erasing algorithms of associated Flash technology ; · Detects the error and replaces the encountered bad sectors with the good by mapping them out ; -------------------------------------------------------------------------------------; Linear address Logical Address ; - Address Map, Address Configuration ; I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 ;1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 CA0 ~ CA7 : column address ;2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 PA0 ~ PA7 : page address 1 ;3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 PA8 ~ PA15 : page address 2 ;4th Cycle A25 A26 PA16 ~ PA23 : page address 3 ; ;Model Valid Page Address Fixed Low ;2MB PA0 ~ PA12 PA13 ~ PA15 ;4MB PA0 ~ PA12 PA13 ~ PA15 ;8MB PA0 ~ PA13 PA14 ~ PA15 ;16MB PA0 ~ PA14 PA15 ;32MB PA0 ~ PA15 ;64MB PA0 ~ PA16 PA17 ~ PA23 ;128MB PA0 ~ PA17 PA18 ~ PA23 ; ; -------------------------------------------------------------------------------------; Considerations for High Density Considerations for High Density SmartMedia ; Zone-based block management for 32MB,64MB and 128MB ; ;Zone Physical Block Description ; 0 0 CIS/Identify Drive Information Area ; 0 1 ~ 1023 Data Area (Logical Block : 0 ~ 999) ; 1 0 ~ 1023 Data Area (Logical Block :1000 ~1999) ; ... ; Last 0 ~ 1023 Data Area (Logical Block : Zone x 1000 + 999 ) ; ;* CIS/Identify Drive Information Area ==>Zone 0 ; Each zone has 1000 data blocks. ; -------------------------------------------------------------------------------------; ; CIS (Card Information System) Area 1 and CIS (Card Information System) Area (1 and 2) Physical BLOCK 1 ; ;Addr Data Contents ; ;00 01h Tuple ID(CIS TPL_Device) ;01 03h Link to Next Tuple ;02 D9h Device Type : I/O, Rate : 250ns ;03 01h Device Size : 2 K Byte ;04 FFh End of Device ID Tuple ;05 01h Tuple ID(CIS TPL_JEDEC_C) ;06 20h Link to Next Tuple ;07 DFh JEDEC Manufacture ID(PC Card ATA) ;08 18h JEDEC Device ID(VPP not required) ;09 02h Tuple ID(CIS TPL_MANF ID) ;0A 04h Link to Next Tuple ;0B 00h Manufacture Code ;0C 00h Manufacture Code ;0D 00h Manufacture Info. ;0E 00h Manufacture Info. ;0F 21h Tuple ID(CIS TPL_FUNC ID) ;10 02h Link to Next Tuple ;11 04h PL FID_FUNCTION ;12 01h TPL_FID_SYS INIT ;13 22h Tuple ID(CIS TPL_FUNCE) ;14 02h Link to Next Tuple ;15 01h Disk Device Interface Tuple ;16 01h PC Card ATA Interface ;17 22h Tuple ID(CIS TPL_FUNCE) ;18 03h Link to Next Tuple ;19 02h PC Card ATA Extension Tuple ;1A 04h ATA Function Byte1 ;1B 07h ATA Function Byte2 ;1C 1Ah Tuple ID(CIS TPL_CONFIG) ;1D 05h Link to Next Tuple ;1E 01h Field Size Byte ;1F 03h Last Entry in the Card Configuration Table ;20 00h CCR Base Address(Low-order Byte) ;21 02h CCR Base Address(High-order Byte) ;22 0Fh CCR Present Mask ;23 1Bh Tuple ID(CIS TPL_CFTABLE_ENTRY) ;24 08h Link to Next Tuple ;25 C0h Configuration Table Index Byte ;26 C0h Interface Description Field ;27 A1h Feature Selection Byte ;28 01h Power Parameter Selection Byte ;29 55h Power Voltage(5V) ;2A 08h Memory Space(Low-order byte) ;2B 00h Memory Space(High-order byte) ;2C 20h Miscellaneous (ex: CCSR power down) ;2D 1Bh Tuple ID(CIS TPL_CFTABLE_ENTRY) ;2E 0Ah Link to Next Tuple ;2F C1h Configuration Table Index Byte ;30 41h Interface Description Field ;31 99h Feature Selection Byte ;32 01h Power Parameter Selection Byte ;33 55h Power Voltage(5V) ;34 64h I/O Space Description Byte ;35 F0h Interrupt IRQ Condition Info. ;36 FFh Interrupt IRQs 0 to 7 ;37 FFh Interrupt IRQs 8 to 15 ;38 20h Miscellaneous (ex: CCSR power down) ;39 1Bh Tuple ID [I/O Primary] ;3A 0Ch Link to Next Tuple ;3B 82h Configuration Table Index Byte ;3C 41h Interface Description Field ;3D 18h Feature Selection Byte ;3E EAh I/O Space Description Byte ;3F 61h I/O Range Description Byte ;40 F0h I/O Address Range(01F0h-01F7h) ;41 01h I/O Address Range(01F0h-01F7h) ;42 07h 8 Bytes ;43 F6h I/O Address Range(03F6h-03F7h) ;44 03h I/O Address Range(03F6h-03F7h) ;45 01h 2 Bytes ;46 EEh IRQ Condition Info. (IRQ14) ;47 1Bh Tuple ID[I/O secondary] ;48 0Ch Link to Next Tuple ;49 83h Configuration Table Index Byte ;4A 41h Interface Description Field ;4B 18h Feature Selection Byte ;4C EAh I/O Space Description Byte ;4D 61h I/O Range Description Byte ;4E 70h I/O Address Range(0170h-0177h) ;4F 01h I/O Address Range(0170h-0177h) ;50 07h 8 Bytes ;51 76h I/O Address Range(0376h-0377h) ;52 03h I/O Address Range(0376h-0377h) ;53 01h 2 Bytes ;54 EEh IRQ Condition Info. (IRQ14) ;55 15h Tuple ID(CIS TPL_VERS_1) ;56 14h Link to Next Tuple ;57 05h Major Version Number[Ver.5] ;58 00h Minor Version Number[Ver.0] ;59 20h Name of Manufacture ;5A 20h Name of Manufacture ;5B 20h Name of Manufacture ;5C 20h Name of Manufacture ;5D 20h Name of Manufacture ;5E 20h Name of Manufacture ;5F 20h Name of Manufacture ;60 00h End of Manufacture Name ;61 20h Name of Product ;62 20h Name of Product ;63 20h Name of Product ;64 20h Name of Product ;65 00h End of Product Name ;66 30h Product Version “0” ;67 2Eh Product Version "." ;68 30h Product Version "0" ;69 00h End of Product Version ;6A FFh End of Product Info. Tuple ;6B 14h CIS TPL_NO_LINK ;6C 00h Link to Next Tuple ;6D FFh CIS TPL_END ;6E-7F 00h Null-Tuple ; ; -------------------------------------------------------------------------------------; ; Logical Format Parameter ; ; 1 MB 2 MB 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB ;NumCylinder 125 125 250 250 500 500 500 500 ;NumHead 4 4 4 4 4 8 8 16 ;NumSector 4 8 8 16 16 16 32 32 ;SumSector 2,000 4,000 8,000 16,000 32,000 64,000 128,000 256,000 ;SectorSize 512 512 512 512 512 512 512 512 ;Logical Block Size 4k 4k 8k 8k 16k 16k 16k 16k ;Unformatted 1MB 2MB 4MB 8MB 16MB 32MB 64MB 128MB ;Formatted 0.977MB 1.953MB 3.906MB 7.813MB 16.63MB 31.25MB 62.5MB 125MB ; ; Physical Format Parameter ; ;Page Size (byte) 256+8 256+8 512+16 512 +16 512+16 512+16 512+16 512+16 (byte/sectror) ;Number of page/block ? 16 16 16 32 32 32 32 (sectror/Cluster) ;Number of block/device ? 512 512 1024 1024 2048 4096 8192 (Cluster)
; -------------------------------------------------------------------------------------; Sector Data Structure ; [1 Sector = 1 Page] ; 0-255 Data Area-1 ; 256-511 Data Area-2 ; ; Spare Area Information (4 ~ 128 MB) ; 512-515 Reserved Area ; 516 Data/User Status Flag/Area ; 517 Block Status Flag/Area ; 518-519 Block Address Area-1 ; 520-522 ECC Area-2 ; 523-524 Block Address Area-2 ; 525-527 ECC Area-1 ; ; -------------------------------------------------------------------------------------; Block Address Area Information ; [Block Address Configuration] ;D7 D6 D5 D4 D3 D2 D1 D0 1,2 MB SM 4,8,16 MB and above SM ; ;0 0 0 1 0 BA9 BA8 BA7 262 bytes(even) 518, 523 bytes ; 259 bytes(odd) ; ;BA6 BA5 BA4 BA3 BA2 BA1 BA0 P 263 bytes(even) 519, 524 bytes ; 260 bytes(odd) ; ;BA9 ~ BA0 : Block Address (values=0 through n,where n = maximum logical block count - 1) ;P : Even Parity bit ; ; -------------------------------------------------------------------------------------; Block_a Parameter Definition ; - Used Valid Block is block_a[ Physical block number] = bl_addr(Block Address value) ; - Invalid Block is block_a[Physical block number] = 0xffee(Invalid Mark is defined as ‘ 0xffee’ ) ; - CIS Block is block_a[Physical block number] = 0 (Actual Block Addess Value is ‘ 0x0000’ .) ; - Unused Valid Block[Physical block number] = 0xffff ; ; -------------------------------------------------------------------------------------; ; Support Devices ; K9S2808V0M-SSB0 16M x 8 bit SmartMedia Card - tested ; [32768 rows(pages), 528 columns] ; ; ; Command Latch Enable(CLE) ; The CLE input controls the path activation for commands sent to the ; command register. When active high, commands are latched into the ; command register through the I/O ports on the rising edge of the ; WE signal. ; ; Address Latch Enable(ALE) ; The ALE input controls the activating path for address to the internal ; address registers. Addresses are latched on the rising edge of WE with ; ALE high. ; ; Chip Enable(CE) ; The CE input is the device selection control. When CE goes high during ; a read operation the device is returned to standby mode. ; However, when the device is in the busy state during program or erase, ; CE high is ignored, and does not return the device to standby mode. ; ; Write Enable(WE) ; The WE input controls writes to the I/O port. Commands, address and data ; are latched on the rising edge of the WE pulse. ; ; Read Enable(RE) ; The RE input is the serial data-out control, and when active drives the ; data onto the I/O bus. Data is valid tREA after the falling edge of RE ; which also increments the internal column address counter by one. ; ; I/O Port : I/O 0 ~ I/O 7 ; The I/O pins are used to input command, address and data, and to output ; data during read operations. The I/O pins float to high-z when the chip ; is deselected or when the outputs are disabled. ; ; Write Protect(WP) ; The WP pin provides inadvertent write/erase protection during power ; transitions. The internal high voltage generator is reset when the ; WP pin is active low. ; ; Ready/Busy(R/B) ; The R/B output indicates the status of the device operation. When low, ; it indicates that a program, erase or random read operation is ; in process and returns to high state upon completion. It is an open ; drain output and does not float to high-z condition when the chip ; is deselected or when outputs are disabled. ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2002.07.19 VFX Creation ; 1.10 2003.02.02 VFX Redesign all functions ; 1.11 2003.05.05 VFX Remove IO pin and change to XMEM mode ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ;
; *************************************************************************** ;* Const Def ;SmartMedia Commands .EQU SM_ReadLowHalf 0x00h
=
;Page read A .EQU .EQU
0x50h
SM_ReadHiHalf SM_ReadEnd
= 0x01h =
SM_ReadID
=
;Page read C .EQU
0x90h
;Read ID .EQU SM_ReadUnique ;Read Unique 128 bit .EQU SM_Reset ;Device reset .EQU SM_PageProgram ;Ready to write, Serial Data Input .EQU SM_PageProgramTrue ;Start to write page, auto program (Toshiba) .EQU SM_PageProgramDumy ; .EQU SM_PageProgramMultiBlk ; .EQU SM_BlockErase ;Erase block (block#) .EQU SM_BlockErase2nd ;Erase block (start) .EQU SM_ReadStatus ;Read status .EQU SM_ReadMultiPlaneStatus ;
0x91h 0xFFh 0x80h 0x10h 0x11h 0x15h 0x60h 0xD0h 0x70h 0x71h
= = = = = = = = = =
;SMIL Commands .equ
SMIL_Standby
= 0x00h ;Standby
.equ
SMIL_RM_ReadData
= 0x14h ;Data
.equ
SMIL_RM_WriteCmd
= 0x15h ;Command
.equ
SMIL_RM_WriteAddr
= 0x16h ;Address
.equ
SMIL_RM_WriteData
= 0x14h ;Data
.equ
SMIL_WM_ReadData
= 0x94h ;Data
.equ
SMIL_WM_WriteCmd
= 0x95h ;Command
.equ
SMIL_WM_WriteAddr
= 0x96h ;Address
.equ
SMIL_WM_WriteData
= 0x94h ;Data
.equ .equ .equ
SMIL_ResetECCLogic SMIL_RWwithECC SMIL_RWwithoutECC
= 0b01100000 = 0b00100000 = 0b00000000
Mode
Read
( SmartMedia Data Read )
Write ( SmartMedia Data Read ) Write ( SmartMedia Data Read ) Write
Read
( SmartMedia Data Read )
( SmartMedia Data Write)
Write ( SmartMedia Data Write) Write ( SmartMedia Data Write) Write
( SmartMedia Data Write)
;SM Manufacturer ID .equ MakerSamsung = 0xEC .equ MakerToshiba = 0x98
;SM IDs, .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
only 3.3V or 2.7-3.6V devices Sign05 = 0xA4 ;0.5 Mb Sign1 = 0x6E ;1 Mb Sign2 = 0xEA ;2 Mb Samsung Sign2a = 0x64 ;2 Mb Toshiba Sign4 = 0xE3 ;4 MB Samsung Sign4a = 0xE5 ;4 MB Toshiba Sign8 = 0xE6 ;8 Mb Sign16 = 0x73 ;16 MB Sign32 = 0x75 ;32 Mb Sign64 = 0x76 ;64 Mb Sign128 = 0x79 ;128 Mb
.EQU .EQU .equ
SM_UniqueIDcode = 0xA5 SM_MultiplaneSupportCode = 0xC0 ExtendedID = 0x21
.equ SM_Protected = ;bit = 1, media write protect .equ SM_Busy = ;bit = 1, media ready .equ SM_Fail = ;bit = 1, Fail
7 6 0
;SmFlags .EQU .EQU .EQU ;Device < 16 MB .EQU ;Device Unknown
5 4
of
SM_UniqueID = 7 SM_MultiplaneSupport = 6 SM_DeviceTooSmall = SM_DeviceUnkown
=
.equ
W500us
= SYSCLK/8000
;Delay 500us units
.equ
W10us
= SYSCLK/160
;Delay 10us
SYSCLK
; ************************************************************************** ;* Hardware Def. ; ; External Controller Address def. by main.asm ;.equ ADR_SMDATA = 0x3F00 ;SmartMedia Data Register ;.equ
ADR_SMMODE = 0x3F01
;SmartMedia
;.equ
ADR_SMSTAT = 0x3F01
;SmartMedia
Mode Register Mode Register
; *************************************************************************** ;**** VARIABLES .DSEG ;-Memory Card-----------Egymas utan kell aljanak -Struct ;dont remove or insert any line here!! SmManufacturerID: .byte 1 ; SM Manufacturer code SmDeviceCode:
.byte 1
; SM Device
Code SmFlags:
.byte 1
; 7 bit = 1
UniqueID Supported ; 6 bit = 1 MultiPlane Supported SmPages:
.byte 3
; Number of pages
(physical sectors) SmPPB:
.byte 1
; Pages per
block SmBlocks:
.byte 2
; Blocks per Devices
;end struct SMDataBuffer:
.byte 512
;I/O Data
buffer
; *************************************************************************** .ESEG
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG Init_SMedia: ldi sts
R16, SMIL_Standby ADR_SMMODE,R16
;SmartMedia
clr sts
R16 SmManufacturerID,R16
;No valid
sts sts
SmDeviceCode,R16 SmFlags,R16
rcall
SM_ResetDevice
;Reset
rcall
SM_GetType
;Get
lds andi
R18,SmFlags R18,(1<
Controller is StandBy
Card in socket
SmartMedia PrintSMType: SmartMedia Type
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that http://avr-asm.tripod.com/vfxsmil.html (1 of 2)1/20/2009 8:50:36 PM
16 BIT MATH (AVR 202)
are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/vfxsmil.html (2 of 2)1/20/2009 8:50:36 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
VFX MEMORY MANAGER HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305
; *************************************************************************** ; ; File Name :'memory.asm" ; Title :Memory Manager for VFX's DataLog ; Date :2003.08.03. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; MCB ; 0. byte - Type/Flag ; 7. =1 last block ; 6. =1 first block ; 5. =1 used block ; 4. = nc ; 3:0 = process number Hi part ; 1. byte - process number low part ; 2. word - low part of length ; 4. byte - hi part of length ; 5. word - low part offset of prev. MCB ; 7. byte - hi part offset of prev. MCB ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.08.03 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; ***************************************************************************
UART 128 UART BUFF USB 232 AVR ISP ISP 2313
.equ .equ .equ .equ .equ .equ .equ
MCB_Type MCB_Proc MCB_LenL MCB_LenH MCB_PrevL MCB_PrevH MCB_Size
= = = = = = =
0 1 2 4 5 7 8
.equ .equ .equ .equ .equ
MCBLast = 7 MCBFirst = 6 MCBUsed = 5 ProcMask = 0x0F NonProcMask = 0xF0
.equ .equ .equ .equ
MMAP0 MMAP1 MMAP2 MMAP3
.equ .equ
MaxMemoryLW = 0x0000 MaxMemoryHW = 0x0002
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
= = = =
0x0000 0x4000 0x8000 0xC000
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
;max memory
0x00020000 == 128kb ; ; ************************************************************************** ;* Hardware Def. ; ; *************************************************************************** ;**** VARIABLES .DSEG
KBD 240 MUX 242 KBD PS2 KBD PC/128
LargeMCB:
.byte
3
;Egybefuggo nagy blokkok
SmallMCB:
.byte
3
;kicsi blokkok <4kb
>4kb kezdopozicioja
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK
; *************************************************************************** .ESEG
CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG
PWM 10K
ExtSRAMTest:
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
ldi
R20,SRAMBASE
;External
ldi
R18,8
;8x16k page
ldi
R21,0x5A sts ADR_EXHH,R20
;test byte ;
ldi ldi
ZL,0 ZH,192
;Z point to
ldi ldi
XL,low(16384) XH,high(16384)
;Count of
sbiw brne inc dec brne
st XL,1 srt1 R20 R18 SRT0
SRAM Base Address = 128k SRT0: Upper memory to SRAM Banks
AVR BOOK upper memory
test byte srt1:
ldi ldi ldi
Z+,R21 ;fill bank
ldi ldi
R20,SRAMBASE R18,8 R21,0x5A sts ADR_EXHH,R20 ZL,0 ZH,192
ldi ldi
XL,low(16384) XH,high(16384)
cp brne sbiw brne inc dec brne
ld R3,Z+ R21,R3 SRAMERR XL,1 srt3 R20 R18 srt2
SRT2:
;test byte
;Z point to
upper memory ;Count of
test byte srt3:
;check bank
clc ret SRAMERR:
sec ret
;****************************************************** ; Convert Phisycal address to Logical Address ; In: R18:R17:R16 Phisycal address ; Out R18 - page, ; R17:R16 - offset address (must add MMAP1,2,3) ; MmTranslatePhysicalAddress: push R17 rol R17 rol R18 rol R17 rol R18 pop R17 andi R17,0b00111111 ret
;****************************************************** ; Set Page at R18:R16 ; In: R18:R17:R16 Phisycal address ; Out R18 - page+1, ; R17:R16 - offset address on MMAP2 ; Z - mapped address on MMAP2 ; MmSetPage: rcall MmTranslatePhysicalAddress MmSetPageMap: ori R17,high(MMAP2) sts ADR_EXHL,R18 inc R18 sts ADR_EXHH,R18 ;2 page -> no page border fault movw
ZL,R16
;Z - offset
at first page RET
;****************************************************** ; Initialize Memory & setup MCBs ; Mem_Init: ldi R16,S1D_DISPLAY_HEIGHT ldi R17,S1D_DISPLAY_SCANLINE_BYTES mul R16,R17 inc R1 ;skip Video RAM + 256 byte clr
R2
sts sts sts movw mov rcall
LargeMCB+0,R0 LargeMCB+1,R1 LargeMCB+2,R2 R16,R0 R18,R2 MmSetPage
ldi
R16,(1<= old delta
movw mov movw mov rjmp
R12,R16 R14,R18 R8,R0 R10,R2 MMVanMeg
MMTeljesenJo: movw mov clr clr clr rjmp
;First MCB
;delta ;best pointer
R8,R0 R10,R2 R12 R13 R14 MMLastInChain
;pointer
;delta=0
MMVanMeg: ldd sbrc rjmp
R16,Z+MCB_Type R16,MCBLast MMLastInChain
ldd ldd ldd add adc adc add adc adc rjmp
R18,Z+MCB_LenH R17,Z+MCB_LenL+1 R16,Z+MCB_LenL+0 R16,R21 R17,R15 R18,R15 R0,R16 R1,R17 R2,R18 MmNextMCB01
MMLastInChain: mov or or brne rjmp mmMoreM00:
R0,R8 R0,R9 R0,R10 mmMoreM00 mmNoMoreMemory ;Memory block
Allocation/sharing ;Alloc = delta < 40 byte (32+8) ;share = delta => 40 byte ldi clr cp cpc cpc brsh
R16,40 R17 R12,R16 R13,R17 R14,R17 MMShare
movw mov movw mov rcall
R0,R8 R2,R10 R16,R8 R18,R10 MmSetPage
ldd
R16,Z+MCB_Type
ori
R16,(1< Proc
ldd cbr
R16,Z+MCB_Type R16,(1<
mmAllocAll:
;set
MCBUsed & Process
mmMakeFree:
Programming the AVR Microcontrollers in Machine Language
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Search
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ http://avr-asm.tripod.com/vfxmem.html (1 of 2)1/20/2009 8:51:14 PM
16 BIT MATH (AVR 202)
USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/vfxmem.html (2 of 2)1/20/2009 8:51:14 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
BUBBLE SORT (AVR 220) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
DIV 24 24 DIV 3216
Title: Version: Last updated: Target:
Bubble Sort Algorithm 1.0 97.07.04 AT90Sxx1x (Devices with SRAM)
Support E-mail:
[email protected]
DESCRIPTION This Application note shows how to sort a block of
data in SRAM using ;* the code efficient Bubble Sort Algorithm. The App. note contains a test
MATH YX DIV16 XX
A V R 2 2 0
************************
ASM MATH
MATH 202
N O T E
;* program which copies a 60-byte block of data from program memory to ;* SRAM and sorts the data. ;* ; ***************************************************************************
FLOAT 128 .include "8515def.inc"
SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII
.equ .equ
SIZE =60 TABLE_L =$60
;data block size ;Low SRAM address
.equ
TABLE_H =$00
;High SRAM address
of first data element of first data element
HX2ASC
rjmp
RESET
;Reset Handle
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
; *************************************************************************** ;* ;* "bubble" ;* ;* This subroutine bubble sorts the number of bytes found in "cnt1" + 1 ;* with the last element in SRAM at location "last". ;* This implementation sorts the data with the highest element at the ;* lowest SRAM address. The sort order can be reversed by changing the ;* "brlo" statement to "brsh". Signed sort can be obtained by using "brlt" ;* or "brge" ;* ;* Number of words :13 + return ;* Number of cycles :6*(SIZE-1)+10*(SIZE(SIZE-1)) +return (Min) ;* 6*(SIZE-1)+13*(SIZE(SIZE-1)) +return (Max) ;* Low registers used :3 (A,B,cnt2) ;* High registers used :3 (cnt1,endL,endH) ;* Pointers used :Z ;* ; ***************************************************************************
ISP 1200
;***** Subroutine Register Variables
AVR SPI I2C 300
;first value to be
.def
B
=r14
;second value to be
.def .def .def
cnt2 cnt1 endL
=r15 =r16 =r17
;inner loop counter ;outer loop counter ;end of data array
.def
endH
=r18
;end of data array
low address
DALLAS-1W DALLAS CRC
=r13
compared
I2C/TWI 128 I2C/TWI AT8
A
compared
I2C 302 I2C TWI26
.def
high address
ETHNET 8019
;***** Code
TEA bubble: mov mov mov i_loop:
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
ZL,endL ZH,endH cnt2,cnt1 ld A,Z
;init Z pointer ;counter2 <- counter1 ;get first byte, A
B,-Z
;decrement Z and get second
A,B L1 Z,A Z+1,B cnt2 i_loop cnt1 bubble
;compare A with B ;if A not lower ; store swapped
(n) ld byte, B (n-1)
IRD 410
cp brlo st std L1: dec brne dec brne ret
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
;end inner loop ;end outer loop
KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
; *************************************************************************** ;* ;* Test Program ;* ;* This program copies 60 bytes of data from Program memory to SRAM. It ;* then calls "bubble" to get the data sorted. ;* ; ***************************************************************************
DTMF 314
RESET:
PWM 6CH
;***** Main program Register variables
PWM 10K .def
ENCODE STH-11
temp
=r16
;***** Code
ATMEL CORP ldi out ldi out
AVR BUTTERFLY AVR BOOK
temp,low(RAMEND) SPL,temp temp,high(RAMEND) SPH,temp ;init Stack Pointer
;***** Memory fill clr ldi
ZH ZL,tableend*2+1 ;Z-pointer <- ROM table end
ldi ldi
YL,low(256*TABLE_H+TABLE_L+SIZE) YH,high(256*TABLE_H+TABLE_L+SIZE) ;Y pointer <- SRAM table
+ 1
end + 1 loop: st
lpm -Y,r0
;get ROM constant ;store in SRAM and
ZL,1 YL,TABLE_L loop YH,TABLE_H loop
;decrement Z-pointer ;if not done ; loop more
decrement Y-pointer sbiw cpi brne cpi brne
;***** Sort data sort: ldi ldi rcall
ldi endL,low(TABLE_H*256+TABLE_L+SIZE-1) endH,high(TABLE_H*256+TABLE_L+SIZE-1) ;Z <- end of array address cnt1,SIZE-1 ;cnt1 <- size of array - 1 bubble
forever:rjmp
forever
;***** 60 ROM Constants table: .db 120,196 .db 78,216 .db 78,100 .db 43,39 .db 241,43 .db 62,172 .db 109,69 .db 48,184 .db 215,231 .db 63,133 .db 216,8 .db 121,126 .db 188,98 .db 168,205 .db 157,172 .db 108,233 .db 80,255 .db 252,102 .db 198,0 .db 171,239 .db 107,114 .db 172,170 .db 17,45 .db 42,55 .db 34,174 .db 229,250 .db 12,179 .db 187,243 .db 44,231 tableend: .db 76,48
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr220.html (1 of 2)1/20/2009 8:51:49 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr220.html (2 of 2)1/20/2009 8:51:49 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
CIRCULAR REDUNDANCY CHECK (AVR 236) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3
MATH 202 com for the latest and updated
;* version of the software. ;* ;* DESCRIPTION ;* This application note describes how to perform CRC
MATH YX DIV16 XX computation
;* of code memory contents using a simple algoritm. ;* To generate CRC checksum load the register "status"
DIV 3216 FLOAT 128
with 00 and call the routine ;* "crc_gen". The resulting checksum is placed in the
SQRT16 MATH 202
registers ;* byte_2(low byte) and byte_3(high byte). ;* ;* To check the CRC checksum load the register "status"
MATH 202 DEC ASCII
with FF and call the routine
INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108
CRC check of program memory 1.3 11.11.2004 AT90Sxxx, ATtinyxxx, ATmegaxxx (All AVR Devices with LPM
;* ;* Support E-mail: [email protected] ;* ;* NOTE: Always check out Atmels web site, www.atmel.
MATH 201
DIV 24 24
Title: Version: Last updated: Target:
instr, not AT90S1200)
MATH 200b
MATH 32X
A V R 236
************************
ASM MATH
MATH 200
N O T E
;* "crc_gen". The resulting checksum is placed in the registers ;* byte_2(low byte) and byte_3(high byte). If the checksum is 00 the program code is ;* correct, if the checksum is non-zero an error has been introduced in the program code ; **************************************************************************
EPROM 100 .include "8515def.inc"
SER EPROM DFLASH AT45
;***** Constants
FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128
.equ Last program memory address(byte address) .equ divisor value
LAST_PROG_ADDR CR
= 0x1FFF
= 0x8005
; ; CRC
; ************************************************************************** ;* ;* PROGRAM START - EXECUTION STARTS HERE ;* ; **************************************************************************
UART BUFF USB 232
;
AVR ISP
.org $0000 rjmp RESET
ISP 2313
.cseg
;Reset handle
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
; *************************************************************************** ;* ;* "crc_gen" - Generation and checking of CRC checksum ;* ;* This subroutine generates the checksum for the program code. ;* 32 bits are loaded into 4 register, the upper 16 bits are XORed ;* with the divisor value each time a 1 is shifted into the carry flag ;* from the MSB. ;* ;* If the status byte is 0x00,the routine will generate new checksum: ;* After the computing the code 16 zeros are ;* appended to the code and the checksum is calculated. ;* ;* If the status byte is different from 0X00, the routine will check if the current checksum is valid. ;* After the computing the code the original checksum are ;* appended to the code and calculated. The result is zero if no errors occurs ;* The result is placed in registers byte_2 and byte_3 ;* ;* Number of words :44 + return ;* Number of cycles :program memory size(word) * 175 (depending on memory contens) ;* Low registers used :6 (byte_0,byte_1,byte_2, byte_3) ;* High registers used :7 (sizel,sizeh,crdivl,crdivh, count,status,zl,zh) ;* ; ***************************************************************************
BOOT DR8 ;***** Subroutine Register Variables
ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
byte_0
= r0
; Lower byte of
.def
byte_1
= r1
; Upper byte of
.def
byte_2
= r2
; Lower byte of
.def
byte_3
= r3
; Upper byte of
.def
crc
= r4
; CRC
.def
crch
= r5
; CRC
.def .def .def .def .def count .def
sizel sizeh crdivl crdivh = r21 status
crc_gen: ldi
sizel,low(LAST_PROG_ADDR)
lower word lower word upper word
DTMF 314 PWM 6CH
upper word
PWM 10K
checksum low byte
ENCODE STH-11
.def
checksum high byte
ATMEL CORP AVR BUTTERFLY AVR BOOK
= = = = ; =
r17 ; Program code size register r18 r19 ; CRC divisor register r20 Bit counter r22 ; Status byte: generate(0)
or check(1)
;Load last
program memory address ldi clr clr ldi ldi lpm
sizeh,high(LAST_PROG_ADDR) zl ;Clear Z pointer zh crdivh,high(CR);Load divisor value crdivl,low(CR) ;Load first memory
mov adiw lpm
byte_3,byte_0 zl,0x01
mov
byte_2,byte_0
location ;Move to highest byte ;Increment Z pointer ;Load second memory
location
next_byte: cp cpc
zl,sizel zh,sizeh
;Loop starts here ;Check for end of
brge adiw lpm mov adiw lpm
end zl,0x01
;Jump if end of code
rcall rjmp
rot_word next_byte
code
;Load high byte ;Move to upper byte ;Increment Z pointer ;Load program
byte_1,byte_0 zl,0x01
memory location ;Call the rotate routine
end: ;ret
;uncomment this line if checksum is stored
ldi cpi brne clr clr
count,0x11 status,0x00 check byte_0 byte_1
in last flash memory address.
;Append 16 bits(0x0000) to ;the end of the code for
CRC generation rjmp check: mov
gen byte_0,crc
;Append the
original checksum to mov
byte_1,crch
;the end of the code for
rot_word crc,byte_2 crch,byte_3
;Call the rotate routine
CRC checking gen: rcall mov mov ret rot_word: ldi rot_loop: dec breq
;Return to main prog
count,0x11 count stop
;Decrement bit counter ;Break if bit
lsl rol
byte_0 byte_1
;Shift zero into lowest bit ;Shift in carry from
rol rol brcc
byte_2 byte_3 rot_loop
;Preceede shift
counter = 0
previous byte
;Loop if MSB =
0 eor eor rjmp stop: ret
byte_2,crdivl byte_3,crdivh rot_loop
;XOR high word if MSB = 1
; *************************************************************************** ;* ;* EERead_seq ;* ;* This routine reads the ;* EEPROM into the global register variable "temp". ;* ;* Number of words :4+ return ;* Number of cycles :8 + return ;* High Registers used :4 (temp,eeadr,eeadrh, eedata) ;* ; *************************************************************************** .def .def .def .def
temp eeadr eeadrh eedata
= r16 = r23 = r24 = r25
;***** Code eeread: out out sbi
EEARH,eeadrh EEARL,eeadr EECR,EERE
;output address high byte ;output address low byte ;set EEPROM Read
eedata,EEDR
;get data
strobe in ret
; *************************************************************************** ;* ;* EEWrite ;* ;* This subroutine waits until the EEPROM is ready to be programmed, then ;* programs the EEPROM with register variable "EEdwr" at address "EEawr" ;* ;* Number of words :7 + return ;* Number of cycles :13 + return (if EEPROM is ready) ;* Low Registers used :None ;* High Registers used: ;4 (temp,eeadr,eeadr,eedata) ;* ; *************************************************************************** .def .def .def .def
temp eeadr eeadrh eedata
= r16
eewrite: sbic rjmp out out out sbi sbi
EECR,EEWE EEWrite EEARH,eeadrh EEARL,eeadr EEDR,eedata EECR,EEMWE EECR,EEWE
= r23 = r24 = r25
;If EEWE not clear ; Wait more ;Output address high byte ;Output address low byte ;Output data ;Set EEPROM Write
strobe ret ; ************************************************************************ ;* ;* Start Of Main Program ;* .cseg .def crc = r4 ;Low byte of checksum to be returned .def crch = r5 ;High byte of checksum to be returned .def temp = r16 .def status = r22 ;Status byte: generate(0) or check(1) .def eeadr = r23 .def eeadrh = r24 .def eedata = r25 RESET: ldi
r16,high(RAMEND)
;Initialize stack
out
SPH,r16
;High byte only
ldi
r16,low(RAMEND) ;RAM is bigger than 256
out
SPL,r16
ldi out out clr
temp,0xff DDRB,temp PORTB,temp status
rcall
crc_gen
ldi
eeadr,0x01
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
mov
eedata,crc
;Set CRC low byte in EEPROM
rcall
eewrite
;Write EEPROM
ldi
eeadr,0x02
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
mov
eedata,crch
;Set CRC high byte in
rcall
eewrite
;Write EEPROM
out
PORTB,crc
;Output CRC low value to
EECR,EEWE mainloop
;If EEWE not clear ; Wait more
pointer required if Bytes
;Set PORTB as output ;Write 0xFF to PORTB ;Clear status register,
prepare for CRC generation
EEPROM write EEPROM write data
EEPROM write EEPROM write EEPROM data
PORTB mainloop: sbic rjmp
;********** Insert program code here ************* ldi
eeadr,0x01
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
rcall mov
eeread crc,eedata
;Read EEPROM ;Read CRC low byte from
ldi
eeadr,0x02
;Set address low byte for
ldi
eeadrh,0x00
;Set address high byte for
rcall mov
eeread crch,eedata
;Read EEPROM ;Read CRC low byte from
ser
status
;Set status register,
rcall
crc_gen
EEPROM read EEPROM read
EEPROM
EEPROM read EEPROM read
EEPROM
prepare for CRC checking
loop: out
PORTB,crc
;Output CRC low value to
PORTB rjmp loop .exit
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the http://avr-asm.tripod.com/arv236.html (1 of 2)1/20/2009 8:52:28 PM
16 BIT MATH (AVR 202)
same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/arv236.html (2 of 2)1/20/2009 8:52:28 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
XMODEM RECEIVE ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220
; *************************************************************************** ; ; File Name :'xmodem.asm" ; Title :XMODEM only receive ; Date :2002.07.03. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2002.07.03 VFX Creation ; ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* Kvarc: f=7.3728 MHz (T=135.63368 ns) ;* ; *************************************************************************** ; ; ; ; *************************************************************************** ;* Const Def
CRC 236 .EQU
Xmodem_Sync
=
0
;
.EQU
Xmodem_SOH
=
1
;SOH byte-
.EQU
Xmodem_Fill
=
2
;SOH byte
Xmodem_Err
=
3
;megszakadt
SyncTiming
=
300
;ket
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
szinkronizalasi fazis ra var megjott, block init megvolt .EQU az atvitel, NAK kuldese 3 masodpercenkent
AVR ISP ISP 2313
.EQU karakter elkuldese kozott
ISP 1200 AVR SPI
;eltelt ido szinc. uzemmodban 3sec @100Hz
I2C 300 I2C 302 I2C TWI26 I2C/TWI 128
; ************************************************************************** ;* Hardware Def. ;
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
; *************************************************************************** ;**** VARIABLES .DSEG
TEA ADC 128 ADC 10B
CRC:
.BYTE
XmodemFlag: .BYTE
1
Xm_BlkCounter:
.BYTE
XmodemPTR:
1
;Xmodem Buffer
XmodemBuf: .BYTE FileLength: .byte LastPocketSize:
133 4 .byte
;XMODEM RxBuffer ;File hossz 32 bites ;utolso
XmodemMode: .byte
1
;Mode0 - Nul modem
.byte
;Mode1 - DSP Boot ;Xmodem
BOOT MG8 BOOT DR8 ALM CLK
1
letolti de nem csinal semmit
KBD PC/128 PS2 EMU
.BYTE
pocket merete byte-ban [0...128]
MUX 242 KBD PS2
;Xmodem
pointer
LCD44 2313 KBD 240
1
Block Counter [00-FF]
LCD HD44 LCD 2313
;Xmodem Flag ;[2:0] = 000
sending 'c' Phase 1: syncronize
THERM 232 IRD 410
; CRC for
XMODEM
ADC 400 ADC 401
2
Xm_ErrorCNT:
1
Time to Abort counter ; *************************************************************************** .ESEG
CLOCK 8564 90 DAYS DELAYS
; *************************************************************************** .CSEG
CALL ID DTMF 314 PWM 6CH PWM 10K
; *************************************************************************** ;** Init Xmodem File Receive ;**
ENCODE Init_Xmodem:
STH-11
ldi R16,128 LastPocketSize,R16 R0 FileLength+0,R0 FileLength+1,R0 FileLength+2,R0 FileLength+3,R0 Xm_ErrorCNT,R0 XmodemFlag,R0 Xm_BlkCounter,R0 clr R0 CRC+0,R0 CRC+1,R0 XmodemPTR,R0 SCNT2+0,R0 SCNT2+1,R0
sts clr sts sts sts sts sts sts sts Init_XmNextBl: sts sts sts STS STS ret
ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;** Calc & Update XMODEM CRC ;* ;* In: R0 - data byte
UpdateCRC:
lds mov swap mov
R17,CRC+1 R15,R17 R17 R16,R17
eor andi andi eor
R17,R15 R17,0xF0 R16,0x0F R15,R16
mov lsl rol
R14,R17 R14 R16
eor eor
R15, R14 R17,R16
lds eor eor
R14,CRC+0 R15,R0 R17,R14
sts sts ret
CRC+0,R15 CRC+1,R17
; *************************************************************************** ;** XMODEM Receive File & Block ;* ;* Xmodem_Rec: lds R16,XmodemFlag cpi R16,Xmodem_Sync breq Xm_Sync cpi brne rjmp
R16,Xmodem_Fill Xmodem_Rec1 Xm_Fill
Xmodem_Rec1:
Xm_Sync:
breq
cpi Xm_SOH
R16,Xmodem_SOH
cpi breq
R16,Xmodem_Err Xm_Sync
rjmp
Xmodem_Cancel
call brcs
Rs232GetByte Xm_valamijott ;itt meg
mindig nem jott semmi lds lds or
R16,SCNT2+0 R17,SCNT2+1 R16,R17
breq ret
Xm_Sync1
ldi
R16,NAK
lds cpi breq
R17,XmodemFlag R17,Xmodem_Err Xm_Sync2
;Timer
lejart?
Xm_Sync1: hiba van
;akkor, ha
NAK megy 3 masodpercenkent
;mivel meg mindig nem jott semmi kuldunk egy ;CRC karaktert 3 masodpercenkent lds
R16,Xm_ErrorCNT
inc sts cpi brne rjmp
R16 Xm_ErrorCNT,R16 R16,20 Xm_Sync25 Xm_Abort
Xm_Sync25:
ldi
R16,'C'
Xm_Sync2:
call ldi
SendChrW R16,Low(SyncTiming)
sts ldi sts ret
SCNT2+0,R16 R17,High(SyncTiming) SCNT2+1,R17
;ha 20 'C'
ideig nem jon semmi akkor abort!!!
;Timer=3sec
@100Hz
Xm_SOH:
call Rs232GetByte Xm_valamijott
brcs ret Xm_valamijott: cpi breq cpi breq cpi breq
mov R16,R0 R16,CAN Xmodem_Cancel R16,SOH Xmodem_StartOfH R16,EOT Xmodem_EndOfT rjmp Xmodem_Rec
Xm_ByteStr: .db
" Bytes received ",CR,0 ;End of
Trans == Canacel Xmodem_EndOfT: ldi call
R16,ACK SendChrW
;Pozitiv
ldi call
R16,CR SendChrW
;soremeles
lds lds lds lds call
R16,FileLength+0 R17,FileLength+1 R18,FileLength+2 R19,FileLength+3 ULTOA
;ACC1 LSByte
ldi
XL,low(ASCIIBuf)
;Ascii
ldi
XH,high(ASCIIBuf)
nyugta Xm_Abort:
FileLength
Buffer Ptr ;ldi R22,12 call
PrintASCII
;rcall
ldi ldi call
R16,Low(Xm_ByteStr) R17,High(Xm_ByteStr) SendStrW
DumpASCII
Xmodem_Cancel:
lds
R16,Term_Stat
;
End of Xmodem receiving cbr
R16,Term_Rec_Xmodem
sts
Term_Stat,R16
lds cpi brne
R17,XmodemMode R17,1 Xm_CancelEnd
;Normal
Terminal Mode
;itt lesz vege a FALSH update-nak Xm_CancelEnd: sts
clr R17 Updating,R17
;Ezel
sts
XmodemMode,R17
;barmi volt
jmp
CMDOk
jelzzuk keszen vagyunk is, most null modem
Xmodem_StartOfH: ldi sts rcall ldi
R16,Xmodem_Fill XmodemFlag,R16 Init_XmNextBl ZL,Low(SyncTiming)
;Timer=3sec
sts
SCNT2+0,ZL
;he nem jon
ldi sts rjmp
ZL,High(SyncTiming) SCNT2+1,ZL Xmodem_Rec
call
Rs232GetByte
;itt
brcs
Xm_data
; blk
@100Hz ujjab byte, akkor baj van!!
Xm_Fill: beolvasunk 132 byte-ot counter,255-blk counter [2 byte]
; adatblok [128 byte] ; CRC [2 byte] ;total 132 byte lds
R16,SCNT2+0
;he nem jon
lds or brne
R17,SCNT2+1 R16,R17 Xm_vanido
ldi sts
R16,Xmodem_Err XmodemFlag,R16
;Time Out,
ldi
ZL,Low(SyncTiming)
;Timer=3sec
sts
SCNT2+0,ZL
;he nem jon
ldi sts
ZL,High(SyncTiming) SCNT2+1,ZL
ldi ldi clr lds add adc
ZL,Low(XmodemBuf) ZH,High(XmodemBuf) R1 R16,XmodemPTR ZL,R16 ZH,R1
;ZL:ZH ->
st
Z,R0
;Char
inc sts cpi
R16 XmodemPTR,R16 R16,3
;3
ujjab byte, akkor baj van!!
Ismetles kell Xm_vanido:
ret
Xm_data: @100Hz ujjab byte, akkor baj van!!
Xmodem Actualis Pos. eltarolasa
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations http://avr-asm.tripod.com/xmodemrec.html (1 of 2)1/20/2009 8:53:11 PM
16 BIT MATH (AVR 202)
R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/xmodemrec.html (2 of 2)1/20/2009 8:53:11 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
HALF DUPLEX SOFTWARE UART (AVR 304) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* Title: ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
MATH 202
AVG8 222 FFT7
;* ;* The constants N and R determine the data rate. R selects clock frequency ;* as described in the T/C Prescaler in the AVR databook. If the T/C pre;* scaling factor is denoted C, the following expression yields the data rate: ;* ;* XTAL ;* BAUD = -----min. N*C = 17 ;* N*C max. N = 170 ;* ;* Absolute minimum value for N*C is 17 (which causes the interrupt flag to be
FLASH CARD
;* set again before the interrupt is finished).
VFX SMIL
Absolute maximum is 170.
VFX MEM
receive bits correctly.)
;* (Caused by the 1.5bit-lenght that is necessary to ;* ;* The UART uses PD2 as receive pin because it utilizes
SORT 220 the external interrupt.
;* The transmit-pin is PD4 in this example, but it can
XMODEM REC be any other pins.
;* ;* Since the UART is half duplex, it can either send or
UART 305
UART BUFF USB 232
recieve data. It can't ;* do both simoutaneausly. When idle it will automatically recieve incoming ;* data, but if it is transmitting data while incoming data arrives, it will
AVR ISP
;* ignore it. Also, if u_transmit is called without
ISP 2313
waiting for the 'READY' bit
ISP 1200
will abort any pending
;* in the 'u_status' register to become cleared, it ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
This application note describes how to make a half
resources.
SER EPROM
UART 128
DESCRIPTION
;* only, a half duplex UART will limit the usage of MCU
EPROM 100
UART 304
Code Size :72 words Low Register Usage :2 High Register Usage :5 Interrupt Usage :External Interrupt, Timer/Counter0 overflow interrupt
direction at a time
LPM 108
CRC 236
[email protected]
;* As a lot of control applications communicate in one
COPY 102
DFLASH AT45
Support E-mail:
External Interrupt.
INT ASCII HX2ASC
1.0 97.07.18 AT90Sxxxx (All AVR Devices)
;* on any AVR device with the 8-bit Timer/Counter0 and
MATH 202 DEC ASCII
Version: Last updated: Target:
duplex software UART
FLOAT 128 SQRT16
Half Duplex Interrupt Driven
Software UART
TUTORIAL #2
DIV 3216
A V R 3 0 4
************************
ASM MATH TUTORIAL #1
N O T E
reception or transmittal.
*** Initialization 1. Call uart_init 2. Enable global interrupts (with 'sei') *** Receive 1. Wait until RDR in 'u_status' becomes set 2. Read 'u_buffer' *** Transmit (0. Initialize the UART by executing uart_init and
sei) ;* 1. Wait until READY in 'u_status' becomes clear ;* 2. Set 'u_buffer' ;* 3. Call 'u_transmit' ;* ; **************************************************************************
LCD HD44 .include "1200def.inc"
LCD 2313
;***** BAUD-rate settings
LCD44 2313 KBD 240 MUX 242
;BAUD-RATES @1MHz XTAL AND R=1 ;.equ ;.equ .equ .equ .equ
KBD PS2 KBD PC/128 PS2 EMU
N=104 N=52 N=26 C=1 R=1
; 9600 ;19200 ;38400 ;Divisor ;R=1 when C=1
BOOT MG8 BOOT DR8 ;***** UART Global Registers
ALM CLK CLOCK 8564 90 DAYS
u_buffer u_sr
=r14 =r15
;Serial buffer ;Status-register
.def .def .def .def
u_tmp u_bit_cnt u_status u_reload
=r16 =r17 =r18 =r19
;Scratchregister ;Bit counter ;Status buffer ;Reload-register
.def
u_transmit
=r20
;Data to transmit
storage
DELAYS CALL ID DTMF 314 PWM 6CH
.def .def
(internal - do not use)
PWM 10K ENCODE ;***** Bit positions in the Status-register
STH-11 ATMEL CORP AVR BUTTERFLY
.equ
RDR=0
;Receive data ready
.equ
TD=6
;Transmitting data
.equ
BUSY=7
;Busy-flag
bit (internal - read-only)
AVR BOOK (internal - read-only)
; ************************************************************************** ;* ;* PROGRAM START - EXECUTION STARTS HERE ;* ; ************************************************************************** .cseg .org $0000 rjmp start
;Reset handler
.org INT0addr rjmp ext_int0
;External interrupt
.org OVF0addr rjmp tim0_ovf
;Timer0 overflow
.org ACIaddr reti
;Analog comparator
handler
handler
handler (Not Used)
; ************************************************************************** ;* ;* EXT_INT0 - External Interrupt Routine 0 ;* ;* ;* DESCRIPTION ;* This routine is executed when a negative edge on the incoming serial ;* signal is detected. It disables further external interrupts and enables ;* timer interrupts (bit-timer) because the UART must now receive the ;* incoming data. ;* ;* This routine sets bits in the GIMSK, TIFR and TIMSK registers. In this ;* code when the bits are set, it overwrites all other bits. This is done ;* because of the lack of available cycles when it operates at low clock ;* rate and high baudrates. ;* ;* ;* Total number of words : 12 ;* Total number of cycles : 15 (incl. reti) ;* Low register usage : 1 (u_sr) ;* High register usage : 4 (u_bit_cnt, u_tmp,u_status,u_reload) ;* ; ************************************************************************** ext_int0: in u_sr,SREG ;Store Status Register ldi rjmp
u_status,1<7) is set tim0_stopb
;
sbrc
u_buffer,0
;if LSB in buffer
sbi
PORTD,PD4
;
sbrs
u_buffer,0
;if LSB in buffer
cbi
PORTD,PD4
;
lsr
u_buffer
;Shift buffer right
out reti
SREG,u_sr
;Restore SREG
jump to stop-
bit-part
is 1 Set transmit
to 1 is 0 Set transmit
to 0
tim0_stopb: sbi PORTD,PD4
;Generate stop-bit
sbrs
u_bit_cnt,0
;if u_bit_cnt==8
rjmp
tim0_ret
;
(stop-bit) jump to exit
tim0_complete: ldi u_tmp,1<' is sent back. The character is also ;* presented on port B. ;* ; ************************************************************************** .def
tmp=r21
;Temp.
.def
buffer=r22
;Recieved
.def
adr=r23
;EEPROM
start: out
ser tmp PORTD,tmp
;Initialize ;Set port D as
sbi
DDRD,DDD4
;
out
DDRB,tmp
;Set port B as
out
PORTB,tmp
rcall sei
uart_init
register byte Address
input with pullups except PD4 ->
output with 1's output with 1's (LED-off)
idle:
sbrs
;Init UART ;Enable interrupts
u_status,RDR
;Wait for
Character rjmp mov
idle buffer,u_buffer
;Get recieved
out
PORTB,u_buffer
;Output the byte on
ldi
adr,example_data
;Set/Restore
character port B pointer to EEPROM data loop:
out
EEAR,adr
;Set the
EEPROM's address sbi
EECR,EERE
;Send the Read
in
u_transmit,EEDR
;Put the data in
rcall
uart_transmit
;And transmit the
strobe the transmit register data wait:
sbrc
u_status,TD
;Wait until
data is sent rjmp
wait
inc cpi
adr adr,example_data+12
;Increase pointer ;Reached byte 12?
breq
idle
;
cpi brne
adr,example_data+10 loop
;Reached byte 10? ; No, jump back
mov
u_transmit,buffer
;Put data in
rcall
uart_transmit
;And transmit it
(End?) Yes, wait for
new char.
transmit register
wait2:
sbrc
u_status,TD
;Wait until
data is sent rjmp
wait2
rjmp
loop
;Continue sendig
chars
; ************************************************************************** ;* ;* Test/Example program data. ;* ;* This is the data that will be sent back when a character is recieved. ;* ; ************************************************************************** .eseg example_data: .db 89 ;'Y' .db 111 ;'o' .db 117 ;'u' .db 32 ;' ' .db 116 ;'t' .db 121 ;'y' .db 112 ;'p' .db 101 ;'e' .db 100 ;'d' .db 32 ;' ' .db 13 ; .db 10 ;
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC http://avr-asm.tripod.com/avr304.html (1 of 2)1/20/2009 8:53:46 PM
16 BIT MATH (AVR 202)
Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr304.html (2 of 2)1/20/2009 8:53:46 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
HALF DUPLEX SOFTWARE UART (AVR 305) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* Title ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX
DIV 3216 FLOAT 128 SQRT16
: Half Duplex Interrupt Driven
Software UART
TUTORIAL #2
DIV 24 24
A V R 3 0 5
************************
ASM MATH TUTORIAL #1
N O T E
Version Last updated Target
: 1.1
Support email
: [email protected]
: 97.08.27 : AT90Sxxxx (All AVR Device)
Code Size Low Register Usage High Register Usage Interrupt Usage : None
: 32 Words : 0 : 4
DESCRIPTION This Application note contains a very code efficient
software UART. ;* The example program receives one character and echoes it back. ; ***************************************************************************
MATH 202
.include "1200def.inc"
MATH 202 ;***** Pin definitions
DEC ASCII INT ASCII HX2ASC
pin is PD0
AVG8 222
pin is PD1
FFT7
.equ
RxD
=0
;Receive
.equ
TxD
=1
;Transmit
;***** Global register variables
COPY 102 LPM 108 EPROM 100
.def .def
bitcnt temp
=R16 =R17
;bit counter ;temporary
.def
Txbyte
=R18
;Data to be
.def
RXbyte
=R19
;Received
storage register
SER EPROM DFLASH AT45
transmitted
FLASH CARD VFX SMIL
data
VFX MEM
.cseg .org 0
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
; *************************************************************************** ;* ;* "putchar" ;* ;* This subroutine transmits the byte stored in the "Txbyte" register ;* The number of stop bits used is set with the sb constant ;* ;* Number of words :14 including return ;* Number of cycles :Depens on bit rate ;* Low registers used :None ;* High registers used :2 (bitcnt,Txbyte) ;* Pointers used :None ;* ; *************************************************************************** .equ sb =1 ;Number of stop bits (1, 2, ...)
I2C/TWI 128 I2C/TWI AT8
putchar:
ldi
bitcnt,9+sb
;1+8+sb (sb is # of
com sec
Txbyte
;Inverte everything ;Start bit
putchar0:
brcc cbi rjmp
putchar1 PORTD,TxD putchar2
;If carry set ; send a '0' ;else
putchar1:
sbi nop
PORTD,TxD
;
putchar2:
rcall UART_delay rcall UART_delay
;One bit delay
lsr dec brne
;Get next bit ;If not all bit sent ; send next ;else ; return
stop bits)
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
Txbyte bitcnt putchar0
ret
LCD44 2313
send a '1'
KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
; *************************************************************************** ;* ;* "getchar" ;* ;* This subroutine receives one byte and returns it in the "Rxbyte" register ;* ;* Number of words :14 including return ;* Number of cycles :Depens on when data arrives ;* Low registers used :None ;* High registers used :2 (bitcnt,Rxbyte) ;* Pointers used :None ;* ; ***************************************************************************
DTMF 314 PWM 6CH
getchar:
ldi
bitcnt,9
;8 data bit + 1
getchar1:
sbic rjmp
PIND,RxD getchar1
;Wait for start bit
stop bit
PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
getchar2:
rcall UART_delay
;0.5 bit delay
rcall UART_delay rcall UART_delay
;1 bit delay
clc sbic sec
PIND,RxD
;clear carry ;if RX pin high ;
dec breq
bitcnt getchar3
ror
Rxbyte
;If bit is stop bit ; return ;else ; shift bit into
rjmp
getchar2
;
AVR BOOK
Rxbyte
getchar3:
go get next
ret
; *************************************************************************** ;* ;* "UART_delay" ;* ;* This delay subroutine generates the required delay between the bits when ;* transmitting and receiving bytes. The total execution time is set by the ;* constant "b": ;* ;* 3·b + 7 cycles (including rcall and ret) ;* ;* Number of words :4 including return ;* Low registers used :None ;* High registers used :1 (temp) ;* Pointers used :None ;* ; *************************************************************************** ; Some b values: (See also table in Appnote documentation) ; ; 1 MHz crystal: ; 9600 bps - b=14 ; 19200 bps - b=5 ; 28800 bps - b=2 ; ; 2 MHz crystal: ; 19200 bps - b=14 ; 28800 bps - b=8 ; 57600 bps - b=2 ; 4 MHz crystal: ; 19200 bps - b=31 ; 28800 bps - b=19 ; 57600 bps - b=8 ; 115200 bps - b=2 .equ
b
=31
UART_delay: ldi UART_delay1: brne
;19200 bps @ 4 MHz crystal
temp,b dec temp UART_delay1
ret ;***** Program Execution Starts Here ;***** Test program reset:
sbi
PORTD,TxD
;Init port
pins
forever:
sbi
DDRD,TxD
ldi rcall
Txbyte,12 putchar
rcall mov rcall rjmp
getchar Txbyte,Rxbyte putchar forever
;Clear terminal
;Echo received char
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr305.html (1 of 2)1/20/2009 8:54:26 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr305.html (2 of 2)1/20/2009 8:54:26 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
UART ROUTINES FOR ATMEGA128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; *************************************************************************** ; ; File Name :'M_rs232.asm" ; Title : ATmega128 UART, RS-232 komunikacios rutinok ; Date :2003.02.08. Lastmod.: [2003.02.08.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) ; ;Circular serial I/O buffers, with handshake handling for hardware. ;Interupt driven, thus 'transparent' to User functions ; ;You have a head and tail pointer, a constant that tells the size of the array ; ;One thing to note, is that the buffer store routine is only concerned with the ;tail pointer, and the recall routine is only concerned with the head pointer. ;Only the buffer init routine is concerned with both pointers! ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2001.07.21 VFX Creation (Base on 8515) ; 1.00 2003.02.08 VFX Redesign for Atmega128 ; ; *************************************************************************** ; ; Init_UART ; SendChr ; SendStr ; ; ;Hardware ; *************************************************************************** ;* ;RTS pin , Adas keres DSUB9 7. .equ SER_HSO_PORT=PORTD ;Hardware Handshake output port .equ SER_HSO_DIR=DDRD ;Hardware Handshake output control .equ SER_HSO=7 ;Hardware Handshake Output bit
DALLAS-1W ;CTS pin , Vetelkezseg
DALLAS CRC ETHNET 8019 TEA ADC 128
nyugtazo DSUB9 8. .equ
SER_HSI_PORT=PIND
;Hardware Handshake
.equ
SER_HSI_DIR=DDRD
;Hardware Handshake
.equ
SER_HSI=5
;Hardware Handshake
input port input control
ADC 10B ADC 400
Input bit
ADC 401 .MACRO HS_Enabled cbi
THERM 232 IRD 410
;
SER_HSO_PORT,SER_HSO
;
Set low, HS to off
LCD HD44
.endm
LCD 2313
.MACRO HS_Disabled sbi
LCD44 2313 KBD 240
SER_HSO_PORT,SER_HSO
Set Hi for Dis .endm
MUX 242 KBD PS2 KBD PC/128 PS2 EMU
; ************************************************************************** ;* Const Def
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ******************************************************************** ; ;ASCII Equivalents ; .equ NUL=0x00 ;Null .equ SOH=0x01 ;Start of Header .equ STX=0x02 ;Start of Text .equ ETX=0x03 ;End of Text .equ EOT=0x04 ;End of Transmission .equ ENQ=0x05 ;Enquiry .equ ACK=0x06 ;Acknowlege .equ BEL=0x07 ;Bell .equ BS=0x08 ;Backspace .equ HT=0x09 ;Horizontal Tab .equ LF=0x0A ;Line Feed .equ VT=0x0B ;Vertical Tab .equ FF=0x0C ;Form Feed .equ CR=0x0D ;Carriage Return .equ SO=0x0E ; .equ SI=0x0F ; .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
DLE=0x10 XON=0x11 XOFF=0x12 DC3=0x13 DC4=0x14 NAK=0x15 SYN=0x16 ETB=0x17 CAN=0x18 EM=0x19 SUB=0x1A ESC=0x1B FS=0x1C GS=0x1D RS=0x1E US=0x1F
;Delete ;AKA DC1 ;AKA DC2 ; ; ;Negative Acknowlege ;Sync ; ;Cancel ; ;End of File ; ;Field Separator ;Group Separator ;Record Separator ;
;From the data sheet:BAUD = XTAL/(16*(UBRR+1)) ;Rearranging you get:UBRR = XTAL/(16*BAUD) - 1 ; ;This would work except that any fraction will be truncated. ;For least error we want to round off the result. ;So we add 1/2 as follows: UBRR = XTAL/(16*BAUD) - 1 + 0.5 ;Combining the -1 and the +0.5 we can rewrite this as follows: ; ;UBRR = INT(XTAL/(16*BAUD) - 0.5) .equ .equ
Rx_Buffer_Length = 24 Tx_Buffer_Length = 32
.equ
SendROMTXT = 0x02
;RS232 Tx
.equ
FlSending = 0b00000001
;Tx Send
.equ
FlSendROM = 0b00000010
;Tx Send
func. Send ROM text to RS232
running ROM TXT Flag
; *************************************************************************** .DSEG Rx_Buffer: Rx_Head: Rx_Tail: Rx_Data:
.byte 1 .byte 1 .byte Rx_Buffer_Length
Tx_Buffer: Tx_Head: Tx_Tail: Tx_Data:
.byte 1 .byte 1 .byte Tx_Buffer_Length
UARTFlg: ROMTXT: kuldeskor az aktualis ROM pozicio cime
.byte 1
;UART Flags ;ROM TXT
.byte 3
; ************************************************************************* ;* Text Const ;* .CSEG
; ************************************************************************ ;** Init_UART1 ;** Set up the inital states for the buffers, and make sure the handshake ;** is turned on (Not the Shaddap state), so we can talk. ;** ;** ; ************************************************************************ Init_UART1: ldi R16,0 sts Tx_Tail,R16 sts Tx_Head,R16 sts Rx_Tail,R16 sts Rx_Head,R16 sts UARTFlg,R16 sts sts
CMD_Len,R16 CMD_Pos,R16 ;Set up
Hardware HS I/O bits sbi
SER_HSO_DIR,SER_HSO
;Set as
output HS_Enabled cbi
SER_HSI_PORT,SER_HSI
;Set as
cbi
SER_HSI_DIR,SER_HSI
ldi sts ldi sts
R16,High(SYSCLK/(16*BaudSpeed1)-1) UBRR1H,R16 R16,Low(SYSCLK/(16*BaudSpeed1)-1) UBRR1L,R16 ;BaudRate
ldi
R16,0b00000000
sts
UCSR1A,R16
ldi
R16,0b11011000
sts
UCSR1B,R16
ldi
R16,0b00000110
sts ret
UCSR1C,R16
input, Pull-up
Gen. ;RXCn,
TXCn, UDREn, FEn, DORn, UPEn, U2Xn, MPCMn
;RXCIE,
TXCIE,UDRIE,RXEN,TXEN,UCSZn2,RXB8,TXB8
;–, UMSELn,
UPMn1, UPMn0, USBSn, UCSZn1, UCSZn0, UCPOLn
ECopyr:
.DB "(C) 2003 VFX ATmega128 Service
Terminal [2003.02.08.]",CR .DB "Firmware version ",MAJOR_REV,".", MINOR_REV,MINOR_REVB," " .DB "Latest Upd.: 2003.05.01.",CR,0
;*********************************************** ;* Megnezi, hogy kell-e ujrainditani a Tx muveletet TxRunning:
lds lds cp
ZL,Tx_Head ZH,Tx_Tail ZL,ZH
;ha
breq lds andi
TxRun1 ZL,UARTFlg ZL,FlSending
;Tx
brne
TxRun1
;ha igen
rjmp
USART1_TXC ret
azonosak akkor nincs mit tenni
folyamatban? nincs mit tenni TxRun1:
; *************************************************************************** ; *************************************************************************** ; *************************************************************************** ;** UART TX Functions ; *************************************************************************** ; kod Bufferbe Osszesen ; 0x02 - send ROM TXT -> 0xE0, 0x02, low addr, hi addr ; 4 byte ; 0xE0 - send 0xE0 -> 0xE0, 0xE0 ; 2 byte
; ************************************************************************ ;** Calc Tx Buffer Free Space ; In: ; Out: R18 - Tx_Tail ; R19 - Tx_Head ; R20 - Free Space in Tx Buffer ; Alt: R21 ; ; Tail < Head -> Free= LEN+Tail-Head-1 ; Tail = Head -> Free= LEN ; Tail > Head -> Free= Tail-Head-1 ; FreeInTxBuff: lds R19,Tx_Head lds R18,Tx_Tail ldi R20,Tx_Buffer_Length mov R21,R18 sub R21,R19 breq FreeInTx1 Tx_Buffer_Length brcs FreeInTx2 clr R20 FreeInTx2: add R20,R21 dec R20 FreeInTx1: ret
;T=H, Free=
;************************************************ ;* The RS232 Tx FIFO manager ROM TEXT ;* In: (R16, R17) address word of text (L, H)
*
* ;* Out: c=1 hiba * ;************************************************ SendStr: rcall FreeInTxBuff ;R18,R19-t
is beallitja cpi brcs
R20,4 ExitwError
;ha <4
clr ldi
R18 ZL,low(Tx_Data)
;R18=0 ;Z to the
ldi add adc
ZH,high(Tx_Data) ZL,R19 ZH,R18
;add
push ldi
R16 R16,0xE0
;
rcall ldi
StoreChar R16,SendROMTXT
;Buf
rcall pop rcall
StoreChar R16 StoreChar
;Buf
mov
R16,R17
;Store
rcall sts
StoreChar Tx_Head,R19
;Store new
rcall
TxRunning
nincs eleg hely! Hiba!
addr of txbuffer (FIFO)
address offset...
z = @Buf[Tx_head]
Alternative function indicator cli
[Tx_head]=SendROMTXT indicate Send ROM TXT
[Tx_head]=RomTXT low address sei
RomTXT high address
pointer
clc ret
;Nincs hiba
ExitwError: sec
;Return
with error ret
SendStrW:
rcall brcs ret
SendStr SendStrW
;************************************************ ;* The RS232 Tx FIFO manager Send CHAR * ;* in: R16 char * ;* out c=1 hiba * ;************************************************ SendChr: rcall FreeInTxBuff ;R18,R19-t is beallitja cpi brcs
R20,2 ExitwError
;ha <1
clr ldi
R18 ZL,low(Tx_Data)
;R18=0 ;Pointer to
ldi add adc
ZH,high(Tx_Data) ZL,R19 ZH,R18
;add
cpi
R16,0xE0
;
brne
only1char
;ha igen
rcall rcall sts
StoreChar StoreChar Tx_Head,R19
rcall
TxRunning
nincs elg hely! Hiba!
the txbuffer (FIFO)
address offset...
z = @Buf[txhead]
Alternative kod? akkor ketszer kell atkuldeni!! only1char:
clc ret SendChrW:
; Nincs hiba
push push rcall pop pop brcs ret
ZL ZH SendChr ZH ZL SendChrW
;*********************************************** ; Subrutin for SendROMTXT & SendChar StoreChar:
st inc cpi brcs
Z+,R16 R19 R19,Tx_Buffer_Length StoreC1
;Store char
;TxHead
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is http://avr-asm.tripod.com/uart128.html (1 of 2)1/20/2009 8:55:05 PM
16 BIT MATH (AVR 202)
either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/uart128.html (2 of 2)1/20/2009 8:55:05 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
UART RING BUFFER HOME RETRO_DAN ;-------------------------------------------------------; A UART RING BUFFER ;-------------------------------------------------------.equ rxfifo_length = 0x40 ; length or size
ASM FORUM ASM MATH TUTORIAL #1
of RX fifo buffer (64 bytes)
TUTORIAL #2 TUTORIAL #3
.equ
MATH 201
DIV 24 24 DIV 3216
; length or size
; UART ring buffers
MATH 202
DIV16 XX
0x40
; Arrays .DSEG .org 0x00C0
MATH 200b
MATH YX
=
of TX fifo buffer (64 bytes)
MATH 200
MATH 32X
txfifo_length
rxfifo_n: .byte 1 bytes currently stored in buffer (init: 0)
; number of
rxfifo_in: .byte 2 address in buffer written to (init: rxfifo_base)
; pointer to
rxfifo_out: .byte 2 address in buffer read from (init: rxfifo_base)
; pointer to
FLOAT 128 SQRT16 MATH 202 MATH 202 rxfifo_base: .byte rxfifo_length
DEC ASCII INT ASCII HX2ASC
; reserves
fifo_length bytes for the ; buffer and is used as the buffer’s base address
AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
txfifo_n: .byte 1 bytes currently stored in buffer (init: 0)
; number of
txfifo_in: .byte 2 address in buffer written to (init: txfifo_base)
; pointer to
txfifo_out: .byte 2 address in buffer read from (init: txfifo_base)
; pointer to
VFX MEM txfifo_base: .byte txfifo_length
SORT 220 CRC 236
; reserves
fifo_length bytes for the ; buffer and is
XMODEM REC UART 304
used as the buffer’s base address
UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
;--------------; *************************************************************************** ;* ;* "USART_UDRE" interrupt handler ;* Transmits data pending in TX buffer in predefined baud rate & 8n1 ;* (RTS handshake via pin PB0, CTS_in; single- or multibyte transfers) ;* ;* All regs saved ;* ; ***************************************************************************
I2C/TWI 128 I2C/TWI AT8
USART_UDRE: sbic
UCSRA,RXC
; if receiving (RXC
rjmp
U_Tx5
; exit immediately
push in
Flags_tmp Flags_tmp,SREG
; flags may be changed
push
Flags_tmp
;
push push
Tmp1 Tmp2
sbrs rjmp sbic
B_Flags4,2 Get_txfifo PINB,0
; set: use HW handshake ; don't use handshake ; check CTS_in (low =
rjmp
U_Tx3
; pardner not ready, try
"1"),
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128
by arithmetics, so save the
status register
ADC 10B ADC 400 ADC 401
U_Tx1:
THERM 232 IRD 410 LCD HD44
pardner ready for receive)
LCD 2313
later (exit), else
LCD44 2313 KBD 240 MUX 242
Get_txfifo: transmit it lds tst breq sts sts lds lds ld out dec sts brne cbr
Tmp1,txfifo_n Tmp1 ; buffer empty? U_Tx3 save_Y,YL save_Y + 1,YH YL,txfifo_out YH,txfifo_out + 1 Tmp2,Y+ ; ** data_out ** UDR,Tmp2 ; to UART transmit Tmp1 txfifo_n,Tmp1 tx_notclr ; buffer not yet empty! B_Flags3,0x40 ; else: clear TX data
cbi
UCSRB,UDRIE
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
; fetch a byte from TX buffer and
pending flag ; and disable UDRE int
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
tx_notclr: ldi cpi cpc brne ldi ldi
Tmp2,high(txfifo_base + txfifo_length) YL,low(txfifo_base + txfifo_length) YH,Tmp2 end_get_txfifo YL,low(txfifo_base) YH,high(txfifo_base)
end_get_txfifo: sts sts lds lds
txfifo_out,YL txfifo_out + 1,YH YL,save_Y YH,save_Y + 1
exit_get_txfifo: rjmp U_Tx4
; (remove this for multi-
byte transmits) ;rjmp
U_Tx1
; (loop until all bytes
are sent ;
remove this for a one
byte transmit) U_Tx3: cbi
UCSRB,UDRIE
; disable UDRE int to
avoid ADC lock-up if ; HW handshake is active U_Tx4: pop pop pop out
Tmp2 Tmp1 Flags_tmp SREG,Flags_tmp
pop
Flags_tmp
; restore the status
register
U_Tx5: reti ;**** End of USART_UDRE interrupt handler **********************************
; *************************************************************************** ;* ;* "USART_Rx" interrupt handler ;* ;* Stores received bytes to fifo ring buffer ("Add_txfifo") ;* Checks for errors, skips byte if error ;* ;* All regs saved ;* ; *************************************************************************** USART_RXC: push in
Flags_tmp Flags_tmp,SREG
; flags may be changed
push
Flags_tmp
;
push push
Tmp1 Tmp3
in ldi and tst
Tmp1,UCSRA ; get status Tmp3,0b00011100 Tmp1,Tmp3 ; isolate bits 4-2 Tmp1 ; if not zero, we have
breq
U_R_cont
; no error
in
Tmp1,UDR
; fetch defective byte,
;call
Init_rxbuf
; (flush rx fifo buffer,
by arithmetics, so save the
status register
U_R1:
an error
clear its error bits too) ;**call error handler rjmp U_R2
; continue -> test fifo
for another byte U_R_cont: in
Tmp1,UDR
; Add_rxfifo - routine
; get data from UDR ... ; ... and store it to RX
buffer lds
Tmp3,rxfifo_n
; check if
cpi
Tmp3,rxfifo_length - 3
; if buffer
brsh
stop_rx
; (-> HW
buffer full
almost full, push RTS_out high handshake, "stop", used if no rollover) add_rxfifo_HWoff: cpi Tmp3,rxfifo_length
; check if
buffer full breq
full_rxfifo_n
; if so, deal
with that add_rxfifo_cont: sts save_Y,YL
; save Y reg
pair sts lds lds st
save_Y + 1,YH YL,rxfifo_in YH,rxfifo_in + 1 Y+,Tmp1
sbr
B_Flags4,0x02
; set bit 1: rx
inc sts
Tmp3 rxfifo_n,Tmp3
; inc FIFO_n
; setup FIFO_in ; ** store data
from Tmp1 **
data received and pending
; 16-bit cpi with FIFO_base + FIFO_length ldi Tmp3,high(rxfifo_base + rxfifo_length) cpi YL,low(rxfifo_base + rxfifo_length) cpc YH,Tmp3 brne end_add_rxfifo ; if end of buffer ram reached, ldi
YL,low(rxfifo_base)
; rollover: load
ldi
YH,high(rxfifo_base)
; FIFO_base
FIFO_in with
end_add_rxfifo: sts rxfifo_in,YL sts rxfifo_in + 1,YH lds YL,save_Y
; store FIFO_in ; restore Y reg
pair lds
YH,save_Y + 1
exit_add_rxfifo: rjmp U_R2
; return (Exit
Add_rxfifo routine)
full_rxfifo_n:
; buffer is full: either ; overwrite older data in buffer (buffer
rollover) ;sbr
B_Flags4,0x02
;rjmp
add_rxfifo_cont
; clear bit 1,
no more rx data pending
; or, alternative: call error handler and end rjmp
;**call rxfifo_err exit_add_rxfifo
stop_rx:
; alternative if no buffer rollover RTS_high ; HW handshake,
"stop" rjmp
add_rxfifo_HWoff
sbic
UCSRA,RXC
; another byte pending
rjmp
U_R1
; yes, loop
pop pop pop out
Tmp3 Tmp1 Flags_tmp SREG,Flags_tmp
; restore the status
pop reti
Flags_tmp
U_R2: in fifo?
U_R_exit:
register
;**** End of USART_RCX interrupt handler -------------------------------****
; *************************************************************************** ;* ;* UART ring buffer functions ;* ;* ("Add_rxfifo": store a byte from IO_Source (UDR) to buffer, -> ISR) ;* "Get_rxfifo": return 1 byte from rx ring buffer in Tmp2 ;* ;* "Add_txfifo": store a byte to transmit buffer ;* ("Get_txfifo": transmits the bytes stored in transmit buffer -> ISR) ;* ;* "Init_rx/txbuf": initialize/clear fifo ring buffers (RX / TX) ;* ; *************************************************************************** ; ************************************************************************** Get_rxfifo:
; returns a byte from RX buffer in Tmp2 ; (all regs saved, comments cf.
add_rxFIFO) push push lds cpi
Tmp1 Tmp3 Tmp1,rxfifo_n Tmp1,rxfifo_length - 8
; if buffer no
brlo
start_rx
; set RTS_out
longer almost full, low again (ready to receive) get_rxfifo_cont: tst Tmp1 breq exit_get_rxfifo sts save_Y,YL sts save_Y + 1,YH lds YL,rxfifo_out lds YH,rxfifo_out + 1 ld Tmp2,Y+
; ** data_out to
Tmp2 ** dec sts brne cbr
Tmp1 rxfifo_n,Tmp1 rx_notclr B_Flags4,0x02
; rx buffer
empty: clear "data pending" bit rx_notclr: ldi cpi cpc brne ldi ldi
Tmp3,high(rxfifo_base + rxfifo_length) YL,low(rxfifo_base + rxfifo_length) YH,Tmp3 end_get_rxfifo YL,low(rxfifo_base) YH,high(rxfifo_base)
end_get_rxfifo: sts sts lds lds
rxfifo_out,YL rxfifo_out + 1,YH YL,save_Y YH,save_Y + 1
exit_get_rxfifo: pop Tmp3 pop Tmp1 ret
; EXIT function
start_rx:
; switch receive
on again RTS_low rjmp get_rxfifo_cont ; ************************************************************************** ; ************************************************************************** Add_txfifo:
; stores a byte to TX buffer / all regs
saved push push
; entry with data to-be-stored in Tmp2 Tmp1 Tmp3
lds
Tmp3,txfifo_n
; load # of
cpi
Tmp3,txfifo_length
; check if
breq
full_txfifo_n
; if so, deal
add_txfifo_cont: sbr B_Flags3,0x40
; set TX data
chars pending
buffer full with that
pending flag ;sbi
UCSRB,UDRIE
; (enable UDRE
sts
save_Y,YL
; save Y reg
sts lds lds st
save_Y + 1,YH YL,txfifo_in YH,txfifo_in + 1 Y+,Tmp2
inc sts
Tmp3 txfifo_n,Tmp3
int to start transmit!) pair ; setup FIFO_in ; ** store data
from Tmp2 ** ; inc FIFO_n
; 16-bit cpi with FIFO_base + FIFO_length ldi Tmp3,high(txfifo_base + txfifo_length) cpi YL,low(txfifo_base + txfifo_length) cpc YH,Tmp3 brne end_add_txfifo ; if end of buffer ram reached, ldi
YL,low(txfifo_base)
; rollover: load
ldi
YH,high(txfifo_base)
; FIFO_base
FIFO_in with
end_add_txfifo: sts txfifo_in,YL sts txfifo_in + 1,YH lds YL,save_Y
; store FIFO_in ; restore Y reg
pair lds
YH,save_Y + 1
exit_add_txfifo: pop Tmp3 pop Tmp1 ret full_txfifo_n:
; return
; buffer is full: either ; overwrite older data in buffer (buffer
rollover) ;rjmp
add_txfifo_cont ; or, alternative: call error handler
and end rjmp
;call txfifo_err exit_add_txfifo
; ************************************************************************** ; ************************************************************************** ; routines to initialize the RX / TX buffers ; All regs saved Init_rxbuf: push push push
YH YL Tmp1
; init rx buffer clr YL sts rxfifo_n,YL ldi YL,low(rxfifo_base) ldi YH,high(rxfifo_base) sts rxfifo_in,YL sts rxfifo_in + 1,YH sts rxfifo_out,YL sts rxfifo_out + 1,YH cbr
B_Flags4,0x02
; clear "rx data
clr sts
Tmp1 rxfifo_n,Tmp1
; reset FIFO_n
pop pop pop ret
Tmp1 YL YH
pending" bit
Init_txbuf: push push push
YH YL Tmp1
; init tx buffer clr YL sts txfifo_n,YL ldi YL,low(txfifo_base) ldi YH,high(txfifo_base) sts txfifo_in,YL sts txfifo_in + 1,YH sts txfifo_out,YL sts txfifo_out + 1,YH cbr
B_Flags3,0x40
; clear "tx data
clr sts
Tmp1 txfifo_n,Tmp1
; reset FIFO_n
pop pop pop ret
Tmp1 YL YH
pending" bit
;**** End of UART buffer functions -----
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler http://avr-asm.tripod.com/uartbuff.html (1 of 2)1/20/2009 8:55:41 PM
16 BIT MATH (AVR 202)
programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible TwoWire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/uartbuff.html (2 of 2)1/20/2009 8:55:41 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
UNIVERSAL SERIAL BUS TO RS232 HOME RETRO_DAN ;*************************************************************************** ;* U S B S T A C K F O R T H E A V R F A M I L Y ;* ;* File Name :"USBtoRS232.asm" ;* Title :USB stack: USB to RS232 converter + USB to 8-bit I/O pins
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2
converter + USB to EEPROM recorder ;* Date :15.09.2003 ;* Version :2.4 ;* Target MCU :ATmega8 ;* AUTHOR :Ing. Igor Cesko ;* Slovakia ;* [email protected] ;* http://www.cesko.host.sk ;* ;* DESCRIPTION: ;* USB protocol implementation into MCU with noUSB interface: ;* Device: ;* Universal USB interface (3x8-bit I/O port + RS232 serial line + EEPROM) ;* + added RS232 FIFO buffer ;* ;* The timing is adapted for 12 MHz crystal ;* ;* Copyright (c) Ing. Igor Cesko 2002-2003 ;* All rights reserved ;* ;* to add your own functions - see section: TEMPLATE OF YOUR FUNCTION ;* ;*************************************************************************** .include "m8def.inc" ;comment for AT90S2313 .equ UCR =UCSRB .equ UBRR =UBRRL .equ EEAR =EEARL .equ USR =UCSRA .equ E2END =127 .equ RAMEND128 =96+127
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
.equ .equ .equ .equ
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
inputport outputport USBdirection DATAplus
=PINB =PORTB =DDRB =1
;signal D+ na PB1
;ENG;signal D+
on PB1 .equ DATAminus =0 ;signal D- na PB0 - treba dat na tento pin pull-up 1.5kOhm ;ENG;signal D- on PB0 - give on this pin pull-up 1.5kOhm .equ USBpinmask =0b11111100 ;mask low 2 bits (D+,D-) on PB ;ENG; mask low 2 bit (D+,D-) on PB .equ USBpinmaskDplus =~(1<
UART 305 .equ .equ .equ ;ENG;signal OUT from IR sensor TSOP1738
UART 128 UART BUFF USB 232
PB2
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44
KBD 240
KBD PC/128 PS2 EMU
ALM CLK
DELAYS CALL ID
STH-11
=PIND
;pripojenie LED diod LSB
LEDdirectionLSB
=DDRD
;vstup/vystup LED LSB
LEDPortMSB
=PORTB
;pripojenie LED diod MSB
LEDPinMSB
=PINB
;pripojenie LED diod MSB
LEDdirectionMSB
=DDRB
;vstup/vystup LED MSB
;ENG;input/
LEDlsb0
=3
;LED0 na pin PD3
;ENG;LED0 on
LEDlsb1
=5
;LED1 na pin PD5
;ENG;LED1 on
LEDlsb2
=6
;LED2 na pin PD6
;ENG;LED2 on
LEDmsb3
=3
;LED3 na pin PB3
;ENG;LED3 on
LEDmsb4
=4
;LED4 na pin PB4
;ENG;LED4 on
LEDmsb5
=5
;LED5 na pin PB5
;ENG;LED5 on
LEDmsb6
=6
;LED6 na pin PB6
;ENG;LED6 on
LEDmsb7
=7
;LED7 na pin PB7
;ENG;LED7 on
.equ
SOPbyte
=0b10000000
;Start of Packet byte
;ENG;Start of
.equ
DATA0PID
=0b11000011
;PID pre DATA0 pole
;ENG;PID for
.equ
DATA1PID
=0b01001011
;PID pre DATA1 pole
;ENG;PID for
.equ
OUTPID
=0b11100001
;PID pre OUT pole
;ENG;PID for
.equ
INPID
=0b01101001
;PID pre IN pole
;ENG;PID for
.equ
SOFPID
=0b10100101
;PID pre SOF pole
;ENG;PID for
.equ
SETUPPID
=0b00101101
;PID pre SETUP pole
;ENG;PID for
.equ
ACKPID
=0b11010010
;PID pre ACK pole
;ENG;PID for
.equ
NAKPID
=0b01011010
;PID pre NAK pole
;ENG;PID for
.equ
STALLPID
=0b00011110
;PID pre STALL pole
;ENG;PID for
.equ
PREPID
=0b00111100
;PID pre PRE pole
;ENG;PID for
=0b00000001
;Start of Packet byte - opacne
=0b11000011
;PID pre DATA0 pole - opacne
=0b11010010
;PID pre DATA1 pole - opacne
=0b10000111
;PID pre OUT pole - opacne
=0b10010110
;PID pre IN pole - opacne
=0b10100101
;PID pre SOF pole - opacne
=0b10110100
;PID pre SETUP pole - opacne
=0b01001011
;PID pre ACK pole - opacne
=0b01011010
;PID pre NAK pole - opacne
=0b01111000
;PID pre STALL pole - opacne
=0b00111100
;PID pre PRE pole - opacne
;ENG;input/ ;ENG;
OUT field IN field SOF field SETUP field ACK field NAK field STALL field FOR field
poradie
.equ nSOPbyte ;ENG;Start of Packet byte - reverse order .equ nDATA0PID ;ENG;PID for DATA0 field - reverse order .equ nDATA1PID ;ENG;PID for DATA1 field - reverse order .equ nOUTPID ;ENG;PID for OUT field - reverse order .equ nINPID ;ENG;PID for IN field - reverse order .equ nSOFPID ;ENG;PID for SOF field - reverse order .equ nSETUPPID ;ENG;PID for SETUP field - reverse order .equ nACKPID ;ENG;PID for ACK field - reverse order .equ nNAKPID ;ENG;PID for NAK field - reverse order .equ nSTALLPID ;ENG;PID for STALL field - reverse order .equ nPREPID ;ENG;PID for FOR field - reverse order
poradie
ATMEL CORP AVR BUTTERFLY
LEDPinLSB
;ENG;
DATA1 field
PWM 10K ENCODE
;pripojenie LED diod LSB
DATA0 field
DTMF 314 PWM 6CH
=PORTD
Packet byte
CLOCK 8564 90 DAYS
LEDPortLSB
;.equ (vstup) ;ENG;connecting LED diode LSB (input) ;.equ output LED LSB ;.equ connecting LED diode MSB ;.equ (vstup) ;ENG;connecting LED diode MSB (input) ;.equ output LED MSB ;.equ pin PD3 ;.equ pin PD5 ;.equ pin PD6 ;.equ pin PB3 ;.equ pin PB4 ;.equ pin PB5 ;.equ pin PB6 ;.equ pin PB7
BOOT MG8 BOOT DR8
;signal OUT z IR senzora TSOP1738 na
connecting LED diode LSB
MUX 242 KBD PS2
=PINB =PORTB =2
;.equ
LCD 2313 LCD44 2313
TSOPPort TSOPpullupPort TSOPPin on PB2
poradie poradie
AVR BOOK poradie poradie poradie poradie poradie poradie poradie
.equ nNRZITokenPID =~0b10000000 SETUP) - opacne poradie NRZI ;ENG;PID mask for Token packet (IN,OUT,SOF,SETUP) - reverse order NRZI .equ nNRZISOPbyte =~0b10101011 NRZI ;ENG;Start of Packet byte - reverse order NRZI .equ nNRZIDATA0PID =~0b11010111 NRZI ;ENG;PID for DATA0 field - reverse order NRZI .equ nNRZIDATA1PID =~0b11001001 NRZI ;ENG;PID for DATA1 field - reverse order NRZI .equ nNRZIOUTPID =~0b10101111 NRZI ;ENG;PID for OUT field - reverse order NRZI .equ nNRZIINPID =~0b10110001 NRZI ;ENG;PID for IN field - reverse order NRZI .equ nNRZISOFPID =~0b10010011 NRZI ;ENG;PID for SOF field - reverse order NRZI .equ nNRZISETUPPID =~0b10001101 NRZI ;ENG;PID for SETUP field - reverse order NRZI .equ nNRZIACKPID =~0b00100111 NRZI ;ENG;PID for ACK field - reverse order NRZI .equ nNRZINAKPID =~0b00111001 NRZI ;ENG;PID for NAK field - reverse order NRZI .equ nNRZISTALLPID =~0b00000111 NRZI ;ENG;PID for STALL field - reverse order NRZI .equ nNRZIPREPID =~0b01111101 NRZI ;ENG;PID for FOR field - reverse order NRZI .equ nNRZIADDR0 =~0b01010101 NRZI ;ENG;Address = 0 - reverse order NRZI
;PID maska pre Token paket (IN,OUT,SOF,
;Start of Packet byte - opacne poradie ;PID pre DATA0 pole - opacne poradie ;PID pre DATA1 pole - opacne poradie ;PID pre OUT pole - opacne poradie ;PID pre IN pole - opacne poradie ;PID pre SOF pole - opacne poradie ;PID pre SETUP pole - opacne poradie ;PID pre ACK pole - opacne poradie ;PID pre NAK pole - opacne poradie ;PID pre STALL pole - opacne poradie ;PID pre PRE pole - opacne poradie ;Adresa = 0 - opacne poradie
;stavove byty - State
;ENG;status bytes -
State .equ .equ .equ .equ .equ .equ
BaseState SetupState InState OutState SOFState DataState
=0 =1 =2 =3 =4 =5
; ; ; ; ; ; ;Flagy pozadovanej akcie
;ENG;Flags of
action .equ .equ .equ .equ .equ
DoNone DoReceiveOutData DoReceiveSetupData DoPrepareOutContinuousBuffer DoReadySendAnswer
.equ
CRC5poly
=0 =1 =2 =3 =4
=0b00101
;CRC5 polynom
;ENG;CRC5
=0b01100
;CRC5 zvysok po uspesnom
=0b1000000000000101
;CRC16 polynom
=0b1000000000001101
;CRC16 zvysok po uspesnom
polynomial .equ CRC5zvysok CRC5 ;ENG;CRC5 remainder after successful CRC5 .equ CRC16poly polynomial .equ CRC16zvysok CRC16 ;ENG;CRC16 remainder after successful CRC16
;ENG;CRC16
.equ MAXUSBBYTES =14 ;maximum bytes in USB input message ;ENG;maximum bytes in USB input message .equ NumberOfFirstBits =10 ;kolko prvych bitov moze byt dlhsich ;ENG;how many first bits allowed be longer .equ NoFirstBitsTimerOffset =256-12800*12/1024 ;Timeout 12.8ms (12800us) na ukoncenie prijmu po uvodnych bitoch (12Mhz:clock, 1024:timer predivider, 256:timer overflow value) ;ENG;Timeout 12.8ms (12800us) to terminate after firsts bits .equ InitBaudRate =12000000/16/57600-1 ;nastavit vysielaciu rychlost UART-u na 57600 (pre 12MHz=12000000Hz) ;ENG;UART on 57600 (for 12MHz=12000000Hz) .equ InputBufferBegin ;ENG;compare of receiving shift buffer .equ InputShiftBufferBegin ;ENG;compare of receiving buffera
=RAMEND128-127
;zaciatok
=InputBufferBegin+MAXUSBBYTES
;zaciatok
prijimacieho shift buffera prijimacieho buffera
.equ OutputBufferBegin buffera ;ENG;compare of transmitting buffer .equ AckBufferBegin Ack ;ENG;compare of transmitting buffer Ack .equ NakBufferBegin Nak ;ENG;compare of transmitting buffer Nak .equ ConfigByte ENG;0=unconfigured state .equ AnswerArray byte answer array .equ StackBegin velky cca 68 bytov) ;ENG;low reservoir (stack is big cca 68 byte)
=RAMEND128-MAXUSBBYTES-2 =OutputBufferBegin-3
;zaciatok vysielacieho buffera
=AckBufferBegin-3
;zaciatok vysielacieho buffera
=NakBufferBegin-1
;0=unconfigured state
;
=ConfigByte-8
;8 byte answer array
;ENG;8
=AnswerArray-1
;spodok zasobnika (stack je
=RAMEND-RAMEND128-10
;maximalna dlzka RS232
=RAMEND128+1
;zaciatok buffera pre RS232
.equ MAXRS232LENGTH ;ENG;maximum length RS232 code .equ RS232BufferBegin ;ENG;compare of buffer for RS232 - receiving .equ RS232BufferEnd .equ RS232ReadPosPtr .equ RS232WritePosPtr .equ RS232LengthPosPtr .equ RS232Reserved .equ RS232FIFOBegin
kodu prijem
.def
;zaciatok vysielacieho
RS232BufferFull
=RS232BufferBegin+MAXRS232LENGTH =RS232BufferBegin+0 =RS232BufferBegin+2 =RS232BufferBegin+4 =RS232BufferBegin+6 =RS232BufferBegin+8
=R1
;priznak plneho RS232 buffera
;ENG;
=R2
;zaloha bitcount registra v INT0
=R3
;ci sa ma citat zo SRAM-ky
=R4
;zaloha Flag registra v Timer
=R5
;zaloha Flag registra v INT0
=R6 =R7
;accumulator ;ENG;accumulator ;pozicia bitstuffingu ;ENG;position
=R8
;kolko bitov sa ma este odvysielat z
=R9
;ci sa ma vkladat alebo mazat
=R10
;kolko sa ma poslat bytov
=R11
;poradove cislo vysielacej
=R12
;dlzka pripravena vo vstupnom USB
=R13
;dlzka odpovede pripravena v USB
=R14
;moja USB adresa na update
=R15
;moja USB adresa
=R16
;co sa ma urobit v hlavnej slucke
=R17
;temporary register
;ENG;temporary
flag of full RS232 buffer .def backupbitcount ;ENG;backup bitcount register in INT0 disconnected .def RAMread if reading from SRAM .def backupSREGTimer interrupte ;ENG;backup Flag register in Timer interrupt .def backupSREG preruseni ;ENG;backup Flag register in INT0 interrupt .def ACC .def lastBitstufNumber in bitstuffing .def OutBitStuffNumber posledneho bytu - bitstuffing ;ENG;how many bits to send last byte - bitstuffing .def BitStuffInOut bitstuffing ;ENG;if insertion or deleting of bitstuffing .def TotalBytesToSend how many bytes to send .def TransmitPart casti ;ENG;order number of transmitting part .def InputBufferLength bufferi ;ENG;length prepared in input USB buffer .def OutputBufferLength bufferi ;ENG;length answers prepared in USB buffer .def MyUpdatedAddress my USB address for update .def MyAddress address preruseni
.def ActionFlag ;ENG;what to do in main program loop .def temp3
programu
;ENG;
;ENG;
;ENG;
;ENG;my USB
register .def
temp2
=R18
;temporary register
;ENG;temporary
.def
temp1
=R19
;temporary register
;ENG;temporary
.def
temp0
=R20
;temporary register
;ENG;temporary
.def
bitcount
=R21
;counter of bits in byte
=R22
;pocitadlo maximalneho poctu prijatych
=R23
;prijimaci register
=R24
;posuvny prijimaci register
;ENG;
;byte stavu stavoveho stroja
;ENG;
register register register ;ENG;
counter of bits in byte bajtov
.def ByteCount ;ENG;counter of maximum number of received bytes .def inputbuf
;ENG;receiver
register .def
shiftbuf
shift receiving register .def State =R25 state byte of status of state machine .def RS232BufptrX =R26 prijatych IR kodov ;ENG;XL register - pointer to buffer of received IR codes .def RS232BufptrXH =R27 .def USBBufptrY =R28 input/output ;ENG;YL register - pointer to USB buffer input/output .def ROMBufptrZ =R30 dat ;ENG;ZL register - pointer to buffer of ROM data
;poziadavky .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
;XL register - pointer do buffera
;YL register - pointer do USB buffera ;ZL register - pointer do buffera ROM
na deskriptory ;ENG;requirements on descriptors GET_STATUS =0 CLEAR_FEATURE =1 SET_FEATURE =3 SET_ADDRESS =5 GET_DESCRIPTOR =6 SET_DESCRIPTOR =7 GET_CONFIGURATION =8 SET_CONFIGURATION =9 GET_INTERFACE =10 SET_INTERFACE =11 SYNCH_FRAME =12
;typy deskriptorov ;ENG;descriptor .equ DEVICE .equ CONFIGURATION .equ STRING .equ INTERFACE .equ ENDPOINT
types =1 =2 =3 =4 =5
;databits .equ .equ .equ .equ
;ENG;databits DataBits5 DataBits6 DataBits7 DataBits8
=0 =1 =2 =3
;parity .equ .equ .equ .equ .equ
;ENG;parity ParityNone ParityOdd ParityEven ParityMark ParitySpace
=0 =1 =2 =3 =4
;stopbits .equ .equ
;ENG;stopbits StopBit1 StopBit2
=0 =1
;user function start number .equ USER_FNC_NUMBER
=100
;-----------------------------------------------------------------------------------------;******************************************************************** ;* Interrupt table ;ENG;* Interrupt table ;******************************************************************** .cseg ;-----------------------------------------------------------------------------------------.org 0 ;po resete ;ENG;after reset rjmp reset ;-----------------------------------------------------------------------------------------.org INT0addr ;externe prerusenie INT0 ;ENG; external interrupt INT0 rjmp INT0handler ;-----------------------------------------------------------------------------------------.org URXCaddr ;prijem zo seriovej linky ;ENG; receiving from serial line push temp0 cbi UCR,RXCIE ;zakazat interrupt od prijimania UART ;ENG;disable interrupt from UART receiving sei ;povol interrupty na obsluhu USB ;ENG;enable interrupts to service USB in temp0,UDR ;nacitaj do temp0 prijate data z UARTu ;ENG;put to temp0 received data from UART in backupSREGTimer,SREG ;zaloha SREG ;ENG;backup SREG push temp2 push temp3 lds temp2,RS232LengthPosPtr lds temp3,RS232LengthPosPtr+1 ;zisti dlzku buffera RS232 kodu ;ENG;determine length of RS232 code buffer cpi temp3,HIGH(RS232BufferEnd-RS232FIFOBegin-1) ;ci by mal pretiect buffer ;ENG;if the buffer would overflow brlo FIFOBufferNoOverflow ;ak nepretecie, tak zapis do FIFO ;ENG;if not overflow then write to FIFO brne NoIncRS232BufferFull ;ak by mal pretiect, tak zabran prepisaniu ;ENG;if buffer would overflow, then prevent of overwriting ;inak (pri rovnosti) este porovnaj Lo byty ;ENG;otherwise (if equall) still compare Lo bytes cpi temp2,LOW(RS232BufferEnd-RS232FIFOBegin-1) ;ak by mal pretiect buffer (Lo byte) ;ENG;if buffer would overflow (Lo byte) brcc NoIncRS232BufferFull ;tak zabran prepisaniu ;ENG; then prevent of overwriting FIFOBufferNoOverflow: push RS232BufptrX push RS232BufptrXH lds RS232BufptrX,RS232WritePosPtr ;nastavenie sa na zaciatok buffera zapisu RS232 kodu ;ENG;set position to begin of buffer write RS232 code lds RS232BufptrXH,RS232WritePosPtr+1 ;nastavenie sa na zaciatok buffera zapisu RS232 kodu ;ENG;set position to begin of buffer write RS232 code st
X+,temp0
;a uloz ho do buffera
;ENG;
and save it to buffer RS232 buffera
cpi RS232BufptrXH,HIGH(RS232BufferEnd+1) ;ENG;if not reached maximum of RS232 buffer brlo NoUARTBufferOverflow
;ak sa nedosiahol maximum ;tak pokracuj
;ENG;then
continue brne
UARTBufferOverflow
;skontroluj aj LSB
;ENG;
check althen LSB RS232 buffera
cpi RS232BufptrX,LOW(RS232BufferEnd+1) ;ENG;if not reached maximum of RS232 buffer brlo NoUARTBufferOverflow
;ak sa nedosiahol maximum ;tak pokracuj
;ENG;then
continue UARTBufferOverflow: ldi RS232BufptrX,LOW(RS232FIFOBegin) ;inak sa nastav na zaciatok buffera ;ENG;otherwise set position to buffer begin ldi RS232BufptrXH,HIGH(RS232FIFOBegin) ;inak sa nastav na zaciatok buffera ;ENG;otherwise set position to buffer begin NoUARTBufferOverflow: sts RS232WritePosPtr,RS232BufptrX ;ulozenie noveho offsetu buffera zapisu RS232 kodu ;ENG;save new offset of buffer write RS232 code sts RS232WritePosPtr+1,RS232BufptrXH ;ulozenie noveho offsetu buffera zapisu RS232 kodu ;ENG;save new offset of buffer write RS232 code ldi temp0,1 ;zvys dlzku RS232 buffera ;ENG;increment length of RS232 buffer add temp2,temp0 ldi temp0,0 adc temp3,temp0 sts RS232LengthPosPtr,temp2 ;uloz dlzku buffera RS232 kodu ;ENG;save length of buffer RS232 code sts RS232LengthPosPtr+1,temp3 ;uloz dlzku buffera RS232 kodu ;ENG;save length of buffer RS232 code pop RS232BufptrXH pop RS232BufptrX NoIncRS232BufferFull: pop temp3 pop temp2 pop temp0 out SREG,backupSREGTimer ;obnova SREG ;ENG;restore SREG cli ;zakazat interrupt kvoli zacykleniu ;ENG;disable interrupt because to prevent reentrant interrupt call sbi UCR,RXCIE ;povolit interrupt od prijimania UART ;ENG;enable interrupt from receiving of UART reti ;-----------------------------------------------------------------------------------------;******************************************************************** ;* Init program ;ENG;* Init program ;******************************************************************** ;-----------------------------------------------------------------------------------------reset: ;inicializacia procesora a premennych na spravne hodnoty ;ENG;initialization of processor and variables to right values ldi temp0,StackBegin ;inicializacia stacku ;ENG;initialization of stack out SPL,temp0 clr clr clr ldi
XH YH ZH temp0,LOW(RS232FIFOBegin)
;RS232 pointer ;ENG;RS232 pointer ;USB pointer ;ENG;USB pointer ;ROM pointer ;ENG;ROM pointer ;nastav na zaciatok buffera Low ;ENG;
sts
RS232ReadPosPtr,temp0
;znuluj ukazovatel citania
;ENG;
sts
RS232WritePosPtr,temp0
;znuluj ukazovatel zapisu
;ENG;
ldi
temp0,HIGH(RS232FIFOBegin)
;nastav na zaciatok buffera
sts
RS232ReadPosPtr+1,temp0
;znuluj ukazovatel citania
;ENG;
sts
RS232WritePosPtr+1,temp0
;znuluj ukazovatel zapisu
;ENG;
sts
RS232LengthPosPtr,YH
;znuluj ukazovatel dlzky
;ENG;
sts
RS232LengthPosPtr+1,YH
;znuluj ukazovatel dlzky
;ENG;
clr
RS232BufferFull
clr
MyUpdatedAddress
;nova adresa USB -
rcall
InitACKBufffer
;inicializacia ACK buffera
;ENG;
rcall
InitNAKBufffer
;inicializacia NAK buffera
;ENG;
rcall
USBReset
;inicializacia USB adresy
;ENG;
ldi
temp0,0b00111100
;nahodit pull-up na PORTB
;ENG;set pull-
out ldi
PORTB,temp0 temp0,0b11111111
;nahodit pull-up na PORTC
;ENG;set pull-
out ldi
PORTC,temp0 temp0,0b11111011
;nahodit pull-up na PORTD
;ENG;set pull-
out
PORTD,temp0
clr out
temp0 UBRRH,temp0
; ;nastavit vysielaciu rychlost UART-u
out
EEARH,temp0
;znulovat EEPROM ukazovatel
;ENG;zero
ldi
temp0,1<
;nastavit mod X2 na UART-e
;ENG;set mode
out ldi
USR,temp0 temp0,InitBaudRate
;nastavit vysielaciu rychlost UART-u
out sbi
UBRR,temp0 UCR,TXEN
;povolit vysielanie UART-u
;ENG;enable
sbi
UCR,RXEN
;povolit prijimanie UART-u
;ENG;enable
sbi
UCR,RXCIE
;povolit interrupt od prijimania UART
;ENG;
ldi
temp0,0x0F
;INT0 - reagovanie na nabeznu hranu
;ENG;
out ldi
MCUCR,temp0 temp0,1<
; ;povolit externy interrupt INT0 ;ENG;enable
set Low to begin of buffer zero index of reading zero index of writing High
;ENG;set High to begin of buffer
zero index of reading zero index of writing zero index of length zero index of length
new address USB -
nedekodovana
;ENG;
non-decoded
initialization of ACK buffer initialization of NAK buffer
initialization of USB addresses
up on PORTB
up on PORTC
up on PORTD
High
;ENG;set UART speed High
EEPROM index
X2 on UART ;ENG;
set UART speed
transmiting of UART receiving of UART enable interrupt from receiving of UART
INT0 - respond to leading edge
external interrupt INT0 out GIMSK,temp0 ;------------------------------------------------------------------------------------------
;******************************************************************** ;* Main program ;ENG;* Main program ;******************************************************************** sei ;povolit interrupty globalne
;ENG;
enable interrupts globally Main: sbis
inputport,DATAminus
;cakanie az sa zmeni D- na 0
;ENG;waiting
rjmp
CheckUSBReset
;a skontroluj, ci to nie je USB reset
cpi breq cpi breq rjmp
ActionFlag,DoReceiveSetupData ProcReceiveSetupData ActionFlag,DoPrepareOutContinuousBuffer ProcPrepareOutContinuousBuffer Main
till change D- to 0 ;ENG;
and check, if isn't USB reset
cca 10ms - tu je to cca 100us)
CheckUSBReset: ldi temp0,255 ;pocitadlo trvania reset-u (podla normy je to ;ENG;counter duration of reset (according to specification is that cca 10ms - here is cca 100us) WaitForUSBReset: sbic inputport,DATAminus ;cakanie az sa zmeni D+ na 0 ;ENG;waiting
till change D+ to 0 rjmp dec brne rcall rjmp
Main temp0 WaitForUSBReset USBReset Main
ProcPrepareOutContinuousBuffer: rcall PrepareOutContinuousBuffer ;priprav pokracovanie odpovede do buffera ;ENG;prepare next sequence of answer to buffer ldi ActionFlag,DoReadySendAnswer rjmp Main ProcReceiveSetupData: ldi USBBufptrY,InputBufferBegin ;pointer na zaciatok prijimacieho buffera ;ENG;pointer to begin of receiving buffer mov ByteCount,InputBufferLength ;dlzka vstupneho buffera ;ENG; length of input buffer rcall DecodeNRZI ;prevod kodovania NRZI na bity ;ENG;transfer NRZI coding to bits rcall MirrorInBufferBytes ;prehodit poradie bitov v bajtoch ;ENG; invert bits order in bytes rcall BitStuff ;odstranenie bit stuffing ;ENG;removal of bitstuffing ;rcall CheckCRCIn ;kontrola CRC ;ENG;rcall CheckCRCIn ;check CRC rcall PrepareUSBOutAnswer ;pripravenie odpovede do vysielacieho buffera ;ENG;prepare answers to transmitting buffer ldi ActionFlag,DoReadySendAnswer rjmp Main ;******************************************************************** ;* Main program END ;ENG;* Main program END ;******************************************************************** ;-----------------------------------------------------------------------------------------;******************************************************************** ;* Interrupt0 interrupt handler ;ENG;* Interrupt0 interrupt handler ;******************************************************************** INT0Handler: ;prerusenie INT0 ;ENG;interrupt INT0 in backupSREG,SREG push temp0 push temp1 ldi
temp0,3
;pocitadlo trvania log0 ;ENG;counter of
ldi
temp1,2
;pocitadlo trvania log1 ;ENG;counter of
duration log0 duration log1 ;cakanie na zaciatok paketu CheckchangeMinus: sbis inputport,DATAminus
;ENG;waiting for begin packet ;cakanie az sa zmeni D- na 1
;ENG;waiting
;cakanie az sa zmeni D+ na 1
;ENG;waiting
till change D- to 1 rjmp CheckchangePlus: sbis
CheckchangeMinus
rjmp DetectSOPEnd: sbis rjmp Increment1: ldi
CheckchangePlus
inputport,DATAplus
till change D+ to 1
inputport,DATAplus Increment0
;D+ =0
temp0,3
;pocitadlo trvania log0 ;ENG;counter of
dec
temp1
;kolko cyklov trvala log1
nop breq
USBBeginPacket
;ak je to koniec SOP - prijimaj paket
rjmp
DetectSOPEnd
ldi
temp1,2
;pocitadlo trvania log1 ;ENG;counter of
dec
temp0
;kolko cyklov trvala log0
;ENG;how many
nop brne
DetectSOPEnd
;ak nenastal SOF - pokracuj
;ENG;if there
;ENG;D+ =0
duration log0 ;ENG;how many
cycles takes log1 ;ENG;
if this is end of SOP - receive packet Increment0: duration log1 cycles take log0
isn't SOF - continue rjmp EndInt0Handler: pop pop pop pop EndInt0HandlerPOP: pop pop mov
EndInt0HandlerPOP2 ACC RS232BufptrX temp3 temp2 USBBufptrY ByteCount bitcount,backupbitcount ;obnova bitcount registra
;ENG;restore
bitcount register EndInt0HandlerPOP2: pop pop out ldi
temp1 temp0 SREG,backupSREG shiftbuf,1<
;znulovat flag interruptu INTF0 ;ENG;zero
interruptu flag INTF0
milisekundu)
out GIFR,shiftbuf reti ;ENG;otherwise finish (was only SOF - every millisecond) USBBeginPacket: mov
;inak skonci (bol iba SOF - kazdu
backupbitcount,bitcount ;zaloha bitcount registra
;ENG;backup
bitcount register in shiftbuf,inputport ;ak ano nacitaj ho ako nulty bit priamo do shift registra ;ENG;if yes load it as zero bit directly to shift register USBloopBegin: push ByteCount ;dalsia zaloha registrov (setrenie casu) ;ENG;additional backup of registers (save of time) push USBBufptrY ldi bitcount,6 ;inicializacia pocitadla bitov v bajte ;ENG; initialization of bits counter in byte ldi ByteCount,MAXUSBBYTES ;inicializacia max poctu prijatych bajtov v pakete ;ENG;initialization of max number of received bytes in packet ldi USBBufptrY,InputShiftBufferBegin ;nastav vstupny buffera ;ENG; set the input buffer USBloop1_6: in inputbuf,inputport cbr inputbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask low 2 bits breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG; if they are zeros - end of USB packet ror inputbuf ;presun Data+ do shift registra ;ENG;transfer Data+ to shift register rol shiftbuf dec bitcount ;zmensi pocitadlo bitov ;ENG;decrement bits counter brne USBloop1_6 ;ak nie je nulove - opakuj naplnanie shift registra ;ENG;if it isn't zero - repeat filling of shift register nop ;inak bude nutne skopirovat shift register bo buffera ;ENG;otherwise is necessary copy shift register to buffer USBloop7: in inputbuf,inputport cbr inputbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask low 2 bits breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG; if they are zeros - end of USB packet ror inputbuf ;presun Data+ do shift registra ;ENG;transfer Data+ to shift register rol shiftbuf ldi bitcount,7 ;inicializacia pocitadla bitov v bajte ;ENG; initialization of bits counter in byte st Y+,shiftbuf ;skopiruj shift register bo buffera a zvys pointer do buffera ;ENG;copy shift register into buffer and increment pointer to buffer USBloop0: ;a zacni prijimat dalsi bajt ;ENG;and start receiving next byte in shiftbuf,inputport ;nulty bit priamo do shift registra ;ENG; zero bit directly to shift register cbr shiftbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask low 2 bits breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG; if they are zeros - end of USB packet dec bitcount ;zmensi pocitadlo bitov ;ENG;decrement bits counter nop ; dec ByteCount ;ak sa nedosiahol maximum buffera ;ENG; if not reached maximum buffer brne USBloop1_6 ;tak prijimaj dalej ;ENG;then receive next rjmp
EndInt0HandlerPOP
;inak opakuj od zaciatku
;ENG;otherwise
cpi
USBBufptrY,InputShiftBufferBegin+3
brcs lds
EndInt0HandlerPOP ;tak skonci ;ENG;then finish temp0,InputShiftBufferBegin+0 ;identifikator paketu do temp0
lds
temp1,InputShiftBufferBegin+1
repeat back from begin USBloopEnd: byte
;ak sa neprijali aspon 3
;ENG;if at least 3 byte not received ;ENG;
identifier of packet to temp0 ;adresa do temp1
;ENG;address
to temp1 brne TestDataPacket ;ak je dlzka ina ako 3 - tak to moze byt iba DataPaket ;ENG;if is length different from 3 - then this can be only DataPaket TestIOPacket: cp temp1,MyAddress ;ak to nie je urcene (adresa) pre mna ;ENG; if this isn't assigned (address) for me brne TestDataPacket ;tak to moze byt este Data Packet ;ENG; then this can be still DataPacket TestSetupPacket:;test na SETUP paket ;ENG;test to SETUP packet cpi temp0,nNRZISETUPPID brne TestOutPacket ;ak nie je Setup PID - dekoduj iny paket ;ENG;if this isn't Setup PID - decode other packet ldi State,SetupState rjmp EndInt0HandlerPOP ;ak je Setup PID - prijimaj nasledny Data paket ;ENG;if this is Setup PID - receive consecutive Data packet TestOutPacket: ;test na OUT paket ;ENG;test for OUT packet cpi temp0,nNRZIOUTPID brne TestInPacket ;ak nie je Out PID - dekoduj iny paket ;ENG; if this isn't Out PID - decode other packet ldi State,OutState rjmp EndInt0HandlerPOP ;ak je Out PID - prijimaj nasledny Data paket ;ENG;if this is Out PID - receive consecutive Data packet TestInPacket: ;test na IN paket ;ENG;test on IN packet cpi temp0,nNRZIINPID brne TestDataPacket ;ak nie je In PID - dekoduj iny paket ;ENG; if this isn't In PID - decode other packet rjmp AnswerToInRequest TestDataPacket: ;test na DATA0 a DATA1 paket ;ENG;test for DATA0 and DATA1 packet cpi temp0,nNRZIDATA0PID breq Data0Packet ;ak nie je Data0 PID - dekoduj iny paket ;ENG;if this isn't Data0 PID - decode other packet cpi temp0,nNRZIDATA1PID brne NoMyPacked ;ak nie je Data1 PID - dekoduj iny paket ;ENG;if this isn't Data1 PID - decode other packet Data0Packet: cpi State,SetupState ;ak bol stav Setup ;ENG;if was state Setup breq ReceiveSetupData ;prijmi ho ;ENG;receive it cpi State,OutState ;ak bol stav Out ;ENG;if was state Out breq ReceiveOutData ;prijmi ho ;ENG;receive it NoMyPacked: ldi State,BaseState ;znuluj stav ;ENG;zero state rjmp EndInt0HandlerPOP ;a prijimaj nasledny Data paket ;ENG;and receive consecutive Data packet AnswerToInRequest: push
temp2
;zazalohuj dalsie registre a pokracuj
;ENG;
backup next registers and continue push push push cpi
temp3 RS232BufptrX ACC ActionFlag,DoReadySendAnswer
brne rcall
NoReadySend SendPreparedUSBAnswer
;ak nie je pripravena odpoved
;ENG;
if isn't prepared answer ;tak posli NAK ;ENG;then send NAK ;poslanie odpovede naspat ;ENG;
transmitting answer back and MyUpdatedAddress,MyUpdatedAddress ;ak je MyUpdatedAddress nenulova ;ENG;if is MyUpdatedAddress nonzero brne SetMyNewUSBAddress ;tak treba zmenit USB adresu ;ENG;then is necessary to change USB address ldi State,InState ldi ActionFlag,DoPrepareOutContinuousBuffer rjmp EndInt0Handler ;a opakuj - cakaj na dalsiu odozvu z USB ;ENG;and repeat - wait for next response from USB ReceiveSetupData: push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG; backup next registers and continue push temp3 push RS232BufptrX push ACC rcall SendACK ;akceptovanie Setup Data paketu ;ENG;accept Setup Data packet rcall FinishReceiving ;ukonci prijem ;ENG;finish receiving ldi ActionFlag,DoReceiveSetupData rjmp EndInt0Handler ReceiveOutData: push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG; backup next registers and continue push temp3 push RS232BufptrX push ACC cpi ActionFlag,DoReceiveSetupData ;ak sa prave spracovava prikaz Setup ;ENG;if is currently in process command Setup breq NoReadySend ;tak posli NAK ;ENG;then send NAK rcall SendACK ;akceptovanie Out paketu ;ENG;accept Out packet clr ActionFlag rjmp EndInt0Handler NoReadySend: rcall SendNAK ;este nie som pripraveny s odpovedou ;ENG; still I am not ready to answer rjmp EndInt0Handler ;a opakuj - cakaj na dalsiu odozvu z USB ;ENG;and repeat - wait for next response from USB ;-----------------------------------------------------------------------------------------SetMyNewUSBAddress: ;nastavi novu USB adresu v NRZI kodovani ;ENG;set new USB address in NRZI coded clr MyAddress ;vychodzi stav odpovede - mojej nNRZI USB adresy ;ENG;original answer state - of my nNRZI USB address ldi temp2,0b00000001 ;maska na xorovanie ;ENG;mask for xoring ldi temp3,8 ;pocitadlo bitov ;ENG;bits counter SetMyNewUSBAddressLoop: mov temp0,MyAddress ;zapamatat si koncovu odpoved ;ENG;remember final answer ror MyUpdatedAddress ;do carry vysielany bit LSB (v smere naskor LSB a potom MSB) ;ENG;to carry transmitting bit LSB (in direction firstly LSB then MSB) brcs NoXORBit ;ak je jedna - nemen stav ;ENG;if one don't change state eor temp0,temp2 ;inak sa bude stav menit podla posledneho bitu odpovede ;ENG;otherwise state will be changed according to last bit of answer NoXORBit: ror temp0 ;posledny bit zmenenej odpovede do carry ;ENG;last bit of changed answer to carry rol MyAddress ;a z carry do koncovej odpovede na miesto LSB (a sucasne prehodenie LSB a MSB poradia) ;ENG;and from carry to final answer to the LSB place (and reverse LSB and MSB order) dec temp3 ;zmensi pocitadlo bitov ;ENG;decrement bits counter brne SetMyNewUSBAddressLoop ;ak pocitadlo bitov nie je nulove opakuj vysielanie s dalsim bitom ;ENG;if bits counter isn't zero repeat transmitting with next bit clr MyUpdatedAddress ;znulovanie adresy ako priznak jej buduceho nemenenia ;ENG;zero addresses as flag of its next unchanging rjmp EndInt0Handler ;-----------------------------------------------------------------------------------------FinishReceiving: ;korekcne akcie na ukoncenie prijmu ;ENG;corrective actions for receive termination cpi bitcount,7 ;prenes do buffera aj posledny necely byte ;ENG;transfer to buffer also last not completed byte breq NoRemainingBits ;ak boli vsetky byty prenesene, tak neprenasaj nic ;ENG;if were all bytes transfered, then nothing transfer inc bitcount ShiftRemainingBits: rol shiftbuf ;posun ostavajuce necele bity na spravnu poziciu ;ENG;shift remaining not completed bits on right position dec bitcount brne ShiftRemainingBits st Y+,shiftbuf ;a skopiruj shift register bo buffera - necely byte ;ENG;and copy shift register bo buffer - not completed byte NoRemainingBits: mov ByteCount,USBBufptrY subi ByteCount,InputShiftBufferBegin-1 ;v ByteCount je pocet prijatych byte (vratane necelych byte) ;ENG;in ByteCount is number of received bytes (including not completed bytes) mov InputBufferLength,ByteCount ;ENG;and save for use in main program ldi USBBufptrY,InputShiftBufferBegin prijimacieho shift buffera ;ENG;pointer to begin of receiving shift buffer ldi RS232BufptrX,InputBufferBegin+1 SOP) ;ENG;data buffer (leave out SOP) push XH ukazovatela ;ENG;save RS232BufptrX Hi index clr XH MoveDataBuffer: ld temp0,Y+ st X+,temp0 dec ByteCount brne MoveDataBuffer
;a uchovat pre pouzitie v
hlavnom programe
;pointer na zaciatok
;data buffer (vynechat ;uschova RS232BufptrX Hi
pop XH ;obnova RS232BufptrX Hi ;ENG;restore RS232BufptrX Hi index ldi ByteCount,nNRZISOPbyte sts InputBufferBegin,ByteCount ;ako keby sa prijal SOP nekopiruje sa zo shift buffera ;ENG;like received SOP - it is not copied from shift buffer ret ;-----------------------------------------------------------------------------------------ukazovatela
;******************************************************************** ;* Other procedures ;ENG;* Other procedures ;******************************************************************** ;-----------------------------------------------------------------------------------------USBReset: ;inicializacia USB stavoveho stroja ;ENG;initialization of USB state engine ldi
temp0,nNRZIADDR0
;inicializacia USB adresy
;ENG;
mov clr
MyAddress,temp0 State
;inicializacia stavoveho stroja ;ENG;
clr clr clr clr
BitStuffInOut OutBitStuffNumber ActionFlag RAMread
;bude sa vycitavat z ROM-ky
initialization of USB address
initialization of state engine
;ENG;will be
reading from ROM
OutputBufferLength do USB
sts ConfigByte,RAMread ;nenakonfiguravany stav ;ENG;unconfigured state ret ;-----------------------------------------------------------------------------------------SendPreparedUSBAnswer: ;poslanie kodovanim NRZI OUT buffera s dlzkou ;ENG;transmitting by NRZI coding OUT buffer with length OutputBufferLength to USB mov ByteCount,OutputBufferLength ;dlzka odpovede ;ENG;length of
answer SendUSBAnswer:
;poslanie kodovanim NRZI OUT buffera do USB
;ENG;transmitting by
NRZI coding OUT buffer to USB ldi USBBufptrY,OutputBufferBegin ;pointer na zaciatok vysielacieho buffera ;ENG;pointer to begin of transmitting buffer SendUSBBuffer: ;poslanie kodovanim NRZI dany buffer do USB ;ENG;transmitting by NRZI coding given buffer to USB ldi temp1,0 ;zvysovanie pointera (pomocna premenna) ;ENG; incrementing pointer (temporary variable) mov temp3,ByteCount ;pocitadlo bytov: temp3 = ByteCount ;ENG; byte counter: temp3 = ByteCount ldi temp2,0b00000011 ;maska na xorovanie ;ENG;mask for xoring ld inputbuf,Y+ ;nacitanie prveho bytu do inputbuf a zvys
http://avr-asm.tripod.com/usb232.html (1 of 4)1/20/2009 8:56:38 PM
16 BIT MATH (AVR 202)
pointer do buffera
;ENG;load first byte to inputbuf and increment pointer to buffer
USB
cbi ;ENG;down DATAPLUS : idle state of USB port sbi ;ENG;set DATAMINUS : idle state of USB port sbi sbi
USB
outputport,DATAplus
;USB ako vystup: ;ENG;USB as output: ;zhodenie DATAplus : kludovy stav portu
outputport,DATAminus
;nahodenie DATAminus : kludovy stav portu
USBdirection,DATAplus USBdirection,DATAminus
;DATAplus ako vystupny ;ENG;DATAPLUS as output ;DATAminus ako vystupny ;ENG;DATAMINUS as
temp0,outputport
;kludovy stav portu USB do temp0
output in
;ENG;
idle state of USB port to temp0 SendUSBAnswerLoop: ldi bitcount,7 SendUSBAnswerByteLoop: nop
;pocitadlo bitov
;ENG;bits counter
;oneskorenie kvoli casovaniu
;ENG;delay
because timing ror inputbuf ;ENG;to carry transmiting bit (in direction first LSB then MSB) brcs NoXORSend if that it is one - don't change USB state eor temp0,temp2 state will be changed NoXORSend: out outputport,temp0 dec bitcount flagu ;ENG;decrement bits counter - according to carry flag brne SendUSBAnswerByteLoop vysielanie s dalsim bitom ;ENG;if bits counter isn't zero - repeat transmiting with next bit sbrs inputbuf,0 USB ;ENG;if is transmiting bit one - don't change USB state eor temp0,temp2 state will be changed NoXORSendLSB: dec temp3 counter ld inputbuf,Y+ buffera ;ENG;load next byte and increment pointer to buffer out outputport,temp0 brne SendUSBAnswerLoop temp3=0) ;ENG;repeat for all buffer (till temp3=0)
;do carry vysielany bit (v smere naskor LSB a
potom MSB)
;ak je jedna - nemen stav na USB ;inak sa bude stav menit
;ENG; ;ENG;otherwise
;vysli von na USB ;ENG;send out to USB ;zmensi pocitadlo bitov - podla carry ;ak pocitadlo bitov nie je nulove - opakuj
;ak je vysielany bit jedna - nemen stav na ;inak sa bude stav menit
;zniz pocitadlo bytov
;ENG;otherwise
;ENG;decrement bytes
;nacitanie dalsieho bytu a zvys pointer do ;vysli von na USB ;ENG;transmit to USB ;opakuj pre cely buffer (pokial
mov
bitcount,OutBitStuffNumber
cpi
bitcount,0
;pocitadlo bitov pre bitstuff
;ENG;
bits counter for bitstuff ;ak nie je potrebny bitstuff
;ENG;if not be
needed bitstuff breq ZeroBitStuf SendUSBAnswerBitstuffLoop: ror inputbuf ;do carry vysielany bit (v smere naskor LSB a potom MSB) ;ENG;to carry transmiting bit (in direction first LSB then MSB) brcs NoXORBitstuffSend ;ak je jedna - nemen stav na USB ;ENG; if is one - don't change state on USB eor temp0,temp2 ;inak sa bude stav menit ;ENG;otherwise state will be changed NoXORBitstuffSend: out outputport,temp0 ;vysli von na USB ;ENG;transmit to USB nop ;oneskorenie kvoli casovaniu ;ENG;delay because of timing dec bitcount ;zmensi pocitadlo bitov - podla carry flagu ;ENG;decrement bits counter - according to carry flag brne SendUSBAnswerBitstuffLoop ;ak pocitadlo bitov nie je nulove opakuj vysielanie s dalsim bitom ;ENG;if bits counter isn't zero - repeat transmiting with next bit ld inputbuf,Y ;oneskorenie 2 cykly ;ENG;delay 2 cycle ZeroBitStuf: nop ;oneskorenie 1 cyklus ;ENG;delay 1 cycle cbr temp0,3 out outputport,temp0 ;vysli EOP na USB ;ENG;transmit EOP on USB
(16 cyklov pri 12MHz)
ldi bitcount,5 ;ENG;delay counter: EOP shouls exists 2 bits (16 cycle at 12MHz) SendUSBWaitEOP: dec bitcount brne SendUSBWaitEOP
;pocitadlo oneskorenia: EOP ma trvat 2 bity
sbi outputport,DATAminus ;nahodenie DATAminus : kludovy stav na port USB ;ENG;set DATAMINUS : idle state on USB port sbi outputport,DATAminus ;oneskorenie 2 cykly: Idle ma trvat 1 bit (8 cyklov pri 12MHz) ;ENG;delay 2 cycle: Idle should exists 1 bit (8 cycle at 12MHz) cbi USBdirection,DATAplus ;DATAplus ako vstupny ;ENG;DATAPLUS as input cbi USBdirection,DATAminus ;DATAminus ako vstupny ;ENG;DATAMINUS as input cbi outputport,DATAminus ;zhodenie DATAminus : treti stav na port USB ;ENG;reset DATAMINUS : the third state on USB port ret ;-----------------------------------------------------------------------------------------ToggleDATAPID: lds temp0,OutputBufferBegin+1 ;nahraj posledne PID ;ENG;load last PID cpi temp0,DATA1PID ;ak bolo posledne DATA1PID byte ;ENG; if last was DATA1PID byte ldi temp0,DATA0PID breq SendData0PID ;tak posli nulovu odpoved s DATA0PID ;ENG;then send zero answer with DATA0PID ldi temp0,DATA1PID ;inak posli nulovu odpoved s DATA1PID ;ENG;otherwise send zero answer with DATA1PID SendData0PID: sts OutputBufferBegin+1,temp0 ;DATA0PID byte ;ENG;DATA0PID byte ret ;-----------------------------------------------------------------------------------------ComposeZeroDATA1PIDAnswer: ldi temp0,DATA0PID ;DATA0 PID - v skutocnosti sa stoggluje na DATA1PID v nahrati deskriptora ;ENG;DATA0 PID - in the next will be toggled to DATA1PID in load descriptor sts OutputBufferBegin+1,temp0 ;nahraj do vyst buffera ;ENG;load to output buffer ComposeZeroAnswer: ldi temp0,SOPbyte sts OutputBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte rcall ToggleDATAPID ;zmen DATAPID ;ENG;change DATAPID ldi temp0,0x00 sts OutputBufferBegin+2,temp0 ;CRC byte ;ENG;CRC byte sts OutputBufferBegin+3,temp0 ;CRC byte ;ENG;CRC byte ldi ByteCount,2+2 ;dlzka vystupneho buffera (SOP a PID + CRC16) ;ENG;length of output buffer (SOP and PID + CRC16) ret ;-----------------------------------------------------------------------------------------InitACKBufffer: ldi temp0,SOPbyte sts ACKBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte ldi temp0,ACKPID sts ACKBufferBegin+1,temp0 ;ACKPID byte ;ENG;ACKPID byte ret ;-----------------------------------------------------------------------------------------SendACK: push USBBufptrY push bitcount push OutBitStuffNumber ldi USBBufptrY,ACKBufferBegin ;pointer na zaciatok ACK buffera ;ENG;pointer to begin of ACK buffer ldi ByteCount,2 ;pocet vyslanych bytov (iba SOP a ACKPID) ;ENG;number of transmit bytes (only SOP and ACKPID) clr OutBitStuffNumber rcall SendUSBBuffer pop OutBitStuffNumber pop bitcount pop USBBufptrY ret ;-----------------------------------------------------------------------------------------InitNAKBufffer: ldi temp0,SOPbyte sts NAKBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte ldi temp0,NAKPID sts NAKBufferBegin+1,temp0 ;NAKPID byte ;ENG;NAKPID byte ret ;-----------------------------------------------------------------------------------------SendNAK: push OutBitStuffNumber ldi USBBufptrY,NAKBufferBegin ;pointer na zaciatok ACK buffera ;ENG;pointer to begin of ACK buffer ldi ByteCount,2 ;pocet vyslanych bytov (iba SOP a NAKPID) ;ENG;number of transmited bytes (only SOP and NAKPID) clr OutBitStuffNumber rcall SendUSBBuffer pop OutBitStuffNumber ret ;-----------------------------------------------------------------------------------------ComposeSTALL: ldi temp0,SOPbyte sts OutputBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte ldi temp0,STALLPID sts OutputBufferBegin+1,temp0 ;STALLPID byte ;ENG;STALLPID byte ldi ByteCount,2 ;dlzka vystupneho buffera (SOP a PID) ;ENG;length of output buffer (SOP and PID) ret ;-----------------------------------------------------------------------------------------DecodeNRZI: ;enkodovanie buffera z NRZI kodu do binarneho ;ENG;encoding of buffer from NRZI code to binary push USBBufptrY ;zalohuj pointer do buffera ;ENG;back up pointer to buffer push ByteCount ;zalohuj dlzku buffera ;ENG;back up length of buffer add ByteCount,USBBufptrY ;koniec buffera do ByteCount ;ENG;end of buffer to ByteCount ser temp0 ;na zabezpecenie jednotkoveho carry (v nasledujucej rotacii) ;ENG;to ensure unit carry (in the next rotation) NRZIloop: ror temp0 ;naplnenie carry z predchadzajuceho byte ;ENG;filling carry from previous byte ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load received byte from buffer mov temp2,temp0 ;posunuty register o jeden bit vpravo a XOR na funkciu NRZI dekodovania ;ENG;shifted register to one bit to the right and XOR for function of NRZI decoding ror temp2 ;carry do najvyssieho bitu a sucasne posuv ;ENG;carry to most significant digit bit and shift eor temp2,temp0 ;samotne dekodovanie NRZI ;ENG;NRZI decoding com temp2 ;negovanie ;ENG;negate st Y+,temp2 ;ulozenie spat ako dekodovany byte a zvys pointer do buffera ;ENG;save back as decoded byte and increment pointer to buffer cp USBBufptrY,ByteCount ;ak este neboli vsetky ;ENG;if not all bytes brne NRZIloop ;tak opakuj ;ENG;then repeat pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length pop USBBufptrY ;obnov pointer do buffera ;ENG;restore pointer to buffer ret ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------BitStuff: ;odstranenie bit-stuffingu v buffri ;ENG;removal of bitstuffing in buffer clr temp3 ;pocitadlo vynechanych bitov ;ENG;counter of omitted bits clr lastBitstufNumber ;0xFF do lastBitstufNumber ;ENG;0xFF to lastBitstufNumber dec lastBitstufNumber BitStuffRepeat: push USBBufptrY ;zalohuj pointer do buffera ;ENG;back up pointer to buffer push ByteCount ;zalohuj dlzku buffera ;ENG;back up buffer length mov temp1,temp3 ;pocitadlo vsetkych bitov ;ENG;counter of all bits ldi temp0,8 ;spocitat vsetky bity v bufferi ;ENG;sum all bits in buffer SumAllBits: add temp1,temp0 dec ByteCount brne SumAllBits ldi temp2,6 ;inicializuj pocitadlo jednotiek ;ENG; initialize counter of ones pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length push ByteCount ;zalohuj dlzku buffera ;ENG;back up buffer length add ByteCount,USBBufptrY ;koniec buffera do ByteCount ;ENG;end of buffer to ByteCount inc ByteCount ;a pre istotu ho zvys o 2 (kvoli posuvaniu) ;ENG;and for safety increment it with 2 (because of shifting) inc ByteCount BitStuffLoop: ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load received byte from buffer ldi bitcount,8 ;pocitadlo bitov v byte ;ENG;bits counter in byte BitStuffByteLoop: ror temp0 ;naplnenie carry z LSB ;ENG;filling carry from LSB brcs IncrementBitstuff ;ak LSB=0 ;ENG;if that LSB=0 ldi temp2,7 ;inicializuj pocitadlo jednotiek +1 (ak bola nula) ;ENG;initialize counter of ones +1 (if was zero) IncrementBitstuff: dec temp2 ;zniz pocitadlo jednotiek (predpoklad jednotkoveho bitu) ;ENG;decrement counter of ones (assumption of one bit) brne NeposunBuffer ;ak este nebolo 6 jednotiek za sebou - neposun buffer ;ENG;if there was not 6 ones together - don't shift buffer cp temp1,lastBitstufNumber ; ldi temp2,6 ;inicializuj pocitadlo jednotiek (ak by sa nerobil bitstuffing tak sa musi zacat odznova) ;ENG;initialize counter of ones (if no bitstuffing will be made then must be started again) brcc NeposunBuffer ;ak sa tu uz robil bitstuffing - neposun buffer ;ENG;if already was made bitstuffing - don't shift buffer dec temp1 ; mov lastBitstufNumber,temp1 ;zapamataj si poslednu poziciu bitstuffingu ;ENG;remember last position of bitstuffing cpi bitcount,1 ;aby sa ukazovalo na 7 bit (ktory sa ma vymazat alebo kde sa ma vlozit nula) ;ENG;for pointing to 7-th bit (which must be deleted or where to insert zero) brne NoBitcountCorrect ldi bitcount,9 ; inc USBBufptrY ;zvys pointer do buffera ENG;increment pointer to buffer NoBitcountCorrect: dec bitcount bst BitStuffInOut,0 brts CorrectOutBuffer ;ak je Out buffer - zvys dlzku buffera ;ENG; if this is Out buffer - increment buffer length rcall ShiftDeleteBuffer ;posun In buffer ;ENG;shift In buffer dec temp3 ;zniz pocitadlo vynechani ;ENG;decrement counter of omission rjmp CorrectBufferEnd CorrectOutBuffer: rcall ShiftInsertBuffer ;posun Out buffer ;ENG;shift Out buffer inc temp3 ;zvys pocitadlo vynechani ;ENG;increment counter of omission CorrectBufferEnd: pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length pop USBBufptrY ;obnov pointer do buffera ;ENG;restore pointer to buffer rjmp BitStuffRepeat ;a restartni od zaciatku ;ENG;and restart from begin NeposunBuffer: dec temp1 ;ak uz boli vsetky bity ;ENG;if already were all bits breq EndBitStuff ;ukonci cyklus ;ENG;finish cycle dec bitcount ;zniz pocitadlo bitov v byte ;ENG;decrement bits counter in byte brne BitStuffByteLoop ;ak este neboli vsetky bity v byte - chod na dalsi bit ;ENG;if not yet been all bits in byte - go to next bit ;inak nahraj dalsi byte ;ENG;otherwise load next byte inc USBBufptrY ;zvys pointer do buffera ;ENG;increment pointer to buffer rjmp BitStuffLoop ;a opakuj ;ENG;and repeat EndBitStuff: pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer length pop USBBufptrY ;obnov pointer do buffera ;ENG;restore pointer to buffer bst BitStuffInOut,0 brts IncrementLength ;ak je Out buffer - zvys dlzku Out buffera ;ENG;if this is Out buffer - increment length of Out buffer DecrementLength: ;ak je In buffer - zniz dlzku In buffera ;ENG;if this is In buffer - decrement length of In buffer cpi temp3,0 ;bolo aspon jedno znizenie ;ENG;was at least one decrement breq NoChangeByteCount ;ak nie - nemen dlzku buffera ;ENG;if no don't change buffer length dec ByteCount ;ak je In buffer - zniz dlzku buffera ;ENG; if this is In buffer - decrement buffer length subi temp3,256-8 ;ak nebolo viac ako 8 bitov naviac ;ENG; if there wasn't above 8 bits over brcc NoChangeByteCount ;tak skonci ;ENG;then finish dec ByteCount ;inak este zniz dlzku buffera ;ENG;otherwise next decrement buffer length ret ;a skonci ;ENG;and finish IncrementLength: mov OutBitStuffNumber,temp3 ;zapamataj si pocet bitov naviac ;ENG; remember number of bits over subi temp3,8 ;ak nebolo viac ako 8 bitov naviac ;ENG; if there wasn't above 8 bits over brcs NoChangeByteCount ;tak skonci ;ENG;then finish inc ByteCount ;inak zvys dlzku buffera ;ENG;otherwise increment buffer length mov OutBitStuffNumber,temp3 ;a zapamataj si pocet bitov naviac (znizene o 8) ;ENG;and remember number of bits over (decremented by 8) NoChangeByteCount: ret ;skonci ;ENG;finish ;-----------------------------------------------------------------------------------------ShiftInsertBuffer: ;posuv buffer o jeden bit vpravo od konca az po poziciu: byteUSBBufptrY a bit-bitcount ;ENG;shift buffer by one bit to right from end till to position: byte-USBBufptrY and bit-bitcount mov temp0,bitcount ;vypocet: bitcount= 9-bitcount ;ENG; calculation: bitcount= 9-bitcount ldi bitcount,9 sub bitcount,temp0 ;do bitcount poloha bitu, ktory treba nulovat ;ENG;to bitcount bit position, which is necessary to clear ld temp1,Y ;nahraj byte ktory este treba posunut od pozicie bitcount ;ENG;load byte which still must be shifted from position bitcount rol temp1 ;a posun vlavo cez Carry (prenos z vyssieho byte a LSB do Carry) ;ENG;and shift to the left through Carry (transmission from higher byte and LSB to Carry) ser temp2 ;FF do masky - temp2 ;ENG;FF to mask - temp2 HalfInsertPosuvMask: lsl temp2 ;nula do dalsieho spodneho bitu masky ;ENG; zero to the next low bit of mask dec bitcount ;az pokial sa nedosiahne hranica posuvania v byte ;ENG;till not reached boundary of shifting in byte brne HalfInsertPosuvMask and temp1,temp2 v temp1 ;ENG;unmask that remains only high shifted bits in temp1 com temp2 lsr temp2 bitu ;ENG;shift mask to the right - for insertion of zero bit ld temp0,Y pozicie bitcount do temp0 ;ENG;load byte which must be shifted from position bitcount to temp0 and temp0,temp2 bity v temp0 ;ENG;unmask to remains only low non-shifted bits in temp0 or temp1,temp0 and put together shifted and nonshifted part
;odmaskuj aby zostali iba vrchne posunute bity
;invertuj masku ;ENG;invert mask ;posun masku vpravo - na vlozenie nuloveho ;nahraj byte ktory este treba posunut od
;odmaskuj aby zostali iba spodne neposunute
;a zluc posunutu a neposunutu cast
;ENG;
ld temp0,Y ;nahraj byte ktory este treba posunut od pozicie bitcount ;ENG;load byte which must be shifted from position bitcount rol temp0 ;a posun ho vlavo cez Carry (aby sa nastavilo spravne Carry pre dalsie prenosy) ;ENG;and shift it to the left through Carry (to set right Carry for further carry) st Y+,temp1 ;a nahraj spat upraveny byte ;ENG;and load back modified byte ShiftInsertBufferLoop: cpse USBBufptrY,ByteCount ;ak nie su vsetky cele byty ;ENG;if are not all entire bytes rjmp NoEndShiftInsertBuffer ;tak pokracuj ;ENG;then continue ret ;inak skonci ;ENG;otherwise finish NoEndShiftInsertBuffer: ld temp1,Y ;nahraj byte ;ENG;load byte rol temp1 ;a posun vlavo cez Carry (prenos z nizsieho byte a LSB do Carry) ;ENG;and shift to the left through Carry (carry from low byte and LSB to Carry) st Y+,temp1 ;a nahraj spat ;ENG;and store back rjmp ShiftInsertBufferLoop ;a pokracuj ;ENG;and continue ;-----------------------------------------------------------------------------------------ShiftDeleteBuffer: ;posuv buffera o jeden bit vlavo od konca az po poziciu: byteUSBBufptrY a bit-bitcount ;ENG;shift buffer one bit to the left from end to position: byte-USBBufptrY and bit-bitcount mov temp0,bitcount ;vypocet: bitcount= 9-bitcount ;ENG; calculation: bitcount= 9-bitcount ldi bitcount,9 sub bitcount,temp0 ;do bitcount poloha bitu, ktory este treba posunut ;ENG;to bitcount bit position, which must be shifted mov temp0,USBBufptrY ;uschovanie pointera do buffera ;ENG;backup pointera to buffer inc temp0 ;pozicia celych bytov do temp0 ;ENG;position of completed bytes to temp0 mov USBBufptrY,ByteCount ;maximalna pozicia do pointera ;ENG;maximum position to pointer ShiftDeleteBufferLoop: ld temp1,-Y ;zniz buffer a nahraj byte ;ENG;decrement buffer and load byte ror temp1 ;a posun vpravo cez Carry (prenos z vyssieho byte a LSB do Carry) ;ENG;and right shift through Carry (carry from higher byte and LSB to Carry) st Y,temp1 ;a nahraj spat ;ENG;and store back cpse USBBufptrY,temp0 ;ak nie su vsetky cele byty ;ENG;if there are not all entire bytes rjmp ShiftDeleteBufferLoop ;tak pokracuj ;ENG;then continue ld temp1,-Y ;zniz buffer a nahraj byte ktory este treba ;ENG;decrement buffer and load byte which must be shifted from position bitcount ror temp1 ;a posun vpravo cez Carry (prenos z vyssieho byte a LSB do Carry) ;ENG;and right shift through Carry (carry from higher byte and LSB to Carry) ser temp2 ;FF do masky - temp2 ;ENG;FF to mask - temp2 HalfDeletePosuvMask: dec bitcount ;az pokial sa nedosiahne hranica posuvania v byte ;ENG;till not reached boundary of shifting in byte breq DoneMask lsl temp2 ;nula do dalsieho spodneho bitu masky ;ENG; zero to the next low bit of mask rjmp HalfDeletePosuvMask DoneMask: and temp1,temp2 ;odmaskuj aby zostali iba vrchne posunute bity v temp1 ;ENG;unmask to remain only high shifted bits in temp1 com temp2 ;invertuj masku ;ENG;invert mask ld temp0,Y ;nahraj byte ktory este treba posunut od pozicie bitcount do temp0 ;ENG;load byte which must be shifted from position bitcount to temp0 and temp0,temp2 ;odmaskuj aby zostali iba spodne neposunute bity v temp0 ;ENG;unmask to remain only low nonshifted bits in temp0 or temp1,temp0 ;a zluc posunutu a neposunutu cast ;ENG; and put together shifted and nonshifted part st Y,temp1 ;a nahraj spat ;ENG;and store back ret ;a skonci ;ENG;and finish ;-----------------------------------------------------------------------------------------MirrorInBufferBytes: push USBBufptrY push ByteCount ldi USBBufptrY,InputBufferBegin rcall MirrorBufferBytes pop ByteCount pop USBBufptrY ret ;-----------------------------------------------------------------------------------------MirrorBufferBytes: add ByteCount,USBBufptrY ;ByteCount ukazuje na koniec spravy ;ENG; ByteCount shows to the end of message MirrorBufferloop: ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load received byte from buffer ldi temp1,8 ;pocitadlo bitov ;ENG;bits counter MirrorBufferByteLoop: ror temp0 ;do carry dalsi najnizsi bit ;ENG;to carry next least bit rol temp2 ;z carry dalsi bit na obratene poradie ;ENG; from carry next bit to reverse order dec temp1 ;bol uz cely byte ;ENG;was already entire byte brne MirrorBufferByteLoop ;ak nie tak opakuj dalsi najnizsi bit ;ENG; if no then repeat next least bit st Y+,temp2 ;ulozenie spat ako obrateny byte a zvys pointer do buffera ;ENG;save back as reversed byte and increment pointer to buffer cp USBBufptrY,ByteCount ;ak este neboli vsetky ;ENG;if not yet been all brne MirrorBufferloop ;tak opakuj ;ENG;then repeat ret ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------;CheckCRCIn: ;ENG;CheckCRCIn: ; push USBBufptrY ;ENG; kiss USBBUFPTRY ; push ByteCount ;ENG; kiss ByteCount ; ldi USBBufptrY,InputBuffercompare ;ENG; ldi USBBUFPTRY, InputBuffercompare ; rcall CheckCRC ;ENG; rcall CheckCRC ; pop ByteCount ;ENG; pope ByteCount ; pop USBBufptrY ;ENG; pope USBBUFPTRY ; ret ;ENG; lip ;-----------------------------------------------------------------------------------------AddCRCOut: push USBBufptrY push ByteCount ldi USBBufptrY,OutputBufferBegin rcall CheckCRC com temp0 ;negacia CRC ;ENG;negation of CRC com temp1 st Y+,temp1 ;ulozenie CRC na koniec buffera (najskor MSB) ;ENG;save CRC to the end of buffer (at first MSB) st Y,temp0 ;ulozenie CRC na koniec buffera (potom LSB) ;ENG;save CRC to the end of buffer (then LSB) dec USBBufptrY ;pointer na poziciu CRC ;ENG;pointer to CRC position ldi ByteCount,2 ;otocit 2 byty CRC ;ENG;reverse bits order in 2 bytes CRC rcall MirrorBufferBytes ;opacne poradie bitov CRC (pri vysielani CRC sa posiela naskor MSB) ;ENG;reverse bits order in CRC (transmiting CRC - MSB first) pop ByteCount pop USBBufptrY ret ;-----------------------------------------------------------------------------------------CheckCRC: ;vstup: USBBufptrY = zaciatok spravy ,ByteCount = dlzka spravy ;ENG; input: USBBufptrY = begin of message ,ByteCount = length of message add ByteCount,USBBufptrY ;ByteCount ukazuje na koniec spravy ;ENG; ByteCount points to the end of message inc USBBufptrY ;nastav pointer na zaciatok spravy - vynechat SOP ;ENG;set the pointer to message start - omit SOP ld temp0,Y+ ;nahraj PID do temp0 ;ENG;load PID to temp0 ;a nastav pointer na zaciatok spravy vynechat aj PID ;ENG;and set the pointer to start of message - omit also PID cpi temp0,DATA0PID ;ci je DATA0 pole ;ENG;if is DATA0 field breq ComputeDATACRC ;pocitaj CRC16 ;ENG;compute CRC16 cpi temp0,DATA1PID ;ci je DATA1 pole ;ENG;if is DATA1 field brne CRC16End ;ak nie tak skonci ;ENG;if no then finish ComputeDATACRC: ser temp0 ;inicializacia zvysku LSB na 0xff ;ENG; initialization of remaider LSB to 0xff ser temp1 ;inicializacia zvysku MSB na 0xff ;ENG;initialization of remaider MSB to 0xff CRC16Loop: ld temp2,Y+ ;nahraj spravu do temp2 a zvys pointer do buffera ;ENG;load message to temp2 and increment pointer to buffer ldi temp3,8 ;pocitadlo bitov v byte - temp3 ;ENG;bits counter in byte - temp3 CRC16LoopByte: bst temp1,7 ;do T uloz MSB zvysku (zvysok je iba 16 bitovy - 8 bit vyssieho byte) ;ENG;to T save MSB of remainder (remainder is only 16 bits - 8 bit of higher byte) bld bitcount,0 ;do bitcount LSB uloz T - MSB zvysku ;ENG; to bitcount LSB save T - of MSB remainder eor bitcount,temp2 ;XOR bitu spravy a bitu zvysku - v LSB bitcount ;ENG;XOR of bit message and bit remainder - in LSB bitcount rol temp0 ;posun zvysok dolava - nizsi byte (dva byty cez carry) ;ENG;shift remainder to the left - low byte (two bytes - through carry) rol temp1 ;posun zvysok dolava - vyssi byte (dva byty cez carry) ;ENG;shift remainder to the left - high byte (two bytes - through carry) cbr temp0,1 ;znuluj LSB zvysku ;ENG;znuluj LSB remains lsr temp2 ;posun spravu doprava ;ENG;shift message to right ror bitcount ;vysledok XOR-u bitov z LSB do carry ;ENG; result of XOR bits from LSB to carry brcc CRC16NoXOR ;ak je XOR bitu spravy a MSB zvysku = 0 , tak nerob XOR ;ENG;if is XOR bitmessage and MSB of remainder = 0 , then no XOR ldi bitcount,CRC16poly>>8 ;do bitcount CRC polynom - vrchny byte ;ENG; to bitcount CRC polynomial - high byte eor temp1,bitcount ;a urob XOR zo zvyskom a CRC polynomom vrchny byte ;ENG;and make XOR from remains and CRC polynomial - high byte ldi bitcount,CRC16poly ;do bitcount CRC polynom - spodny byte ;ENG; to bitcount CRC polynomial - low byte eor temp0,bitcount ;a urob XOR zo zvyskom a CRC polynomom spodny byte ;ENG;and make XOR of remainder and CRC polynomial - low byte CRC16NoXOR: dec temp3 ;boli uz vsetky bity v byte ;ENG;were already all bits in byte brne CRC16LoopByte ;ak nie, tak chod na dalsi bit ;ENG;unless, then go to next bit cp USBBufptrY,ByteCount ;bol uz koniec spravy ;ENG;was already endof-message brne CRC16Loop ;ak nie tak opakuj ;ENG;unless then repeat CRC16End: ret ;inak skonci (v temp0 a temp1 je vysledok) ;ENG;otherwise finish (in temp0 and temp1 is result) ;-----------------------------------------------------------------------------------------LoadDescriptorFromROM: lpm ;nahraj z pozicie ROM pointera do R0 ;ENG; load from ROM position pointer to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index to ROM dec ByteCount ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromROM ;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadDescriptorFromROMZeroInsert: lpm ;nahraj z pozicie ROM pointerra do R0 ;ENG; load from ROM position pointer to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer posunut od pozicie bitcount
bst nula
RAMread,3
;ak je 3 bit jednotkovy - nebude sa vkladat
brtc
InsertingZero
;inak sa bude vkladat nula
adiw
ZH:ZL,1
;zvys ukazovatel do ROM ;ENG;increment index
;ENG;if bit 3 is one - don't insert zero ;ENG;otherwise
zero will be inserted to ROM lpm
;nahraj z pozicie ROM pointerra do R0
;ENG;
;R0 uloz do buffera a zvys buffer
;ENG;
load from ROM position pointer to R0 st
Y+,R0
R0 save to buffer and increment buffer
vkladali nuly
clt bld RAMread,3 ;ENG;the third bit in RAMread - for to the next zero insertion will be made rjmp InsertingZeroEnd InsertingZero: clr R0
;a znuluj ;ENG;and clear ;treti bit v RAMread - aby sa v dalsom
;a pokracuj
;ENG;and continue
;na vkladanie nul
;ENG;for insertion of
zero st
Y+,R0
;nulu uloz do buffera a zvys buffer
;ENG;
zero save to buffer and increment buffer InsertingZeroEnd: adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index to ROM subi ByteCount,2 ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromROMZeroInsert ;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadDescriptorFromSRAM: ld R0,Z ;nahraj z pozicie RAM pointerra do R0 ;ENG; load from position RAM pointer to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer adiw ZH:ZL,1 ;zvys ukazovatel do RAM ;ENG;increment index to RAM dec ByteCount ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromSRAM ;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadDescriptorFromEEPROM: out EEARL,ZL ;nastav adresu EEPROM Lo ;ENG;set the address EEPROM Lo out EEARH,ZH ;nastav adresu EEPROM Hi ;ENG;set the address EEPROM Hi sbi EECR,EERE ;vycitaj EEPROM do registra EEDR ;ENG; read EEPROM to register EEDR in R0,EEDR ;nahraj z EEDR do R0 ;ENG;load from EEDR to R0 st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG; R0 save to buffer and increment buffer adiw ZH:ZL,1 ;zvys ukazovatel do EEPROM ;ENG;increment index to EEPROM dec ByteCount ;pokial nie su vsetky byty ;ENG;till are not all bytes brne LoadDescriptorFromEEPROM;tak nahravaj dalej ;ENG;then load next rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish ;-----------------------------------------------------------------------------------------LoadXXXDescriptor: ldi temp0,SOPbyte ;SOP byte ;ENG;SOP byte sts OutputBufferBegin,temp0 ;na zaciatok vysielacieho buffera dat SOP ;ENG;to begin of tramsmiting buffer store SOP ldi ByteCount,8 ;8 bytov nahrat ;ENG;8 byte store ldi USBBufptrY,OutputBufferBegin+2 ;do vysielacieho buffera ;ENG; to transmitting buffer and RAMread,RAMread ;ci sa bude citat z RAM alebo ROM-ky alebo EEPROM-ky ;ENG;if will be reading from RAM or ROM or EEPROM brne FromRAMorEEPROM ;0=ROM,1=RAM,2=EEPROM,4=ROM s vkladanim nuly ;ENG;0=ROM,1=RAM,2=EEPROM,4=ROM with zero insertion (string) FromROM: rjmp LoadDescriptorFromROM ;nahrat descriptor z ROM-ky ;ENG; load descriptor from ROM FromRAMorEEPROM: sbrc RAMread,2 ;ak RAMread=4 ;ENG;if RAMREAD=4 rjmp LoadDescriptorFromROMZeroInsert ;citaj z ROM s vkladanim nuly ;ENG; read from ROM with zero insertion sbrc RAMread,0 ;ak RAMread=1 ;ENG;if RAMREAD=1 rjmp LoadDescriptorFromSRAM ;nahraj data zo SRAM-ky ;ENG;load data from SRAM rjmp LoadDescriptorFromEEPROM ;inak citaj z EEPROM ;ENG;otherwise read from EEPROM EndFromRAMROM: sbrc RAMread,7 ;ak je najvyssi bit v premennej RAMread=1 ;ENG;if is most significant bit in variable RAMread=1 clr RAMread ;znuluj RAMread ;ENG;clear RAMread rcall ToggleDATAPID ;zmenit DATAPID ;ENG;change DATAPID ldi USBBufptrY,OutputBufferBegin+1 ;do vysielacieho buffera - pozicia DATA PID ;ENG;to transmitting buffer - position of DATA PID ret ;-----------------------------------------------------------------------------------------PrepareUSBOutAnswer: ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer rcall PrepareUSBAnswer ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer MakeOutBitStuff: inc BitStuffInOut ;vysielaci buffer - vkladanie bitstuff bitov ;ENG;transmitting buffer - insertion of bitstuff bits ldi USBBufptrY,OutputBufferBegin ;do vysielacieho buffera ;ENG; to transmitting buffer rcall BitStuff mov OutputBufferLength,ByteCount ;dlzku odpovede zapamatat pre vysielanie ;ENG;length of answer store for transmiting clr BitStuffInOut ;prijimaci buffer - mazanie bitstuff bitov ;ENG;receiving buffer - deletion of bitstuff bits ret ;-----------------------------------------------------------------------------------------PrepareUSBAnswer: ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer clr RAMread ;nulu do RAMread premennej - cita sa z ROM-ky ;ENG;zero to RAMread variable - reading from ROM lds temp0,InputBufferBegin+2 ;bmRequestType do temp0 ;ENG; bmRequestType to temp0 lds temp1,InputBufferBegin+3 ;bRequest do temp1 ;ENG;bRequest to temp1 cbr temp0,0b10011111 ;ak je 5 a 6 bit nulovy ;ENG;if is 5 and 6 bit zero brne VendorRequest ;tak to nie je Vendor Request ;ENG; then this isn't Vendor Request rjmp StandardRequest ;ale je to standardny request ;ENG; but this is standard Request ;-------------------------VendorRequest: clr ZH ;pre citanie z RAM alebo EEPROM ;ENG; for reading from RAM or EEPROM cpi temp1,1 brne NoDoSetInfraBufferEmpty rjmp DoSetInfraBufferEmpty zastavene citanim z RAM-ky) ;ENG;restart infra receiving (if it was stopped by reading from RAM) NoDoSetInfraBufferEmpty: cpi temp1,2 brne NoDoGetInfraCode rjmp DoGetInfraCode bufferi) ;ENG;transmit received infra code (if it is in buffer) NoDoGetInfraCode: cpi temp1,3 brne NoDoSetDataPortDirection rjmp DoSetDataPortDirection bitov ;ENG;set flow direction of datal bits NoDoSetDataPortDirection: cpi temp1,4 brne NoDoGetDataPortDirection rjmp DoGetDataPortDirection detect of flow direction of data bits NoDoGetDataPortDirection: cpi temp1,5 brne NoDoSetOutDataPort rjmp DoSetOutDataPort tak ich pull-up) ;ENG;set data bits (if they are inputs, then pull-ups) NoDoSetOutDataPort: cpi temp1,6 brne NoDoGetOutDataPort rjmp DoGetOutDataPort (ak su vstupne, tak ich pull-up) ;ENG;detect settings of data out bits (if they are input, then pull-ups) NoDoGetOutDataPort: cpi temp1,7 brne NoDoGetInDataPort rjmp DoGetInDataPort portu ;ENG;return value of input data port NoDoGetInDataPort: cpi temp1,8 brne NoDoEEPROMRead rjmp DoEEPROMRead adresy ;ENG;return contents of EEPROM from given address NoDoEEPROMRead: cpi temp1,9 brne NoDoEEPROMWrite rjmp DoEEPROMWrite data ;ENG;write to EEPROM to given address given data NoDoEEPROMWrite: cpi temp1,10 brne NoDoRS232Send rjmp DoRS232Send transmit byte to serial line NoDoRS232Send: cpi temp1,11 brne NoDoRS232Read rjmp DoRS232Read (ak sa nejaky prijal) ;ENG;returns received byte from serial line NoDoRS232Read: cpi temp1,12 brne NoDoSetRS232Baud rjmp DoSetRS232Baud linky ;ENG;set line speed of of serial line NoDoSetRS232Baud: cpi temp1,13 brne NoDoGetRS232Baud rjmp DoGetRS232Baud linky ;ENG;return line speed of serial line NoDoGetRS232Baud: cpi temp1,14 brne NoDoGetRS232Buffer rjmp DoGetRS232Buffer linky ;ENG;return line speed of serial line NoDoGetRS232Buffer: cpi temp1,15 brne NoDoSetRS232DataBits rjmp DoSetRS232DataBits linky ;ENG;set line speed of serial line NoDoSetRS232DataBits: cpi temp1,16 brne NoDoGetRS232DataBits rjmp DoGetRS232DataBits linky ;ENG;return line speed of serial line NoDoGetRS232DataBits: cpi temp1,17 brne NoDoSetRS232Parity rjmp DoSetRS232Parity linky ;ENG;set line speed of serial line NoDoSetRS232Parity: cpi temp1,18 brne NoDoGetRS232Parity rjmp DoGetRS232Parity linky ;ENG;return line speed of serial line NoDoGetRS232Parity: cpi temp1,19 brne NoDoSetRS232StopBits rjmp DoSetRS232StopBits linky ;ENG;set line speed of serial line NoDoSetRS232StopBits: cpi temp1,20 brne NoDoGetRS232StopBits rjmp DoGetRS232StopBits linky ;ENG;return line speed of serial line NoDoGetRS232StopBits: cpi brne rjmp
; ; ;restartne infra prijimanie (ak bolo
; ;vysle prijaty infra kod (ak je v
; ;nastavi smer toku datovych
; ;zisti smer toku datovych bitov ;ENG;
; ;nastavi datove bity (ak su vstupne,
; ;zisti nastavenie datovych out bitov
; ;vrati hodnotu datoveho vstupneho
; ;vrati obsah EEPROM od urcitej
; ;zapise EEPROM na urcitu adresu urcite
; ;vysle byte na seriovy linku
;ENG;
; ;vrati prijaty byte zo seriovej linky
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
; ;nastavi prenosovu rychlost seriovej
; ;vrati prenosovu rychlost seriovej
temp1,USER_FNC_NUMBER+0 NoDoUserFunction0 DoUserFunction0
;
NoDoUserFunction0: cpi brne rjmp
temp1,USER_FNC_NUMBER+1 NoDoUserFunction1 DoUserFunction1
;
NoDoUserFunction1: cpi brne rjmp
temp1,USER_FNC_NUMBER+2 NoDoUserFunction2 DoUserFunction2
;
;vykona uzivatelsku rutinu0
;ENG;
execute of user function0
;vykona uzivatelsku rutinu1
;ENG;
execute of user function1
;vykona uzivatelsku rutinu2
;ENG;
execute of user function1 NoDoUserFunction2:
nulovu odpoved
rjmp ZeroDATA1Answer ;ENG;if that it was something unknown, then prepare zero answer
;ak to bolo nieco nezname, tak priprav
;----------------------------- USER FUNCTIONS -------------------------------------;------------------------------TEMPLATE OF YOUR FUNCTION---------------------------;------------------ BEGIN: This is template how to write own function -------------;free of use are registers: ;temp0,temp1,temp2,temp3,ACC,ZH,ZL ;registers are destroyed after execution (use push/pop to save content) ;at the end of routine you must correctly set registers: ;RAMread - 0=reading from ROM, 1=reading from RAM, 2=reading from EEPROM ;temp0 - number of transmitted data bytes ;ZH,ZL - pointer to buffer of transmitted data (pointer to ROM/RAM/EEPROM) ;to transmit data (preparing data to buffer) : ;to transmit data you must jump to "ComposeEndXXXDescriptor" ;to transmit one zero byte you can jump to "OneZeroAnswer" (commonly used as confirmation of correct processing) ;to transmit two zero byte you can jump to "TwoZeroAnswer"
(commonly used as
confirmation of error in processing) ;for small size (up to 8 bytes) ansver use buffer AnswerArray (see function DoGetOutDataPort:) DoUserFunctionX: DoUserFunction0:
;send byte(s) of RAM starting at position given by first parameter in
function lds lds ;lds ;lds ;lds
temp0,InputBufferBegin+4 temp1,InputBufferBegin+5 temp2,InputBufferBegin+6 temp3,InputBufferBegin+7 ACC,InputBufferBegin+8
;first parameter Lo into temp0 ;first parameter Hi into temp1 ;second parameter Lo into temp2 ;second parameter Hi into temp3 ;number of requested bytes from USB
host (computer) into ACC ;Here add your own code: ;------------------------------------------------------------------nop ;example of code - nothing to do nop nop nop nop ;------------------------------------------------------------------mov ZL,temp0 ;will be sending value of RAM - from address stored in temp0 (first parameter Lo of function) mov ZH,temp1 ;will be sending value of RAM - from address stored in temp1 (first parameter Hi of function) inc RAMread ;RAMread=1 - reading from RAM ldi temp0,255 ;send max number of bytes - 255 bytes are maximum rjmp ComposeEndXXXDescriptor ;a prepare data DoUserFunction1: rjmp OneZeroAnswer ;only confirm receiving by one zero byte answer DoUserFunction2: rjmp TwoZeroAnswer ;only confirm receiving by two zero bytes answer ;------------------ END: This is template how to write own function ----------------
;----------------------------- USER FUNCTIONS -------------------------------------;-------------------------DoSetInfraBufferEmpty: rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-------------------------DoGetInfraCode:
http://avr-asm.tripod.com/usb232.html (2 of 4)1/20/2009 8:56:38 PM
16 BIT MATH (AVR 202)
rjmp
OneZeroAnswer
;potvrd prijem jednou nulou
acknowledge reception with single zero ;-------------------------DoSetDataPortDirection: lds temp1,InputBufferBegin+7 porty menit ;ENG;fourth parameter - bit mask - which port(s) to change
;ENG;
;stvrty parameter - bitova maska ktore
lds temp0,InputBufferBegin+4 DDRB ;ENG;first parameter - direction of data bits DDRB andi temp0,0b00111100 mask unused pins sbrc temp1,0 if bit0 is zero - don't change port state out DDRB,temp0 and update direction of data port
;prvy parameter - smer datovych bitov
lds DDRC ;ENG;second parameter - direction of data bits DDRC sbrc if bit1 is zero - don't change port state out and update direction of data port
temp0,InputBufferBegin+5
;druhy parameter - smer datovych bitov
temp1,1
;ak je bit1 nulovy - nemen port ;ENG;
DDRC,temp0
;a update smeru datoveho portu
;zamaskovat nepouzite piny
;ak je bit0 nulovy - nemen port ;ENG; ;a update smeru datoveho portu
lds temp0,InputBufferBegin+6 DDRD ;ENG;third parameter - direction of data bits DDRD andi temp0,0b11111000 mask unused pins ori temp0,0b00000010 mask unused pins sbrc temp1,2 if bit2 is zero - don't change port state out DDRD,temp0 and update direction of data port rjmp
;ENG;
;ENG;
;treti parameter - smer datovych bitov ;zamaskovat nepouzite piny
;ENG;
;zamaskovat nepouzite piny
;ENG;
;ak je bit2 nulovy - nemen port ;ENG;
OneZeroAnswer
acknowledge reception with single zero ;-------------------------DoGetDataPortDirection: in temp0,DDRB read direction of DDRB sts AnswerArray,temp0 AnswerArray in temp0,DDRC read direction of DDRC sts AnswerArray+1,temp0 AnswerArray in temp0,DDRD read direction of DDRD sts AnswerArray+2,temp0 AnswerArray ldi ZL,AnswerArray AnswerArray ;ENG;sending is value from AnswerArray ldi temp0,0x81 RAMREAD=1 - reading from RAM mov RAMread,temp0 premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,3 are three bytes rjmp ComposeEndXXXDescriptor ;-------------------------DoSetOutDataPort: lds temp1,InputBufferBegin+7 porty menit ;ENG;fourth parameter - bit mask - which port(s) to change
;a update smeru datoveho portu
;ENG;
;potvrd prijem jednou nulou
;ENG;
;nacitaj stav smeru DDRB
;ENG;
;do pola AnswerArray
;ENG;to array
;nacitaj stav smeru DDRC
;ENG;
;do pola AnswerArray
;ENG;to array
;nacitaj stav smeru DDRD
;ENG;
;do pola AnswerArray
;ENG;to array
;posiela sa hodnota z ;RAMread=1 - cita sa z RAM-ky
;ENG;
;(najvyssi bit na 1 - aby sa hned
;posielaju sa tri byty
;ENG;sending
;a priprav data ;ENG;and prepare data
;stvrty parameter - bitova maska ktore
lds temp0,InputBufferBegin+4 ;ENG;first parameter - value of data bits PORTB andi temp0,0b00111100
bitov PORTB
;ENG;
;prvy parameter - hodnota datovych ;zamaskovat nepouzite piny
;ENG;
mask unused pins sbrc
temp1,0
;ak je bit0 nulovy - nemen port ;ENG;
out
PORTB,temp0
;a update datoveho portu
if bit0 is zero - don't change port state ;ENG;
and update data port lds temp0,InputBufferBegin+5 bitov PORTC ;ENG;second parameter - value of data bits PORTC sbrc temp1,1 if bit1 is zero - don't change port state out PORTC,temp0 and update data port
;druhy parameter - hodnota datovych
lds temp0,InputBufferBegin+6 ;ENG;third parameter - value of data bits PORTD andi temp0,0b11111000
;treti parameter - hodnota datovych
bitov PORTD
;ak je bit1 nulovy - nemen port ;ENG; ;a update datoveho portu
;ENG;
;zamaskovat nepouzite piny
;ENG; ;ENG;
mask unused pins ori
temp0,0b00000011
;zamaskovat nepouzite piny
sbrc
temp1,2
;ak je bit2 nulovy - nemen port ;ENG;
out
PORTD,temp0
;a update datoveho portu
;ENG;
rjmp
OneZeroAnswer
;potvrd prijem jednou nulou
;ENG;
mask unused pins if bit2 is zero - don't change port state and update data port
acknowledge reception with single zero ;-------------------------DoGetOutDataPort: in temp0,PORTB ;nacitaj stav PORTB ;ENG;read PORTB sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PORTC ;nacitaj stav PORTC ;ENG;read PORTC sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PORTD ;nacitaj stav PORTD ;ENG;read PORTD sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray ldi ZL,AnswerArray ;posiela sa hodnota z AnswerArray ;ENG;sending is value from AnswerArray ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG; RAMREAD=1 - reading from RAM mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,3 ;posielaju sa tri byty ;ENG;sending are three bytes rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-------------------------DoGetInDataPort: in temp0,PINB ;nacitaj stav PINB ;ENG;read PINB sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PINC ;nacitaj stav PINC ;ENG;read PINC sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray in temp0,PIND ;nacitaj stav PIND ;ENG;read PIND sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array AnswerArray ldi ZL,AnswerArray ;posiela sa hodnota z AnswerArray ;ENG;sending is value from AnswerArray ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG; RAMREAD=1 - reading from RAM mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,3 ;posielaju sa tri byty ;ENG;sending are three bytes rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-----------------------------------------------------------------------------------------DoGetIn: ldi ZL,0 ;posiela sa hodnota v R0 ;ENG; sending value in R0 ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG; RAMread=1 - reading from RAM mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread immediatelly) ldi temp0,1 ;posli iba jeden byte ;ENG;send only single byte rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-----------------------------------------------------------------------------------------DoEEPROMRead: lds ZL,InputBufferBegin+4 ;prvy parameter - offset v EEPROMke ;ENG;first parameter - offset in EEPROM lds ZH,InputBufferBegin+5 ldi temp0,2 mov RAMread,temp0 ;RAMread=2 - cita sa z EEPROMky ;ENG;RAMREAD=2 - reading from EEPROM ldi temp0,E2END+1 ;pocet mojich bytovych odpovedi do temp0 - cela dlzka EEPROM ;ENG;number my byte answers to temp0 entire length of EEPROM rjmp ComposeEndXXXDescriptor ;inak priprav data ;ENG;otherwise prepare data ;-------------------------DoEEPROMWrite: lds ZL,InputBufferBegin+4 ;prvy parameter - offset v EEPROM-ke (adresa) ;ENG;first parameter - offset in EEPROM (address) lds ZH,InputBufferBegin+5 lds R0,InputBufferBegin+6 ;druhy parameter - data, ktore sa maju zapisat do EEPROM-ky (data) ;ENG;second parameter - data to store to EEPROM (data) out EEAR,ZL ;nastav adresu EEPROM ;ENG;set the address of EEPROM out EEARH,ZH out EEDR,R0 ;nastav data do EEPROM ;ENG;set the data to EEPROM cli ;zakaz prerusenie ;ENG;disable interrupt sbi EECR,EEMWE ;nastav master write enable ;ENG; set the master write enable sei ;povol prerusenie (este sa vykona nasledujuca instrukcia) ;ENG;enable interrupt (next instruction is performed) sbi EECR,EEWE ;samotny zapis ;ENG;write WaitForEEPROMReady: sbic EECR,EEWE ;pockaj si na koniec zapisu ;ENG; wait to the end of write rjmp WaitForEEPROMReady ;v slucke (max cca 4ms) (kvoli naslednemu citaniu/zapisu) ;ENG;in loop (max cca 4ms) (because of possible next reading/writing) rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-------------------------DoRS232Send: lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota vysielana na RS232 ;ENG;first parameter - value transmitted to RS232 out UDR,temp0 ;vysli data na UART ;ENG;transmit data to UART WaitForRS232Send: sbis UCR,TXEN ;ak nie je povoleny UART vysielac ;ENG;if disabled UART transmitter rjmp OneZeroAnswer ;tak skonci - ochrana kvoli zacykleniu v AT90S2323/2343 ;ENG;then finish - protection because loop lock in AT90S2323/2343 sbis USR,TXC ;pockat na dovysielanie bytu ;ENG; wait for transmition finish rjmp WaitForRS232Send rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-------------------------DoRS232Read: rjmp TwoZeroAnswer ;iba potvrd prijem dvoma nulami ;ENG; only acknowledge reception with two zero ;-------------------------DoSetRS232Baud: lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota baudrate na RS232 ;ENG;first parameter - value of baudrate of RS232 lds temp1,InputBufferBegin+6 ;druhy parameter - hodnota baudrate na RS232 - high byte ;ENG;second parameter - baudrate of RS232 - high byte cbr temp1,1<
temp0,0
;ak nie je RS232 Buffer prazdny ;ENG;
brne cpi
SomeRS232Send temp1,0
;tak ho posli ;ENG;then send it ;ak nie je RS232 Buffer prazdny ;ENG;
if this isn't RS232 Buffer empty
if this isn't RS232 Buffer empty brne SomeRS232Send rjmp OneZeroAnswer jednou nulou ;ENG;otherwise nothing send and acknowledge reception with single zero SomeRS232Send: lds ACC,InputBufferBegin+8 ACC ;ENG;number of requiring bytes to ACC ldi temp2,2 word dlzky buffera) ;ENG;number of possible bytes (plus word of buffer length) add temp0,temp2 ldi temp2,0 adc temp1,temp2 cpi temp1,0 brne AsRequiredGetRS232Buffer transmit as many as requested cp ACC,temp0 dodat ;ENG;if no requested more that I can send brcc NoShortGetRS232Buffer transmit as many as requested AsRequiredGetRS232Buffer: mov temp0,ACC ldi temp1,0 NoShortGetRS232Buffer: subi temp0,2 word length sbci temp1,0 lds temp2,RS232ReadPosPtr RS232 kodu ;ENG;obtain index of reading of buffer of RS232 code lds temp3,RS232ReadPosPtr+1 add temp2,temp0 where is end adc temp3,temp1 cpi temp3,HIGH(RS232BufferEnd+1) would overflow brlo ReadNoOverflow brne ReadOverflow if yes - skip to overflow cpi
;tak ho posli ;ENG;then send it ;inak nic neposli a potvrd prijem
;pocet pozadovanych bytov do ;pocet moznych dodanych bajtov (plus
;ak je MSB>0 ;ENG;if is MSB>0 ;vysli tolko kolko sa ziada ;ENG; ;ak sa neziada viac ako mozem ;vysli tolko kolko sa ziada
;uber word dlzky
;ENG;
;ENG;substract
;zisti ukazovatel citania buffera
;zisti kde je koniec
;ENG;obtain
;ci by mal pretiect
;ENG;if it
; ;ak ano - skoc na pretecenie
;ENG;
temp2,LOW(RS232BufferEnd+1)
;inak porovnaj LSB
;ENG;otherwise
ReadNoOverflow
;a urob to iste ;ENG;and do the same
temp2,LOW(RS232BufferEnd+1)
;vypocitaj kolko sa neprenesie
;ENG;
sbci
temp3,HIGH(RS232BufferEnd+1)
;vypocitaj kolko sa neprenesie
;ENG;
sub
temp0,temp2
;a o to skrat dlzku citania
;ENG;
sbc
temp1,temp3
;a o to skrat dlzku citania
;ENG;
ldi
temp2,LOW(RS232FIFOBegin)
;a zacni od nuly
;ENG;and start
ldi
temp3,HIGH(RS232FIFOBegin)
;a zacni od nuly
;ENG;and start
compare LSB brlo ReadOverflow: subi caculate how many not transfered caculate how many not transfered and with this short length of reading and with this short length of reading from zero from zero
RS232 kodu
ReadNoOverflow: lds ZL,RS232ReadPosPtr ;ENG;obtain index of reading of buffer of RS232 code lds ZH,RS232ReadPosPtr+1 ;ENG;obtain index of reading of buffer of RS232 code
RS232 kodu
;zisti ukazovatel citania buffera
sts RS232ReadPosPtr,temp2 ;ENG;write new index of reading of buffer of RS232 code sts RS232ReadPosPtr+1,temp3 ;ENG;write new index of reading of buffer of RS232 code sbiw ZL,2 ;ENG;space for length data - transmitted as first word
RS232 kodu
RS232 kodu
ako prvy word
cbi UART ;ENG;disable interrupt from UART receiving inc RAMread=1 reading from RAM lds lds kodu ;ENG;obtain buffer length of RS232 code sub buffer length sbc sts kodu ;ENG;write new buffer length of RS232 code sts sbi UART ;ENG;enable interrupt from UART receiving
paketu
;zisti ukazovatel citania buffera
;zapis novy ukazovatel citania buffera
;zapis novy ukazovatel citania buffera
;priestor pre udaj dlzky - prenasa sa
UCR,RXCIE
;zakazat interrupt od prijimania
RAMread
;RAMread=1 - cita sa z RAM-ky
temp2,RS232LengthPosPtr temp3,RS232LengthPosPtr+1
;zisti dlzku buffera RS232
temp2,temp0
;zniz dlzku buffera
temp3,temp1 RS232LengthPosPtr,temp2
;zapis novu dlzku buffera RS232
RS232LengthPosPtr+1,temp3 UCR,RXCIE
;povolit interrupt od prijimania
st
Z+,temp2
;a uloz skutocnu dlzku do
st
Z,temp3
;a uloz skutocnu dlzku do
sbiw
ZL,1
;a nastav sa na zaciatok
;ENG;
;ENG;decrement
paketu
;ENG;and save real length to packet ;ENG;and save real length to packet ;ENG;
and set to begin inc temp0 ;a o tento jeden word zvys pocet prenasanych bajtov (dlzka buffer) ;ENG;and about this word increment number of transmited bytes (buffer length) inc temp0 rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data ;-----------------------------------------------------------------------------------------DoSetRS232DataBits: lds temp0,InputBufferBegin+4 ;prvy parameter - data bits 0=5db, 1=6db, 2=7db, 3=8db ;ENG;first parameter - data bits 0=5db, 1=6db, 2=7db, 3=8db cpi temp0,DataBits8 ;ak sa ma nastavit 8-bitova komunikacia ;ENG;if to set 8-bits communication breq Databits8or9Set ;tak nemen 8/9 bitovu komunikaciu ;ENG;then don't change 8/9 bit communication in temp1,UCSRB ;inak nacitaj UCSRB ;ENG;otherwise load UCSRB cbr temp1,(1<
temp0,3
;nastav 9-databit
;ENG;set the 9-
rcall
RS232DataBitsLocal
;a sucasne vrat v temp1 obsah
cbr rcall rjmp
temp1,(1<
;zakaz paritu
databit UCSRC
;ENG;and return in temp1 contents UCSRC ;ENG;disable parity
;potvrd prijem jednou nulou
;ENG;
acknowledge reception with single zero ParityErrorAnswer: rjmp TwoZeroAnswer ;potvrd prijem dvoma nulami ;ENG; acknowledge reception with two zero ;-----------------------------------------------------------------------------------------DoGetRS232Parity: in temp1,UCSRB ;nacitaj UCSRB ;ENG;load UCSRB sbrc temp1,UCSZ2 ;ak je 9-bitova komunikacia ;ENG; if is 9-bits communication rjmp ParityIsStable ;tak je parita space alebo mark ;ENG; then parity is space or mark
bity
rcall cbr
GetUCSRCtotemp1 temp1,~((1<
;a nechaj nenulove iba paritne
cpi
temp1,(1<
;ak su obidva nastavene ;ENG;if are
ldi
temp0,ParityOdd
;je to odd parita
breq cpi
RetGetParity temp1,(1<
;a skonci ;ENG;and finish ;ak je nastaveny UPM1 ;ENG;if is
ldi
temp0,ParityEven
;je to even parita
breq ldi
RetGetParity temp0,ParityNone
;a skonci ;ENG;and finish ;inak je to none parita ;ENG;otherwise
RetGetParity
;a skonci
temp1,TXB8
;zisti ake je 9.-ty bit ;ENG;obtain
ldi
temp0,ParityMark
;priprav si mark odpoved
;ENG;
brts
RetGetParity
;ak je 1 potom vrat mark
;ENG;
ldi
temp0,ParitySpace
;inak vrat space
R0,temp0
;odpoved daj z temp0 do R0
;ENG;and let nonzero only parity bits
both set ;ENG;this is
odd parity
UPM1 set ;ENG;this is
even parity
is that none parity rjmp ParityIsStable: bst
;ENG;and finish
what is 9-th bit prepare mark answer if is 1 then return mark ;ENG;otherwise
return space RetGetParity: mov
;ENG;
answer move from temp0 to R0 rjmp DoGetIn ;a ukonci ;ENG;and finish ;-----------------------------------------------------------------------------------------DoSetRS232StopBits: lds temp0,InputBufferBegin+4 ;prvy parameter - stop bits 0=1stopbit 1=2stopbits ;ENG;first parameter - stop bit 0=1stopbit 1=2stopbits rcall GetUCSRCtotemp1 bst temp0,0 ;a najnizsi bit z parametra ;ENG; and lowest bit from parameter bld temp1,USBS ;uloz ako stopbit ;ENG;save as stopbit rcall Settemp1toUCSRC rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG; acknowledge reception with single zero ;-----------------------------------------------------------------------------------------DoGetRS232StopBits: rcall GetUCSRCtotemp1 clr R0 ;znuluj odpoved ;ENG;clear answer bst temp1,USBS ;a bit USBS ;ENG;and bit USBS bld R0,0 ;zapis do odpovede ;ENG;write to answer rjmp DoGetIn ;a ukonci ;ENG;and finish ;-----------------------------------------------------------------------------------------;----------------------------- END USER FUNCTIONS ------------------------------------END USER FUNCTIONS -----------------------------OneZeroAnswer: ;posle jednu nulu ;ENG;send single zero ldi temp0,1 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeGET_STATUS2 ;----------------------------- STANDARD USB REQUESTS ---------------------------------STANDARD USB REQUESTS -----------------------------StandardRequest: cpi temp1,GET_STATUS ; breq ComposeGET_STATUS ; cpi breq
temp1,CLEAR_FEATURE ComposeCLEAR_FEATURE
; ;
cpi breq
temp1,SET_FEATURE ComposeSET_FEATURE
; ;
cpi
temp1,SET_ADDRESS
;ak sa ma nastavit adresa
breq
ComposeSET_ADDRESS
;nastav adresu
cpi
temp1,GET_DESCRIPTOR
;ak sa ziada descriptor ;ENG;if
breq
ComposeGET_DESCRIPTOR
;vygeneruj ho
cpi breq
temp1,SET_DESCRIPTOR ComposeSET_DESCRIPTOR
; ;
cpi breq
temp1,GET_CONFIGURATION ComposeGET_CONFIGURATION
; ;
cpi breq
temp1,SET_CONFIGURATION ComposeSET_CONFIGURATION
; ;
cpi breq
temp1,GET_INTERFACE ComposeGET_INTERFACE
; ;
cpi breq
temp1,SET_INTERFACE ComposeSET_INTERFACE
; ;
cpi breq
temp1,SYNCH_FRAME ComposeSYNCH_FRAME
; ; ;ak sa nenasla znama poziadavka ;ENG;
;ENG;
if to set address ;ENG;set the address
requested descriptor ;ENG;generate it
if not found known request nulovu odpoved
rjmp ZeroDATA1Answer ;ENG;if that was something unknown, then prepare zero answer
;ak to bolo nieco nezname, tak priprav
MyUpdatedAddress
ComposeSET_ADDRESS: lds MyUpdatedAddress,InputBufferBegin+4 ;nova adresa do ;ENG;new address to MyUpdatedAddress rjmp ZeroDATA1Answer ;posli nulovu odpoved ;ENG;send zero
answer
ConfigByte
ComposeSET_CONFIGURATION: lds temp0,InputBufferBegin+4 ;ENG;number of configuration to variable ConfigByte sts ConfigByte,temp0 ComposeCLEAR_FEATURE: ComposeSET_FEATURE: ComposeSET_INTERFACE: ZeroStringAnswer: rjmp ZeroDATA1Answer
;cislo konfiguracie do premennej ;
;posli nulovu odpoved
;ENG;send zero
answer ComposeGET_STATUS: TwoZeroAnswer: ldi temp0,2 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 ComposeGET_STATUS2: ldi ZH, high(StatusAnswer<<1) ;ROMpointer na odpoved ;ENG; ROMpointer to answer ldi ZL, low(StatusAnswer<<1) rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeGET_CONFIGURATION: lds temp0,ConfigByte and temp0,temp0 ;ak som nenakonfigurovany ;ENG; if I am unconfigured breq OneZeroAnswer ;tak posli jednu nulu - inak posli moju konfiguraciu ;ENG;then send single zero - otherwise send my configuration ldi temp0,1 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 ldi ZH, high(ConfigAnswerMinus1<<1) ;ROMpointer na odpoved ;ENG; ROMpointer to answer ldi ZL, low(ConfigAnswerMinus1<<1)+1 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeGET_INTERFACE: ldi ZH, high(InterfaceAnswer<<1) ;ROMpointer na odpoved ;ENG; ROMpointer to answer ldi ZL, low(InterfaceAnswer<<1) ldi temp0,1 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeSYNCH_FRAME: ComposeSET_DESCRIPTOR: rcall ComposeSTALL ret ComposeGET_DESCRIPTOR: lds temp1,InputBufferBegin+5 ;DescriptorType do temp1 ;ENG; DescriptorType to temp1 cpi temp1,DEVICE ;DeviceDescriptor ;ENG; DeviceDescriptor breq ComposeDeviceDescriptor ; cpi temp1,CONFIGURATION ;ConfigurationDescriptor ;ENG; ConfigurationDescriptor breq ComposeConfigDescriptor ; cpi temp1,STRING ;StringDeviceDescriptor ;ENG; StringDeviceDescriptor breq ComposeStringDescriptor ; ret ComposeDeviceDescriptor: ldi ZH, high(DeviceDescriptor<<1) ;ROMpointer na descriptor ;ENG; ROMpointer to descriptor ldi ZL, low(DeviceDescriptor<<1) ldi temp0,0x12 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeConfigDescriptor: ldi ZH, high(ConfigDescriptor<<1) ;ROMpointer na descriptor ;ENG; ROMpointer to descriptor ldi ZL, low(ConfigDescriptor<<1) ldi temp0,9+9+7 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 ComposeEndXXXDescriptor: lds TotalBytesToSend,InputBufferBegin+8 ;pocet pozadovanych bytov do TotalBytesToSend ;ENG;number of requested bytes to TotalBytesToSend cp TotalBytesToSend,temp0 ;ak sa neziada viac ako mozem dodat ;ENG;if not requested more than I can send brcs HostConfigLength ;vysli tolko kolko sa ziada ;ENG; transmit the requested number mov TotalBytesToSend,temp0 ;inak posli pocet mojich odpovedi ;ENG;otherwise send number of my answers HostConfigLength: mov temp0,TotalBytesToSend ; clr TransmitPart ;nuluj pocet 8 bytovych odpovedi ;ENG;zero the number of 8 bytes answers andi temp0,0b00000111 ;ak je dlzka delitelna 8-mimi ;ENG; if is length divisible by 8 breq Length8Multiply ;tak nezapocitaj jednu necelu odpoved (pod 8 bytov) ;ENG;then not count one answer (under 8 byte) inc TransmitPart ;inak ju zapocitaj ;ENG;otherwise count it Length8Multiply: mov temp0,TotalBytesToSend ; lsr temp0 ;dlzka 8 bytovych odpovedi sa dosiahne ;ENG;length of 8 bytes answers will reach lsr temp0 ;delenie celociselne 8-mimi ;ENG; integer division by 8 lsr temp0 add TransmitPart,temp0 ;a pripocitanim k poslednej necelej 8mici do premennej TransmitPart ;ENG;and by addition to last non entire 8-bytes to variable TransmitPart ldi temp0,DATA0PID ;DATA0 PID - v skutocnosti sa stoggluje na DATA1PID v nahrati deskriptora ;ENG;DATA0 PID - in the next will be toggled to DATA1PID in load descriptor sts OutputBufferBegin+1,temp0 ;nahraj do vyst buffera ;ENG;store to output buffer rjmp ComposeNextAnswerPart ComposeStringDescriptor: ldi temp1,4+8 ;ak RAMread=4(vkladaj nuly z ROMkoveho citania) + 8(za prvy byte nevkldadaj nulu) ;ENG;if RAMread=4(insert zeros from ROM reading) + 8(behind first byte no load zero) mov RAMread,temp1 lds temp1,InputBufferBegin+4 ;DescriptorIndex do temp1 ;ENG; DescriptorIndex to temp1 cpi temp1,0 ;LANGID String ;ENG;LANGID String breq ComposeLangIDString ; cpi temp1,2 ;DevNameString ;ENG;DevNameString breq ComposeDevNameString ; brcc ZeroStringAnswer ;ak je DescriptorIndex vyssi nez 2 posli nulovu odpoved ;ENG;if is DescriptorIndex higher than 2 - send zero answer ;inak to bude VendorString ;ENG; otherwise is VendorString ComposeVendorString: ldi ZH, high(VendorStringDescriptor<<1) ;ROMpointer na descriptor ;ENG;ROMpointer to descriptor ldi ZL, low(VendorStringDescriptor<<1) ldi temp0,(VendorStringDescriptorEnd-VendorStringDescriptor)*4-2 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeDevNameString: ldi ZH, high(DevNameStringDescriptor<<1) ;ROMpointer na descriptor ;ENG;ROMpointer to descriptor ldi ZL, low(DevNameStringDescriptor<<1) ldi temp0,(DevNameStringDescriptorEnd-DevNameStringDescriptor)*4-2 ;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ComposeLangIDString: clr RAMread ldi ZH, high(LangIDStringDescriptor<<1) ;ROMpointer na descriptor ;ENG;ROMpointer to descriptor ldi ZL, low(LangIDStringDescriptor<<1) ldi temp0,(LangIDStringDescriptorEnd-LangIDStringDescriptor)*2;pocet mojich bytovych odpovedi do temp0 ;ENG;number of my bytes answers to temp0 rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete ;-----------------------------------------------------------------------------------------ZeroDATA1Answer: rcall ComposeZeroDATA1PIDAnswer ret ;----------------------------- END positionARD USB REQUESTS ------------------------------------- END DATA ENCRYPTION USB REQUESTS -----------------------------PrepareOutContinuousBuffer: rcall PrepareContinuousBuffer rcall MakeOutBitStuff ret ;-----------------------------------------------------------------------------------------PrepareContinuousBuffer: mov temp0,TransmitPart cpi temp0,1 brne NextAnswerInBuffer ;ak uz je buffer prazdny ;ENG; if buffer empty rcall
ComposeZeroAnswer
;priprav nulovu odpoved ;ENG;prepare
zero answer ret NextAnswerInBuffer: dec TransmitPart
;znizit celkovu dlzku odpovede
;ENG;
decrement general length of answer ComposeNextAnswerPart: mov temp1,TotalBytesToSend
;zniz pocet bytov na vyslanie
;ENG;decrement
number of bytes to transmit subi temp1,8 ;ci je este treba poslat viac ako 8 bytov ;ENG;is is necessary to send more as 8 byte ldi temp3,8 ;ak ano - posli iba 8 bytov ;ENG;if yes send only 8 byte brcc Nad8Bytov mov temp3,TotalBytesToSend ;inak posli iba dany pocet bytov ;ENG; otherwise send only given number of bytes clr TransmitPart inc TransmitPart ;a bude to posledna odpoved ;ENG;and this will be last answer Nad8Bytov: mov TotalBytesToSend,temp1 ;znizeny pocet bytov do TotalBytesToSend ;ENG;decremented number of bytes to TotalBytesToSend rcall LoadXXXDescriptor ldi ByteCount,2 ;dlzka vystupneho buffera (iba SOP a PID) ;ENG;length of output buffer (only SOP and PID) add ByteCount,temp3 ;+ pocet bytov ;ENG;+ number of bytes rcall AddCRCOut ;pridanie CRC do buffera ;ENG;addition of CRC to buffer inc ByteCount ;dlzka vystupneho buffera + CRC16 ;ENG; length of output buffer + CRC16 inc ByteCount ret ;skonci ;ENG;finish ;-----------------------------------------------------------------------------------------.equ USBversion =0x0100 ;pre aku verziu USB je to (1.00) ;ENG;for what version USB is that (1.00) .equ VendorUSBID =0x03EB ;identifikator dodavatela (Atmel=0x03EB) ;ENG; vendor identifier (Atmel=0x03EB) .equ DeviceUSBID =0x0004 ;identifikator vyrobku (USB to RS232 converter ATmega8=0x0004) ;ENG;product identifier (USB to RS232 converter ATmega8=0x0004) .equ DeviceVersion =0x0003 ;cislo verzie vyrobku (verzia=0.03) ;ENG;version number of product (version=0.03) ;(0.01=AT90S2313 Infra buffer) ;ENG; (0.01=AT90S2313 Infra buffer) ;(0.02=AT90S2313 RS232 buffer 32bytes) ;ENG; (0.02=AT90S2313 RS232 buffer 32bytes) ;(0.03=ATmega8 RS232 buffer 800bytes) ;ENG; (0.03=ATmega8 RS232 buffer 800bytes) .equ MaxUSBCurrent =50 ;prudovy odber z USB (50mA) - rezerva na MAX232 ;ENG;current consumption from USB (50mA) - together with MAX232 ;-----------------------------------------------------------------------------------------DeviceDescriptor: .db 0x12,0x01 ;0 byte - velkost deskriptora v bytoch ;ENG;0 byte - size of descriptor in byte ;1 byte - typ deskriptora: Deskriptor zariadenia ;ENG;1 byte - descriptor type: Device descriptor .dw USBversion ;2,3 byte - verzia USB LSB (1.00) ; ENG;2,3 byte - version USB LSB (1.00) .db 0x00,0x00 ;4 byte - trieda zariadenia ;ENG;4 byte device class ;5 byte - podtrieda zariadenia ;ENG;5 byte subclass .db 0x00,0x08 ;6 byte - kod protokolu ;ENG;6 byte - protocol code ;7 byte - velkost FIFO v bytoch ;ENG;7 byte FIFO size in bytes .dw VendorUSBID ;8,9 byte - identifikator dodavatela (Cypress=0x04B4) ;ENG;8,9 byte - vendor identifier (Cypress=0x04B4) .dw DeviceUSBID ;10,11 byte - identifikator vyrobku (teplomer=0x0002) ;ENG;10,11 byte - product identifier (teplomer=0x0002) .dw DeviceVersion ;12,13 byte - cislo verzie vyrobku (verzia=0.01) ;ENG;12,13 byte - product version number (verzia=0.01) .db 0x01,0x02 ;14 byte - index stringu "vyrobca" ; ENG;14 byte - index of string "vendor" ;15 byte - index stringu "vyrobok" ; ENG;15 byte - index of string "product" .db 0x00,0x01 ;16 byte - index stringu "seriove cislo" ;ENG;16 byte - index of string "serial number" ;17 byte - pocet moznych konfiguracii ; ENG;17 byte - number of possible configurations DeviceDescriptorEnd: ;-----------------------------------------------------------------------------------------ConfigDescriptor: .db 0x9,0x02 ;dlzka,typ deskriptoru ;ENG;length, descriptor type ConfigDescriptorLength: .dw 9+9+7 ;celkova dlzka vsetkych deskriptorov ;ENG; entire length of all descriptors ConfigAnswerMinus1: ;pre poslanie cisla congiguration number (pozor je treba este pricitat 1) ;ENG;for sending the number - congiguration number (attention - addition of 1 required) .db 1,1 ;numInterfaces,congiguration number ;ENG; numInterfaces, congiguration number .db 0,0x80 ;popisny index stringu, atributy;bus powered ;ENG;string index, attributes; bus powered .db MaxUSBCurrent/2,0x09 ;prudovy odber, interface descriptor length ;ENG;current consumption, interface descriptor length .db 0x04,0 ;interface descriptor; cislo interface ;ENG; interface descriptor; number of interface InterfaceAnswer: ;pre poslanie cisla alternativneho interface ;ENG;for sending number of alternatively interface .db 0,1 ;alternativne nastavenie interface; pocet koncovych bodov okrem EP0 ;ENG;alternatively interface; number of endpoints except EP0 StatusAnswer: ;2 nulove odpovede (na usetrenie miestom) ;ENG;2 zero answers (saving ROM place) .db 0,0 ;trieda rozhrania; podtrieda rozhrania ;ENG; interface class; interface subclass .db 0,0 ;kod protokolu; index popisneho stringu ;ENG; protocol code; string index .db 0x07,0x5 ;dlzka,typ deskriptoru - endpoint ;ENG; length, descriptor type - endpoint .db 0x81,0 ;endpoint address; transfer type ;ENG; endpoint address; transfer type .dw 0x08 ;max packet size ;ENG;max packet size .db 10,0 ;polling interval [ms]; dummy byte (pre vyplnenie) ;ENG;polling interval [ms]; dummy byte (for filling) ConfigDescriptorEnd: ;-----------------------------------------------------------------------------------------LangIDStringDescriptor: .db (LangIDStringDescriptorEnd-LangIDStringDescriptor)*2,3 ;dlzka, typ: string deskriptor ;ENG;length, type: string descriptor .dw 0x0409 ;English ;ENG;English LangIDStringDescriptorEnd: ;-----------------------------------------------------------------------------------------VendorStringDescriptor: .db (VendorStringDescriptorEnd-VendorStringDescriptor)*4-2,3 ; dlzka, typ: string deskriptor ;ENG;length, type: string descriptor CopyRight: .db "Ing. Igor Cesko, Copyright(c) 2003" CopyRightEnd: VendorStringDescriptorEnd: ;-----------------------------------------------------------------------------------------DevNameStringDescriptor: .db (DevNameStringDescriptorEnd-DevNameStringDescriptor)*4-2,3;dlzka, typ: string deskriptor ;ENG;length, type: string descriptor .db "Igor Atmel-AVR device: Advanced USB to RS232 converter + I/O pins control + EEPROM scratch pad" DevNameStringDescriptorEnd: ;-----------------------------------------------------------------------------------------;******************************************************************** ;* End of Program ;ENG;* End of program ;******************************************************************** ;-----------------------------------------------------------------------------------------;******************************************************************** ;* EEPROM contents ;ENG;* EEPROM contents ;******************************************************************** ;-----------------------------------------------------------------------------------------.eseg ;data v EEPROM-ke (vo finalnej verzii zapoznamkovat) ;ENG;data in EEPROM (at final version comment) ;.org 0x400 ;pre naplnenie EEPROM dat na spravne adresy - hned za kod programu (vo finalnej verzii odpoznamkovat) ;ENG;.org 0x400 ;for filling EEPROM give on right addresses - behind the program code (at final version uncomment) EEData: .db "This device was developed by Ing. Igor Cesko: [email protected] " .db "For more information see: http://www.cesko.host.sk. " .db "S/N:00000001" ;-----------------------------------------------------------------------------------------;******************************************************************** ;* End of file ;ENG;* End of file ;********************************************************************
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16 BIT MATH (AVR 202)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/ stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
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16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ISP PROTOCOL HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* Title : AVR ISP (Auto adr inc, 19200bps) ;* Version : 2.0 ;* Last updated : 1998.01.06 (mlund) ;* Target : AT90S1200 ;* File : ispprog.asm ;* Author : Atmel Norway ;* ;* DESCRIPTION ;* The firmware on all programmers now support a unified protocol for ;* program and data memory programming. The host computer do not need ;* to know if the programmer operates in serial or parallel mode. ;* ;* The following commands are supported. All commands start with a ;* single letter. The programmer returns 13d (carriage return) or the ;* data read after the command is finished. ;* ;* +------------+------------+------+ ;* Commands | Host writes | Host reads | | ;* -------+-----+------+------+-----+ | ;* | ID | data | data | | Note | ;* +-----------------------------------+-----+------+------+-----+------+ ;* | Enter programming mode | 'P' | | | 13d | 1 | ;* | Set address | 'A' | ah al | | 13d | 2 | ;* | Write program memory, low byte | 'c' | dd | | 13d | 3 | ;* | Write program memory, high byte | 'C' | dd | | 13d | 3 | ;* | Issue Page Write | 'm' | | | 13d | | ;* | Read program memory | 'R' | |dd (dd)| | 4 | ;* | Write data memory | 'D' | dd | | 13d | | ;* | Read data memory | 'd' | | dd | | | ;* | Chip erase | 'e' | | | 13d | | ;* | Write lock bits | 'l' | dd | | 13d | | ;* | Write fuse bits | 'f' | dd | | 13d | 11 | ;* | Read fuse and lock bits | 'F' | | dd | | 11 | ;* | Leave programming mode | 'L' | | | 13d | 5 | ;* | Select device type | 'T' | dd | | 13d | 6 | ;* | Read signature bytes | 's' | | 3*dd | | | ;* | Return supported device codes | 't' | | n*dd | 00d | 7 | ;* | Return software identifier | 'S' | | s [7] | | 8 | ;* | Return sofware version | 'V' | | dd dd | | 9 | ;* | Return hardware version | 'v' | | dd dd | | 9 | ;* | Return programmer type | 'p' | | dd | | 10 | ;* | Set LED | 'x' | dd | | 13d | 12 | ;* | Clear LED | 'y' | dd | | 13d | 12 | ;* | Universial command | ':' | 3*dd | dd | 13d | | ;* +-----------------------------------+-----+------+------+-----+------+ ;* ;* NOTE 1 ;* The Enter programming mode command MUST be sent one time prior to ;* the other commands, with the exception of the 't', 'S', 'V', 'v' ;* and 'T' commands. The 'T' command must be sent before this command ;* (see note 6). ;* ;* For programmers supporting both parallel and serial programming ;* mode this command enters parallel programming mode. For programmers ;* supporting only serial programming mode, this command enters serial ;* programming mode. ;* ;* NOTE 2 ;* The ah and al are the high and low order bytes of the address. For ;* parallel programmers this command issues the Load Address Low/High ;* Byte command. For serial programmers the address byte is stored for ;* use by the Read/Write commands. ;* ;* NOTE 3 ;* For parallel programmers this command issues the Program Flash ;* command. For serial programmers this command iussues the Write ;* Program Memory Command. For devices with byte-wide program memories ;* only the low byte command should be used. ;* ;* NOTE 4 ;* The contents of the program memory at the address given by the 'A' ;* command are written to the serial port in binary form. For byte ;* wide memories one byte is written. For 16 bit memories two bytes ;* are written,MSB first. ;* ;* NOTE 5 ;* This command must be executed after the programming is finished. ;* ;* NOTE 6 ;* The select device type command must be sent before the enter ;* programming command ;* ;* NOTE 7 ;* The supported device codes are returned in binary form terminated ;* by 0x00. ;* ;* NOTE 8 ;* This return a 7 character ASCII string identifying the programmer. ;* For the in-system programmer it is "AVR ISP". ;* ;* NOTE 9 ;* The software/hardware version are returned as two ASCII numbers. ;* ;* NOTE 10 ;* This command should be used to identify the programmer type. The ;* return value is 'S' for serial (or SPI) programmers or 'P' for ;* parallel programmers. ;* ;* NOTE 11 ;* The write fuse bits command are available only on parallel ;* programmers and only for AVR devices (device code < 0x80). The host ;* should use the return programmer type command to determine the ;* programmer type, do not use the "AVR PPR" idenifier because other ;* programmers may be available in the future. ;* ;* NOTE 12 ;* Currently only the AVR development board has LEDs. The other boards ;* must implement this commands as NOPs. ;* ;* NOTE 13 ;* Devices using Page Mode Programming write one page of flash memory ;* before issuing a Page Mode Write Pulse. ; *************************************************************************** ;**** includes **** .include "1200def.inc" ; *************************************************************************** ;* ;* CONSTANTS ;* device codes ;* ;* DESCRIPTION ;* The following device codes must be used by the host computer. Note ;* that the device codes are arbitrary selected, they do not have any ;* thing in common with the signature bytes stored in the device. ;* ;* The following devices are supported (make a new table for each ;* software release): ;* ;* SW_MAJOR=1, SW_MINOR=5 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ;* SW_MAJOR=1, SW_MINOR=6 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ATmega103 rev. A (abbreviated S01838A) ;* ; *************************************************************************** .equ .equ .equ .equ .equ .equ .equ
S1200C S1200D S2313A S4414A S8515A S8252 S2323A
= = = = = = =
0x12 0x13 0x20 0x28 0x38 0x86 0x48
.equ .equ
S01838C = 0x40 S01838D = 0x41
;**** Revision Codes **** .equ
SW_MAJOR = 2
; Major SW revision
.equ
SW_MINOR = 0
; Minor SW revision
.equ
HW_MAJOR = 1
; Major HW revision
.equ
HW_MINOR = 0
; Minor HW revision
number number number number
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following four macros if the RESET pin to the ;* target moves and/or if the SCK/MISO/MOSO moves. ;* ; *************************************************************************** .macro sbi .endm
set_reset portb,4
.macro cbi .endm
clr_reset portb,4
.macro nop ; sbi .endm
ddrd_init
.macro ldi out
ddrb_init temp1,0xdf ddrb,temp1
ddrd,3
; PB5 is input, the rest is
output .endm .macro ldi brlo tst brmi s0b: ldi s1: rcall == 0x53)
ddrb_release temp1,(1<= 0x20) && (device <= 0x7F) ) s2 device s2 ; { count,32 ; count = 32; ; do { rdser ; if (rdser
// SPI read (byte 3) cpi breq
s_data,0x53 s3
;
ldi
s_data,0x00
;
wrser
rcall wrser pulse_sck ldi s_data,0xac
; ;
pulse SCK wrser
rcall ldi
wrser s_data,0x53
;
wrser
rcall dec brne rjmp
wrser count s1 s3
ldi
s_data,0x00
rcall
wrser
cpi breq ldi
device,S8252 s4 s_data,0x00
rcall
wrser
break; (0x00);
(0xac);
// SPI write (byte 4)
(0x53);
// SPI write (byte 1)
// SPI write (byte 2) } while(--count);
; } ; else ; { ;
wrser
s2:
;
(0x00);
// SPI write (byte 3) s3:
; } ; if (device != S8252) ; { ; wrser(0x00);
//
SPI write (byte 4) s4: ldi rcall ret
temp1,0x10 delay
; } ; delay(0x10);
; *************************************************************************** ;* ;* FUNCTION ;* show_id ;* ;* DESCRIPTION ;* Show our ID ("AVR ISP") on the serial line. ;* ; *************************************************************************** show_id:ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ret
u_data,0x41 putc u_data,0x56 putc u_data,0x52 putc u_data,0x20 putc u_data,0x49 putc u_data,0x53 putc u_data,0x50 putc
; 'A' ; 'V' ; 'R' ; ' ' ; 'I' ; 'S' ; 'P'
; *************************************************************************** ;* ;* RESET ;* ;* DESCRIPTION ;* Initialization ;* ; *************************************************************************** RESET: clr temp1 out GIMSK,temp1 ser temp1 out PORTD,temp1 set_reset out PORTB,temp1 ddrb_release rcall u_init sei
; disable external interrupt ; Initialize ; set RESET=1
; Initialize UART ; Enable interrupts
; *************************************************************************** ;* ;* PROGRAM ;* waitcmd -> main ;* ;* DESCRIPTION ;* Wait for and execute commands. ;* ; *************************************************************************** waitcmd:rcall
getc
; while (getc() ==
ESC) {}; cpi breq
u_data,0x1b waitcmd
;**** Device Type **** cpi brne rcall mov rjmp
u_data,0x54 w0 getc device,u_data put_ret
; 'T' Device type ; getc(); // dummy ; putc(device);
;**** Return Software Identifier **** w0: cpi
u_data,0x53
; 'S' Return software
w1 show_id waitcmd
; show_id();
identifier brne rcall rjmp
;**** Return Software Version **** w1: cpi brne ldi rcall ldi rcall rjmp
u_data,0x56 ;'V' Return software version w2 u_data,0x30+SW_MAJOR ; putc(0x30+SW_MAJOR); putc u_data,0x30+SW_MINOR ; putc(0x30+SW_MINOR); putc waitcmd
;**** Return Hardware Version **** w2: cpi brne ldi rcall ldi rcall rjmp
u_data,0x76 ;'v' Return hardware version w3 u_data,0x30+HW_MAJOR ; putc(0x30+HW_MAJOR); putc u_data,0x30+HW_MINOR ; putc(0x30+HW_MINOR); putc waitcmd
;**** Show Supported Devices **** w3: cpi brne ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi
u_data,0x74 w4 u_data,S1200C putc u_data,S1200D putc u_data,S2313A putc u_data,S4414A putc u_data,S8515A putc u_data,S2323A putc u_data,S8252 putc u_data,0x00
; 't' Show supported devices ; putc(S1200C); ; putc(S1200D); ; putc(S2313A); ; putc(S4414A); ; putc(S8515A); ; putc(S2323A); ; putc(S8252); ; putc(0x00);
// end of
device list rcall rjmp
putc waitcmd
;**** Return Programmer Type **** w4: cpi brne ldi
u_data,0x70 w5 u_data,0x53
; 'p' Return programmer type ; putc('S');
// serial
programmer rcall rjmp
putc waitcmd
;**** Set LED **** w5: cpi brne rjmp
u_data,0x78 w6 put_ret
; 'x' Set LED (ignored)
;**** Clear LED **** w6: cpi brne rjmp
u_data,0x79 w7 put_ret
; 'y' Clear LED (ignored)
;**** Enter Programming Mode **** ; We require that the device code be selected before any of the other commands w7: cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq rjmp w72:
device,S1200C w72 device,S1200D w72 device,S8515A w72 device,S4414A w72 device,S2313A w72 device,S8252 w72 device,S01838C w72 device,S01838D w72 device,S2323A w72 put_err cpi
; if ((device != S1200C) && ;
(device != S1200D) &&
;
(device != S8515A) &&
;
(device != S4414A) &&
;
(device != S2313A) &&
;
(device != S8252) &&
;
(device != S01838C) &&
;
(device != S01838D) &&
;
(device != S2323A))
;
goto put_err();
u_data,0x50
; 'P' Enter
programming mode brne rcall rjmp
w8 spiinit put_ret
; spiinit();
;**** Wait Program Memory **** ;* USAGE ;* wait_pm(byte cmd, byte c_data); ;* ;* cmd : 0x28 - wait for high byte written ;* 0x20 - wait for low byte written ;* u_data : current data written ;wait_pm: ; ; mov (cmd); // SPI write (byte 1) ; rcall ; mov (addrh); // SPI write (byte 2) ; rcall ; mov (addrl); // SPI write (byte 3) ; rcall ; rcall (); // SPI read (byte 4) ; ; ;
cp brne ret
s_data,cmd
; do ; { ;
wrser
wrser s_data,addrh
;
wrser
wrser s_data,addrl
;
wrser
wrser rdser
;
s_data = rdser
s_data,u_data wait_pm
; } ; while(s_data != u_data);
;**** Write Program Memory, High Byte **** w8: cpi
u_data,0x43
; 'C' Write program memory,
high byte brne rcall cpi brne rjmp
w9 getc device,S8252 w81 put_err
; if (device == S8252) ; { ; goto err(); ; // (AT89 series
have byte wide program memory !)
(0x48);
w81: // SPI write (byte 1)
ldi
; } s_data,0x48
; wrser
rcall mov
wrser s_data,addrh
; wrser(addrh);
//
rcall mov
wrser s_data,addrl
; wrser(addrl);
//
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
SPI write (byte 2)
SPI write (byte 3)
C! brne com w81b: mov
w81b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq
w82 device,S01838D w82
ldi
temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
ldi
temp1,0x01
; Auto increment
clr add adc rjmp
temp2 addrl,temp1 addrh,temp2 put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w82: address
!!!!
;**** Write Program Memory, Low Byte **** w9: cpi
u_data,0x63
; 'c' Write program memory,
low byte brne rcall
w12 getc
cpi breq ldi
device,S8252 w989 s_data,0x40
rcall mov rjmp
wrser s_data,addrh w91
; if (device != S8252) ; { ; wrser(0x40);
//
SPI write (byte 1)
w989: mov
s_data,addrh
; ; } ; else
s_data = addrh;
;
; { s_data = (addrh <<
3) | 0x02; rcall ori
shift_s_data3 s_data,0x02
w91: rcall
wrser
; } ; wrser(s_data);
mov
s_data,addrl
; wrser(addrl);
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
// //
SPI write (byte 2) SPI write (byte 3)
C! brne com w91b: mov
w91b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq ldi
w92 device,S01838D w92 temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w92: rjmp
;**** Read Program Memory **** w12:
cpi
u_data,0x52
; 'R' Read program
memory brne cpi breq ldi
w10 device,S8252 w1289 s_data,0x28
rcall mov rjmp
wrser s_data,addrh w121
; ; if (device != S8252) ; { ; wrser(0x28);
//
SPI write (byte 1)
w1289: mov
s_data,addrh
; ; } ; else
s_data = addrh;
;
; { s_data = (addrh <<
3) | 0x01; rcall ori w121: rcall
shift_s_data3 s_data,0x01 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall cpi brne rjmp
u_data,s_data putc device,S8252 w122 waitcmd
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
s_data,0x20
if (device == S8252) { goto waitcmd(); } else ; { ; wrser(0x20); //
rcall mov
wrser s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall rcall
wrser rdser
;
putc(rdser());
//
mov rcall
u_data,s_data putc
ldi
temp1,0x01
;
Auto increment
clr add adc
temp2 addrl,temp1 addrh,temp2
rjmp
waitcmd
; ; }
goto waitcmd();
w122: ldi
; ; ; ; ;
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
Send data (byte 4)
address
!!!!
shift_s_data3: lsl s_data lsl s_data lsl s_data ret ;**** Load Address **** w10: brne rcall mov rcall mov rjmp
cpi u_data,0x41 ; 'A' Load address w11 getc ; addrh = getc(); addrh,u_data getc ; addrl = getc(); addrl,u_data put_ret ; goto reply();
;**** Write Data Memory **** w11:
cpi
u_data,0x44
; 'D' Write data
memory brne rcall cpi breq
w13 getc device,S8252 w1189
ldi rcall mov rjmp
s_data,0xc0 wrser s_data,addrh w111
w1189: rcall ori
mov s_data,addrh shift_s_data3 s_data,0x06
w111: mov rcall mov rcall ldi rcall rjmp
rcall wrser s_data,addrl wrser s_data,u_data wrser temp1,0x20 delay put_ret
;;**** Read Data Memory **** w13:
cpi
u_data,0x64
; 'd' Read data
memory brne cpi breq ldi
w14 device,S8252 w1389 s_data,0xa0
rcall mov rjmp
wrser s_data,addrh w131
; if (device != S8252) ; { ; wrser(0xA0);
//
SPI write (byte 1)
w1389: mov
s_data,addrh
; ; } ; else
s_data = addrh;
;
; { s_data = (addrh <<
3) | 0x05; rcall ori w131: rcall
shift_s_data3 s_data,0x05 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall rjmp
u_data,s_data putc waitcmd
; goto waitcmd();
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
;**** Leave Programming Mode **** w14:
cpi
u_data,0x4c
; 'L' Leave
programming mode brne w15 ddrb_release cpi device,S8252 breq w141 set_reset rjmp put_ret w141: clr_reset rjmp put_ret
; set RESET = 1 ; set RESET = 0
;**** Chip Erase **** w15:
cpi
u_data,0x65 brne w16 ldi s_data,0xac rcall wrser cpi device,S8252 breq w1589 ldi s_data,0x80 rcall wrser w1589: ldi s_data,0x04 rcall wrser ldi s_data,0x00 rcall wrser ldi temp1,0x30 rcall delay rjmp put_ret
; 'e' Chip erase
;**** Write Lock Bits **** w16:
cpi
u_data,0x6c
; 'l' Write lock
bits brne rcall ldi rcall mov cpi breq andi ori rcall ldi rcall rjmp w1689: ori rcall w162: rcall ldi rcall rjmp
w17 getc s_data,0xac wrser s_data,u_data device,S8252 w1689 s_data,0x06 s_data,0xe0 wrser s_data,0x00 wrser w162 andi s_data,0xe0 s_data,0x07 wrser ldi s_data,0x00 wrser temp1,0x30 delay put_ret
;**** Read Signature Bytes **** w17:
cpi
u_data,0x73
brne cpi brne rjmp w17begin: ldi rcall ldi rcall ldi rcall rjmp
w18 device,S8252 w17begin put_err
w17call:ldi rcall ldi rcall mov rcall rcall mov rcall ret
s_data,0x30 wrser s_data,0x00 wrser s_data,param1 wrser rdser u_data,s_data putc
; 's' Read
signature bytes
param1,0x02 w17call param1,0x01 w17call param1,0x00 w17call waitcmd
;**** Write Program Memory Page **** w18:
cpi
u_data,0x6D
; 'm' Write Program
Memory Page brne
w19
ldi
s_data,0x4c
rcall
wrser
mov
;
wrser(0x4c);
//
s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall
wrser
ldi
s_data,0x00
;
wrser(0x00);
//
rcall ldi
wrser temp1,0xff
;
delay(0xFF);
//
rcall rjmp
delay put_ret
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
SPI write (byte 4)
0x20 = 24585 cycles delay
;**** Universal Command **** w19:
cpi
u_data,0x3A
; ':' Universal
Command brne
w99
rcall mov rcall mov rcall mov rcall ldi
getc cmd1,u_data getc cmd2,u_data getc cmd3,u_data universal temp1,0xff
rcall rjmp
delay put_ret
;
delay(0xFF);
//
0x20 = 24585 cycles delay
universal: mov rcall mov rcall mov rcall rcall mov rcall ret
s_data,cmd1 wrser s_data,cmd2 wrser s_data,cmd3 wrser rdser u_data,s_data putc
w99: ;**** Command Error **** put_err:ldi u_data,0x3f rcall putc rjmp waitcmd
; putc('?');
\\ send '?'
; putc(0x0D);
\\ send CR
;**** Reply Command **** put_ret:ldi u_data,0x0d rcall putc rjmp waitcmd ;**** End of File ****
http://avr-asm.tripod.com/avrisp.html (1 of 2)1/20/2009 8:57:59 PM
16 BIT MATH (AVR 202)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avrisp.html (2 of 2)1/20/2009 8:57:59 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ISP FOR 2313 HOME RETRO_DAN ;* ;* Title
ASM FORUM ASM MATH
: AVR ISP (Auto adr inc, 115200bps,
supports AVR109 commands) ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3
Version Last updated Target File Author(s)
: 3.7e : Jan 14 2005 : AT90S2313 : avr910_2313_v37e.asm : klaus@mikrocontroller-
MATH 200
projekte.de
MATH 200b
;* last Filename : avr910_2313_V36.asm ;* initial File : avr910_31.asm, Author: [email protected], source: www.mit8.ru/~mars/ ) ;* ;* DESCRIPTION ;* The firmware on all programmers now support a unified protocol for ;* program and data memory programming. The host computer do not need ;* to know if the programmer operates in serial or parallel mode. ;* ;* The following commands are supported. All commands start with a ;* single letter. The programmer returns 13d (carriage return) or the ;* data read after the command is finished. ;* ;* +-------------------+-------------+------+ ;* Commands | Host writes | Host reads | | ;* -------+----------+-------+-------+-----+ | ;* | ID (hex ) | data | data | | Note | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* | Enter programming mode | 'P'(0x50) | | | 13d | 1 | ;* | Report autoincrement address | 'a'(0x61) | | | 'Y' | | ;* | Set address | 'A'(0x41) | ah al | | 13d | 2 | ;* | Write program memory, low byte | 'c'(0x63) | dd | | 13d | 3 | ;* | Write program memory, high byte | 'C'(0x43) | dd | | 13d | 3 | ;* | Issue Page Write | 'm'(0x6d) | | | 13d | 13 | ;* | Read program memory | 'R'(0x52) | | dd(dd)| | 4 | ;* | Write data memory | 'D'(0x44) | dd | | 13d | | ;* | Read data memory | 'd'(0x64) | | dd | | | ;* | Chip erase | 'e'(0x65) | | | 13d | | ;* | Write lock bits | 'l'(0x6c) | dd | | 13d | | ;* | Leave programming mode | 'L'(0x4c) | | | 13d | 5 | ;* | Select device type | 'T'(0x54) | dd | | 13d | 6 | ;* | Read signature bytes | 's'(0x73) | | 3*dd | | | ;* | Return supported device codes | 't'(0x74) | | n*dd | 00d | 7 | ;* | Return software identifier | 'S'(0x53) | | s[7] | | 8 | ;* | Return sofware version | 'V'(0x56) | | dd dd | | 9 | ;* | Return hardware version | 'v'(0x76) | | dd dd | | 9 | ;* | Return programmer type | 'p'(0x70) | | dd | | 10 | ;* | Set LED | 'x'(0x78) | dd | | 13d | 12 | ;* | Clear LED | 'y'(0x79) | dd | | 13d | 12 | ;* | Universial command | ':'(0x3a) | 3*dd | dd | 13d | 15 | ;* | New universal command | '.'(0x2E) | 4*dd | dd | 13d | 15 | ;* |-----------------------------------+----------+-------+-------+-----+------| ;* | New Commands since Version 3.3 | | | | | | ;* | Exit (AVR109, Bootloader) | 'E'(0x45) | | | 13d | 15 | ;* | Return Chip ID (Terminalmode only)| 'i'(0x69) | | s[n] | | 14 | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* | New Commands since Version 3.5 | | | | | | ;* | Implemented Atmel Bootloader commands (Atmel Appl. Note 109) | | | ;* | Report Block write Mode | 'b'(0x62) | |'Y'2*nn| 13d | 16 | ;* | Block Write | 'B'(0x42) | 2*nn'M'| n*dd | 13d | 16 | ;* | Block Read | 'g'(0x67) | 2*nn'M'| n*dd | 13d | 16 | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* | Commands to test (Since V3.6, (Unverified) | | | | | ;* | Return Lockbits | 'r'(0x72) | | dd | 13d | 17 | ;* | Return High Fusebits | 'N'(0x4E) | | dd | 13d | 17 | ;* | Return extendet Fusebits | 'Q'(0x51) | | dd | 13d | 17 | ;* | Write fuse bits (reserved) | 'f'(0x66) | dd | | 13d | 11 | ;* | Read fuse and lock bits (reserved)| 'F'(0x46) | | dd | | 11 | ;* +-----------------------------------+----------+-------+-------+-----+------+ ;* ;* NOTE 1 ;* The Enter programming mode command MUST be sent one time prior to ;* the other commands, with the exception of the 't', 'S', 'V', 'v' ;* and 'T' commands. The 'T' command must be sent before this command ;* (see note 6). ;* ;* For programmers supporting both parallel and serial programming ;* mode this command enters parallel programming mode. For programmers ;* supporting only serial programming mode, this command enters serial ;* programming mode. ;* ;* NOTE 2 ;* The ah and al are the high and low order bytes of the address. For ;* parallel programmers this command issues the Load Address Low/High ;* Byte command. For serial programmers the address byte is stored for ;* use by the Read/Write commands. ;* ;* NOTE 3 ;* For parallel programmers this command issues the Program Flash ;* command. For serial programmers this command iussues the Write ;* Program Memory Command. For devices with byte-wide program memories ;* only the low byte command should be used. ;* ;* NOTE 4 ;* The contents of the program memory at the address given by the 'A' ;* command are written to the serial port in binary form. For byte ;* wide memories one byte is written. For 16 bit memories two bytes ;* are written,MSB first. ;* ;* NOTE 5 ;* This command must be executed after the programming is finished. ;* ;* NOTE 6 ;* The select device type command must be sent before the enter ;* programming command ;* ;* NOTE 7 ;* The supported device codes are returned in binary form terminated ;* by 0x00. ;* ;* NOTE 8 ;* This return a 7 character ASCII string identifying the programmer. ;* For the development board it is "AVR DEV", for the parallel ;* programmer it is "AVR PPR" and for the in-curcuit programmer it is ;* "AVR ISP". ;* ;* NOTE 9 ;* The software/hardware version are returned as two ASCII numbers. ;* ;* NOTE 10 ;* This command should be used to identify the programmer type. The ;* return value is 'S' for serial (or SPI) programmers or 'P' for ;* parallel programmers. ;* ;* NOTE 11 ;* The write fuse bits command are available only on parallel ;* programmers and only for AVR devices (device code < 0x80). The host ;* should use the return programmer type command to determine the ;* programmer type, do not use the "AVR PPR" idenifier because other ;* programmers may be available in the future. ;* ;* NOTE 12 ;* Currently only the AVR development board has LEDs. The other boards ;* must implement this commands as NOPs. ;* ;* NOTE 13 ;* Devices using Page Mode Programming write one page of flash memory ;* before issuing a Page Mode Write Pulse. ;* ;* NOTE 14 ;* The 'i' command is only used with a Terminal, for debug reasons. ;* Not used in any Programmer so far ;* ;* NOTE 15 ;* Lock and Fuse Bits are written using the "universal command" (:) and ;* "new universal command" (.) in AVRProg and AVRDUDE. ;* AVRProg has an Exit (E) command implemented, which switches AVRProg offline ;* ;* NOTE 16 ;* Atmel Bootloader commands described in Atmel Application Note 109 implemented. ;* Very useful if you use USB to serial converter. ;* AVRProg since Version 1.33 checks if Programmer supports Block Mode, ;* IF Programmer responds 'Y' and the size of the internal Buffer (nn nn), Bootloader commands ;* are used automatically from AVRProg. (faster Protocoll) ;* Block commands send size Buffersize (nn nn) and Type of Memory ('F'=Flash, 'E'=Data) ;* Compatibility to AVR Butterfly command set and Bootloader. Works with AVR911 Open Source ;* Programmer. ;* For avrdude use -c butterfly instead of -c avr910 and you get same behaviour. ;* ;* NOTE 17 ;* Commands implemented but not tested yet. ;* ;* NOTE 18 ;* Device 89S8252 was tested to programm with avrprog. Shows a avrprog bug in "block Mode". Works in "standart" ;* avr910 Programming Mode. To program this Device, disable the "Block Mode" by changing "w53: rjmp w6" ;* ;* HISTORY ;* V3.7e 11.01.05 (Klaus) Matched Devicecodes to the new Atmel AVRProgV1.40 ;* V3.7d 05.01.05 (Klaus) Removed 1200A/B/C devicecodes, Polling 0x7F for AT90S4414, default PollcodeF = 0xFF ;* V3.7c 04.01.05 (Klaus/Micha) Some devicecodes changed (Bootloader and "default" mode). ;* V3.7b 03.01.05 (Klaus/Leo) Bugfix for Block read of Flash Mamory for AT89Snnnn Controllers. ;* V3.7a 29.12.04 (Klaus/Micha) addet devicecodes for m64, m162 and m169. ;* V3.7 15.12.04 (Klaus) Rewriting polled timing for "non Page Mode" Chips, reorganised Table for ;* different polling Codes. Skip 0xFF Byte polling. (was buggy for some Controllers) ;* Added ATTiny2313 (device Code 0x23), and ATMega8535 (0x6A)Support. ;* Not Supported from avrprog, avrdude Support possible. ;* Reorganised Table for Page Mode Chips with Pagesize. Adding different Pagesizes ;* Try to fix S89 write, BUG in avrprog detected. Firmware should be OK now. (NOTE 18) ;* After 256 unsuccesful polls for Flash wait additional standart time. ;* Modified "release_ports" so that RESET is released also. ;* V3.6 10.07.04 (Klaus) Changed Block Mode Commands to AVR109 compatibility. ;* Additional AVR109 Commands, not testet yet. ;* V3.4-V3.5 unreleased (Klaus) cleaning up, tests for Block Modes ;* V3.3 25.06.04 (Klaus, Thomas) added enhanced Block write commands ; with own Protocol. ; Add 0xFF, 0x7F (2313) check for polling Mode ;* V3.2.1 18.11.03 (Klaus) Commented out some Controller Types, which are ; not really Supported by the hardware, but from ; AVRProg Software. See Comments at the end. ;* V3.2 16.11.03 (Klaus) Correctet typo in Chrystal frequency. ;* V3.2 13.10.03 (Klaus) 7,3728 Mhz chrystal for 115.200 Baud. ;* Swap MOSI <> MISO Pinnumbers. ;* Add dual color LED Support. ;* Add some new Dewices. ;* V3.0 02.01.23 (wubble) Ported from 1200 to 2313. ;* Serial IO modified to use hardware UART. ;* Added support for multiple new devices. ;* Used data polling to short write process. ;* Added LED support to indicate R/W process. ;* V2.2 00.03.10 (pkastnes) Added support for multiple new devices. ;* V2.1 98.10.26 (mlund) New date marking. ;* Removed support for AT90S1200C. ;* Added support for AT90S4433A. ;* V2.0 98.01.06 (mlund) ATmega103 support. ;* V1.7 97.11.06 (mlund) Universial command (':') implemented. ;* Releases all pins when not in ;* programming mode. ;* V1.6e 97.11.04 (mlund) mega103 rev D support ;* V1.6c 97.10.30 (mlund) Auto incrementing / SPI sync ;* also works for mega103. ;* V1.6 97.09.09 (hskar) Created Page Mode Version (mega103) ;* V1.5 97.08.21 (mlund) Modified / Bugfix / Major cleanup ;* ... ... (no records) ;* V?.? 97.03.15 (OS) Created ;* ;* ;* Device Support List: see table "Devices" at the end of this file.
MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;**** includes **** .include "2313def.inc" ; *************************************************************************** ;* ;* CONSTANTES ;* ; *************************************************************************** ;**** Constant declarations Data Rate **** ;******** Chrystals for maximum Baudrates .equ XTAL = 7373
; XTAL
frequency, Khz (7.3728 Mhz) ;******** .equ .equ
BAUD = 115200 N = 3
; Data rate, bauds ; for
;******** ;.equ ;.equ
BAUD = 38400 N = 11
; Data rate, bauds ; for
7.3728 Mhz/115.200Baud
7.3728 Mhz/38400Baud ;******** ;**** definitions for different chrystals and 115.200 baud **** ;.equ
XTAL = 3686
;********* ;.equ ;.equ
BAUD = 115200 N = 1
; XTAL
frequency, Khz (3.6864 Mhz) ; Data rate, bauds ; for
3.6864 Mhz/115.200Baud ;********* ; ;********* Baudrates for 8 Mhz Chrystal ;.equ XTAL = 8000
; XTAL
frequency, Khz (8.000 Mhz) ;********* ;.equ ;.equ
BAUD = 38400 N = 12
; Data rate, bauds ; for 8.00
;********* ;.equ ;.equ
BAUD = 19200 N = 25
;Data rate, bauds ; for 8.00
Mhz/38.400 Baud
Mhz/19.200 Baud ;********* ;.equ BAUD = 9600 rate, bauds ! Not valid for AVRProg, use for avrdude only ! ;.equ N = 51 Mhz/9.600 Baud ;*********
; Data ; for 8.00
;********* Baudrates for 4 Mhz Chrystal ;.equ XTAL = 4000
; XTAL
frequency, Khz (4.000 Mhz) ;********* ;.equ ;.equ
BAUD = 19200 N = 12
; Data rate, bauds ; for 4.00
Mhz/19.200 Baud ;********* ;.equ BAUD = 9600 rate, bauds ! Not valid for AVRProg, use for avrdude only ! ;.equ N = 25 Mhz/9.600 Baud ;*********
; Data ; for 4.00
.equ RAMSTART = 0x60
; first SRAM Adress
.equ PAGESIZE = 0x10
; default Page size
.equ BUFSIZE
; 64 bytes internal
of 2313 for Programming = 0x40
RAM for Buffer ; *************************************************************************** ;* ;* PORTS ;* Ports Definitions ;* ;* DESCRIPTION ;* Change the following definitions if the RESET pin to the ;* target moves and/or if the SCK/MISO/MISO/LED moves. ;* ; *************************************************************************** .equ
LEDH
= PB3
; dual color LED
.equ active low, dual color LED Kathode green .equ target (input) .equ target (output)
LED (output) MISO
= PB0
; LED output,
= PB6
; MISO
pin of the
MOSI
= PB5
; MOSI
pin of the
.equ
RESET
= PB4
; RESET pin of the
.equ
SCK
= PB7
; SCK
.equ .equ
RXD TXD
= PD0 = PD1
; UART RXD line ; UART TXD line
output, anode green
(output)
target (output) pin of the
target (output)
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following macros if the RESET pin to the ;* target moves and/or if the SCK/MISO/MISO/LED moves. ;* ; *************************************************************************** .macro ldi out ldi out .endm
init_ports temp2,0xff PORTD,temp2 temp2,0xff PORTB,temp2
; init ports
.macro
catch_ports
; catch
ports ldi temp2,(1<<TXD) out DDRD,temp2 ldi temp2,(1<<RESET) | (1<<MOSI) | (1<<SCK) | (1<<LED) | (1<<LEDH) out DDRB,temp2 .endm .macro ldi out ldi out .endm
release_ports ; release ports temp2,(1<<TXD) DDRD,temp2 temp2,(1<<LED) | (1<<LEDH) DDRB,temp2
.macro
pas_RESET
tst brmi sbi rjmp m2: cbi m3: .endm
device m2 PORTB,RESET m3 PORTB,RESET
.macro
act_RESET
tst brmi cbi rjmp m4: sbi m5: .endm
device m4 PORTB,RESET m5 PORTB,RESET
; set RESET
passive ; S89 device
; set RESET
active ; S89 device
.macro set_LED Port -> Standart LED off, dual LED green sbi PORTB,LED cbi PORTB,LEDH color support .endm
; set LED
; added for dual
.macro clr_LED Port --> Standart LED on, dual LED red cbi PORTB,LED sbi PORTB,LEDH color support .endm
; clear LED
; added for dual
.macro LED_off
; for dual
color LED, not in use cbi PORTB,LED cbi PORTB,LEDH .endm .macro
sbic_MISO
; skip if
sbic .endm
PINB,MISO
.macro sbi .endm
set_MOSI PORTB,MOSI
; set MOSI
.macro cbi .endm
clr_MOSI PORTB,MOSI
; clear MOSI
.macro cbi .endm
clr_SCK PORTB,SCK
; clear SCK
MISO cleared
.macro pulse_SCK sbi PORTB,SCK ldi temp2,(XTAL/750+1) for ATTiny2313 (internal clock) default was (XTAL/1500+1) m0: dec temp2 brne m0 cbi PORTB,SCK ldi temp2,(XTAL/1500+1) for ATTiny2313 (internal clock) default was (XTAL/3000+1) m1: dec temp2 brne m1 .endm .macro
table
ldi ldi .endm
ZL,low(@0*2) ZH,high(@0*2)
; pulse SCK ; had to slow down
; had to slow down
; load Z
pointer ; low ; high
; *************************************************************************** ;* ;* Global Register Variables ;* ; *************************************************************************** ;r0 used with lpm instruction .def cmd1 = r1
; Universal
.def .def .def
cmd2 cmd3 pol_al
= r2 = r3 = r4
; .. ; .. ; Polling address
.def
pol_ah
= r5
; Polling address
.def
Bcnt1
= r6
; Block Mode
.def
Bcnt2
= r7
; Block Mode
.def
Bcnt3
= r8
; Block Mode
commands params
low high Counter1 Counter2 Counter2 .def
B_Flag
= r9
; Flag for ws_del
.def
B_Mode
= r10
; Marks Block Mode
= r11
; Flag for
= r12
; Size of
= r13
; Code for Polling
Routine commands (See Note 16) .def Memtype Memorytype for Block Commands (See Note 16) .def Pagewords Controller page to program in Page Mode (Words!) .def PollcodeF Flash .def
temp1
= r16
; Temporary
.def
temp2
= r17
; Temporary
.def
temp3
= r18
; Temporary
.def .def .def .def
s_data u_data device param1
= = = =
; ; ; ;
register 1 register 2 register 3 r19 r20 r21 r22
SPI data UART data Device code Param to read
signature .def rd_s_data .def pol_cmd .def p_data ;r26,r27 used as X register .def addrl
= r23 = r24 = r25
; Read data on SPI ; Polling command ; Polling data
= r28
; (YL) Low order
.def
= r29
; (YH) High order
byte of address addrh
byte of address ;r30,r31 used as Z register ; *************************************************************************** ;* ;* Interrupt Vectors ;* ; *************************************************************************** .CSEG rjmp
INIT
; Reset Handle
; *************************************************************************** ;* ;* FUNCTION ;* u_init ;* ;* DESCRIPTION ;* Initialize UART. ;* ; *************************************************************************** u_init: ldi
temp1,N
; set baud
rate out ldi
UBRR,temp1 temp1,(1<<TXEN)|(1<<RXEN) ;
out ret
UCR,temp1
initialize UART for TX and RX
; *************************************************************************** ;* ;* FUNCTION ;* getc ;* ;* DESCRIPTION ;* Wait for start bit and receive a character on the UART Rx line. ;* ; *************************************************************************** getc: sbis
USR,RXC
; wait until a
character has been received rjmp in
getc u_data,UDR
; Read byte
from the UART ret ; *************************************************************************** ;* ;* FUNCTION ;* putc ;* ;* DESCRIPTION ;* Send a character on the UART Tx line. ;* ; *************************************************************************** putc: sbis
USR,UDRE
; test for TX
rjmp
putc
; loop until TX
out
UDR,u_data
register empty empty ; send the
byte ret ; *************************************************************************** ;* ;* FUNCTION ;* put_string ;* ;* DESCRIPTION ;* Send Z - pointed null-terminated string on the UART Tx line. ;* ; *************************************************************************** put_string: lpm tst r0 breq ps_ret
; check for end of
string (0x00) mov rcall adiw rjmp ps_ret:
u_data,r0 putc ZL,1 put_string ret
; putc(char) ; next char
; *************************************************************************** ;* ;* FUNCTION ;* put_table ;* ;* DESCRIPTION ;* Send Z - pointed table on the UART Tx line. ;* ; *************************************************************************** put_table: lpm tst breq
r0 pt_ret
mov rcall adiw rjmp pt_ret:
u_data,r0 putc ZL,2 put_table ret
; check for end of
table (0x00) ; putc(Byte) ; skip MSB
; *************************************************************************** ;* ;* FUNCTION ;* bel_table ;* ;* DESCRIPTION ;* C=0 if device belongs to table. ;* ; *************************************************************************** bel_table: lpm
;
read table tst
r0
;
check for end of table breq cp breq adiw rjmp c1_ret:
c1_ret device,r0 c0_ret ZL,2 bel_table sec
c0_ret:
ret
; C=0 ; skip MSB ;
C=1
; *************************************************************************** ;* ;* FUNCTION ;* set_pagesize ;* ;* DESCRIPTION ;* sets programming Page size for selected Device. ;* ; *************************************************************************** set_pagesize: lpm tst r0
; read table ; check for end of
table breq cp breq adiw rjmp spa_set: adiw
spa_end device,r0 spa_set ZL,2 set_pagesize
; no Pagesize to set
ZL,1
; Point to high
; C=0 ; skip MSB
Byte of Word lpm mov Pagewords,r0 mov Bcnt3,Pagewords spa_end: ret
; get Pagesize to R0 ; initiate Counter
; *************************************************************************** ;* ;* FUNCTION ;* set_pollcode ;* ;* DESCRIPTION ;* sets Code for Polling Flash for selected Device. ;* ; *************************************************************************** set_pollcode: lpm tst r0
; read table ; check for end of
table breq cp breq adiw rjmp spo_set: adiw
spo_end device,r0 spo_set ZL,2 set_pollcode
; no Pollcode to set
ZL,1
; Point to high
; C=0 ; skip MSB
Byte of Word lpm mov PollcodeF,r0
; get Pagesize to R0 ; Set Pollcode for
Flash Rom spo_end: ret ; *************************************************************************** ;* ;* FUNCTION ;* delay ;* ;* DESCRIPTION ;* Make delay 1mS (x temp1). ;* ; *************************************************************************** delay: ldi dl2: dl1: brne dec brne dec brne ret
temp2,40 ldi temp3,(XTAL/120) dec temp3 dl1 temp2 dl2 temp1 delay
; *************************************************************************** ;* ;* FUNCTION ;* spi123 ;* ;* DESCRIPTION ;* Write bytes 1 to 3 on the SPI. Byte 1 must be loadet into s_data ;* Byte 2 ist addrh, Byte 3 ist addrl ;* ; *************************************************************************** spi123: rcall
wrser
; wrser(s_data) SPI
mov rcall
s_data,addrh wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
write (byte 1)
write (byte 2)
write (byte 3) ret ; *************************************************************************** ;* ;* FUNCTION ;* w1234 (for Code simplification, not used yet) ;* ;* DESCRIPTION ;* Write SPI bytes 1 to 4. ; Byte 1 must be loadet into cmd1 ; Byte 2 must be loadet into cmd2 ; Byte 3 must be loadet into cmd3 ; Byte 4 must be loadet into u_data ;* ; *************************************************************************** w1234: mov s_data,cmd1 rcall wrser mov s_data,cmd2 rcall wrser mov s_data,cmd3 rcall wrser mov s_data,u_data rcall wrser ret ; *************************************************************************** ;*
http://avr-asm.tripod.com/isp2313.html (1 of 4)1/20/2009 8:58:51 PM
16 BIT MATH (AVR 202)
;* FUNCTION ;* w123r4 (for Code simplification, not used yet) ;* ;* DESCRIPTION ;* Write SPI bytes 1 to 3, read Byte 4 to serial. ; Byte 1 must be loadet into cmd1 ; Byte 2 must be loadet into cmd2 ; Byte 3 must be loadet into cmd3 ;* ; *************************************************************************** w123r4: mov s_data,cmd1 rcall wrser mov s_data,cmd2 rcall wrser mov s_data,cmd3 rcall wrser rcall rdser mov u_data,s_data rcall wrser ; get Byte 4 from serial rcall putc ret
; *************************************************************************** ;* ;* FUNCTION ;* rdser, wrser ;* ;* DESCRIPTION ;* Write and read bytes on the SPI. ;* ; *************************************************************************** rdser: clr s_data wrser: ldi temp1,8 ldi rd_s_data,0 wrs0: rol s_data brcc wrs1 set_MOSI rjmp wrs2 wrs1: clr_MOSI wrs2: lsl rd_s_data sbic_MISO ori rd_s_data,1 pulse_SCK dec temp1
; load bit counter
; MOSI = 1
; MOSI = 0
; read MISO ; pulse SCK ; advance bit
counter brne mov ret
wrs0 s_data,rd_s_data
; loop
; *************************************************************************** ;* ;* FUNCTION ;* read_send_progmem ;* ;* DESCRIPTION ;* Read one adress (2 Byte) from Program Memory and send it through UART ;* ; *************************************************************************** read_send_progmem: tst device brmi rsp1 ; S89 device ldi s_data,0x20 ; read low Byte rcall wrser ; wrser(0x28) SPI write (byte 1) mov s_data,addrh rjmp rsp2 rsp1: mov s_data,addrh ; s_data = (addrh << 3) | 0x01; rcall shift_s_data3 ori s_data,0x01 rsp2: rcall wrser ; wrser(addrh) SPI write (byte 2) (S89=byte1) mov s_data,addrl rcall wrser ; wrser(addrl) SPI write (byte 3) rcall rdser ; SPI read (byte 4) mov u_data,s_data rcall putc ; send data tst device brmi rsp3 ; S89 device ldi s_data,0x28 ; read High Byte rcall wrser ; wrser(0x20) SPI write (byte 1) mov s_data,addrh rcall wrser ; wrser(addrh) SPI write (byte 2) mov s_data,addrl rcall wrser ; wrser(addrl) SPI write (byte 3) rcall rdser ; SPI read (byte 4) mov u_data,s_data rcall putc ; send data rsp3: adiw addrl,1 ; Auto increment address ret ; *************************************************************************** ;* ;* FUNCTION ;* read_send_datamem ;* ;* DESCRIPTION ;* Read one Byte from Data Memory (eeprom) and send it through UART ;* ; *************************************************************************** read_send_datamem: ; Subroutine to read one eeprom Address tst device brmi rsd1 ; S89 device ldi s_data,0xa0 rcall wrser ; wrser(0xa0) SPI write (byte 1) mov s_data,addrh rjmp rsd2 rsd1: cpi device,0x87 ; if (device == S53) breq rsd3 ; no Support for 89S53 device due to Bug in AVRProg V1.37 mov s_data,addrh rcall shift_s_data3 ori s_data,0x05 rsd2: rcall wrser ; wrser(addrh) SPI write (byte 2) mov s_data,addrl rcall wrser ; wrser(addrl) SPI write (byte 3) rcall rdser ; SPI read (byte 4) mov u_data,s_data rcall putc ; send data adiw addrl,1 ; Auto increment address ret rsd3: pop temp1 ; remove return Adress from Stack in case of Error pop temp1 rjmp put_err
; *************************************************************************** ;* ;* FUNCTION ;* eeprom_write ;* ;* DESCRIPTION ;* Write u_data to Data Memory (eeprom) ;* ; *************************************************************************** eeprom_write: tst device brmi eew1 ; S89 device ldi s_data,0xc0 rcall wrser ; wrser(0xc0) write (byte 1) mov s_data,addrh rjmp eew2 eew1: cpi device,0x87 ; if (device == breq eew3 mov s_data,addrh rcall shift_s_data3 ori s_data,0x06 eew2: rcall wrser ; wrser(addrh) write (byte 2) mov s_data,addrl rcall wrser ; wrser(addrl) write (byte 3) mov s_data,u_data rcall wrser ; wrser(u_data) write (byte 4) ldi temp1,10 ; delay 10mS rcall delay adiw
addrl,1
SPI
S53)
SPI
SPI
SPI
; Auto increment
address ret eew3: pop temp1
; remove return
Adress from Stack in case of failure pop temp1 rjmp put_err ; *************************************************************************** ;* ;* FUNCTION ;* shift_s_data3 ;* ;* DESCRIPTION ;* Shift s_data 3 times left for S89 device. ;* ; *************************************************************************** shift_s_data3: lsl s_data lsl s_data lsl s_data brcc s3_ret cpi device,0x87 brne s3_ret sbr s_data, 4 s3_ret: ret
; if (device != S53) ; a13 +
; *************************************************************************** ;* ;* FUNCTION ;* healthcheck ;* ;* DESCRIPTION ;* changes color of dual color led. ;* ; *************************************************************************** healthcheck:
; for dual
color LED clr_LED ldi temp1,200 rcall delay ldi temp1,200 rcall delay ldi s_data,200
; LED red ; 200 ms ; again 200 ms ; counter Register
LEDloop:
; Pulse for yellow
LED set_LED ldi temp1,2 rcall delay clr_LED ldi temp1,1 rcall delay dec s_data brne LEDloop set_LED ret
; LED green ; 2 ms ; LED red ; 1 ms ; dec. counter ; LED green
; *************************************************************************** ; *************************************************************************** ; *************************************************************************** ;* ;* INIT ;* ;* DESCRIPTION ;* Initialization ;* ; *************************************************************************** ; *************************************************************************** ; *************************************************************************** INIT: ldi temp1,RAMEND out SPL,temp1 ldi temp1,PAGESIZE mov Pagewords,temp1 mov Bcnt3,Pagewords
; Locate stack ; default Pagesize ; set counter for
Pagesize ldi device,0x20 clr B_Mode
; S2313 as default ; Flag for Block
clr B_Flag
; Flag for eNhanced
init_ports release_ports rcall u_init rcall healthcheck
; ; ; ;
Modes (see Note 16) Block write Initialize ports Release ports Initialize UART show that Prog is
working after Powerup (LED test)
; *************************************************************************** ;* ;* PROGRAM ;* waitcmd -> main ;* ;* DESCRIPTION ;* Wait for and execute commands. ;* ; *************************************************************************** waitcmd: rcall
getc
; while (getc() ==
ESC) {}; cpi breq
u_data,0x1b waitcmd
;====== 'T' - Device Type ================================================== cpi u_data,'T' brne w0 rcall getc mov device,u_data table Dev_M
; 'T' Device type
rcall set_pagesize
; If device has
; get device type ; prepare to set
Pagesize Page Mode support, set Pagesize ldi temp1,0xFF mov PollcodeF,temp1 with 0xFF, will be overwritten if Pollcode known table Dev_S Polling Code rcall set_pollcode Page Size support, set code for Polling Flash rjmp put_ret
; preset PollcodeF ; prepare to set ; If device has no
;====== 'S' - Return Software Identifier =================================== w0: cpi
u_data,'S'
; 'S' Return
brne table rcall
w1 ID_Str put_string
; put string "AVR
rjmp
waitcmd
software identifier
ISP"
;====== 'V' - Return Software Version ====================================== w1: cpi
u_data,'V'
; 'V' Return
brne table rcall
w2 SW_Ver put_string
; put software
rjmp
waitcmd
software version
version
;====== 'v' - Return Hardware Version ====================================== w2: cpi
u_data,'v'
; 'v' Return
brne table rcall
w3 HW_Ver put_string
; put hardware
rjmp
waitcmd
hardware version
version
;====== 't' - Show Supported Devices ======================================= w3: cpi
u_data,'t'
; 't' Show
brne table rcall
w4 Dev_S put_table
; put supported
table rcall
Dev_M put_table
; put supported
ldi
u_data,0x00
; putc(0x00) - end
rcall rjmp
putc waitcmd
supported devices
devices codes
devices codes of device list
;====== 'p' - Return Programmer Type ======================================= w4: cpi
u_data,'p'
; 'p' Return
brne ldi
w5 u_data,'S'
; putc('S') -
rcall rjmp
putc waitcmd
programmer type
serial programmer
;====== 'a' - Return autoincrement address support ========================= w5: cpi
u_data,'a'
; 'a' Return
brne ldi
w51 u_data,'Y'
; putc('Y') -
rcall rjmp
putc waitcmd
address auto increment
supports autoinc
;====== 'M' - Return enhanced Mode support (Note 14) ======================== w51: ; cpi
u_data,'M'
; 'M' Return
enhanced mode Support ; ;
brne w52 ldi u_data,'Y'
; ;
rcall putc rjmp waitcmd
; putc('Y') -
supports enhanced Mode
;====== 'i' - Return Chip ID (Note 14) ====================================== w52: cpi brne table rcall
u_data,'i' w53 ChipID put_string
; 'i' Return Chip ID
; put Chip ID
string ldi u_data,0x0a rcall putc rjmp put_ret
; putc(LF)
;====== 'b' - Return Block write Mode support (Note 17) ======================== w53: cpi
u_data,'b'
; 'b' Return
enhanced mode Support brne w6 ldi u_data,'Y'
; putc('Y') -
rcall putc ldi u_data,high(BUFSIZE)
; putc((BUFSIZE>
rcall putc ldi u_data,low(BUFSIZE)
; putc
supports enhanced Mode
>8) & 0xff);
(BUFSIZE&0xff); rcall putc rjmp waitcmd ;====== 'x' - Set LED ====================================================== w6: cpi
u_data,'x'
; 'x' Set LED (LED
off or green) brne w61 rcall getc set_LED rjmp put_ret
; get parameter
;====== 'y' - Clear LED ==================================================== w61: cpi
u_data,'y'
; 'y' Clear LED
(LED on or red) brne w7 rcall getc clr_LED rjmp put_ret
; get parameter
; =========================================================================== ; We require that the device code be selected before any of the other commands w7: table rcall brcc
Dev_S bel_table w71
; load pointer
table rcall brcc
Dev_M bel_table w71
; device belongs to
rjmp
put_err
; not match, goto
; device belongs to
table
table put_err(); ;====== 'P' - Enter Programming Mode ======================================= w71: cpi
u_data,'P'
breq rjmp
w70 w8
; 'P' Enter
programming mode
w70: clr_LED catch_ports clr_SCK pas_RESET ldi temp1,50 rcall delay act_RESET ldi temp1,50 rcall delay ldi s_data,0xac rcall wrser
; ; ; ; ;
LED on catch ports clear SCK set RESET passive delay 50mS;
; set RESET active ; delay 50mS;
; wrser(0xac) SPI
write (byte 1) ldi rcall
s_data,0x53 wrser
; wrser(0x53) SPI
write (byte 2) ; SPI Synchronization (fix!) cpi
device,0x20
; if ( (device >
s2 device s2 temp3,32 rdser s_data,0x53 s3
; ; ; ;
wrser
; wrser(0x00) SPI
= 0x20) && (device <= 0x7F) ) brlo tst brmi ldi s1: rcall cpi breq ldi
count = 32; SPI read (byte 3) if (rdser == 0x53) break
s_data,0x00 rcall write (byte 4) pulse_SCK ldi s_data,0xac rcall wrser
; pulse SCK ; wrser(0xac) SPI
write (byte 1) ldi rcall
s_data,0x53 wrser
dec brne rjmp s2: ldi rcall
temp3 s1 s3 s_data,0x00 wrser
s3: tst brmi ldi rcall
device s4 s_data,0x00 wrser
s4: ldi rcall rjmp
temp1,4 delay put_ret
; wrser(0x53) SPI
write (byte 2) ; count-1 ; loop ; else ; wrser(0x00) SPI
write (byte 3) ; S89 device ; wrser(0x00) SPI
write (byte 4) ; delay 4mS;
;====== 'c' - Write Program Memory, Low Byte =============================== w8: cpi
u_data,'c'
brne rcall mov
w9 getc ldi s_data,0x40 pol_cmd,s_data
tst brmi rcall
device w81 wrser
mov rjmp
s_data,addrh w82
; 'c' Write program
memory, low byte
w8b:
; get data byte ; save command for
polling ; S89 device ; wrser(0x40)
SPI
write (byte 1)
w81: mov
s_data,addrh
rcall ori
shift_s_data3 s_data,0x02
; s_data = (addrh
<< 3) | 0x02;
w82: rcall
wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
mov rcall
s_data,u_data wrser
; wrser(u_data) SPI
mov
p_data,u_data
; save data for
mov
pol_al,addrl
; save address for
mov tst brpl adiw
pol_ah,addrh device w83 addrl,1
; Auto increment
wait_S
; write FLASH delay
write (byte 2)
write (byte 3)
write (byte 4) polling polling
address for S89 device w83: rjmp
;====== 'C' - Write Program Memory, High Byte ============================== w9: cpi
u_data,'C'
; 'C' Write program
brne rcall brmi ldi mov
w92 getc tst device w91 s_data,0x48 pol_cmd,s_data
rcall
wrser
; wrser(0x48)
SPI
mov rcall
s_data,addrh wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
mov
s_data,u_data
; wrser(u_data) SPI
rcall mov
wrser p_data,u_data
; save data for
mov
pol_al,addrl
; save address for
mov adiw
pol_ah,addrh addrl,1
; Auto increment
rjmp
wait_S
; write FLASH delay
put_err
; S89 device have
memory, high byte
w9a:
; get data byte ; S89 device ; save command for
polling write (byte 1)
write (byte 2)
write (byte 3) write (byte 4)
polling polling
address w91: rjmp byte wide program memory! ;====== 'B' Block Write Memory (see Note 17) ====================== w92: cpi
u_data,'B'
; 'B' Block Write
Program Memory breq w92a rjmp w10 w92a: rcall getc
; get count High
tst u_data breq w92b ldi u_data,1 rjmp put_err w92b: rcall getc cpi u_data,BUFSIZE+1
; get count Low Byte ; check maximum
brlo w92c ldi u_data,2 rjmp put_err w92c: mov Bcnt1, u_data
; ignore BUFSIZE
Byte
count
high Byte (must be 0 here) mov Bcnt2, u_data rcall getc
; get Memory type
to write mov Memtype,u_data clr XH ldi XL, RAMSTART
; Flag for Memtype ; set X pointer to
SRAM begin w93: rcall
getc
; get data until
Bcnt1 is reached st X+, u_data dec Bcnt1 brne w93 clr XH ldi XL, RAMSTART
; store data to SRAM
; set X pointer to
SRAM begin ldi temp3,1 mov B_Mode,temp3 mov u_data,Memtype cpi u_data,'F'
; B_Mode != 0 ; restore Memtype ; 'F' Flash Memory
breq cpi
w94a u_data,'E'
; 'E' eeprom Memory
breq
w94
; Entry Point for
ist to write
ist to write Data Memory Block write ldi u_data,3 rjmp put_err w94:
; write
Data Memory ld u_data,X+ rcall eeprom_write dec Bcnt2 brne w94 rjmp put_ret ;Entry Point for Flash Block write w94a: table Dev_M rcall bel_table brcc w95
; device belongs to
table rjmp
w96
; not match, goto
"non Paged" Mode w95:
; Entry
Point for AVRProg Block Flash write ldi s_data,0x40 rcall spi123 ld s_data, X+ rcall wrser
; write low byte
ldi mov
; write high byte ; save command for
; wrser(s_data) SPI
write (byte 4) s_data,0x48 pol_cmd,s_data
polling rcall spi123 ld s_data, X+ mov p_data,s_data
; save data for
mov
pol_al,addrl
; save address for
mov rcall
pol_ah,addrh wrser
; wrser(u_data) SPI
adiw
addrl,1
; Auto increment
polling polling
write (byte 4) address dec Bcnt2 breq w95b dec Bcnt2 breq w95b tst B_Mode breq w95
; Loop for "Block
dec Bcnt3
; count Bytes for
Mode Commands" see Note 16 Pagesize brne w95 w95b: tst B_Mode brne w95c rjmp put_ret w95c: dec Bcnt3
; Bcnt3 will be set
correct after write ldi rcall
s_data,0x4c wrser
; write Memory Page ; wrser(0x4c) SPI
mov
s_data,pol_ah
; last written
rcall
wrser
; wrser(addrh) SPI
mov
s_data,pol_al
; last written
rcall
wrser
; wrser(addrl) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
write (byte 1) Adress is in Page to be programmed! write (byte 2) Adress is in Page to be programmed! write (byte 3) SPI
write (byte 4) mov Bcnt3,Pagewords
; reload Counter
für Pagesize rjmp wait_M
;#@KL4 test for 89S8252 Device w96:
; Non Page
Mode Flash write tst brmi ld
device w96b p_data, X+
; S89 device ; load byte to Poll
cpi
p_data,0xFF
; if (p_data ==
breq ldi mov
w961 s_data,0x40 pol_cmd,s_data
; skip burning ; write low byte ; save command for
data 0xFF)
polling rcall spi123 mov s_data,p_data
; reload data from
rcall
wrser
; wrser(s_data) SPI
mov
pol_al,addrl
; save address for
Poll data write (byte 4) polling mov pol_ah,addrh rcall Bws_pol w961: dec Bcnt2 ld p_data, X+
; load byte to Poll
data cpi
p_data,0xFF
; if (p_data ==
breq ldi mov
w962 s_data,0x48 pol_cmd,s_data
; write high byte ; save command for
0xFF)
polling rcall spi123 mov s_data,p_data
; reload data from
rcall
; wrser(u_data) SPI
Poll data wrser
write (byte 4) w96a:
mov
pol_al,addrl
; save
address for polling mov pol_ah,addrh rcall Bws_pol w962: adiw addrl,1
; Auto increment
address dec Bcnt2 brne w96 rjmp put_ret
; reply
w96b:
; Code for
89S8252 ; ;
ldi mov
s_data,0x40 pol_cmd,s_data
; save command for
mov
s_data,addrh
; s_data = (addrh
rcall ori rcall
shift_s_data3 s_data,0x02 wrser
; wrser(addrh)
SPI
mov rcall
s_data,addrl wrser
; wrser(addrl)
SPI
ld mov
s_data, X+ p_data,s_data
; save data for
rcall
wrser
; wrser(u_data) SPI
rjmp
w96a
polling << 3) | 0x02;
write (byte 1)
write (byte 2)
polling write (byte 3)
;====== 'R' - Read Program Memory ========================================== w10: cpi
u_data,'R'
; 'R' Read program
w10B device rpm1 s_data,0x28
; S89 device ; read high
wrser
; wrser(0x28)
memory
Byte (order write (byte
<< 3)
write (byte
write (byte read
(byte
brne tst brmi ldi is different from Block Read!) rcall 1) mov rjmp rpm1: mov | 0x01; rcall ori rpm2: rcall 2) mov rcall 3) rcall 4) mov rcall tst brmi ldi
SPI
s_data,addrh rpm2 s_data,addrh
; s_data = (addrh
shift_s_data3 s_data,0x01 wrser
; wrser(addrh) SPI
s_data,addrl wrser
; wrser(addrl) SPI
rdser
;
u_data,s_data putc device rpm3 s_data,0x20
SPI
; send data ; S89 device ; read Low
Byte rcall
wrser
; wrser(0x20)
SPI
mov rcall
s_data,addrh wrser
; wrser(addrh) SPI
mov rcall
s_data,addrl wrser
; wrser(addrl) SPI
rcall
rdser
;
u_data,s_data putc
; send data
addrl,1
; Auto increment
waitcmd
; goto waitcmd();
write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4) mov rcall rpm3: adiw
address rjmp
;====== 'g' - Block Read Memory (See Note 17) ====================== w10B: cpi
u_data,'g'
; 'g' Block Read
Program Memory brne w11 rcall getc mov XH,u_data rcall getc mov XL,u_data rcall getc cpi u_data,'F' breq w10B2 cpi u_data,'E' breq w10B1 rjmp put_err w10B1: rcall read_send_datamem sbiw XL, 1 brne w10B1 rjmp waitcmd w10B2: rcall read_send_progmem tst device
http://avr-asm.tripod.com/isp2313.html (2 of 4)1/20/2009 8:58:51 PM
; XH = getc(); ; XL = getc(); ; getc(Memorytype);
; goto waitcmd();
16 BIT MATH (AVR 202)
brmi sbiw brne rjmp w10B3: sbiw brne rjmp
w10B3 XL, 2 w10B2 waitcmd XL, 1 w10B2 waitcmd
; goto waitcmd();
;====== 'A' - Load Address ================================================= w11: cpi brne rcall mov rcall mov rjmp
u_data,'A' w12 getc addrh,u_data getc addrl,u_data put_ret
; 'A' Load address ; addrh = getc(); ; addrl = getc(); ; goto reply();
;====== 'D' - Write Data Memory ============================================ w12: cpi
u_data,'D'
; 'D' Write data
memory brne w13 rcall getc rcall eeprom_write rjmp put_ret
; get data
;====== 'd' - Read Data Memory ============================================= w13: cpi
u_data,'d'
; 'd' Read data
brne rcall rjmp
w14 read_send_datamem waitcmd
; goto waitcmd();
memory
;====== 'L' - Leave Programming Mode ======================================= w14: cpi
u_data,'L'
; 'L' Leave
programming mode brne w142 w141: pas_RESET release_ports set_LED rjmp put_ret
; set RESET passive ; release ports ; LED off
;====== 'E' - Exit , release all Ports, inhibit AVR910 ===================== w142: cpi u_data,'E' brne w15 rjmp w141
; 'E' xit ; exit command for
AVR Prog ;====== 'e' - Chip Erase =================================================== w15: cpi brne ldi rcall
u_data,'e' w16 s_data,0xac wrser
; 'e' Chip erase
tst brmi ldi rcall
device w151 s_data,0x80 wrser
w151: ldi rcall
s_data,0x04 wrser
; wrser(0x04) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00) SPI
ldi rcall rjmp
temp1,40 delay put_ret
; wrser(0xac) SPI
write (byte 1) ; S89 device ; wrser(0x80) SPI
write (byte 2)
write (byte 3)
write (byte 4)
;====== 'l' ============================================== ; Some more w16: cpi bits brne rcall ldi rcall write (byte 1) tst brmi cpi tn26) breq mov andi 0x06) | 0xe0 ori rcall write (byte 2) ldi rcall write (byte 3) rjmp w163: ldi rcall write (byte 2) ldi rcall write (byte 3) mov ori rcall write (byte 4) rjmp w161: mov andi ori rcall w162: ldi rcall write (byte 4) w164: ldi rcall rjmp
; delay 40mS
- Write Lock Bits different Adresses for other devices? u_data,'l'
; 'l' Write lock
w17 getc s_data,0xac wrser
; get data ; wrser(0xac)
SPI
device w161 device,0x5e
; S89 device ; if (device ==
w163 s_data,u_data s_data,0x06
; (u_data &
s_data,0xe0 wrser
; wrser(u_data) SPI
s_data,0x00 wrser
; wrser(0x00)
SPI
s_data,0xe0 wrser
; tn26 device ; wrser(0xe0)
SPI
s_data,0x00 wrser
; wrser(0x00)
SPI
s_data,u_data s_data,0xfc wrser
; wrser(u_data) SPI
w162
w164 s_data,u_data s_data,0xe0 s_data,0x07 wrser
; S89 device
s_data,0x00 wrser
; wrser(0x00)
temp1,10 delay put_ret
SPI
; delay 10mS
;====== 's' - Read Signature Bytes ========================================= w17: cpi
u_data,'s'
; 's' Read
signature bytes brne tst brmi ldi rcall ldi rcall ldi rcall rjmp w171: rjmp ca17: ldi rcall
w18 device w171 param1,0x02 ca17 param1,0x01 ca17 param1,0x00 ca17 waitcmd
s_data,0x30 wrser
; wrser(0x30)
SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
SPI
mov rcall
s_data,param1 wrser
; wrser(param1) SPI
rcall
rdser
;
mov rcall ret
u_data,s_data putc
; send data
; S89 device ; param1 = 0x02 ; param1 = 0x01 ; param1 = 0x00
put_err
write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4)
;====== 'm' - Write Program Memory Page ==================================== w18: cpi
u_data,'m'
; 'm' Write Program
brne ldi rcall
w19 s_data,0x4c wrser
; wrser(0x4c)
mov
s_data,addrh
; original, reload
mov
s_data,pol_ah
; for speeding up
rcall
wrser
; wrser(addrh) SPI
mov
s_data,addrl
; original, reload
mov
s_data,pol_al
; for speeding up
rcall
wrser
; wrser(addrl) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
rjmp
wait_M
; write FLASH delay
Memory Page
SPI
write (byte 1) ; address transfer write (byte 2) ; address transfer write (byte 3) SPI
write (byte 4)
;====== ':' - Universal Command ============================================ w19: cpi
u_data,':'
brne rcall mov rcall mov rcall mov mov rcall
w20 getc cmd1,u_data getc cmd2,u_data getc cmd3,u_data s_data,cmd1 wrser
mov rcall
; ':' Universal
Command ; ; ; ; ; ;
get data1 cmd1 = data1 get data2 cmd2 = data2 get data3 cmd3 = data3
; wrser(cmd1)
SPI
s_data,cmd2 wrser
; wrser(cmd2)
SPI
mov rcall
s_data,cmd3 wrser
; wrser(cmd3)
SPI
rcall
rdser
;
SPI
mov rcall ldi rcall rjmp
u_data,s_data putc temp1,50 delay put_ret
write (byte 1)
write (byte 2)
write (byte 3) read
(byte 4) ; send data ; delay 50mS
;====== '.' - New Universal Command ======================================== w20: cpi
u_data,'.'
; '.' New Universal
brne rcall mov
w21 getc cmd1,u_data
; get data1 ; cmd1 =
rcall mov
getc cmd2,u_data
; get data2 ; cmd2 =
rcall mov
getc cmd3,u_data
; get data3 ; cmd3 =
rcall mov rcall
getc s_data,cmd1 wrser
; get data4
mov rcall
Command
data1
data2
data3
; wrser(cmd1)
SPI
s_data,cmd2 wrser
; wrser(cmd2)
SPI
mov rcall
s_data,cmd3 wrser
; wrser(cmd3)
SPI
mov rcall
s_data,u_data wrser
; wrser(u_data) SPI
mov rcall ldi rcall rjmp
u_data,rd_s_data putc temp1,50 delay put_ret
write (byte 1)
write (byte 2)
write (byte 3)
write (byte 4) ; send data ; delay 50mS
;====== 'r' - Read Lock Bits ============================================== w21: cpi brne ldi rcall
u_data,'r' w30 s_data,0x58 wrser
; 'r' Read lock bits
; wrser(0x58)
SPI
write (byte 1) ;
ldi s_data,0x00 clr s_data rcall wrser
; wrser(0x00) SPI
ldi rcall
s_data,0x00 wrser
; wrser(0x00)
rcall
rdser
;
mov rcall rjmp
u_data,s_data putc put_ret
; send data
write (byte 2) ;
SPI
write (byte 3) read
SPI
(byte 4)
;====== Unknown Command ==================================================== w30:
rjmp
put_err
;====== Wait for FLASH write in avr910 mode ================================== wait_S: table rcall brcs
Dev_M bel_table ws_pol
; No Page Mode,
put_ret
; in Byte Mode time
poll last Byte rjmp is long enougt to get next Byte... Bws_pol:
; entry adress for
Block mode delay ldi temp3,1 mov B_Flag,temp3
; set Flag that
ws_poll comes back with ret ... ws_pol: tst
PollcodeF
; if polling not
ws_del
; polling not used
p_data,PollcodeF
; if (data ==
breq andi
ws_del pol_cmd,0x0f
; wait default delay ; write command:
ori
pol_cmd,0x20
; read
clr
temp3
; clear polling
applicable, standart delay breq ws_def: cp PollcodeF)
0x48, 0x40 command:
0x28, 0x20 counter ws_cy: tst brmi mov rcall
device ws_89 s_data,pol_cmd wrser
; S89 device ; wrser(pol_cmd)
SPI write (byte 1) mov rjmp ws_89: mov
s_data,pol_ah ws_90
rcall ori ws_90: rcall
shift_s_data3 s_data,0x01 wrser
; wrser(pol_ah) SPI
mov rcall
s_data,pol_al wrser
; wrser(pol_al) SPI
rcall
rdser
;
tst brpl andi
device ws_cb s_data,0x80
; compare only MSB
s_data,pol_ah
; s_data = (pol_ah
<< 3) | 0x01;
write (byte 2) (S89=byte1)
write (byte 3) (S89=byte2) read
SPI
(byte 4) (S89=byte3)
for S89 device andi p_data,0x80 ws_cb: cp s_data,p_data breq ws_ok dec temp3 brne ws_cy ws_del: polling cycles are over, give additional standart Time ldi temp1,10 rcall delay ws_ok: tst B_Flag breq put_ret clr B_Flag normal operation ret
; s_data = p_data ; loop ; 256 ; delay 10mS
; Reset B_Flag for
;====== Wait for FLASH write in page mode ================================== wait_M: cpi breq
device,0x41 wm_del
; polling
cpi breq
device,0x23 poll_t2313
; polling different
cpi
p_data, 0xFF
; if last Byte was
breq andi
wm_del pol_cmd,0x0f
; write command:
ori
pol_cmd,0x20
; read
clr
temp3
; clear polling
s_data,pol_cmd wrser
; wrser(pol_cmd)
mov rcall
s_data,pol_ah wrser
; wrser(pol_ah) SPI
mov rcall
s_data,pol_al wrser
; wrser(pol_al) SPI
rcall
rdser
;
inapplicable for m103
for t2313 0xFF give standart delay
0x48, 0x40 command:
0x28, 0x20 counter wm_cy: mov rcall SPI write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4)
cp s_data,p_data breq wm_ok dec temp3 breq wm_del cycles are over, give another 50ms delay... rjmp wm_cy wm_del: ldi temp1,50 rcall delay wm_ok: tst B_Mode breq wm_end tst Bcnt2 breq wm_end rjmp w95 wm_end: clr B_Mode Flag rjmp put_ret poll_t2313:
; s_data = p_data ; 256 polling ; loop ; delay 50mS
; Reset Block Mode
; Polling
ATTiny2313 is different ldi clr
pol_cmd,0xf0 temp3
; Byte1= 0xF0 ; clear polling
pol_ah,temp3
; Byte2= 0x00
s_data,pol_cmd wrser
; wrser(pol_cmd)
mov rcall
s_data,pol_ah wrser
; wrser(pol_ah) SPI
mov rcall
s_data,pol_al wrser
; wrser(pol_al) SPI
rcall
rdser
;
andi
s_data,0x01
; last Bit tells if
wm_ok temp3 wm_del
; s_data = p_data
p2313_1
; loop
counter mov p2313_1: mov rcall SPI write (byte 1)
write (byte 2)
write (byte 3) read
SPI
(byte 4)
polling OK breq dec breq cycles are over, give another 50ms delay... rjmp
; 256 polling
;====== Command Error ====================================================== put_debug:
; shows u_data on
serial for debug reason rcall putc put_err: ldi u_data,'?' rcall putc rjmp waitcmd
; putc('?') ; send '?'
;====== Reply Command ====================================================== put_ret: ldi rcall rjmp
u_data,0x0d putc waitcmd
; putc(0x0D) ; send CR
; *************************************************************************** ;* ;* TABLE ;* device codes ;* ;* DESCRIPTION ;* The following device codes must be used by the host computer. Note ;* that the device codes are arbitrary selected, they do not have any ;* thing in common with the signature bytes stored in the device. ;* This are the device Codes recognized by the AVRprog Software. Some ;* Devices may require special hardware or a different, not yet ;* implemented Protocol! Use at your own risk. ;* ; *************************************************************************** Dev_S: ; byte write ; avr910-devcode ,Code during polling Flash. 0x00: no polling supported, program default time ; .db 0x10 ,0x00 ;AT90S1200A No support for this type ; .db 0x11 ,0x00 ;AT90S1200B No support for this type ; .db 0x12 ,0x00 ;AT90S1200C No support for this type .db 0x13 ,0x00 ;AT90S1200 .db 0x20 ,0x7F ;AT90S2313A .db 0x28 ,0x7F ;AT90S4414A .db 0x30 ,0xFF ;AT90S4433A .db 0x34 ,0xFF ;AT90S2333A .db 0x38 ,0x7F ;AT90S8515A .db 0x48 ,0xFF ;AT90S2323A .db 0x4C ,0xFF ;AT90S2343A .db 0x51 ,0xFF ;tn10 .db 0x55 ,0xFF ;tn12 .db 0x56 ,0xFF ;tn15 .db 0x68 ,0xFF ;AT90S8535 .db 0x6C ,0xFF ;AT90S4434 .db 0x86 ,0xFF ;AT89S8252 bug in avrprog in Block write Mode!(See Note 18 for Workaround) .db 0x87 ,0xFF ;AT89S53 bug in avrprog .dw 0 ;End of table Dev_M: ; Devices which support Page Programming. Dont forget the Page Size of different Devices. ; Maximum ist 0x40 due to limitated RAM in 2313 Chip. (Pages with bigger Pages are programmed multiple times) ; avr910-devcode ,Pagesite in Words .db 0x23 ,0x10 ;tn2313 avr910-Devicecode not official (STK500 Code used, avrdude.conf modification!) .db 0x3a ,0x20 ;m8515, Pagesize 32 words (0x20) .db 0x3b ,0x20 ;m8515boot Bootloader Mode untested! .db 0x41 ,0x40 ;m103 .db 0x43 ,0x40 ;m128 .db 0x44 ,0x40 ;m128boot Bootloader Mode untested! .db 0x45 ,0x40 ;m64 .db 0x46 ,0x40 ;m64boot Bootloader Mode untested! .db 0x5E ,0x10 ;tn26 .db 0x60 ,0x40 ;m161 .db 0x61 ,0x40 ;m161boot Bootloader Mode untested! .db 0x62 ,0x40 ;m162 .db 0x63 ,0x40 ;m162boot Bootloader Mode untested! .db 0x64 ,0x40 ;m163 .db 0x66 ,0x40 ;m163boot Bootloader Mode untested! .db 0x69 ,0x20 ;m8535 .db 0x6a ,0x20 ;m8535boot Bootloader Mode untested! .db 0x72 ,0x40 ;m32 .db 0x73 ,0x40 ;m32boot Bootloader Mode untested! .db 0x74 ,0x40 ;m16 .db 0x75 ,0x40 ;m16boot Bootloader Mode untested! .db 0x76 ,0x20 ;m8 .db 0x77 ,0x20 ;m8boot Bootloader Mode untested! .db 0x78 ,0x40 ;m169 .db 0x79 ,0x40 ;m169boot Bootloader Mode untested! .db 0x65 ,0x20 ;m83 obsolete .db 0x67 ,0x20 ;m83boot obsolete .db 0x42 ,0x40 ;m603 obsolete .dw 0 ;End of Table
; Devices with known avr910 Devicecodes, but not supported with this Programmer ; .db 0x50 Voltage Hardware and uses different Protocoll! No Support! ; .db 0x58 ; .db 0x5C parallel Programming Mode! ; .db 0x70 Hardware, untested! ; .db 0x71 Hardware, untested! ; .db 0x80 Hardware, untested! ; .db 0x81 Hardware, untested!
;tn11 Needs additional High ;tn19 Obsolete ;tn28 Only supported in ;AT90C8534
unknown
;AT90C8544
unknown
;AT89C1051
unknown
;AT89C2051
unknown
; *************************************************************************** ;* ;* TABLE ;* revision codes ;* ; *************************************************************************** SW_Ver: .db "37",0,0 HW_Ver: .db "12",0,0 ; *************************************************************************** ;* ;* TABLE ;* ID string "AVR ISP" ;* ; *************************************************************************** ID_Str: .db "AVR ISP",0 ; *************************************************************************** ;* ;* TABLE ;* Chip ID string to identify the Firmware ;* ; *************************************************************************** ChipID: .db "Ver.3.7e (AVR109 Mode, 7.3728Mhz, 115.200 baud) for AN910, AT90S2313" .db "www.mikrocontroller-projekte.de 14.Jan.2005",0 ;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and http://avr-asm.tripod.com/isp2313.html (3 of 4)1/20/2009 8:58:51 PM
16 BIT MATH (AVR 202)
Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/isp2313.html (4 of 4)1/20/2009 8:58:51 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ISP FOR 1200 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* Title : AVR ISP (Auto adr inc, 19200bps) ;* Version : 2.0 ;* Last updated : 1998.01.06 (mlund) ;* Target : AT90S1200 ;* File : ispprog.asm ;* Author : Atmel Norway ;* ;* DESCRIPTION ;* The firmware on all programmers now support a unified protocol for ;* program and data memory programming. The host computer do not need ;* to know if the programmer operates in serial or parallel mode. ;* ;* The following commands are supported. All commands start with a ;* single letter. The programmer returns 13d (carriage return) or the ;* data read after the command is finished. ;* ;* +------------+------------+------+ ;* Commands | Host writes | Host reads | | ;* -------+-----+------+------+-----+ | ;* | ID | data | data | | Note | ;* +-----------------------------------+-----+------+------+-----+------+ ;* | Enter programming mode | 'P' | | | 13d | 1 | ;* | Set address | 'A' | ah al | | 13d | 2 | ;* | Write program memory, low byte | 'c' | dd | | 13d | 3 | ;* | Write program memory, high byte | 'C' | dd | | 13d | 3 | ;* | Issue Page Write | 'm' | | | 13d | | ;* | Read program memory | 'R' | |dd (dd)| | 4 | ;* | Write data memory | 'D' | dd | | 13d | | ;* | Read data memory | 'd' | | dd | | | ;* | Chip erase | 'e' | | | 13d | | ;* | Write lock bits | 'l' | dd | | 13d | | ;* | Write fuse bits | 'f' | dd | | 13d | 11 | ;* | Read fuse and lock bits | 'F' | | dd | | 11 | ;* | Leave programming mode | 'L' | | | 13d | 5 | ;* | Select device type | 'T' | dd | | 13d | 6 | ;* | Read signature bytes | 's' | | 3*dd | | | ;* | Return supported device codes | 't' | | n*dd | 00d | 7 | ;* | Return software identifier | 'S' | | s [7] | | 8 | ;* | Return sofware version | 'V' | | dd dd | | 9 | ;* | Return hardware version | 'v' | | dd dd | | 9 | ;* | Return programmer type | 'p' | | dd | | 10 | ;* | Set LED | 'x' | dd | | 13d | 12 | ;* | Clear LED | 'y' | dd | | 13d | 12 | ;* | Universial command | ':' | 3*dd | dd | 13d | | ;* +-----------------------------------+-----+------+------+-----+------+ ;* ;* NOTE 1 ;* The Enter programming mode command MUST be sent one time prior to ;* the other commands, with the exception of the 't', 'S', 'V', 'v' ;* and 'T' commands. The 'T' command must be sent before this command ;* (see note 6). ;* ;* For programmers supporting both parallel and serial programming ;* mode this command enters parallel programming mode. For programmers ;* supporting only serial programming mode, this command enters serial ;* programming mode. ;* ;* NOTE 2 ;* The ah and al are the high and low order bytes of the address. For ;* parallel programmers this command issues the Load Address Low/High ;* Byte command. For serial programmers the address byte is stored for ;* use by the Read/Write commands. ;* ;* NOTE 3 ;* For parallel programmers this command issues the Program Flash ;* command. For serial programmers this command iussues the Write ;* Program Memory Command. For devices with byte-wide program memories ;* only the low byte command should be used. ;* ;* NOTE 4 ;* The contents of the program memory at the address given by the 'A' ;* command are written to the serial port in binary form. For byte ;* wide memories one byte is written. For 16 bit memories two bytes ;* are written,MSB first. ;* ;* NOTE 5 ;* This command must be executed after the programming is finished. ;* ;* NOTE 6 ;* The select device type command must be sent before the enter ;* programming command ;* ;* NOTE 7 ;* The supported device codes are returned in binary form terminated ;* by 0x00. ;* ;* NOTE 8 ;* This return a 7 character ASCII string identifying the programmer. ;* For the in-system programmer it is "AVR ISP". ;* ;* NOTE 9 ;* The software/hardware version are returned as two ASCII numbers. ;* ;* NOTE 10 ;* This command should be used to identify the programmer type. The ;* return value is 'S' for serial (or SPI) programmers or 'P' for ;* parallel programmers. ;* ;* NOTE 11 ;* The write fuse bits command are available only on parallel ;* programmers and only for AVR devices (device code < 0x80). The host ;* should use the return programmer type command to determine the ;* programmer type, do not use the "AVR PPR" idenifier because other ;* programmers may be available in the future. ;* ;* NOTE 12 ;* Currently only the AVR development board has LEDs. The other boards ;* must implement this commands as NOPs. ;* ;* NOTE 13 ;* Devices using Page Mode Programming write one page of flash memory ;* before issuing a Page Mode Write Pulse. ; *************************************************************************** ;**** includes **** .include "1200def.inc" ; *************************************************************************** ;* ;* CONSTANTS ;* device codes ;* ;* DESCRIPTION ;* The following device codes must be used by the host computer. Note ;* that the device codes are arbitrary selected, they do not have any ;* thing in common with the signature bytes stored in the device. ;* ;* The following devices are supported (make a new table for each ;* software release): ;* ;* SW_MAJOR=1, SW_MINOR=5 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ;* SW_MAJOR=1, SW_MINOR=6 ;* AT90S1200 rev. C (abbreviated S1200C) ;* AT90S1200 rev. D (abbreviated S1200D) ;* AT90S8515 rev. A (abbreviated S8515A) ;* AT89S8252 (abbreviated S8252) ;* ATmega103 rev. A (abbreviated S01838A) ;* ; *************************************************************************** .equ .equ .equ .equ .equ .equ .equ
S1200C S1200D S2313A S4414A S8515A S8252 S2323A
= = = = = = =
0x12 0x13 0x20 0x28 0x38 0x86 0x48
.equ .equ
S01838C = 0x40 S01838D = 0x41
;**** Revision Codes **** .equ
SW_MAJOR = 2
; Major SW revision
.equ
SW_MINOR = 0
; Minor SW revision
.equ
HW_MAJOR = 1
; Major HW revision
.equ
HW_MINOR = 0
; Minor HW revision
number number number number
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following four macros if the RESET pin to the ;* target moves and/or if the SCK/MISO/MOSO moves. ;* ; *************************************************************************** .macro sbi .endm
set_reset portb,4
.macro cbi .endm
clr_reset portb,4
.macro nop ; sbi .endm
ddrd_init
.macro ldi out
ddrb_init temp1,0xdf ddrb,temp1
; PB5 is input, the rest is
ddrb_release temp1,(1<
; PB4 (RESET) is output,
ddrd,3
output .endm .macro ldi out the rest is input .endm .macro sbi ldi m0: dec brne cbi ldi m1: dec brne .endm
pulse_sck portb,SCK temp2,6 temp2 m0 portb,SCK temp2,1 temp2 m1
; 3
;***************** ;* SPI Constants * ;***************** .equ
MOSI
= 6
; Bit number on
.equ
MISO
= 5
; Bit number on
.equ
SCK
= 7
; Bit number on
PORTB PORTB PORTB
;****************** ;* UART Constants * ;****************** ;**** Constant declarations Data Rate **** ;.equ
N = 95
; 115200 BAUD when
;.equ
N = 31
; 57600 BAUD when
;.equ
N = 43
; 38400 BAUD when
.equ
N = 33
; 19200 BAUD when
;.equ
N = 102
; 38400 BAUD when
.equ
R = 2
R=1 and XTAL=11.059MHz R=2 and XTAL=11.059MHz R=2 and XTAL=11.059MHz R=2 and XTAL=4.00MHz R=1 and XTAL=4.00MHz
;**** UART transmit pin in PORTD **** .equ .equ
TXPIN = 1 RXPIN = 0
; Receive pin must
be external interrupt !! ;**** Bit positions in UART Status Register **** .equ .equ
TXC = 0 RXC = 1
; Transmit ; Receive
;***************************** ;* Global Register Variables * ;***************************** .def .def .def .def .def .def
device temp1 temp2 s_data u_data addrl
= = = = = =
r16 r17 r18 r19 r20 r21
; Device code
.def
addrh
= r22
.def
bit_cnt = r23
; Bit count used by
.def
u_stat
= r24
; Status byte used
.def
cmd
= r25
; Serial
.def
count
= r26
; Time out variable
.def .def .def .def
param1 cmd1 cmd2 cmd3
= = = =
; SPI data ; UART data ; Low order byte of
address ; High order byte
of address UART routine by UART routine programming command for "enter programming mode" r27 r28 r29 r30
;********************* ;* Interrupt Vectors * ;********************* .CSEG rjmp reti rjmp reti
RESET
; ; ; ;
TIM0_OVF
Reset Handle IRQ0 Handle (not used) Timer0 Overflow Handle Analog Comparator Handle
(not used)
; *************************************************************************** ;* ;* INTERRUPT ;* TIM0_OVF - Software UART Service Routine ;* ; *************************************************************************** TIM0_OVF: in ldi out
r0,SREG ; store SREG temp1,(256-N+8) TCNT0,temp1 ; reset T/C0 to one bit
lenght inc sbrs
bit_cnt u_stat,TXC
; increment bit counter ; if (transmit complete
rjmp
transmit
;
sec PIND,RXPIN u_data
; set carry ; if (RxD == LOW) ; clear carry ; shift carry into u_data
bit_cnt,8 to_1 temp1
; if (bit_cnt == 8) ; { ; disable T/C0 Overflow
TIMSK,temp1 u_stat,1<
;
flag clear)
to_0: sbis clc ror cpi brne clr
goto transmit
Interrupt out sbr to_1: out reti transmit: cpi
SREG,r0
set receive complete ; } ; restore SREG ; exit
bit_cnt,1
; if (bit_cnt == 1)
\\
brne cbi rjmp to_2: cpi
to_2 PORTD,TXPIN to_1
; { ; ;
bit_cnt,10
generate start bit exit ; } ; if (bit_cnt == 10) \\
brne sbi clr
to_3 PORTD,TXPIN temp1
; { ; ;
generate stop bit disable TC0
out sbr
TIMSK,temp1 u_stat,1<
;
set transmit
to_1
;
u_data,0 PORTD,TXPIN u_data,0 PORTD,TXPIN u_data to_1
; ; ; ; ; ;
start bit
stop bit
overflow interrupt
complete bit rjmp to_3: sbrc sbi sbrs cbi lsr rjmp
exit ; } if (LSB set) PD3 = HIGH if (LSB clear) PD3 = LOW shift left u_data exit
; *************************************************************************** ;* ;* FUNCTION ;* u_init ;* ;* DESCRIPTION ;* Initialize UART. ;* ; *************************************************************************** u_init: ldi out sbi cbi ret
ldi u_stat,1<
; *************************************************************************** ;* ;* FUNCTION ;* putc ;* ;* DESCRIPTION ;* Send a character on the UART Tx line. ;* ; *************************************************************************** putc:
clr
u_stat
; clear UART status
flags clr ldi
bit_cnt temp1,1<
; clear bit counter ; enable T/C0 overflow
interrupt out putc0:
TIMSK,temp1 sbrs u_stat,TXC
; while (!(u_stat &
TXC)); // Wait for TXC rjmp ret
putc0
; *************************************************************************** ;* ;* FUNCTION ;* getc ;* ;* DESCRIPTION ;* Wait for start bit and receive a character on the UART Rx line. ;* ; *************************************************************************** getc: rjmp getc0: rjmp ldi out
sbis PIND,RXPIN getc sbic PIND,RXPIN getc0 temp1,(256-(N+N/2)+8+12); TCNT0,temp1 ; preset T/C0 to 1.5 bit
lengths ldi out out
temp1,1<
; clear T/C0 overflow flag ; enable T/C0 overflow
Interrupt clr getc1:
bit_cnt ; clear bit counter sbrs u_stat,RXC ; wait for Receive
Complete rjmp cbr ret
getc1 u_stat,1<
; clear RXC
; *************************************************************************** ;* ;* FUNCTION ;* delay ;* ;* DESCRIPTION ;* Make a small delay. ;* ; *************************************************************************** delay: dl: dec brne dec brne ret
ldi temp2 dl temp1 delay
temp2,0xff
; *************************************************************************** ;* ;* FUNCTION ;* wrser ;* ;* DESCRIPTION ;* Write a byte to the SPI. ;* ; *************************************************************************** wrser: wrs0: brcc sbi rjmp wrs1: wrs2: dec brne ret
ldi temp1,8 rol s_data wrs1 portb,MOSI wrs2 cbi portb,MOSI pulse_sck temp1 wrs0
; *************************************************************************** ;* ;* FUNCTION ;* rdser ;* ;* DESCRIPTION ;* Read a byte from the SPI. ;* ; *************************************************************************** rdser: ldi temp1,8 ldi s_data,0 rd0: lsl s_data sbic pinb,MISO ori s_data,1 pulse_sck dec temp1 brne rd0 ret
; *************************************************************************** ;* ;* FUNCTION ;* spiinit (Enter programming mode) ;* ;* DESCRIPTION ;* Initialize SPI interface on AVR or 'AT89 device. ;* ; *************************************************************************** spiinit:ddrd_init ddrb_init cbi portb,SCK cpi device,S8252 breq s89 set_reset ldi temp1,0xff rcall delay clr_reset rjmp s0
; ; ; ; ; ; ;
initialize port D initialize port B clear SCK if (device != S8252) { set RESET = 1 delay(0xff);
; ; } ; else
s89:
set RESET = 0
clr_reset ldi temp1,0xff rcall delay set_reset s0:
; ;
; { set RESET = 0 delay(0xff);
; set RESET = 1 ; } ; delay(0xff);
ldi rcall
temp1,0xff delay
ldi
s_data,0xac
; wrser(0xac);
//
rcall ldi
wrser s_data,0x53
; wrser(0x53);
//
rcall
wrser
SPI write (byte 1)
SPI write (byte 2)
; // SPI Synchronization (fix!) cpi
device,0x20
brlo tst brmi
s2 device s2
; if ( (device >= 0x20) &&
(device <= 0x7F) )
s0b: ldi
count,32
rcall
rdser
; ; ;
cpi breq
s_data,0x53 s3
;
ldi
s_data,0x00
;
wrser
rcall wrser pulse_sck ldi s_data,0xac
; ;
pulse SCK wrser
rcall ldi
wrser s_data,0x53
;
wrser
rcall dec brne rjmp
wrser count s1 s3
ldi
s_data,0x00
rcall
wrser
s1: == 0x53)
; { count = 32; do { if (rdser
// SPI read (byte 3)
break; (0x00);
(0xac);
// SPI write (byte 4)
(0x53);
// SPI write (byte 1)
// SPI write (byte 2)
s2: (0x00);
;
} while(--count);
; } ; else ; { ;
wrser
// SPI write (byte 3) s3: cpi breq ldi
device,S8252 s4 s_data,0x00
rcall
wrser
; } ; if (device != S8252) ; { ; wrser(0x00);
//
SPI write (byte 4) s4: ldi rcall ret
temp1,0x10 delay
; } ; delay(0x10);
; *************************************************************************** ;* ;* FUNCTION ;* show_id ;* ;* DESCRIPTION ;* Show our ID ("AVR ISP") on the serial line. ;* ; *************************************************************************** show_id:ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ret
u_data,0x41 putc u_data,0x56 putc u_data,0x52 putc u_data,0x20 putc u_data,0x49 putc u_data,0x53 putc u_data,0x50 putc
; 'A' ; 'V' ; 'R' ; ' ' ; 'I' ; 'S' ; 'P'
; *************************************************************************** ;* ;* RESET ;* ;* DESCRIPTION ;* Initialization ;* ; *************************************************************************** RESET: clr temp1 out GIMSK,temp1 ser temp1 out PORTD,temp1 set_reset out PORTB,temp1 ddrb_release rcall u_init sei
; disable external interrupt ; Initialize ; set RESET=1
; Initialize UART ; Enable interrupts
; *************************************************************************** ;* ;* PROGRAM ;* waitcmd -> main ;* ;* DESCRIPTION ;* Wait for and execute commands. ;* ; *************************************************************************** waitcmd:rcall
getc
; while (getc() ==
ESC) {}; cpi breq
u_data,0x1b waitcmd
;**** Device Type **** cpi brne rcall mov rjmp
u_data,0x54 w0 getc device,u_data put_ret
; 'T' Device type ; getc(); // dummy ; putc(device);
;**** Return Software Identifier **** w0: cpi
u_data,0x53
; 'S' Return software
w1 show_id waitcmd
; show_id();
identifier brne rcall rjmp
;**** Return Software Version **** w1: cpi brne ldi rcall ldi rcall rjmp
u_data,0x56 ;'V' Return software version w2 u_data,0x30+SW_MAJOR ; putc(0x30+SW_MAJOR); putc u_data,0x30+SW_MINOR ; putc(0x30+SW_MINOR); putc waitcmd
;**** Return Hardware Version **** w2: cpi brne ldi rcall ldi rcall rjmp
u_data,0x76 ;'v' Return hardware version w3 u_data,0x30+HW_MAJOR ; putc(0x30+HW_MAJOR); putc u_data,0x30+HW_MINOR ; putc(0x30+HW_MINOR); putc waitcmd
;**** Show Supported Devices **** w3: cpi brne ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall ldi
u_data,0x74 w4 u_data,S1200C putc u_data,S1200D putc u_data,S2313A putc u_data,S4414A putc u_data,S8515A putc u_data,S2323A putc u_data,S8252 putc u_data,0x00
; 't' Show supported devices ; putc(S1200C); ; putc(S1200D); ; putc(S2313A); ; putc(S4414A); ; putc(S8515A); ; putc(S2323A); ; putc(S8252); ; putc(0x00);
// end of
device list rcall rjmp
putc waitcmd
;**** Return Programmer Type **** w4: cpi brne ldi
u_data,0x70 w5 u_data,0x53
; 'p' Return programmer type ; putc('S');
// serial
programmer rcall rjmp
putc waitcmd
;**** Set LED **** w5: cpi brne rjmp
u_data,0x78 w6 put_ret
; 'x' Set LED (ignored)
;**** Clear LED **** w6: cpi brne rjmp
u_data,0x79 w7 put_ret
; 'y' Clear LED (ignored)
;**** Enter Programming Mode **** ; We require that the device code be selected before any of the other commands w7: cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq cpi breq rjmp w72:
device,S1200C w72 device,S1200D w72 device,S8515A w72 device,S4414A w72 device,S2313A w72 device,S8252 w72 device,S01838C w72 device,S01838D w72 device,S2323A w72 put_err cpi
; if ((device != S1200C) && ;
(device != S1200D) &&
;
(device != S8515A) &&
;
(device != S4414A) &&
;
(device != S2313A) &&
;
(device != S8252) &&
;
(device != S01838C) &&
;
(device != S01838D) &&
;
(device != S2323A))
;
goto put_err();
u_data,0x50
; 'P' Enter
programming mode brne rcall rjmp
w8 spiinit put_ret
; spiinit();
;**** Wait Program Memory **** ;* USAGE ;* wait_pm(byte cmd, byte c_data); ;* ;* cmd : 0x28 - wait for high byte written ;* 0x20 - wait for low byte written ;* u_data : current data written ;wait_pm: ; ; mov (cmd); // SPI write (byte 1) ; rcall ; mov (addrh); // SPI write (byte 2) ; rcall ; mov (addrl); // SPI write (byte 3) ; rcall ; rcall (); // SPI read (byte 4) ; ; ;
cp brne ret
s_data,cmd
; do ; { ;
wrser
wrser s_data,addrh
;
wrser
wrser s_data,addrl
;
wrser
wrser rdser
;
s_data = rdser
s_data,u_data wait_pm
; } ; while(s_data != u_data);
;**** Write Program Memory, High Byte **** w8: cpi
u_data,0x43
; 'C' Write program memory,
high byte brne rcall cpi brne rjmp
w9 getc device,S8252 w81 put_err
; if (device == S8252) ; { ; goto err(); ; // (AT89 series
have byte wide program memory !)
(0x48);
w81: // SPI write (byte 1)
ldi
; } s_data,0x48
; wrser
rcall mov
wrser s_data,addrh
; wrser(addrh);
//
rcall mov
wrser s_data,addrl
; wrser(addrl);
//
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
SPI write (byte 2)
SPI write (byte 3)
C! brne com w81b: mov
w81b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq
w82 device,S01838D w82
ldi
temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
ldi
temp1,0x01
; Auto increment
clr add adc rjmp
temp2 addrl,temp1 addrh,temp2 put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w82: address
http://avr-asm.tripod.com/isp1200.html (1 of 3)1/20/2009 8:59:30 PM
!!!!
16 BIT MATH (AVR 202)
;**** Write Program Memory, Low Byte **** w9: cpi
u_data,0x63
; 'c' Write program memory,
low byte brne rcall
w12 getc
cpi breq ldi
device,S8252 w989 s_data,0x40
rcall mov rjmp
wrser s_data,addrh w91
; if (device != S8252) ; { ; wrser(0x40);
//
SPI write (byte 1)
w989: mov
s_data,addrh
; ; } ; else
s_data = addrh;
; { s_data = (addrh <<
;
3) | 0x02; rcall ori
shift_s_data3 s_data,0x02
w91: rcall
wrser
; } ; wrser(s_data);
mov
s_data,addrl
; wrser(addrl);
rcall cpi
wrser device,S01838C
; invert data on 01838 rev
// //
SPI write (byte 2) SPI write (byte 3)
C! brne com w91b: mov
w91b u_data s_data,u_data
; wrser(u_data);
//
rcall cpi
wrser device,S01838C
; no delay for S01838 (Uses
breq cpi breq ldi
w92 device,S01838D w92 temp1,0x20
; delay(0x20);
//
rcall
delay
;
//
put_ret
; goto reply();
SPI write (byte 4)
Page Write Mode instead)
24585 cycles delay Page mode requires no delay! w92: rjmp
;**** Read Program Memory **** w12:
cpi
u_data,0x52
; 'R' Read program
memory brne cpi breq ldi
w10 device,S8252 w1289 s_data,0x28
rcall mov rjmp
wrser s_data,addrh w121
; ; if (device != S8252) ; { ; wrser(0x28);
//
SPI write (byte 1)
w1289: mov
s_data,addrh
; ; } ; else
s_data = addrh;
; { s_data = (addrh <<
;
3) | 0x01; rcall ori w121: rcall
shift_s_data3 s_data,0x01 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall cpi brne rjmp
u_data,s_data putc device,S8252 w122 waitcmd
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
s_data,0x20
if (device == S8252) { goto waitcmd(); } else ; { ; wrser(0x20); //
rcall mov
wrser s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall rcall
wrser rdser
;
putc(rdser());
//
mov rcall
u_data,s_data putc
ldi
temp1,0x01
;
Auto increment
clr add adc
temp2 addrl,temp1 addrh,temp2
rjmp
waitcmd
; ; }
goto waitcmd();
w122: ldi
; ; ; ; ;
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
Send data (byte 4)
address
!!!!
shift_s_data3: lsl s_data lsl s_data lsl s_data ret ;**** Load Address **** w10: brne rcall mov rcall mov rjmp
cpi u_data,0x41 ; 'A' Load address w11 getc ; addrh = getc(); addrh,u_data getc ; addrl = getc(); addrl,u_data put_ret ; goto reply();
;**** Write Data Memory **** w11:
cpi
u_data,0x44
; 'D' Write data
memory brne rcall cpi breq
w13 getc device,S8252 w1189
ldi rcall mov rjmp
s_data,0xc0 wrser s_data,addrh w111
w1189: rcall ori
mov s_data,addrh shift_s_data3 s_data,0x06
w111: mov rcall mov rcall ldi rcall rjmp
rcall wrser s_data,addrl wrser s_data,u_data wrser temp1,0x20 delay put_ret
;;**** Read Data Memory **** w13:
cpi
u_data,0x64
; 'd' Read data
memory brne cpi breq ldi
w14 device,S8252 w1389 s_data,0xa0
rcall mov rjmp
wrser s_data,addrh w131
; if (device != S8252) ; { ; wrser(0xA0);
//
SPI write (byte 1)
w1389: mov
s_data,addrh
; ; } ; else
s_data = addrh;
; { s_data = (addrh <<
;
3) | 0x05; rcall ori w131: rcall
shift_s_data3 s_data,0x05 wrser
; } ; wrser(s_data);
//
mov
s_data,addrl
; wrser(addrl);
//
rcall rcall
wrser rdser
; putc(rdser());
//
mov rcall rjmp
u_data,s_data putc waitcmd
; goto waitcmd();
SPI write (byte 2) SPI write (byte 3)
Send data (byte 4)
;**** Leave Programming Mode **** w14:
cpi
u_data,0x4c
; 'L' Leave
programming mode brne w15 ddrb_release cpi device,S8252 breq w141 set_reset rjmp put_ret w141: clr_reset rjmp put_ret
; set RESET = 1 ; set RESET = 0
;**** Chip Erase **** w15:
cpi
u_data,0x65 brne w16 ldi s_data,0xac rcall wrser cpi device,S8252 breq w1589 ldi s_data,0x80 rcall wrser w1589: ldi s_data,0x04 rcall wrser ldi s_data,0x00 rcall wrser ldi temp1,0x30 rcall delay rjmp put_ret
; 'e' Chip erase
;**** Write Lock Bits **** w16:
cpi
u_data,0x6c
; 'l' Write lock
bits brne rcall ldi rcall mov cpi breq andi ori rcall ldi rcall rjmp w1689: ori rcall w162: rcall ldi rcall rjmp
w17 getc s_data,0xac wrser s_data,u_data device,S8252 w1689 s_data,0x06 s_data,0xe0 wrser s_data,0x00 wrser w162 andi s_data,0xe0 s_data,0x07 wrser ldi s_data,0x00 wrser temp1,0x30 delay put_ret
;**** Read Signature Bytes **** w17:
cpi
u_data,0x73
brne cpi brne rjmp w17begin: ldi rcall ldi rcall ldi rcall rjmp
w18 device,S8252 w17begin put_err
w17call:ldi rcall ldi rcall mov rcall rcall mov rcall ret
s_data,0x30 wrser s_data,0x00 wrser s_data,param1 wrser rdser u_data,s_data putc
; 's' Read
signature bytes
param1,0x02 w17call param1,0x01 w17call param1,0x00 w17call waitcmd
;**** Write Program Memory Page **** w18:
cpi
u_data,0x6D
; 'm' Write Program
Memory Page brne
w19
ldi
s_data,0x4c
rcall
wrser
mov
;
wrser(0x4c);
//
s_data,addrh
;
wrser(addrh);
//
rcall mov
wrser s_data,addrl
;
wrser(addrl);
//
rcall
wrser
ldi
s_data,0x00
;
wrser(0x00);
//
rcall ldi
wrser temp1,0xff
;
delay(0xFF);
//
rcall rjmp
delay put_ret
SPI write (byte 1)
SPI write (byte 2)
SPI write (byte 3)
SPI write (byte 4)
0x20 = 24585 cycles delay
;**** Universal Command **** w19:
cpi
u_data,0x3A
; ':' Universal
Command brne
w99
rcall mov rcall mov rcall mov rcall ldi
getc cmd1,u_data getc cmd2,u_data getc cmd3,u_data universal temp1,0xff
rcall rjmp
delay put_ret
;
delay(0xFF);
//
0x20 = 24585 cycles delay
universal: mov rcall mov rcall mov rcall rcall mov rcall ret
s_data,cmd1 wrser s_data,cmd2 wrser s_data,cmd3 wrser rdser u_data,s_data putc
w99: ;**** Command Error **** put_err:ldi u_data,0x3f rcall putc rjmp waitcmd
; putc('?');
\\ send '?'
; putc(0x0D);
\\ send CR
;**** Reply Command **** put_ret:ldi u_data,0x0d rcall putc rjmp waitcmd ;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on http://avr-asm.tripod.com/isp1200.html (2 of 3)1/20/2009 8:59:30 PM
16 BIT MATH (AVR 202)
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/isp1200.html (3 of 3)1/20/2009 8:59:30 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR SPI PROTOCOL HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202
MATH YX DIV16 XX
FLOAT 128
MATH 202 DEC ASCII
COPY 102
UART 128
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
;*
interface routines, and do not inherently contain a
;*
structure; that is dictated by the connected SPI
;* ;*
Due to having separate Enable/Disable and Read/
;*
routines, larger blocks of data can be sent simply
;*
the RW_SPI routine multiple times before disabling /
These routines are low-
;* ;*
ena_spi:
forces SCK low, and activates /SS signal. No calling requirements, returns
;* ;*
disa_spi: brings /SS signal hi (inactive). No calling requirements, returns
;*
rw_spi:
nothing. sends/receives a an 8-bit or 16-bit data
word. ;*
Must set up data to be sent in
;*
prior to calling; it returns
;*
the same register pair (if 8-bit,
(spi_hi,spi_lo) received data in uses only ;* the spi_lo register). ;* ;* VARIABLES: ;* The spi_hi and spi_lo variables are the high and low data bytes. ;* ;* ;*
AVR SPI
I2C/TWI 128
store the new received bit.
nothing.
ISP 1200
I2C TWI26
;*
nothing.
AVR ISP
I2C 302
is shifted out (transmitted), the vacated bit
;* ;* MAJOR ROUTINES: ;* init_spi: initializes the port lines used for SPI. ;* No calling requirements, returns
USB 232
I2C 300
;*
SS.
UART BUFF
ISP 2313
registers is used both to send and to receive; i.
by calling
XMODEM REC
UART 305
;*
Data is sent and received MSB-first.
Write-Word
VFX MEM
UART 304
word format.
peripheral(s).
FLASH CARD
CRC 236
;*
command
SER EPROM
SORT 220
It simultaneously transmits and receives SPI data
level
EPROM 100
VFX SMIL
;*
position is used to
LPM 108
DFLASH AT45
DESCRIPTION This is a collection of 8/16-bit word, Mode 0,
e., when one bit
AVG8 222 FFT7
:[email protected]
One pair of
INT ASCII HX2ASC
Support E-mail
in 8- or 16-bit
SQRT16 MATH 202
Title : Software SPI Master Version : 1.0 Last updated : 98.04.21 Target : AT90S1200 Easily modified for : Any AVR microcontroller
Master SPI routines.
DIV 24 24 DIV 3216
A V R 3 2 0
*****************
ASM MATH
MATH 32X
N O T E
They can be located anywhere in the register file. The temp variable holds the bit count, and is also
used in timing ;*
the high/low minimum pulse width.
This must be
located in an ;*
upper register due to the use of an IMMEDIATE-mode
instruction. ;* ;* HISTORY ;* V1.0 98.04.21 (rgf) Created ;* ; ***************************************************************************
TEA ADC 128
;**** includes ****
ADC 10B ADC 400
.include "1200def.inc"
;you can change
this to any device
ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
; *************************************************************************** ;* ;* CONSTANTS ;* ; ***************************************************************************
KBD PS2
;**** Revision Codes ****
KBD PC/128 PS2 EMU
ALM CLK
; Major SW revision
.equ
SW_MINOR = 0
; Minor SW revision
.equ
HW_MAJOR = 0
; Major HW revision
.equ
HW_MINOR = 0
; Minor HW revision
number number
CLOCK 8564 90 DAYS
SW_MAJOR = 1
number
BOOT MG8 BOOT DR8
.equ
number
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
; *************************************************************************** ;* ;* PORT DEFINITIONS ;* ; *************************************************************************** .equ .equ .equ .equ
ATMEL CORP AVR BUTTERFLY
sck nss mosi miso
= = = =
0 1 2 3
;PB0 ;PB1 ;PB2 ;PB3
pin pin pin pin
AVR BOOK
; *************************************************************************** ;* ;* REGISTER DEFINITIONS ;* ; *************************************************************************** .def .def .def
spi_lo spi_hi temp
=r0 =r1 =r16
;change as needed ; " ;misc usage, must be in
upper regs for IMMED mode
; *************************************************************************** ;* ;* MACROS ;* Program Macros ;* ;* DESCRIPTION ;* Change the following macros if a port other than PORTB is used. ;* ; *************************************************************************** .macro cbi .endm
ss_active portb,nss
.macro sbi .endm
ss_inactive portb,nss
.macro sbi .endm
sck_hi portb,sck
.macro cbi .endm
sck_lo portb,sck
.macro sbi .endm
mosi_hi portb,mosi
.macro cbi .endm
mosi_lo portb,mosi
.macro subi
addi @0, -@1
;subtract the negative of
an immediate value .endm .macro
set_delay
;set up the time
delay amount, from 1 to 7 subi
@0, (@1 << 5)
;NOTE: THIS shift affects
INC macro (below)! .endm .macro
inc_delay
;bump the delay
counter subi
@0, -(1 << 5)
;shift value here must be
same as above! .endm
; *************************************************************************** ;* ;* SAMPLE APPLICATION, READY TO RUN ON AN AT90S1200 ;* ; *************************************************************************** .cseg .org Rvect:
0 rjmp
Reset
; *************************************************************************** ;* ;* FUNCTION ;* init_spi ;* ;* DESCRIPTION ;* Initialize our port pins for use as SPI master. ;* ;* CODE SIZE: ;* 8 words ;* ; *************************************************************************** init_spi: ss_inactive sbi ddrb,nss ; sck_lo sbi ddrb,sck ; mosi_lo sbi ddrb,mosi ; cbi ddrb,miso
;set latch bit hi (inactive) ;make it an output ;set clk line lo ;make it an output ;set data-out lo ;make it an output ;not really required, it
powers up clr'd! ret
; *************************************************************************** ;* ;* FUNCTION ;* ena_spi ;* ;* DESCRIPTION ;* Init data & clock lines, then assert /SS. Note that if more than ;* one slave is used, copies of this could be made that would each ;* reference a different /SS port pin (use SS_ACTIVE0, SS_ACTIVE1, ...) ;* ;* CODE SIZE: ;* 4 words ;* ; *************************************************************************** ena_spi: sck_lo
;(should already be
there...) mosi_lo ss_active ret
; *************************************************************************** ;* ;* FUNCTION ;* disa_spi ;* ;* DESCRIPTION ;* De-assert /SS. Since this routine is so short, it might be better ;* to use the SS_INACTIVE statement directly in higher level code. ;* Again, if multiple slaves exist, additional copies of this could ;* be created; or ONE routine that disabled ALL /ss signals could be ;* used instead to make the code less error-prone due to calling the ;* wrong Disable routine. ;* ;* CODE SIZE: ;* 2 words ;* ; *************************************************************************** disa_spi: ss_inactive ret
; *************************************************************************** ;* ;* FUNCTION ;* rw_spi ;* ;* DESCRIPTION ;* Write a word out on SPI while simultaneously reading in a word. ;* Data is sent MSB-first, and info read from SPI goes into ;* the same buffer that the write data is going out from. ;* Make sure data, clock and /SS are init'd before coming here. ;* SCK high time is ((delay * 3) + 1) AVR clock cycles. ;* ;* If 8-bit use is needed, change LDI TEMP,16 to ,8 and also ;* eliminate the ROL SPI_HI statement. ;* ;* CODE SIZE: ;* 21 words ;* NUMBER OF CYCLES: ;* Overhead = 8, loop = 16 * (16 + (2* (delay_value*3))) ; (With call + return + delay=4, it is about 648 cycles.) ;* ; *************************************************************************** rw_spi: ldi
temp,16
;init loop counter to 16
bits ;ldi temp,8
;use THIS line instead if 8-
bit desired ; spi_loop: lsl
spi_lo
;move 0 into D0, all other
spi_hi
; and C ends up being first
bits UP one slot, rol bit to be sent. ;If 8-bit desired, also comment out the preceding ROL SPI_HI statement ; brcc lo_mosi mosi_hi rjmp mosi_done
;this branch creates setup
time on MOSI lo_mosi: mosi_lo nop
;also create setup time on
MOSI mosi_done: ; sck_hi ; ;must now time the hi pulse - not much else we can do here but waste time ; set_delay temp,4
;(4 * 3) cycle delay; range
is from 1 to 7! time_hi: inc_delay temp
;inc upper nibble until it
rolls over; then, brcs
time_hi
; C gets CLEARED, & temp
has original value ; sck_lo ;drop clock line low ; ;must now delay before reading in SPI data on MISO ; set_delay temp,4 time_lo: inc_delay temp brcs time_lo ; sbic pinb,miso ;after delay, read in SPI bit & put into D0 inc
spi_lo
; dec brne ret
temp spi_loop
;we FORCED D0=0, so use INC
to set D0.
;************************
End of SPI routines
**************************** ;**** Application example **** Reset: ser out rjmp
rcall init_spi temp ;load w/ FF DDRD,temp Main
Main: mov
ldi R22,0xA3 ;misc data spi_lo,R22 ;set up information to be
sent mov
spi_hi,R22
;COMMENT THIS OUT IF 8-BIT
rcall rcall
ena_spi rw_spi
;activate /SS ;send/receive 16 bits (or 8
rcall rcall rjmp
disa_spi use_spi_rcv Main
;deactivate /SS ;go use whatever we received
MODE
bits)
Use_spi_rcv:
;just copy rcv'd
data to Port D pins out ret
PortD,R22
;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other http://avr-asm.tripod.com/avrspi.html (1 of 2)1/20/2009 9:00:10 PM
16 BIT MATH (AVR 202)
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avrspi.html (2 of 2)1/20/2009 9:00:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR I2C MASTER PROTOCOL (AVR 300) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
multimaster ability
DIV 24 24
implementation uses, by far,
DIV 3216 FLOAT 128 SQRT16
DEC ASCII INT ASCII
FLASH CARD
;*
"single" master implementation is limited to one
;*
I2C bus. Most applications do not need the
;*
the I2C bus provides. A single master
;* ;* ;* ;*
less resources and is less XTAL frequency dependent.
;* ;* ;* ;* ;* ;*
* Supports normal and fast mode. * Supports both 7-bit and 10-bit addressing. * Supports the entire AVR microcontroller family.
Some features : * All interrupts are free, and can be used for
Main I2C functions : 'i2c_start' -
Issues a start condition
'i2c_rep_start' -
and transfer direction. Issues a repeated start
condition and sends ;*
address and transfer
direction. ;*
'i2c_do_transfer' -
Sends or receives data
depending on ;*
SER EPROM DFLASH AT45
DESCRIPTION Basic routines for communicating with I2C slave
;* ;*
COPY 102
EPROM 100
: [email protected]
and sends address
AVG8 222
LPM 108
Support email
other activities.
MATH 202
FFT7
: I2C (Single) Master Implementation : 1.0 (BETA) : 97.08.27 : AT90Sxxxx (any AVR device)
bus master on the
DIV16 XX
HX2ASC
Title Version Last updated Target
devices. This
MATH YX
MATH 202
A V R 3 0 0
************************
ASM MATH
MATH 202
N O T E
direction given in address/
dir byte. ;*
'i2c_stop' -
Terminates the data
transfer by issue a ;* stop condition. ;* ;* USAGE ;* Transfer formats is described in the AVR300
VFX SMIL VFX MEM SORT 220 documentation. CRC 236
;* (An example is shown in the 'main' code). ;* ;* NOTES ;* The I2C routines can be called either from non-
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300
interrupt or ;* interrupt routines, not both. ;* ;* STATISTICS ;* Code Size : 81 words (maximum) ;* Register Usage : 4 High, 0 Low ;* Interrupt Usage : None ;* Other Usage : Uses two I/O pins on port D ;* XTAL Range : N/A ;* ; ***************************************************************************
I2C 302
;**** Includes ****
I2C TWI26 I2C/TWI 128
.include "1200def.inc"
; change if
an other device is used
I2C/TWI AT8
;**** Global I2C Constants ****
DALLAS-1W DALLAS CRC ETHNET 8019 TEA
SCLP
= 1
; SCL Pin
.equ
SDAP
= 0
; SDA Pin
.equ
b_dir
= 0
; transfer
.equ .equ
i2crd i2cwr
= 1 = 0
number (port D) number (port D)
ADC 128 ADC 10B
.equ
direction bit in i2cadr
ADC 400 ADC 401 THERM 232
;**** Global Register Variables ****
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
i2cdelay= r16
; Delay
.def
i2cdata = r17
; I2C data
.def
i2cadr
; I2C
.def
i2cstat = r19
loop variable transfer register
;**** Interrupt Vectors ****
PS2 EMU BOOT MG8 BOOT DR8
CLOCK 8564
; I2C bus
status register
KBD PC/128
ALM CLK
= r18
address and direction register
MUX 242 KBD PS2
.def
; ;
rjmp ( rjmp ( rjmp
RESET EXT_INT0 ) TIM0_OVF )
; Reset handle ; ( IRQ0 handle ) ; ( Timer 0
;
( rjmp
ANA_COMP )
; ( Analog
overflow handle ) comparator handle )
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* FUNCTION ;* i2c_hp_delay ;* i2c_qp_delay ;* ;* DESCRIPTION ;* hp - half i2c clock period delay (normal: 5.0us / fast: 1.3us) ;* qp - quarter i2c clock period delay (normal: 2.5us / fast: 0.6us) ;* ;* SEE DOCUMENTATION !!! ;* ;* USAGE ;* no parameters ;* ;* RETURN ;* none ;* ; *************************************************************************** i2c_hp_delay: ldi i2cdelay,2 i2c_hp_delay_loop: dec i2cdelay brne i2c_hp_delay_loop ret i2c_qp_delay: ldi i2cdelay,1 i2c_qp_delay_loop: dec i2cdelay brne i2c_qp_delay_loop ret
; *************************************************************************** ;* ;* FUNCTION ;* i2c_rep_start ;* ;* DESCRIPTION ;* Assert repeated start condition and sends slave address. ;* ;* USAGE ;* i2cadr - Contains the slave address and transfer direction. ;* ;* RETURN ;* Carry flag - Cleared if a slave responds to the address. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_start. ;* ; *************************************************************************** i2c_rep_start: sbi DDRD,SCLP cbi DDRD,SDAP rcall i2c_hp_delay cbi DDRD,SCLP rcall i2c_qp_delay
; ; ; ; ;
force SCL low release SDA half period delay release SCL quarter period
delay
; *************************************************************************** ;* ;* FUNCTION ;* i2c_start ;* ;* DESCRIPTION ;* Generates start condition and sends slave address. ;* ;* USAGE ;* i2cadr - Contains the slave address and transfer direction. ;* ;* RETURN ;* Carry flag - Cleared if a slave responds to the address. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_write. ;* ; *************************************************************************** i2c_start: mov
i2cdata,i2cadr
; copy address to
DDRD,SDAP i2c_qp_delay
; force SDA low ; quarter period
transmitt register sbi rcall delay
; *************************************************************************** ;* ;* FUNCTION ;* i2c_write ;* ;* DESCRIPTION ;* Writes data (one byte) to the I2C bus. Also used for sending ;* the address. ;* ;* USAGE ;* i2cdata - Contains data to be transmitted. ;* ;* RETURN ;* Carry flag - Set if the slave respond transfer. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_get_ack. ;* ; *************************************************************************** i2c_write: sec rol
; set carry flag ; shift in carry
i2cdata
and out bit one rjmp i2c_write_first i2c_write_bit: lsl i2cdata
; if transmit
i2c_write_first: breq i2c_get_ack
;
register empty goto get
acknowledge sbi
DDRD,SCLP
; force SCL low
brcc nop
i2c_write_low
; if bit high ; (equalize
number of cycles) cbi DDRD,SDAP rjmp i2c_write_high i2c_write_low: sbi DDRD,SDAP
;
release SDA
;
; else force SDA
;
(equalize
low rjmp
i2c_write_high
number of cycles) i2c_write_high: rcall i2c_hp_delay cbi DDRD,SCLP rcall i2c_hp_delay rjmp
; half period delay ; release SCL ; half period delay
i2c_write_bit
; *************************************************************************** ;* ;* FUNCTION ;* i2c_get_ack ;* ;* DESCRIPTION ;* Get slave acknowledge response. ;* ;* USAGE ;* (used only by i2c_write in this version) ;* ;* RETURN ;* Carry flag - Cleared if a slave responds to a request. ;* ; *************************************************************************** i2c_get_ack: sbi DDRD,SCLP cbi DDRD,SDAP rcall i2c_hp_delay cbi DDRD,SCLP i2c_get_ack_wait: sbis PIND,SCLP
; ; ; ;
force SCL low release SDA half period delay release SCL
; wait SCL high ;(In case wait
states are inserted) rjmp clc sbic sec
i2c_get_ack_wait
PIND,SDAP
; clear carry flag ; if SDA is high ; set carry
i2c_hp_delay
; half period delay
flag rcall ret
; *************************************************************************** ;* ;* FUNCTION ;* i2c_do_transfer ;* ;* DESCRIPTION ;* Executes a transfer on bus. This is only a combination of i2c_read ;* and i2c_write for convenience. ;* ;* USAGE ;* i2cadr - Must have the same direction as when i2c_start was called. ;* see i2c_read and i2c_write for more information. ;* ;* RETURN ;* (depends on type of transfer, read or write) ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_read. ;* ; *************************************************************************** i2c_do_transfer: sbrs i2cadr,b_dir rjmp i2c_write
; if dir = write ; goto write
data
; *************************************************************************** ;* ;* FUNCTION ;* i2c_read ;* ;* DESCRIPTION ;* Reads data (one byte) from the I2C bus. ;* ;* USAGE ;* Carry flag If set no acknowledge is given to the slave ;* indicating last read operation before a STOP. ;* If cleared acknowledge is given to the slave ;* indicating more data. ;* ;* RETURN ;* i2cdata - Contains received data. ;* ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by i2c_put_ack. ;* ; *************************************************************************** i2c_read: rol
i2cstat
; store acknowledge ; (used by
i2c_put_ack) ldi i2cdata,0x01 i2c_read_bit: sbi DDRD,SCLP
; data = 0x01 ; do ; force SCL
low rcall
i2c_hp_delay
;
half period
cbi rcall
DDRD,SCLP i2c_hp_delay
; ;
release SCL half period
;
clear carry
;
if SDA is
delay
delay clc flag sbic
PIND,SDAP
high sec
;
set
carry flag rol
i2cdata
;
store data
brcc
i2c_read_bit
; while receive
bit register not full
; *************************************************************************** ;* ;* FUNCTION ;* i2c_put_ack ;* ;* DESCRIPTION ;* Put acknowledge. ;* ;* USAGE ;* (used only by i2c_read in this version) ;* ;* RETURN ;* none ;* ; *************************************************************************** i2c_put_ack: sbi DDRD,SCLP ror brcc
i2cstat i2c_put_ack_low
; force SCL low ; get status bit ; if bit low goto
assert low cbi DDRD,SDAP rjmp i2c_put_ack_high i2c_put_ack_low: sbi DDRD,SDAP
;
release SDA
; else ;
force SDA
low i2c_put_ack_high: rcall i2c_hp_delay cbi DDRD,SCLP i2c_put_ack_wait: sbis PIND,SCLP rjmp i2c_put_ack_wait rcall i2c_hp_delay ret
; half period delay ; release SCL ; wait SCL high ; half period delay
; *************************************************************************** ;* ;* FUNCTION ;* i2c_stop ;* ;* DESCRIPTION ;* Assert stop condition. ;* ;* USAGE ;* No parameters. ;* ;* RETURN ;* None. ;* ; *************************************************************************** i2c_stop: sbi sbi rcall cbi rcall
DDRD,SCLP DDRD,SDAP i2c_hp_delay DDRD,SCLP i2c_qp_delay
; ; ; ; ;
force SCL low force SDA low half period delay release SCL quarter period
DDRD,SDAP i2c_hp_delay
; release SDA ; half period delay
delay cbi rcall ret
; *************************************************************************** ;* ;* FUNCTION ;* i2c_init ;* ;* DESCRIPTION ;* Initialization of the I2C bus interface. ;* ;* USAGE ;* Call this function once to initialize the I2C bus. No parameters ;* are required. ;* ;* RETURN ;* None ;* ;* NOTE ;* PORTD and DDRD pins not used by the I2C bus interface will be ;* set to Hi-Z (!). ;* ;* COMMENT ;* This function can be combined with other PORTD initializations. ;* ; *************************************************************************** i2c_init: clr
i2cstat
; clear I2C status
register (used ; as a temporary register) out
PORTD,i2cstat
out ret
DDRD,i2cstat
; set I2C pins to
open colector
; *************************************************************************** ;* ;* PROGRAM ;* main - Test of I2C master implementation ;* ;* DESCRIPTION ;* Initializes I2C interface and shows an example of using it. ;* ; *************************************************************************** RESET: main:
rcall
i2c_init
;
initialize I2C interface ;**** Write data => Adr(00) = 0x55 **** ldi
i2cadr,$A0+i2cwr
; Set device
rcall
i2c_start
; Send start
ldi
i2cdata,$00
; Write word
rcall
i2c_do_transfer
; Execute transfer
ldi
i2cdata,$55
; Set write data to
rcall
i2c_do_transfer
; Execute transfer
rcall
i2c_stop
; Send stop
address and write condition and address
address (0x00)
01010101b
condition ;**** Read data => i2cdata = Adr(00) **** ldi
i2cadr,$A0+i2cwr
; Set device
rcall
i2c_start
; Send start
ldi rcall
i2cdata,$00 i2c_do_transfer
; Write word address ; Execute transfer
ldi
i2cadr,$A0+i2crd
; Set device
rcall
i2c_rep_start
; Send repeated
address and write condition and address
address and read start condition and address sec acknowledge (read is followed by a stop condition) rcall i2c_do_transfer (read)
; Set no ; Execute transfer
rcall
i2c_stop
; Send stop
rjmp
main
; Loop forewer
condition - releases bus
;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 http://avr-asm.tripod.com/avr300.html (1 of 2)1/20/2009 9:00:50 PM
16 BIT MATH (AVR 202)
have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr300.html (2 of 2)1/20/2009 9:00:50 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR I2C SLAVE PROTOCOL (AVR 302) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
FLOAT 128
INT ASCII
: [email protected]
Code Size : 160 words Low Register Usage : 0 High Register Usage : 5 Interrupt Usage : External Interrupt0, Timer/Counter0 overflow interrupt DESCRIPTION This application note shows how to implement an AVR
;*
as an I2C slave peripheral. For use with other
;*
I/O pins might have to be used, and the stack
;* ;*
initialized. Received data is stored in r0 and r0 is transmitted
;*
read transfer. This simple protocol is implemented
;* ;* ;* ;* ;*
purposes only.
;* ;* ;* ;* ;* ;*
* * * *
during a master for demonstration
AVG8 222 FFT7
Some features : * Interrupt based (using INT0 and TIM0). * The device can be given any 7-bit address.
(Expandable to 10bit).
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD
Support email
pointer might have to be
HX2ASC
COPY 102
: I2C Slave Implementation : 1.2 : 97.07.17 : AT90Sxxxx (All AVR Device) Fast Mode: AT90S1200 only
AT90S AVR devices, other
MATH 202 DEC ASCII
Title Version Last updated Target
AT90S1200 device
SQRT16 MATH 202
A V R 3 0 2
************************
ASM MATH
DIV 3216
N O T E
Supports normal and fast mode. Easy insertion of "wait states". Size and speed optimized. Supports wake-up from idle mode.
Refers to the application note AVR302 documentation
for more ;* detailed description. ;* ;* USAGE ;* Insert user code in the two locations marked
VFX SMIL VFX MEM SORT 220 "insert user code here". CRC 236
;* ;* NOTES ;* Minimum one instruction will be executed between
XMODEM REC UART 304 UART 305
each interrupt.
AVR SPI
;* ;* STATISTICS ;* Code Size : 160 ;* Register Usage : 5 High, 0 Low ;* Interrupt Usage : EXT_INT0 and TIM0_OVF ;* Port Usage : PD4(T0) and PD2(INT0) ;* XTAL : - I2C Fast Mode : min 16.0MHz ;* - I2C Standard Mode : min 3.0MHz ;* ; ***************************************************************************
I2C 300
;**** Includes ****
UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200
I2C 302 .include "1200def.inc"
I2C TWI26 I2C/TWI 128
;**** Global I2C Constants ****
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
.equ
devadr
= 0x50
; Slave device
.equ
devadrm = 0x7F
; Slave multi
.equ
pinmask = 0x14
; <=> (1<
address address mask
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313
Programming the AVR Microcontrollers in Machine Language
KBD 240 MUX 242
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BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr302.html (1 of 2)1/20/2009 9:01:29 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr302.html (2 of 2)1/20/2009 9:01:29 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
I2C/TWI PROTOCOL FOR ATINY26 HOME RETRO_DAN ASM FORUM
.include "tn26def.inc"
ASM MATH TUTORIAL #1 TUTORIAL #2
.org $0000 rjmp reset ;.org INT0addr ;rjmp EXT_INT0 .org OC1Aaddr rjmp TIMER1_CMPA ;.org OVF0addr ;rjmp TIMER0_OVF0 .org USI_STARTaddr rjmp USI_STRT .org USI_OVFaddr rjmp USI_OVF
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX
;(1) ;(2) ;(4) ;(7) ;(8) ;(9)
DIV 24 24 ;Cal=0x99
DIV 3216 FLOAT 128
.equ OwnTWIAddress
=11;16
SQRT16 .equ .equ .equ .equ .equ .equ .equ .equ .equ
MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222
UserRAM USI_State AddressAndWR USI_ByteReceivedPointerLow USI_ByteReceivedPointerHigh USI_Byte0 USI_Byte1 USI_Byte2 USI_Byte3
=$0060 =UserRAM =UserRAM+1 =UserRAM+2 =UserRAM+3 =UserRAM+4 =UserRAM+5 =UserRAM+6 =UserRAM+7
FFT7 COPY 102 reset:
LPM 108 EPROM 100
;*** Init at startup ***
SER EPROM ;Clear RAM at startup clr r16 sts USI_State,r16 sts USI_Byte0,r16 sts USI_Byte1,r16 sts USI_Byte2,r16 sts USI_Byte3,r16
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236
ldi r16,RAMEND out SP,
XMODEM REC UART 304
r16
UART 305
;*** MCUCR *** ;MCU Control Register MCUCR ;Bit1,Bit0=ISC01,ISC00: Interrupt Sense Control (11=rising edge) ldi r16,(1< 40 kHz) ;xxx ldi
UART 128 UART BUFF USB 232 AVR ISP
;Setting stackpointer to RAM end
r16,255 xxx
;
ISP 2313
out OCR1C,r16
ISP 1200
;*** USI *** ;USI Control Register: USICR ;Bit7=USISIE: Start Condition Interrupt Enable ;Bit6=USIOIE: Counter Overflow Interrupt Enable ;Bit5,Bit4=USIWM1,USIWM0: Wire Mode (11=TWI) ;Bit3,Bit2=USICS1,USICS0: Clock Source Select (110=Negative edge External,
AVR SPI I2C 300 I2C 302 I2C TWI26
TWI)
I2C/TWI 128
;Bit1=USICLK: Clock Strobe ;Bit0=USITC: Toggle Clock Port Pin ldi r16,(1<
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
Programming the AVR Microcontrollers in Machine Language
LCD HD44
AVR << Prev | Ring Hub | Join | Rate| Next >>
LCD 2313 LCD44 2313 KBD 240 © WebRing Inc.
MUX 242
Search
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: AlfEgil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/ O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirtytwo single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/ O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bidirectional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/twi26.html (1 of 2)1/20/2009 9:02:06 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/twi26.html (2 of 2)1/20/2009 9:02:06 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
I2C/TWI PROTOCOL FOR 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
; *************************************************************************** ; ; File Name :'twi.asm" ; Title : I2C (TWI) Hardware ; Date :2003.04.29. Lastmod.:[2003.04.29.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.04.29 VFX Creation ; ; *************************************************************************** ; ; ; ;Hardware ; *************************************************************************** ;*
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF
; ************************************************************************** ;* Const Def ; ;Bit Rate Generator in Master Mode ;TWBR = Value of the TWI Bit Rate Register ;TWPS = Value of the prescaler bits in the TWI Status Register ; ;Note: TWBR should be 10 or higher if the TWI operates in Master mode. ; If TWBR is lower than 10, the master may produce an incorrect output on SDA ; and SCL for the reminder of the byte. ; ; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255 ; ; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
USB 232 AVR ISP
.EQU .EQU
SCL_Freq = 100000 TWI_SlaveAddress = 0xFE
;Hz ;Slave Address is FECO :)
.equ .equ .equ .equ
TWI_WriteByte = 0x00 TWI_WriteRAW = 0x01 TWI_ReadByte = 0x02 TWI_ReadRAW = 0x03
;Send ;Send ;Read ;Read
ISP 2313 ISP 1200 AVR SPI I2C 300
Byte Blokk of data Byte Block of data
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; *************************************************************************** .DSEG
DALLAS-1W
TWI_CTL: TWI_Count: TWI_Slave: TWI_ADR: TWI_Flag: TWI_SADR:
DALLAS CRC ETHNET 8019 TEA ADC 128
.byte .byte .byte .byte .byte .byte
2 1 1 1 1 2
;Address of TWI IO Control Blokk ;Byte counter for TWI ;Slave Address ;Slave internal Address ;0. = 1 TWI in use ;TWI State Machin Address
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
; ************************************************************************* ;* Code ;* .CSEG
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; ************************************************************************* ;* Init TWI Device, Clear TWI_CTL ; TWI_Init: ldi R16,Low(TWIRET) sts TWI_SADR+0,R16 ldi R16,High(TWIRET) sts TWI_SADR+1,R16
PS2 EMU BOOT MG8
DELAYS CALL ID
;TWI Bit Rate
sts ldi
TWBR,R16 R16,0b00000101
;TWI Control
sts
TWCR,R16
;7 – TWINT: TWI
Register – TWCR
CLOCK 8564 90 DAYS
R16,SYSCLK/(2*SCL_Freq)-8
Register - TWBR
BOOT DR8 ALM CLK
ldi
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition
DTMF 314
;4 – TWSTO: TWI
PWM 6CH
STOP Condition
PWM 10K
Write Collision Flag
;3 - TWWC: TWI ;2 – TWEN: TWI
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
Enable ;1 – Res: Reserved Bit ;0 – TWIE: TWI Interrupt Enable
AVR BOOK
ldi
R16,0b11111000
;TWI Status
sts
TWSR,R16
;7..3 – TWS: TWI
Register – TWSR Status ;2 – Res: Reserved Bit ;1..0 – TWPS: TWI Prescaler Bits ldi
R16,TWI_SlaveAddress
sts clr sts ret
TWAR,R16 R16 TWI_Flag,R16
;TWI (Slave)
Address Register
; ************************************************************************* ;* Start TWI Comunication in Master Mode ; In: X - Address of IO_CTR Block ; ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartRead: rcall WaitToTWI ldi
R16,Low(RBlock0) sts TWI_SADR+0,R16 ldi R16,High(RBlock0) sts TWI_SADR+1,R16
sts sts sts sts sts
TWI_CTL+0,XL TWI_CTL+1,XH TWI_Count,R17 TWI_Slave,R18 TWI_ADR,R19
lds ori andi sts
R16,TWI_Flag R16,1 R16,0b11111101 TWI_Flag,R16
ldi sts
R16,0b11100101 TWCR,R16
TWI_Common:
;TWI in use! ;TWI no error
;7 – TWINT: TWI
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition ;4 – TWSTO: TWI STOP Condition ;3 – TWWC: TWI Write Collision ;2 – TWEN: TWI Enable ;1 – Res: Reserved ;0 – TWIE: TWI Interrupt Enable TWIRET: ret ; ************************************************************************* ;* Start TWI Comunication in Master Mode - Write! ; In: X - Address of IO_CTR Block ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartWrite: rcall WaitToTWI ldi
rjmp
R16,Low(WBlock0) sts TWI_SADR+0,R16 ldi R16,High(WBlock0) sts TWI_SADR+1,R16 TWI_Common
; ************************************************************************* ;* TWI interrupt ;* TWI: Interrupt Handler push ZL push ZH in ZL,SREG reg. push ZL push R16 push R0 push R17 in ZL,RAMPZ push ZL
; Two-wire Serial Interface
;preserve main OS status
lds andi
R16,TWSR R16,0b11111000
;Load TWI Status ;csak a status marad
lds
ZL,TWI_SADR+0 lds ZH,TWI_SADR+1
icall pop out pop POP POP POP OUT POP POP RETI
ZL RAMPZ,ZL R17 R0 R16 ZL SREG,ZL ZH ZL
; ************************************************************************************************************ ;*** R E A D B L O C K ;*** ; ;*********************** ; Read Block of data - State 0 ; Start bit sended RBlock0: cpi R16,0x08 ;A START condition has been transmitted breq Rbl0 cpi R16,0x10 ;A Repeated START condition has been transmitted breq Rbl0 rjmp TWI_ReadError Rbl0: lds R16,TWI_Slave andi R16,0b11111110 ;Write SLA sts TWDR,R16 ;Send Slave Address ldi
R16,Low(RBlock1) sts TWI_SADR+0,R16 ldi R16,High(RBlock1) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
RBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq RBl1 TWI_ReadError
lds sts
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(RBlock2) sts TWI_SADR+0,R16 ldi R16,High(RBlock2) sts TWI_SADR+1,R16 R16,(1< Repeated Satrt send
cpi
R16,0x28
rjmp
breq Rbl21 TWI_ReadError
RBl1: ;Send Slave
Internal Address
RBlock2: ;
SlaveAddress sended + ACK received
Rbl21: ldi
R16,Low(RBlock3) sts TWI_SADR+0,R16 ldi R16,High(RBlock3) sts TWI_SADR+1,R16
ldi
R16,(1< Send SLA+R
cpi
R16,0x10
rjmp
breq RBl31 TWI_ReadError
lds ori sts
R16,TWI_Slave R16,1 TWDR,R16
ldi
R16,Low(RBlock4) sts TWI_SADR+0,R16 ldi R16,High(RBlock4) sts TWI_SADR+1,R16
ldi
R16,(1< Read data byte
cpi
R16,0x40
RBlock3: ;Repeated
Start sended + ACK received
RBl31: ;Write SLA+R ;Send Slave
Address
RBlock4: ;SLA+R send
+ ACK received brne
TWI_ReadError
lds cpi breq
R16,TWI_Count R16,1 TWILAstByte
ldi
R16,Low(RBlock5) sts TWI_SADR+0,R16 ldi R16,High(RBlock5) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
WBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq WBl1 TWI_WriteError
lds sts
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(WBlock2) sts TWI_SADR+0,R16 ldi R16,High(WBlock2) sts TWI_SADR+1,R16 R16,(1< Write data
cpi
R16,0x28
breq rjmp
WB12 TWI_WriteError
WBl1: ;Send Slave
Internal Address
WBlock2: ;Data byte
has been transmitted + ACK received
WB12:
;
Send data byte continous lds lds ld sts
ZL,TWI_CTL+0 ZH,TWI_CTL+1 R0,Z+ TWDR,R0
sts sts
TWI_CTL+0,ZL TWI_CTL+1,ZH
lds cpi breq dec sts
R16,TWI_Count R16,1 TWI_WriteLastByte R16 TWI_Count,R16
ldi
R16,(1<
;next data
byte
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with http://avr-asm.tripod.com/twi128.html (1 of 2)1/20/2009 9:02:45 PM
16 BIT MATH (AVR 202)
multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/twi128.html (2 of 2)1/20/2009 9:02:45 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
I2C/TWI PROTOCOL FOR ATEMGA8 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100
; *************************************************************************** ; ; File Name :'twi.asm" ; Title : I2C (TWI) Hardware ; Date :2003.04.29. Lastmod.:[2003.04.29.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga8 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.04.29 VFX Creation ; ; *************************************************************************** ; ; ; ;Hardware ; *************************************************************************** ;*
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF
; ************************************************************************** ;* Const Def ; ;Bit Rate Generator in Master Mode ;TWBR = Value of the TWI Bit Rate Register ;TWPS = Value of the prescaler bits in the TWI Status Register ; ;Note: TWBR should be 10 or higher if the TWI operates in Master mode. ; If TWBR is lower than 10, the master may produce an incorrect output on SDA ; and SCL for the reminder of the byte. ; ; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255 ; ; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
USB 232 AVR ISP
.EQU .EQU
SCL_Freq = 100000 TWI_SlaveAddress = 0xFE
;Hz ;Slave Address is FECO :)
.equ .equ .equ .equ
TWI_WriteByte = 0x00 TWI_WriteRAW = 0x01 TWI_ReadByte = 0x02 TWI_ReadRAW = 0x03
;Send ;Send ;Read ;Read
ISP 2313 ISP 1200 AVR SPI I2C 300
Byte Blokk of data Byte Block of data
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; *************************************************************************** .DSEG
DALLAS-1W
TWI_CTL: TWI_Count: TWI_Slave: TWI_ADR: TWI_Flag: TWI_SADR:
DALLAS CRC ETHNET 8019 TEA ADC 128
.byte .byte .byte .byte .byte .byte
2 1 1 1 1 2
;Address of TWI IO Control Blokk ;Byte counter for TWI ;Slave Address ;Slave internal Address ;0. = 1 TWI in use ;TWI State Machin Address
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410
; ************************************************************************* ;* Code ;* .CSEG
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; ************************************************************************* ;* Init TWI Device, Clear TWI_CTL ; TWI_Init: ldi R16,Low(TWIRET) sts TWI_SADR+0,R16 ldi R16,High(TWIRET) sts TWI_SADR+1,R16
PS2 EMU BOOT MG8
DELAYS CALL ID
;TWI Bit Rate
out ldi
TWBR,R16 R16,0b00000101
;TWI Control
out
TWCR,R16
;7 – TWINT: TWI
Register – TWCR
CLOCK 8564 90 DAYS
R16,SYSCLK/(2*SCL_Freq)-8
Register - TWBR
BOOT DR8 ALM CLK
ldi
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition
DTMF 314
;4 – TWSTO: TWI
PWM 6CH
STOP Condition
PWM 10K
Write Collision Flag
;3 - TWWC: TWI ;2 – TWEN: TWI
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
Enable ;1 – Res: Reserved Bit ;0 – TWIE: TWI Interrupt Enable
AVR BOOK
ldi
R16,0b11111000
;TWI Status
out
TWSR,R16
;7..3 – TWS: TWI
Register – TWSR Status ;2 – Res: Reserved Bit ;1..0 – TWPS: TWI Prescaler Bits ldi
R16,TWI_SlaveAddress
out clr sts ret
TWAR,R16 R16 TWI_Flag,R16
;TWI (Slave)
Address Register
; ************************************************************************* ;* Start TWI Comunication in Master Mode ; In: X - Address of IO_CTR Block ; ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartRead: rcall WaitToTWI ldi R16,Low(RBlock0) sts TWI_SADR+0,R16 ldi R16,High(RBlock0) sts TWI_SADR+1,R16 TWI_Common: sts TWI_CTL+0,XL sts TWI_CTL+1,XH sts TWI_Count,R17 sts TWI_Slave,R18 sts TWI_ADR,R19 lds ori andi sts
R16,TWI_Flag R16,1 R16,0b11111101 TWI_Flag,R16
ldi out
R16,0b11100101 TWCR,R16
;TWI in use! ;TWI no error
;7 – TWINT: TWI
Interrupt Flag ;6 – TWEA: TWI Enable Acknowledge ;5 – TWSTA: TWI START Condition ;4 – TWSTO: TWI STOP Condition ;3 – TWWC: TWI Write Collision ;2 – TWEN: TWI Enable ;1 – Res: Reserved ;0 – TWIE: TWI Interrupt Enable TWIRET: ret ; ************************************************************************* ;* Start TWI Comunication in Master Mode - Write! ; In: X - Address of IO_CTR Block ; R17 - count of byte ; R18 - Slave Address ; R19 - Internal Address of Slave ; Out: c = 1 error ; TWI_StartWrite: rcall WaitToTWI ldi
rjmp
R16,Low(WBlock0) sts TWI_SADR+0,R16 ldi R16,High(WBlock0) sts TWI_SADR+1,R16 TWI_Common
; ************************************************************************* ;* TWI interrupt ;* TWI: Interrupt Handler push ZL push ZH in ZL,SREG reg. push ZL push R16 push R0 push R17
;
; Two-wire Serial Interface
;preserve main OS status
cbi
GreenLED_PORT,GreenLED
;LED
in andi
R16,TWSR R16,0b11111000
;Load TWI Status ;csak a status marad
lds
ZL,TWI_SADR+0 lds ZH,TWI_SADR+1
icall pop POP POP POP OUT POP POP RETI
R17 R0 R16 ZL SREG,ZL ZH ZL
; ************************************************************************************************************ ;*** R E A D B L O C K ;*** ; ;*********************** ; Read Block of data - State 0 ; Start bit sended RBlock0: cpi R16,0x08 ;A START condition has been transmitted breq Rbl0 cpi R16,0x10 ;A Repeated START condition has been transmitted breq Rbl0 rjmp TWI_ReadError Rbl0: lds R16,TWI_Slave andi R16,0b11111110 ;Write SLA out TWDR,R16 ;Send Slave Address ldi
R16,Low(RBlock1) sts TWI_SADR+0,R16 ldi R16,High(RBlock1) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
RBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq RBl1 TWI_ReadError
lds out
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(RBlock2) sts TWI_SADR+0,R16 ldi R16,High(RBlock2) sts TWI_SADR+1,R16 R16,(1< Repeated Satrt send
cpi
R16,0x28
rjmp
breq Rbl21 TWI_ReadError
RBl1: ;Send Slave
Internal Address
RBlock2: ;
SlaveAddress sended + ACK received
Rbl21: ldi
R16,Low(RBlock3) sts TWI_SADR+0,R16 ldi R16,High(RBlock3) sts TWI_SADR+1,R16
ldi
R16,(1< Send SLA+R
cpi
R16,0x10
rjmp
breq RBl31 TWI_ReadError
lds ori out
R16,TWI_Slave R16,1 TWDR,R16
ldi
R16,Low(RBlock4) sts TWI_SADR+0,R16 ldi R16,High(RBlock4) sts TWI_SADR+1,R16
ldi
R16,(1< Read data byte
cpi
R16,0x40
RBlock3: ;Repeated
Start sended + ACK received
RBl31: ;Write SLA+R ;Send Slave
Address
RBlock4: ;SLA+R send
+ ACK received brne
TWI_ReadError
lds cpi breq
R16,TWI_Count R16,1 TWILAstByte
ldi
R16,Low(RBlock5) sts TWI_SADR+0,R16 ldi R16,High(RBlock5) sts TWI_SADR+1,R16
ldi
R16,(1< Send slave internal address
WBlock1: cpi
R16,0x18
;SLA
+W has been transmitted rjmp
breq WBl1 TWI_WriteError
lds out
R16,TWI_ADR TWDR,R16
ldi
ldi
R16,Low(WBlock2) sts TWI_SADR+0,R16 ldi R16,High(WBlock2) sts TWI_SADR+1,R16 R16,(1< Write data
cpi
R16,0x28
breq rjmp
WB12 TWI_WriteError
WBl1: ;Send Slave
Internal Address
WBlock2: ;Data byte
has been transmitted + ACK received
WB12:
;
Send data byte continous lds lds ld out
ZL,TWI_CTL+0 ZH,TWI_CTL+1 R0,Z+ TWDR,R0
sts sts
TWI_CTL+0,ZL TWI_CTL+1,ZH
lds cpi breq dec sts
R16,TWI_Count R16,1 TWI_WriteLastByte R16 TWI_Count,R16
ldi
R16,(1<
;next data
byte
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer http://avr-asm.tripod.com/twi8.html (1 of 2)1/20/2009 9:03:20 PM
16 BIT MATH (AVR 202)
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/twi8.html (2 of 2)1/20/2009 9:03:20 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DALLAS 1 WIRE PROTOCOL HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII
;*********************************************************************** ;* ;* Number :Dallas 1-wire ;* File Name :"ds1wire.asm" ;* Title :Dallas 1-wire rutinok ;* Date :2000.10.15. ;* Version :0.0 ;* Support telephone :+36-70-333-4034, Old: +36-30-9541-658 ;* Support fax : ;* Support E-mail :[email protected] ;* Target MCU :AVR ;* ; ************************************************************************** ;* DESCRIPTION ;* - DS1990A security unit ;* ;* SYSCLK=3686400 Hz (T=271.267 ns) ;* ;* DS119A - Family Code (0x01) ;* 48-bit Serial Number ;* 8-bit CRC ;* ;* ; ************************************************************************** ;* Hardware Def.
INT ASCII HX2ASC AVG8 222
.EQU .equ .equ .EQU
DS1wire_PORT =PORTB DS1wire_DIR = DDRB DS1wire_PIN = PINB DS1wire = 0
.equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
DSReadROM = 0x33 DSMatchROM = 0x55 DSSkipROM = 0xCC DSSearchROM = 0xF0 DSAlarmSearch = 0xEC DSWriteScratchpad= 0x4E DSReadScratchpad = 0xBE DSCopyScratchpad = 0x48 DSConvertTemp = 0x44 DSRecall = 0xB8
.equ .equ
DSDev1990A DSDev1920
;Dallas 1-Wire bus
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC
= 0x01 = 0x10
UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313
; ****************************************************************************** ;**** VARIABLES .DSEG CRC: .BYTE 1 ;DS1990A CRC GENERATOR HASZNALJA DSRD: .BYTE 9 ;Ide olvassa be a DS Chipet DSRDMem:.byte 9 ;Scrach Pad tartalma BadCRC: .BYTE 1 ;Bad CRC szamlalo
ISP 1200 AVR SPI I2C 300
; ***************************************************************************** .CSEG
I2C 302 I2C TWI26 I2C/TWI 128 ;************************************************************************ ;*********************** 1-Wire Bus ************************************* ;************************************************************************
I2C/TWI AT8 DALLAS-1W DALLAS CRC
DS1Wire_Init: clr sts sts
ETHNET 8019 TEA ADC 128 ADC 10B
cbi cbi ret
R16, CRC,R16 BadCRC,R16
ADC 400
DS1wire_PORT,DS1wire DS1wire_DIR,DS1wire
ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP
; ******************************************************************************* ;****** T O U C H R E S E T ; ******************************************************************************* ; ;Inicialization procedure "Reset and PreSence Pulses" ; ; Ez a rutin egy Reset jelet general a mikrovrzerlo ketiranyu DS_BIT nevu laban, ;a Touch Memory fele es figyeli a visszajovo PreSence jelet. ;Ha a PreSence jel megerkezett, akkor C=1 kulonben C=0 (nincs eszkoz a buszon) ; ; |-Master Rx "Presence Pulse"-| ; |---Master Reset Tx Pulse---| |----t(RSTH)---------------| ; __ t(RSTL) _____ _____ \\ ___ ; \ / \ / \ ; \_________________________/ \______/ \__ ... ; |-----|-------| ; t(PDH) t(PDL) ; t(R) <-- |-| ; ; 480us<=t(RSTL)< . t(RSTL)+t(R)<960us ; 480us<=t(RSTH)< ; 15us<=t(PDH)<=60us ; 60us<=t(PDL)<=240us ; ; C-flag = 1 DS1990A a buszon van ; = 0 DS1990A nincs a buszon ; ; R16, X
AVR BUTTERFLY
TouchReset:
AVR BOOK
SBI
DS1wire_DIR,DS1wire
ldi ldi
YL,low((480*SYSCLK)/(1000000*4)) YH,high((480*SYSCLK)/(1000000*4));loop cycle = 4 sbiw YL,1 ;[2] TR0 ;[1/2] 480us wait with data
;
1-wire = Master LOW ,
Start the reset pulse
TR0: brne low
SBI nop nop CBI CBI nop nop
DS1wire_PORT,DS1wire
;[2] ;[1]
1-wire =Active Hi
DS1wire_DIR,DS1wire DS1wire_PORT,DS1wire
;[2] ;[2] ;[1]
1-wire HI (felengedve) 1-wire = Tri-state
SBIS RJMP
DS1wire_PIN,DS1wire Short
;[1/2] ;[2]
ldi ldi RJMP sbiw BRNE
YL,low((60*SYSCLK)/(1000000*6)) YH,high((60*SYSCLK)/(1000000*6));loop cycle = 6 SBIS DS1wire_PIN,DS1wire ;[1/2] WL ;[2] Exit loop if line low YL,1 ;[2] TR1 ;[1/2] 60 us wait with data
RJMP
SHORT
ldi ldi
YL,low((240*SYSCLK)/(1000000*6)) YH,high((240*SYSCLK)/(1000000*6));loop cycle = 6 SBIC DS1wire_PIN,DS1wire ;[1/2] WH ;[2] Exit loop if line hi YL,1 ;[2] TR3 ;[1/2] us wait with data low
TR1:
ha egybol Low az rossz
low ;[2]
Line could not go low
WL:
TR3: RJMP sbiw BRNE SHORT: RET
CLC
;[1] Error ;[4]
WH: ldi ldi TR4: BRNE
YL,low((480*SYSCLK)/(1000000*4)) YH,high((480*SYSCLK)/(1000000*4)) sbiw YL,1 ;[2] TR4 ;[1/2] us wait with data low
SEC RET
;[1] RESET OK. ;[4]
; **************************************************************************** ;******* TOUCHBYTE ; **************************************************************************** ;R0-ban megadott byte-ot kikuldi a touchmemory-nak ;es szimultan beolvas egy byte-ot onnan az R1-be ;Hasznalja a R17, R16 R3, R2, X ; TouchByte: LDI BIT_LOOP: ROR RCALL ROR DEC BRNE RET TOUCHBIT: sbi
R17,8
;[1]
R1 TOUCHBIT R0 R17 BIT_LOOP
;[1] ;[3] ;[1] ;[1] ;[1/2] ;[1]
DS1wire_DIR,DS1wire
;[2] Start Window line = L,
1us <= Tlowr <= 15us ldi ldi BRNE
YL,low((2*SYSCLK)/(1000000*4)) ;[1] 2us YH,high((2*SYSCLK)/(1000000*4)) ;[1] loop cycle = 4 sbiw YL,1 ;[2] BW0 ;[1/2] eddig
SBRC CBI
R0,0 DS1wire_DIR,DS1wire
ldi ldi BRNE
YL,low((13*SYSCLK)/(1000000*4)) ;[1] 13us YH,high((13*SYSCLK)/(1000000*4)) ;[1] loop cycle = 4 sbiw YL,1 ;[2] BW1 ;[1/2]
IN BST BLD
R2,DS1wire_PIN R2,DS1wire R1,7
BW0:
BW1:
ldi ldi TCHL: BRNE CBI RET
;[1/2] ;[2]
;[1] ;[1] ;[1]
YL,low((45*SYSCLK)/(1000000*4)) ;[1] 45us YH,high((45*SYSCLK)/(1000000*4));[1] loop cycle = 4 sbiw YL,1 ;[2] TCHL ;[1/2] DS1wire_DIR,DS1wire ;[2] ;[4]
;*********************************************************************** ;....................................................................... ;Read ROM ; In: X = address ; Out: ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvas egy chippet az X-ban megadott cimre) ; ;Hasznalja a R18, R17, R16, R3, R2, R0; ;....................................................................... ReadDS: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet clr sts rcall BRCS CLC RET RDS1: LDI MOV LDI RCALL RDS2: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST ldi ldi RDS3: brne SEC RET
R16 CRC,R16 TouchReset RDS1
;CRC=0 ;ESZKOZ A BUSZON VAN
R16,DSReadROM ;SEARCH ROM COMMAND R0,R16 R19,7 ;7-SZER OLVASUNK BE TouchByte LDI R16,0xFF ;BEOLVASUNK 8 BITET R0,R16 TouchByte X+,R1 CRCGEN R19 RDS2 R16,0xFF ;BEOLVASSUK A CRC-t R0,R16 TouchByte X+,R1 YL,low((480*SYSCLK)/4000000) YH,high((480*SYSCLK)/4000000) sbiw YL,1 RDS3 ;CHIP RENDBEN
;*********************************************************************** ;....................................................................... ;Read Scratchpad ; In: X = address ; Out: ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvassa a Scratchpadot az X-ban megadott cimre) ; ;Hasznalja a R19, R18, R17, R16, R3, R2, R0; X ;....................................................................... ReadScratchpadMem: LDI XL,LOW(DSRDMem) LDI XH,HIGH(DSRDMem) ;ide olvassa DS Chipet LDI MOV RCALL
R16,DSSkipROM R0,R16 TouchByte
ldi mov RCALL clr sts
R16,DSReadScratchpad R0,R16 TouchByte R16 CRC,R16 ;CRC=0
LDI RDS2s: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST ldi ldi RDS3s: brne RET
;Skip ROM Command
R19,8 ;Read 8 byte LDI R16,0xFF R0,R16 TouchByte X+,R1 CRCGEN R19 RDS2s R16,0xFF R0,R16 TouchByte X+,R1
;BEOLVASSUK A CRC-t
YL,low((480*SYSCLK)/4000000) YH,high((480*SYSCLK)/4000000) sbiw YL,1 RDS3s
;*********************************************************************** ;....................................................................... ;Convert Temperature to digital ; In: ; Out: ;c=1 Chip convert ok ;c=0 Chip none ; ;Hasznalja a R18, R17, R16, R3, R2, R0; SWTmr0 ;....................................................................... ConvTemp: LDI R16,DSConvertTemp ;Convert T Command MOV R0,R16 RCALL TouchByte sbi sbi
DS1wire_PORT,DS1wire DS1wire_DIR,DS1wire
ldi
R16,(SYSTACK/4)*3
;1-wire port ACTIVE 'H' during convert
;most 0.75s a gyari 0.5s
helyett sts sei W1sec: sleep nop lds cpi brne
SWTmr0,R16 ;interrupt enabled!!!
R16,SWTmr0 R16,0 W1sec
cbi
DS1wire_PORT,DS1wire
cbi nop rcall ret
DS1wire_DIR,DS1wire
;1-wire port tre-stated,
external pullup
TouchReset
;************************************************************************* ;......................................................................... ; DS1990A CRC GENERATOR ;IN: R1 ;USE: R21,R20, R4,R3, R0, R18 ;......................................................................... CRCGEN: PUSH R1 LDI R20,8 LDI R18,0x18 PUSH R1 CRC_L: EOR ROR MOV BRCC EOR ZERO: sts POP SEC SBRS CLC ROR PUSH DEC BRNE POP POP RET
lds R1,R3 R1 R1,R3 ZERO R1,R18 ROR CRC,R1 R1
R3,CRC
;CRC
R1
R1,0 R1 R1 R20 CRC_L R1 R1
;************************************************************************* ;......................................................................... ; wait until Dallas 1-wire device is on bus ;IN: ;USE: ;......................................................................... EszkVan: CLI rcall TouchReset rcall ReadDS SEI brcs EszkVan ;mig eszkoz van a buszon, addig nem megy tovabb ldi
YL,low(1285)
ldi
YH,high(1285) push YL YH
;legalabb 1785 ciklusig ne legyenek a
buszon Cikl1:
push CLI rcall ReadDS SEI pop YH pop YL brcs EszkVan sbiw YL,1 brne Cikl1 ret
;ha ismet eszkoz van kezdjuk elolrol!!
;************************************************************************* ;......................................................................... ; Extend DS1920 & DS1820 temperature ;IN: ; out R23:R22 - temperature ;USE: ; ;Tc=8T-2+(8*Count-8*Remainder)/8Count ;......................................................................... ComuteT: LDI ZL,LOW(DSRDMem) LDI ZH,HIGH(DSRDMem) ;ide olvassa DS Chipet LDD LDI
dd16uL,Z+7 dd16uH,0
;CPC
LDD LDI
R22,Z+6 R23,0
;CRM
LSL ROL LSL ROL LSL ROL
dd16uL dd16uH dd16uL dd16uH dd16uL dd16uH
;8*CPC
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*CRM
SUB SBC
dd16uL,R22 dd16uH,R23
LDD LDI
dv16uL,Z+7 dv16uH,0
MOV OR BRNE LDI LDI RJMP
R0,dv16uL r0,dv16uH DIV1 R16,0 R17,0 LKI1
;CPC
;0-VAL NEM OSZTUNK
DIV1:
RCALL
div16u
;OSZTAS eredmeny az
LKI1: SBCI SBCI
CLC dres16uL,2 dres16uH,0
LDD LDD CBR
R22,Z+0 R23,Z+1 R22,1
;Temperature
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*T
ADD
R22,dres16uL
;R22,R23 a korigalt
ADC ret
R23,dres16uH
R16,R17-ben
;eredmeny-2
;Truncate 0.5C
homerseklet
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in http://avr-asm.tripod.com/dallas1.html (1 of 2)1/20/2009 9:03:56 PM
16 BIT MATH (AVR 202)
length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dallas1.html (2 of 2)1/20/2009 9:03:56 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DALLAS 1 WIRE CRC CHECK HOME RETRO_DAN ASM FORUM
I've implemented the 1-wire CRC with both calculation and table lookup.
ASM MATH
I haven't actually used it with 1-wire stuff, but for
TUTORIAL #1
some other communication.
TUTORIAL #2
These routines do 1 byte at a time, so you need to put input data into the register crc_in, and the register crc is used for the crc value. So what you typically do is the set crc to whatever init value it should have (I think it's 0 for 1-wire), and run one of these routines for each byte. And in the end register crc will contain the crc value calulated.
TUTORIAL #3 MATH 200 MATH 200b MATH 201
Calculated: dow_crc: ldi crc_bitcnt, 8 crc_loop: mov crc_data, crc_in eor crc_data, crc ror crc_data mov crc_data, crc brcc crc_zero ldi crc_temp, 0x18 eor crc_data, crc_temp crc_zero: ror crc_data mov crc, crc_data lsr crc_in dec crc_bitcnt brne crc_loop ret
MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7
Table lookup: dow_crc: ldi ZL, low(crc_tab * 2) ldi ZH, high(crc_tab * 2) eor r0, crc_in add ZL, r0 brcc crc_b1 inc ZH crc_b1: lpm ret
COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM
crc_tab: .db 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126,
SORT 220 32, 163, 253, 31, 65 CRC 236 XMODEM REC UART 304
.db 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220 .db 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98
UART 305 UART 128 UART BUFF USB 232
.db 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255 .db 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7 .db 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154
AVR ISP ISP 2313 ISP 1200
.db 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36 .db 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185 .db 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242,
AVR SPI I2C 300 I2C 302 I2C TWI26
172, 47, 113, 147, 205 .db 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80 .db 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238
I2C/TWI 128
.db 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76,
I2C/TWI AT8
18, 145, 207, 45, 115
DALLAS-1W
234, 105, 55, 213, 139
.db 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, .db 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41,
DALLAS CRC ETHNET 8019 TEA ADC 128
119, 244, 170, 72, 22 .db 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168 .db 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 Programming the AVR Microcontrollers in Machine Language
KBD PC/128 PS2 EMU
AVR << Prev | Ring Hub | Join | Rate| Next >>
BOOT MG8 BOOT DR8 ALM CLK © WebRing Inc.
CLOCK 8564
Search
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dalcrc.html (1 of 2)1/20/2009 9:04:29 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/dalcrc.html (2 of 2)1/20/2009 9:04:29 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
ETHERNET DRIVER FOR RTL8019 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102
; *************************************************************************** ; ; File Name :"RTL8019.asm" ; Title :RTL8019AS Ethernet Controller driver ; Date :2002.11.22. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; EGZ-03002-v1 Ethernet Driver ; ; Support Devices ; RTL8019AS Ethernet Controller Card ; ; Provides functions to initialize the Realtek 8019AS, and send and retreive ; packets ; ;Ethernet Frame Header ; ; +--------------------------------------+ ; | Destination | Source | Frame | ; | Address | Address | Type | ; | (6 octets) | (6 octets) |(2 octets)| ; +--------------------------------------+ ;
LPM 108 EPROM 100
.EQU NICBASE = 0x4300h ; IRQ = 0 ; BOOTROM = none
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; ****************************************************************** ;* REALTEK CONTROL REGISTER OFFSETS ;* All offsets in Page 0 unless otherwise specified ;* All functions accessing CR must leave CR in page 0 upon exit ; ****************************************************************** ; RTL8019AS Register Def
UART 305 UART 128 UART BUFF USB 232
.EQU
NICCR
= 0x00
;Command Register R/
W ;This register is used to select register pages, ;enable or disable remote DMA operation and
AVR ISP
;issue commands.
ISP 2313 ISP 1200
.EQU
NICISR
= 0x07
;Interrupt Status
Register, R/W in Page0 ;This register reflects the
AVR SPI I2C 300 I2C 302 I2C TWI26
NIC status. The host ;reads it to determine the cause of an interrupt ;Individual bits are cleared by writing a "1"
I2C/TWI 128 I2C/TWI AT8
;into the corresponding bit. ;It must be cleared after power up.
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128
.EQU Register, W in Page0, Type=R in Page2
NICIMR
= 0x0F
;Interrupt Mask ;All bits correspond to the
bits in the ISR register ;POWER UP=all 0s. Setting individual bits will
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44
;enable the corresponding interrupts. .EQU Register, Type=W in Page0, Type=R in Page2
KBD 240 MUX 242 KBD PS2
.EQU
= 0x04
;Transmit Status
the status of a packet transmission .EQU NICRCR = 0x0C Configuration Register, Type=W in Page0, Type=R in Page2 .EQU
NICRSR
.EQU .EQU
NICCLDA0 = 0x01 NICCLDA1 = 0x02
;Receive
= 0x0C
;Receive Status
Register, Type=R in Page0
BOOT DR8
CLOCK 8564
NICTSR
;Transmit
;This register indicates
BOOT MG8
ALM CLK
;Data Configuration
Register, Type=R in Page0
KBD PC/128 PS2 EMU
= 0x0E
.EQU NICTCR = 0x0D Configuration Register, Type=W in Page0, Type=R in Page2
LCD 2313 LCD44 2313
NICDCR
;Current Local DMA
Registers Type=R in Page0 ;These two registers can be read to get the ;current local DMA address.
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
.EQU Register, Type=W in Page0, Type=R in Page 2
NICPSTART = 0x01
;Page Start ;The Page Start register
sets the start page ;address of the receive buffer ring
PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
.EQU Register, Type=W in Page0, Type=R in Page2
NICPSTOP = 0x02
;Page Stop ;The Page Stop register
sets the stop page ;address of the receive buffer ring. In 8 bit ;mode the PSTOP register should not exceed ;to 0x60, in 16 bit mode the PSTOP register ;should not exceed to 0x80. .EQU
NICBNRY = 0x03
;Boundary Register,
Type=R/W in Page0 ;This register is used to prevent overwrite ;of the receive buffer ring. It is typically ;used as a pointer indicating the last receive ;buffer page the host has read. .EQU
NICTPSR = 0x04
;Transmit Page
Start Register, Type=W in Page0 ;This register sets the start page address of the ;packet to the transmitted .EQU .EQU
NICTBCR0 = 0x05 NICTBCR1 = 0x06
;Transmit Byte
Count Registers, Type=W in Page0 ;These two registers set the byte counts of the ;packet to be transmitted. .EQU
NICNCR
= 0x05
;Number of
Collisions Register, Type=R in Page0 ;The register records the number of collisions ;a node experiences during a packet transmission. .EQU
NICFIFO = 0x06
;First In First Out
Register, Type=R in Page0 ;This register allows the host to examine ;the contents of the FIFO after loopback. .EQU .EQU
NICCRDA0 = 0x08 NICCRDA1 = 0x09
;Current Remote DMA
Address registers, Type=R in Page0 ;These two registers contain the current address of remote DMA. .EQU .EQU
NICRSAR0 = 0x08 NICRSAR1 = 0x09
;Remote Start
Address Registers, Type=W in Page0 ;These two registers set the start address of ;remote DMA. .EQU .EQU
NICRBCR0 = 0x0A NICRBCR1 = 0x0B
;Remote Byte Count
Registers, Type=W in Page0 ;These two registers se the data byte counts of ;remote DMA. .EQU Error Tally Counter Register, Type=R in Page0
NICCNTR0 = 0x0D
;Frame Alignment
.EQU
NICCNTR1 = 0x0E
;CRC Error Tally
.EQU Tally Counter Register, Type=R in Page0
NICCNTR2 = 0x0F
;Missed Packet
NICPAR0 NICPAR1 NICPAR2 NICPAR3 NICPAR4 NICPAR5
;Physical Address
Counter Register, Type=R in Page0
.EQU .EQU .EQU .EQU .EQU .EQU
= = = = = =
0x01 0x02 0x03 0x04 0x05 0x06
Registers, Type=R/W in Page1 ;These registers contain my Ethernet node address ;and are used to compare the destination adderss ;of incoming packets for acceptation or rejection .EQU
NICCURR = 0x07
;Current Page
Register, Type=R/W in Page1 ;This register points to the page address of ;the first receive buffer page to be used for ;a packet reception. .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU
NICMAR0 NICMAR1 NICMAR2 NICMAR3 NICMAR4 NICMAR5 NICMAR6 NICMAR7
= = = = = = = =
0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
;Multicast Address
Register, Type=R/W in Page1 ;These registers provide filtering bits of ;multicast addresses hashed by the CRC logic .EQU .EQU .EQU
NICCR9346 = 0x01 NICRDMAPORT = 0x10 NICRSTPORT = 0x18
;Page 3
; ***************************************************************************** ; ; RTL ISR Register Bits ; ; ****************************************************************************/ .EQU ISR_RST = 7 .EQU ISR_RDC = 6 .EQU ISR_OVW = 4 .EQU ISR_PTX = 1 .EQU ISR_PRX = 0
; ***************************************************************************** ; ; RTL Register Initialization Values ; ; **************************************************************************** ;RCR : accept broadcast packets and packets destined to this MAC ; drop short frames and receive errors .equ RCR_INIT = 0x04 ;TCR : default transmit operation - CRC is generated .equ
TCR_INIT = 0x00 ;DCR : allows send packet
to be used for packet retreival ;
FIFO threshold: 8-
;
8-bit transfer mode
bits (works) .equ
DCR_INIT = 0x58 ;IMR : interrupt enabled
for receive and overrun events .equ
IMR_INIT = 0x11 ;buffer boundaries -
transmit has 6 256-byte pages ;
receive has 26 256-byte
;
entire available packet
pages buffer space is allocated .equ .equ .equ
TXSTART_INIT = 0x40 RXSTART_INIT = 0x46 RXSTOP_INIT = 0x60
; ********************************************************* ;* Receive RTL8019's Ring Buffer Page Header Layout ;* This is the 4-byte header that resides infront of the ;* data packet in the receive buffer. ; ********************************************************* .equ enetpacketstatus= 0x00 .equ nextblock_ptr = 0x01 .equ enetpacketLenL = 0x02 .equ enetpacketLenH = 0x03
; LANBUFSIZE: The size of the buffer that holds incoming and outgoing packets. .equ
LANBUFSIZE = 1564
; ***************************************************************************** ; ; Ethernet constants ; ; **************************************************************************** .equ ETHERNET_MIN_PACKET_LENGTH = 0x3C .equ ETHERNET_HEADER_LENGTH = 0x0E .equ .equ
IP_TCP_HEADER_LENGTH = 40 TOTAL_HEADER_LENGTH = IP_TCP_HEADER_LENGTH
+ETHERNET_HEADER_LENGTH
; *************************************************************************** .ESEG ; ETHADDR: The Ethernet address ; 48 bit IEEE OUI (Organizationally Unique Identifier) EETHADDR:
.db
"DEDO",0x00,0x01
; *************************************************************************** .DSEG ; packet[LANBUFSIZE] ; ; The packet array is used to hold incoming and outgoing packets. ; The device driver fills this with incoming packets. pageheader: .byte 4
;Rx RTL8019's page
header packet: nextPage:
.byte LANBUFSIZE .byte 1
;RTL8019's page
header -> next page currentRetreiveAddress:
.byte 2
;innen kell
a kilvasast folytatni (pointer)
;pointers to locations in the RTL8019 receive buffer uip_len: .byte 2 ETHADDR:
.byte 6
; *************************************************************************** .CSEG ;***************************************************** ;** SetLANToActive ;** ;** IN: ;** ;** Out: ;* ;* Alt: R16 ;* ;* Description: Sets LAN to Active & SRAM to Inactive ;* ; SetLANToActive: SBI RAMCS_PORT,RAMCS nop CBI LANCS_PORT,LANCS nop ret ;***************************************************** ;** SetLANToInactive ;** ;** IN: ;** ;** Out: ;* ;* Alt: R16 ;* ;* Description: Sets LAN to Inactive LANCS=H ;* ; SetLANToInactive: SBI LANCS_PORT,LANCS nop ret
;***************************************************** ;** SetISAReset ;** ;** IN: R0 -> 1 ISA Reset, 0 Normal mode ;** ;** Out: ;* ;* Alt: ;* ;* Description: Sets ISA RESET Line to R0; 0 = low, 1 = hi ;* ; SetISAReset: sbrs sbrc
R0,0 CBI R0,0 SBI
LANRES_PORT,LANRES LANRES_PORT,LANRES
nop ret ;***************************************************** ;** Wait1ms ;** ;** In: R16 - 16*1ms varakozas ;** ;** Out: ;** ;** ;** Alt R16, XL,XH ;** ;** Description: wating for R16 * 1 ms ;* Wait1ms: ldi XL,low(SYSCLK/(5*1000)) ldi Xh,high(SYSCLK/(5*1000)) Waitx1: sbiw XL,1 ;[2] \ nop ;[1] - 5 cycles in loop brne dec brne ret
Waitx1 R16 Wait1ms
;[2] /
;****************************************************** ;** RTLHW_Reset ;** ;** In: ;** ;** Out: ;** ;** ALt: R0, R16, XL, XH ;** ;** Description: Power-up initialization of the RTL8019 and ISA ;* RTLHW_Reset: rcall clr inc rcall ldi rcall
SetLANToInactive R0 R0 SetISAReset R16,10 Wait1ms
clr rcall ret
R0 SetISAReset
;10ms
warakozas
; ***************************************************************************** ;** RTLreadReg ;** ;** IN: R16 - RTL_ADDRESS offset ;** ;** Out: R17 - register data ;** ;** Alt: ;** ;** Description: Reads byte from RTL8019 register ;* RTLReadReg: rcall SetLANToActive push XL push XH ldi XL,low(NICBASE) add XL,R16 ldi XH,high(NICBASE) ldi R17,0 adc XH,R17 = NIC real address to ISA ld R17,X rcall SetLANToInactive pop XH pop XL ret ; ***************************************************************************** ;** RTLWriteReg ;** ;** IN: R16 - RTL_ADDRESS offset ;** R17 - RTL_DATA ;** ;** Out: ;** ;** Alt: R0 ;** ;** Description: Writes byte to RTL8019 register. ;* RTLWriteReg: rcall SetLANToActive push XL push XH clr R0 ldi XL,low(NICBASE) add XL,R16 ldi XH,high(NICBASE) adc XH,R0 = NIC real address to ISA st X,R17 rcall SetLANToInactive pop XH pop XL ret
;X
;X
; *********************************************************************** ;** RTL8019_Init ;** ;** IN: ;** ;** Out: ;** ;** ALt: R0, R16, XL, XH ;** ;* Description: Sets up the RTL8019 NIC hardware interface, and initializes ;* the buffers and configuration of the NIC ; RTL8019_Init: rcall RTLHW_Reset ;do soft reset & clear pending interrupt ldi R16,NICISR ;clear Interrupt register rcall RTLReadReg ldi R16,NICISR rcall RTLWriteReg ldi
R16,50
;50ms
rcall
Wait1ms
ldi
R16,NICCR
;stop the
ldi rcall ldi rcall
R17,0x21 RTLWriteReg R16,2 Wait1ms
;Delay 2ms ;make sure
ldi ldi
R16,NICCR R17,0xC0
;select
rcall
RTLWriteReg
ldi
R16,NICCR9346
ldi rcall
R17,0xC0 RTLWriteReg
ldi ldi
R16,0x04 R17,0b10000000
rcall
RTLWriteReg
ldi ldi
R16,0x05 R17,0b00100000
rcall
RTLWriteReg
ldi ldi
R16,0x06 R17,0b00010000
rcall
RTLWriteReg
ldi ldi rcall
R16,0x0D R17,0x00 RTLWriteReg
ldi ldi rcall
R16,NICCR9346 R17,0x00 RTLWriteReg
;End Config
ldi
R16,NICCR
;stop the
ldi rcall
R17,0x01 RTLWriteReg
varakozas
NIC, abort DMA, page 0
nothing is coming in or going out
;
CONFIGx
Page3
;Enable SW
Config
;IRQ0, Base
0x300
;
AutoDetect, ROM Disabled
;
Halfduplex, LED0 - link, LED1 - RX led2 - TX
; !!!!
NIC, page 0
ldi ldi Normal Operation, FIFO Treshold, Auto Init Remote rcall
R16,NICDCR R17,DCR_INIT
ldi ldi rcall ldi rcall
R16,NICRBCR0 R17,0x00 RTLWriteReg R16,NICRBCR1 RTLWriteReg
;Remote DMA
ldi ldi
R16,NICRCR R17,0x04
;only
rcall
RTLWriteReg
;
ldi ldi
R16,NICTPSR R17,TXSTART_INIT
;Transmit
rcall
RTLWriteReg
ldi ldi
R16,NICTCR R17,0x02
rcall
RTLWriteReg
ldi ldi
R16,NICPSTART R17,RXSTART_INIT
;page
rcall ldi
RTLWriteReg R16,NICBNRY
;utolso
rcall
RTLWriteReg
ldi ldi
R16,NICPSTOP R17,RXSTOP_INIT
rcall
RTLWriteReg
ldi ldi
R16,NICCR R17,0x61
;Stop &
rcall ldi
RTLWriteReg R16,2
;2ms
rcall
Wait1ms
ldi ldi
R16,NICCURR R17,RXSTART_INIT
rcall
RTLWriteReg
ldi
ZL,low(EETHADDR)
;MAC
ldi call sts mov ldi
ZH,high(EETHADDR) EERead ETHADDR+0,R0 R17,R0 R16,NICPAR0
;Setup our
rcall
RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+1,R0 R17,R0 R16,NICPAR1 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+2,R0 R17,R0 R16,NICPAR2 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+3,R0 R17,R0 R16,NICPAR3 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+4,R0 R17,R0 R16,NICPAR4 RTLWriteReg
adiw call sts mov ldi rcall
ZL,1 EERead ETHADDR+5,R0 R17,R0 R16,NICPAR5 RTLWriteReg
ldi ldi
R16,NICCR R17,0x21
rcall
RTLWriteReg
ldi ldi
R16,NICDCR R17,DCR_INIT
rcall
RTLWriteReg
ldi ldi
R16,NICCR R17,0x22
rcall
RTLWriteReg
ldi ldi rcall
R16,NICISR R17,0xFF RTLWriteReg
;Clear
ldi ldi
R16,NICIMR R17,IMR_INIT
;11,
rcall
RTLWriteReg
;packet
;0x58
RTLWriteReg
Byte Count =0x0000
packets with broadcast destination address are accepted
Page Start Register=40
;Internal
loopback
address of the receive buffer ring = 46
olvasott page = 46
;stop page
address of the receive buffer ring = 60
Abort DMA
varakozas
;Rx Page =
46
address from EEPROM
MAC Address
;Stop NIC,
Abort DMA
;58 Normal
operation...
;Start
Command, DMA abort
pending Interrupt
Interrupt Enable received with no errors ;receive buffer has been exhausted ldi ldi
R16,NICTCR R17,TCR_INIT
rcall
RTLWriteReg
ldi ldi rcall
R16,NICCR R17,0x22 RTLWriteReg
;00 -
Normal operation
;start the
NIC ret
; *********************************************************************** ;** RTL8019endPacketSend ;** ;** In : ;** ;** ;** Alt : ;** ;* Description: Ends a packet send operation and instructs the NIC to transmit ;* the frame over the network ; RTL8019endPacketSend: ldi R16,NICCR ;send the contents of the transmit buffer onto the network ldi R17,0x24 rcall RTLWriteReg ;clear the remote DMA interrupt ldi R16,NICISR ldi R17,(1< sendPacketLength push R16 ;R17:R16 - > packetLength ldi ldi rcall
packf: transmitting a packet - wait for it to finish
R16,NICCR R17,0x22 RTLWriteReg
ldi
;start the NIC
R16,NICCR
rcall
RTLReadReg
andi brne
R17,0x04 packf
;still
;while( readRTL(CR)
& 0x04 );
;load beginning page for transmit buffer ldi ldi rcall
R16,NICTPSR R17,TXSTART_INIT RTLWriteReg ;set start address
for remote DMA operation ldi ldi rcall ldi ldi rcall
R16,NICRSAR0 R17,0x00 RTLWriteReg R16,NICRSAR1 R17,0x40 RTLWriteReg ;clear the packet
stored interrupt ldi ldi
R16,NICISR R17,(1<= RXSTOP_INIT) || (bnry <
ldi ldi rcall ldi ldi rcall ldi ldi rcall ldi ldi rcall clc ret
R16,NICBNRY R17,RXSTART_INIT RTLWriteReg R16,NICCR R17,0x62 RTLWriteReg R16,NICCURR R17,RXSTART_INIT RTLWriteReg R16,NICCR R17,0x22 RTLWriteReg
ldi
R16,NICRBCR0
;initiate
ldi rcall ldi ldi rcall
R17,0x04 RTLWriteReg R16,NICRBCR1 R17,0x00 RTLWriteReg
;Remote
ldi ldi rcall ldi mov rcall
R16,NICRSAR0 R17,0x00 RTLWriteReg R16,NICRSAR1 R17,R20 RTLWriteReg
;Remote
ldi ldi rcall
R16,NICCR R17,0x0A RTLWriteReg
;Start
ldi
R18,4
;4 byte-ot
ldi ldi
XL,Low(pageheader) XH,high(pageheader)
;ide
rcall st dec brne
ldi R16,NICRDMAPORT RTLReadReg X+,R17 R18 Getph
ldi
R16,NICCR
ldi rcall
R17,0x22 RTLWriteReg
rcall
WaitToDMA
lds lds
ZL,pageheader+enetpacketLenL ZH,pageheader+enetpacketLenH
;
lds
R16,pageheader+nextblock_ptr
;
sts
nextPage,R16
;
ldi sts sts
R17,4 currentRetreiveAddress+0,R17 currentRetreiveAddress+1,R20
;
RXSTART_INIT)) invpointer:
;Z= meg
mindig 0!! jopointer: DMA to transfer the RTL8019 packet header
Byte Count = 4
start address= Start boundary page
Remote Read DMA
olvasunk be
Getph:
;end the
DMA operation
Z=rxlen
nextPage eltaroljuk ,aborthoz kell
innen folytatjuk majd a kiolvasast (offset cim) ;if the nextPage pointer is invalid, the packet is not ready yet - exit ldi cp brsh ldi cp brcs
R18,RXSTOP_INIT R16,R18 pageErr1 R18,RXSTART_INIT R16,R18 pageErr1 ;if((nextPage >=
clr sub sbc sec ret
R18 ZL,R17 ZH,R18
clr clr clc ret
Zl ZH
RXSTOP_INIT) || (nextPage < RXSTART_INIT))
pageErr1:
;rxlen-4
; ***************************************************************************** ; Device Manager ; A foprogrambol ezek hivhatoak ; ***************************************************************************** ;* RTL8019dev_send ;* ;* In: ;* ;* Out:
http://avr-asm.tripod.com/ethnet8019.html (1 of 2)1/20/2009 9:05:10 PM
16 BIT MATH (AVR 202)
;* ;* Alt: ;* ;* Description:
Sends the packet contained in
packet over the network ; RTL8019dev_send: ldi ldi RTL8019dev_sendA: push push rcall
R16,low(LANBUFSIZE) R17,high(LANBUFSIZE) R16 R17 RTL8019beginPacketSend
;send packet, using data in ip_appdata if over the IP+TCP header size ldi ldi pop pop rcall
XL,Low(packet) XH,high(packet) ZH ZL RTL8019sendPacketData
rcall ret
RTL8019endPacketSend
; ***************************************************************************** ;* RTL8019dev_poll ;* ;* In: ;* ;* Out: Z = Length of the packet retreived, or zero if no packet retreived ;* Y = Address of retreived packet ;* c flag = 0, no packet ;* ;* Description: Polls the RTL8019 looking for an overflow condition or a new ;* packet in the receive buffer. If a new packet exists and will ;* fit in packet, it is retreived, and the length is returned. ;* A packet bigger than the buffer is discarded ; *****************************************************************************/ ; RTL8019dev_poll: rcall RTL8019beginPacketRetreive ;Z = packetLength brcs Vanpacket2 ;if there's no packet or an error ;exit without ending the operation ret Vanpacket2: cpi ZL,low(LANBUFSIZE+1) ldi R16,high(LANBUFSIZE+1) ;drop anything too big for the buffer cpc ZH,R16 brcs PacketSizejo ;Ezt el kell dobni, tul nagy rcall RTL8019endPacketRetreive clr ZL clr ZH clc ret PacketSizejo: push packet data into the IP packet buffer push ldi ldi rcall rcall pop pop sts sts ldi ldi sec ret
ZL
;copy the
ZH XL,low(packet) XH,high(packet) RTL8019retreivePacketData RTL8019endPacketRetreive ZH ZL pageheader+enetpacketLenL,ZL pageheader+enetpacketLenH,ZH YL,low(packet) YH,high(packet)
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/ethnet8019.html (2 of 2)1/20/2009 9:05:10 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
TEA PROTOCOL HOME RETRO_DAN ;(C)2005 wek http://www.efton.sk ;free for personal use ;for commercial use, please contact [email protected]
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2
;implementation of original TEA algorithm by Needham&Wheeler for AVR ;
TUTORIAL #3 MATH 200 MATH 200b
;uses 8 bytes of SRAM (input/output data) and 14 registers ;!!! uses reordered key !!! ;;!!! reordered key !!! k[1]k[0]k[3]k[2]
MATH 201 MATH 202 MATH 32X
;6861 cycles ;5E=94 words = 188 bytes, excl. key ;no stack
MATH YX DIV16 XX DIV 24 24 DIV 3216
;key can be easily placed into SRAM - replace lpm xxx,Z + by ld xxx,Z+
FLOAT 128 SQRT16
;for devices which don't support lpm xxx,Z+ replace it by lpm; mov xxx,r0
MATH 202 .dseg
MATH 202 DEC ASCII
ydata: zdata:
INT ASCII HX2ASC
.byte .byte
4 4
;register definitions .def ZL .def ZH .def YL = r28 .def YH = r29
AVG8 222 FFT7 COPY 102
= r30 = r31
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
.def .def .def .def .def .def .def .def .def
tmp0 tmp1 tmp2 tmp3 tmp4 tmp5 tmp6 tmp7 tmp8
= = = = = = = = =
r1 r2 r3 r4 r5 r6 r7 r8 r9
.def .def .def .def
sum0 sum1 sum2 sum3
= = = =
r16 r17 r18 r19
.def
RoundCnt
= r20
UART 305 UART 128 UART BUFF
.cseg
USB 232
Tea:
AVR ISP
ldi RoundCnt,2*32 clr sum0 clr sum1 clr sum2 clr sum3 ldi YL,LOW(zdata) ldi YH,HIGH(zdata) ldd tmp0,Y+0 ldd tmp1,Y+1 ldd tmp2,Y+2 ldd tmp3,Y+3 TeaRound: ldi ZL,LOW(Key*2) ldi ZH,HIGH(Key*2) subi sum0,$47 sbci sum1,$86 sbci sum2,$C8 sbci sum3,$61 TeaSubRound: clr tmp4 ;z>>5 but as (z<<3)>>8
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B
(simultaneously preparing for z<<4) lsl rol rol rol rol lsl rol rol rol rol lsl rol rol rol rol
tmp0 tmp1 tmp2 tmp3 tmp4 tmp0 tmp1 tmp2 tmp3 tmp4 tmp0 tmp1 tmp2 tmp3 tmp4
lpm
tmp5,Z+
add lpm adc lpm adc lpm adc
tmp5,tmp1 tmp6,Z+ tmp6,tmp2 tmp7,Z+ tmp7,tmp3 tmp8,Z+ tmp8,tmp4
lsl rol rol rol lpm add lpm adc lpm adc lpm adc
tmp0 ;last shift for z<<4 tmp1 tmp2 tmp3 tmp4,Z+ ;z<<4 + key[0] tmp0,tmp4 tmp4,Z+ tmp1,tmp4 tmp4,Z+ tmp2,tmp4 tmp4,Z+ tmp3,tmp4
eor eor eor eor
tmp5,tmp0 tmp6,tmp1 tmp7,tmp2 tmp8,tmp3
;xor the first two parts
ldd ldd ldd ldd add adc adc adc
tmp0,Y+0 tmp1,Y+1 tmp2,Y+2 tmp3,Y+3 tmp0,sum0 tmp1,sum1 tmp2,sum2 tmp3,sum3
;z+sum
eor eor eor eor
tmp0,tmp5 tmp1,tmp6 tmp2,tmp7 tmp3,tmp8
ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
;!!! reordered key !!! k[1]k[0]k[3]k
[2]
BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS
;z>>5 + key[1]
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
sbrc RoundCnt,0 increment sum (AVR: decrement by its neg) rjmp TeaRoundX3 ldi YL,LOW(ydata) add the calculated value in tmp (and it remains valid for the subround, too) ldi YH,HIGH(ydata) rjmp TeaRoundX4 TeaRoundX3: ldi YL,LOW(zdata) set pointer to zdata ldi YH,HIGH(zdata) TeaRoundX4: ldd
tmp4,Y+0
add std ldd adc std ldd adc std ldd adc std
tmp0,tmp4 Y+0,tmp0 tmp4,Y+1 tmp1,tmp4 Y+1,tmp1 tmp4,Y+2 tmp2,tmp4 Y+2,tmp2 tmp4,Y+3 tmp3,tmp4 Y+3,tmp3
;in the first subround
;and set pointer to ydata to next
;in the second subround only
;add the calculated value to
y or z
dec RoundCnt brne TeaRoundA ret TeaRoundA: sbrs RoundCnt,0 rjmp TeaRound rjmp TeaSubRound
Key: ;
.db .db .db .db .db
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 $0f,$1e,$2d,$3c $4b,$5a,$69,$78 $87,$96,$a5,$b4 $c3,$d2,$e1,$f0
Programming the AVR Microcontrollers in Machine Language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/tea.html (1 of 2)1/20/2009 9:05:44 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/tea.html (2 of 2)1/20/2009 9:05:44 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
ANALOG TO DIGITAL COMPARATOR (AVR 128) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2
MATH 201 MATH 202 some features of the
;* AVR's on-board precision Analog Comparator. ;* ;* The Application note is written as a program example
MATH YX performing the
DIV 24 24
;* following tasks: ;* ;* - Wait for a positive output edge by polling the
DIV 3216 FLOAT 128
comparator output ;* - Wait for a positive output edge by polling the
SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
Setup and Use the Analog Comparator 1.1 97.07.04 AT90Sxxxx (Devices with Analog
;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION: ;* This Application note shows how to enable and use
MATH 200b
DIV16 XX
Title: Version: Last updated: Target:
Comparator)
MATH 200
MATH 32X
A V R 1 2 8
************************
ASM MATH
TUTORIAL #3
N O T E
interrupt flag ;* - Enable interrupt on comparator output toggle. The interrupt routine ;*
increments a 16 bit register counter each time it
is executed ;* ; ***************************************************************************
AVG8 222 .include "1200def.inc"
FFT7 COPY 102
;***** Global Register Variables
LPM 108 EPROM 100
FLASH CARD
temp
=r16
;temporary storage
.def
cntL
=r17
;register counter
.def
cntH
=r18
;register counter
register
SER EPROM DFLASH AT45
.def
low byte high byte
VFX SMIL
;***** Interrupt Vectors
VFX MEM rjmp
SORT 220 CRC 236
;Reset Handle
ACIaddr ANA_COMP
;Analog Comparator Handle
.org
RESET
rjmp
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
; *************************************************************************** ;* ;* "ANA_COMP" ;* ;* This interrupt routine is served each time ACI in the ACSR register is ;* set, provided that the Analog Comparator interrupt is enabled (ACIE is ;* set). The routine increments a 16-bit counter each time it is run ;* ;* Number of words :5 ;* Number of cycles :8 ;* Low registers used :1 (ac_tmp) ;* High registers used :2 (cntL,cntH) ;* ; ***************************************************************************
DALLAS CRC ;***** Interrupt Routine Register Variables
ETHNET 8019
.def
TEA ADC 128
ac_tmp
=r0
;temporary storage
register for SREG
ADC 10B
;***** Code
ADC 400
ANA_COMP:
ADC 401 THERM 232
in
ac_tmp,SREG
;temporarily store the
subi sbci out reti
cntL,low(-1) cntH,high(-1) SREG,ac_tmp
;counter = counter + 1 ;restore Status register
Status register
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
; *************************************************************************** ;* ;* PROGRAM EXECUTION STARTS HERE ;* ; ***************************************************************************
BOOT DR8 RESET:
ALM CLK CLOCK 8564
;***** Include if used on device with RAM ; ldi temp,low(RAMEND) ; out SPL,temp ; ldi temp,high(RAMEND) ; out SPH,temp
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************************** ;* ;* "wait_edge1" ;* ;* This piece of code waits until the output of the comparator (the ACO-bit ;* in ACSR) goes high. This way of doing it requires no setup, however, ;* extremely short pulses can be missed, since the program runs three clock ;* cycles between each time the comparator is checked. Another disadvantage ;* is that the program has to wait for the output to be come negative first, ;* in case the output is positive when polling starts. ;* ;* Number of words :4 ;* Number of cycles :4 per loop. Response time: 3 - 5 clock cycles ;* Low registers used :None ;* High registers used :None ;* ; *************************************************************************** ;***** Code wait_edge1: sbic rjmp we1_1: rjmp
ACSR,ACO ;if output is high wait_edge1 ; wait sbis ACSR,ACO ;if output is low we1_1 ; wait
; *************************************************************************** ;* ;* "wait_edge2" ;* ;* This piece of code waits until the output of the comparator (the ACO-bit ;* in ACSR) goes high. This is a more secure solution, since the interrupt ;* flag is polled. This allows the user to insert code within the wait loop ;* because hardware "remembers" pulses of shorter duration than the polling ;* interval. Another positive feature is that there is no need to wait for ;* a preceeding negative edge. ;* ;* Number of words :5 ;* Number of cycles :Inital setup :2 ;* Flag clearing:1 ;* Loop :4 ;* Response time:3 - 5 ;* Low registers used :None ;* High registers used :None ;* ; *************************************************************************** ;***** Code wait_edge2: ;***** Initial Hardware setup (assumes ACIE = 0 from reset) sbi sbi
ACSR,ACIS0 ACSR,ACIS1
;enable interrupt on rising
ACSR,ACI
;write a "1" to the ACI
output edge ;***** Wait sbi flag to clear it we2_1: sbis rjmp
;----------------------- user code goes here ACSR,ACI ;if ACI is low we2_1 ; wait more
; *************************************************************************** ;* ;* "ana_init" ;* ;* This code segment enables Analog Comparator Interrupt on output toggle. ;* The program then enters an infinite loop. ;* The 16-bit counter is cleared prior to enabling the interrupt. ;* ;* Performance figures apply to interrupt initialization only. ;* ;* Number of words :4 ;* Number of cycles :5 ;* Low registers used :None ;* High registers used :1 (temp) ;* ; *************************************************************************** ;***** Register Variables .def
temp
=r16
;temporary register
;***** Code ana_init: ;***** Clear 16-bit counter clr clr
cntL cntH
;***** Enable Interrupt (assumes ACIE = 0 from reset) ldi
temp,(ACI<<1)
;clear interrupt flag and
out
ACSR,temp
;...to select interrupt on
sei sbi
ACSR,ACIE
;enable global interrupts ;enable Analog Comparator
ACIS1/ACIS0... toggle
interrupt forever:rjmp
forever
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/avr128.html (1 of 2)1/20/2009 9:06:20 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/avr128.html (2 of 2)1/20/2009 9:06:20 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
10 BIT ANALOG TO DIGITAL COMPARATOR FOR 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236
; *************************************************************************** ; ; File Name :'adc.asm" ; Title :ATmega128 internal 10-bit ADC Driver ; Date :2003.08.03. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AVR ; ; *************************************************************************** ; D E S C R I P T I O N ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.08.03 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ; ; ************************************************************************** ;* Hardware Def. ; ; *************************************************************************** ;**** VARIABLES .DSEG
XMODEM REC ;egymas utan kell aljanak!!!! ADCCH0: .byte 2 ADCCH1: .byte 2 ADCCH2: .byte 2 ADCCH3: .byte 2 ADCCH4: .byte 2 ADCCH5: .byte 2 ADCCH6: .byte 2 ADCCH7: .byte 2
UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302
; *************************************************************************** .ESEG
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG
TEA ADC_Init:
ADC 128 ADC 10B ADC 400
clr ldi
R16 R17,16
ldi ldi dec brne
ZL,low(ADCCH0) ZH,high(ADCCH0) st Z+,R16 R17 ADCI1
ldi out
R16,0b00000000 ADMUX,R16
;2*8 csatorna
valtozoterulet = 0
ADC 401 ADCI1:
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
Reference Selection Bits ; REFS1 REFS0 Vref Selection
BOOT MG8
CLOCK 8564 90 DAYS
; 0
1
; 1
0
; 1
1
Reserved Internal 2.56V Voltage Reference with external capacitor at AREF pin ;[5] - ADLAR: ADC Left Adjust Result ;[4:0] - MUX4:0: Analog Channel and Gain Selection Bits
DELAYS CALL ID
0
AVCC with external capacitor at AREF pin
BOOT DR8 ALM CLK
; 0 AREF, Internal Vref turned off
KBD PC/128 PS2 EMU
;[7:6] - REFS1:0:
; MUX4..0 Single Ended Input ; ; ; ; ; ; ; ;
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
00000 00001 00010 00011 00100 00101 00110 00111
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
ATMEL CORP AVR BUTTERFLY
ldi out
R16,0b00011111 ADCSRA,R16
;[7] - ADEN: ADC
Enable ;[6] - ADSC: ADC
AVR BOOK Start Conversion
;[5] - ADFR: ADC Free Running Select ;[4] - ADIF: ADC Interrupt Flag ;[3] - ADIE: ADC Interrupt Enable ;[2:0] - ADPS2:0: ADC Prescaler Select Bits ;ADPS2 ADPS1 ADPS0 Division Factor 0 1 0 1 0 1 0 1
;
0
0
;
0
0
;
0
1
;
0
1
;
1
0
;
1
0
;
1
1
;
1
1
2 2 4 8 16 32 64 128 ret
StartADC: in ori out ret
ZL,ADCSRA ZL,0b11011000 ADCSRA,ZL
;**************************************** ;ADC Conversion Complete Handler ; ; ADC: PUSH ZL PUSH ZH IN ZL,SREG PUSH ZL push R0 in push in push
ZL,ADCL ZL R0,ADCH R0
cbi
ADCSRA,ADEN
;ADC Stop
in inc andi out
ZL,ADMUX ZL ZL,7 ADMUX,ZL
;kovetkezo
clr dec andi add ldi add ldi adc pop st pop st
R0 ZL ZL,7 ZL,ZL ZH,Low(ADCCH0+2) ZL,ZH ZH,high(ADCCH0+2) ZH,R0 R0 -Z,R0 R0 -Z,R0
pop POP OUT POP POP RETI
R0 ZL SREG,ZL ZH ZL
csatorna kivalasztva
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/adc10b.html (1 of 2)1/20/2009 9:06:54 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/adc10b.html (2 of 2)1/20/2009 9:06:54 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
CHEAP ANALOG DIGITAL COMPARATOR (AVR 400) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
MATH 202
EPROM 100
FLASH CARD VFX SMIL
This application note shows how you can make a A/D
the MCU while ;* conversion is taking place. ;* ;* To minimize the usage of external components, this A/ D converter uses ;* the charging of a capacitor (controlled by port D pin 2)through a ;* resistor while converting. ;* The voltage across the capacitor will follow an exponential curve of ;* voltage versus time. By constricting the voltage range of ;* the converter to 2/5Vdd, the exponential curve is a good approximation ;* of a straight line. This makes it possible to simply measure the time ;* it takes before the voltage across the capacitor equals the voltage which
VFX MEM SORT 220
DESCRIPTION
;* comparator interrupt. The usage of interrupts free's
SER EPROM DFLASH AT45
Code Size :37 words Low Register Usage :0 High Register Usage :2 Status Flag Usage :1 (t flag) Interrupt usage :Timer/Counter0 overflow interrupt, Analog comparator interrupt
addition to the Analog
COPY 102 LPM 108
[email protected]
;* uses the Timer/Counter0 overflow interrupt in
AVG8 222 FFT7
Support E-mail:
capacitor. This solution
INT ASCII HX2ASC
Low Cost A/D Converter 1.0 97.07.18 AT90Sxxxx (All AVR Devices)
;* device, one external resistor and one external
MATH 202 DEC ASCII
Title: Version: Last updated: Target:
converter using a AVR
FLOAT 128 SQRT16
A V R 4 0 0
************************
ASM MATH
DIV 3216
N O T E
;* is to be converted. To do this we use the analog comparator. The ;* comparator will give an interrupt when the voltage
CRC 236
across the capacitor ;* rises above the measurement voltage. The output is
XMODEM REC UART 304
divided into 64 ;* different levels. ;* ;* To ensure correct timing the time constant of the RC-
UART 305 UART 128
network must
UART BUFF USB 232
;* satisfie 512*(1/f)=-R*C*ln(1-2/5). ;* For the A/D converter to operate properly, the capacitor must be
AVR ISP ISP 2313
;* completly discharged between each conversion. This is done by allowing ;* the discharging to take a minimum of 200us. ;* ;* ;* *** Initialization ;* ;* 1. Call convert_init ;* 2. Enable global interrupts (with sei) ;* ;* *** A/D conversion ;* ;* 1. Call AD_convert ;* 2. Wait for conversion complete (t to be set) (less
ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
than 521 cycles)
ETHNET 8019
;* 3. Read data from result ; **************************************************************************
TEA ADC 128 ADC 10B
.include "1200def.inc"
ADC 400
;***** Constants
ADC 401 THERM 232
.equ
preset=192
;T/C0
Preset constant (256-64)
IRD 410 LCD HD44
;***** A/D converter Global Registers
LCD 2313
.def
result=r16
;Result and
.def
temp=r17
;Scratch
LCD44 2313 KBD 240
intermediate data register
MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS
; ************************************************************************** ;* ;* PROGRAM START - EXECUTION STARTS HERE ;* ; ************************************************************************** .cseg
DELAYS .org rjmp .org rjmp .org rjmp
CALL ID DTMF 314 PWM 6CH PWM 10K
$0000 RESET OVF0addr ANA_COMP ACIaddr ANA_COMP
;Reset handle ;Timer0 overflow handle ;Analog comparator handle
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ************************************************************************** ;* ;* ANA_COMP - Analog comparator interrupt routine ;* ;* ;* DESCRIPTION ;* This routine is executed when one of two events occur: ;* 1. Timer/counter0 overflow interrupt ;* 2. Analog Comparator interrupt ;* Both events signals the end of a conversion. Timer overflow if the signal ;* is out of range, and analog comparator if it is in range. ;* The offset will be corrected, and the t'flag will be set. ;* Due to the cycles needed for interruption handling, it is necessary ;* to subtract 1 more than was added previously. ;* ;* ;* Total numbers of words : 7 ;* Total number of cycles : 10 ;* Low register usage : 0 ;* High register usage : 2 (result, temp) ;* Status flags : 1 (t flag) ;* ; ************************************************************************** ANA_COMP: in result,TCNT0 ;Load timer value clr out
temp TCCR0,temp
;Stop timer0
subi
result,preset+1 ;Rescale A/D output
cbi set
PORTD,PD2
;Start discharge ;Set conversion
complete flag reti
;Return from
interrupt
; ************************************************************************** ;* ;* convert_init - Subroutine for A/D converter initialization ;* ;* ;* DESCRIPTION ;* This routine initializes the A/D converter. It sets the timer and the ;* analog comparator. The analog comparator interrupt is being initiated by ;* a rising edge on AC0. To enable the A/D converter the global interurrupt ;* flag must be set (with SEI). ;* ;* The conversion complete flag (t) is cleared. ;* ;* Total number of words : 6 ;* Total number of cycles : 10 ;* Low register usage : 0 ;* High register usage : 1 (result) ;* Status flag usage : 0 ;* ; ************************************************************************** convert_init: ldi result,$0B ;Initiate comparator out ACSR,result ;and enable comparator interrupt
ldi
result,$02
out
TIMSK,result
sbi
PORTD,PD2
;Enable timer
interrupt
;Set converter
charge/discharge ;as output ret
;Return from
subroutine
; ************************************************************************** ;* ;* AD_convert - Subroutine to start an A/D conversion ;* ;* DESCRIPTION ;* This routine starts the conversion. It loads the offset value into the ;* timer0 and starts the timer. It also starts the charging of the ;* capacitor. ;* ;* ;* Total number of words : 7 ;* Total number of cycles : 10 ;* Low register usage : 0 ;* High register usage : 1 (result) ;* Status flag usage : 1 (t flag) ;* ; ************************************************************************** AD_convert: ldi result,preset ;Clear counter out TCNT0,result ;and load offset value clt
;Clear conversion
complete flag (t) ldi
result,$02
;Start timer0 with
out sbi
TCCR0,result PORTB,PB2
;Start charging of
prescaling f/8
capacitor
ret
;Return from
subroutine
; ************************************************************************** ;* ;* Example program ;* ;* This program can be used as an example on how to set up the A/D ;* converter properly. ;* NOTE! To ensure proper operation, make sure the discharging period ;* of the capacitor is longer than 200us in front of each conversion. ;* The results of the conversion is presented on port B. ;* To ensure proper discharging we have added a delay loop. This loop is ;* 11 thousand cycles. This will give a 550us delay with a 20MHz oscillator ;* (11ms with a 1MHz oscillator). ;* ; ************************************************************************** RESET: rcall
convert_init
;Initialize A/D
converter sei
;Enable global
interrupt ldi
result,$ff
;set port B as
out
DDRB,result clr result
output Delay:
;Clear temp
counter 1 ldi
temp,$f0
;Reset temp counter
2 loop1:
inc
result
;Count up
temp counter 1 brne
loop1
;Check if inner
inc
temp
;Count up temp
brne
loop1
;Check if delay is
rcall
AD_convert brtc Wait
;Start conversion ;Wait until
out
PORTB,result
;Write result on
rjmp
Delay
;Repeat conversion
loop is finished counter 2 finished
Wait: conversion is complete port B
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K Inhttp://avr-asm.tripod.com/avr400.html (1 of 2)1/20/2009 9:07:27 PM
16 BIT MATH (AVR 202)
System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr400.html (2 of 2)1/20/2009 9:07:27 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
PRECISION 8 BIT ADC (AVR 401) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2
MATH 201 MATH 202
DIV16 XX
slope-alike ;* A/D conversion utilizing the on-chip analog comparator and a few ;* external components. Included is a test program that performs
DIV 24 24 DIV 3216 FLOAT 128 SQRT16
8-bit precision A/D converter 1.03 97.07.17 AT90Sxxxx (All AVR Devices with
;* ;* Support E-mail: [email protected] ;* ;* DESCRIPTION ;* This Application note shows how to perform dual-
MATH 200b
MATH YX
Title: Version: Last Updated: Target:
analog comparator)
MATH 200
MATH 32X
A V R 4 0 1
************************
ASM MATH
TUTORIAL #3
N O T E
;* conversions in a eternal loop, outputting the result to eight LEDs. ;* ; ***************************************************************************
MATH 202
;***** Registers used by mpy9u multiplication routine
MATH 202 DEC ASCII
mc9u
=r0
;multiplicand used by
.def
mp9u
=r1
;multiplier used by
.def .def
m9uL m9uH
=r1 =r2
;result Low byte ;result High byte
multiplication routine
INT ASCII HX2ASC
.def
multiplication routine
AVG8 222 FFT7
;***** Registers used by div17u division routine
COPY 102 LPM 108 EPROM 100 SER EPROM
didL didH dresL
=r1 =r2 =r1
;Dividend
.def .def .def .def
dresH divL divH remL
=r2 =r3 =r4 =r5
.def
remH
=r6
.def .def .def
TinH TinL Tref
=r14 =r15 =r16
;Time to reach input voltage
.def
TH
=r17
;Timer variable
.def
Vref
=r18
;Computed Vref
.def .def
temp temp2
=r19 =r20
;Holds the result of the
division
DFLASH AT45 FLASH CARD VFX SMIL
.def .def .def
;Divisor ;Reminder variables used by
division routine
VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
;Time to reach reference
voltage
UART 305 UART 128 UART BUFF USB 232 AVR ISP ;Port B pins .equ AIN0 .equ AIN1 .equ Ref1 .equ Ref2 .equ LED .equ T
ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
.equ .equ
I2C/TWI 128
=0 =1 =2 =3 =4 =7
PRESC =2 VrefAddr=0
;Timer clocked at CK/8 ;EEPROM Address holding Vref
I2C/TWI AT8 DALLAS-1W
.include "1200def.inc"
DALLAS CRC .cseg .org 0
ETHNET 8019
rjmp reset reti
TEA ADC 128 ADC 10B ADC 400
.org OVF0addr ;** Timer/counter 0 overflow interrupt ******************************
ADC 401 THERM 232
;Reset handler
T0_int:
inc TH
;Increase
timer high-byte reti
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
;*** Reset handler ************************************************** reset: sbi DDRB,LED ser temp used to out DDRD,temp
KBD PS2
;drive LEDs
ldi temp,(1< multiplier ldi temp,128 ;128
KBD PC/128 PS2 EMU
;PB4 and ;Port D as output,
->
multiplicand ( = 2.5 volts)
BOOT MG8
mov mc9u,temp rcall mpy9u
;Tref x 128
clr divH mov divL,TinL rcall div17u
;(Tref x 128) ; ----------; Tcal
ldi out out sbi
;Store Vref
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
temp,VrefAddr EEAR,temp EEDR,dresL EECR,EEWE
DTMF 314 calibrate1: sbic EECR,EEWE rjmp calibrate1
PWM 6CH PWM 10K ENCODE STH-11
;Main program main:
ATMEL CORP AVR BUTTERFLY AVR BOOK
cbi PORTB,T
;Turn off
pull-up on T-pin ldi temp,VrefAddr
;Read Vref from
EEPROM out EEAR,temp sbi EECR,EERE in Vref,EEDR
loop:
rcall reference
;Measure
Tref rcall delay
;A small delay to
let ;
the capacitor
discharge, rcall input
;Measure Tin
brts error
;If Vin > Vcc
calc:
lsr TinH
;TinH -> C
(multiplier) mov mp9u,TinL mov mc9u,Vref
;TinL -> multiplier ;Tref ->
rcall mpy9u
;Tin x Tref
clr divH mov divL,Tref rcall div17u
;(Tin x Vref) ;-----------; Tref
multiplicand
tst dresH breq write error:
ldi temp,255
;
Vin
= 255 mov dresL,temp
write:
com dresL
;Show the
value on the LEDs rcall long_delay rcall long_delay rcall long_delay out PORTD,dresL rol dresL brcs wr1 cbi PORTB,LED rjmp loop wr1:
sbi PORTB,LED rjmp loop
;*** Subroutine delay ****************************************************** delay: ldi temp,$FF d1: dec temp brne d1 ret
long_delay: ser temp2 ld1: rcall delay dec temp2 brne ld1 ret
;*** Subroutine reference ************************************************** ;* Measures Tref reference:
sbi DDRB,AIN0
;Discharge the
sbi DDRB,Ref1 sbi PORTB,Ref1 sbi DDRB,Ref2
;Turn on Vref
rcall delay
;Let the capacitor
clr TH out TCNT0,TH
;Reset timer
cbi DDRB,AIN0
;AIN0 as input
ldi temp,PRESC out TCCR0,temp
;Start timer
sbi DDRB,T
;Turn on the
sbic ACSR,ACO
;If Capacitor
rjmp ref_ok
;
cpi TH,1
;Continue if timer
capacitor
discharge completely
transistor
ref_wait: voltage > reference voltage
conversion
conplete overflow brlo ref_wait ref_ok:
in Tref,TCNT0
;Store Tref
clr temp out TCCR0,temp
;Stop timer
cbi DDRB,T sbi DDRB,AIN0
;Turn off transistor ;Discharge capacitor
cbi PORTB,Ref1 cbi DDRB,Ref1 cbi DDRB,Ref2
;Turn off Vref
ret
;*** subroutine input ************************************************** ;* Measures Tin ;* Returns with the T-flag set if timer overflow (i.e. Vin > Vcc) input:
cbi DDRB,AIN0
;Tri-state
AIN0 clt clr TH out TCNT0,TH
;Clear error flag ;Clear timer
ldi temp,PRESC out TCCR0,temp
;Start timer
sbi DDRB,T
;Turn on transistor
input_wait: sbic ACSR,ACO
;If Capacitor
voltage > Vin rjmp input_ok
;
charging
cpi TH,2 brlo input_wait set
;T=1 indicates Vin
complete
> Vcc input_ok:
in TinL,TCNT0 mov TinH,TH
;Store Tin
input_exit: clr temp out TCCR0,temp
;Stop timer
cbi DDRB,T sbi DDRB,AIN0
;Turn off transistor ;Discharge capacitor
ret
; ******************************************************************** ;* ;* This routine divides a 17 bit number (carry:didH: didLL) on ;* a 16 bit number (divH:divL). ;* The result is placed in (dresH:dresL) ;* ;* The carry flag must contain the 17th bit of the divident before ;* the routine is executed. ;* ;* The routine is based on the div16u - 16/16 Bit Unsigned Division ;* routine found in the avr200.asm application note file ;* ; ********************************************************************
div17u:
clr remL
;clear
remainder Low byte clr remH
;clear remainder
ldi temp,17
;init loop counter
High byte
d17u_1:
rol remL
;shift
dividend into remainder rol remH sub remL,divL
;remainder = remainder -
divisor sbc remH,divH brcc d17u_2 add remL,divL adc remH,divH clc
; ;
;if result negative restore remainder ;
clear carry to
be shifted into result rjmp d17u_3 d17u_2: d17u_3:
;else
sec rol didL
;shift left
dividend rol didH dec temp brne d17u_1 ret
;decrement counter ;if done ; return with
value in didL
; *************************************************************************** ;* ;* "mpy9u" - 9x8 Bit Unsigned Multiplication ;* ;* This subroutine multiplies the two register variables (carry:mp9u) and mc9u. ;* The result is placed (carry:m8uH:m8uL) ;* ;* Number of words :11 (return included) ;* Number of cycles : (return included) ;* Low registers used :3 (mp9u,mc9/m9uL,m9uH) ;* High registers used :1 (temp) ;* ;* Note: Result Low byte and the multiplier share the same register. ;* This causes the multiplier to be overwritten by the result. ;* ; *************************************************************************** mpy9u:
clr m9uH
;clear
result High byte ldi temp,9 ror mp9u m9u_1:
;init loop counter
brcc m9u_2
;if bit 0
of multiplier set add m9uH,mc9u
;
add
multiplicand to result High byte m9u_2:
dec temp
;decrement
loop counter brne m9u_3
;if not done, loop
more ret m9u_3:
ror m9uH
;shift
right result High byte ror m9uL
;rotate right
result L byte and multiplier rjmp m9u_1
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. http://avr-asm.tripod.com/avr401.html (1 of 2)1/20/2009 9:08:03 PM
16 BIT MATH (AVR 202)
The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/avr401.html (2 of 2)1/20/2009 9:08:03 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
THERMOMETER DS1820 VIA RS232 PROGRAM HOME RETRO_DAN ;*********************************************************************** ;* ;* Number :DS1820 ;* File Name :"DS1820.asm" ;* Title :AVR alapu DS1820 thermometer + RS232 interface ;* - LM16x21A Driver via Lattice ispLSI2032 ;* ;* Date :2000.06.12. ;* Version :1.0 ;* Support telephone :+36-70-333-4034 ;* Support fax : ;* Support E-mail :[email protected] ;* Target MCU :AT90S2313 ;* ;* DESCRIPTION ;* kezeli a következõ eszközöket: ;* - DS1820 Thermometer unit ;* - Fulduplex RS232 port ;* - SS0=0 & SS1=0 akkor az LCD port az SPI target ;* ;* AT90S2313 lábkiosztás ;* ;* RESET 1. 20. VCC ;* * RxD (PD0) 2. 19. (PB7) SCK * ;* * TxD (PD1) 3. 18. (PB6) MISO * ;* XTAL2 4. 17. (PB5) MOSI * ;* XTAL1 5. 16. (PB4) SS0 * ;* INT0 (PD2) 6. 15. (PB3 OC1) LED0 ;* INT1 (PD3) 7. 14. (PB2) SS1 * ;* (T0 PD4) 8. 13. PB1 {AIN1} AT45D CS ;* DS1820 T1 (PD5) 9. 12. PB0 {AIN0} ;* GND 10. 11. {PD6 ICP} ;* ;* Kristályfrekvencia: f=1.8432 MHz (T=0.54253 us) ;* ;* * a csillagos IO labak fix huzalozasuak, masra nem hasznalhatok fel!!! ;*********************************************************************** .include "2313def.inc"
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
; ************************************************************************** ;* Hardware Def.
VFX MEM SORT 220
.EQU .EQU
DS1820_BIT = 5 DS1820_PORT =DDRD
;Dallas 1-Wire bus ;Dallas Port cime
.EQU .EQU
LEDPORT LED = 3
;A LED bitcime
.EQU .EQU .EQU .EQU
;SPI selector SS0PORT= DDRB SS0= BP4 SS1PORT= DDRB SS1= BP2
CRC 236 XMODEM REC UART 304
= DDRB
UART 305 UART 128 UART BUFF USB 232
00 LCD
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
; ************************************************************************** ;* UART Def .EQU BaudRate=11 ;11 - 9600 ;7 - 14400 ;5 - 19200 ;1 - 57600
I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
; *************************************************************************** ;***** Divide Subroutine Register Variables
ETHNET 8019
.def .def .def .def .def .def .def .def
TEA ADC 128 ADC 10B ADC 400 ADC 401
drem16uL=r14 drem16uH=r15 dres16uL=r16 dres16uH=r17 dd16uL =r16 dd16uH =r17 dv16uL =r18 dv16uH =r19
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS
; *************************************************************************** ;* SPI Master, Mode 0, MSB-first ;* ;* MAJOR ROUTINES: ;* init_spi: initializes the port lines used for SPI. ;* No calling requirements, returns nothing. ;* ena_AT: forces SCK low, and activates /SS signal. ;* No calling requirements, returns nothing. ;* disa_AT: brings /SS signal hi (inactive). ;* No calling requirements, returns nothing. ;* rw_spi: sends/receives an 8-bit data. ;* Must set up data to be sent in (spi_lo) ;* prior to calling; it returns received data in ;* the same register (spi_lo register). ;* ;* .equ sck = 7 ;PB7 pin .equ miso = 6 ;PB6 pin .equ mosi = 5 ;PB5 pin
CALL ID
.equ
ATss
= 1
;PB4=1 , PB2=0 pin AT45D041 CS
???????
.def .def
spi_lo temp
= R0 = R16
;change as needed ;misc usage, must be in upper regs for IMMED
ATMEL CORP
.def .def .def .def
ATComm ATPoint ATPageL ATPageH
= = = =
;AT45Dxxx ;AT45Dxxx ;AT45Dxxx ;AT45Dxxx
AVR BUTTERFLY
.def .def
LCDLo LCDHi
= R20 = R21
;LCD Low byte ;
.equ
BFSeg
= 32
;32 byte r/w
.macro CBI cbi .endm
Select_LCD SS0PORT+1,SS0 SS1PORT+1,SS1
DTMF 314 PWM 6CH PWM 10K
mode
ENCODE STH-11
R20 R21 R21 R22
command parameter register Buffer Pointer register Page Address low Page Address hi
AVR BOOK
; *************************************************************************** ;* ;* SPI MACROS ;* Program Macros .macro cbi .endm
AT_active portb,ATss
.macro sbi .endm
AT_inactive portb,ATss
.macro sbi .endm
sck_hi portb,sck
.macro cbi .endm
sck_lo portb,sck
.macro sbi .endm
mosi_hi portb,mosi
.macro cbi .endm
mosi_lo portb,mosi
;.macro ; subi ;.endm
addi @0, -@1
.macro
set_delay
subi .endm
@0, (@1 << 5)
;NOTE: THIS shift affects INC macro (below)!
.macro subi .endm
inc_delay @0, -(1 << 5)
;bump the delay counter ;shift value here must be same as above!
;subtract the negative of an immediate value
;set up the time delay amount, from 1
to 7
; ****************************************************************************** ;**** CONST ;;;;.EQU .EQU
RPMFACT = 17280 T0Freq=220
;RPM= RPMFACT/IMP*100 ;1.8432MHz = 50Hz
;FLAGS .EQU
Active
;Imo Active bit
= 2
; ****************************************************************************** ;**** VARIABLES .DSEG DS1: .BYTE 1 ;Flagbitek ; 0. = 1 RPM overflow ; 1. = 1 Velocity overflow ; 2. = 1 Immo. Active ; 4. = 1 LED kijelzo frissites kell CNT1: DS3: DS4: DS5: DS6: DS7: DS8: DS9: DS10: DS11: CRC: DSRD: DS12: IOBuff:
.BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE
2 4 2 2 2 2 2 2 2 1 1 10 1 BFSeg
;Interupt COUNTER ;RealTime Clock ;UART Transmit Interrupt rutin cime ;UART Receive Interrupt rutin cime ;UART Transmit Buffer Address ;Fordulatszam binaris ;Sebesseg bin ;Fordulatszamalalo start ;SebessegSZAMLALO start ;TEMP az UART RX-hez ;DS1820 CRC GENERATOR HASZNALJA ;Ide olvassa be a DS Chipet ;Bad CRC szamlalo ;AT45Dxxx IO munkaterulet
;*Variables Offset to Y .EQU .EQU .EQU
FLAGS RTC UTx
= DS1-DS1 = DS3-DS1 = DS4-DS1
;Z+0 ;RealTime Clock ;UART Transmit Interrupt
.EQU
URx
= DS5-DS1
;UART Receive Interrupt rutin
.EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU
TXT = DS6-DS1 RPMB = DS7-DS1 VELB = DS8-DS1 RPMC = DS9-DS1 VELC = DS10-DS1 TEMP = DS11-DS1 CRCoff = CRC-DS1 CNT1L = CNT1-DS1 CNT1H = CNT1-DS1+1 BadCRC = DS12-DS1
rutin cime cime ;UART Transmit Buffer Address ;Fordulatszam binaris ;Sebesseg bin ;Fordulatszamalalo start ;SebessegSZAMLALO start ;TEMP az UART RX-hez ;CRC ;CNT1 ;
; ************************************************************************************** .ESEG KEY1: .DB 0x01 .DB 0x88 .DB 0xDD .DB 0x07 .DB 0x02 .DB 0x00 .DB 0x00 KEY2: .DB 0x01 .DB 0x6D .DB 0xB9 .DB 0x07 .DB 0x02 .DB 0x00 .DB 0x00
; ***************************************************************************** ;**** I N T E R R U P T S ;**** ; ***************************************************************************** .CSEG rjmp RESET ;Reset Handle rjmp EXT_INTO ;IRQ0 Handle rjmp EXT_INT1 ;IRQ1 Handle rjmp TIM_CAPT1 ;Timer1 capture Handle rjmp TIM_COMP1 ;Timer1 compare Handle rjmp TIM_OVF1 ;Timer1 overflow Handle rjmp TIM_OVF0 ;Timer0 overflow Handle rjmp UART_RXC ;UART RX Complete Handle rjmp UART_DRE ;UDR Empty Handle rjmp UART_TXC ;UART TX Complete Handle rjmp ANA_COMP ;Analog Comparator Handle ;*********** ;* RESET ;*********** RESET: CLI
;GLOBAL INTERRUP DIS.
LDI
R16,42
;Sleep enable, Idle mode,INT0, INT1 fall-edge
OUT
MCUCR,R16
LDI OUT
R16,RAMEND SPL,R16
LDI OUT
R16,0 GIMSK,R16
LDI OUT
R16,2 TIMSK,R16
LDI OUT LDI OUT
R16,0 TCCR1A,R16 R16,3 TCCR1B,R16
LDI OUT LDI OUT
R16,T0Freq TCNT0,R16 R16,5 TCCR0,R16
LDI LDI
YL,LOW(DS1) YH,HIGH(DS1)
LDI
R16,0
STD
Y+CRCoff,R16
;CRC=0
STD STD
Y+CNT1L,R16 Y+CNT1H,R16
;CNT1=0
STD STD STD STD STD
Y+RTC+0,R16 Y+RTC+1,R16 Y+RTC+2,R16 Y+RTC+3,R16 Y+BadCRC,R16
LDI
R16,(1< ADIW MOV STD STD CPI BRNE
sens.
LDI STD LDI STD
;STACK A BELSO RAM VEGETOL INDUL LEFELE ;INT0, INT1 Disabled ;7. = 1 EXT INT1 ACTIVE ;6. = 1 EXT INT0 ACTIVE
;7. ;6. ;3. ;1.
= = = =
1 1 1 1
TC1 TC1 TC1 TC0
OWRF EN. * COMP MATCH EN. INP CAPTURE EN. OWRF EN. *
;TC1 Disconected from OC1 pin, PWM Dis. ;Input Capture Dis., f=CLK/64
;50Hz ;f(TC1)=CLK/1024
;BAZIS 'X' +0
;RealTime Clock=1970\01\01
;BadCRC=0
R0 ZL,1 R16,R0 Y+TXT+0,ZL Y+TXT+1,ZH R16,0 MoreTXT
;VAN MEG SZOVEG
R16,low(UReti) Y+UTx+0,R16 R16,high(UReti) Y+UTx+1,R16 CPSE R16,R16
;UART TX INT. ADDR ;AZERT, HOGY
AKOVETKEZO SOR KIMARADJON MoreTXT:
OUT
UDR,R16 POP R0 POP R16 POP ZL OUT SREG,ZL POP ZH POP ZL RETI
;************************************************************************* ;* Text Const ;* Copyr: .DB "(C) 2000, DS1820 Thermometer V1.0 ", 10,13 Ready: .DB "Ready>>",0 Hiba: .DB "Error..",10,13,0
;*********************************************************************** ;*********************************************************************** ;******** M A I N ******** ;******** ******** ;*********************************************************************** Main: LDI R16,10 STD Y+CNT1L,R16 LDI R16,0 STD Y+CNT1H,R16 ;CNT1=25 0.5s
wait:
;SLEEP ldd CPI BREQ CPI BREQ
R16,Y+TEMP R16,'R' WHTROM R16,'r' WHTROM
CPI BREQ CPI BREQ
R16,'T' RDTH R16,'t' RDTH
rjmp
Csokkent
RDTH: rcall sei brcc
cli ReadTh CMDsEND
;ha nincs eszkoz a buszon, akkor
rcall
ComuteT
;R22,R23 a korigalt hom
MOV rcall MOV rcall
R0,R23 TOUART R0,R22 TOUART
kihagy
Wt6:
SBIS
USR,UDRE
;a kovetkezo kimarad, ha a TX
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures RJMP LDI OUT Wt7:
Wt6 R16,' ' UDR,R16 SBIS
reg ures
WHTROM:
RJMP LDI OUT
Wt7 R16,' ' UDR,R17
LDI LDI LDI rjmp
XL,LOW(DSRD) XH,HIGH(DSRD) R19,8 WHTR1
CLI rcall ReadROM SEI brcc CMDsEND
;ide olvasta a DS Chipet ;8 byteot kuldunk ki
;ha nincs eszkoz a buszon, akkor
kihagy
LDI LDI LDI
R19,8 XL,LOW(DSRD) XH,HIGH(DSRD)
MOV rcall
LD R0,R16 TOUART SBIS
WHTR1:
Wt4:
;8 byteot kuldunk ki ;ide olvasta a DS Chipet
R16,X+
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures
CMDsEND:
RJMP LDI OUT dec BRNE
Wt4 R16,' ' UDR,R16 R19 WHTR1
SBIS RJMP LDI OUT
USR,UDRE CMDsEND R16,13 UDR,R16
Wt9:
SBIS
;a kovetkezo kimarad, ha a TX reg ures
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures
Csokkent:
RJMP LDI OUT LDI std
Wt9 R16,10 UDR,R16 R16,0 Y+TEMP,R15
LDD LDD OR BRNE
R24,Y+CNT1L R25,Y+CNT1H R24,R25 wait
;a parancssort kinullazzuk
;Kell-e villogni? LDD R16,Y+FLAGS SBRS R16,Active rjmp Main ;
;a kovetkezo kimarad ha az Active=1
Led villogtato
LEDvil: RJMP CBI RJMP Led_be: RJMP
;CRC-t ellenorzi ; LD ; LDD ; CP ; BREQ
SBIS LEDPORT+1,LED ;kihagy, ha LED=1 Led_be LEDPORT+1,LED ;LED eg Main SBI LEDPORT+1,LED ;LED nem eg Main
R1,X+ R0,Y+CRCOff R1,R0 CRCOK
;olvasott CRC ;szamolt CRC ;GoodCRC
;R0-ban levo byte kiirasa az uartra (HEX) TOUART: LDI Wt1:
LDI R18,7
R17,48
SBIS
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures RJMP MOV SWAP ANDI CPI BRCS ADD Kicsi1: OUT
Wt2:
Wt1 R16,R0 R16 R16,0x0F R16,10 Kicsi1 R16,R18 ADD R16,R17 UDR,R16
SBIS
USR,UDRE
;a kovetkezo kimarad, ha a TX
reg ures RJMP MOV ANDI CPI BRCS ADD Kicsi0: OUT
Wt2 R16,R0 R16,0x0F R16,10 Kicsi0 R16,R18 ADD R16,R17 UDR,R16
ret
.include .include
"div16.asm" "SPI.asm"
;************************************************************************ ;*********************** 1-Wire Bus ************************************* ;************************************************************************ ;-----------------------------------------------------------------------;Kiolvasott DS chip tartalmat osszehasonlitja az EEpromban taroltakkal ; ; R14 a KEY Offsetcime ; ;C=0 Nem jo ;C=1 Kulcs jo DScomp: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet OUT EEAR,R24 ;EEPROM address LDI
R16,7
Cikl2: LD SUB BRNE DEC BRNE SEC RET Rossz: RET
RCALL R1,X+ R1,R0 Rossz R16 Cikl2
;CRC-vel egyutt 8 byte comp. EERead_seq
;EEPrombol akovetkezo elem R0-ba
CLC
;*********************************************************************** ;....................................................................... ;Read DS1820 ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvas egy chippet az Y-ban megadott cimre) ; ;Hasznalja a R18, R17, R16, R3, R2, R0; ;....................................................................... ReadROM: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet LDI R16,0 STD Y+CRCoff,R16 ;CRC=0 ; RCALL TouchReset BRCS RDS1 ;ESZKOZ A BUSZON VAN CLC RET RDS1: MOV LDI RCALL RDS2: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST LDI RDS3: BRNE SEC RET
LDI R16,0x33 ;SEARCH ROM COMMAND R0,R16 R19,7 ;7-SZER OLVASUNK BE TouchByte LDI R16,0xFF ;BEOLVASUNK 8 BITET R0,R16 TouchByte X+,R1 CRCGEN R19 RDS2 R16,0xFF R0,R16 TouchByte X+,R1
;BEOLVASSUK A CRCT
R19,0xFF DEC R19 RDS3 ;CHIP RENDBEN
; **************************************************************************** ;******* TOUCHBYTE ; **************************************************************************** ; ;R0-ban megadott byte-ot kiküldi a touchmemory-nak ;és szimultán beolvas egy byte-ot onnan az R1-be ;Hasznalja a R17, R16 R3, R2 ; TouchByte: LDI R17,8 ;[1] BIT_LOOP: ROR R1 ;[1] RCALL TOUCHBIT ;[3] ROR R0 ;[1] DEC R17 ;[1] BRNE BIT_LOOP ;[1/2] RET ;[1] TOUCHBIT: SBI DS1820_PORT,DS1820_BIT ;[2] LDI R16,3 ;[1] BW0: DEC R16 BRNE BW0 ;[1/2] SBRC R0,0 ;[1/2] CBI DS1820_PORT,DS1820_BIT ;[2] LDI R16,8 ;[1] BW1: DEC R16 BRNE BW1 ;[1/2] IN R2,DS1820_PORT-1 ;[1] BST R2,DS1820_BIT ;[1] BLD R1,7 ;[1] LDI R16,26 ;[1] TCHL: DEC R16 BRNE TCHL ;[1/2] CBI DS1820_PORT,DS1820_BIT ;[2] RET ;[4]
;[1]
;[1]
;[1]
; ******************************************************************************* ;****** T O U C H R E S E T ; ******************************************************************************* ; ;Inicialization procedure "Reset and PreSence Pulses" ; ; Ez a rutin egy Reset jelet general a mikrovrzerlo ketiranyu DS_BIT nevu laban, ;a Touch Memory fele es figyeli a visszajovo PreSence jelet. ;Ha a PreSence jel megerkezett, akkor C=1 kulonben C=0 (nincs eszkoz a buszon) ; ; |-Master Rx "Presence Pulse"-| ; |---Master Reset Tx Pulse---| |----t(RSTH)---------------| ; __ t(RSTL) _____ _____ \\ ___ ; \ / \ / \ ; \_________________________/ \______/ \__ ... ; |-----|-------| ; t(PDH) t(PDL) ; t(R) <-- |-| ; ; 480us<=t(RSTL)< . t(RSTL)+t(R)<960us ; 480us<=t(RSTH)< ; 15us<=t(PDH)<=60us ; 60us<=t(PDL)<=240us ; ; C-flag = 1 DS1990A a buszon van ; = 0 DS1990A nincs a buszon ; ; R16 ; Testelt jol mukodik ; Cyc: TouchReset: SBI DS1820_PORT,DS1820_BIT
;[2]
1-wire = Master LOW , Start
the reset pulse LDI TR0: DEC BRNE
R16,222 NOP R16 TR0
;[1] ;[1] ;[1] ;[1/2] 480us wait with data
low SBI nop CBI CBI nop SBIS RJMP LDI TR1: RJMP DEC BRNE RJMP WL: LDI TR3: RJMP DEC BRNE SHORT: RET WH: SEC RET
DS1820_PORT+1,DS1820_BIT
;[2] 1-wire =Active Hi ;[1] DS1820_PORT,DS1820_BIT ;[2] 1-wire HI (felengedve) DS1820_PORT+1,DS1820_BIT ;[2] 1-wire = Tri-state ;[1] DS1820_PORT-1,DS1820_BIT ;[1/2] Short ;[2] ha egybol Low az rossz R16,21 ;[1] SBIS DS1820_PORT-1,DS1820_BIT ;[1/2] WL ;[2] Exit loop if line low R16 ;[1] TR1 ;[1/2] us wait with data low SHORT ;[2] Line could not go low R16,87 ;[1] SBIC DS1820_PORT-1,DS1820_BIT ;[1/2] WH ;[2] Exit loop if line hi R16 ;[1] TR3 ;[1/2] us wait with data low CLC ;[1] Error ;[4] ;[1] RESET OK. ;[4]
;************************************************************************* ;......................................................................... ; DS1990A CRC GENERATOR ;IN: R1 ;USE: R21,R20, R4,R3, R0, R18 ;......................................................................... CRCGEN: PUSH R1 LDI R20,8 LDI R18,0x18 PUSH R1 CRC_L: EOR ROR MOV BRCC EOR ZERO: STD POP SEC SBRS CLC ROR PUSH DEC BRNE POP POP RET
LDD R3,Y+CRCoff R1,R3 R1 R1,R3 ZERO R1,R18 ROR R1 Y+CRCoff,R1 R1
;CRC
R1,0 R1 R1 R20 CRC_L R1 R1
;*********************************************************************** ;....................................................................... ;Read DS1820 ;c=1 Chip kiolvasva ;c=0 Chip nincs ;(Beolvas egy chippet az Y-ban megadott cimre) ; ;Hasznalja a R18, R17, R16, R3, R2, R0; ;....................................................................... ReadTh: LDI XL,LOW(DSRD) LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet LDI R16,0 STD Y+CRCoff,R16 ;CRC=0 RCALL TouchReset BRCS DSVAN ;ESZKOZ A BUSZON VAN CLC RET DSVAN: MOV RCALL
LDI MOV RCALL
LDI R16,0xCC R0,R16 TouchByte
R16,0x44 R0,R16 TouchByte
;Skip ROM Command
;Convert T Command
nop nop nop nop nop nop nop
DSW1:
SBIS
DS1820_PORT-1,DS1820_BIT
;ha 1 akkor a
kovetkezo kimarad RJMP
DSW1
;varunk mig a komvertalas vege nincs
nop nop LDI STD RCALL BRCS CLC RET
R16,0 Y+CRCoff,R16 TouchReset DS2VAN
;CRC=0
;
;ESZKOZ A BUSZON VAN
DS2VAN: LDI
;Skip ROM Command
MOV RCALL
R16,0xCC R0,R16 TouchByte
LDI MOV RCALL
R16,0xBE R0,R16 TouchByte
;Read Scratchpad command.
nop nop LDI DS2T: MOV RCALL ST RCALL DEC BRNE LDI MOV RCALL ST LDI DS3T: BRNE RCALL SEC RET
R19,8 ;8-SZOR OLVASUNK BE LDI R16,0xFF ;BEOLVASUNK 8 BITET R0,R16 TouchByte X+,R1 CRCGEN R19 DS2T R16,0xFF R0,R16 TouchByte X+,R1
;BEOLVASSUK A CRCT
R19,0xFF DEC R19 DS3T TouchReset ;CHIP RENDBEN
;Tc=8T-2+(8*Count-8*Remainder)/8Count
ComuteT:
http://avr-asm.tripod.com/therm232.html (1 of 2)1/20/2009 9:08:49 PM
LDI LDI
ZL,LOW(DSRD) ZH,HIGH(DSRD)
LDD LDI
dd16uL,Z+7 dd16uH,0
;CPC
LDD LDI
R22,Z+6 R23,0
;CRM
LSL ROL LSL ROL LSL ROL
dd16uL dd16uH dd16uL dd16uH dd16uL dd16uH
;8*CPC
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*CRM
SUB SBC
dd16uL,R22 dd16uH,R23
LDD LDI
dv16uL,Z+7 dv16uH,0
;ide olvassa DS Chipet
;CPC
16 BIT MATH (AVR 202)
MOV OR BRNE LDI LDI RJMP
R0,dv16uL r0,dv16uH DIV1 R16,0 R17,0 LKI1
;0-VAL NEM OSZTUNK
DIV1:
RCALL
div16u
;OSZTAS eredmeny az
LKI1: SBCI SBCI
CLC dres16uL,2 dres16uH,0
LDD LDD CBR
R22,Z+0 R23,Z+1 R22,1
;Temperature
LSL ROL LSL ROL LSL ROL
R22 R23 R22 R23 R22 R23
;8*T
ADD
R22,dres16uL
;R22,R23 a korigalt
ADC ret
R23,dres16uH
R16,R17-ben
;eredmeny-2
;Truncate 0.5C
homerseklet
; *************************************************************************** ;* ;* EERead_seq ;* ;* This subroutine increments the address stored in EEAR and reads the ;* EEPROM into the register variable "EEdrd_s". ;* ;* Number of words :8515 ; 7 + return ;* Number of cycles :8515 ; 11 + return (if EEPROM is ready) ;* Low Registers used :R0 ;* High Registers used: :R24 ;* ; *************************************************************************** EERead_seq: sbic EECR,EEWE ;if EEWE not clear rjmp EERead_seq ; wait more ;The above sequence for EEWE = 0 ;can be skipped if no write is initiated. in R24,EEAR ;get address low 8515 inc R24 ;increment address 8515 out EEAR,R24 ;output address 8515 sbi
EECR,EERE
in ret
R0,EEDR
;set EEPROM Read strobe ;This instruction takes 4 clock cycles since ;it halts the CPU for two clock cycles ;get data
; *************************************************************************** ;* ;* FUNCTION ;* ena_LCD ;* ;* DESCRIPTION ;* Init data & clock lines, then assert /CS for LCD. ;* ;* CODE SIZE: ;* 4 words ;* ; *************************************************************************** ena_LCD: sck_lo mosi_lo Select_LCD ret
;(should already be there...)
;* LCDlo, LCDHi - kikuldese RW_LCD: mov spi_lo,LCDHi rcall ena_LCD rcall rw_spi mov spi_lo,LCDLo rcall rw_spi ret ;**** A P P L I C A T I O N
;Mov Command byte ;activate /CS ;send Command byte ;Mov Command byte ;send Command byte N O T E
A V R 2 0 0
************************ ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
Title: Version: Last updated: Target:
Multiply and Divide Routines 1.1 97.07.04 AT90Sxxxx (All AVR Devices)
Support E-mail:
[email protected]
DESCRIPTION This Application Note lists subroutines for the following Divide applications. Routines are straight-line implementations optimized for speed: 16 / 16 = 16 + 16 bit unsigned
; ***************************************************************************
; *************************************************************************** ;* ;* "div16u" - 16/16 Bit Unsigned Division ;* ;* This subroutine divides the two 16-bit numbers ;* "dd16uH:dd16uL" (dividend) and "dv16uH:dv16uL" (divisor). ;* The result is placed in "dres16uH:dres16uL" and the remainder in ;* "drem16uH:drem16uL". ;* ;* Number of words :196 + return ;* Number of cycles :148/173/196 (Min/Avg/Max) ;* Low registers used :2 (drem16uL,drem16uH) ;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH,dv16uL,dv16uH) ;* ; ***************************************************************************
;***** Code div16u: sub
clr drem16uL ;clear remainder Low byte drem16uH,drem16uH;clear remainder High byte and carry
rol rol rol rol sub sbc brcc add adc clc rjmp d16u_1:
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_1 drem16uL,dv16uL drem16uH,dv16uH
d16u_2: rol rol rol sub sbc brcc add adc clc rjmp d16u_3:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_3 drem16uL,dv16uL drem16uH,dv16uH
d16u_4: rol rol rol sub sbc brcc add adc clc rjmp d16u_5:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_5 drem16uL,dv16uL drem16uH,dv16uH
d16u_6: rol rol rol sub sbc brcc add adc clc rjmp d16u_7:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_7 drem16uL,dv16uL drem16uH,dv16uH
d16u_8: rol rol rol sub sbc brcc add adc clc rjmp d16u_9:
rol dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_9 drem16uL,dv16uL drem16uH,dv16uH
d16u_10:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_11:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_11 drem16uL,dv16uL drem16uH,dv16uH
d16u_12:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_13:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_13 drem16uL,dv16uL drem16uH,dv16uH
d16u_14:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_15:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_15 drem16uL,dv16uL drem16uH,dv16uH
d16u_16:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_17:
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_17 drem16uL,dv16uL drem16uH,dv16uH
d16u_18:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_19:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_19 drem16uL,dv16uL drem16uH,dv16uH
d16u_20:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_21:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_21 drem16uL,dv16uL drem16uH,dv16uH
d16u_22:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_23:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_23 drem16uL,dv16uL drem16uH,dv16uH
d16u_24:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_25:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_25 drem16uL,dv16uL drem16uH,dv16uH
d16u_26:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_27:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_27 drem16uL,dv16uL drem16uH,dv16uH
d16u_28:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_29:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_29 drem16uL,dv16uL drem16uH,dv16uH
d16u_30:rol rol rol rol sub sbc brcc add adc clc rjmp d16u_31:sec
dd16uL dd16uH drem16uL drem16uH drem16uL,dv16uL drem16uH,dv16uH d16u_31 drem16uL,dv16uL drem16uH,dv16uH
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_2 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_4 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_6 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_8 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_10 sec
result ;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_12
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_14
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_16
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into
d16u_18 sec
result
;remainder = remainder - divisor ; ;if result negative ; restore remainder
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_22
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_24
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_26
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_28
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_30
d16u_32:rol dd16uL rol dd16uH ret
;shift dividend into remainder
; clear carry to be shifted into result ;else ; set carry to be shifted into result
d16u_20
d16u_32
;shift left dividend
;shift left dividend ;shift dividend into remainder ;remainder = remainder - divisor ; ;if result negative ; restore remainder ; clear carry to be shifted into result ;else ; set carry to be shifted into result ;shift left dividend
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an onchip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/therm232.html (2 of 2)1/20/2009 9:08:49 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
INFARED REMOTE DECODER (AVR 410) HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16
; *************************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR410 ;* File Name :"rc5.asm" ;* Title :RC5 IR Remote Control Decoder ;* Date :97.08.15 ;* Version :1.0 ;* Target MCU :AT90S1200 ;* ;* DESCRIPTION ;* This Application note describes how to decode the frequently used ;* RC5 IR remote control protocol. ;* ;* The timing is adapted for 4 MHz crystal ;* ; *************************************************************************** .include "1200def.inc" .device AT90S1200
MATH 202 .equ .equ
INPUT SYS_ADDR
FFT7
.def .def .def .def
S inttemp ref1 ref2
=R0 =R1 =R2 =R3
COPY 102
.def
temp
=R16
.def .def
timerL timerH
=R17 =R16
.def .def
system =R19 command =R20
.def
bitcnt
=R21
rjmp
reset
MATH 202 DEC ASCII
=2 =0
;PD2 ;The system address
INT ASCII HX2ASC AVG8 222
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM .cseg .org 0
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
; ******************************************************************** ;* "TIM0_OVF" - Timer/counter overflow interrupt handler ;* ;* The overflow interrupt increments the "timerL" and "timerH" ;* every 64us and 16,384us. ;* ;* Number of words: 7 ;* Number of cycles: 6 + reti ;* Low registers used: 1 ;* High registers used: 3 ;* Pointers used: 0 ; ******************************************************************** .org OVF0addr TIM0_OVF: in S,sreg inc timerL ;Updated every 64us inc inttemp brne TIM0_OVF_exit
DALLAS-1W
inc
timerH
DALLAS CRC TIM0_OVF_exit: reti
ETHNET 8019
out
sreg,S
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; ******************************************************************** ;* Example program ;* ;* Initializes timer, ports and interrupts. ;* ;* Calls "detect" in an endless loop and puts the result out on ;* port B. ;* ;* Number of words: 16 ;* Low registers used: 0 ;* High registers used: 3 ;* Pointers used: 0 ; ********************************************************************
PS2 EMU BOOT MG8
reset:
;ldi
temp,low(RAMEND)
;
Initialize stackpointer ;out ;ldi
SPL,temp temp,high(RAMEND)
;out
SPH,temp
ldi
temp,1
out
TCCR0,temp
PWM 6CH
ldi brge
temp,1< 3/4 bit time fault ; exit
PWM 10K
sbic
PIND,INPUT
rjmp
start3
clr ldi clr clr
timerL bitcnt,12 command system
BOOT DR8 ALM CLK
out since 1200 does not hae SRAM
CLOCK 8564 90 DAYS DELAYS
;Timer/Counter 0
clocked at CK
CALL ID DTMF 314
ENCODE
; Commented
;Wait for falling
edge start bit 2
STH-11 ATMEL CORP AVR BUTTERFLY
;Receive 12 bits
AVR BOOK sample:
cp
timerL,ref1
;Sample
INPUT at 1/4 bit time brlo
sample
sbic rjmp
PIND,INPUT bit_is_a_1
bit_is_a_0: clc rol rol
;Jump if line high
;Store a '0' command system
bit_is_a_0a:
cp
;Synchronize timing timerL,ref2 ;If no edge
within 3/4 bit time brge sbis
fault PIND,INPUT
; exit ;Wait for rising
rjmp
bit_is_a_0a
;in the middle of
clr rjmp
timerL nextbit
edge the bit
bit_is_a_1: sec rol rol
;Store a '1' command system
bit_is_a_1a:
cp
;Synchronize timing timerL,ref2 ;If no edge
within 3/4 bit time brge sbic
fault PIND,INPUT
; exit ;Wait for falling
rjmp
bit_is_a_1a
;in the middle of
clr
timerL
dec brne
bitcnt sample
edge the bit
nextbit:
;If bitcnt > 0 ; get next bit
;All bits sucessfully received! mov temp,command
;Place system bits
in "system" rol rol rol rol
temp system temp system
bst bld
system,5 command,6
;Move toggle bit ;to "command" ;Clear remaining
bits andi andi
command,0b01111111 system,0x1F
ret fault:
ser
command
;Both
"command" and "system" ser
system
;0xFF indicates
failure ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/ird410.html (1 of 2)1/20/2009 9:09:24 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/ird410.html (2 of 2)1/20/2009 9:09:24 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LCD DRIVER FOR HD44xx HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; *************************************************************************** ; ; File Name :'lcd4.asm" ; Title :HD44xx kompatibilis LCD Driver (I/O Port) ; Date :2003.10.28. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; http://home.iae.nl/users/pouweha/lcd/lcd.shtml ; ; Support 2x16 char LCD ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2003.10.28 VFX Creation ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* SYSCLK: f=16.000 MHz (T= 62.5 ns) ;* ; *************************************************************************** ; ; ; ************************************************************************** ;* Hardware Def. ; ; ***************************************************************************
UART 305 .equ .equ
LCDRS_PORT=PORTD LCDRS_DIR=DDRD
USB 232
.equ
LCDRS=0
AVR ISP
.equ .equ
LCDRW_PORT=PORTD LCDRW_DIR=DDRD
.equ
LCDRW=1
.equ .equ
LCDEN_PORT=PORTD LCDEN_DIR=DDRD
.equ
LCDEN=4
.equ
LCDDAT_PORT=PORTF
.equ .equ .equ
LCDDAT_DIR=DDRF LCDDAT_PIN=PINF LCDDAT_Mask=0b00001111
UART 128 UART BUFF
1=data 0=command
ISP 2313 ISP 1200
;LCD Register Select ;Register Select
;LCD Read/Write ;0=write to
display, 1= read from display
AVR SPI I2C 300 I2C 302
clocked on falling edge
I2C TWI26 I2C/TWI 128 I2C/TWI AT8
;LCD Enable ;Enable - data
;LCD Data PortF
[3..0]
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400
; *************************************************************************** ;**** VARIABLES .DSEG
ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313
; *************************************************************************** .ESEG
LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;**** CODE SEG ; *************************************************************************** .CSEG
PS2 EMU BOOT MG8
;***************************************************** ;** Wait1ms ;** ;** In: R16 - 16*1ms varakozas ;** ;** Out: ;** ;** ;** Alt R16 ;** ;** Description: wating for R16 * 1 ms ;* Wait1ms: ldi XL,low(SYSCLK/(5*1000)) ldi XH,high(SYSCLK/(5*1000)) Waitx1: sbiw XL,1 ;[2] \ nop ;[1] - 5 cycles in
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP
loop brne dec brne ret
AVR BUTTERFLY AVR BOOK
Waitx1 R16 Wait1ms
;[2] /
;***************************************************** ;** LCD_pulseE ;** ;** In: ;** ;** Out: R0 - Data on LCDDat pin ;** ;** ;** Alt ;** ;** Description: Generate ENABLE signal to LCD ;* LCD_pulseE: sbi LCDEN_PORT,LCDEN ;Enable high nop ;Wait 500ns @16MHz nop nop nop nop nop nop nop in cbi
R0,LCDDAT_PIN LCDEN_PORT,LCDEN
;Enable
low, latch data ret
;***************************************************** ;** LCD_Init ;** ;** In: ;** ;** Out: ;** ;** ;** Alt: ;** ;** Description: Initialize LCD in 4 bit mode ;* LCD_Init: sbi LCDEN_DIR,LCDEN ;LCD I/O Disabled cbi
LCDEN_PORT,LCDEN
sbi
LCDRS_DIR,LCDRS
cbi
LCDRS_PORT,LCDRS
sbi
LCDRW_DIR,LCDRW
cbi
LCDRW_PORT,LCDRW
ldi
R16,LCDDAT_Mask
;LCD Data
sts ldi sts
LCDDAT_DIR,R16 R16,0 LCDDAT_PORT,R16
;All zeros
ldi
R16,15
;Wait at
rcall
Wait1ms
;powerup
;Sel. LCD
Command Register
;LCD Write
mode
lines outputs
least 15msec after before writing to display ;tuti ami tuti legyen 250ms
; Put the LCD in 8-bit mode.
Even though
we want the display to ; operate in 4-bit mode, the only way to guarantee that our commands ; are aligned properly is to initialize in 8-bit.
(The user might have ; hit reset between nibbles of a dual 4-bit
cycle.) lds andi ori
R16,LCDDAT_PORT R16,255-LCDDAT_PORT R16,0b00000011
sts nop nop cbi
LCDDAT_PORT,R16
LCDRS_PORT,LCDRS
;Set to
cbi rcall ldi rcall
LCDRW_PORT,LCDRW LCD_pulseE R16,15 Wait1ms
;read ;1
cbi
LCDRS_PORT,LCDRS
;Set to
cbi rcall ldi rcall
LCDRW_PORT,LCDRW LCD_pulseE R16,5 Wait1ms
;read ;2
cbi
LCDRS_PORT,LCDRS
;Set to
cbi rcall ldi rcall
LCDRW_PORT,LCDRW LCD_pulseE R16,5 Wait1ms
;read ;3
;3x
probalkozunk 8 bit mode-ba rakni
Command Reg.
;wait 5ms
Command Reg.
;wait 5ms
Command Reg.
;wait 5ms
; Now it's safe to go into 4-bit mode. lds andi ori
R16,LCDDAT_PORT R16,255-LCDDAT_PORT R16,0b00000010
;4bit bus
sts rcall ldi rcall
LCDDAT_PORT,R16 LCD_pulseE R16,5 Wait1ms
;wait 5ms
mode
; *** Send the 'FUNCTION SET' command ; +------ Data: 0 = 4-bit; 1 = 8-bit ; ;
|+----- Lines: 0 = 1; 1 = 2 ||+---- Font: 0 = 5x8; 1
= 5x11 ldi rcall
R16,0b00101000 LCD_SendCmd
; *** Send the 'CURSOR/DISPLAY SHIFT' command ;
+----- S/C:
0 = cursor;
;
|+---- R/L:
0 = left; 1
1 = display = right ldi rcall
R16,0b00010100 LCD_SendCmd
; *** Send the 'ENTRY MODE' command ; +--- Direction: 0 = left; 1 = right ;
|+-- Shift Dislay: 0 =
off; 1 = on ldi rcall
R16,0b00000110 LCD_SendCmd
; *** Send the 'DISPLAY ON/OFF' command ; +---- Display: 0 = off; 1 = on ;
|+--- Cursor: 0 = off; 1
;
||+-- Blink: 0 = off; 1
= on = on ldi rcall
R16,0b00001100 LCD_SendCmd
rcall ret
LCD_Clear
;***************************************************** ;** LCD_Clear ;** ;** In: ;** ;** Out: ;** ;** ;** Alt: ;** ;** Description: ;** Clears the display and sends the cursor home. ; LCD_Clear: ldi R16,0b00000001 ;Clear LCD rcall LCD_SendCmd ldi R16,0b00000010 ;Send the cursor home rcall ret
LCD_SendCmd
;***************************************************** ;** LCD_WaitBusy ;** ;** In: ;** ;** Out: ;** ;** ;** Alt: R0, R16 ;** ;** Description: ;** Waits for the busy flag to go low. Since we're in 4-bit mode, ;** the register has to be read twice (for a total of 8 bits). ;* LCD_WaitBusy: push
R16
lds andi
R16,LCDDAT_DIR R16,255-LCDDAT_Mask
sts
LCDDAT_DIR,R16
lds ori sts rjmp
R16,LCDDAT_PORT R16,LCDDAT_Mask LCDDAT_PORT,R16 LCDWait1
ldi
R16,2
nop dec brne
R16 LCDWait01
cbi
LCDRS_PORT,LCDRS
;Set to
sbi rcall
LCDRW_PORT,LCDRW LCD_pulseE
;read ;Busy Flag
mov rcall
R16,R0 LCD_pulseE
;lower
sbrc
R16,3
;Check busy
;LCD data
bits going to input
;pull-up
LCDWait0: ;Wait min.
~1us LCDWait01:
LCDWait1: Command Reg.
read bit 7.
nibble must read flag rjmp
LCDWait0
lds
R16,LCDDAT_DIR
ori sts lds andi sts pop ret
R16,LCDDAT_Mask LCDDAT_DIR,R16 R16,LCDDAT_PORT R16,255-LCDDAT_Mask LCDDAT_PORT,R16 R16
;LCD Data
lines outputs
;All zero
;***************************************************** ;** LCD_SendCmd ;** ;** In: R16 - Command byte ;** ;** Out: ;** ;** ;** Alt: R0, R1, R16, R17 ;** ;** Description: ;** Routine to write a command to the instruction register. ; LCD_SendCmd: rcall mov swap andi
LCD_WaitBusy R1,R16 R16 R16,LCDDAT_Mask
;send upper
lds andi or sts cbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
mov andi
R16,R1 R16,LCDDAT_Mask
;send lower
lds andi or sts cbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
nibble first
Command Reg.
upper nibble
nibble
Command Reg.
lower nibble ret
;***************************************************** ;** LCD_SendChar ;** ;** In: R16 - character code ;** ;** Out: ;** ;** ;** Alt: R0,R1, R16, R17 ;** ;** Description: ;** Routine to write a character to the data register. ; LCD_SendChar: rcall LCD_WaitBusy mov R1,R16 swap R16 andi R16,LCDDAT_Mask ;send upper nibble first lds andi or sts sbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
mov andi
R16,R1 R16,LCDDAT_Mask
;send lower
lds andi or sts sbi
R17,LCDDAT_PORT R17,255-LCDDAT_Mask R17,R16 LCDDAT_PORT,R17 LCDRS_PORT,LCDRS
;Set to
cbi rcall
LCDRW_PORT,LCDRW LCD_PulseE
;Write ;Latch
data Reg.
upper nibble
nibble
Data Reg.
lower nibble ret
;***************************************************** ;** LCD_Goto ;** ;** In: R16 - position ;** 0x00 - 1.row, 1.col ;** 0x40 - 1.row, 2.col ;** ;** Out: ;** ;** ;** Alt: R0, R1, R16, R17 ;** ;** Description: ;** ; LCD_Goto: ori R16,0b10000000 ;Set address Command rcall ret
LCD_SendCmd
;***************************************************** ;** LCD_PrnFLASHStr ;** ;** In: Z+RAMP - start address of string ;** ;** Out: ;** ;** ;** Alt: R0, R1, R16, R17 ;** ;** Description: ;** Print a null terminated string to LCD ; LCD_PrnFLASHStr: elpm R16,Z+ tst R16 breq LCD_PrnFLSH0 rcall LCD_SendChar rjmp LCD_PrnFLASHStr LCD_PrnFLSH0: ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) http://avr-asm.tripod.com/lcdhd44.html (1 of 2)1/20/2009 9:10:19 PM
16 BIT MATH (AVR 202)
Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/lcdhd44.html (2 of 2)1/20/2009 9:10:19 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LCD DRIVER FOR HD44780 AND 2313 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
; *************************************************************** ;Programm LCD.ASM ;Das Programm demonstriert, wie man eine LCD-Anzeige mit ;16 Zeichen x 2 Zeilen an einen AT90S2313 anschliesst. ;Es wird vorausgesetzt, dass die Anzeige einen HD44780 oder ;kompatiblen Controller verwendet. ;AT90S2313 mit 4 MHz Takt ; ***************************************************************
MATH 202 .device AT90S2313 .include "2313def.inc" ;muss im selben ;Verzeichnis stehen
MATH 32X MATH YX DIV16 XX DIV 24 24
;Definition der Steuerleitungen .equ E = PD0 ;E an Pin PD0 .equ RW = PD1 ;RW an Pin PD1 .equ RS = PD2 ;RS an Pin PD2 ;.equ LCD_cntr = PORTD ;PORTD ist Kontroll-Port ;.equ LCD_data = PORTB ;PORTB ist Daten-Port .equ BF = PB7 ;Busy flag
DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII
;LCD .equ .equ .equ .equ .equ
INT ASCII HX2ASC AVG8 222 FFT7
Befehle clear_LCD = 0b00000001 ;loesche Anzeige home_LCD = 0b00000010 ;return home set_LCD = 0b00111000 ;8 bits,2 Zeilen,5x7dots LCD_on = 0b00001110 ;schalte LCD ein entry_mode = 0b00000110 ;setze Cursor
COPY 102 ;Variablendefinition
LPM 108 EPROM 100
.def .def .def .def
SER EPROM DFLASH AT45
zeichen = r0 ;Zeichen aus der Tabelle buffer = r16 ;RX/TX Daten von/zu LCD counter = r17 ;Zaehler fuer den Text temp = r18
FLASH CARD VFX SMIL
.CSEG .ORG 0x00 ; Programm beginnt bei 0 rjmp main ; Starte Hauptprogramm
VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128
; ************************************************************** ; Subroutine init ; Initialisiere PORTD ; **************************************************************
UART BUFF
init: ldi temp,0b11111111 ;PORTD ist Ausgang out DDRD,temp cbi PORTD,E ;E initialisieren cbi PORTD,RS cbi PORTD,RW ret
USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
; *************************************************************** ; Subroutine busy_flag ; Diese Routine testet, ob die LCD-Anzeige bereit ist, einen ; neuen Befehl oder weitere Daten zu empfangen. ; ***************************************************************
DALLAS CRC busy_flag: ldi temp,0b00000000 ;PORTB ist Eingang out DDRB,temp cbi PORTD,RS ;Befehl wird gesendet sbi PORTD,RW ;setze LCD in Lesemodus sbi PORTD,E ;spreche LCD an nop nop sbic PINB,BF ;LCD bereit? rjmp busy_flag ;nein, wiederhole cbi PORTD,E ;disable LCD ret ;LCD bereit
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
; *************************************************************** ; Subroutine write_data ; Diese Routine sendet Daten zur LCD-Anzeige. ; Die Daten muessen im Register buffer uebergeben werden. ; ***************************************************************
KBD PC/128 write_data: rcall busy_flag ;LCD bereit? ldi temp,0b11111111 ;PORTB ist Ausgang out DDRB,temp sbi PORTD,RS ;Daten werden gesendet cbi PORTD,RW ;LCD in Schreibmodus sbi PORTD,E ;spreche LCD an out PORTB,buffer ;sende Daten cbi PORTD,E ;disable LCD ret
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11
; *************************************************************** ; Subroutine write_instr ; Diese Routine sendet Befehle zur LCD-Anzeige. ; Der Befehl muss im Register buffer uebergeben werden. ; *************************************************************** write_instr: rcall busy_flag ;LCD bereit? ldi temp,0b11111111 ;RB ist Ausgang out DDRB,temp cbi PORTD,RS ;Befehl wird gesendet cbi PORTD,RW ;LCD in Schreibmodus sbi PORTD,E ;spreche LCD an out PORTB,buffer ;sende Befehl cbi PORTD,E ;disable LCD ret
ATMEL CORP AVR BUTTERFLY AVR BOOK
; *************************************************************** ; Hauptprogramm ; Schreibt "AT90S2313" in die erste Zeile und "LCDRoutine" ; in die zweite Zeile des LCDs. ; *************************************************************** main: ldi temp,RAMEND ; setze Stack-Pointer out SPL,temp ; an das SRAM-Ende rcall init ; PORTD initialisieren ldi buffer,set_LCD ;setze LCD Funktion rcall write_instr ldi buffer,LCD_on ;schalte LCD ein rcall write_instr ldi buffer,clear_LCD ;loesche Anzeige rcall write_instr ldi buffer,entry_mode ;Eingabemodus rcall write_instr
;Holt den Text 'AT90S2313' aus der Tabelle und schreibt diesen in ;die erste Zeile der Anzeige ldi counter,9 ;Zeichenzaehler ldi ZL,LOW(Tabelle1*2) ;Low-Zeiger auf Tabellenanfang ldi ZH,HIGH(Tabelle1*2) ;High-Zeiger auf Tabellenanfang loop_msg1: lpm ;hole Zeichen aus Tabelle mov buffer,zeichen ;Zeichen uebergeben rcall write_data ;schreibe Zeichen in LCD adiw ZL+1 ;16-Bit Zeiger erhoehen dec counter ;alle Zeichen gesendet? brne loop_msg1 ;Nein! Sende naechstes Zeichen
;Holt den Text 'LCD-Routine' aus der Tabelle und schreibt diesen ;in die zweite Zeile der Anzeige ldi buffer,0b11000000 ;LCD-Startadresse 2.Zeile rcall write_instr ;sende Befehl ldi counter,11 ;Zeichenzaehler ldi ZL,LOW(Tabelle2*2) ;Low-Zeiger auf Tabellenanfang ldi ZH,HIGH(Tabelle2*2) ;High-Zeiger auf Tabellenanfang loop_msg2: lpm ;hole Zeichen aus Tabelle mov buffer,zeichen ;Zeichen uebergeben rcall write_data ;schreibe Zeichen in LCD adiw ZL+1 ;16-Bit Zeiger erhoehen no_carry2: dec counter ;alle Zeichen gesendet? brne loop_msg2 ;Nein! Sende naechstes Zeichen
;Endlosschleife. AVR zuruecksetzen, um Programm erneut zu starten loop: rjmp loop
;Tabelle 1 mit dem Text "AT90S2313", der in die 1.Zeile geschrieben ;werden soll Tabelle1: .DB "AT90S2313"
;Tabelle 2 mit dem Text "LCD-Routine", der in die 2. Zeile geschrieben ;werden soll Tabelle2: .DB "LCD-Routine"
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/lcd2313.html (1 of 2)1/20/2009 9:10:53 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/lcd2313.html (2 of 2)1/20/2009 9:10:53 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
LCD DRIVER II FOR HD44780 AND 2313 HOME RETRO_DAN ASM FORUM
The attached code shows how to connect, initialise and drive a 44780-based LCD in 4-bit mode.
ASM MATH TUTORIAL #1
The 2 additional pins are probably reserved for a backlight option - they were on my display from Dontronics.
TUTORIAL #2 ;----------------------------------------------------------------; ; Name: LCDMain.asm ; Title: Main routine for driving Hitach LCD display ; Version: 1.0 ; Last updated: 2001.06.04 ; Target: AT90S2313 ; ;----------------------------------------------------------------; ; DESCRIPTION ; ; Driver for Hitachi HD44780-based LCD display ; ; Display is wired to Port B. Each individual pin on the display ; is wired as follows: ; ; Pin 1 - Vss GND Supply ground ; Pin 2 - Vdd VTG Supply +ve ; Pin 3 - Vee GND Contrast adjust = maximum ; Pin 4 - RS PB4 Command/data ; Pin 5 - R/W PB5 Read/write ; Pin 6 - EN PB6 Enable ; Pin 7 - DB0 GND Data bit 0 = 0 ; Pin 8 - DB1 GND Data bit 1 = 0 ; Pin 9 - DB2 GND Data bit 2 = 0 ; Pin 10- DB3 VTG Data bit 3 = 1 to indicate 2-line display at
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7
startup
COPY 102
; Pin 11- DB4 PB0 Data bit 4 = PortB:0 ; Pin 12- DB5 PB1 Data bit 5 = PortB:1 ; Pin 13- DB6 PB2 Data bit 6 = PortB:2 ; Pin 14- DB7 PB3 Data bit 7 = PortB:3 ; Pin 15- (if present) No connection ; Pin 16- (if present) No connection ; ;-----------------------------------------------------------------
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
.nolist .include "2313def.inc" .list
VFX MEM SORT 220 CRC 236
;----------------------------------------------------------------; ; General purpose registers
XMODEM REC UART 304 UART 305
.def rRETURN =r0 ; return value from functions
UART 128
.def rZERO =r1
UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300
.def .def .def .def
rSCRATCH =r7 rSCRATCH2 =r8 rSCRATCH3 =r9 rSCRATCH4 =r10
.def .def .def .def
rISCRATCH =r11 ; for use in interrupt routines rISCRATCH2 =r12 ; ditto rISCRATCH3 =r13 ; ditto rISCRATCH4 =r14 ; ditto
I2C 302 .def rISREGSAVE =r15 ; sreg saved here in interrupts
I2C TWI26 I2C/TWI 128
.def rTEMP =r16 .def rTEMP2 =r17
I2C/TWI AT8 DALLAS-1W
.def rITICK =r18 ; Decreasing tick, used for delays .def rITEMP =r19
DALLAS CRC ETHNET 8019
.def rPARAM1 =r20 .def rPARAM2 =r21
TEA ADC 128
.def rLOOPI =r22 ; loop counters .def rLOOPJ =r23
ADC 10B ADC 400
;----------------------------------------------------------------; ; Equates
ADC 401 THERM 232 IRD 410
;----------------------------------------------------------------; ; IO Port Bits
LCD HD44 LCD 2313
.equ .equ .equ .equ
LCD44 2313 KBD 240 MUX 242 KBD PS2
mDATA =0x0F bRS =4 bRW =5 bEN =6
;----------------------------------------------------------------; ; Timings ; ; We need a multiple of 100Hz for the clock tick, so for 4MHz ; this equates to 40,000 clock cycles, and for a 3.6864MHz clock, ; this is 36,864 cycles. Given the prescaler values available ; on counter/timer 0, we get the following: ; ; Divider Counts 4MHz Counts 3.7MHz In range? ; Clk/8 5000 4608 No (greater than 255) ; Clk/64 625 576 No (greater than 255) ; Clk/64 125 for 500Hz 144 for 400Hz Yes ; ; The actual values loaded into the registers are these values ; subtracted from 256, since we are counting up, and the clock ; interrupt happens when the clock register overflows to 256.
KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K
.equ TIMERSCALE =$03 ; Clk/64
ENCODE STH-11
; Timer value for 3.6864 MHz clock .equ TIMERVALUE = (256-144) .equ TICKVALUE = 4 ; 4 x 400Hz ticks = 100Hz clock
ATMEL CORP AVR BUTTERFLY
; Timer value for 4 MHz clock ; .equ TIMERVALUE = (256-125) ; .equ TICKVALUE = 5 ; 5 x 500Hz ticks = 100Hz clock
AVR BOOK
;----------------------------------------------------------------; ; Variables .dseg tickcount: .byte 1 ; clock count to 4 or 5 for centiseconds centi: .byte 1 ; centisecond count second: .byte 1 ; second count minute: .byte 1 ; minute hour: .byte 1 ; hour day: .byte 1 ; day ;----------------------------------------------------------------; ; Interrupt service vectors .cseg .org 0 rjmp Reset ; Reset vector .org OVF0addr rjmp Timer0 ; Timer tick
;----------------------------------------------------------------; ; Start of actual code. ; ;----------------------------------------------------------------; ; Timer 0 overflow - decreases tick count in tickcount until it ; reaches 0, then ripples the count along to the next biggest ; counter, all the way up to the "days" count. Timer0: in rISREGSAVE,SREG ; store status register ldi rITEMP,TIMERVALUE ; reset counter out TCNT0,rITEMP ; to start counting again mov rISCRATCH,YL ; store Y register mov rISCRATCH2,YH ; since we will be using it dec rITICK ; decrease register tick count ldi YL,low(tickcount) ; Y points to tick count clr YH ld rITEMP,Y ; get tick count inc rITEMP ; increment it cpi rITEMP,TICKVALUE ; is it the target value yet? brne Timer0_Done ; no... exit immediately clr rITEMP ; yes - clear it and store it again st Y+,rITEMP ; increment Y to point to centiseconds ; ; We get through to here once every 4 or 5 timer ticks, in ; other words, 100 times every second. ; ld rITEMP,Y ; load centiseconds inc rITEMP ; increment cpi rITEMP,100 ; and check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to seconds ld rITEMP,Y ; load seconds inc rITEMP ; increment cpi rITEMP,60 ; check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to minutes ld rITEMP,Y ; load minutes inc rITEMP ; increment cpi rITEMP,60 ; check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to hours ld rITEMP,Y ; load hours inc rITEMP ; increment cpi rITEMP,24 ; check for overflow brne Timer0_Done ; no... exit immediately clr rITEMP ; else reset to 0 st Y+,rITEMP ; store, and increment Y to point to days ld rITEMP,Y ; load days inc rITEMP ; and increment ; ; However we get here, the most recently incremented value is in rITEMP, ; and Y points to where we got it from. ; Timer0_Done: st Y,rITEMP ; store valid value back again mov YL,rISCRATCH ; restore saved Y pointer mov YH,rISCRATCH2 out SREG,rISREGSAVE ; restore status register reti ; and return from interrupt, done. ;----------------------------------------------------------------; ; WaitTick ; Waits for between rPARAM1 and rPARAM1+1 timer ticks, depending ; on exactly when the next tick is about to happen. Each tick takes ; 20ms on a 4MHz clock, or 25ms on a 3.6864MHz clock. This is enough ; to act as a timed delay for those commands which take more than ; the 40us "standard" delay. WaitTick: inc rPARAM1 mov rITICK,rPARAM1 WaitTick_Loop: and rITICK,rITICK brne WaitTick_Loop ret
;----------------------------------------------------------------; ; Reset vector - generic system. Reset: ldi rTEMP,RAMEND-1 ; Set stack to end of RAM out SPL,rTEMP ; Get the timer going ldi rTEMP,(1< out TIMSK,rTEMP ldi rTEMP,TIMERVALUE ; timer value out TCNT0,rTEMP ldi rTEMP,TIMERSCALE ; clock prescaler for Timer 0 out TCCR0,rTEMP ; ; And allow timer interrupts ; sei ; Set port B to all output, all 0. ldi rTEMP,$00 out PORTB,rTEMP ldi rTEMP,$FF out DDRB,rTEMP ; ; Now initialize the display ; rcall InitDisplay ; ; And reset the displayed time to 00 00:00:00.00 ; clr sts sts sts sts sts sts
rTEMP tickcount,rTEMP centi,rTEMP second,rTEMP minute,rTEMP hour,rTEMP day, rTEMP
ldi rPARAM1,0x00 rcall LCDGoto ; go to display position 0 ldi ZL,low(String*2) ldi ZH,high(String*2) rcall LCDString ; and send string Loop: ldi rPARAM1,0x40 rcall LCDGoto ; go to display position 0x40 (2nd line) lds rPARAM1,day ; get the day rcall LCDNumber ; output as a 2-digit number ldi rPARAM1,' ' ; followed by a space, rcall WriteData lds rPARAM1,hour ; then the hour rcall LCDNumber ; as a 2 digit number ldi rPARAM1,':' ; followed by a colon rcall WriteData lds rPARAM1,minute ; then the minute rcall LCDNumber ; as a 2 digit number ldi rPARAM1,':' ; followed by a colon rcall WriteData lds rPARAM1,second ; then the second rcall LCDNumber ; as a 2 digit number ldi rPARAM1,'.' ; followed by a decimal point rcall WriteData lds rPARAM1,centi ; and finally the 1/100ths of a second rcall LCDNumber ; yes, as a 2 digit number. lds rTEMP,centi ; get the centiseconds "then" Wait: lds rTEMP2,centi ; get the centiseconds "now" cp rTEMP,rTEMP2 ; same? breq Wait ; yes... go round again and wait till it changes rjmp Loop ; then display all over again, for ever
;----------------------------------------------------------------; ; InitDisplay ; Initialize display as shown in data sheet. InitDisplay: ; Initial power-up delay ; Wait for 15ms or more (100-125ms in fact) ldi rPARAM1,5 rcall WaitTick ; Send 8-bit mode command ldi rTEMP2,0x03 ; 8 bit mode indicator rcall Strobe ; and strobe it out ; Wait again ldi rPARAM1,1 ; min 20ms delay (4ms + leeway) rcall WaitTick ; until ready to receive ; Send 8-bit mode command again ldi rTEMP2,0x03 ; 8 bit mode indicator rcall Strobe ; and strobe it out ; Wait again ldi rPARAM1,100 ; 100us rcall WaitMicro ; until ready to receive ; Now 4-bit mode command to actually place us in 4-bit mode ; as originally required. ldi rTEMP2,0x02 ; 4 bit mode indicator rcall Strobe ; and strobe it out ; Wait ldi rPARAM1,100 ; 100us rcall WaitMicro ; until ready to receive ; ; We can now use the normal functions for writing data, ; which are designed to work with 4-bit mode data timings ; ; Function set ldi rPARAM1,0x28 ; 4 bit, dual line rcall WriteInstruction ; Display on ldi rPARAM1,0x0E ; display on, cursor on, no blink. rcall WriteInstruction ; Display clear ldi rPARAM1,0x01 rcall WriteInstruction ldi rPARAM1,1 ; min 20ms delay (4ms + leeway) rcall WaitTick ; until ready to receive
; Entry mode set ldi rPARAM1,0x06 ; Advance cursor, no shift rcall WriteInstruction ret ;----------------------------------------------------------------; ; LCDGoto ; Go to character position rPARAM1 LCDGoto: ori rPARAM1,0x80 rjmp WriteInstruction ;----------------------------------------------------------------; ; LCDNumber ; Write number from 00 to 99 at current position LCDNumber: mov rPARAM2,rPARAM1 ldi rTEMP,'0' LCD10s: subi rPARAM2,10 brmi LCD1s inc rTEMP rjmp LCD10s LCD1s: mov rPARAM1,rTEMP rcall WriteData subi rPARAM2,-(0x3A) mov rPARAM1,rPARAM2 rjmp WriteData ;----------------------------------------------------------------; ; LCDString ; Write string at Z from flash to LCD at current position LCDString: lpm and r0,r0 breq LCDString_End adiw ZL,1 mov rPARAM1,r0 rcall WriteData rjmp LCDString LCDString_End: ret
;----------------------------------------------------------------; ; WriteData ; Write rPARAM1 as data WriteData: ldi rTEMP,(1< rjmp Write ;----------------------------------------------------------------; ; WriteInstruction ; Write rPARAM1 as instruction WriteInstruction: ldi rTEMP,0 Write: mov rTEMP2,rPARAM1 swap rTEMP2 andi rTEMP2,$0F or rTEMP2,rTEMP rcall Strobe mov rTEMP2,rPARAM1 andi rTEMP2,$0F or rTEMP2,rTEMP rcall Strobe rjmp Wait40 ;----------------------------------------------------------------; ; Strobe ; Output rTEMP2 to PortB and then strobe the enable line Strobe: out PORTB,rTEMP2 nop nop nop sbi PORTB,bEN nop nop nop cbi PORTB,bEN ret ;----------------------------------------------------------------; ; Wait40, WaitMicro ; Wait 40 (or rPARAM1) microseconds Wait40: ldi rPARAM1,40 ; 40uS WaitMicro: ; 4 cycles nop ; per loop dec rPARAM1 ; at 4 MHz brne WaitMicro ; = 1 uS per loop ret ;----------------------------------------------------------------; ; ReadStatus ; Read Status into rReturn. ReadStatus: ldi rTEMP,(1< rjmp Read ;----------------------------------------------------------------; ; ReadData ; Read Data into rReturn ReadData: ldi rTEMP,(1< Read: out PORTB,rTEMP nop sbi PORTB,bEN nop nop in rTEMP,PINB cbi PORTB,bEN andi rTEMP,0x0F swap rTEMP sbi PORTB,bEN mov rRETURN,rTEMP nop in rTEMP,PINB cbi PORTB,bEN andi rTEMP,0x0F or rRETURN,rTEMP rjmp Wait40 ;----------------------------------------------------------------; ; WaitBusy ; Waits until device is not busy WaitBusy: rcall ReadStatus and rRETURN,rRETURN brmi WaitBusy ; if bit 7 still set, go round again ret ;----------------------------------------------------------------; ; Strings to display String: .db "Time since start:", 0 ;-----------------------------------------------------------------
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead http://avr-asm.tripod.com/lcd44.html (1 of 2)1/20/2009 9:11:30 PM
16 BIT MATH (AVR 202)
CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/ branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pullup Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/lcd44.html (2 of 2)1/20/2009 9:11:30 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
KEYPAD WAKE UP (AVR 240) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
MATH 32X
[email protected]
DESCRIPTION This Application note scans a 4 x 4 keypad and uses The design
;* external components. Included is a test program that
DIV 24 24
flashes one of two LEDs
;* and performs a scan when a key is pressed and ;* the number of the key pressed.
The external
interrupt line is used for
FLOAT 128
;* wake-up.
The example runs on the AT90S1200 but can
be any AVR with suitable ;* changes in vectors, EEPROM and stack pointer. The timing assumes a 4 MHz clock. ;* A look up table is used in EEPROM to enable the same
MATH 202 DEC ASCII
Support E-mail:
uses a minimum of wakes up the AVR
MATH 202
4x4 keypad, wake-up on keypress 1.2 2004.11.11 All AVR Devices
;* causing the AVR to wake up on keypress.
DIV16 XX
SQRT16
Title: Version: Last Updated: Target:
sleep mode
MATH YX
DIV 3216
A V R 2 4 0
************************
ASM MATH
MATH 202
N O T E
structure to be used ;* with more advanced programs e.g ASCII output to
INT ASCII
displays.
HX2ASC
; ***************************************************************************
AVG8 222 ;***** Register used by all programs ;******Global variable used by all routines
FFT7 COPY 102
.def
LPM 108 EPROM 100
temp
=r16
;general scratch space
=3 =2 =1 =0 =7 =6 =5 =4
;keypad input rows
=0 =1 =2
;green LED ;red LED ;interrupt input
;Port B pins
SER EPROM .equ .equ .equ .equ .equ .equ .equ .equ
DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220
ROW1 ROW2 ROW3 ROW4 COL1 COL2 COL3 COL4
;keypad output columns
CRC 236 ;Port D pins
XMODEM REC UART 304
.equ .equ .equ
UART 305 UART 128 UART BUFF
GREEN RED INTR
.include "1200def.inc"
USB 232
;***** Registers used by interrupt service routine
AVR ISP ISP 2313 .def .def
ISP 1200
key status
=r17 =r21
;key pointer for EEPROM ;preserve sreg here
AVR SPI ;***** Registers used by delay subroutine ;***** as local variables
I2C 300 I2C 302
.def .def .def
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
fine medium coarse
=r18 =r19 =r20
;loop delay counters
;*****Look up table for key conversion****************************** .eseg segment .org 0
;EEPROM
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
.db 1,2,3,15,4,5,6,14,7,8,9,13,10,0,11,12 ;****Source code*************************************************** .cseg ;CODE segment .org 0 rjmp reset ;Reset handler rjmp scan ;interrupt service routine reti ;unused timer interrupt reti ;unused analogue interrupt ;*** Reset handler ************************************************** reset:
KBD PC/128 PS2 EMU BOOT MG8
ldi temp,0xFB
;initialise port D
out DDRD,temp
;all OUT except PD2
ldi temp,0x30
;turn on sleep mode
out MCUCR,temp
;down plus
ldi temp,0x40
;enable external
out GIMSK,temp sbi ACSR,ACD
;shut down
as O/I ext.int.
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS
and power interrupt on low level. interrupts
DELAYS CALL ID
comparator to save power
DTMF 314
main:
PWM 6CH
global interrupts
PWM 10K
as I/O
cli ldi temp,0xF0
;initialise port B
out DDRB,temp ldi temp,0x0F
; 4 OUT 4 IN ;key columns all
out PORTB,temp
;active pull ups on
ldi temp,0x07
;enable pull up on
out PORTD,temp sei
;turn off LEDs ;enable global
sleep rcall flash
;fall asleep ;flash LEDs for
ldi temp,0x40 out GIMSK,temp
;enable external
rjmp main
;go back to sleep
ENCODE STH-11
low and
ATMEL CORP AVR BUTTERFLY
;disable
rows enabled PD2 and
AVR BOOK interrupts ready
example usage
interrupt after keyscan ;****Interrupt service routine*************************************** scan: in status,SREG register sbis PINB,ROW1 keypress ldi key,0 sbis PINB,ROW2 ldi key,4 sbis PINB,ROW3 ldi key,8 sbis PINB,ROW4 ldi key,12 ldi temp,0x0F to out DDRB,temp ldi temp,0xF0 out PORTB,temp rcall settle port to settle sbis PINB,COL1 keypress ldi temp,0 sbis PINB,COL2 ldi temp,1 sbis PINB,COL3 ldi temp,2 sbis PINB,COL4 ldi temp,3 add key,temp for pointer ldi temp,0xF0 B as I/O out DDRB,temp ldi temp,0x0F low and out PORTB,temp rows enabled out SREG,status register
;preserve status ;find row of ;and set ROW pointer
;change port B I/O ;find column press ;enable pull ups and ;write 0s to rows ;allow time for ;find column of ;and set COL pointer
;merge ROW and COL ;reinitialise port ; 4 OUT 4 IN ;key columns all ;active pull ups on ;restore status
ldi temp,0x00 out GIMSK,temp
;disable external
interrupt ;have to do this, because we're ;using a leveltriggered interrupt reti
;go back to main
for example program ;***Example test program to flash LEDs using key press data************ flash:
out EEAR,key
;address
EEPROM sbi EECR,EERE in temp,EEDR
;strobe EEPROM ;set number of
tst temp breq zero
;is it zero? ;do RED LED
flashes
green_flash: cbi PORTD,GREEN ;flash green LED 'temp' times rcall delay sbi PORTD,GREEN rcall delay dec temp brne green_flash ret ldi temp,10 cbi PORTD,RED
exit: zero: flash_again:
;flash red
LED ten times rcall delay sbi PORTD,RED rcall delay dec temp brne flash_again rjmp exit
;****Time Delay Subroutine for LED flash********************************* delay: ldi coarse,8 ;triple nested FOR loop cagain: ldi medium,255 ;giving about 1/2 second magain: ldi fine,255 ;delay on 4 MHz clock fagain: dec fine brne fagain dec medium brne magain dec coarse brne cagain ret ;***Settling time delay for port to stabilise****************************** settle: ldi temp,255 tagain: dec temp brne tagain ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/kbd240.html (1 of 2)1/20/2009 9:12:04 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/kbd240.html (2 of 2)1/20/2009 9:12:04 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
KEYPAD LED MUX (AVR 242) HOME RETRO_DAN ASM FORUM
;**** A P P L I C A T I O N ;* ;* Title: ;* ;* ;* ;* ;* ;* ;* ;*
TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202
MATH YX DIV16 XX
;* four digit LED display and two ON/OFF outputs to ;* interface circuitry.
Tactile feedback is provided ;* on every key press by a piezo sounder which beeps when a key is pressed. ;* Included is a main program that allows clock setting via the keypad
INT ASCII
;* and one ON/OFF time setting per 24 hours for each load, functions for the ;* real time clock, key scanning, and adjustment routines. The example runs on ;* the AT90S1200 to demonstrate how limited I/O
EPROM 100
;* be any AVR with suitable changes in vectors, EEPROM and stack pointer. ;* The timing assumes a 4.096 MHz crystal is employed (a 4 MHz crystal produces ;* an error of -0.16% if 178 instead of 176 used in the
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
timer load sequence, but this ;* could be adjusted in software at regular intervals). Look up tables are ;* used in EEPROM to decode the display data, with additional characters provided
VFX MEM SORT 220
can be
overcome, but can
COPY 102 LPM 108
LED loads are driven in this
;* any load with the addition of suitable components.
SQRT16
FFT7
DESCRIPTION This Application note covers a program to provide a
multiplexed
example but it could drive
AVG8 222
[email protected]
;* With input via a 4 x 4 matrix keypad, output to a
FLOAT 128
HX2ASC
Support E-mail:
functions.
drive loads via additional
DEC ASCII
1.0 98.07.24 All AVR Devices
;* timer or real-time clock using I/O pins for dual
DIV 3216
MATH 202
Version: Last Updated: Target:
24 hr Industrial
DIV 24 24
MATH 202
Multiplexing LED drive and 4x4
keypad sampling
TUTORIAL #2
MATH 32X
A V R ???
************************
ASM MATH TUTORIAL #1
N O T E
;* for time and ON/OFF setting displays and a key pad conversion table. ;* If the EEPROM is needed for your application the
CRC 236 XMODEM REC UART 304
tables could be moved ;* to ROM in the larger AVR devices. ; ***************************************************************************
UART 305 ;***** Registers used by all programs ;******Global variables used by routines
UART 128 UART BUFF
.def .def
loset hiset
.def
ld1minon=r3
;storage for load on and
.def .def
ld1hron =r4 ld1minoff=r5
;set from keypad entry ;and tested in the
.def
ld1hroff=r6
;and stores on or off times
.def .def .def .def
ld2minon=r7 ld2hron =r8 ld2minoff=r9 ld2hroff=r10
.def .def
temp second
=r16 =r17
;general scratch space ;storage for RTC second
.def
minute
=r18
;storage for RTC minute
.def .def
hour mask
=r19 =r20
;storage for RTC hour count ;flash mask for digits
.def .def .def .def
blink bounce flash lobyte
=r21 =r22 =r23 =r24
;colon blink rate counter ;keypad debounce counter ;flash delay counter ;storage for display
.def
hibyte
=r25
;storage for display
.def
key
=r26
;key number from scan
USB 232 AVR ISP
off times
AVR SPI I2C 300 I2C 302
housekeeping function for the loads
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA
count count
ADC 128 ADC 10B
flashing
ADC 400 ADC 401 THERM 232
function minutes digits
IRD 410 LCD HD44
function hours digits
LCD 2313
;***'key' values returned by
LCD44 2313 KBD 240 MUX 242 KBD PS2
'keyscan'*************************** 11 9
12 13 D
14
A
0
15 B
C
90 DAYS
1
2
3
4
5
6
7
8
9
;KEY
1
2
3
F
4
5
6
E
7
8
;FUNC
1
2
3 LD1ON 4
5
6 LD1OFF 7
8
.def .def
tock flags
=r27 =r28
2
1
;5 ms pulse ;flag byte for keypad
;
7
6
;
5ms
5
4
3
0 keyok ld2off ld2on ld1off
ld1on ld2 ld1 .equ
ms5
; tick =7
0 = off, 1 = on ;ticks at 5 ms intervals
.equ
keyok
=6
;sets when key is
.equ
ld2off
=5
;set by load ON/OFF key
.equ .equ .equ .equ
ld2on ld1off ld1on ld2
=4 =3 =2 =1
;up the need for action ;in the housekeeping routine
.equ
ld1
=0
;check load on/off times.
for display time
DTMF 314 PWM 6CH
debounced, must be cleared again
PWM 10K
press and flags
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
9
command keys
DELAYS CALL ID
10
LD2ON SET 0 CLEAR LD2OFF
BOOT DR8
CLOCK 8564
0
NONE
BOOT MG8
ALM CLK
;VALUE 16
KBD PC/128 PS2 EMU
;storage for timeset minutes ;storage for timeset
hours
ISP 2313 ISP 1200
=r1 =r2
;when set tells the
housekeeping routine to
;***the T flag in the status register is used as a SET
AVR BOOK flag for time set
.equ
clear
=0
;RTC modification demand
=0 =1 =2 =3 =4 =5 =6 =7
;LED ;LED ;LED ;LED ;LED ;LED ;LED ;LED
flag
;Port B pins .equ .equ .equ .equ .equ .equ .equ .equ
col1 col2 col3 col4 row1 row2 row3 row4
a segment/keypad col b segment/keypad col c segment/keypad col d segment/keypad col e segment/keypad row f segment/keypad row g segment/keypad row decimal point/keypad
1 2 3 4 1 2 3
row 4 ;Port D pins .equ
A1
=0
;common anode drives
.equ .equ .equ .equ .equ .equ
A2 A3 A4 LOAD1 LOAD2 PZ
=1 =2 =3 =4 =5 =6
; ; ; ;Load 1 output (active low) ;Load 2 output (active low) ;Piezo sounder output
(active low)
(active low) .include "1200def.inc" ;***** Registers used by timer overflow interrupt service routine
.def
timer
=r31
;scratch space for timer
.def
status
=r0
;low register to preserve
loading status register ;*****Look up table for LED display decoding ********************** .eseg
;EEPROM
segment .org 0 table1: .db 0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90 ;digit 0 8 9 .db ;digit
1
2
3
4
5
6
7
0x86,0x8E,0xA3,0xAB,0XFF,0XFF E f o n BLANK
special
characters ;****Look up table for key value conversion into useful numbers**** ;key 0
B
1
2
3
F
4
5
6
E
7
8
9
D
A
C table2:
.db
1, 2, 3,15, 4, 5, 6,14, 7, 8, 9,
13, 10, 0, 11, 12 ;value 13
14
0
1
2
3
4
5
6
7
8
9
10
11
12
15
;****Source code*************************************************** .cseg segment .org 0 rjmp reset nop interrupt rjmp tick overflow (5 ms) nop interrupt
;CODE
;Reset handler ;unused ext. ;timer counter ;unused analogue
;*** Reset handler ************************************************** ;*** to provide initial port, timer and interrupt setting up reset: ser temp out DDRB,temp
; ;initialize port B
out DDRD,temp
;initialize port D
out PORTB,temp
;key columns all
out PORTD,temp
;turn off LEDs and
ldi temp,0x04
;timer
out TCCR0,temp ldi timer,176 out TCNT0,timer
;load timer for 5 ms ;(256 - n)
ldi temp,0x02
;enable timer
out clr clr clr
;clear control flags ;clear 5 ms tick ;clear key bounce
as all Outputs as all Outputs high/LEDs off loads off prescalar /256
*256*0.2441 us interrupts TIMSK,temp flags tock bounce
counter clr flash clr blink sei
;enable global
interrupts ;****Flash EEEE on LEDS as test and power down warning************** ;****repeats until SET key is pressed on keypad
timesetting:
ldi hibyte,0xaa
;show
"EEEE" on LED ldi lobyte,0xaa ser mask
;display and ;set flashing
display notyet:
rcall display
;display
until time set brtc notyet
;repeat until SET
rcall setrtc
;and reset
mov hour,hiset
;and reload
mov minute,loset clt
;and minutes ;clear T flag
key pressed time hours
;*****Main clock house keeping loop***************************** do: clr mask cpi blink,100 brne nohalf clr blink com flash
;do housekeeping ;is half second up
cpi second,60 brne nochange clr second
;is one minute up? ;no ;yes clear seconds
inc minute mov temp,minute andi temp,0x0f cpi temp,10 brne nochange andi minute,0xf0 ldi temp,0x10 add minute,temp
;add one to minutes
cpi minute,0x60 brne nochange clr minute
;is it 60 minutes? ;no ;yes, clear minutes
inc hour mov temp,hour andi temp,0x0f cpi temp,10 brne nochange andi hour,0xf0 ldi temp,0x10 add hour,temp
;add one to hours
cpi hour,0x24
;is it 24
brne sameday clr hour
;no, ;yes, clear time
clr minute clr second
;to start new day
;invert flash
nohalf:
and
;mask high minute ;is it ten minutes? ;no ;clear low minutes ;increment high
minutes
and
;mask high hour ;is 10 hours up? ;no ;yes, increment ;high hours
nochange: hours?
variables
sameday:
;update times mov lobyte,minute mov hibyte,hour rcall display brtc case1 rcall setrtc
;show time for 20 ms ;if not SET ;and reset
mov hour,hiset
;and reload
mov minute,loset clt
;and minutes ;else, clear T
time hours
flag case1:
sbrc flags,ld1
;is load 1
case2:
rjmp chkload1 sbrc flags,ld2
;yes, check load 1 ;is load 2
case3:
rjmp chkload2 ;yes, check load 2 sbrc flags,ld1on ;is load 1
case4:
rjmp setld1on ;yes reset on time sbrc flags,ld1off ;is load 1
case5:
rjmp setld1off ;yes reset off time sbrc flags,ld2on ;is load 2
case6:
rjmp setld2on ;yes reset on time sbrc flags,ld2off ;is load 2
case7:
rjmp setld2off rjmp do
active?
active
on time reset
off time reset
on time reset
on time reset ;yes reset on time ;repeat
housekeeping loop ;****case routines to service load times and key presses********
chkload1:
cp hour,ld1hroff
;is load 1 off time
brne onload1 cp minute,ld1minoff brne onload1 sbi PORTD,LOAD1
;yes, turn load 1
cp hour,ld1hron
;is load 1 on time
brne case2 cp minute,ld1minon brne case2 cbi PORTD,LOAD1 rjmp case2
;yes,turn load 1 on ;repeat with load on
cp hour,ld2hroff
;is load 2 off time
brne onload2 cp minute,ld2minoff brne onload2 sbi PORTD,LOAD2
;yes, turn load 2
cp hour,ld2hron
;is load 2 on time
brne case3 cp minute,ld2minon brne case3 cbi PORTD,LOAD2 rjmp case3
;yes,turn load 2 on ;repeat with load on
reached?
off onload1: reached?
chkload2: reached?
off onload2: reached?
setld1on: sbr flags,0x01 rcall setrtc mov ld1hron,hiset mov ld1minon,loset cbr flags,0x04 rjmp case4
;make load 1 active ;pickup new on time ;and store
rcall setrtc mov ld1hroff,hiset mov ld1minoff,loset cbr flags,0x08 rjmp case5
;pickup new off time ;and store
sbr flags,0x02 rcall setrtc mov ld2hron,hiset mov ld2minon,loset cbr flags,0x10 rjmp case6
;make load 2 active ;pickup new on time ;and store
rcall setrtc mov ld2hroff,hiset mov ld2minoff,loset cbr flags,0x20 rjmp case7
;pickup new on time ;and store
;clear ld1on flag
setld1off:
;clear ld1off flag
setld2on:
;clear ld2on flag
setld2off:
;clear ld2off flag
;****Multiplexing routine to display time and scan keypad every***** ;****second pass,used by all routines taking digits from hibyte ;****and lobyte locations with each digit on for 5 ms display:
ser temp ;clear display out PORTB,temp ;****Keypad scanning routine to update key flags******************* keyscan:
cbr flags,0x40 ldi key,0x10
;clear keyok flag ;set no key pressed
ser temp
;set keypad port
out PORTB,temp
;reinitializing the
in temp,PORTD
;turn off LEDs and
ori temp,0x0f out PORTD,temp ldi temp,0x0f
;untouched prior to ;key scan ;set columns output
out DDRB,temp
;rows input with
ldi temp,0xf0
;enabled and all
out PORTB,temp ldi temp,20 dec temp brne tagain1 sbis PINB,ROW1
;low ready for scan ;short settling time
ldi key,0 sbis PINB,ROW2 ldi key,4 sbis PINB,ROW3 ldi key,8 sbis PINB,ROW4 ldi key,12 ldi temp,0xF0
;and set ROW pointer
out DDRB,temp ldi temp,0x0F out PORTB,temp ldi temp,20 dec temp brne tagain2
;find column press ;enable pull ups and ;write 0s to rows ;short settling time
value high prior to port leave loads
and pull-ups columns
tagain1:
;find row of
keypress
;change port B I/O
to
tagain2:
;allow time for
port to settle clr temp sbis PINB,COL1
;find column of
keypress ldi temp,0 sbis PINB,COL2 ldi temp,1 sbis PINB,COL3 ldi temp,2 sbis PINB,COL4 ldi temp,3 add key,temp
;and set COL pointer
cpi key,0x10 breq nokey
;if no key pressed ;escape routine,
ldi temp,0x10 add key,temp out EEAR,key
;change to table 2 ;send address to
sbi EECR,EERE in key,EEDR
;strobe EEPROM ;read decoded
cpi key,10 brne notset set
;is it SET key ? ;no check next key ;yes set T flag in
;merge ROW and COL
for pointer
else
EEPROM (0 - 15)
number for true key convert:
status register notset:
cpi key,11
;is key
CLEAR? brne notclear sbi PORTD,LOAD1
;no, check next key ;yes, shut down all
sbi PORTD,LOAD2 cbr flags,0x03
;deactivate both
cpi key,15 brne notld1on sbr flags,0x04 cpi key,14 brne notld1off sbr flags,0x08
;is key LD1ON? ;no, check next key ;yes, set LD1ON flag ;is key LD1OFF? ;no, check next key ;yes, set LD1OFF
cpi key,13 brne notld2on sbr flags,0x10 cpi key,12 brne notld2off sbr flags,0x20
;is key LD2ON? ;no, check next key ;yes, set LD2ON flag ;is key LD2OFF? ;no, check next key ;yes, set LD2OFF
loads
loads notclear:
notld1on:
flag notld1off:
notld2on:
flag notld2off: ;***Tactile feedback note generation routine***************** ;***provides a 4 kHz TONE to the piezo sounder for 5 ms***** tactile:
t1again:
t2again:
notok:
nokey:
cbr flags,0x80 cbi PORTD,PZ ldi temp,125 dec temp brne t1again sbi PORTD,PZ ldi temp,125 dec temp brne t2again sbrs flags,ms5 rjmp tactile cpi bounce,40 brlo nokey sbr flags,0x40 ser temp out DDRB,temp
;turn on piezo ;for a short time
;turn on piezo ;for a short time
;repeat for 5ms
;set bounce flag ;reinitialize port
B as all Outputs out PORTB,temp
;and clear LEDs
;***Display routine to multiplex all four LED digits**************** cbi PORTD,A1 mov temp,lobyte
;turn digit 1 on ;find low minute
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash every 1/2
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
digit1: flag of digit EEPROM (0 - 15)
second needed ms led1:
sbrs flags,ms5
;5 ms
finished? rjmp led1 sbi PORTD,A1 ser temp out PORTB,temp cbi PORTD,A2 mov temp,lobyte swap temp
;no, check again ;turn digit 1 off ;clear display
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash every 1/2
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
; ;find high minute
digit2: flag of digit EEPROM (0 - 15)
second needed ms led2:
sbrs flags,ms5
;5 ms
finished? rjmp led2 sbi PORTD,A2 ser temp out PORTB,temp cbi PORTD,A3 mov temp,hibyte
;no, check again ; ;clear display
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs second,clear andi temp,0x7f sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash colon
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
;
digit3: flag of digit EEPROM (0 - 15)
;flash every 1/2
second needed ms led3:
sbrs flags,ms5
;5 ms
finished? rjmp led3 sbi PORTD,A3 ser temp out PORTB,temp cbi PORTD,A4 mov temp,hibyte swap temp andi temp,0x0f brne digit4 ldi temp,0xff
;no, check again
cbr flags,0x80
;clear 5 ms tick
andi temp,0x0f
;mask high nibble
out EEAR,temp
;send address to
sbi EECR,EERE in temp,EEDR sbrs flash,clear
;strobe EEPROM ;read decoded number ;flash every 1/2
or temp,mask
;flash digit if
out PORTB,temp
;write to LED for 5
;clear display ;
;is hi hour zero? ;yes,blank hi hour
digit4: flag of digit EEPROM (0 - 15)
second needed ms led4:
sbrs flags,ms5
;5 ms
finished? rjmp led4 sbi PORTD,A4 ser temp out PORTB,temp tst mask breq outled cpi blink,50 brlo outled clr blink
;no, check again
com flash
;and invert flash
;clear display ;is flash complete? ;yes, exit ;is blink time done? ;no, exit ;yes, clear blink
rate counter byte outled:
ret
;****Function to Set RTC/on-off hours and minutes from keypad ;****returns with minutes in 'loset' and hours in'hiset' setrtc:
ser mask
;set
flashing display ldi hibyte,0xdf
;place 'n' in hi
ser lobyte
;and blank in lo hr
clr bounce rcall display
;display and check
hour & minutes hihrus: bounce1: keypad sbrs flags,keyok rjmp bounce1 cbr flags,0x40 cpi key,0x03 brsh hihrus hihrok:
;clear keyok flag ;is high hour > 2 ;yes, read key again ;no, valid
entry swap key
;move hihour to hi
mov hiset,key ldi hibyte,0x0d
;and store in hours ;place 'n' in lo
add hibyte,hiset
;merge hihour and
clr bounce rcall display
;display and check
sbrs flags,keyok rjmp bounce2 cbr flags,0x40
;is key stable? ;no try again ;yes, clear keyok
mov temp,hibyte
;check that total
andi temp,0xf0 add temp,key cpi temp,0x24 brsh lohrus add hiset,key
;are not > 24
mov hibyte,hiset
;display hours as
ldi lobyte,0xdf
;place 'n' in hi
clr bounce rcall display
;display and check
sbrs flags,keyok rjmp bounce3 cbr flags,0x40 cpi key,6 brsh himinus
;clear keyok flag ;is hi minutes >5 ;no, read key again
swap key
;move himin to hi
mov loset,key
;and store in
ldi lobyte,0x0d
;place 'n' in lo
add lobyte,loset
;merge with hi
clr bounce rcall display
;display and check
sbrs flags,keyok rjmp bounce4 cbr flags,0x40 cpi key,10 brsh lominus add loset,key
;clear keyok flag ;is key >9 ;no, read key again ;yes, merge hi and
clr mask ret
;clear digits flash ;and return with
nibble
hour 'n' lohrus: bounce2: keypad
flag hours
;is hour>24? ;yes, read key again ;no, merge hi and
lo hours lohrok: set minutes himinus: bounce3: keypad
lominok: nibble minutes minutes minute lominus: bounce4: keypad
lo minutes
time set ;****Timer Overflow Interrupt service routine****************************** ;****Updates 5 ms, flash and debounce counter to provide RTC time reference tick: in status,SREG
;preserve status
inc tock
;add one to 5 ms
inc blink
;and blink rate
inc bounce
;and bounce rate
sbr flags,0x80
;set 5 ms flag for
cpi tock,200 breq onesec
;is one second up? ;yes, add one to
nop
;balance interrupt
rjmp nosecond inc second
;no, escape ;add one to
clr ldi out out
;clear 5 ms counter ;reload timer
register 'tock' counter counter delay display time
seconds time onesec: seconds nosecond:
tock timer,176 TCNT0,timer SREG,status
;restore status
register reti
;return to main
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due http://avr-asm.tripod.com/mux242.html (1 of 2)1/20/2009 9:12:40 PM
16 BIT MATH (AVR 202)
to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/mux242.html (2 of 2)1/20/2009 9:12:40 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AT/PS2 KEYBOARD PROGRAM HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
; *************************************************************************** ; ; File Name :"PS2Drv.asm" ; Title :PS/2 target communication protocoll ; Date :2001.10.06. ; Date (Last) :2002.12.15. ; Version :1.10 ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; - PS/2 style communication from AT keyboard or MARGOR HI01 to MAGOR CP01-1v2 ; ; CLK & DATA = H -> Two way communication ; DATA = L -> PC (MAGOR) sends to Keyb ; CLK = L -> PC (MAGOR) inhibits communiaction ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2001.10.06 VFX Creation ; 1.02 2001.12.27 VFX Modify for MAGOR CP01-1v2 ; 1.10 2002.12.15 VFX Fixed Sendig Command to keyboard, time out added ; ; ; ************************************************************************** ;* Hardware Abstraction Layer
VFX MEM
PS2_CLKPort = PORTD PS2_CLKDIR = DDRD PS2_CLKPIN = PIND KCLK = 2
.EQU .EQU .EQU .EQU
PS2_DATPort = PORTB PS2_DATDIR = DDRB PS2_DATPIN = PINB KDATA = 0
SORT 220
.EQU .EQU .EQU .EQU
CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; *************************************************************************** ;* Const Def
ISP 2313 ISP 1200
.equ
wait100us = SYSCLK/10000
;ennyi ciklus
.EQU
Kb_ScData_Lenght = 6
;Received
100us
AVR SPI I2C 300
ScanCode buffer
I2C 302 ;-------------------------------;Define commands to the keyboard. ; .equ SET_KEYBOARD_INDICATORS = 0xED .equ KEYBOARD_ECHO = 0xEE .equ SELECT_SCAN_CODE_SET = 0xF0 .equ READ_KEYBOARD_ID = 0xF2 .equ SET_KEYBOARD_TYPEMATIC = 0xF3 .equ KBD_ENABLE = 0xF4 .equ KBD_DISABLE = 0xF5 .equ SET_ALL_TYPEMATIC_MAKE_BREAK = 0xFA .equ KEYBOARD_RESET = 0xFF
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B
;--------------------------------; Define the keyboard responses. ; .equ ACKNOWLEDGE = 0xFA .equ RESEND = 0xFE .equ KEYBOARD_COMPLETE_SUCCESS .equ KEYBOARD_COMPLETE_FAILURE .equ KEYBOARD_BREAK_CODE = 0xF0 .equ KEYBOARD_DEBUG_HOTKEY_ENH
ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
= 0xAA = 0xFC
;BAT complete
= 0x37
;SysReq scan
= 0x54
;SysReq scan
code for Enhanced Keyboard .equ KEYBOARD_DEBUG_HOTKEY_AT code for 84-key Keyboard
MUX 242 KBD PS2 KBD PC/128 PS2 EMU
.equ
ST_Success
= 0x80
;a parancs
.equ
ST_Unsuccess
= 0x81
;a parancs
.equ
ST_ResendError
= 0x82
;3-szor probltuk
sikeres volt sikertelen
BOOT MG8 BOOT DR8 ALM CLK
kuldeni a keyboard fele, de nem ment .equ
ST_ACKnotreseived=0x83
;ACK-t vartunk
de nem az jott...
CLOCK 8564 90 DAYS DELAYS CALL ID
; *************************************************************************** ;**** VARIABLES .DSEG
DTMF 314 PWM 6CH
PtrINT0:
.BYTE 2
;INT0 Keyboard interrupt
aktualis cime ;int0 eseten ide ugrik
PWM 10K Kb_BitCounter:
ENCODE STH-11
;hany bitet olvasott
ResevedBits: .byte 1 ;received Kb_bits Kb_Paritas: .byte 1 ;Vett paritas bit
ATMEL CORP AVR BUTTERFLY AVR BOOK
.BYTE 1
eddig be
Kb_ScHead:
.byte 1
;Dekodolatlan Scankod buffer
Kb_ScTail: Kb_ScData:
.byte 1 .byte Kb_ScData_Lenght
Head mutato
kb_SendByte:
.byte 1
;send this data to
keyboard kb_ComStat: .byte 1
;=0 szabadon megallithato a
komunikacio
kb_lastAction:
;=1 komunikacio megallitasa tilos ;=3 kuldes folyamatban .byte 1 ;utolso muvelet mi volt ;=255 normal mukodes ;=0,1,2,3,4,5 command/parameter
kb_CmdBuffer:
.byte 3
kuldes volt ACK-ot varunk vissza ;1 CMD + 3 data bytenak
van hely kb_ResendCnt: .byte 1 elkuldeni, ha tobb mint 3 akkor error kb_Status: .byte 2 jumptabla: .byte 2 kb_SWStatus:
.byte 1
;hanyszor probaltuk
;keyboard status ; [7:6] = 00 Standard PS/2
keyboard ; = 01 MAGOR HI-01 keyboard ; = 1x future ; [5:0] = CAPS,NUM, SCROLL lock & future LEDs ; *************************************************************************** .ESEG
; *************************************************************************** .CSEG ; *************************************************************************** ; PS/2 Billentyuzet inicializalasa ; Init_PS2: CBI PS2_CLKPort,KCLK CBI PS2_CLKDIR,KCLK stated external pull-up res!! CBI PS2_DATPort,KDATA CBI PS2_DATDIR,KDATA stated external pull-up res!!
;CLK pin tre-
;DATA pin tre-
ldi
R16,Low(Kb_Rec_Start)
;Most csak adat
sts ldi sts
PtrINT0+0,R16 R16,High(Kb_Rec_Start) PtrINT0+1,R16
clr sts
R16 Kb_ScHead,R16
;ScanCode
sts sts sts sts sts ldi sts
Kb_ScTail,R16 kb_ComStat,R16 kb_ResendCnt,R16 kb_Status,R16 kb_SWStatus,R16 R16,255 kb_lastAction,R16
;normal mukodes
ldi
R16,11
;1 start +8 adat
sts
Kb_BitCounter,R16
ldi ldi sts sts
ZL,low(NormalUzem) ZH,high(NormalUzem) jumptabla+0,ZL jumptabla+1,ZH
in cbr
R16,MCUCR R16,0b00000011
;mask for 1,0
sbr
R16,0b00000010
;set for falling
OUT
MCUCR,R16
;1:0 = Inerrupt
vetele van!
Pointer Head = 0
+1 par +1 stop
bits edge Sense Control for INT0 ; 00 -> Low Level INT0 ; 01 -> Reserved ; 10 -> Falling Edge INT0 ; 11 -> Rising Edge INT0 ldi
R16,64
;INT0,1 IRQ flag
out
GIFR,R16
in ori OUT
R16,GIMSK R16,64 GIMSK,R16
;INT0 enabled ;6. = 1 EXT INT0
ldi
R16,250
;varunk 2500ms-
sts
SWTmr0,R16
;ha kozben
lds tst breq
R16,SWTmr0 R16 WTCTO
;ha innen ugrik,
sleep nop rcall brcs
Get_ScanC WTC0
rcall rcall brcs cpi brne
kb_CMD_Reset WaitToComplete KeybErr R16,KEYBOARD_COMPLETE_SUCCESS KeybErr
rcall rcall brcs
kb_CMD_ReadID WaitToComplete KeybErr
ldi cpi brne cpi
R18,64 R16,0xDE nonPS2 R17,0xD0
;0x83AB
breq
storeType
;0x9EAB -
torlese
ACTIVE
ig, hogy a power-up reset befejezodjon megjon az 0xAA, akkor jo. WTC0:
szinte biztos hogy hiba lesz
WTCTO:
nem tudom mi lehet minden billentyu vel ter vissza ;0xDED0 csak MAGOR HI-01 lehet nonPS2:
ldi
R18,04
;
Itt csak szabvany billentyu lehet storeType: sts
kb_SWStatus,R18
rcall rcall brcs cpi brne
kb_CMD_ALLMakeBrake WaitToComplete KeybErr R16,ST_Success KeybErr
ldi
R17,0
rcall rcall brcs cpi brne
kb_CMD_SetSpeed WaitToComplete KeybErr R16,ST_Success KeybErr
ldi rcall
R17,0 kb_CMD_SetLEDs
rcall brcs cpi brne
WaitToComplete KeybErr R16,ST_Success KeybErr
ldi ldi lds andi
R16,low(ps2stszov*2) R17,high(ps2stszov*2) R18,kb_SWStatus R18,0b11000000
breq ldi ldi rjmp
kszoveg R16,low(magorszov*2) R17,high(magorszov*2) kszoveg
ldi ldi rcall ret
R16,Low(kbTimeOutErr*2) R17,High(kbTimeOutErr*2) SendMSG
;
keyboard tipus eltarolva, majd kesobb kell meg
;30char/
s, 250ms rep. time
;LEDek
kikapcsolva
;csak a
bill tipusa kell
KeybErr:
kszoveg:
;************************************************ ;* WaitToComplete ;* kivarja egy billentyuparancs vegrehajtasat vagy time-out ;* R17:R16 ststus kod (redszerint csak az R16 kell) ; c=1 error WaitToComplete: ldi R16,40 ;ha 400ms-ig nincs valasz hiba @100Hz rendszermegwszakitas mellett sts SWTmr0,R16 WTC1: lds R16,SWTmr0 tst R16 breq WTCTimeOut lds R16,kb_Status+0 cpi R16,0x33 breq WTC1 ldi R17,kb_Status+1 clc ret WTCTimeOut: sec ret
; ****************************************************************************** ;* INERRUPT: R E C E I V E ;* ;* External generated clock & data - host changes the Data line only when ;* the Clock line is low, and data is latched on the falling edge of the clock pulse ;* Host may abort transmission at time before the 11th clock pulse (acknowledge bit) ;* by holding Clock low for at least 100 microseconds. ;* ;* EXT_INT0: push ZL push ZH in ZL,SREG ; preserve main OS status reg. push ZL push R16 push R2 in bst
R2,PS2_DATPIN R2,KDATA
lds lds icall
ZL,PtrINT0+0 ZH,PtrINT0+1
ldi
R16,64
;INT0
out
GIFR,R16
;lehet,
pop pop pop out
R2 R16 ZL SREG,ZL
;
pop pop reti
ZH ZL
;T-ben a
vett bit
;Int0
vegrehajto rutin meghivasa IRQ flag torlese hogy ez nem kell majd!!!!
restore previous status reg
;***************************************** ; Receive 11 keyboard bit ; Kb_Rec_Start: lds R16,Kb_BitCounter dec R16 sts Kb_BitCounter,R16 cpi R16,10 ;start bitnel tartunk breq
JaStartbit cpi R16,1 breq JaParitasJon cpi R16,0 breq JaStopJon
;Paritasbit jon? ;Stopbit jon?
;**************************************
;8
adatbit vetele ;* 8 DATA BIT Kb_Rec_Dat: lds
R16,ResevedBits
;az eddig
lsr bld
R16 R16,7
;rota 7. -> 0. ;az ujbitet a 7.
sts clr bld
ResevedBits,R16 R2 R2,0
;tarolas
lds add sts
R16,Kb_Paritas R16,R2 Kb_Paritas,R16
;uj paritas
lds
R16,Kb_BitCounter
;ha tobb mint 9
beolvasott bitek
pos-on taroljuk
;a paritas
generalashoz kell
eltarolva
bit jott eddig, ;akor mar nem lehet megallitani ;a vetelt. Be kell fejezni! cpi brsh
R16,4 kb_Rec_end1 ldi R16,1 sts kb_ComStat,R16 kb_Rec_end1:
ret
;************************************** ;* START BIT JaStartbit: clr sts
R16 Kb_Paritas,R16
;Paritas = 0,
bld
R16,0
;Received Start
tst brne ret
R16 Kb_StartErr
most meg :) bit in pos. 0
Kb_StartErr: ;ide jon az az eset, ha a start bit = 1 ,azaz hiba van!!!! ;de Vigyazat! Meg interrupt rutinban vagyuk!!!! ret ;************************************** ; PARITAS BIT JaParitasJon: bld
clr R16,0
R16 ;Paritasbit
tarolasa a 0. bitben lds
R2,Kb_Paritas
;R2 vett adat
inc
R2
;paratlan
par, R16 vett paritas bit paritas kell! eor R2,R16
;R2 = parity xor
parity bit ror
R2
;C-flagben a
brcs ret
Kb_RxParErr
parity
Kb_RxParErr:
;ide jon majd a paritas hiba lekezelese ;De figyelem, meg mindig interruptban
vagyuk!!!!!! ret
;************************************ ;* STOP BIT JaStopJon:
bld
R16,0
;itt mar R16=0,
tst breq
R16 Kb_StopErr ldi R16,11
R16=stop bit
;1 start
+8 adat +1 par +1 stop sts
Kb_BitCounter,R16
lds cpi breq
R16,kb_lastAction R16,255 NemParancsvolt
lds cpi brne
R16,ResevedBits R16,RESEND nemresend
lds inc sts cpi
R16,kb_ResendCnt R16 kb_ResendCnt,R16 R16,4
;a kovetkezo
adat vetelehez
;ha mar
haromszor probaltuk elkuldeni, de nem ment ;akkor resend error brne ldi sts
Mehettovabb R16,255 kb_lastAction,R16
ldi sts ret
R16,ST_ResendError kb_Status,R16
;vissza anormal
mukodesre
Mehettovabb: NextComdData
lds lds ijmp
ZL,jumptabla+0 ZH,jumptabla+1
nemresend:
rcall ret
NemParancsvolt: rcall
Put_ScanC
;Scankod a
R16 kb_ComStat,R16
;Stop tilalom
bufferbe clr sts feloldva! ret Kb_StopErr: ;ide jon majd a hibas stop bit lekezelese ;Meg mindig INTERRUPTBAN vagyunk!!!! clr sts
R16 kb_ComStat,R16
;Stop tilalom
feloldva! ret
;************************************************ ;* The Put_ScanC FIFO manager * ;* in: * ;* out c=1 hiba * ;************************************************ Put_ScanC: lds R16,Kb_ScHead ldi ZL,Kb_ScData_Lenght lds R2,Kb_ScTail sub R2,R16 breq PSC4 ;T=H, akkor Kb_ScData_Lenght hely van brcs clr dec cpi
PSC2 ZL add ZL ZL,1
brcs
PSCExitwError
;ha <1 nincs elg
clr ldi
R2 ZL,low(Kb_ScData)
;Pointer to the
ldi add adc
ZH,high(Kb_ScData) ZL,R16 ZH,R2
;add address
lds
R2,ResevedBits
;ez elobb vet 8
st
Z,R2
;eltarolva a
inc cpi brcs clr
R16 R16,Kb_ScData_Lenght PSC3 R16
PSC2: PSC4:
ZL,R2 ;ZL = hely a
bufferben hely! Hiba!
buffer (FIFO)
offset.. kb_data bit scankod bufferben ;Pointer>Len ;ha igen
Pointer=0, atfordult PSC3: ScanCexit:
sts
Kb_ScHead,R16
clc ret
; Nincs hiba
PSCExitwError:
;ide jon az, ha a scankod bufferben
nincs hely! ;de mi van ha nincs hely, es meg mindig megszakitasban vagyunk!! sec ret
;Hiba!!
;************************************** ; FIFO Manager folytatasa ; mar nem interruptbol megy!!!! ; Out: c=0, R0 = scankod ; Get_ScanC: clr R0 lds R18,Kb_ScTail lds R19,Kb_ScHead cp R19,R18 breq ScanErrExit
;nincs adat a
bufferben ldi
ZL,low(Kb_ScData)
;Pointer to the
ldi add adc
ZH,high(Kb_ScData) ZL,R18 ZH,R0
;add address
ld inc cpi brlo clr
R0,Z R18 R18,Kb_ScData_Lenght ScanCbx R18
;Circle around
sts clc ret
Kb_ScTail,R18
rxbuffer (FIFO)
offset...
to the first buffer pos. ScanCbx:
;Valid Char
ScanErrExit:
sec
;no char
in buff, or error ret
;*************************************************** ;* Send data to keyboard ;* start bit sending ; Kb_StartSend: lds R16,Kb_BitCounter dec R16 sts Kb_BitCounter,R16 cpi R16,2 breq SendParitas cpi R16,1 breq SendStopbit cpi R16,0 breq GetAckBit
lds lds ror sts brcs CBI
R16,kb_SendByte R2,Kb_Paritas R16 kb_SendByte,R16 send1bit PS2_DATPort,KDATA
inc rjmp
R2 kb_sendbitx
SBI
PS2_DATPort,KDATA
;send
bit 0
send1bit: ;send
bit 1 kb_sendbitx:
;
uj adatbit a porton sts
Kb_Paritas,R2
;uj
paritas eltarolasa ret
;************************************** ;* Paritas bit kuldese SendParitas: lds R16,Kb_Paritas ror R16 brcc send1paritas CBI PS2_DATPort,KDATA
;send
ret send1paritas: SBI
;paritas
bit 0
PS2_DATPort,KDATA
bit = 1 ret
;*************************************** ;* Stop bit kuldese ; SendStopbit: CBI PS2_DATPort,KDATA CBI PS2_DATDIR,KDATA
;DATA pin tre-
stated external pull-up!! ret
;************************************** ;* Get Ack bit from keyboard ; GetAckBit: ldi R16,11
;1 start
+8 adat +1 par +1 stop sts
Kb_BitCounter,R16
;a kovetkezo
ldi
R16,Low(Kb_Rec_Start)
;Vissza allunk
sts ldi sts
PtrINT0+0,R16 R16,High(Kb_Rec_Start) PtrINT0+1,R16
adat vetelehez
adat vetelre
bld R16,0 ;R16=ack bit tst R16 brne Kb_SendAckErr ret Kb_SendAckErr: ;ide jon az az eset amikor nem kuldott ack-ot ;es amost mit kezdjek vele, kuldjem ujra az egeszet??? ret
;*************************************************** ;** Parancskuldes kezdemenyezese a keyboard fele ;** In : R0 data to keyboard ;** Out: c=0 sikeres kuldes meginidtasa ;** c=1 sikertelen kuldes TrySendCmd: lds
R2,kb_ComStat
;Stop tilalom
van-e? tst breq sec NormalUzem: ret
R2 TrySend
TrySend: sts sts sts sts sts
jumptabla+0,ZL jumptabla+1,ZH kb_CmdBuffer+0,R16 kb_CmdBuffer+1,R17 kb_CmdBuffer+2,R18
ldi sts clr sts
R16,0x33 kb_Status,R16 R16 kb_lastAction,R16
clr sts
R16 kb_ResendCnt,R16
NextComdData: clr lds
R16 R2,kb_lastAction
;0. byte kuldese
lesz NewParam:
;a kovetkezo
byte kuldese ldi ldi add adc
ZL,low(kb_CmdBuffer) ZH,high(kb_CmdBuffer) ZL,R2 ZH,R16
ld sts
R0,Z kb_SendByte,R0
in andi OUT
R16,GIMSK R16,0b10111111 GIMSK,R16
;6. = 0 EXT INT0
inactive ;hogy ne okozzunk megszakitas ;mikor leallitjuk a CLK vonalat SBI
PS2_CLKDIR,KCLK
;CLK push-pull
ldi ldi
ZL,low(wait100us/5) ZH,high(wait100us/5)
;100us idozito
sbiw brne
nop ZL,1 w100us
Low nop
konstans w100us:
nop
;[1] ;[2] ;[2] ;itt mart eszre
kellett vegye ;hogy adni akarunk ldi
R16,Low(Kb_StartSend)
;Most parancs
sts ldi sts
PtrINT0+0,R16 R16,High(Kb_StartSend) PtrINT0+1,R16
ldi sts
R16,3 kb_ComStat,R16
;Stop tilalom
ldi
R16,11
;1 start +8 adat
sts
Kb_BitCounter,R16
clr sts
R16 Kb_Paritas,R16
;paritas
SBI
PS2_DATDIR,KDATA
;DATA pin push-
nop CBI
PS2_CLKDIR,KCLK
;CLK tre-state
ldi
R16,64
;INT0 IRQ flag
out
GIFR,R16
in ori OUT
R16,GIMSK R16,64 GIMSK,R16
kuldes lesz
lesz az adas allat...
+1 par +1 stop +1 ack
szamolashoz kell
pull low
ismet
torlese
;6. = 1 EXT INT0
ujra aktive clc ret
;jump tablak ;********************** ;* Reset keyboard ;* In: R17,R18,R19 parameter ahol kell ;* Out: status ; kb_CMD_Reset: ldi R16,KEYBOARD_RESET kb_CMD_single: ldi ZL,low(Egyvalasz) ldi ZH,high(Egyvalasz) rjmp TrySendCmd
kb_CMD_ALLMakeBrake: ldi R16,SET_ALL_TYPEMATIC_MAKE_BREAK ldi ZL,low(CsakACKkell) ldi ZH,high(CsakACKkell) rjmp TrySendCmd kb_CMD_Echo: ldi ldi ldi rjmp kb_CMD_SetLEDs: andi
R16,KEYBOARD_ECHO ZL,low(StoreResult) ZH,high(StoreResult) TrySendCmd
R17,0b00111111
;csak az
also 6 bit kell -> 6 LEDek lds andi or sts ldi param1: ldi rjmp
R16,kb_SWStatus R16,0b11000000 R16,R17 kb_SWStatus,R16 R16,SET_KEYBOARD_INDICATORS ldi ZL,low(EgyParameter) ZH,high(EgyParameter) TrySendCmd
kb_CMD_SetSpeed: ldi rjmp
R16,SET_KEYBOARD_TYPEMATIC param1
kb_CMD_ReadID: ldi ldi ldi rjmp
R16,READ_KEYBOARD_ID ZL,low(ketparamjon) ZH,high(ketparamjon) TrySendCmd
; ************************************************************* ;* subrutinok a keyboard parancsok vegrehajtasahoz ; CsakACKkell: cpi R16,ACKNOWLEDGE ldi R16,ST_Success breq StoreResult ldi R16,ST_Unsuccess rjmp StoreResult
Egyvalasz:
cpi breq
R16,ACKNOWLEDGE nyugtamegjott
ldi
R16,ST_ACKnotreseived
StoreResult: ldi ldi sts sts Alaphelyzebe: ldi sts
ZL,low(NormalUzem) ZH,high(NormalUzem) jumptabla+0,ZL jumptabla+1,ZH sts kb_Status,R16 R16,255 kb_lastAction,R16
;vissza anormal
R16 kb_ComStat,R16
;Stop tilalom
mukodesre clr sts feloldva! ret nyugtamegjott: ldi ldi sts sts ret
EgyParameter: cpi breq ldi rjmp Elsonyugtaok: lds
ZL,low(StoreResult) ZH,high(StoreResult) jumptabla+0,ZL jumptabla+1,ZH
R16,ACKNOWLEDGE Elsonyugtaok R16,ST_ACKnotreseived StoreResult R16,kb_lastAction
byte kuldese inc sts ldi ldi sts sts rjmp
R16 kb_lastAction,R16 ZL,low(CsakACKkell) ZH,high(CsakACKkell) jumptabla+0,ZL jumptabla+1,ZH NewParam
ketparamjon: sts rjmp
http://avr-asm.tripod.com/kbdps2.html (1 of 2)1/20/2009 9:13:24 PM
kb_Status+1,R16 nyugtamegjott
;a kovetkezo
16 BIT MATH (AVR 202)
Programming the AVR Microcontrollers in Machine Language
AVR << Prev | Ring Hub | Join | Rate| Next >> © WebRing Inc.
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Lowvoltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/kbdps2.html (2 of 2)1/20/2009 9:13:24 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AT KEYBOARD PROGRAM 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1
Below is some assembly code I wrote for the mega128 last fall. It worked but has not been tested extensively. I did a look-up table to give me a ASCII character for the corresponding keyboard scan code.
TUTORIAL #2 ; ; ; ; ;
TUTORIAL #3 MATH 200 MATH 200b MATH 201
\keyboard4a\keyboard4a.asm ; Clock frequency:
MATH 202 MATH 32X
; ; ; The purpose of this project is to: ; 1. Read a keyboard scan code using the keyboard
DIV16 XX
DIV 3216
SCL and SDA lines
SQRT16
MATH 202 DEC ASCII
COPY 102
SER EPROM
VFX SMIL
;
transmit the equivalent ASCII code for that key
;
if the key is held down it will keep
;
If it is 0xF0 then it will transmit the word
"Break" and then wait for ; ;
the next scan code 4. Only the alphabet and number keys are decoded in
this code. The Ctrl, Alt, ;
Shift, Enter, Function, etc. keys are not
;
will result in a capital letter or a "?" being
;
look at the table at the end of the code and get
decoded. Hitting one of those keys sent via the USART0. You can an idea of what I mean. ; ; This project will use code from previous projects as
DFLASH AT45 FLASH CARD
"Basic Assurance Test complete" via USART0 3. Determine if the scan code is 0xF0, if it is not
transmitting that ASCII character).
LPM 108 EPROM 100
; ;
(in other words,
AVG8 222 FFT7
2. Determine if the scan code is 0xAA in which case
it will look up and
INT ASCII HX2ASC
; it will transmit
FLOAT 128
MATH 202
3.6864MHz (via STK500 onboard
oscillator)
MATH YX
DIV 24 24
Date: 9/26/03 By: Stephen L. Nuttall Hardware platform; STK500/STK501 Software platform: Atmel Studio 4.07 File location: C:\My Documents\AVR Projects
well as code ; from keyboard5.asm, keyboard5a.asm and keyboard5b. asm.
VFX MEM
ISP 2313
; .nolist .include "m128def.inc" .list ; .def temp = R16 .def bitcntr = R17 .def keydata = R18 .def temphi = R19 .def templo = R20 .def flags = R21 .def parity = R22 ; .org 0x0000 jmp RESET
ISP 1200
.org
SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
; Reset Handler
0x0046
AVR SPI I2C 300 I2C 302
I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
ADC 10B ADC 400
out ldi out ser out out ldi
SPH,temp temp, low(RAMEND) SPL,temp temp ; PortB = DDRB,temp ; all outputs PORTB,temp ; PortB LED's = off temp,0b11111100 ; PortD0 and PortD1 =
inputs, all
TEA ADC 128
; Main program start temp, high(RAMEND) ; Stack pointer = top
of internal SRAM
I2C TWI26
ETHNET 8019
RESET: ldi
out com
DDRD,temp temp
; other pins = output ; temp now becomes
out
PORTD,temp
0b00000011 ; PortD0 and PortD1 have
pullups ;
enabled, remaining pins
output 0's
ADC 401 THERM 232
LCD HD44
MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP
ldi sts
templo,0x17 UBRR0H,temphi
; "sts" is used because
UBRR0L,templo
; of "out" ; UBRR0L is within reach
out of "out"
; *********************************************************************************** ; USART ; Frame format = 1 start bit, 8 data bits, no parity bit, 1 stop bit (8,N,1) ; ; Registers UCSR0B and UCSR0C are already setup for this Frame format at RESET. ; ; No programming action is required for the above registers...if any settings need ; to be changed I need to remember that UCSR0C cannot be accessed via the OUT ; instruction, use STS instead. ; ; *********************************************************************************** ; init: clr bitcntr ; initialize appropriate registers clr keydata clr parity clr flags
AVR BUTTERFLY AVR BOOK
; setup BAUD rate for
UBRR0H is not within reach
LCD44 2313 KBD 240
temphi,0x00
9600 @ 3.6864MHz
IRD 410
LCD 2313
ldi
main: call
sclhi
; make sure SCL is high to
call inc cpi breq cpi brlt breq
scllo bitcntr bitcntr,0x01 startbit bitcntr,0x0A databit paritybit
; look for SCL going low
cpi breq
bitcntr,0x0B stopbit
start off
; is this a Start bit? ; yes, go check Start bit ; is this a Data bit? ; yes, go get Data bit ; no, go get and calculate
parity ; is this a Stop bit ; yes, go check Stop bit
startbit: sbic PIND,PD1 rjmp starterr rjmp main
; Start bit = 0? ; no...go send error message ; yes..go look for data bits
databit: bclr sbic bset brbc
; pre-clear Carry flag ; SDA = 0? ; no, then set Carry flag ; now check status of Carry
0 PIND,PD1 0 0,rotate
flag for parity chk in push inc pop out rotate: ror
flags,SREG flags parity flags SREG,flags
; save ; status register ; for parity check later ; restore ; status register
keydata
; rotate contents of
Carry flag into keydata rjmp
main
; go get another bit
; ; Parity checking..... ; this routine is based on Odd Parity; meaning if there are an even number of 1's ; in the data byte the Parity bit will be 1 so that an odd number of 1's now exist, ; if there are already an odd number of 1's then the Parity bit will be 0. ; ; I will keep track of Parity by incrementing the parity register once for every 1 ; that is received on the data line. If there are an odd number of 1's the lsb of ; parity register will always be 1 ; ; Therefore, if the lsb of the parity register = 1 (odd number of 1's) then the ; Parity bit should be 0 (there were an odd number of 1's already. This condition ; can be checked by exclusive ORing those 2 bits. As long as they are opposite ; the parity checks out good. ; paritybit: in flags,PIND ; SDA = PD1 ror flags ; rotate SDA into bit 0 position andi
flags,0x01
andi
parity,0x01
; clear all but bit 0
position ; again, clear all but
bit 0 eor
flags,parity
; exclusive-or to find
out if lsb's of flags ; breq
parerr
rjmp
main
and parity the same ; report error if they are
the same
stopbit: sbis rjmp cpi
; return and get stop bit now
PIND,PD1 stoperr keydata,0xAA
; SDA = 1? ; no, go report error ; BAT message from
keyboard? brne
chkforbrkcode
; no, check for next code
of interest ldi
ZH,high(2*batmsg)
; pre-load BAT message
address ldi call rjmp
ZL,low(2*batmsg) sendmsg ; go send message init ; go look for another key
press chkforbrkcode: cpi keydata,0xF0 brne sendkeychar
; Break code (0xF0):? ; no, go send ASCII key
code ldi
ZH,high(2*brkmsg)
; yes, now pre-load
Break message address ldi call rjmp
ZL,low(2*brkmsg) sendmsg ; go send message init ; look for another keypress
starterr: ldi
ZH,high(2*sterrmsg)
ldi
ZL,low(2*sterrmsg)
; load high part of
message address in ZH ; load low part of
message address in ZL call
senderrmsg
parerr: ldi
ZH,high(2*parerrmsg); load high part of
message address in ZH ldi
ZL,low(2*parerrmsg)
; load low part of
message address in ZL call
senderrmsg
stoperr: ldi
ZH,high(2*sperrmsg)
; load high part of
message address in ZH ldi
ZL,low(2*sperrmsg)
; load low part of
message address in ZL call
senderrmsg
;********* Subroutines ************** scllo: sbic rjmp ret
PIND,PD0 scllo
; PD0(SCL) = 0? ; no...continue checking SCL ; yes...return main program
sclhi: sbis rjmp ret
PIND,PD0 sclhi
; PD0(SCL) = 1? ; no...continue checking SCL ; yes..return to main
getsda: bclr sbic bset ret
0 PIND,PD1 0
; pre-clear the Carry flag ; check state of SDA ; if SDA = 1, set Carry flag ; if SDA = 0. Carry flag is
program
already cleared ; ****************************************************************************** senderrmsg: ; the calling program will have to load ZH and ZL with the appropriate message ; address sbi
UCSR0B,TXEN0
; enable transmitter,
TXEN = 1 getmsg: lpm
R0,Z+
; retrieve character from
tst
R0
; is it the last
breq out
loop UDR0,R0
call
chkxmitend
rjmp
getmsg
program memory character? ; yes..then loop forever ; no...transmit
character ; wait for transmit to
finish
loop: cbi rjmp
; get next character
UCSR0B,TXEN0 loop
; disable transmitter ; program stops here when
error occurs, user ;
will have to reset the
STK500 and try again ; ****************************************************************************** sendmsg: ; the calling program will have to load ZH and ZL with the appropriate message ; address sbi
UCSR0B,TXEN0
; enable transmitter,
TXEN = 1 getmsg1: lpm
R0,Z+
; retrieve character from
R0
; is it the last
program memory tst character? breq out
continue UDR0,R0
call
chkxmitend
; yes..then loop forever ; no...transmit
character ; wait for transmit to
finish rjmp getmsg1 continue: cbi UCSR0B,TXEN0 ret
; get next character ; disable transmitter
; ****************************************************************************** sendkeychar: sbi
UCSR0B,TXEN0
; enable transmitter,
ldi
ZH,high(2*ascii)
ldi
ZL,low(2*ascii)
add
ZL,keydata
TXEN = 1 ; load high part of key
character address in ZH ; load low part of key
character address in ZL ; add keydata offset to
ZL register brcc
getchar
inc
ZH
; if no carry, load key
character in R0 ; if there is a carry,
increment ZH register getchar: lpm
; load appropriate key
character into R0 out
UDR0,R0
call
chkxmitend
; no...transmit
character ; wait for transmit to
finish cbi ret
UCSR0B,TXEN0
; disable transmitter
; ****************************************************************************** chkxmitend: sbis UCSR0A,UDRE0
; data register empty flag
= 1 rjmp ret
chkxmitend
; no...keep checking ; yes..continue with program
;************* MESSAGES ****************************************************** batmsg: .db
"
brkmsg: .db
"
Basic Assurance Test complete
Break
",0
",0
; ************* ERROR MESSAGES ************************************************ sterrmsg: .db "Start Bit Error",0 parerrmsg: .db "Parity Bit Error" .db 0,0 sperrmsg: .db "Stop Bit Error" .db 0,0 ; ************ KEY CHARACTERS ************************************************ ascii: ; 0x00 - 0x0F .db '?','F','?','F','F','F','F','F','?','F','F','F','F','T','`','?' ; 0x10 - 0x1F .db '?','L','L','?','L','q','1','?','?','?','z','s','a','w','2','?' ; 0x20 - 0x2F .db '?','c','x','d','e','4','3','?','?','S','v','f','t','r','5','?' ; 0x30 - 0x3F .db '?','n','b','h','g','y','6','?','?','?','m','j','u','7','8','?' ; 0x40 - 0x4F .db '?',',','k','i','o','0','9','?','?','.','/','l',';','p','-','?' ; 0x50 - 0x5F .db '?','?',''','?','[','=','?','?','C','R','E',']','?','\','?','?' ; 0x60 - 0x6F .db '?','?','?','?','?','?','B','?','?','1','?','4','7','?','?','?' ; 0x70 - 0x7F .db '0','.','2','5','6','8','E','N','F','+','3','-','*','9','S','?' ; 0x80 - 0x83 .db '?','?','?','F'
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is http://avr-asm.tripod.com/kbd128.html (1 of 2)1/20/2009 9:13:59 PM
16 BIT MATH (AVR 202)
indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/kbd128.html (2 of 2)1/20/2009 9:13:59 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
PS2 KEYBOARD EMULATOR FOR 8515 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304
; *********************************************************************** ;* ;* Number : **.** ;* File Name :"Main.asm" ;* Title :Keymatrix interface to AT PS/2 ;* ;* Date (Orig.) :2001.09.13. ;* Date (Last) :2001.10.14. ;* Version :1.1.0 ;* Support telephone :+36-30-9541-658 ;* Support fax :+36-30-9809-372 ;* Support E-mail :[email protected] ;* Target MCU :AT90S8515 ;* ;* DESCRIPTION ;* kezeli a kovetkezo eszkozoket: ;* - 84 key ;* - 6 LED ;* - 16,11,11x Jacksly?? ;* - PS/2 style interface to AT or MARGOR CP-01 ;* ;* AT90S8515 PLCC Pin discriptions ;* ;* ROW0 T0 (PB0) VCC ;* ROW1 T1 (PB1) (PA0) AD0 D0 ;* ROW2 AIN0 (PB2) (PA1) AD1 D1 ;* ROW3 AIN1 (PB3) (PA2) AD2 D2 ;* ROW4 SS (PB4) (PA3) AD3 D3 ;* LED3 * MOSI (PB5) (PA4) AD4 D4 ;* LED4 * MISO (PB6) (PA5) AD5 D5 ;* LED5 * SCK (PB7) (PA6) AD6 D6 ;* RESET (PA7) AD7 D7 ;* LED0 RxD (PD0) ICP ;* LED1 TxD (PD1) ALE ;* KCLK INT0 (PD2) OC1B ;* KDATA INT1 (PD3) (PC7) A15 D8 ;* LED2 (PD4) (PC6) A14 D9 ;* ROW5 OC1A (PD5) (PC5) A13 D10 ;* ROW6 WR (PD6) (PC4) A12 D11 ;* ROW7 RD (PD7) (PC3) A11 D12 ;* XTAL2 (PC2) A10 D13 ;* XTAL1 (PC1) A9 D14 ;* GND (PC0) A8 D15 ;* ;* Quarc: f=3.6864 MHz (T=0.27126 us) ;* ; *********************************************************************** .include "8515def.inc"
UART 305 UART 128 UART BUFF
;**********************!!!!!!!!!!!!!!!!!!!!!! ***************************
USB 232
;* R15 regisztert modositani tilos! ;* Atjaro az interrupt rutinok es a foprogram kozott!!!! ; 0. = 1 ismetles kell a
AVR ISP ISP 2313 ISP 1200
bill.nyomas utan, Timer lejart
AVR SPI I2C 300
;**********************!!!!!!!!!!!!!!!!!!!!!! ***************************
I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC
; ************************************************************************** ;* Const Def .EQU BaudRate=23 ;23 - 9600 @3.6864MHz
ETHNET 8019 TEA
.EQU
T0Freq=227
;220
@1.8432MHz/1024 = 50Hz ;184 @3.6864MHz/1024 = 50Hz ;220 @7.3728MHz/1024 = 200Hz ;227 @7.3728MHz/64 =
ADC 128 ADC 10B ADC 400
4000Hz/250us
ADC 401 ;238 @3.6864MHz/1024 = 200Hz ;250 @3.6864MHz/1024 = 600Hz
THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
.EQU
ONESEC=200
;for 1s
.EQU
FlashPeriod=1000
;LEDek villogasi
periodusa ~250us egysegekben
MUX 242 KBD PS2 KBD PC/128
; *************************************************************************** ;***** Hardware Abstraction Layer
PS2 EMU
.EQU DTLo_PORT = DDRA .EQU DTHi_PORT = ;2x8 bit adat port Pull-upos kell
BOOT MG8 BOOT DR8
DDRC
ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
LED3
PWM 10K
LED4
ENCODE STH-11
.EQU .EQU .EQU .EQU .EQU .EQU
Row0 = 0 Row1 = 1 Row2 = 2 Row3 = 3 Row4 = 4 LED3 = 5
;PortB kiosztasa
.EQU
LED4 = 6
;
.EQU
LED5 = 7
;
.EQU .EQU
LED345 = PORTB Row01234 = PORTB
.EQU
LED0
= 0
.EQU
LED1
= 1
;
.EQU
LED2
= 4
;
.EQU .EQU .EQU
Row5 Row6 Row7
= 5 = 6 = 7
.EQU .EQU
LED012 = PORTD Row567 = PORTD
;
LED5
ATMEL CORP AVR BUTTERFLY AVR BOOK
;PortD kiosztasa
LED0 LED1 LED2
; ****************************************************************************** ;**** VARIABLES .DSEG Flag1: .BYTE 1 ;Flagbitek ;2 = paros/paratlan szamlalo led villogtatashoz ;1:0 = scan mode 01 = scan1, 10 = scan2, 11 = scan3 CNT1L: CNT1H:
.BYTE 1 .BYTE 1
;software Timer
CNT2L: CNT2H:
.BYTE 1 .BYTE 1
;LED villogtatas
freki
KeyHead: .BYTE 1 KeyTrail:.BYTE 1
;Bill. puffer eleje ;Bill. puffer vege
WTime:
.BYTE 2
;Bill.nyomas utan a
WRep:
.BYTE 2
;Bill.nyomas utan a
varakozas ido ismetlesi ido PS2Flag: .BYTE 1
;PS2 flag csak az int.
rutin hasznalhatja ;3. = 1 Parameterre var, komunikacio kozben vagyunk ;2. = 1 Request resend ;1. = 1 Resend last data to host ;0. = 1 Send ACK PS2NextA:.BYTE 2
;PS2 program cim, ahova a
LastSend:.BYTE 1 RepChar: .BYTE 1
;PS2 Utoljara kuldott kod ;karakter sorszama amit
StatLEDs:.BYTE 2
;STAUS LEDek
kovetkezo int ugrik
ismetelni kell
allapota eg /
nem eg ;masodik byte a villogas mask byte-ja
ParamErr:.BYTE 1
;parameterre max 4ms ideig
var utana hiba
.EQU KeyBuff:
KeyBuffLen = 17 .BYTE KeyBuffLen
.EQU bill.,de csak 119 db billenyut kell kezelni Matrix: allapota
;Transmit key-buffer
KeyCount = 128
;max 128
.BYTE KeyCount
;Keys
; ************************************************************************************** .ESEG .db "MAGOR HI-01 Keyboard-matrix Controller by VFX. V1.1.0 [orig. 2001.09.16] " .db "Last Upd. [2001.10.14] Info: [email protected] Data area>>" ; ***************************************************************************** ;**** I N T E R R U P T S ;**** ; ***************************************************************************** .CSEG rjmp RESET ; Reset Handler rjmp EXT_INT0 ; IRQ0 Handler rjmp EXT_INT1 ; IRQ1 Handler rjmp TIM1_CAPT ; Timer1 Capture Handler rjmp TIM1_COMPA ; Timer1 CompareA Handler rjmp TIM1_COMPB ; Timer1 CompareB Handler rjmp TIM1_OVF ; Timer1 Overflow Handler rjmp TIM0_OVF ; Timer0 Overflow Handler rjmp SPI_INT ; SPI Transfer Complete Handler rjmp UART_RXC ; UART RX Complete Handler rjmp UART_DRE ; UDR Empty Handler rjmp UART_TXC ; UART TX Complete Handler rjmp ACI_INT ; Analog Comparator Handler
;********************* EXT_INT0: RETI EXT_INT1: RETI TIM1_CAPT: RETI ;************************ ;* Key Deleay & Rep Time ;************************ TIM1_COMPA: PUSH ZL IN ZL,SREG PUSH ZL ldd out ldd out
ZL,Y+WRep+1-RAMSTRT OCR1AH,ZL ZL,Y+WRep+0-RAMSTRT OCR1AL,ZL
;rep. timer
ldi or
ZL,1 R15,Zl
;timer
POP OUT POP RETI
ZL SREG,ZL ZL
beallitasa
lejart ismetles mehet Flag
;** TIM1_COMPB: RETI TIM1_OVF: RETI ;********************* ;* RealTime Clock Int ;********************* ;* TIM0_OVF: PUSH ZL PUSH ZH IN ZL,SREG PUSH ZL LDI OUT
ZL,T0Freq TCNT0,ZL
LDD LDD OR BREQ LDD SBIW STD STD
ZL,Y+CNT1L-RAMSTRT ZH,Y+CNT1H-RAMSTRT ZL,ZH TIM_01 ZL,Y+CNT1L-RAMSTRT ZL,1 Y+CNT1L-RAMSTRT,ZL Y+CNT1H-RAMSTRT,ZH
LDD LDD OR BREQ LDD SBIW STD STD
ZL,Y+CNT2L-RAMSTRT ZH,Y+CNT2H-RAMSTRT ZL,ZH TIM_02 ZL,Y+CNT2L-RAMSTRT ZL,1 Y+CNT2L-RAMSTRT,ZL Y+CNT2H-RAMSTRT,ZH
;Reload
Timer
TIM_01:
TIM_02: OUT POP POP RETI
POP ZL SREG,ZL ZH ZL
;******************** ;* SPI Int Handle ;******************** SPI_INT: RETI UART_RXC: RETI UART_DRE: RETI UART_TXC: RETI EPR_INT: RETI ACI_INT: RETI
; ********************************************************************** ;* Iclude files .include .include .include
"keyb.asm" "ps2.asm" "EEprom.asm"
; ********************************************************************** ;* RESET ; ********************************************************************** RESET: CLI ;GLOBAL INTERRUP DIS. clr R15 ;Flags!!!
ldi out ldi out
r16, high(RAMEND) SPH,r16 r16, low(RAMEND) SPL,r16
;setup stack
LDI
R16,0b00101010
;Sleep enable, Idle mode,
OUT
MCUCR,R16
;7. =1 SRE External SARAM
INT0, INT1 fall-edge sens. Enabled, Alternate Function ;6. =1 SRW External SRAM WaitStates Enabled ;5. = 1 Sleep Enable ;4. = 0 SLEEP => Idle Mode ; 1 SLEEP => Power Down Mode ;3:2 = Inerrupt Sense Control for INT1 ; 00 ; 01 ; 10 ; 11 ;1:0
-> Low Level INT1 -> Reserved -> Falling Edge INT1 -> Rising Edge INT1 = Inerrupt Sense
; ; ; ;
-> -> -> ->
Control for INT0 00 01 10 11
Low Level INT0 Reserved Falling Edge INT0 Rising Edge INT0
LDI OUT
R16,0b00000000 GIMSK,R16
;INT0, INT1 Disabled ;7. = 1 EXT INT1 ACTIVE ;6. = 1 EXT INT0 ACTIVE
LDI OUT
R16,0b01000010 TIMSK,R16
LDI LDI
YL,LOW(RAMSTRT) YH,HIGH(RAMSTRT) ;BAZIS 'Y' +0
;7. ;6. ;3. ;1.
= = = =
1 1 1 1
TC1 TC1 TC1 TC0
OWRF EN. * COMP MATCH EN. INP CAPTURE EN. OWRF EN. *
; ************************************************************************ ;*Prot/Keymatrix and Hardware Init ;* ldi STD
R16,255 Y+RepChar-RAMSTRT,R16
clr
R17
out out
DTLo_PORT,R17 DTLo_PORT+1,R16
;Lower 8
out out
DTHi_PORT,R17 DTHi_PORT+1,R16
;Higher 8
out out
DDRB,R16 DDRB+1,R16
;Row0..4
ldi
R17,255-(1< OC1 not connected
;
;
ismetelhetettlen karakter sorszam
data bit Input & Pull up
data bit Input & Pull up
output & H, LED3,4,5 Nem vilagit
Disconnect OC1A connected PWM
;
01 => OC1 not
;
10 => OC1 non-inv
;
11 => OC1 inverted
; Togle OC1A
PWM
; Clear OC1A ; Set OC1A ;5:4 00 => OC1 not
connected
""
connected PWM
OC1B ;
01 => OC1 not
;
10 => OC1 non-inverted
;
11 => OC1 inverted
;1:0 ; ; ;
00 01 10 11
""
""
PWM
""
LDI OUT
R17,0b00001000 TCCR1B,R17
=> PWM Disabled => 8 bit PWM => 9 bit PWM => 10 bit PWM
;7. = 0 Input Capture Noise
Canceller Disabled ;6. = 0 InputCapture ICP Falling edge ;3. = 1 Reset TC1 when copare match ;2:0 Clock ; 000 => ; 001 => ; 010 => ; 011 => ; 100 => ; 101 => ; 110 =>
select TC1 Stop Ck Ck/8 Ck/64 Ck/256 Ck/1024 External T1
Falling Edge ;
111 => External T1
rising Edge
;************************************ ;** Timer0 Init ***** ;** LDI R16,T0Freq OUT TCNT0,R16 ;megszakitas frekvenciaja LDI OUT
R16,0b00000011 TCCR0,R16
;TC0 Control Register ;2:0 Clock Select ; 000 -> Stop ; 001 -> CK ; 010 -> CK/8 ; 011 -> CK/64 ; 100 -> CK/256 ; 101 -> CK/1024 ; 110 -> External pin T0
falling edge ; 111 -> External pin T0 risinrg edge
SEI
;SET GLOBAL
INT EN.
CBI
LED012,LED0
;LEDx
CBI CBI CBI CBI CBI
LED012,LED1 LED012,LED2 LED345,LED3 LED345,LED4 LED345,LED5
ldi STD
R16,Low(ONESEC) Y+CNT1L-RAMSTRT,R16
ldi STD
R16,High(ONESEC) Y+CNT1H-RAMSTRT,R16
LDD or brne
LDD R16,Y+CNT1L-RAMSTRT R17,Y+CNT1H-RAMSTRT R16,R17 wait1
SBI
LED012,LED0
SBI SBI SBI SBI SBI
LED012,LED1 LED012,LED2 LED345,LED3 LED345,LED4 LED345,LED5
ldi
ZL,low(0)
STD ldi STD
Y+CNT2L-RAMSTRT,ZL ZH,high(0) Y+CNT2H-RAMSTRT,ZH
vilagit
;software
down counter, wait for 1s
wait1:
;LEDx nem
vilagit
;
led villogtatas kb 0.5s
; *********************************************************************** ; *********************************************************************** ;******** M A I N ******** ; ******** ******** ; *********************************************************************** WWW: ldi ZL,low(40) STD Y+CNT1L-RAMSTRT,ZL ldi ZH,high(40) STD Y+CNT1H-RAMSTRT,ZH Main: rcall
SLEEP PS2_Com
LDD LDD OR BRNE
ZL,Y+CNT2L-RAMSTRT ZH,Y+CNT2H-RAMSTRT ZL,ZH LEDkihagy
(FlashPeriod)
ldi ZL,low ;led villogtatas kb 0.5s STD Y+CNT2L-RAMSTRT,ZL ldi ZH,high(FlashPeriod) STD Y+CNT2H-RAMSTRT,ZH LDD ldi eor STD
R16,Y+Flag1-RAMSTRT R17,0b0000100 R16,R17 Y+Flag1-RAMSTRT,R16
rcall
Puts_LEDs
LDD cpi brne
R16,Y+CNT1L-RAMSTRT R16,0 Main
rcall
ScanMatrix
rcall rjmp
MakeScanC WWW
;
paros/paratlan bit valtas
LEDkihagy:
;
keymatrix beolvasasa a memoriaba
;* LEd 7 ;*
6
Puts_LEDs:
5 4 3 2 1 0 3P 2P 1P 3Z 2Z 1Z LDD andi
R16,Y+Flag1-RAMSTRT R16,4
;D0
ldi
R18,0b00000111
;
breq ldi
paros R18,0b00111000
;
= Paros/paratlan bit csak zoldek villognak
csak pirosak villognak paros:
LDD
R16,Y+StatLEDs+1-
RAMSTRT ;villogas mask = 1 villog and
R18,R16
LDD
R16,Y+StatLEDs+0-RAMSTRT
;
or com andi
R16,R18 R16 R16,0b00111111
;
mov rol rol andi mov andi or
R17,R16 R17 R17 R17,0b00010000 R18,R16 R18,0b00000011 R17,R18
;ez
in andi or out
R18,LED012 R18,0b11101100 R18,R17 LED012,R18
;
rol rol andi in andi or out
R16 R16 R16,0b11100000 R17,LED345 R17,0b00011111 R17,R16 LED345,R17
;
LED data = 1 villagit
inv. kell mert kozos anodosak a ledek
megy ki a PD portra, zold ledek
LED0,1,2 kikuldve
LED3,4,5 kikuldve ret
; *********************************************************************** ;* ;* File Name :"PS2.asm" ;* Title :PS/2 communication protocoll ;* ;* Date (Orig.) :2001.10.06. ;* Date (Last) :2001.10.12. ;* Version :1.0.10 ;* Support telephone :+36-30-9541-658 ;* Support fax :+36-30-9809-372 ;* Support E-mail :[email protected] ;* Target MCU :AT90S8515 ;* ;* DESCRIPTION ;* - PS/2 style communication to AT or MARGOR CP-01 ;* ;* CLK & DATA = H -> Two way communication ;* DATA = L -> PC (MAGOR) sends to Keyb ;* CLK = L -> PC (MAGOR) inhibits communiaction ; ************************************************************************** ;* Const Def
; *************************************************************************** ;***** Hardware Abstraction Layer .EQU .EQU
PS2_CLKPort = DDRD PS2_DATPort = DDRD
.EQU .EQU
KCLK = 2 KDATA = 3
; ****************************************************************************** ;**** VARIABLES .DSEG .EQU .EQU .EQU .EQU
NoError = RxF_Abort = TxBreak = Parity_Err=
0 2 3 4
;No Error ;Abort communication ;Abort Transmit ;Parity Error
; ****************************************************************************** .ESEG
; ****************************************************************************** .CSEG Init_PS2: CBI
CBI PS2_CLKPort,KCLK PS2_CLKPort+1,KCLK ;CLK pin tre-stated
external pull-up res!!
CBI
CBI PS2_DATPort,KDATA PS2_DATPort+1,KDATA ;DATA pin tre-
stated external pull-up res!! ldi STD STD
R16,0 Y+PS2NextA+0-RAMSTRT,R16 Y+PS2NextA+1-RAMSTRT,R16 ;nincs
STD
Y+PS2Flag-RAMSTRT,R16
aktiv komunikacio folyamatban
ret
; ****************************************************************************** ;** Communication between Host and Keyboard ;** ; ****************************************************************************** PS2_Com: sbis PS2_CLKPort-1,KCLK ret ;if clk pin low, comm. inhibit sbis PS2_DATPort-1,KDATA rjmp RxCommand ;if data pin low, HOST sends command/data
LDD
R16,Y+PS2Flag-RAMSTRT
;Request
andi breq ldi
R16,0b00000100 Ps2_C2 R16,0xFE
;RESEND
mov rcall
R1,R16 SendByte
;keres
brcs LDD
ResSendERR R16,Y+PS2Flag-RAMSTRT
;Request
andi STD ret
R16,0b11111011 Y+PS2Flag-RAMSTRT,R16
Resend?
Command
elkuldese
Resend flag torlese
Ps2_C2:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Resend last data? andi breq ldd
R16,0b00000010 Ps2_C0 R1,Y+LastSend-RAMSTRT
rcall brcs LDD
SendByte ResSendERR R16,Y+PS2Flag-RAMSTRT
;utoljara
kuldott karakter ismetleshez ;ujrakuldes ;Resend
flag torlese andi STD ResSendERR: ret
R16,0b11111101 Y+PS2Flag-RAMSTRT,R16
Ps2_C0:
LDD
;ha hiba
volt ujra kuldjuk R16,Y+PS2Flag-RAMSTRT
;
Send ACK flag active? andi breq ldi
R16,0b00000001 Ps2_C1 R16,0xFA
;Send ACK
mov rcall brcs
R1,R16 SendByte ResSendERR
;ha hiba
LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11111110
;Host Abort ;ACK flag
STD
Y+PS2Flag-RAMSTRT,R16
;
to HOST
van ujrakuldes lesz
torlove sikeresen elment komunikacio nincs ret Ps2_C1:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Parameterre var? andi breq
R16,0b00001000 Ps2_C3
;ha nem,
LDD
R16,Y+ParamErr-RAMSTRT
;parameterr
cpi
R16,20
;20*250us
brcs
Megidovan
;
LDD
R16,Y+PS2Flag-RAMSTRT
;
andi STD clr STD STD
R16,0b11110111 Y+PS2Flag-RAMSTRT,R16 R16 Y+PS2NextA+0-RAMSTRT,R16 Y+PS2NextA+1-RAMSTRT,R16 ;
STD ret
Y+ParamErr-RAMSTRT,R16
akkor hadmenjen
error counter>4ms -> igen, hiba inc R16 ido ~4..5ms idotullepes!!
Parameterre var bit torlese, nem varunk tovabb!
alapallapotba hozas! Megidovan:
Ps2_C3: LDD mov or
LDD ZL,Y+PS2NextA+0-RAMSTRT ZH,Y+PS2NextA+1-RAMSTRT R16,ZL R16,ZH ;ha nincs
breq
SendScan
komunikacio folyamatban ;akkor
kuldjunk scan kodot ijmp
;ugras a
komunikacios rutinra ;******************************************** ;** Send scan/fifo ;******************************************** SendScan: ldi ZL,Low(KeyBuff) ldi ZH,High(KeyBuff) LDD R0,Y+KeyHead-RAMSTRT LDD R16,Y+KeyTrail-RAMSTRT cp R0,R16 brne SendScn1 ret SendScn1: clr R0 add Zl,R16 adc ZH,R0 ld R1,Z inc R16 cpi R16,KeyBuffLen brcs SendScn2 clr R16 SendScn2: STD Y+KeyTrail-RAMSTRT,R16 ;uj pointer elmentve rcall brcc
SendByte NoSendErr
;nincs hiba
LDD
R16,Y+PS2Flag-RAMSTRT
;Resend
ori STD ret
R16,0b00000010 Y+PS2Flag-RAMSTRT,R16
siman elment flag beallitasa
NoSendErr:
;***************************************** ;** Send R1 to Host ;** C=1 hiba tortent R17= hibakod ;***************************************** SendByte: sbis PS2_CLKPort-1,KCLK rjmp SendByte
;wait for
clk=hi rcall rcall sbis rjmp
Delay45us Delay5us PS2_CLKPort-1,KCLK SendByte
sec std
Y+LastSend-RAMSTRT,R1
;utoljara
ldi
R17,TxBreak
;R17=
sbis
PS2_DATPort-1,KDATA
;Is Data
;wait 50us ;wait for
clk=hi
kuldott karakter Transmit break still hi? ret
;ha nem,
vissza R17 hibakod! rcall clr
Delay40us R0
rcall brcs
SendBit SendAborted
ldi mov mov clr rcall brcs dec brne
R16,8 R3,R16 R0,R1 R2 SendBit SendAborted R3 SendLoop ;paratlan paritas
mov rcall clr dec
R0,R2 SendBit R0 R0
rcall rcall rcall ldi
SendBit Delay15us Delay15us R17,NoError
;R0=0 start
bit
SendLoop:
inc R2 kell!!!!!???
;R0=255
stop bit =H
clc ret SendAborted:
ldi
R17,TxBreak
;
R17= Transmit break sec ret ;* C=1 break, C=0 normal transmit SendBit: ror R0 ;0. bit -> C brcc bit0 bit1: CBI PS2_DATPort,KDATA ; DATA pin H inc
R2
rjmp
bitn SBI
;paritas no
egyel bit0:
PS2_DATPort,KDATA
;
DATA pin L bitn: SBI rcall CBI rcall clc sbis sec
rcall Delay20us PS2_CLKPort,KCLK Delay40us PS2_CLKPort,KCLK Delay20us PS2_CLKPort-1,KCLK
;clk = L ;clk = H
;Clock=high? ;if no ->
C=1 ret
; ****************************************************************************** ;* R E C E I V E ;* ;* 80 us/bit device generated clock - host changes the Data line only when ;* the Clock line is low, and data is latched on the rising edge of the clock pulse ;* Host may abort transmission at time before the 11th clock pulse (acknowledge bit) ;* by holding Clock low for at least 100 microseconds. ;* ;* Uses:R1,R2,R17,R18 RxStream:
sbis
PS2_CLKPort-1,KCLK
;Wait for
Clock=high rjmp sbic
RxStream PS2_DATPort-1,KDATA
;Is Data
RxErr
;ha nem,
still low? rjmp akkor hiba! ;Read each bit (8 data bits, parity bit, and stop bit) as follows:
RxBitLoop:
clr clr ldi
R1 R2 R17,8
;data reg. ;parity reg. ;8 bit
rcall
RxBit
;R18-ban a
add
R2,R18
bit
http://avr-asm.tripod.com/ps2emu.html (1 of 4)1/20/2009 9:14:56 PM
16 BIT MATH (AVR 202)
ror
R18
;adatbit a
ror sbis rjmp
R1 PS2_CLKPort-1,KCLK RxAbort
;Clock=high? ;if no then
dec brne
R17 RxBitLoop
C flagben
Abort
;Read parity bit rcall
RxBit
;R18-ban a
inc
R2
;paratlan
sbis rjmp
;R2 = parity xor parity bit PS2_CLKPort-1,KCLK RxAbort
bit paritas kell!!??!!!????? eor R2,R18
;Read stop bit rcall
RxBit
;R18-ban a
bit sbis rjmp
PS2_CLKPort-1,KCLK RxAbort
sbis
PS2_DATPort-1,KDATA
;Is Data
RxErr1
;Data still
still low? rjmp equals 0? ;Output Acknowledge bit rcall
SendAckBit
;
rcall
Delay45us
;Delay 45
Acknowledge bit microseconds ;(to give host time to inhibit ;next transmission.) ldi
R17,0
;no error
ror
R2
;C-flagben
brcs ret
RxParErr
ldi
R17,Parity_Err
flag a parity ;R1 =
reseived data
RxParErr:
;Parity
Error sec ret RxAbort:
;C flag =0
ldi sec ret
R17,RxF_Abort
;Abort ;C flag =0
;*Keep clocking until Data=1 then generate an error RxErr1:
rcall RxBit PS2_DATPort-1,KDATA
sbis
;Is Data
still low? rjmp akkor hiba! until Data=1 then generate an error
RxErr1 ;ha nem, ;Data still equals 0? Keep clocking
RxErr: ret ;Read a bit RxBit: SBI rcall CBI rcall clr sbic ldi
rcall Delay20us PS2_CLKPort,KCLK Delay40us PS2_CLKPort,KCLK Delay20us R18 PS2_DATPort-1,KDATA R18,1
;clk = L ;clk = H
;R18 a
beolvasott adatbit ret ;Send the acknowledge bit SendAckBit: rcall Delay15us SBI PS2_DATPort,KDATA rcall Delay5us SBI PS2_CLKPort,KCLK rcall Delay40us CBI PS2_CLKPort,KCLK rcall Delay5us CBI PS2_DATPort,KDATA ret
;data = L ;clk = L ;clk = H ;data = H
; ****************************************************************************** ;* Delayxxus ;* ;*rcall [3] + wait [xx] +ret [4] = Delay ;* @7.3728MHz ;* 45 us [332cycl ;* 40 us [296cycl ;* 20 us [148cycl ;* 10 us [74cycl] ;* 5 us [37cycl] Delay45us: ldi R16,104 ;[1] 104*3+10 cycl rjmp DelayLoop ;[2] Delay5us: ldi R16,9 ;[1] 9*3+10 cycl rjmp DelayLoop ;[2] Delay15us: ldi R16,34 ;[1] 34*3+10 cycl rjmp DelayLoop ;[2] Delay20us: ldi R16,46 ;[1] 46*3+10 cycl rjmp DelayLoop ;[2] Delay40us: ldi R16,96 ;[1] 96*3 cycl DelayLoop: dec R16 ;[1] brne DelayLoop ;[1/2] ret ;[4]
;******************************************* ;** Host request to send... receive data ;** ;******************************************* RxCommand: LDD ZL,Y+PS2NextA+0-RAMSTRT LDD ZH,Y+PS2NextA+1-RAMSTRT mov R16,Zl or R16,ZH breq NewCommand ijmp ;ha nem uj, akkor ugras a vegrehajtasra NewCommand: rcall
RxStream
;Read data
R1, C=1 hiba, R17 hibakod brcc
RxComNoErr
LDD
R16,Y+PS2Flag-RAMSTRT
ori STD NoValidComm:
R16,0b00000100 Y+PS2Flag-RAMSTRT,R16 ret
RxComNoErr: ldi
ZL,Low(2*ComTab)
ReqResend:
;Host read
error Resend needed
;uj parancs
jott ldi
ZH,High
(2*ComTab) RxCommLoop: lpm tst
R0
;ha a tabla
breq cp breq adiw
NoValidComm R0,R1 HitComm ZL,2*(ComNex-ComTab)
;kovetkezo
rjmp
RxCommLoop
adiw
ZL,2
;pointerre
R1,R0 ZL,1
;low byte
ZH,R0 ZL,R1
;hi byte
vege es nincs parancs kihagyjuk
parancs
HitComm: mutat
lpm mov adiw lpm mov mov ijmp
;ugras a
parancs vegrehajtasara ComTab:
.dw
0xED,STATUS_IND ;Turns on/
ComNex: .dw .dw .dw .dw .dw .dw
.dw 0xEE,ECHO ;Echo 0xF0,ALT_SCAN ;Set Scan Code Set 0xF3,TYPE_RATE ;Set repeat rate 0xF4,KEN ;Enables keysacnning 0xF5,KDIS ;Disable keyscanning 0xF6,SET_DEF ;Set Default Value 0xF7,ALL_TYPE ;Set all keys -
.dw
0xF8,ALL_BREAK
;Set all keys -
.dw .dw
0xF9,ALL_MAKE 0xFA,ALL_MTB
;Set all keys - Make ;Set all keys -
.dw
0xFB,KEY_TYPE
;Set ket type -
.dw
0xFC,KEY_BREAK
;Set ket type -
.dw .dw .dw .dw .dw
0xFD,KEY_MAKE 0xFE,RESEND 0xFF,KRES 0xF2,READID 0x00
;Set ket type - Make ;Resend ;Reset Command ;Read ID Command ;ez az utolso sor!
rcall
RxStream
brcs ret
RD_Err
off LEDs
Typematic Make/Break
Typematic/Make/Break Typematic Make/Break
Read_Data:
;Read data
R1, C=1 hiba, R17 hibakod
RD_Err:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Host read error Resend needed ori STD sec ret
R16,0b00000100 Y+PS2Flag-RAMSTRT,R16
; ****************************************************************************** ;* C O M M A N D S from host ;* ; ****************************************************************************** ;*Set/reset status indicators. A '1' bit turns the indicator ON. ;* 0. Scrollock,LED0 Green ;* 1. Numlock, LED0 Red ;* 2. Capslock, LED1 Green ;* 3. LED1 Red ;* 4. LED2 Green ;* 5. LED2 Red ;* 6. =1 Flash ;* 7. =0 ;******************************************************* STATUS_IND: ldi ZL,Low(StatInd1) ldi ZH,High(StatInd1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active ori R16,0b00001001 STD Y+PS2Flag-RAMSTRT,R16 ret StatInd1: rcall Read_Data brcc SatInd2 ret SatInd2: mov R16,R1 andi R16,0b01000000 ; flash bit active? ldi R16,0b00111111 breq noflash and R16,R1 STD Y+StatLEDs+1-RAMSTRT,R16 rjmp SatInd3 noflash: and R16,R1 STD Y+StatLEDs+0-RAMSTRT,R16 SatInd3: LDD R16,Y+PS2Flag-RAMSTRT andi R16,0b11110111 ; parameter renben megjott, torolve a bit ori R16,0b00000001 ; ACK kuldes kell STD Y+PS2Flag-RAMSTRT,R16 rcall Puts_LEDs ;uj led allapot kikuldese rjmp EndBack ;******************************************************* ECHO: ldi ZL,Low(Echo1) ldi ZH,High(Echo1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH ret Echo1: ldi ;Echo valasz a parancsra mov R1,R16 rcall SendByte ;
R16,0xEE
Send rjmp
EndBack
;******************************************************* ALT_SCAN:
ldi ldi STD STD LDD
ZL,Low(Altscan1) ZH,High(Altscan1) Y+PS2NextA+0-RAMSTRT,ZL Y+PS2NextA+1-RAMSTRT,ZH R16,Y+PS2Flag-RAMSTRT
ori STD ret rcall brcc ret LDD andi
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD
Y+PS2Flag-RAMSTRT,R16
mov
R16,R1
;
andi
R16,3
;
cpi breq ldd andi
R16,0 Lekerdezes R17,Y+Flag1-RAMSTRT R17,0b11111100
;
or STD
R17,R16 Y+Flag1-RAMSTRT,R17
;uj
rjmp
EndBack
;
Make ACK & Parameter bit flag active
Altscan1:
Altscan2:
Read_Data Altscan2
parameter renben megjott, torolve a bit ACK kuldes kell
parameter byte csak az alo 2 bit kell
scan mode maskolasa
scan mode mentese
Lekerdezes: ldi ldi STD STD ret
ZL,Low(Scanlek) ZH,High(Scanlek) Y+PS2NextA+0-RAMSTRT,ZL Y+PS2NextA+1-RAMSTRT,ZH
Scanlek:
ldd andi
R16,Y+Flag1-RAMSTRT R16,0b00000011
;
inc
R16
;
mov rcall
R1,R16 SendByte
;
rjmp
EndBack
scan mode maskolasa igy lesz 1,2,3 kodtabla
Send scan tab kod
;******************************************************* TYPE_RATE: ldi ZL,Low(TYPE_RATE1) ldi ZH,High(TYPE_RATE1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active ori STD ret TYPE_RATE1: rcall brcc ret
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data TR1 ;ha
hiba volt: request to resend
;
rcall
SetWait
;
mov swap andi rcall LDD
R16,R1 R16 R16,0b00000011 SetRep R16,Y+PS2Flag-RAMSTRT
;
ori STD rjmp
R16,0b00000001 Y+PS2Flag-RAMSTRT,R16 EndBack
R1
TR1: mov R16, ;Bit 7 is unimplemented. andi R16,0b00011111
Bits 6:5 - Repeat Delay Bits 4:0 - Repeat Rate
Make ACK flag active
;******************************************************* KEN: ;Make ACK flag active
RAMSTRT
LDD
R16,Y+PS2Flag-
ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a enables code rjmp EndBack ;*******************************************************
RAMSTRT
KDIS: ;Make ACK flag active
LDD
R16,Y+PS2Flag-
ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon disables code rjmp EndBack ;******************************************************* SET_DEF:
LDD
R16,Y+PS2Flag-RAMSTRT
;
ori STD rcall
R16,0b00000001 Y+PS2Flag-RAMSTRT,R16 Scan_Init
;
rjmp
EndBack
Make ACK flag active
Default Scantable
;******************************************************* ALL_TYPE:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* ALL_BREAK:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* ALL_MAKE:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* ALL_MTB:
LDD
R16,Y+PS2Flag-RAMSTRT
;
Make ACK flag active ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ;ide jon a set code rjmp EndBack ;******************************************************* KEY_TYPE: ldi ZL,Low(Ktype1) ldi ZH,High(Ktype1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active
Ktype1:
Ktype2:
ori STD ret rcall brcc ret mov
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data Ktype2 R16,R1
;
parameter byte
;ide jon az feldolgozas!! LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD rjmp
Y+PS2Flag-RAMSTRT,R16 EndBack
parameter renben megjott, torolve a bit ACK kuldes kell
;******************************************************* KEY_BREAK: ldi ZL,Low(Kbreak1) ldi ZH,High(Kbreak1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active
Kbreak1:
Kbreak2:
ori STD ret rcall brcc ret mov
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data Kbreak2 R16,R1
;
parameter byte
;ide jon a feldolgozas!! LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD rjmp
Y+PS2Flag-RAMSTRT,R16 EndBack
parameter renben megjott, torolve a bit ACK kuldes kell
;******************************************************* KEY_MAKE: ldi ZL,Low(Kmake1) ldi ZH,High(Kmake1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK & Parameter bit flag active
Kmake1:
Kmake2:
ori STD ret rcall brcc ret mov
R16,0b00001001 Y+PS2Flag-RAMSTRT,R16 Read_Data Kmake2 R16,R1
;
parameter byte
;ide jon a feldolgozas!! LDD andi
R16,Y+PS2Flag-RAMSTRT R16,0b11110111
;
ori
R16,0b00000001
;
STD rjmp
Y+PS2Flag-RAMSTRT,R16 EndBack
parameter renben megjott, torolve a bit ACK kuldes kell
;******************************************************* RESEND: LDD R16,Y+PS2FlagRAMSTRT
;Resend last data! ori STD rjmp
R16,0b00000010 Y+PS2Flag-RAMSTRT,R16 EndBack
;******************************************************* ;* Keyboard RESET ;******************************************************* KRES: ldi ZL,Low(KRES1) ldi ZH,High(KRES1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK flag active ori STD ret
R16,0b00000001 Y+PS2Flag-RAMSTRT,R16
R16,0xAA
KRES1: ldi ;Basic Assurance Test Result mov R1,R16 rcall SendByte
;
Send Result of BAT rcall
Scan_Init
;Re-
ldi STD
R16,0 Y+PS2Flag-RAMSTRT,R16
;
STD
Y+StatLEDs+0-RAMSTRT,R16
;
STD
Y+StatLEDs+1-RAMSTRT,R16
;
rjmp
EndBack
init Scantable
Calears Flags LED nem villagit LED nem villog
;******************************************************* READID: ldi ZL,Low(READID1) ldi ZH,High(READID1) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH LDD R16,Y+PS2Flag-RAMSTRT ; Make ACK flag active
READID1:
ldi
ori R16,0b00000001 STD Y+PS2Flag-RAMSTRT,R16 ret ldi ZL,Low(READID2) ldi ZH,High(READID2) STD Y+PS2NextA+0-RAMSTRT,ZL STD Y+PS2NextA+1-RAMSTRT,ZH R16,0xD0 ;Eredeti:
0xAB mov rcall
R1,R16 SendByte
;
ret ldi
R16,0xDE
;
Send Result of BAT READID2: Eredeti: 0x83 mov rcall EndBack:
R1,R16 SendByte ldi R16,0 Y+PS2NextA+0-RAMSTRT,R16 Y+PS2NextA+1-RAMSTRT,R16
STD STD ret ;******************************************************* ; ************************************************************************************** .ESEG ;************************************** ;* Scan kod tabla Scan1 & Scan2 kodokkal ;* ;Keys allapota ;7. = 1 Enabled ;6. = 1 Ismetleses mod (Typematic) ;5. = 1 Break mode (felengedeskor scan kod kell) ;4. = 1 Make mode (lenyomaskor scan kod kell) ;3. = 1 Utolso ervenyes allapot ;2:1 = > counter prellegesmentesiteshez ;0. = 1 Utolso allapot ; ; 6..4 = 1 Typematic/make/break mode ; 5..4 = 1 Make/break mode ; 4 = 1 Olny Make mode
MatrixTab:
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;0. ;1. ;2. ;3. ;4. ;5. ;6. ;7. ;8. ;9.
P L E A B % Space Bar 7 Menu Up Menu Ok
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;10. ;11. ;12. ;13. ;14. ;15. ;16. ;17. ;18. ;19.
+C +Z +Y Used 9 8 D H R I
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xB0 0xB0 0xB0 0xB0
;20. ;21. ;22. ;23. ;24. ;25. ;26. ;27. ;28. ;29.
J K O 4 Menu Menu Cancel Used +X Gyorsmenet -X
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;30. ;31. ;32. ;33. ;34. ;35. ;36. ;37. ;38. ;39.
6 5 N G M F S T Q 1
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xB0 0xB0 0xB0 0xB0 0xF0 0xF0 0xF0 0xF0
;40. ;41. ;42. ;43. ;44. ;45. ;46. ;47. ;48. ;49.
Menu Down MODE -C Used -Y -Z 3 2 X Y
.db .db .db .db .db .db .db .db .db .db
0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xB0
;50. ;51. ;52. ;53. ;54. ;55. ;56. ;57. ;58. ;59.
Z U V W C . End Up Arrow Home Rotate Right
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xB0
;60. ;61. ;62. ;63. ;64. ;65. ;66. ;67. ;68. ;69.
Rotate stop Rotate Left 0 S1 S2 S3 S4 S5 START
.db .db .db .db .db .db .db .db .db .db
0xB0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0 0xF0
;70. ;71. ;72. ;73. ;74. ;75. ;76. ;77. ;78. ;79.
STOP DEL R Arrow Dn Arrow L Arrow ENTER CTRL SHIFT Backspace INS
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0
;80. ;81. ;82. ;83. ;84. ;85. ;86. ;87. ;88. ;89.
Yac-16[0] Yac-16[1] Yac-16[2] Yac-16[3] Yac-16[4] Yac-16[5] Yac-16[6] Yac-16[7] Yac-16[8] Yac-16[9]
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0
;90. ;91. ;92. ;93. ;94. ;95. ;96. ;97. ;98. ;99.
Yac-16[10] Yac-16[11] Yac-16[12] Yac-16[13] Yac-16[14] Yac-16[15] Yac-11[0] Yac-11[1] Yac-11[2] Yac-11[3]
.db .db .db .db .db .db .db .db .db .db
0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0 0xB0
;100. ;101. ;102. ;103. ;104. ;105. ;106. ;107. ;108. ;109.
.db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db .db
0xB0 ;110. 0xF0 ;111. 0xB0 ;112. 0xB0 ;113. 0xB0 ;114. 0xB0 ;115. 0xB0 ;116. 0xB0 ;117. 0xB0 ;118. 0xB0 ;119. 0xB0 ;120. 0xB0 ;121. 0xB0 ;122. 0xB0 ;123. 0xF0 ;124. 0xF0 ;125. 0xF0 ;126. 0xF0 ;127. 0x01,0x0C
;10.
;20.
;30.
;40.
;50.
;60.
;70.
;80.
;90.
;100 Yac-11[4] Yac-11[5] Yac-11[6] Yac-11[7] Yac-11[8] Yac-11[9] Yac-11[10] 3 allasu kapcs1A 3 allasu kapcs1B 3 allasu kapcs2A
;110
DeleayT:
3 allasu kapcs2B Not used Yac-12[0] Yac-12[1] Yac-12[2] Yac-12[3] Yac-12[4] Yac-12[5] Yac-12[6] Yac-12[7] Yac-12[8] Yac-12[9] Yac-12[10] Yac-12[11] Not used Not used Not used Not used ;Set 500ms
rep., 10 char/s
; ************************************************************************************** .CSEG Scan_Init:
ldi ldi ldi ldi out
XL,Low(Matrix) XH,High(Matrix) ZL,Low(MatrixTab) ZH,High(MatrixTab) EEARH,ZH
;output
out
EEARL,ZL
;output
ldi rcall
R17,KeyCount EERead_seq
;get EEPROM
ST dec brne
X+,R0 R17 GetMatrix
;Scan
ldi ldi out out rcall
ZL,Low(DeleayT) ZH,High(DeleayT) EEARH,ZH EEARL,ZL EERead_seq
;get Dleay
rcall rcall
SetWait EERead_seq
;get Rep.
rcall clr STD ret
SetRep R16 Y+ParamErr-RAMSTRT,R16
address high for 8515 address low for 8515 GetMatrix: data
filter torlese
mov R16,R0
Time mov R16,R0
;********************************** ;* Beolvas a Keymatrixrol egy teljes matrixot a memoriaba ;* ScanMatrix: CBI ldi ldi
Row01234,Row0 ZL,Low(Matrix) ZH,High(Matrix)
;a
billentyu parametertabla cime
Row0w: var mig a pin fizikailag nem lesz alacsony
SBIC
Row01234-2,Row0
;
rjmp Row0w IN R0,DTLo_PORT-1
;Lower 8
HalfRow IN R0,DTHi_PORT-1
;Higher 8
bit rcall bit SBI CBI Row0u: var mig a pin fizikailag nem lesz magas
Row01234,Row0 Row01234,Row1 rcall HalfRow SBIS Row01234-2,Row0
;
rjmp Row0u
Row1w:
SBIC Row01234-2,Row1 rjmp Row1w IN R0,DTLo_PORT-1 ;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row1u:
Row2w:
Row01234,Row1 Row01234,Row2 rcall HalfRow SBIS Row01234-2,Row1 rjmp Row1u
SBIC Row01234-2,Row2 rjmp Row2w IN R0,DTLo_PORT-1 ;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row2u:
Row3w:
Row01234,Row2 Row01234,Row3 rcall HalfRow SBIS Row01234-2,Row2 rjmp Row2u
SBIC Row01234-2,Row3 rjmp Row3w IN R0,DTLo_PORT-1 ;Lower 8
bit rcall HalfRow R0,DTHi_PORT-1
IN
;Higher 8
bit SBI CBI Row3u:
Row4w:
Row01234,Row3 Row01234,Row4 rcall HalfRow SBIS Row01234-2,Row3 rjmp Row3u
SBIC Row01234-2,Row4 rjmp Row4w IN R0,DTLo_PORT-1 ;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row4u:
Row5w:
Row01234,Row4 Row567,Row5 rcall HalfRow SBIS Row01234-2,Row4 rjmp Row4u
SBIC Row567-2,Row5 rjmp Row5w IN R0,DTLo_PORT-1
;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row5u:
Row6w:
Row567,Row5 Row567,Row6 rcall HalfRow SBIS Row567-2,Row5 rjmp Row5u
SBIC Row567-2,Row6 rjmp Row6w IN R0,DTLo_PORT-1
;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI CBI Row6u:
Row7w:
Row567,Row6 Row567,Row7 rcall HalfRow SBIS Row567-2,Row6 rjmp Row6u
SBIC Row567-2,Row7 rjmp Row7w IN R0,DTLo_PORT-1
;Lower 8
bit IN
rcall HalfRow R0,DTHi_PORT-1
;Higher 8
bit SBI Row7u:
Row567,Row7 rcall HalfRow SBIS Row567-2,Row7 rjmp Row7u
ret
;filter
bufferben a beolvasott matrix
;***************************** ;xx. sor feldolgozasa HalfRow:
com
R0
;inv, ekkor
ldi
R16,8
ld
R1,Z
;R1-ban a
mov ror andi
R19,R1 R19 R19,3
;a szamlalo
cpi breq inc andi
R19,3 kc1 R19 mov R17,1
mov andi
R18,R0 R18,1
;0. bit
eor breq
R17,R18 kc2
;azonos? ;ha igen
clr
R19
;szamlalo
rol andi
ror R19 R19,7
mov
R17,R1
0 = nincs lenyomas, 1 = lenyomva
KeyCycl: bill. parameter
allapota
kc1:
;szamlalo+1 R17,R1 ;0. bit az
elozo allapot
mostani allapot
ugras torlese, ha nem azonos kc2:
szamlalot es az uj allapotbit kell
http://avr-asm.tripod.com/ps2emu.html (2 of 4)1/20/2009 9:14:56 PM
R0 ;csak a
16 BIT MATH (AVR 202)
andi
R17,0b11111000
;a
or
R19,R17
;counter es
st
Z+,R19
dec brne ret
R16 KeyCycl
parameter byte also 3 bitje nem kell uj allapot bemasolasa
;***************************************************** ;* Eloallitja a scankodokat a bill.matrix allapota alapjan ;* ;***************************************************** MakeScanC: ldi ZL,Low(2*ScanTabl) ldi ZH,High(2*ScanTabl) ; Scancode table ldi ldi
XL,Low(Matrix) XH,High(Matrix)
;a
clr ldd andi
R1 R16,Y+Flag1-RAMSTRT R16,3
;
cpi breq
R16,1 scanjo
;ha
billentyu parametertabla cime
scan mode kinyerese
1, akkor scan mode1 adiw ZL,2
;scan mode2 cpi breq
R16,2 scanjo
;ha
adiw
ZL,2
;
2, akkor scan mode2 scan mode3 scanjo:
ldi
KeyCount table cime
R20, ;Z-ben az aktualis scan
keyloop:
lpm adiw mov
ZL,1 R4,R0
;R4
lpm mov adiw
R5,R0 ZL,5
;
ld
R1,X
mov
R17,R1
low, R5 hi part
kovetkezo kod cime
;allapot
byte andi
R17,1
;
R17 0. bit az uj allapot mov ror mov ror ror andi
R18,R1 R18 R19,R18 R19 R19 R19,1
;R19 elozo
andi
R18,3
;counter
cpi
R18,3
;counter<>3
breq rjmp
kl1 nextkey eor R19,R17
allapot erteke nem tortenik semmi
kl1:
;
ket allapot azonos? brne
diffrent
;ha nem,
cpi
R17,1
;lenyomott
breq rjmp
kl2 nextkey
;ha nem,
akkor make scan/break kod allapot?
akkor nem tortenik semmi kl2:
LDD
R9,Y+RepChar-RAMSTRT
;
ismetelendo karakter sorszama cp
R20,R9
;itt
brne
nextkey
;ha nem
mov andi breq
R17,R15 R17,1 nextkey
;ismetles
ldi and
R17,0b11111110 R15,R17
;flag
mov andi
R16,R1 R16,0b01000000
;
breq
nextkey
;ha
ldi
R17,2
mov mov rjmp
R1,R5 R2,R4 mb2
mov andi mov lsl lsl lsl or ST
R18,R1 R18,0b11110111 R2,R17 R2 R2 R2 R2,R18 X,R2
mov
R16,R1
;a gomb
andi breq
R16,0b10000000 nextkey
;ha
cpi
R17,1
;ha az uj
breq
lenyom
tartunk? kimarad
meg nem kell
torolve
typematic mode? igen ugras
;ismetles
mehet
diffrent:
aktiv? kell figyelni?
inaktiv, jon a kovetkezo bit 1, akkor lenyomas
feleng:
LDD
R16,Y+RepChar-RAMSTRT
;
ismetelendo karakter sorszama cp
R20,R16
;itt
brne
Fel1
;ha nem
rcall
RepTimerStop
andi
mov R16,R1 R16,0b00100000
breq
nextkey
ldd andi
R16,Y+Flag1-RAMSTRT R16,3
;
cpi breq
R16,1 scantab1
;ha
ldi
R17,0xF0
;
mov mov mov ldi rjmp
R1,R5 R2,R17 R3,R4 R17,3 mb2
tartunk? kimarad
Fel1:
;kell break
kodot generalni?
scan mode kinyerese
1, akkor scan mode1
scantab2 & 3
scantab1:
ldi R17,0x80
;
use scantable 1 or
R4,R17
;7.
mov mov ldi rjmp
R1,R5 R2,R4 R17,2 mb2
andi
mov R16,R1 R16,0b00010000
breq
nextkey
ldi
R17,2
mov mov rcall
R1,R5 R2,R4 RepTimerStart
brne mov mov dec
tst mb3 R1,R2 R2,R3 R17 rcall
bit =1 break
lenyom:
;
kell make kodot generalni?
;
make code 0xE0xx 2 byte
mb2:
mb3:
nextkey:
R1
PutScanCodes
adiw
XL,1
;
dec
R20
;
breq rjmp ret
keyextit keyloop
kovetkezo matrix elem kovetkezo scan kod cime
keyextit:
;************************************************ ;* Put Scan code into FIFO ;* in: R17 - mennyi hely kell, R1,R2,R3 parameterek ami a pufferbe kerul ;* out C=1 hiba ;************************************************ PutScanCodes: push ZL push ZH ldd ldd sub breq
R18,Y+KeyTrail-RAMSTRT R19,Y+KeyHead-RAMSTRT R18,R19 Sntolc1
;R18=txtail ;R19=txhead
brsh
Sndjoc1
Sntolc1:
subi
R18,(-1*KeyBuffLen)
;(T-H)+32
Sndjoc1:
cp
R18,R17
;R18 hely a
brcs
SendchrExit1
;ha <1
clr ldi
R18 zl,low(KeyBuff)
;R18=0 ;Pointer to
ldi add adc
zh,high(KeyBuff) zl,R19 zh,R18
; add
st
z+,R1
;Store
inc cpi brcs
R19 R19,KeyBuffLen Snd2c
;TxHead<32
clr ldi
R19 zl,low(KeyBuff)
;TxHead=0 ;Pointer to
ldi
zh,high(KeyBuff)
breq st
dec stend z+,R2
inc cpi brcs clr ldi
R19 R19,KeyBuffLen Snd3c R19 zl,low(KeyBuff)
ldi breq
zh,high(KeyBuff) dec R17 stend
st
z+,R3
;Store 3.
inc cpi brcs clr
R19 R19,KeyBuffLen stend R19
;TxHead=0
;T=H, akkor
TXbuffSize hely van
pufferben nincs elg hely! Hiba!
the txbuffer (FIFO)
address offset...
z = @Buf[txhead]
first data
akkor jo
the txbuffer (FIFO)
Snd2c:
R17 ;Store 2.
data
;TxHead=0 ;Pointer to
the txbuffer (FIFO) Snd3c:
data
stend:
std clc
Y+KeyHead-RAMSTRT,R19 ; Nincs
hiba Addr eltarolva, kuldes folya,atban rjmp SendChrExit1:
putend sec
;
Return with error clr ldi
R18 zl,low(KeyBuff)
;R18=0 ;Pointer to
ldi add adc
zh,high(KeyBuff) zl,R19 zh,R18
; add
st
z+,R18
;Store
the txbuffer (FIFO)
address offset...
z = @Buf[txhead]
error marker (0) putend:
pop ZL
pop ret
ZH
;************************************** ;* Scan kod tabla Scan1 & Scan2 kodokkal ;* ScanTabl: .dw 0x0019,0x004d,0x004d .dw 0x0026,0x004b,0x004b .dw 0x0012,0x0024,0x0024 .dw 0x001E,0x001C,0x001C .dw 0x0030,0x0032,0x0032 .dw 0x0029,0x000E,0x000E .dw 0x0039,0x0029,0x0029
;0. ;1. ;2. ;3. ;4. ;5. ;6.
P L E A B % Space
Bar .dw .dw .dw
0x0008,0x003D,0x003D 0xE049,0xE07D,0x006F 0x0041,0x0083,0x0037
;7. 7 ;8. Menu Up ;9. Menu Ok
.dw .dw .dw .dw .dw .dw .dw .dw .dw .dw
0x004E,0x0079,0x0079 0x0049,0x007D,0x007D 0x0048,0x0075,0x0077 0x0047,0x006C,0x006C 0x000A,0x0046,0x0046 0x0009,0x003E,0x003E 0x0020,0x0023,0x0023 0x0023,0x0033,0x0033 0x0013,0x002D,0x002D 0x0017,0x0043,0x0043
;10. ;11. ;12. ;13. ;14. ;15. ;16. ;17. ;18. ;19.
+C +Z +Y Used 9 8 D H R I
.dw .dw .dw .dw .dw .dw
0x0024,0x003B,0x003B 0x0025,0x0042,0x0042 0x0018,0x0044,0x0044 0x0005,0x0025,0x0025 0x0043,0x0001,0x0047 0x0040,0x000B,0x002F
;20. ;21. ;22. ;23. ;24. ;25.
J K O 4 Menu Menu
.dw .dw .dw
0x0053,0x0071,0x0071 0x004D,0x0074,0x0074 0x0038,0x0011,0x0019
;26. Used ;27. +X ;28.
.dw
0x004B,0x006B,0x006B
;29. -X
.dw .dw .dw .dw .dw .dw .dw .dw .dw .dw
0x0007,0x0036,0x0036 0x0006,0x002E,0x002E 0x0031,0x0031,0x0031 0x0022,0x0034,0x0034 0x0032,0x003A,0x003A 0x0021,0x002B,0x002B 0x001F,0x001B,0x001B 0x0014,0x002C,0x002C 0x0010,0x0015,0x0015 0x0002,0x0016,0x0016
;30. ;31. ;32. ;33. ;34. ;35. ;36. ;37. ;38. ;39.
.dw
0xE051,0xE07A,0x006D
;40. Menu
.dw .dw .dw .dw .dw .dw .dw .dw .dw
0x000F,0x000D,0x000D 0x004A,0x007B,0x0084 0x0051,0x007A,0x007A 0x0050,0x0072,0x0072 0x004F,0x0069,0x0069 0x0004,0x0026,0x0026 0x0003,0x001E,0x001E 0x002D,0x0022,0x0022 0x0015,0x0035,0x0035
;41. ;42. ;43. ;44. ;45. ;46. ;47. ;48. ;49.
MODE -C Used -Y -Z 3 2 X Y
.dw .dw .dw .dw .dw .dw .dw .dw
0x002C,0x001A,0x001A 0x0016,0x003C,0x003C 0x002F,0x002A,0x002A 0x0011,0x001D,0x001D 0x002E,0x0021,0x0021 0x0034,0x0049,0x0049 0xE04F,0xE069,0x0065 0xE048,0xE075,0x0063
;50. ;51. ;52. ;53. ;54. ;55. ;56. ;57.
Z U V W C . End Up
.dw .dw
0xE047,0xE06C,0x006E 0x0058,0x0007,0x005E
;58. Home ;59. Rotate
.dw
0x0001,0x0076,0x0008
;60. Rotate
.dw
0x0044,0x0009,0x004F
;61. Rotate
.dw .dw .dw .dw .dw .dw .dw .dw
0x000B,0x0045,0x0045 0x000C,0x004E,0x004E 0x003B,0x0005,0x0007 0x003C,0x0006,0x000F 0x003D,0x0004,0x0017 0x003E,0x000C,0x001F 0x003F,0x0003,0x0027 0xE065,0xE010,0xE010
;62. ;63. ;64. ;65. ;66. ;67. ;68. ;69.
0 S1 S2 S3 S4 S5 START
.dw .dw .dw .dw
0xE064,0xE008,0xE008 0xE053,0xE071,0x0064 0xE04D,0xE074,0x006A 0xE050,0xE072,0x0060
;70. ;71. ;72. ;73.
STOP DEL R Arrow Dn
.dw .dw .dw .dw .dw
0xE04B,0xE06B,0x0061 0x001C,0x005A,0x005A 0x001D,0x0014,0x0011 0x002A,0x0012,0x0012 0x000E,0x0066,0x0066
;74. ;75. ;76. ;77. ;78.
L Arrow ENTER CTRL SHIFT
.dw
0xE052,0xE070,0x0067
;79. INS
.dw
0xE066,0xE018,0xE018
;80. Yac-16
.dw
0xE067,0xE020,0xE020
;81. Yac-16
.dw
0xE068,0xE028,0xE028
;82. Yac-16
.dw
0xE069,0xE030,0xE030
;83. Yac-16
.dw
0xE06A,0xE038,0xE038
;84. Yac-16
.dw
0xE06B,0xE040,0xE040
;85. Yac-16
.dw
0xE06C,0xE048,0xE048
;86. Yac-16
.dw
0xE06D,0xE050,0xE050
;87. Yac-16
.dw
0xE06E,0xE057,0xE057
;88. Yac-16
.dw
0xE06F,0xE06F,0xE06F
;89. Yac-16
.dw
0xE070,0xE013,0xE013
;90. Yac-16
.dw
0xE071,0xE019,0xE019
;91. Yac-16
.dw
0xE072,0xE039,0xE039
;92. Yac-16
.dw
0xE074,0xE053,0xE053
;93. Yac-16
.dw
0xE075,0xE05C,0xE05C
;94. Yac-16
.dw
0xE076,0xE05F,0xE05F
;95. Yac-16
.dw
0xE056,0xE061,0x0061
;96. Yac-11
.dw
0xE02C,0xE01A,0x001A
;97. Yac-11
.dw
0xE02D,0xE022,0x0022
;98. Yac-11
.dw
0xE02E,0xE021,0x0021
;99. Yac-11
.dw
0xE02F,0xE02A,0x002A
;100. Yac-11
.dw
0xE030,0xE032,0x0032
;101. Yac-11
.dw
0xE031,0xE031,0x0031
;102. Yac-11
.dw
0xE032,0xE03A,0x003A
;103. Yac-11
.dw
0xE033,0xE041,0x0041
;104. Yac-11
.dw
0xE034,0xE049,0x0049
;105. Yac-11
.dw
0xE035,0xE04A,0x004A
;106. Yac-11
.dw
0x0000,0x0000,0x0000
;107. Kapcs
.dw
0x0000,0x0000,0x0000
;108. Kapcs
.dw
0x0000,0x0000,0x0000
;109. Kapcs
.dw
0x0000,0x0000,0x0000
;110. Kapcs
.dw
0x0000,0x0000,0x0000
;111. Not
.dw
0xE03A,0xE058,0xE058
;112. Yac-12
.dw
0xE01E,0xE01C,0xE01C
;113. Yac-12
.dw
0xE01F,0xE01B,0xE01B
;114. Yac-12
.dw
0xE020,0xE023,0xE023
;115. Yac-12
.dw
0xE021,0xE02B,0xE02B
;116. Yac-12
.dw
0xE022,0xE034,0xE034
;117. Yac-12
.dw
0xE023,0xE033,0xE033
;118. Yac-12
.dw
0xE024,0xE03B,0xE03B
;119. Yac-12
.dw
0xE025,0xE042,0xE042
;120. Yac-12
.dw
0xE026,0xE04B,0xE04B
;121. Yac-12
.dw
0xE027,0xE04C,0xE04C
;122. Yac-12
.dw
0xE028,0xE052,0xE052
;123. Yac-12
.dw
0x0000,0x0000,0x0000
;124. Not
.dw
0x0000,0x0000,0x0000
;125. Not
.dw
0x0000,0x0000,0x0000
;126. Not
.dw
0x0000,0x0000,0x0000
;127. Not
;10.
;20.
Cancel
Gyorsmenet ;30. 6 5 N G M F S T Q 1
;40. Down
;50.
Arrow
Right ;60. stop Left
;70.
Arrow
Backspace ;80. [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] ;90. [10] [11] [12] [13] [14] [15] [0] [1] [2] [3] ;100 [4] [5] [6] [7] [8] [9] [10] 1A 1B 2A ;110 2B used [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] used used used used
;************** ;** Kivarasi idotablazat ;** ;** f=3.6864MHz, fc=f/256 = ;** WaitTime: .dw 0x0E10 .dw 0x1C20 .dw 0x2A30 .dw 0x3840
14400Hz => 69.44us ;250ms ;500ms ;750ms ;1000ms
;**ismetlesi ido idotablazat RepTime:
.dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw .dw
0x01E0 0x021B 0x0258 0x0295 0x02D0 0x030A 0x034A 0x0384 0x03C0 0x043A 0x04B0 0x0529 0x05A0 0x061D 0x068A 0x0708 0x0780 0x0865 0x0960 0x0A3A 0x0B40 0x0C3A 0x0D14 0x0E10 0x0F33 0x110B 0x12C0 0x14D5 0x1680 0x1874 0x1AC9 0x1C20
;00000 ;00001 ;00010 ;00011 ;00100 ;00101 ;00110 ;00111 ;01000 ;01001 ;01010 ;01011 ;01100 ;01101 ;01110 ;01111 ;10000 ;10001 ;10010 ;10011 ;10100 ;10101 ;10110 ;10111 ;11000 ;11001 ;11010 ;11011 ;11100 ;11101 ;11110 ;11111
30.0 26.7 24.0 21.8 20.0 18.5 17.1 16.0 15.0 13.3 12.0 10.9 10.0 9.2 8.6 8.0 7.5 6.7 6.0 5.5 5.0 4.6 4.3 4.0 3.7 3.3 3.0 2.7 2.5 2.3 2.1 2.0
char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s char/s
;************************************************ ;* Set Deleay Time ;* in: R16 Wait time selector 0..3 ;* ;************************************************ SetWait: ldi ZL,Low(2*WaitTime) ldi ZH,High(2*WaitTime) clr R0 andi R16,3 add R16,R16 add ZL,R16 adc ZH,R0 LDI OUT
R16,0b00001000 TCCR1B,R16
;Timer Stop ;7. = 0 Input
Capture Noise Canceller Disabled ;6. = 0 InputCapture ICP Falling edge ;3. = 1 Reset TC1 when copare match ;2:0 Clock ; 000 => ; 001 => ; 010 => ; 011 => ; 100 => ; 101 => ; 110 =>
select TC1 Stop Ck Ck/8 Ck/64 Ck/256 Ck/1024 External
T1 Falling Edge ;
111 => External
T1 rising Edge lpm adiw add csak 3.68MHz-re keszult mi meg 7.37MHz-en ketyegunk std lpm adc std ret
ZL,1 R0,R0
;mert a tablazat
Y+WTime+0-RAMSTRT,R0 R0,R0 Y+WTime+1-RAMSTRT,R0
;************************************************ ;* Set Repeat Time ;* in: R16 rep time selector 0..31 ;* ;************************************************ SetRep: andi R16,0b00011111 add R16,R16 ;mert word meretu adatok kellenek ldi ldi clr add adc
ZL,Low(2*RepTime) ZH,High(2*RepTime) R0 ZL,R16 ZH,R0
LDI OUT
R16,0b00001000 TCCR1B,R16
;Timer Stop ;7. = 0 Input
Capture Noise Canceller Disabled ;6. = 0 InputCapture ICP Falling edge ;3. = 1 Reset TC1 when copare match ;2:0 Clock ; 000 => ; 001 => ; 010 => ; 011 => ; 100 => ; 101 => ; 110 =>
select TC1 Stop Ck Ck/8 Ck/64 Ck/256 Ck/1024 External
T1 Falling Edge ;
111 => External
T1 rising Edge lpm adiw add csak 3.68MHz-re keszult mi meg 7.37MHz-en ketyegunk std lpm adc std ret
ZL,1 R0,R0
;mert a tablazat
Y+WRep+0-RAMSTRT,R0 R0,R0 Y+WRep+1-RAMSTRT,R0
;**************************************************** ;* Billentyu nyomas utani elso ismetles timer inditas ;* R20 - ismetlendo billentyu sorszama ;**************************************************** RepTimerStart: STD Y+RepChar-RAMSTRT,R20 ; ismetelendo karakter sorszama LDI OUT OUT OUT
R16,0b00000000 TCCR1B,R16 TCNT1H,R16 TCNT1L,R16
in andi
R16,TIFR R16,255-(1< TC1 Stop
;Timer Stop
;Counter
torlese
;
001 =>
;
010 =>
;
011 =>
;
100 =>
;
101 =>
;
110 =>
;
111 =>
Ck Ck/8 Ck/64 Ck/256 Ck/1024 External T1 Falling Edge External T1 rising Edge ret
RepTimerStop:
LDI
R16,0b00000000
;
Timer Stop OUT in andi
TCCR1B,R16 R16,TIFR R16,255-(1<
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 http://avr-asm.tripod.com/ps2emu.html (3 of 4)1/20/2009 9:14:56 PM
16 BIT MATH (AVR 202)
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/ps2emu.html (4 of 4)1/20/2009 9:14:56 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
MEGA 8 BOOTLOADER HOME RETRO_DAN ;---------------------------------------------------------------------------------------; ; Program: Bootloader_Mega8.asm ; ; Writer: Herbert Dingfelder, DL5NEG ; for contact information visit WWW.DL5NEG.DE ; ; Based on: AVR-Freaks Design Note #32 ; ; Function: Bootloader for ATmega8, works via the UART with the normal ; AVRProg PC-Software ; ; Hardware: ATmega8 with a 7.3728MHz crystal ; ; History: ; ; 13.07.2004 - Source code adapted for Mega8, assembles without errors ; ; 15.07.2004 - Used crystal is not 7.3 but 3.686 MHz -> UART setting adapted ; - Red LED on PORTB 0 is switched on within the boot section, ; tested in Hardware and works -> processor starts correctly ; within the boot section ; ; 18.07.2004 - Problem how to download the bootloader is solved: Simply use ; the AVRProg in the "mega8" mode, not in "mega8boot" mode. ; Since the Intel-Hex Format contains the address for the code ; in each line, the programmers recognizes that the code has to ; go to the bootrom part of the flash (provided that the ; ".org MY_BOOTSTART" is put at the beginning of the source
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
code) - UART communication between bootloader and host PC works (echo mode and character recognition tested and works) - Crystal changed to 7.3728MHz in an attempt to fight "flushing" problems in AVRProg (without success), UART setting adapted - AVRProg is able to read the flash correctly (tested, works) - Reading and writing to EEPROM on host commands 'D' and 'd'
; ; ; ; ;
- Flash erase did not work in the NRWR section (the last 1024 words of the flash) The original version from DesignNote #32 was for ATmega163 which does not have RWR/NRWR sections. Problem solved by implementing the wait_for_spm function that makes sure that a new SPM does only start when the previous
; ; ;
is completed. (tested, works now) - function to reenable the RWW section implemented -> loading data into the application section tested and works
AVG8 222
; ; ; ; ; ;
FFT7 COPY 102 LPM 108 EPROM 100
works.
SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
one
VFX MEM SORT 220 fine CRC 236 XMODEM REC UART 304
;
(Still some problems with sync on the interface between
;
and the boot loader, messagebox "flushing" appears, fuse bits
; ;
read differently many times and software download needs to be started twice sometimes. As it is known that AVRProg is very
;
command/answer sync, this does not point towards real
AVRProg are
UART 305 UART 128
sensible
UART BUFF USB 232
bootloader problems. ; ; ;
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300
on. If ;
no ASCII(27) is received via UART within that time, the
;
If the application section is empty (all cells are $FF) e.g.
;
after uploading the bootloader itself, then software will
application starts. directly
I2C 302 I2C TWI26
wait forever ; ; ;
for a ESC via the UART to start the bootloader software (while waiting for the ESC the LED blinks) - Function pause implemented for delays in steps of 10ms
;
- Command 'E' implemented for leaving the bootloader mode and
; ;
application - With that entry end exit function the bootloader is fully
; ; ;
the downloaded application is tested and works perfectly -> Version 1.1 released - Still known problem: the above mentioned sync problem in
; ;
with AVRProg have to be identified and solved. - Only 2 Words are left in the bootloader memory. If Bugfixing
I2C/TWI 128 I2C/TWI AT8
(tested works)
DALLAS-1W DALLAS CRC
start the
ETHNET 8019 TEA
usable, starting
ADC 128 ADC 10B ADC 400
combination
ADC 401 THERM 232
needs more, ; ; ;
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
KBD PC/128 PS2 EMU
ALM CLK
DELAYS CALL ID
;
- Command 'v' for Hardware Version was not implemented ->
;
- Command ':' for tranparent command setting was not
Window. fixed implemented ; ;
By monitoring the PC/AVR interface it was found that
;
not use the defined commands r/F/N for reading the lock and
;
but uses the universal command ':' to send the programming
;
directly. Additionally the calibration byte is read by the
;
- Command 'b' is send by AVRProg1.37 but is not implemented.
;
it is fatal for the programming mode to implement 'b' to
;
To simply leave it out (returns ? for unknow command) works
AVRProg1.37 does fuse bits, instructions ':' command. It was found that return 'Y'. perfectly. ; ;
PWM 10K ENCODE STH-11
25.07.2004
- To implement all improvements found on 24.07.2004 without skipping
lots of ;
of other code made it necessary to increase the boot loader
; ; ;
(=1kByte). Code adapted. - Command ':' enlarged to map r/F/N functionality - Tested, current status: Works well in AVRProg both for flash
size to 512words
ATMEL CORP AVR BUTTERFLY
-> is now implemented in simple version, always
returning \0
DTMF 314 PWM 6CH
- Debug Session with Andy, DG9NDZ to find why AVRProg 1.37 still has problems with the bootloader, especially in the "Advanced"
CLOCK 8564 90 DAYS
24.07.2004
;
BOOT MG8 BOOT DR8
the erease counter within the EEPROM can be skipped
some
MUX 242 KBD PS2
It has to be tracked on the interface.) -> Good enough to work with temporarily, Version 1.0 released. - Startup-function implemented for 10 second wait after power-
reading and writing ;
and also in the Advance window the lock and fuse bits are
;
Only week point remaining to press "write" in advance window,
;
loose of sync between host and bootloader. No harm is done to
; ; ;
-> Version 1.2 released.
AVR BOOK display correctly. that causes a the target device.
26.07.2004
- Monitoring of interface from host reveals the root cause of the sync
problem when ;
writing the the lock and fuse bits. AVRProg1.37 uses the "new
;
which is "." + 4 data bytes. This command was not
;
fuse bits is dangerous when the device is remote (one could
;
forever), the command is now implemented simply to ignore the
;
serve the interface to the host to avoid sync problems.
; ; ;
-> Version 1.3 released
universal command" implemented. As changing the lock himself out inputs but correctly Tested and works perfectly.
07.04.2005
- The code contained the "call" command, which is not supported by
ATmega8. Obviously ;
the AVR implementation is in a way that lets the software
;
commands are now replaced by the supported "rcall" command
;
- The definition of E2END was missing in the mega8 definition
;
assembler, so it was included within this source file. Now
;
available in the include file, so it is taken out of this
; ; ;
- Intended Assembler Version is now: AVR macro assembler 2.0.28 (build 121 Jan 11 2005 10:28:51) - Configuration block implemented for easier user-defining of
; ; ;
the number of wait cycles at power on or the LED pin. - Code and Comments clean up - Version 1.4 decleared which will be used for testing on
work anyhow. All "call" now. file of the old the definition is file.
parameters like
hardware together with ; ; ;
AVRProg Version 1.40. 09.04.2005
- Goodbye-Message implemented to inform user via UART that bootloader
is left ; ; ; ; ; ; ; ; ; ; ;
when command 'E' was sent - Tests on hardware successful -> Version 2.0 released
Before or after programming a new ATmega8 with this Boot Loader the fuse bits must be set like this: The ATmega8 Fuse High bits must be programmed to configure the Boot size to 512
words ; ; ; ; ; ;
and to move the Reset Vector to word address 0xE00. (BOOTSZ1=0, BOOTSZ0=1)
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
(Settings can be checked now or later with "read").
I.e. set the check box for BOOTRST in AVR-Prog-Advanced and set the selector to 512 words, then press "write". It is important that this selected size of the bootrom fits to the .org command within this source code, otherwise the processor will not correctly start at the first line of this code after
reset.
Optional: The Lock bits can be programmed to 0xEF to protect the Boot Flash Section from unintentional changes and to allow accessing the Application Flash Section. I.e. the setting for BLB0 and BLB1 in AVR-Prog-Advance: BLB0 (sets the protection for the application section) must be set to Mode 1 (no protection) to allow full access of LPM and SPM commands within the application section. BLB1 (sets the protection for the boot loader section) can be set to Mode 2 (SPM cannot write to boot section) or can be left to Mode 1 (no protection). The Fuse bits must be programmed before programming the Lock bits.
AVRProg Commands as defined by Atmel Host Writes
Host Reads ; Data
ID
Data
; Enter Programming Mode (implemented to ignore) ; Auto Increment Address dd (fully implemented) ; Set Address 13d (fully implemented) ; Write Program Memory, Low Byte 'c' 13d (fully implemented) ; Write Program Memory, High Byte 'C' 13d (fully implemented) ; Issue Page Write 'm' 13d (fully implemented) ; Read Lock Bits dd (fully implemented) ; Read Program Memory 2*dd (fully implemented) ; Read EEPROM Memory dd (fully implemented) ; Write EEPROM Memory dd 13d (fully implemented) ; Chip Erase 'e' 13d (implemented, erases appl. area ; Write Lock Bits dd 13d (implemented to ignore) ; Read Fuse Bits dd (fully implemented) ; Read High Fuse Bits dd (fully implemented) ; Read Extended Fuse Bits dd (not implemented) ; Leave Programming Mode 13d (implemented to ignore) ; Select Device Type dd 13d (implemented to ignore) ; Read Signature Bytes 3*dd (fully implemented) ; Return Supported Device Codes 't' (implemented, returns only Mega8) ; Return Software Identifier [7] (fully implemented) ; Return Software Version dd (fully implemented) ; Return Hardware Version 'v' (fully implemented) ; Return Programmer Type dd (fully implemented) ; Set LED dd 13d (implemented to ignore) ; Clear LED dd 13d (implemented to ignore) ; Exit Bootloader 'E' {13d} (implemented 'E' is not confirmed) ; Check Block Support 2*dd (implemented to return no) ; Start Block Flash Load 13d (not implemented) ; n*dd ; Start Block EEPROM Load 13d (not implemented) ; n*dd ; Start Block Flash Read (not implemented) ; Start Block EEPROM Read (not implemented) ; Universal Command (3 data bytes) ':' 13d (implemented to ignore) ; New Universal Command (4 data bytes)'.' (implemented to ignore) ;
'P'
13d
'a' 'A'
ah al
dd dd
'r' 'R' 'd' 'D'
only) 'l' 'F' 'N' 'Q' 'L' 'T' 's' n*dd
00d
'S'
s
'V'
dd
'p' 'x' 'y'
'b'
'Y'
'B'
2*dd 'F'
'B'
2*dd 'E'
'g'
2*dd 'F'
n*dd
'g'
2*dd 'E'
n*dd
3*dd 4*dd
dd
dd
13d
;------------------------------- definition and includes -------------------------------.INCLUDE "m8def.inc"
; Include Register/Bit Definitions for
.def dummy = r18 .def pa_10ms = r19
; Use Reg. R18 for temporary stuff ; used for selecting the pause time in
.def uni_cmd1 = r20
; Universal command ':' send three
.def uni_cmd2 = r21
; are stored for futher usage in r20,
the mega8
steps of 10ms
bytes. These r21, r28 .def uni_cmd3 = r10 .equ VER_H = '2'
; bootloader software version higher
.equ VER_L = '0'
; bootloader software version lower
.equ VERH_H = '1'
; bootloader hardware version higher
.equ VERH_L = '0'
; bootloader hardware version lower
.equ DT
; Device Type = 0x76 (ATmega8)
number number
number number = 0x76
.equ SB1 = 0x07 .equ SB2 = 0x93 .equ SB3 = 0x1e
; Signature byte 1 ; Signature byte 2 ; Signature byte 3
.equ UBR = 23
; Baud rate = 19.2 kbps with
.equ ESC = 27
; Ascii 27 = Escape
fCK = 7.3728 MHz
;
.equ E2END = 1FF
; This definition is missing in the
m8def.inc file ; that came with the older Assembler. In "Assembler2" ; it is correct, so it is not required any more. .equ MY_BOOTSTART = THIRDBOOTSTART
; here we define where the bootloader starts in the
flash ;------------------------------ configuration parameters -------------------------------.equ STUP_WT_CKL
= 10
; number of waiting loops (LED flashes) at
power on ; before the main application starts automatically .equ LED_PORT .equ LED_DIR
= PORTB = DDRB
.equ LED_PIN
= 1
; Port B is used for the LED ; Direction register for LED Port is
DDRB ; LED is connected to pin 1 of
Port B
;------------------------------------- here we go --------------------------------------.org MY_BOOTSTART
; The code of this bootloader has to be
located in ; the bootloader area at the end of the flash. With ; this .org it can be loaded into the device just ; like any other software (normal ATmega8 setting). ; ------------------------------- init stackpointer ------------------------------------ldi ldi out out
R24, R25, SPL, SPH,
low(RAMEND) high(RAMEND) R24 R25
; SP = RAMEND
; ---------------------------------- init UART -----------------------------------------ldi R24, UBR out UBRRL, R24
; Baud rate = 19.2 bps
ldi R24,(1<
; Enable receiver & transmitter, 8-bit mode
-------------------------- check for action on UART ----------------------------------After power-on, the processor starts with the bootloader section. Ususally the user want the application to start automatircally. Only in special cases, a software update is required. So if no ESC (ASCII(27)) is received within the defined number of wait cycles after power-on, the application starts.
sbi LED_PORT, LED_PIN
; Switch PortB to output to drive an LED
ldi R17, STUP_WT_CKL
; Preset the number of LED-flashes (=number of
(active low) loops) ; for the waiting periode start_wait: sbi LED_PORT, LED_PIN ldi pa_10ms, 20 rcall pause
; switch off the LED
cbi LED_PORT, LED_PIN ldi pa_10ms, 20 rcall pause
; switch on the LED
; wait a moment
; wait a moment
sbis UCSRA,RXC rjmp Lwait
; check for incoming data (if RXC==1) ; if not, continue at Lwait
;--- some character was received --in R16, UDR
; fetch received character and put it
into R16 cpi R16, ESC breq bootload_start
; if the received character was ESC ; start the bootloader main loop ; LED stays switched on
(all other incomming characters ; are simply ignored) Lwait: dec R17 brne start_wait
; decrement the loop counter ; and leave loop if counter has reached
zero sbi LED_PORT, LED_PIN
; switch off the LED
rjmp FLASHEND+1
; Start the application program ; (flashend+1) =
Address 0
;------------------- here starts the real bootloader functionality ---------------------bootload_start: ; To indicate to the user that the attemt to start the bootloader functionality ; was successful, we send a message back on the UART. ldi ZL,low( 2*uart_msg) ldi ZH,high(2*uart_msg)
; load the start-address of the startup message ; into the Z-Register
str_output: lpm R16,Z+
; read one character of the
string and increment ; string pointer (the Zregister) tst R16 breq L10
; exit the character output
loop if character was '\0' rcall uartSend
; send the read character via the UART
rjmp str_output
; go to start of loop for next character
;---------------------------------- start of main loop ----------------------------------
;-------------------- wait for a character from UART other than ESC --------------------L10: rcall uartGet ; repeat (R16 = uartGet) cpi R16, ESC ; while (R16 == ESCAPE) breq L10 ;--------- Command 'E' leaves the bootloader mode and starts the application -----------cpi R16, 'E' brne L11
; if(R16=='E') 'E' = Exit bootloader
; Send goodbye-message on UART ldi ZL,low( 2*goodbye_msg) ldi ZH,high(2*goodbye_msg)
; load the start-address of the startup message ; into the Z-Register
goodbye_output: lpm R16,Z+
; read one character of the
string and increment ; string pointer (the Zregister) tst R16 breq leave_bootloader
; exit the character output loop if character
was '\0' rcall uartSend
; send the read character via the UART
rjmp goodbye_output
; go to start of loop for next character
leave_bootloader: sbi LED_PORT, LED_PIN
; switch off the LED
rjmp FLASHEND+1
; Start the application program ; (flashend+1) =
Address 0
;--------- Command 'a' is question from host for autoimcrement capability---------------; simple anser is 'Y' for yes, autoincrement is done L11: cpi R16, 'a' brne L12
; if(R16=='a') 'a' = Autoincrement?
ldi R16,'Y' rjmp L70
; Yes, autoincrement is quicker ; uartSend(R16) Send the 'Y'
and go up for next command
;--------- Command 'A' is setting the address for the next operation -------------------; two bytes (in total) for high and low address are sent from the host L12: cpi R16,'A' brne L14
; else if(R16=='A') write address
rcall uartGet mov R27,R16
; address high byte is stored in R27
rcall uartGet mov R26,R16
; address low byte is stored in R26
lsl R26 rol R27
; address=address<<1 ; convert from byte address to
rjmp L68
; uartSend('\r') send CR and go
word address
up for next command
;--------- Command 'c' is write low byte to program memory -----------------------------; the low byte is simply stored in a register, the actual writing to the flashes ; page-buffer is done later, after the high byte was received L14: cpi R16,'c' ; else if(R16=='c') write program memory, low byte brne L16 rcall uartGet
; read the byte to be written from host
mov R22,R16
; store data low byte in R22
rjmp L68
; uartSend('\r') send CR and go
up for next command
;--------- Command 'C' is write high byte to program memory ----------------------------; together with the (already received) low byte, the highbyte is writen to the flashes ; page buffer. When the page buffer is completely written, it can be transfered into ; the real flash by the "page write" command. ; ; If only SPMEN is written, the following SPM instruction will store the value in R1:R0 ; in the temporary page buffer addressed by the Z pointer. L16: cpi R16,'C'
; else if(R16=='C') write program
memory,high byte brne L18 rcall uartGet mov R23,R16
; read the high byte from the host ; store the data high byte in R23
movw ZL,R26
; load the Z pointer with the current
movw R0,R22
; transfer the data word (data high and
address
low byte) ; into registers R0 and R1 rcall wait_for_spm
; make sure SPM is ready to accept a
ldi R24, (1<<SPMEN) out SPMCR,R24
; set SPMEN in SPMCR ; page load (fill temporary buffer)
new task
spm
; Store program memory
adiw R26,2 rjmp L68
; address=address+2 ; uartSend('\r') send CR and go
up for next command
;-------------------------- Command 'e' is chip erase ----------------------------------; "chip erase" for the boot loader means to erase all flash pages othen than the ; boot loader sector itself L18: cpi R16,'e' brne L28
; else if(R16=='e') Chip erase
; the loop that has to be performed to clear the application section is: ; for(address=0; address < (2*MY_BOOTSTART); address += (2*PAGESIZE)) ; the "address" variable to be used are the registers R26 and R27 clr R26 clr R27
; start with address 0
rjmp L24
; continue the loop at the
check for ; "end-criteria reached" ;......... beginning of erase loop ............ L20: ; If the PGERS bit is written to one at the same time as SPMEN, the next SPM ; instruction within four clock cycles executes page erase. The page address ; is taken from the high part of the Z pointer. rcall wait_for_spm
; make sure SPM is ready to accept a
movw ZL,R26
; load the Z-pointer with the address
new task
of the ; page to be erased ldi R24, (1<
; Store program memory
subi R26,low(-2*PAGESIZE) sbci R27,high(-2*PAGESIZE)
; increment the address by the size of a page
; this is the check for end-criteria reached, i.e. has the address already ; reached the beginning of the boot-loader section L24: ldi R24,low( 2*MY_BOOTSTART) ldi R25,high(2*MY_BOOTSTART)
; load R24, R25 with the address where the boot-loader ; section starts
cp R26,R24
; do a word-compare to check if
cpc R27,R25
; smaller than the address
brlo L20
; if that is the case, go to
the address is still where the bootloader starts
the beginning of the erase loop ; ..... remember the number of flash-erases in the EEPROM ..... ldi R26,low( E2END -1) ; increment Chip Erase Counter located ldi R27,high(E2END -1) ; at address E2END-1 movw R22,R26 ; Save Chip Erase Counter Address in R22 ldi R17,1 ; read EEPROM rcall EepromTalk mov R24,R16 ; R24 = Chip Erase Counter low byte rcall EepromTalk mov R25,R16 ; R25 = Chip Erase Counter high byte adiw R24,1 ; counter ++ out EEDR,R24 ; EEDR = R24 Chip Erase Counter low byte movw R26,R22 ; R26 = Chip Erase Counter Address ldi R17,6 ; write EEPROM rcall EepromTalk out EEDR,R25 ; EEDR = R25 Chip Erase Counter high byte rcall EepromTalk ; .......................................................... rcall wait_for_spm
; make sure SPM is ready to accept a
rcall enable_rww
; reenable the RWW section so it can be
new task
accessed again rjmp L68
; uartSend('\r') send CR and go
up for next command ;---------------------------- Command 'm' is write page --------------------------------; To execute page write, set up the address in the Z pointer, write 'X0000101' to SPMCR ; and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 ; is ignored. The page address must be written to PCPAGE. Other bits in the Z pointer will ; be ignored during this operation. L28: cpi R16,'m' ; else if(R16== 'm') Write page brne L34 rcall wait_for_spm
; make sure SPM is ready to accept a
movw ZL,R26
; load Z-pointer with address
new task
ldi R24, (1<
; Store program memory
nop rcall enable_rww
; reenable the RWW section so it can be
accessed again L32: rjmp L68
; uartSend('\r') send CR and go
up for next command
;--------------------- Command 'P' is enter programming mode ---------------------------; nothing is done here, only the command is confirmed to host by sending CR L34: cpi R16,'P' ; else if(R16=='P') Enter programming mode breq L32
; uartSend('\r') Send CR to
host and go up for next command
;--------------------- Command 'L' is leave programming mode ---------------------------; nothing is done here, only the command is confirmed to host by sending CR cpi R16,'L' ; else if(R16=='L') Leave programming mode breq L32
; uartSend('\r') Send CR to
host and go up for next command
;--------------------- Command 'p' is Return programmer type ---------------------------; simply return an 'S' to indicate to host that this is a serial programmer cpi R16,'p'
; else if (R16=='p') return programmer
type brne L38 ldi R16,'S' rjmp L70
; uartSend('S') for type is serial ; uartSend(R16) and go up for
next command
;--------------------- Command 'R' is "Read one word from program memory" --------------; reads one word from the 'current' address that is stored in R26 and increments R26 L38: cpi R16,'R' ; else if(R16=='R') Read program memory brne L40 movw ZL,R26
; load Z-pointer with address of memory
to be read lpm R24,Z+
; read program memory LSB;
lpm R16,Z+
; read program memory MSB;
store LSB in R24 and Z pointer ++ store MSB in R16 and Z pointer ++ rcall uartSend
; uartSend(R16) write back MSB to host
movw R26,ZL
; increment the 'current' address += 2
mov R16,R24
; LSB stored in R16
rjmp L70
; uartSend(R16) write back the
LSB to host and go ; up for next command ;--------------------- Command 'D' is "write data to EEPROM" ---------------------------L40: cpi R16,'D' ; else if (R16=='D') Write data to EEPROM brne L41 rcall uartGet out EEDR,R16 ldi R17,6 rcall EepromTalk rjmp L68
; fetch the data to write from the UART ; EEDR = uartGet() ; write EEPROM ; uartSend('\r') Confirm the
command to host with CR
;--------- Command 'b' is question from host for block mode capability------------------; simple anser is 'N', no bootloader does not support blockmode L41: cpi R16, 'b' brne L42
; if(R16=='b') 'b' = Blockmode?
ldi R16,'N' rcall uartSend
; send 'N'
ldi R16,'N' rjmp L70
; send 'N' ; uartSend(R16) Send the 'N'
and go up for next command ;--------------------- Command 'd' is "read data from EEPROM ---------------------------L42: cpi R16,'d' ; else if (R16=='d') Read data from EEPROM brne L43 ldi R17,1 rcall EepromTalk rjmp L70
; read EEPROM ; R16 = EEPROM data ; uartSend(R16)
;-------------------------- Command ':' is universal command ---------------------------; Host sends 3 more bytes which must be used to determine the required action. AVRProg ; uses the ':' with parameters to do things that could simply be done by r/F/N. ; We have to map recognized parameters to the refering action. L43: cpi R16,':' brne L44
; else if(R16==':') Universal Command
;.............. read in the parameters ............................... rcall uartGet mov uni_cmd1, r16
; R16 = uartGet() ; store the read byte
rcall uartGet mov uni_cmd2, r16
; R16 = uartGet() ; store the read byte
rcall uartGet mov uni_cmd3, r16
; R16 = uartGet() ; store the read byte
;..................................................................... clr r16
; preset r16 with zero, if
parameters are not ; recognized, zero will be returned to host ;..................................................................... cpi uni_cmd1, 0x58 brne cmd1_not_0x58
; check if 1st paramter is 0x58
cpi uni_cmd2, 0x00 brne cmd2_not_0x00_1
; check if 2nd paramter is 0x00
; -> 58 00 is read lock bits, ldi ZL,1
; Z pointer = 0001 (->
readFuseAndLock will read lock) rcall readFuseAndLock
; go get the requested bits
cmd2_not_0x00_1: cpi uni_cmd2, 0x08 brne cmd2_not_0x08 ; -> 58 08 is read fuse high bits, ldi ZL,3
; check if 2nd paramter is 0x08
; Z pointer = 0003 (->
readFuseAndLock will read high fuse) rcall readFuseAndLock
; go get the requested bits
cmd2_not_0x08: cmd1_not_0x58: cpi uni_cmd1, 0x50 brne cmd1_not_0x50
; check if 1st paramter is 0x50
cpi uni_cmd2, 0x00 brne cmd2_not_0x00_2
; check if 2nd paramter is 0x00
; -> 50 00 is read fuse bits, clr ZL
; Z-pointer = 0000 (->
readFuseAndLock will read fuse) rcall readFuseAndLock
; go get the requested bits
cmd2_not_0x00_2: cmd1_not_0x50: rcall uartSend
; uartSend(bits) send the read lock/
fuse bits rjmp L68
; uartSend('\r') and go up for
next command
;--------------------- Command 'F' is "read fuse bits" ---------------------------------L44: cpi R16,'F' ; else if(R16=='F') Read fuse bits brne L46 clr ZL ; Z-pointer = 0000 (-> readFuseAndLock will read fuse) rjmp L50
; rcall readFuseAndLock
;--------------------- Command 'r' is "read lock bits" ---------------------------------L46: cpi R16,'r' ; else if(R16=='r') Read lock bits brne L48 ldi ZL,1 ; Z pointer = 0001 (-> readFuseAndLock will read lock) rjmp L50
; rcall readFuseAndLock
;--------------------- Command 'N' is "read fuse high bits" ----------------------------L48: cpi R16,'N' ; else if(R16=='N') Read high fuse bits brne L52 ldi ZL,3 ; Z-pointer = 0003 (-> readFuseAndLock will read high fuse)
;-------- for all previous commands F,r,N hear we rcall the readFuseAndLock -------------; function that will read the bits that are indicated by the Z-register L50: rcall readFuseAndLock rjmp L70 ; uartSend(R16)
;--------------------- Command 't' is Return supported devices code --------------------; obviously we return only the device code of the mega8 here L52: cpi R16,'t' ; else if(R16=='t') Return supported devices code brne L54 ldi R16,DT rcall uartSend clr R16
; Device Type ; uartSend(DT) send Device Type of Mega8 ; command set of AVRProg
requires the termination of ; the t-command with a \0 not with a CR as other commands rjmp L70
; uartSend(0) and go up for
next command ; ---------------- ignored commands that are not sensible for boot loader --------------; The following 4 commands only make sense for a general programmer, not for a bootloader. ; As theres commands come with an additional byte as parameter, with have to fetch that ; byte from the UART to avoid messing up the UART reading. L54:
http://avr-asm.tripod.com/mg8boot.html (1 of 2)1/20/2009 9:15:38 PM
cpi R16,'l' breq L56
; 'l' = Write Boot Loader lockbits
cpi R16,'x' breq L56
; 'x' = Set LED
16 BIT MATH (AVR 202)
cpi R16,'y' breq L56
; 'y' = Clear LED
cpi R16,'T' brne L60
; 'T' = Select device type
L56: rcall uartGet rjmp L68
; R16 = uartGet() ; uartSend('\r') and go up for
next command
;--------------------- Command 'S' is Return software identifier -----------------------L60: cpi R16,'S' ; else if(R16=='S') Return software identifier brne L62 ldi ZL,low(2*Soft_Id) ldi ZH,high(2*Soft_Id)
; load address of String into Z-Register
L61: lpm R16,Z+
; read one character of the
tst R16 breq L72
; exit the character output
string and increment string pointer
loop charcter was '\0' rcall uartSend
; send the read character via the UART
rjmp L61
; go to start of loop for next
character
;--------------------- Command 'V' is Return software Version --------------------------L62: cpi R16,'V' ; else if (R16=='V') Return Software Version brne L63 ldi R16, VER_H
; send bootloader software version
higher number rcall uartSend ldi R16, VER_L
; send bootloader software version
lower number rjmp L70
; uartSend and go up for next
command ;--------------------- Command 'v' is Return hardware Version --------------------------L63: cpi R16,'v' ; else if (R16=='v') Return hardware Version brne L64 ldi R16, VERH_H
; send bootloader software version
higher number rcall uartSend ldi R16, VERH_L
; send bootloader software version
lower number rjmp L70
; uartSend and go up for next
command
;--------------------- Command 's' is Return Signature Byte ----------------------------L64: cpi R16,'s' ; else if (R16=='s') Return Signature Byte brne L65 ldi R16,SB1 rcall uartSend
; uartSend(SB1) Signature Byte 1
ldi R16,SB2 rcall uartSend
; uartSend(SB2) Signature Byte 2
ldi R16,SB3 rjmp L70
; uartSend(SB3) Signature Byte 3 ; uartSend and go up for next
command
;--------------------- Command '.' is new universal command ----------------------------; this command will be ignored, only the inteface will be handled correctly L65: cpi R16,'.' ; else if (R16=='.') New Universal Command brne L66 ;.............. read in the 4 parameters ............................... rcall rcall rcall rcall
uartGet uartGet uartGet uartGet
; ; ; ;
R16 R16 R16 R16
= = = =
uartGet() uartGet() uartGet() uartGet()
; ...................................................................... clr R16 rcall uartSend
; uartSend(/0)
rjmp L68
; uartSend('\r') and go up for
next command
;++++++++++++++ handling the different commands is done till here +++++++++++++++++++++++ ; only general completion for all commands below
;---------------------- failed commands can end up here --------------------------------; an '?' is send via the UART to indicate fail host, then main loop starts again L66: ldi R16,'?' rjmp L70
; else uartSend('?') ; uartSend(R16)
;--------- successfully completed commands without return value can end up here --------; an CR is sent via the UART to confirm execution to host, then main loop starts again L68: ldi R16,13
; uartSend('\r')
;------------ successfully completed commands with return value can end up here --------; the return value is sent via the UART to confirm execution to host ; then main loop starts again L70: rcall uartSend ; uartSend(R16) L72: rjmp L10
; jump up to beginning of main
loop ;-------------------------- end of main loop --------------------------------------------
;================= end of main program, only subroutines from here on ===================
;------------------ reads fuse or lock bits (depending on Z-Reg.) ------------readFuseAndLock: ; An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR ; Register, will read either the Lock bits or the Fuse bits ; (depending on Z0 in the Z pointer) into the destination register. rcall wait_for_spm
; make sure SPM is ready to accept a
new task clr ZH
; Z pointer high byte = 0
ldi R24,(1<
; set BLBSET and SPMEN in SPMCR ; read fuse and lock ; read program memory
ret ;------------- does an read or write on the EEPROM (depending on R17) --------; if R17 == 6 then Write, if R17 == 1 then Read EepromTalk: out EEARL,R26 ; EEARL = address low out EEARH,R27 ; EEARH = address high adiw R26,1 ; address++ sbrc R17,1 ; skip if R17 == 1 (read Eeprom) sbi EECR,EEMWE ; EEMWE = 1 (write Eeprom) out EECR,R17 ; EECR = R17 (6 write, 1 read) L90: sbic EECR,EEWE rjmp L90 in R16,EEDR
; wait until EEWE == 0 ; R16 = EEDR
ret ;---------------- send one character via UART (parameter is r16) -------------uartSend: sbis UCSRA,UDRE ; wait for empty transmit buffer (until UDRE==1) rjmp uartSend out UDR,R16
; UDR = R16, start transmission
ret ;---------------- read one character from UART (returned in r16) -------------uartGet: sbis UCSRA,RXC rjmp uartGet in R16,UDR
; wait for incoming data (until RXC==1) ; return received data in R16
ret ;-------------------- wait for SPM to be ready for new tasks -----------------; while( SPMCR_REG & (1<<SPMEN) ) wait_for_spm: in r16, SPMCR
; read the content of SPMCR into
register andi r16, (1<<SPMEN) brne wait_for_spm
; check if bit SPMEN is set ; and do more loops if bit not yet
cleared Wait_ee: sbic EECR, EEWE
; check that no EEPROM write access is
present rjmp Wait_ee ret
; ---------------------------- re-enable the RWW section ---------------------; When programming (page erase or page write) to the RWW section, the RWW section ; is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW ; section, the user software must wait until the programming is completed (SPMEN will be ; cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the ; next SPM instruction within four clock cycles re-enables the RWW section. ; If this is not done, all addresses will read $FF even if they contain other values. enable_rww: rcall wait_for_spm
; make sure SPM is ready to accept a
new task ldi r16, (1<
; set rwwsre and spmen in SPMCR to prepare ; for reenabling the rww section
spm
; initiate the
reenabling ret ;---------------------------------- Pause ------------------------------------; Delays the CPU the selected periode, parameter pa_10ms is in 10ms steps pause: ldi dummy, 0b00000101 out TCCR0, dummy
; set prescaler to 1024
ldi dummy, 184 out TCNT0, dummy
; preset the counter for 72 remaining ; cycles till overflow
in dummy, TIFR sbr dummy, (1<
; reset the overflow flag
pw: in dummy, TIFR sbrs dummy, TOV0 rjmp pw
; check if overflow flag is set ; if not, wait more
;--- do this 10ms as often as requested in parameter pa_10ms dec pa_10ms ; decrement the counter brne pause ; and do the loop again if not zero yet ret ;-------------------------- data for identifier string ---------------------------------Soft_Id: .db "AVRB_M8", 0 ;--------------- data for message on UART when bootloader starts -----------------------uart_msg: .db .db .db .db .db .db
"+--------------------------------------------------+",10,13 "| Bootloader for ATmega8, Version ", VER_H, '.',VER_L, " by DL5NEG "| Use AVRProg to download new software. |",10,13 "| Press E to leave the bootloader and to start the |",10,13 "| application software from the flash memory. |",10,13 "+--------------------------------------------------+ ",10,13,10,13,0
|",10,13
;------------- data for message on UART when leaving the bootloader --------------------goodbye_msg: .db "Thanks for using DL5NEGs bootloader. ",10,13,10,13,0
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have ondie EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R, $FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have ondie EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/mg8boot.html (2 of 2)1/20/2009 9:15:38 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
PAGED BOOTLOADER HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; **************************************************************************** ;* Simple page-oriented boot loader for AVR parts with boot block. ;* (c) 2005 Mike Dvorsky ;* ;* Target: Any AVR with boot loader capability. ;* ;* Function: Accepts serial commands to erase, write, or read FLASH memory, ;* or to transfer control to a specified address. ;* ;* Supported commands: ;* 1. Erase page at address AAAA ;* command: "eAAAA\n" ;* response: "." ;* 2. Read page at address AAAA; response is 1 page (32 words) of data ;* command: "rAAAA\n" ;* response: "DDDD...DDDD." ;* 3. Write page at address AAAA with 1 page of data DDDD...DDDD ;* command: "wAAAA\nDDDD...DDDD\n" (\n = carriage return) ;* response: "." ;* 4. Transfer control to address AAAA. ;* command: "gAAAA\n" ;* response: none ;* ;* "AAAA" = 2-byte address in hex ;* "DDDD...DDDD" = page of data in hex = 32 words = 64 bytes = 128 hex digits ;* "\n" = carriage return = ASCII 0x0D ;* ;* Received characters are not echoed. Any line feeds (ASCII 0x0A) are ;* ignored. The command bytes MUST be lower case. The hex address and ;* data characters MUST be upper case. Any incorrect character will ;* cause the command to be terminated. ;* ;* Communication parameters = 8 data bits, 1 stop bit, no parity. Baud ;* rate is platform dependent, but will be 115.2 kBaud if that rate is ;* supported by the platform. ;* ;* At any time, the following sequence will terminate any partially ;* entered command and restore the boot loader to the state where it is ;* waiting for a new command. The sequence is ".\n" (a period character ;* followed by a carriage return). ;* ;* The order of data bytes for a page read or page write is LSB first. ;* ;* Following a page erase or page write command, the processor will be ;* unavailable for several milliseconds while the FLASH is being ;* modified. The device sending the data must account for this in one ;* of the following ways: ;* 1. Wait for receipt of the '.' character indicating the erase/write ;* command is complete. At this time the processor will be ready ;* to receive and process another command. ;* 2. Delay at least 5 milliseconds following the erase/write command ;* before starting the next command. ;* 3. Send enough "fill" bytes to ensure at least a 5 millisecond delay. ;* The fill byte must not be a valid command byte. Examples of valid ;* fill bytes are carriage return, line feed, space, '.', etc. The ;* fill bytes will be ignored, and should be terminated with a ;* carriage return. 60 fill bytes will be sufficient to ensure the ;* required delay at all Baud rates up to and including 115.2 kBaud. ;* ;* There are no restrictions on which pages can be read or written, but ;* in order to prevent accidental corruption of the boot section, it is ;* recommended that the boot lock bits be set to disallow SPM to write ;* to the boot loader section. ;* ;* In addition to the serial commands described above, the boot loader ;* makes two services available to the application: ;* 1. Jump to boot. If the application jumps to the last location in ;* FLASH, the boot loader will be started This allows the flash ;* process to be started without the need to install a jumper. ;* 2. Modify FLASH memory. If the application calls the next ;* to last location in FLASH, the boot loader will spin until any ;* previous SPM instruction completes, load the value in R16 into ;* SPMCR, and then execute an SPM instruction. (The SPM instruction ;* can only be used in the boot section, so this is the only way for ;* the application to modify FLASH memory.) ;* ;* When the SPM service is called, interrupts must be disabled and ;* there must be no EEPROM write in progress. It is the application's ;* responsibility to ensure this. Also, if the function being ;* performed is a write to the page buffer, then R0, R1, and Z must ;* be set to the appropriate values. ;* ;* Normally, after reset, the boot loader will branch to the reset vector ;* in the application section (unless it finds the reset vector erased). ;* There is a method to force the boot loader to remain in boot, which ;* varies with different platforms. Usually there will be one or more I/O ;* pins that can be jumpered or driven in a special way that indicates to ;* the boot loader that it should remain in boot and not jump to the ;* application. This is useful for recovering from a defective application. ; **************************************************************************** .include "m8def.inc"
;*
Processor-specific defines ; **************************************************************************** ;* Global constants ; **************************************************************************** .equ
BAUD_DIVISOR = 7
;* 14.7456
;.equ
BAUD_DIVISOR = 12
;* 4 MHz,
.equ
ASCII_LF = 10
;* ASCII
.equ
ASCII_CR = 13
;* ASCII
.equ .equ
PAGESIZEW = PAGESIZE PAGESIZEB = PAGESIZE*2
MHz, 115.2k 19.2k, for testing on STK200
carriage return line feed
; **************************************************************************** ;* Global register definitions ; **************************************************************************** .def .def .def .def .def .def
zeroreg imm1 imm2 imm3 counter command
= = = = = =
R2 R16 R17 R18 R19 R20
; **************************************************************************** ;* Start of code. Interrupts will be disabled for all boot loader ;* operations, so no interrupt vector table is needed. The code starts at ;* the reset vector address. ; **************************************************************************** .cseg .org SMALLBOOTSTART ;* Init a register with the value 0 clr zeroreg ; **************************************************************************** ;* Determine whether the boot loader should remain in boot or jump to the ;* application. There are two parts to this test: ;* 1. Check the first word of the application section (the reset ;* vector). If it is erased (i.e. 0xFFFF), assume there is not a ;* valid application and remain in boot. Otherwise continue with the ;* next test. ;* 2. Test the I/O pins for the presence of a jumper or other signal that ;* the code should remain in the boot loader. This is useful for ;* recovery from a run-away application. The specific I/O pins and the ;* test performed are platform specific. ;* ;* Also, before jumping to the application, it is necessary to set the vector ;* table to the application section. This can be done at any time, since the ;* boot loader does not use interrupts. ;* ;* The operations of setting the vector table and testing the first word of ;* the application are interspersed with the I/O pin test. They are used ;* to introduce delays after the pins are set up, in order to allow the ;* signals time to settle. ; **************************************************************************** ;* For the SSC-32 platform, pins PD3 and PD4 are normally left open or ;* jumpered to GND in order to select one of 4 Baud rates. If PD3 and PD4 ;* are jumpered together, this indicates to the boot loader that it should ;* remain in boot and not automatically jump to the application. ; **************************************************************************** ;* Test Baud Select pins (PD3, PD4); if jumpered together stay in boot ;* loader. ;* First, set PD4 for input w/o pullup, and PD3 for input w/pullup. out
DDRD, zeroreg
ldi
imm1, 0x08
out
PORTD, imm1
;* PORTD =
input ;*
Pullup on PD3
;************* ;* The next few instructions are placed here rather than separately, ;* in order to allow them to be used for doubleduty as delay instructions ;* to allow the input value to settle before the pin is read. ;* ;* Set vector table to app section ldi imm1, (1<
If it is erased (i.e. 0xFFFF), stay in
boot. ldi ZL, 0 ldi ZH, 0 lpm R28, Z+ lpm R29, Z adiw R28, 1 breq bootmain ;************* ;* Now the input value should have settled. Check PD3.
If the ;* PD3 value is 0, then the "stay in boot" jumper
is not ;* installed, so jump to the app.
If the PD3 value
is 1, then ;* we need to continue testing to determine whether the jumper ;* is installed. sbis PIND, PD3 rjmp $000
;* Jump to
app reset vector ;* Next, set PD4 for output with value 0. PD3.
Check
If the PD3 ;* value is 0, then the "stay in boot" jumper is
installed, so fall ;* through to boot.
If the PD3 value is 1, then
the "stay in boot" ;* jumper is not installed, so jump to the app. sbi DDRD, DDD4 ;* PD4 = output lpm
imm1, Z
;*
3 cycle delay for input to settle sbic rjmp
PIND, PD3 $000
;* Go to
the app reset vector ; **************************************************************************** ;* Bootloader main code. ; **************************************************************************** bootmain: ;* Clear zeroreg again in case of jump to boot from app clr zeroreg ;* Initialize the UART to 1 stop bit, no parity, interrupts ;* disabled, and the baud rate set by BAUD_DIVISOR. out UBRRH, zeroreg ldi imm1, low(BAUD_DIVISOR) out UBRRL, imm1 out UCSRA, zeroreg ldi imm1, (1<
UCSRC, imm1
;* Branch back to this point if an invalid command is received. wait_for_command_byte: ;* Set stack pointer to a known location in RAM. ;* NOTE: prior to this point, the stack pointer is invalid, so no ;* instructions may be used that depend on the stack (i.e. rcall, ;* ret, push, pop). ;* NOTE: the stack pointer is re-initialized at the end of every ;* command.
This allows subroutines to "bail out"
in case of error, ;* without needing to worry about fixing the stack. out SPH, zeroreg ldi imm1, 0xFF out SPL, imm1 ;* Receive and process a command byte.
Ignore any
unrecognized bytes. command_loop: rcall rx_byte cpi imm1, ASCII_CR
;* Get command ;* If carriage
return, discard breq mov rcall
wait_for_command_byte command, imm1 get_addr
;* Get address for
command ;* Check for Go command cpi command, 'g' breq go_command ;* Check for Read Page command cpi command, 'r' breq read_page ;* Check for Write Page command cpi command, 'w' breq write_page ;* Check for Erase Page command cpi command, 'e' brne command_loop ; **************************************************************************** ;* Process the Erase command. ; **************************************************************************** erase_page: ;* Page erase. Address is in Z. ldi imm1, ( 1 << PGERS ) | ( 1 << SPMEN ) rcall do_spm ;* Enable the RWW section.
Needed following a page
erase or page write. ;* The call to do_spm will not return until the read or write is ;* complete, so the '.' character will not be transmitted until the ;* read/write is complete. enable_rww: ldi imm1, ( 1 << RWWSRE ) | ( 1 << SPMEN ) rcall
do_spm
;* Send a '.' character to the UART to indicate previous command (if ;* any) is complete.
Branch back to this point if
a valid command ;* has been received and processed. tx_command_complete: ldi imm1, '.' rcall tx_byte rjmp wait_for_command_byte ; **************************************************************************** ;* Process the Read command. ; **************************************************************************** read_page: ;* Interate through the page, sending bytes. Starting address is in Z. ldi counter, PAGESIZEB read_page_loop: lpm imm1, Z+ rcall tx_hex_2 dec counter brne read_page_loop ;* Transmit "command complete" byte and Resume command processing rjmp
tx_command_complete
; **************************************************************************** ;* Process the Write command. ; **************************************************************************** write_page: ;* Read and store 1 page worth of data. Starting address is in Z. ldi counter, PAGESIZEW write_page_loop: rcall rx_hex_4 ;* Data into imm2: imm1 mov R0, imm2 mov R1, imm1 ldi imm1, ( 1 << SPMEN ) rcall do_spm adiw ZL, 2 dec counter brne write_page_loop ;* Wait for carriage return, bail out if any other character received rcall
wait_cr
;* Complete page of data received without error; write page subi sbci ldi
ZL, low ( PAGESIZEB ) ZH, high ( PAGESIZEB ) imm1, ( 1 << PGWRT ) | ( 1 <<
rcall
do_spm
SPMEN )
;* Transmit "command complete" byte and Resume command processing rjmp
enable_rww
; **************************************************************************** ;* Wait for a carriage return. If any other character is received, jump ;* to the error routine. ; **************************************************************************** wait_cr: rcall rx_byte cpi imm1, ASCII_CR brne wait_for_command_byte ret ; **************************************************************************** ;* Read a hex digit from the UART. If the value is '0' - '9' or 'A' - 'F', ;* convert to an integer 0-15 in register 'imm1'. Otherwise jump to the ;* error routine. ; **************************************************************************** rx_hex_1: rcall rx_byte ;* Test subi brcs cpi brcs
for '0' - '9' imm1, '0' wait_for_command_byte imm1, 10 rx_hex_1_end
;* Byte subi brcs cpi brcc
was greater than '9', test for 'A' - 'F' imm1, ( 'A' - '0' - 10 ) wait_for_command_byte imm1, 16 wait_for_command_byte
rx_hex_1_end: ret ; **************************************************************************** ;* Process the Go command. Jump to the address specified (in Z). ; **************************************************************************** go_command: ijmp ; **************************************************************************** ;* Read a 2-byte (4 hex digits) address from the UART and store it in Z. ;* Wait for carriage return after address is received. ; **************************************************************************** get_addr: rcall rx_hex_4 movw ZL, imm1 ;* Store address in Z rjmp wait_cr ;* Wait for carriage return
; **************************************************************************** ;* Read 4 hex digits from the UART. Return the value in 'imm2:imm1'. ; **************************************************************************** rx_hex_4: rcall rx_hex_2 mov imm2, imm1 ; Fall through to rx_hex_2 ; **************************************************************************** ;* Read 2 hex digits from the UART. Return the value in 'imm1'. ; **************************************************************************** rx_hex_2: rcall rx_hex_1 swap imm1 mov imm3, imm1 rcall rx_hex_1 or imm1, imm3 ret ; **************************************************************************** ;* Read a byte from the UART. Return the byte in register 'imm1'. ;* This function will spin until a byte has been received by the UART. ; **************************************************************************** rx_byte: sbis UCSRA, RXC rjmp rx_byte in imm1, UDR cpi imm1, ASCII_LF ;* Discard line feeds breq rx_byte ret ; **************************************************************************** ;* Send 2 hex digits to the UART. The byte to be sent must be in register ;* 'imm1'. ; **************************************************************************** tx_hex_2: mov imm2, imm1 swap imm1 ;* Send high order nibble first rcall tx_hex_1 mov imm1, imm2 ;* Send low order nibble next ; Fall through to tx_hex_1 ; **************************************************************************** ;* Send a hex digit to the UART. The digit to be sent will be the low ;* nibble of register 'imm1'. The high nibble will be ignored. ; **************************************************************************** tx_hex_1: andi imm1, 0x0F subi imm1, ( - '0' ) ;* Convert 0-9 to ASCII cpi imm1, ( '0' + 10 ) ;* Was it >9 ? brcs tx_byte subi imm1, ( '0' - 'A' + 10 ) ;* Convert A-F to ASCII ; Fall through to tx_byte ; **************************************************************************** ;* Send a byte to the UART. The byte to be sent must be in register 'imm1'. ;* This function will spin until the UART is ready to transmit. ; **************************************************************************** tx_byte: sbis UCSRA, UDRE rjmp tx_byte out UDR, imm1 ret ; **************************************************************************** ;* Issue the SPM instruction. The SPM command register value must be in ;* 'imm1'. Interrupts must be disabled, and no EEPROM write may be in ;* process. For a write to the page buffer, R0, R1, and Z must be set up ;* prior to calling do_spm. ; **************************************************************************** do_spm: ;* Wait for previous SPM to complete in imm2, SPMCR sbrc imm2, SPMEN rjmp do_spm ;* Write the SPMCR value from 'imm1' and issue the SPM instruction out spm
SPMCR, imm1
ret ; **************************************************************************** ;* Application services table. This is a jump table for services that ;* are made available to the application. The entry points for these ;* services are fixed addresses at the end of FLASH memory. ; **************************************************************************** ; **************************************************************************** ;* Write to program memory. This function will wait for any previous SPM ;* instruction to complete, then load SPMCR with the value in R16 and ;* issue the SPM instruction. R0, R1, and Z must be set up appropriately ;* for the function being performed. ;* Note: no EEPROM access may in in process, and interrupts must be disabled ; **************************************************************************** .org FLASHEND-1 appsrv_spm: rjmp do_spm
; **************************************************************************** ;* Start the boot loader. ; **************************************************************************** .org FLASHEND appsrv_go_boot: rjmp bootmain
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian http://avr-asm.tripod.com/bootdr8.html (1 of 2)1/20/2009 9:16:15 PM
16 BIT MATH (AVR 202)
Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/bootdr8.html (2 of 2)1/20/2009 9:16:15 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
ALARM CLOCK HOME RETRO_DAN ;-------------------------------------------------------; ; Developed by Claes Sundman , [email protected] ; ; Version 0.1 ; ; Alarmclock with calender and temp. and humidity sensor ; ; AT90S4433 PIN Project
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b
PIN
Project ; ; RESET
MATH 201 MATH 202 MATH 32X
PC5
26
DIV 24 24
25
PC3
24
PC2
INT ASCII HX2ASC
23
PC0
21
AREF
20
; PD1
3
RS
; PD2
4
R/W
; PD3
5
E
; PD4
6
D4
; VCC
7
; GND
8
; X1
9
; X2
10
; PD5
11
D5
; PD6
12
D6
; PD7
13
D7
; PB0
14
I/0
COPY 102
17
LED
PB5 PB4
I2C_SDA
PB3
I2C_SCL
16
PB2
PB1
SCLK DS1302 TST
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 direction bit in TWIadr
UART BUFF
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
.equ
SDAP
= 4
; SDA Pin number
.def .def
TWIdelay TWIdata
= r22 = r23
; Delay loop variable ; TWI data transfer
.def
TWIadr
= r24
; TWI address and
.def
TWIstat
= r25
; TWI bus status register
; SHT11 needs 11ms of delay after power up! ; SoftReset then wait 11ms
I2C/TWI 128
ETHNET 8019
; write bit ; write bit ; SCL Pin number
direction register
I2C TWI26
DALLAS CRC
= 1 = 0 = 3
register
I2C 302
DALLAS-1W
TWIrd TWIwr SCLP
(port B)
ISP 1200
I2C/TWI AT8
.equ .equ .equ (port B)
AVR ISP
I2C 300
15
; ;-------------------------------------------------------.include "4433def.inc" ;.include "i2c.inc" ;-------------------------------------------------------.DSEG .def tmp1 = r16 .def tmp2 = r17 .def tmp3 = r18 .def tmp4 = r19 .def tmp5 = r20 .def tmp6 = r21 ; Delay loop variable .equ b_dir = 0 ; transfer
FLASH CARD
AVR SPI
DS1302
DS1302
DFLASH AT45
ISP 2313
22
+5.0V
LPM 108
USB 232
PC4
AVCC
19 18
UART 128
27
AGND
FFT7
SER EPROM
-
PC1
AVG8 222
EPROM 100
2
Button4
MATH 202 DEC ASCII
; PD0
Button3
FLOAT 128
MATH 202
28
Button2
DIV16 XX
SQRT16
Resetbutton
Button1
MATH YX
DIV 3216
1
; .equ ADDR_SHT11_temp (00000011) ; .equ ADDR_SHT11_humi address byte Humidity read (00000101) ; .equ ADDR_SHT11_status_read = 0x03 byte Status read (00000111) ; .equ ADDR_SHT11_status_write = 0x07 byte Status write (00000110) ; .equ ADDR_SHT11_softreset = 0x0F byte SoftReset write(00011110) ; .equ ADDR_24LC16 24LC16, EEPROM address (10100000) ; .equ 24LC16_memsize EEPROM size
= 0x01
; SHT11
= 0x02
; SHT11
address byte Temp. read
; SHT11 address ; SHT11 address ; SHT11 address = 0x50
;
= 16384 ; 2048x8,
IRD 410 ; M24C16B Microchip max 400khz and 5ms to write. ; Address: 000 - 7FF = 24LC26B ;-------------------------------------------------------.cseg .org $000 rjmp reset ;rjmp INT_0 ; Ext. Interrupt 0 ;rjmp INT_1 ; Ext. Interrupt 1 ;reti TIMER1_CAPT ; Timer/Counter1
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU
Capture
ALM CLK
DELAYS
;reti
TIMER1_OVF
; Timer/Counter1
;reti
TIMER0_OVF
; Timer/Counter0
;reti
SPI_STC
; SPI Transfer
;rjmp
UART_RX
; UART Receive,
;reti ;reti ;reti ;reti ;reti
UART_UDRE UART_TX ADAC EEE_RDY ANA_COMP
; ; ; ; ;
Overflow Complete serial data in
CALL ID DTMF 314 PWM 6CH PWM 10K
; Timer/Counter1
Overflow
CLOCK 8564 90 DAYS
TIMER1_COMP
Overflow
BOOT MG8 BOOT DR8
;reti
UART empty UART Transmit ADC Ready EE2 Ready Analog
comparator ;-------------------------------------------------------; Program memory starts here reset: ldi tmp1, low(RAMEND) out SPL, tmp1 ldi tmp1, 0xFF ; Init keys out PORTC, tmp1 ; -"out DDRC, tmp1 ; -"out DDRB, tmp1 ldi tmp1, 0x00 out PORTB, tmp1 CLR tmp1 CLR tmp2 CLR tmp3 ;-------------------------------------------------------main: rcall init_port rcall lcd_init ; rcall lcd_ready ; rcall alarm_led_off rcall ds1302_init ; rcall i2c rcall loop
ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
loop: ;rcall rcall rcall ;rcall rjmp
keys ds1302_read_to_lcd ds1302_days_to_lcd temp loop
;-------------------------------------------------------alarm_led_on: sbi portc, 0 ret alarm_led_off: cbi portc, 0 ret ;-------------------------------------------------------keys: push tmp1 in tmp1, PORTC pop tmp1 ret ;-------------------------------------------------------temp: ldi tmp1, 0x8E rcall lcd_cmd ldi tmp1, 0b11011111 rcall lcd_char ldi tmp1, 'C' rcall lcd_char ret ;-------------------------------------------------------; Initial date/time code for lcd stored in format mon_day: .db "Monday *C";,0xA9 tues_day: .db "Tuesday *C";,0xA9 wednes_day: .db "Wednesday *C";,0xA9 thurs_day: .db "Thursday *C";,0xA9 fri_day: .db "Friday *C";,0xA9 satur_day: .db "Saturday *C";,0xA9 sun_day: .db "Sunday *C";,0xA9 ds1302_days_to_lcd: ldi tmp1, rcall lcd_cmd ldi tmp1,
0x80
; first line
$8B
; read
days rcall ldi cp breq ldi cp breq ldi cp breq ldi cp breq ldi cp breq ldi cp breq ldi cp breq
RdCmd tmp2, tmp1,
0b00000001 tmp2
tmp2, tmp1,
0b00000010 tmp2
tmp2, tmp1, wednesday tmp2, tmp1, thursday tmp2, tmp1, friday tmp2, tmp1, saturday tmp2, tmp1, sunday
0b00000011 tmp2
; test days...
monday
tuesday
0b00000100 tmp2 0b00000101 tmp2 0b00000110 tmp2 0b00000111 tmp2
ret monday: ldi rcall ldi ldi ldi rcall ret tuesday: ldi ldi ldi rcall ret wednesday: ldi ldi ldi rcall ret thursday: ldi ldi ldi rcall ret friday: ldi ldi ldi rcall ret saturday: ldi ldi ldi rcall ret sunday: ldi ldi ldi rcall ret
tmp1,
0x00
lcd_cmd r30, r31, tmp2, LCD_PrintPM
low (mon_day*2) high(mon_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (tues_day*2) high(tues_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (wednes_day*2) high(wednes_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (thurs_day*2) high(thurs_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (fri_day*2) high(fri_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (satur_day*2) high(satur_day*2) 16
r30, r31, tmp2, LCD_PrintPM
low (sun_day*2) high(sun_day*2) 16
;-------------------------------------------------------; Init the LCD in 4-bit mode BEGINNING lcd_init: push tmp1 ldi tmp1, 0x30 out portd, tmp1 rcall enable rcall wait rcall wait ldi out rcall rcall
tmp1, portd,
0x30 tmp1
ldi out rcall rcall
tmp1, portd,
0x30 tmp1
tmp1,
0x20
tmp1,
0x28
tmp1,
0x14
tmp1,
0x0c
tmp1,
0x06
tmp1,
0x01
tmp1,
0x80
enable wait
ldi rcall
enable wait
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall
lcd_cmd
ldi rcall pop
lcd_cmd
lcd_cmd tmp1
ret ;-------------------------------------; Init the LCD in 4-bit mode READY lcd_ready: ldi tmp1, 'L' rcall lcd_char ldi tmp1, 'C' rcall lcd_char ldi tmp1, 'D' rcall lcd_char ldi tmp1, ' ' rcall lcd_char ldi tmp1, 'T' rcall lcd_char ldi tmp1, 'e' rcall lcd_char ldi tmp1, 's' rcall lcd_char ldi tmp1, 't' rcall lcd_char ldi tmp1, '!' rcall lcd_char ret ;-------------------------------------------------------init_port: ldi tmp1, 0xff out ddrd, tmp1 ret ;-------------------------------------------------------lcd_cmd: push tmp1 push tmp2 rcall lcd_busyread mov tmp2, tmp1 ;Load the value to the tmp2 also. andi
tmp2,
0xf0
;select the upper 4bits of the
tmp2, portd,
0x00 tmp2
tmp2, 0x0f
tmp1 ;load sent value to tmp2 ;select the 4 lower bits ;swap the lower D3-D0
tmp2, portd,
0x00 tmp2
sent byte ori out rcall mov andi swap
;mask the tmp2 RS=0 ;put result out to portc
enable tmp2, tmp2
bits to D7-D4 ori out rcall pop pop rcall
;mask the tmp2 RS=0 ;put result out to portc
enable tmp2 tmp1 wait_short
ret ;-------------------------------------------------------lcd_char: push tmp1 push tmp2 rcall lcd_busyread mov tmp2, tmp1 ;Load the value to the tmp2 also. andi
tmp2,
0xf0
;select the upper 4bits of the
tmp2, portd,
0x02 tmp2
tmp2, 0x0f
tmp1 ;load sent value to tmp2 ;select the 4 lower bits ;swap the lower D3-D0
tmp2, portd,
0x02 tmp2
sent byte ori out rcall mov andi swap
;mask the tmp2 RS=1 ;put result out to portc
enable tmp2, tmp2
bits to D7-D4 ori out rcall pop pop
;mask the tmp2 and RS=1 ;put result out to portc
enable tmp2 tmp1
ret ;-------------------------------------------------------lcd_busyread: push tmp1 ldi tmp1, 0x00 ;clear portC out portd, tmp1 ;make it happen ldi tmp1, 0x0f ;turn D7-D4 to inputs out ddrd, tmp1 ;make it happen lcd_busyread_wait: sbi portd, 2 ;R/W = 1 sbi portd, 3 ;Enable = 1 nop nop nop nop nop nop nop in tmp1, pind ;read from LCD cbi portd, 3 ;Enable = 0 nop nop nop nop rcall enable ;to complete reading the byte andi cpi brne ldi out pop
tmp1,
0x80 ;want only D7 tmp1, 0x00 ;is it zero ? lcd_busyread_wait ;jump if not equal to zero tmp1, 0xff ;make portC to output ddrd, tmp1 ;make it happen tmp1
ret ;-------------------------------------------------------; Toggle the Enable on the LCD enable: sbi portd, 3 ;pin D3 = 1 push tmp1 ldi tmp1, 10 enable_loop: dec tmp1 brne enable_loop pop tmp1 cbi portd, 3 ;pin D3 = 0 ret ;-------------------------------------------------------wait_short: push tmp1 ldi tmp1, 0x80 wait_short_loop: dec tmp1 brne wait_short_loop pop tmp1 ret wait: push tmp2 ldi tmp2, 0xff wait_loop: rcall wait_short dec tmp2 brne wait_loop pop tmp2 ret ;-------------------------------------------------------; LCD_PrintMem. Prints from memory. Put the starting, ; memory location in Z (r31:r30). Put the number of ; characters to print in tmp2. After execution, ; Z is at the character AFTER the last to be ; printed and tmp2 is zero. This function will ; not wrap if you the string is bigger than the LCD. LCD_PrintMem: push tmp1 LCD_MemRead: ld tmp1, Z+ rcall lcd_char dec tmp2 brne LCD_MemRead pop tmp1 ret ;-------------------------------------------------------; LCD_PrintPM. Prints from program memory LCD_PrintPM: push r0 push tmp1 LCD_PMRead: lpm mov tmp1, r0 rcall lcd_char adiw r30, 1 dec tmp2 brne LCD_PMRead pop tmp1 pop r0 ret ;-------------------------------------------------------; Macros, delay 0.125 x 40 = 5us 200khz and max are 400khz ;.MACRO rtc_delay: push tmp1 ldi tmp1, 0xFF;40 Load with 4 to generate 2MHz to DS1302 rtc_delay_2: dec tmp1 brne rtc_delay_2 pop tmp1 ret ;.ENDMACRO ;-------------------------------------------------------; DS1302 macro .MACRO IO_in cbi DDRB, 0 ; Make I/O line input. .ENDMACRO .MACRO
IO_out sbi
DDRB,
0
; Make I/O line
2
; Set SCLK output.
output. .ENDMACRO .MACRO
SCLK_high nop nop nop nop nop sbi nop
PORTB, nop nop nop nop
.ENDMACRO .MACRO
SCLK_low nop nop nop nop nop cbi nop nop
PORTB,
2
PORTB,
0
PORTB,
0
PORTB,
1
PORTB,
1
nop nop nop .ENDMACRO .MACRO
IO_high sbi .ENDMACRO .MACRO
IO_low cbi .ENDMACRO .MACRO
RST_high nop nop nop nop nop sbi nop nop nop nop nop .ENDMACRO .MACRO
RST_low nop nop nop nop nop cbi nop nop nop nop nop .ENDMACRO
;-------------------------------------------------------; Write a cmd / data combo from tmp1 / tmp2 to the RTC. WrtCmd: RST_high mov tmp3, tmp1 ; write command to RTC rcall WrtByte mov tmp3, tmp2 ; write data to RTC rcall WrtByte RST_low ret ; Clock out the byte in tmp3 to the RTC. ; Data is clocked out starting with bit 0. ; Data is clocked into the RTC on the rising edge. WrtByte: ldi tmp1, 8 WrtByte1: lsr tmp3 brcc WrtByte2 IO_high rjmp WrtByte3 WrtByte2: IO_low WrtByte3: SCLK_high dec tmp1 breq WrtByte4 SCLK_low rjmp WrtByte1 WrtByte4: IO_high SCLK_low applicable). @@ Claes , last bit is still here after last clock clc ret
; 8 bits to clock out. ; rotate.............bit 0 into C ; skip if bit = 0
; Clock it out. ; Do all the bits. ; turn on pull up. ; Clock data in (if
; Read a byte following write of command byte. RdCmd: RST_high IO_out mov tmp3, tmp1 rcall WrtByte IO_in rcall RdByte mov tmp1, tmp3 RST_low IO_out ret ; Clock in a byte from the RTC to tmp3 RdByte: ldi tmp3, 0
; Empty register
for data ldi
tmp1,
8
; 8 bits to clock
in. RdByte1: clc
; Clear
carry. sbic sec
PINB,
ror
tmp3
0
; Jump if I/O = 0. ; Set
Carry Flag ; Rotate data
into bit. SCLK_high
; clock in next
SCLK_low dec tmp1 brne RdByte1
; more bits ?
bit.
ret ;-------------------------------------------------------ds1302_init: ldi tmp1, $8E ; remove write protection ldi rcall ldi ldi rcall ldi ldi rcall ldi ldi rcall ldi ldi rcall
WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd
ldi ldi rcall ldi ldi rcall ldi ldi rcall
tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd tmp1, tmp2, WrtCmd
tmp2,
$00
;
$80 0x55
; write seconds ; 00; 0xxx xxxx
$82 0x59
; write minutes ; 00; 0xxx xxxx
$84 0x23
; write hours, 24h mode ; 00xx xxxx
$8A 0x01
; write day ; monday 01 - 07
$86 0x27
; write date for day ; 00xx xxxx
$88 0x02
; write month ; 000x xxxx
$8C 0x03
; write year ; xxxx xxxx
ret ; Info: ; sec. ; min. ; hour ; days
0xxx 0xxx 00xx 0000
BCD xxxx xxxx xxxx 0xxx
BCD
ds1302_read_to_lcd: ldi tmp1, 0xC0 rcall lcd_cmd ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $85 ; read 10 hour. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $85 ; read 1 hour. rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, 0xC2 ; colon rcall lcd_cmd ldi tmp1, ':' rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $83 ; read 10 minutes. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $83 ; read 1 minutes. rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, 0xC5 ; colon rcall lcd_cmd ldi tmp1, ':' rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $81 ; read seconds. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $81 rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, 0xCB ; date@lcd rcall lcd_cmd ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $87 ; read date. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi tmp1, $87 rcall RdCmd andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, '/' rcall lcd_char ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ldi tmp1, $89 ; read month. rcall RdCmd swap tmp1 andi tmp1, 0x3F ori tmp1, 0x30 rcall lcd_char ldi rcall andi ori rcall
$89
0x3F tmp1,
0x30
RdCmd tmp1,
tmp1,
lcd_char
ret ; *************************************************************************** ;* Supports both 7-bit and 10-bit addressing. ;* TWI functions : ;* 'TWI_start' Issues a start condition and sends address ;* and transfer direction. ;* 'TWI_rep_start' Issues a repeated start condition and sends ;* address and transfer direction. ;* 'TWI_do_transfer' Sends or receives data depending on ;* direction given in address/dir byte. ;* 'TWI_stop' Terminates the data transfer by issue a ;* stop condition. ;* Code Size : 81 words (maximum) ;* Register Usage : 4 High, 0 Low ;* ;* TWI_hp_delay: ;* TWI_qp_delay ;* hp - half TWI clock period delay (normal: 5.0us / fast: 1.3us) ;* qp - quarter TWI clock period delay (normal: 2.5us / fast: 0.6us) ; *************************************************************************** TWI_hp_delay: ldi TWIdelay, 2 TWI_hp_delay_loop: dec TWIdelay brne TWI_hp_delay_loop ret TWI_qp_delay: ldi TWIdelay, 1 TWI_qp_delay_loop: dec TWIdelay brne TWI_qp_delay_loop ret ; *************************************************************************** ;* TWI_rep_start Assert repeated start condition and sends slave address. ;* TWIadr - Contains the slave address and transfer direction. ;* Carry flag - Cleared if a slave responds to the address. ;* This funtion must be directly followed by TWI_start. ; *************************************************************************** TWI_rep_start: sbi DDRB, SCLP ; force SCL low cbi DDRB, SDAP ; release SDA rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL rcall TWI_qp_delay ; quarter period delay ; *************************************************************************** ;* FUNCTION ;* TWI_start ;* DESCRIPTION ;* Generates start condition and sends slave address. ;* USAGE ;* TWIadr - Contains the slave address and transfer direction. ;* RETURN ;* Carry flag - Cleared if a slave responds to the address. ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by TWI_write. ; *************************************************************************** TWI_start: mov TWIdata,TWIadr ; copy address to transmitt register sbi DDRB, SDAP ; force SDA low rcall TWI_qp_delay ; quarter period delay ; *************************************************************************** ;* FUNCTION ;* TWI_write ;* DESCRIPTION ;* Writes data (one byte) to the TWI bus. Also used for sending ;* the address. ;* USAGE ;* TWIdata - Contains data to be transmitted. ;* RETURN ;* Carry flag - Set if the slave respond transfer. ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by TWI_get_ack. ; *************************************************************************** TWI_write: sec ; set carry flag rol TWIdata ; shift in carry and out bit one rjmp TWI_write_first TWI_write_bit: lsl TWIdata ; if transmit register empty TWI_write_first: breq TWI_get_ack ; goto get acknowledge sbi DDRB, SCLP ; force SCL low brcc TWI_write_low ; if bit high nop ; (equalize number of cycles) cbi DDRB, SDAP ; release SDA rjmp TWI_write_high TWI_write_low: ; else sbi DDRD, SDAP ; force SDA low rjmp TWI_write_high ; (equalize number of cycles) TWI_write_high: rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL rcall TWI_hp_delay ; half period delay rjmp TWI_write_bit ; *************************************************************************** ;* FUNCTION ;* TWI_get_ack ;* DESCRIPTION ;* Get slave acknowledge response. ;* USAGE ;* (used only by TWI_write in this version) ;* RETURN ;* Carry flag - Cleared if a slave responds to a request. ; *************************************************************************** TWI_get_ack: sbi DDRB, SCLP ; force SCL low cbi DDRB, SDAP ; release SDA rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL TWI_get_ack_wait: sbis PINB, SCLP ; wait SCL high(In case wait states are inserted) rjmp TWI_get_ack_wait clc ; clear carry flag sbic PINB,SDAP ; if SDA is high sec ; set carry flag rcall TWI_hp_delay ; half period delay ret ; *************************************************************************** ;* FUNCTION ;* TWI_do_transfer ;* DESCRIPTION ;* Executes a transfer on bus. This is only a combination of TWI_read ;* and TWI_write for convenience. ;* USAGE ;* TWIadr - Must have the same direction as when TWI_start was called. ;* see TWI_read and TWI_write for more information. ;* RETURN ;* (depends on type of transfer, read or write) ;* NOTE ;* IMPORTANT! : This funtion must be directly followed by TWI_read. ; *************************************************************************** TWI_do_transfer: sbrs TWIadr, b_dir ; if dir = write rjmp TWI_write ; goto write data
http://avr-asm.tripod.com/almclk.html (1 of 2)1/20/2009 9:16:58 PM
16 BIT MATH (AVR 202)
; *************************************************************************** ;* TWI_reads data (one byte) from the TWI bus. ;* USAGE ;* Carry flag If set no acknowledge is given to the slave ;* indicating last read operation before a STOP. ;* If cleared acknowledge is given to the slave ;* indicating more data. ;* TWIdata Contains received data. ;* This funtion must be directly followed by TWI_put_ack. ; *************************************************************************** TWI_read: rol TWIstat ; store acknowledge (used by TWI_put_ack) ldi TWIdata, 0x01 ; data = 0x01 TWI_read_bit: ; do sbi DDRD, SCLP ; force SCL low rcall TWI_hp_delay ; half period delay cbi DDRD, SCLP ; release SCL rcall TWI_hp_delay ; half period delay clc ; clear carry flag sbic PIND,SDAP ; if SDA is high sec ; set carry flag rol TWIdata ; store data bit brcc TWI_read_bit ; while receive register not full ; *************************************************************************** ;* TWI_put_ack Put acknowledge.(used only by TWI_read in this version) ; *************************************************************************** TWI_put_ack: sbi DDRD, SCLP ; force SCL low ror TWIstat ; get status bit brcc TWI_put_ack_low ; if bit low goto assert low cbi DDRD, SDAP ; release SDA rjmp TWI_put_ack_high TWI_put_ack_low: ; else sbi DDRD, SDAP ; force SDA low TWI_put_ack_high: rcall TWI_hp_delay ; half period delay cbi DDRD, SCLP ; release SCL TWI_put_ack_wait: sbis PIND, SCLP ; wait SCL high rjmp TWI_put_ack_wait rcall TWI_hp_delay ; half period delay ret ; *************************************************************************** ;* TWI_stop Assert stop condition. ; *************************************************************************** TWI_stop: sbi DDRB, SCLP ; force SCL low sbi DDRB, SDAP ; force SDA low rcall TWI_hp_delay ; half period delay cbi DDRB, SCLP ; release SCL rcall TWI_qp_delay ; quarter period delay cbi DDRD, SDAP ; release SDA rcall TWI_hp_delay ; half period delay ret ; *************************************************************************** ;* TWI_init Initialization of the TWI bus interface. ;* Call this function once to initialize the TWI bus. No parameters ;* are required. PORTD and DDRD pins not used by the TWI bus interface will be ;* set to Hi-Z (!). This function can be combined with other PORTD initializations. ; *************************************************************************** TWI_init: clr TWIstat ; clear TWI status register (used as a temporary register) out PORTB, TWIstat ; set TWI pins to open colector out DDRB, TWIstat ret ; *************************************************************************** ;* main - Test of TWI master implementation ;* Initializes TWI interface and shows an example of using it. ; ; .equ ADDR_SHT11_temp = 0x01 ; (00000011) ; .equ ADDR_SHT11_humi = 0x02 ; (00000101) ; .equ ADDR_SHT11_status_read = 0x03 ; (00000111) ; .equ ADDR_SHT11_status_write = 0x07 ; (00000110) ; .equ ADDR_SHT11_softreset = 0x0F ; (00011110) ; .equ ADDR_24LC16 = 0x50 ; (10100000) ; .equ 24LC16_memsize = 16384 ; 2048x8, EEPROM size ; ; *************************************************************************** i2c: rcall TWI_init ; initialize ldi TWIadr,$A0+TWIwr ; Set device Adr (00) = 0x55 and write rcall TWI_start ; start ldi TWIdata,$00 ; Write word address (0x00) rcall TWI_do_transfer ; transfer ldi TWIdata,$55 ; Set write data to 01010101b rcall TWI_do_transfer ; transfer rcall TWI_stop ; stop ldi TWIadr,$A0+TWIwr ; Set device TWIdata = Adr(00) and write rcall TWI_start ; start ldi TWIdata,$00 ; Write word address rcall TWI_do_transfer ; transfer ldi TWIadr,$A0+TWIrd ; Set device address and read rcall TWI_rep_start ; repeated start sec ; Set no acknowledge (read is followed by a stop condition) rcall TWI_do_transfer ; transfer (read) rcall TWI_stop ; stop - releases bus ret ;**** End of File ****
Programming the AVR Microcontrollers in Machine Language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/ O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for longterm parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/ O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/ Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/almclk.html (2 of 2)1/20/2009 9:16:58 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
REAL TIME CLOCK FOR EPSON 8564 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45
; *************************************************************************** ; ; File Name :'RTC8564.asm" ; Title :Epson RTC8564JE Driver ; Date :2003.04.30. Lastmod.: [2003.04.30.] ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmaga128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; Real Time Clock Modul Driver ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.04.30 VFX Creation ; ; *************************************************************************** ; ; ; ;Hardware ; *************************************************************************** ;*
FLASH CARD VFX SMIL VFX MEM SORT 220
; ************************************************************************** ;* Const Def ;
CRC 236
.equ
RTC_SlaveAddr = 0b10100010
XMODEM REC UART 304
; RTC internal Registers ; All data address 0x02 through 05 & 0x08 through 0x0B
UART 305 UART 128
is in BCD format .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ .equ
UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
RTC_Control1 = 0x00 RTC_Control2 = 0x01 RTC_Seconds = 0x02 RTC_Minutes = 0x03 RTC_Hours = 0x04 RTC_Days = 0x05 RTC_WeekDays = 0x06 RTC_Months = 0x07 RTC_Years = 0x08 RTC_MinuteAlarm = 0x09 RTC_HourAlarm = 0x0A RTC_DayAlarm = 0x0B RTC_WeekdayAlarm= 0x0C RTC_CLKOUT_Freq = 0x0D RTC_TimerControl= 0x0E RTC_Timer = 0x0F
DALLAS-1W ;RTC Commands ;Control Register 1 .equ RTC_StopRunning = 0b00100000 .equ RTC_ContRunning = 0b00000000
DALLAS CRC ETHNET 8019 TEA ADC 128
;Control Register 2 .equ RTC_AlarmIntEnable = .equ RTC_AlarmIntDisable=
ADC 10B ADC 400 ADC 401
0b00000010 0b00000000
;Seconds [addr 0x02] .equ RTC_LowBat = 0b10000000
THERM 232 IRD 410
;century [Addr 0x07] .equ RTC_Cetury
LCD HD44
= 0b10000000
LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2
; *************************************************************************** .DSEG
KBD PC/128
IO_CTR_RTC: .byte 17
PS2 EMU
controll
BOOT MG8
Line end
;IO buffer for RTC ;Time -> 00:00:00 + ;Date -> 2000-01-01
BOOT DR8 ALM CLK
+ Line end
CLOCK 8564 90 DAYS DELAYS CALL ID
; ************************************************************************* ;* Text Const ;* .CSEG
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ************************************************************************* ;* Read RTC All dataa ;* RTC_ReadALL: ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R17,16 ;reads 16 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,0 ;Begining fo read rcall TWI_StartRead ret ; ************************************************************************* ;* Start RTC ;* RTC_Start: rcall WaitToTWI ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R16,RTC_ContRunning st X,R16 ldi R17,1 ;write 16 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,0 ;Begining of write rcall TWI_StartWrite ret ; ************************************************************************* ;* Stop RTC ;* RTC_Stop: rcall WaitToTWI ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R16,RTC_StopRunning st X,R16 ldi R17,1 ;write 1 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,0 ;Begining of write rcall TWI_StartWrite ret ; ****************************************************************** ;* RTC Low Battery detector ; ; Out: ; z = 1 TWI Error ; z = 0 No error and ; c=1 Battery Low ; c=0 Battery Ok RTC_BatLow: ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R17,1 ;read 1 byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19, RTC_Seconds ;Begining of read rcall TWI_StartRead rcall WaitToTWI brcs RTC_BatLow1 ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ld R16,X rol R16 ;csak a c=VL bit marad clz ret RTC_BatLow1: sez ;TWI Error ret LowBatS:
.db
"RTC Battery is Low - Check Date/
Time",CR,0 noRTC:
.db
"RTC not found - setup date/
time manualy ",CR,0 ; *************************************************************************** ; RTC Get Time ; ; In: ; Out: var X -> IO_CTR_RTC (00:00:00+zero byte) ASCCI ; R4:R3:R2 - hh:mm:ss BCD ; Used: RTC_GetTime:
R17,3 RTC_SlaveAddr
+0
+1
+2
rcall ldi ldi ldi
RTC_Stop XL,Low(IO_CTR_RTC+1) XH,High(IO_CTR_RTC+1)
ldi
R18,
ldi rcall rcall
R19,RTC_Seconds TWI_StartRead RTC_Start
ldi ldi ldd
ZL,Low(IO_CTR_RTC+1) ZH,High(IO_CTR_RTC+1) R16,Z
andi mov ldd
R16,0b01111111 R2,R16 R16,Z
andi mov ldd
R16,0b01111111 R3,R16 R16,Z
andi mov mov rcall std std ldi std mov rcall std std std mov rcall std std clr std movw ret
R16,0b00111111 R0,R16 R4,R16 BCDToASCII Z+0,R1 Z+1,R0 R17,':' Z+2,R17 R0,R3 BCDToASCII Z+3,R1 Z+4,R0 Z+5,R17 R0,R2 BCDToASCII Z+6,R1 Z+7,R0 R16 Z+8,R16 XL,ZL
;noumber of byte ;Slave Address
;sec
;min
;hrs
; *************************************************************************** ; RTC Set Time ; ; In: R4:R3:R2 -> hh:mm:ss BCD ; Out: c = 0 sucess ; c = 1 error ; Used: ; RTC_SetTime: rcall RTC_Stop ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) rcall WaitToTWI st X+,R2 st X+,R3 st X,R4 ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) ldi R17,3 ;noumber of byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,RTC_Seconds rcall TWI_StartWrite rcall RTC_Start ret ; *************************************************************************** ; RTC Set Date ; ; In: R4:R3:R2 -> yy:mm:dd BCD ; R5 - Century bit 0/1 ; Out: c = 0 sucess ; c = 1 error ; Used: ; RTC_SetDate: clr R16 ror R5 ror R16 or R3,R16 rcall RTC_Stop ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) rcall WaitToTWI st X+,R3 st X,R4 sbiw XL,1 ldi R17,2 ;noumber of byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,RTC_Months rcall TWI_StartWrite rcall WaitToTWI ldi XL,Low(IO_CTR_RTC) ldi XH,High(IO_CTR_RTC) st X,R2 ldi R17,1 ;noumber of byte ldi R18, RTC_SlaveAddr ;Slave Address ldi R19,RTC_Days rcall TWI_StartWrite rcall RTC_Start ret ; *************************************************************************** ; RTC Get Date ; ; In: ; Out: var X -> IO_CTR_RTC (yyyy-mm-dd+zero byte) ASCCI ; R4:R3:R2 - yy-mm-dd BCD ; R5 - Century bit ; Used: RTC_GetDate:
R17,4 RTC_SlaveAddr
+0
rcall ldi ldi ldi
RTC_Stop XL,Low(IO_CTR_RTC+1) XH,High(IO_CTR_RTC+1)
ldi
R18,
ldi rcall rcall
R19,RTC_Days TWI_StartRead RTC_Start
ldi ldi ldd
ZL,Low(IO_CTR_RTC+1) ZH,High(IO_CTR_RTC+1) R16,Z
andi mov ldd mov andi mov rol clr rol tst brne ldi std ldi rjmp
R16,0b00111111 R2,R16 R16,Z+2 R5,R16 R16,0b00011111 R3,R16 R5 R5 R5 R5 XXICentury R16,'1' Z+0,R16 R16,'9' CenturyOk
ldi std ldi
R16,'2' Z+0,R16 R16,'0'
std
Z+1,R16
ldd
R16,Z
mov mov rcall std std ldi std mov rcall std std std mov rcall std std clr std movw ret
R0,R16 R4,R16 BCDToASCII Z+2,R1 Z+3,R0 R17,'-' Z+4,R17 R0,R3 BCDToASCII Z+5,R1 Z+6,R0 Z+7,R17 R0,R2 BCDToASCII Z+8,R1 Z+9,R0 R16 Z+10,R16 XL,ZL
;noumber of byte ;Slave Address
;days
XXICentury:
CenturyOk:
+3
;years
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two http://avr-asm.tripod.com/clock8564.html (1 of 2)1/20/2009 9:17:33 PM
16 BIT MATH (AVR 202)
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/clock8564.html (2 of 2)1/20/2009 9:17:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
90 DAY TIMER HOME RETRO_DAN ASM FORUM
; A 90 Day timer with 4 LEDs based on the AVR 90S2343 or Tiny22
ASM MATH
; Inputs - RESET button - pulls to ground when
TUTORIAL #1
pressed.
TUTORIAL #2
timer is running
TUTORIAL #3
; Outputs -
MATH 201
MATH YX
This design
improves on the App ; ; ; ;
note by: 1) Using timer0 and sleep mode to use less power. 2) Using a possibly lower cost AVR part. 3) Offering blinking LEDs to reduce power
consumption. (Future implementation) ; A constant-on mode is also available. ; Written 8/12/99 by Brian Hammill (hammill@ipass. net)
This code is ; copyright (C) 1999 by Brian Hammill.
Please give
credit to the ; author whenever using or distributing this code. Otherwise, you
INT ASCII HX2ASC
90 Day LED - Blinks when 90
; Note for the ACE1101 processor.
SQRT16
DEC ASCII
;
; This is based on an idea from a Fairchild
FLOAT 128
MATH 202
60 Day LED - Blinks when 60
Semiconductor Application
DIV 24 24
MATH 202
;
days have passed
DIV16 XX
DIV 3216
30 Day LED - Blinks when 30
days have passed
MATH 202 MATH 32X
; days have passed
MATH 200 MATH 200b
Status LED - Blinks to show the
; are free to use and make changes to this code.
If
you make ; an improvement, be nice and send a copy to me.
AVG8 222 FFT7
; Using the 1 MHz Internal OSC and a timer prescaler of CK/1024
COPY 102
; Timer0 will overflow approximately every 250 mS. ; We start up, init the timer, and put the chip to
LPM 108 EPROM 100 SER EPROM
sleep. ; When the timer overflows the chip wakes up, increments the 1 mS ; counter and goes back to sleep. ; When the 250 mS counter reaches 240 (1 Minute ),
DFLASH AT45 FLASH CARD
then the 1 min. counter is ; incremented and the 250 mS counter is reset to 0. ; When the 1 minute counter reached 60 (1 hour) then
VFX SMIL VFX MEM
we increment ; the 1 hour counter and reset the 1 minute counter
SORT 220 to 0 CRC 236 XMODEM REC UART 304
; when the 1 hour counter reaches 240 (10 days) increment the ; 10 day counter and reset the 1 hour counter. The 1 hour and 10 day count
UART 305 UART 128
; is stored in EEPROM so that if the power fails, at most an hour's count ; is lost. ; The timer ISR will check the EEPROM to see when the
UART BUFF USB 232
elapsed
AVR ISP
blink the
; time reaches 30, 60, and 90 days and set a flag to ; appropriate LED.
ISP 2313 ISP 1200
timer values and the ; EEPROM location and start counting from 0 again. ; Blinking the LEDs is handled in the 250 mS timer
AVR SPI I2C 300
ISR.
A low duty cycle is ; used to flash the LEDs so that power can be reduced. ; ; Written for the Atmel AVR Assembler version 1.30. ; This code illustrates a way to generate extremely
I2C 302 I2C TWI26 I2C/TWI 128
long delays. ; It also shows how to read/write the AVR EEPROM and ; how to use timer0 with interrupts. This program
I2C/TWI AT8 DALLAS-1W
uses 6 registers ; and 2 EEPROM locations.
DALLAS CRC ETHNET 8019
needed.
No SRAM is used or
It is approximately ; 123 words of code space. ; ; The external interrupt for reset operation is not
TEA ADC 128
The reset button will clear all
yet active.
ADC 10B ADC 400
; For some reason the hour location in EEPROM gets incremented
ADC 401 THERM 232 IRD 410
; about 4 times as often as it should. timer is
; running faster than CK/1024 or CK is faster than 1MHz (internal RC) ; So I changed the hour counter to 240 minutes
LCD HD44 LCD 2313 LCD44 2313
instead of 60 minutes. ; Can trim the minute and hour count compare values to improve the ; timer accuracy.
KBD 240 MUX 242 KBD PS2
I think the
; Make sure to set the RCEN flag when programming the 2343.
KBD PC/128
.include "2343def.inc"
PS2 EMU BOOT MG8 .def .def .def .def .def .def
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS
times through ISR.
CALL ID
.equ .equ
reset_pin = 1 status_led = 0
; PB1 is the reset (INPUT) ; PB0 is the status LED
.equ
days30_led = 2
; PB2 is the 30 day LED
.equ
days60_led = 3
; PB3 is the 60 day LED
DTMF 314 PWM 6CH
indicator. (OUTPUT)
PWM 10K
indicator. (OUTPUT)
ENCODE STH-11 ATMEL CORP
count_250ms = r16 count_10s = r17 count_1m = r18 temp = r19 led_mask = r20 led_counter = r21 ; used to flash the LEDs every n
indicator. (OUTPUT) .equ
days90_led = 4
; PB4 is the 90 day LED
indicator. (OUTPUT)
AVR BUTTERFLY
; There are no more I/O pins on the 2343. ; the Interrupt Vector table
AVR BOOK
.org 0x00 ; Power up reset rjmp POWER_ON ; External HW Int ;rjmp reset_button reti ; Internal Timer0 Overflow rjmp Timer0
POWER_ON: ; Initialize the Stack Pointer, WDT, Interrupts, I/ O Pins, and Timer0 cli
; Make sure
interrupts are disabled for now. ldi
temp, 14
;15 = 2048 mS, 14 = 1024, 13 =
out
WDTCR, temp ; Watchdog timer is a good idea
ldi out clr out
ZL,low(RAMEND) SPL,ZL ;init Stack Pointer temp GIMSK, temp ; don't allow
512 mS here.
External INT0 ldi out
temp, 2 TIMSK, temp
; allow
ldi out
temp,0b11111111 DDRB, temp
; all
ldi out
temp, 0b101 TCCR0, temp
; timer
ldi out
temp, 0b00100000 MCUCR, temp
; sleep
Timer0 overflow interrupts.
outputs except for PB1
prescaler = CK/1024
mode enabled, Idle mode selected ;ldi ;out
temp,$80 ACSR,temp
; ; Comparator
Disabled to save power
; All LEDs OFF ser led_mask out PORTB, led_mask clr
led_counter
zero_timer: clr out
temp TCNT0, temp
; start
timer at 0 sleep_and_wait: ; check the 10 days location in EEPROM to see if we need to light any LEDs ldi
temp, 1 ; put address 0 in the EEPROM
address register
enable bit until it is cleared.
out EEAR, temp sbi EECR, EERE Get_READ_POLL: ; this will poll the EECR read Then sbic EECR, EERE ; the EEPROM data will be available
at the EEPROM data register. rjmp Get_READ_POLL in temp, EEDR ; copy the contents to our local variable. ; Now the 10 days value is in temp. cpi temp, 3 ; 30 days brlt done_setting_bits ;cbr led_mask, days30_led cbi PORTB, days30_led cpi temp, 6 ; 60 days brlo done_setting_bits ;cbr led_mask, days60_led cbi PORTB, days60_led cpi temp, 9 ; 90 days brlo done_setting_bits ;cbr led_mask, days90_led cbi PORTB, days90_led done_setting_bits: sei make sure interrupts are enabled at this time. sleep CPU in idle mode. The Timer0 still runs. nop nop rjmp sleep_and_wait
; ; put the
;The following is the Timer0 ISR where all the work gets done. ;At 1 MHz the timer will overflow approximately every 250 mS. Timer0: cli We have 250 mS to do all this. inc sbis rjmp rjmp
in case.
; disable further interrupts just led_counter PORTB, status_led led_now_on led_now_off
led_now_off: ; we want to turn it on when count gets to 8 cpi led_counter, 8 ;rjmp turn_on_status_led breq turn_on_status_led rjmp skip_over turn_on_status_led: cbi PORTB, status_led clr led_counter rjmp skip_over led_now_on: ; it is on, so turn it off sbi PORTB, status_led skip_over: ;cpi led_counter, 30 ;brlt dont_clear ;clr led_counter dont_clear: ; com led_mask ; temp test code. ;out PORTB, led_mask ; turn on the LEDs for number of days. ms250_handler: wdr
;
don't forget to reset the WDT inc cpi reached 1 minute?
count_250ms count_250ms, 240
; has the count
Adjust for accuracy. breq one_minute ; flash the LED's in this section. rjmp exit_interrupt one_minute: clr count_250ms inc count_1m cpi count_1m, 240 breq hour_handler rjmp exit_interrupt
; has 1 hour passed?
hour_handler: ; this routine has to write the EEPROM.
Put in the
checks in the 100ms section ; to flash the corresponding LEDs when EEPROM value reaches specific numbers. clr count_1m ; set aside two EEPROM locations. Location 0 counts the hours up to 240 hours (10 days). ; then location 1 is incremented to count tens of days. When location 0 reaches 240 ; hours, then we increment location 1 and clear location 0. ; start by getting the value of location 0. is less than 240 increment it.
If it
Else ; clear and increment location 1. ldi
temp, 0 ; put address 0 in the EEPROM
address register
enable bit until it is cleared.
out EEAR, temp ldi temp, 1 ; enable EEPROM read out EECR, temp EE_READ_POLL: ; this will poll the EECR read Then sbic EECR, 0 ; the EEPROM data will be available at
the EEPROM data register. rjmp EE_READ_POLL in temp, EEDR
; copy the contents to our local
variable. cpi temp, 240 ; see if 10 days have passed breq TEN_DAYS inc temp ; if not 10 days, then increment the hour counter and write back to EEPROM out EEDR, temp sbi EECR, EEMWE ; set the EEPROM master write enable sbi EECR, EEWE ; set the EEPROM write enable bit EE_WRITE_POLL: sbic EECR, EEWE ; this will poll on the write enable bit until it clears (write complete) rjmp EE_WRITE_POLL cbi EECR, EEMWE ; clear the master write enable bit to prevent any further write. rjmp exit_interrupt
hours).
TEN_DAYS: ; ten days has passed if we reach here (240 If we get here, then we need to clear ; EEPROM location 0 and increment EEPROM location 1. ldi temp, 1
; put address 1 in the EEPROM data
register out EEAR, temp sbi EECR, EERE ; set the read enable bit READ_POLL: sbic EECR, EERE ; poll the read bit rjmp READ_POLL in temp, EEDR
; get the EEPROM data into local
variable temp. inc temp
; add 1 to the temp
register. ; need to set flags for LEDs here, now that we have the number of 10 day periods in temp out EEDR, temp ; get ready to write back to EEPROM. sbi EECR, EEMWE ; set master write enable sbi EECR, EEWE WRITE_POLL: sbic EECR, EEWE ; poll the write bit rjmp WRITE_POLL ; now we have to clear the hours location in EEPROM to start over. clr out out sbi
temp EEAR, temp ; set EEPROM address to 0. EEDR, temp ; set data register to 0. EECR, EEMWE ; set the master write
enable. sbi EECR, EEWE
; set the write bit strobe.
POLL_WRITE: sbic EECR, EEWE ; poll the write bit rjmp POLL_WRITE cbi EECR, EEMWE ; clear the master write enable bit
updated.
; now the 10 day location in EEPROM has been Next we reset the counter re-enable ; interrupts, and return from the interrupt. exit_interrupt: ;sbi PORTB, status_led
; turn off the status LED
before we leave. ;sbi PORTB, days30_led ;sbi PORTB, days60_led ;sbi PORTB, days90_led
; turn off the day count
LEDs. clr temp out TCNT0, temp sei reti
reset_button: ; if the reset button is pressed, we will come here. Reset the EEPROM locations ; reset the register counters, and jump back to the beginning.
ldi
temp, 0 ; put address 0 in the EEPROM
address register out EEAR, temp out EEDR, temp sbi EECR, EEMWE ; set the EEPROM master write enable sbi EECR, EEWE ; set the EEPROM write enable bit CLEAR_LOCATION_ZERO: sbic EECR, EEWE ; this will poll on the write enable bit until it clears (write complete) rjmp CLEAR_LOCATION_ZERO out EEDR, temp inc temp out EEAR, temp sbi EECR, EEMWE sbi EECR, EEWE CLEAR_LOCATION_ONE: sbic EECR, EEWE rjmp CLEAR_LOCATION_ONE cbi EECR, EEMWE ; clear the master write enable bit to prevent any furthe rjmp
POWER_ON
; start over.
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed http://avr-asm.tripod.com/90days.html (1 of 2)1/20/2009 9:18:08 PM
16 BIT MATH (AVR 202)
using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/90days.html (2 of 2)1/20/2009 9:18:08 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DELAYS PACKAGE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201
; ****************************************************************************** ;_Delays.asm Version 0.0a ; ****************************************************************************** ; ;Written for : Atmel "AVR Assembler" and "AVR Assembler 2" ; when : 2005 November 20 ; where: BRUSSELS - BELGIUM - EUROPE ; who : Jan Huygh ; E-mail: [email protected]
MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019
; ****************************************************************************** ;A WORD FROM THE AUTHOR : ; ;I would find it motivating to find out that people use this code. ; ;On regular base (every 10 to 12 weeks) I gather the comments on the code I ;posted and use the comments to improve my code. If you have constructive ;comment then let me know. ; * Give me an evaluation. ; * Send me a mail ([email protected]) subject "I use your _Delays.asm". ; * Send me a mail ([email protected]) subject "Comment on your _Delays.asm" ; ****************************************************************************** ;ABOUT VERSION 0.0a ; ;This is the first posted version. ; ; KNOWN BUGS : ; * None so far ; OPPORTUNITIES FOR IMPROVEMENT : ; * a version that can be used as a subroutine taking in to acount the time ; for the call and for the return. ; * a version that takes the input from the stack so it can take a variable ; for the input. ; * a version that is less precise but takes less bytes of program memory ; ; ****************************************************************************** ;.INCLUDE "_Delays.asm" enables you to use the following macro in your code ; ; _Waiste_us n ; With (1.000.000/F_CPU) <= n <= 25769803779/ Your_CPU_frequency_in_MHz ; ; This macro will generate a wait loop from 1 µs to 25.769.803.779 µs ; Depending on the CPU-speed set in F_CPU here below you will need to ; respect a minimum value for n. (n_minimum) = 1.000.000/F_CPU). ; This is needed because we can not loop for less then 1 ; instruction cycle. ; 25.769.803.779 µs, that's over 3h30 when you use a CPU running at 20 MHz. ; _Waiste_us is absolutely exact down to (1/ Your_CPU_frequency_in_MHz) µs ; _Waiste_us will pick the smallest code for your delay (Maximum 13 words)
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
; ****************************************************************************** ;How to use this in your code : ; ; A) Pick the correct ".equ F_CPU = x" statement ; AND ; save this file to your disk ; ; B) Make sure it is in the same folder as the other files of your current project ; OR ; Make sure the folder where you saved this file is referenced in the ; assembler options (Project=>Assembler Options=>Additional include path) ; ; C) Include the statement .INCLUDE "_Delays.asm" at the top of your program ; ; D) Use the statement _Waiste_us n, in your code ; ;Here is a code example : ; ; .INCLUDE "_Waiste.asm" ;Make the macro _Waiste_us n available in your code ; _Waiste_us 100 ;loop for 100 µs (that's 0,1 ms) ; _Waiste_us 16000 ;loop for 16.000 µs (that's 16 ms) ; _Waiste_us 7000000 ;loop for 7.000.000 µs (that's 7 s ) ; ; ****************************************************************************** ;The CPU-speed needs to be set before you can use _Waiste_us. ;Find your CPU-speed in the list here below and uncomment it (remove the ";") ;then press Ctrl^S to save to disk otherwise the include file used by AVR studio ;will be the unchanged version on your disk. ; ; ; .equ F_CPU = 1000000 ;Hz ; .equ F_CPU = 2000000 ;Hz .equ F_CPU = 3579545 ;Hz ; .equ F_CPU = 3686400 ;Hz ; .equ F_CPU = 4000000 ;Hz ; .equ F_CPU = 4032000 ;Hz ; .equ F_CPU = 4096000 ;Hz ; .equ F_CPU = 4194304 ;Hz ; .equ F_CPU = 4433619 ;Hz ; .equ F_CPU = 4915200 ;Hz ; .equ F_CPU = 5000000 ;Hz ; .equ F_CPU = 5068800 ;Hz ; .equ F_CPU = 5990400 ;Hz ; .equ F_CPU = 6000000 ;Hz ; .equ F_CPU = 6144000 ;Hz ; .equ F_CPU = 6500000 ;Hz ; .equ F_CPU = 7372800 ;Hz ; .equ F_CPU = 7680000 ;Hz ; .equ F_CPU = 8000000 ;Hz ; .equ F_CPU = 9000000 ;Hz ; .equ F_CPU = 9216000 ;Hz ; .equ F_CPU = 9830400 ;Hz ; .equ F_CPU = 10000000 ;Hz ; .equ F_CPU = 10240000 ;Hz ; .equ F_CPU = 11000000 ;Hz ; .equ F_CPU = 11059200 ;Hz ; .equ F_CPU = 11520000 ;Hz ; .equ F_CPU = 12000000 ;Hz ; .equ F_CPU = 12000393 ;Hz ; .equ F_CPU = 12288000 ;Hz ; .equ F_CPU = 13500000 ;Hz ; .equ F_CPU = 14318180 ;Hz ; .equ F_CPU = 14745600 ;Hz ; .equ F_CPU = 15000000 ;Hz ; .equ F_CPU = 15360000 ;Hz ; .equ F_CPU = 16000000 ;Hz ; .equ F_CPU = 16000312 ;Hz ; .equ F_CPU = 16257000 ;Hz ; .equ F_CPU = 16384000 ;Hz ; .equ F_CPU = 17734475 ;Hz ; .equ F_CPU = 18000000 ;Hz ; .equ F_CPU = 18432000 ;Hz ; .equ F_CPU = 19660800 ;Hz ; .equ F_CPU = 20000000 ;Hz
.Macro _Waiste_us ;n ; Calculate the number of CPU-cycles needed to generate the requested delay ;
taking in to account the frequency you are using
;
You can simplify the next 9 lines of code before
;
to "Cycles_Needed = @0 * F_CPU / 1000000". If you
;
generate the exact delay you requested or the delay
;
number of cpu-cycles that brings just less then the
;
This might be a good option if you need a certain
;
you never have a delay that is even a fraction of a
; ;
delay you requested. The 9 lines of code here below do NOT use any space
; ;
memory of your AVR. The code here below will actually pick the number
;
generate EXACTLY the delay you requested and when
;
it will select the number of cycles that generate
;
approximation for the delay you requested even if
;
delay you requested. .set Fraction = ; .set Fraction = Fraction * 100 .set Fraction = @0*F_CPU/10000 - Fraction .if Fraction >= 50 .equ Cycles_Needed = (@0 *
for your CPU. "_Cycle_Waister Cycles_Needed" do so _Waist_us will obtained by executing the delay you requested. delay but need to be sure CPU-cycle longer than the
in the actual program
of CPU-cycles needed to that can not be achieved the delay that is the best that is just above the
@0*F_CPU/1000000
F_CPU /1000000)+1 .endif .if .equ
Fraction < 50 Cycles_Needed = (@0 *
F_CPU /1000000) .endif _Cycle_Waister Cycles_Needed .endmacro .macro _Cycle_Waister .If @0 == 1 nop .EndIf .If @0 == 2 nop nop .EndIf .If ((@0 > 2) && (@0 < 769)) ;C=3n ;769=(3 * (2^8)) + 1 .set Loops_Needed = @0/3 ldi R16,Low(Loops_Needed) Loop: dec R16 brne Loop .set Cycles_Left_To_Do = @0 (3*Loops_Needed) _Cycle_Waister Cycles_Left_To_Do .EndIf .If (@0 > 768) && (@0 < 262146) ;C=1+4n ;262146 = 1 + (4 * 2^16) + 1 .set Loops_Needed = (@0 - 1)/4 ldi ZL,Low(Loops_Needed) ldi ZH,High(Loops_Needed) Loop: sbiw ZL,1 brne Loop .set Cycles_Left_To_Do = (@0 (4*Loops_Needed))-1 _Cycle_Waister Cycles_Left_To_Do .EndIf .If (@0 > 262145) && (@0 < 83886083) ;C=2+5n ;83.886.083 = 2 + (5 * 2^24) +1 .set Loops_Needed = (@0 - 2)/5 ldi R16,Low(Loops_Needed) ldi ZL,Byte2(Loops_Needed) ldi ZH,Byte3(Loops_Needed) Loop: subi R16,1 sbci ZL,0 sbci ZH,0 brne Loop .set Cycles_Left_To_Do = (@0 (5*Loops_Needed))-2 _Cycle_Waister Cycles_Left_To_Do .EndIf .If (@0 > 83886082) && (@0 < 25769803780) ;C=3+6n ;25769803780 = 3 + (6 * 2^32) +1 .set Loops_Needed = (@0 - 3)6 ldi XL,Low(Loops_Needed) ldi XH,Byte2(Loops_Needed) ldi ZL,Byte3(Loops_Needed) ldi ZH,Byte4(Loops_Needed) Loop: sbiw Xl sbci ZL,0 sbci ZH,0 brne Loop .set Cycles_Left_To_Do = (@0 (6*Loops_Needed)) - 3 _Cycle_Waister Cycles_Left_To_Do .endif .endmacro
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB http://avr-asm.tripod.com/delays.html (1 of 2)1/20/2009 9:18:41 PM
16 BIT MATH (AVR 202)
Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/delays.html (2 of 2)1/20/2009 9:18:41 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
CALLER ID HOME RETRO_DAN ;callerID.asm ; ;neil barnes / nailed_barnacle 2003
ASM FORUM ASM MATH TUTORIAL #1
;this is intended to run on the AVRMega8 at 16MHz
TUTORIAL #2 TUTORIAL #3
.include "m8def.inc"
MATH 200 MATH 200b ;*************************************************************************** ;* most variables live in the registers full time ;***************************************************************************
MATH 201 MATH 202 MATH 32X
.CSEG
MATH YX ;r1 ;r0 ;r2 ;r3
DIV16 XX DIV 24 24 DIV 3216
and r0 are needed by multiply has low byte, r1 high byte used as temp store for 16*16 mul used as temp store
FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
.def .def .def .def
result0 result1 result2 result3
.def .def .def .def
main0 main1 main2 main3
= = = =
;partial result for 16*16 mult summed here ;also accumulator for fir filter ; ;high byte
r20 r21 r22 r23
;Temp variable used by main program ; " " " " " ; " " " " " ; " " " " "
= = = =
r16 r17 r18 r19
AVG8 222 FFT7 COPY 102
;*************************************************************************** ;* Port Pin Assignements ;***************************************************************************
LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD
;*************************************************************************** ;* Interrupt vectors ;***************************************************************************
VFX SMIL VFX MEM SORT 220 CRC 236
.org 0 rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp
XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26
RESET RESET RESET RESET RESET RESET sample RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET
;reset ;external int 0 ;external int 1 ;timer 2 compare ;timer 2 overflow ;timer 1 capture ;timer 1 compare a ;timer 1 compare b ;timer 1 overflow ;timer 0 overflow ;serial xfer complete ;usart rx complete ;usart data register empty ;usart tx complete ;adc conversion complete ;eeprom ready ;analogue comparator ;two-wire serial ;store program memory ready
I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
.equ length = 21
;size of buffer
DALLAS CRC ; bit defines for the UART status register .equ idle = 1 .equ rxflag = 2 .equ start = 3 .equ run = 4 .equ framerr = 5 .equ stop = 6
ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401
.dseg
THERM 232
input: .byte 2 output: .byte 2 result: .byte 1 rx: .byte 1 status: .byte 1 clock: .byte 1 bit: .byte 1 q: .byte 1
IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
buffer: delay: ;offset: nextwrite:
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
.byte .byte .byte .byte
(length*2) ; room here for 21 samples 10 2 ; this says where we're reading the data offset 2 ; and this is where the next write occurs
.cseg
BOOT DR8 ALM CLK
;*************************************************************************** ;* ;* MAIN PROGRAM ;* ;*************************************************************************** ;* INITAILIZATION ;***************************************************************************
CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
RESET:
PWM 10K ;we need to set the stack pointer to top of ram Main1,$04 SPH, Main1 Main1,$5f SPL, Main1 ;top of ram is $045f
ENCODE ldi out ldi out
STH-11 ATMEL CORP AVR BUTTERFLY
;*************************************************************************** ;* MAIN LOOP ;***************************************************************************
AVR BOOK
; ; ; ; ; ;
set up an interrupt to look at a port so we can use a pre-fudged test data suite in the real world we will read the adc port using a 16MHz clock and with a 9600 per second sample rate it needs an interrupt every 1667 clocks (strictly 1666.6666...) so we will use timer 1 with no prescale
ldi out ldi out ldi out ldi out
main1,0b11111111 DDRD,main1 main1,0b00000000 PortD,main1 main1,0b00000000 DDRB,main1 main1,0b11111111 PortB,main1
;set port D bits to outputs
ldi ldi out out
main0,low(1667) main1,high(1667) ocr1ah,main1 ocr1al,main0
;set timer values for 9600
ldi out
main0,0b00001001 TCCR1B,main0
;don't use timer prescaler, use CTC mode
ldi out
main0,0b00010000 TIMSK,main0
;M8 uses bit 5 to ;enable comparator a interrupt
;preset
output state
;set port B to inputs ;turn on pullups on inputs
;clear the delay and main buffer ldi main0,10 ldi ZH,high(delay) ldi ZL,low(delay) clr main1 init_01: st Z+,main1 dec main0 brne init_01 ldi ldi ldi init_02: st dec brne
main0,42 ZH,high(buffer) ZL,low(buffer) Z+,main1 main0 init_02
sei
;and allow interrupts
;setup stuff for the software uart ;it occurs to me that one could pass the data out ;on a pin and back to the usart as an input ;but where's the fun in that? clr sts sts sts
main0 nextwrite,main0 nextwrite+1,main0 result,main0
clr r15 sts sts ldi sts FOREVER:
bit,main0 clock,main0 main0,exp2(idle) status,main0
lds andi breq lds out forever_1: lds andi brne
r24,status r24,exp2(rxflag) forever r24,rx portd,r24
jmp
;watch for the rxflag to be set ;output the data
r24,status r24,exp2(rxflag) forever_1
;wait for rxflag to reset
FOREVER
sample:
;loop forever
;we get here when there's a timer1 tick ;every 104uS or thereabouts ;read the B port and feed it to the filter ;routine ;the main program will look after what's happening ;to the data itself
in rcall inc reti
main1,pinb filter r15
filter: ; this is translated from C code ; it can probably be improved :) ; ; called every time a new sample is taken ; i.e. every 9600th second ; ; other frequencies could be used; but the sample ; rate must be chosen to give an even whole number of ; samples per bit period e.g. 7200, 9600, 12000 ; ; 7200 samples/sec = 6 samples/bit and is the lowest that ; will reliably work ; ; 'thingy' is the sample received from the ADC, though we could ; get the sample directly in finished code ; ; the system decodes the codec tones by delaying ; each sample by half a bit length, multiplying the ; delayed sample by the inverse of the current sample, ; and low-pass filtering the result
;
input = ((((short)thingy)-0x80)<<8); ; ; ; ;
this assumes 8-bit unipolar data is being received i.e. maximum negative is 0, maximum positive is 0xff, and zero is 0x80 the data is expected to arrive in the main1 register
ldi sub clr sts sts ; ; ; ;
main0,0x80 main1,main0 r2 input,r2 input+1,main1
; and save the result
// we delay the input samples_per_bit/2 samples (4 samples) for (q=0; q<5; q++) delay[q] = delay[q+1]; ldi
main0,4
ldi ldi ldi ldi
r30,low(delay) r31,high(delay) r28,low(delay+2) r29,high(delay+2)
fi_0001: ld st ld st dec brne ; ; ;
// upscale the sample
;point Z at delay[0]
r0,Y+ Z+,r0 r0,Y+ Z+,r0 main0 fi_0001
;point Y at delay[1]
;copy one word ;and repeat four times
// save new sample delay[spb/2] = input; ;Z should be pointing at delay[4] lds r0,input lds r1,input+1 st Z+,r0 st Z+,r1
; ; ;
// now we multiply todays sample with the delayed one ac = (int)delay[0]*(int)input*-1; movw lds lds movw rcall ldi ldi eor eor eor eor inc inc add adc adc adc
; ; ;
main1:main0,r1:r0 r0,delay r1,delay+1 main3:main2,r1:r0 mul16 main0,0xff main1,0 result0,main0 result1,main0 result2,main0 result3,main0 main0 main0 result0,main0 result1,main1 result2,main1 result3,main1
;result in result0-3
;now multiply by -1 ;the fast way
;should be a touch quicker than ;calling mul16 again
// and finally, low pass filter the result b[0] = ac>>15; ; ; ; ;
if it we so
we look at the result of a 16*16 signed multiply turns out there are two sign bits only want one of them we'll shift up one rather than down 15
rol rol rol
result1 result2 result3
;our result is in result2,3
; work out where to put it ; see below - we're emulating a circular buffer ; we are trying to synchronise two buffers here ; the buffer itself is in ram ; the coefficients are in program rom ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
what we are implementing is this: a standard FIR filter sums the products of the filter coefficients and the data, and then shifts the data along one place the next item of data gets added in at the beginning of the data buffer we don't want to do the shift if we can avoid it as it costs 11uS and we don't have time to spare a real DSP chip would have a circular buffer, we emulate it we have two copies of the filter coefficients butted to each other P
Q
R
S
T
P' Q' R' S' T'
and one copy of the data buffer A
B
C
D
E
we start with a pointer to P', and do the summation AP'+BQ'+CR'+DS'+ET' next time we add new data to replace A F
B
C
D
E
decrement the pointer to T, and do the summation FT+BP'+CQ'+DR'+ES' and so on. When the coefficient filter passes P we aim it at P' and in this way need not move any data
; buffer[nextwrite] = ac>>15; lds main0,nextwrite clr main1
;will always be 0
push push
main1 main0
;save nextwrite
ldi ldi add adc
YL,low(buffer) YH,high(buffer) YL,main0 YH,main1
;Y points to buffer[nextwrite]
st st
Y+,result2 Y+,result3
; offset = 21-nextwrite; ldi ZL,42 clr ZH sub ZL,main0 sbc ZH,main1
;21 words
;Z now has offset
; ac = 0; clr result0 clr result1 clr result2 clr result3 ; for (q=0; q<21; q++) ldi main3,20 mov r3,main3 ; ldi ldi ldi ldi add adc
ac+= (int)buffer[q]*(int)hi1k2[q+offset]; YL,low(buffer) YH,high(buffer) main2,low(hi1k2*2) main3,high(hi1k2*2) ZL,main2 ZH,main3
clr
r2
fi_0002: ld ld lpm lpm
;this needs to be zero ;for the multiply
main0,Y+ main1,Y+ main2,Z+ main3,Z+
;buffer[q]
;hi1k2[q+offset] ;and both pointers incremented ; 16*16->32 bit multiply and accumulate ; result0-3 += main0,1 * main2,3 ; inlined for speed muls add adc mul add adc adc adc mulsu sbc add adc adc mulsu sbc add adc adc
main3,main1 result2,r0 result3,r1 main2,main0 result0,r0 result1,r1 result2,r2 result3,r2 main3,main0 result3,r2 result1,r0 result2,r1 result3,r2 main1,main2 result3,r2 result1,r0 result2,r1 result3,r2
dec brge
r3 fi_0002
;and do this 21 times
; nextwrite++; pop main0 pop main1 inc main0 inc main0
;get it back ;increment to next word - won't roll over
; if (nextwrite > 20) cpi main0,42 brne PC+2 ; clr sts ;sts
nextwrite = 0; main0 nextwrite,main0 nextwrite+1,main1
; if (ac>0) ; result = 1; ;else ; result = 0; ; at this point, r2 is still cleared ; ; we need to do a 16-bit compare to set the final result
subi sbc brlt
result2,1 result3,r2 PC+2
inc
r2
;then make r2 positive
; from here r2 holds the output of the filter stage fi_0002a: ; ; ; ; ; ; ; ;
// // // // // // // //
now we can build a uart the data is delivered in ten bit chunks... in order, start bit (0) bit 0 ... bit 7 stop bit (1)
; some register assignments .def r_clock = r20 .def r_rx = r21 .def r_bit = r22 .def r_status = r23 ; ; ; // see what our state is lds lds lds lds ;
; ;
r_clock,clock r_rx,rx r_bit,bit r_status,status
;get clock and status and such
if (status & IDLE) sbrs r_status,idle jmp fi_0003 { status &= ~RXFLAG; cbr r_status,EXP2(rxflag)
// we're idling ;skip if clear
;clear rxflag bit
;
if (!result) // falling edge of start bit tst r2 ;result is still in r2 breq fi_0004 ; { ; status &= ~IDLE; // so we idle no longer cbr r_status,EXP2(idle) ; status |= START; // we're started sbr r_status,EXP2(start) ; bit = 0; // reset bit counter clr r_bit ; clock = 0; // and the clock count clr r_clock ; } fi_0004: ; // else we're still waiting for end of stop bit ; } jmp fi_0005 ; else fi_0003: ; { ; if (status & START) // aha, we got the falling edge sbrs r_status,start jmp fi_0005 ; { ; if ((clock <= spb/2) && (result)) // oops, false trigger...noise perhaps cpi r_clock,5 brge fi_0014 tst r2 brne fi_0014 ; { ; status &= ~START; cbr r_status,EXP2(start) ; status |= IDLE; // so drop back to idle mode sbr r_status,EXP2(idle) jmp fi_0007 ; } ; else fi_0014: ; { ; clock++; // otherwise, one more clock inc r_clock ; } fi_0007: ; if (clock == spb/2) // or are we now in mid start-bit cpi r_clock,4 brne fi_0006: ; { ; status &= ~START; cbr r_status,EXP2(start) ; status &= ~IDLE; cbr r_status,EXP2(idle) ; status |= RUN; // so now we're hot to trot sbr r_status,EXP2(run) ; clock = 0; // reset counter clr r_clock; ; } ; } fi_0006: jmp fi_0008 ; else fi_0005: ; { ; if (status & RUN) // we're reading data (allegedly) ; { sbrs r_status,run jmp fi_0009 ; if (clock < spb-1) // time for a sample? cpi r_clock,7 breq fi_0010 ; clock++; // not yet inc r_clock jmp fi_0011 ; else fi_0010: ; { ; if (bit != 8) // normal read cpi r_bit,8 breq fi_0012 ; { ; clock = 0; clr r_clock ; ; ; ; ;
rx = rx>>1; if (result) rx |= 0x80; else rx &= 0x7f; clc sbrc sec ror
;
r2,0
;skip if output was '1' ;else set carry ;and slide it into the rx byte
r_rx
bit ++; inc r_bit jmp fi_0013
; ; fi_0012: ; ; ; ; ; ; ; ; ;
} else { if (! result) // frame error { status |= FRAMERR; } else { status &= ~FRAMERR; } sbr r_status,EXP2(framerr) tst r2 brne PC+1 cbr r_status,EXP2(framerr)
;
bit = 0 clr r_bit status |= IDLE; sbr r_status,exp2(idle)
;
;
status |= RXFLAG; sbr r_status,exp2(rxflag)
;
status &= ~RUN; cbr r_status,exp2(run)
;
status &= ~START; cbr r_status,exp2(start)
; } ; } fi_0013: ; } fi_0011: ; } fi_0009: ; } fi_0008: ; ; output = (status<<8)+rx; ; return(output); sts sts sts sts ret
status,r_status clock,r_clock bit,r_bit rx,r_rx
;} break mul16: ; 16*16->32 bit multiply, signed ; code from Atmel appnote AVR201 ; multiplicands are in main1/2 and main3/4 clr muls movw mul movw mulsu sbc add adc adc mulsu sbc add adc adc
r2 main3,main1 result3:result2, r1:r0 main2,main0 result1:result0, r1:r0 main3,main0 result3,r2 result1,r0 result2,r1 result3,r2 main1,main2 result3,r2 result1,r0 result2,r1 result3,r2
; which should leave a nice 32-bit product in result ret mac16: ; 16*16->32 bit multiply and accumulate ; result0-3 += main0,1 * main2,3 clr r2 muls main3,main1 add result2,r0 adc result3,r1 mul main2,main0 add result0,r0 adc result1,r1 adc result2,r2 adc result3,r2 mulsu main3,main0 sbc result3,r2 add result1,r0 adc result2,r1 adc result3,r2 mulsu main1,main2 sbc result3,r2 add result1,r0 adc result2,r1 adc result3,r2 ret ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; the static data for the filter coefficients ; ; these are 16-bit binary fractions of the coefficients for a low pass filter ; there are two copies of the filter so we can emulate a circular buffer ; without having to test for end conditions hi1k2: .dw
0,84,0,-284,-691,-796,0,1992,4756,7209,8191,7209,4756,1992,0,-796,-691,-
.dw
0,84,0,-284,-691,-796,0,1992,4756,7209,8191,7209,4756,1992,0,-796,-691,-
284,0,84,0 284,0,84,0
;// a dll to decode an 8 bit audio data stream into its fsk ;// data symbols assuming 1200Hz = 0, 2200Hz = 1, 1200 bps ;// and a sample rate of either 7200 or 9600 ; ;// definitions of calls ;int filter (unsigned char thingy, int spb); ;#include "nbfsk.h" ;// uart variables ;#define IDLE 1 ;#define START 2 ;#define RUN 4 ;#define RXFLAG 8 ;#define FRAMERR 16 ;#define STOP 32 ; ;static int lo1k2[21] = { ; 0, // -0.00000010 ; 0, // -0.00000010 ; 189, // 0.00578410 ; 347, // 0.01061810 ; 0, // 0.00000010 ; -975, // -0.02977210 ; -1540, // -0.04701110 ; 0, // -0.00000010 ; 4119, // 0.12572310 ; 8829, // 0.26945810 ; 10922, // 0.33333310 ; 8829, // 0.26945810 ; 4119, // 0.12572310 ; 0, // -0.00000010 ; -1540, // -0.04701110 ; -975, // -0.02977210 ; 0, // 0.00000010 ; 347, // 0.01061810 ; 189, // 0.00578410 ; 0, // -0.00000010 ; 0}; // -0.00000010 ; ;static int hi1k2[21] = { ; 0, // 0.00000010 ; 84, // 0.00256410 ; 0, // 0.00000010 ; -284, // -0.00866910 ; -691, // -0.02110710 ; -796, // -0.02430910 ; 0, // -0.00000010 ; 1992, // 0.06080010 ; 4756, // 0.14517310 ; 7209, // 0.22001210 ; 8191, // 0.25000010 ; 7209, // 0.22001210 ; 4756, // 0.14517310 ; 1992, // 0.06080010 ; 0, // -0.00000010 ; -796, // -0.02430910 ; -691, // -0.02110710 ; -284, // -0.00866910 ; 0, // 0.00000010 ; 84, // 0.00256410 ; 0}; // 0.00000010 ; ;int filter (unsigned char thingy, int spb) ;{ ;int ac; ;short input; ;short output; ;char result; ; ;static short delay[5]; ;static short b[22]; ; ;static char rx = 0; ;static short status = 1; ;static int clock = 0; // counter for sample ;static int bit = 0; // bit counter ;int q; ; ; input = ((((short)thingy)-0x80)<<8); // upscale the sample ; ; // we delay the input samples_per_bit/2 samples... ; for (q=0; q<(spb/2+1); q++) ; delay[q] = delay[q+1]; ; ; // save new sample ; delay[spb/2] = input; ; ; // now we multiply todays sample with the delayed one ; ac = (int)delay[0]*(int)input*-1; ; ; // and finally, low pass filter the result ; // select filter depending on sample rate ; b[0] = ac>>15; ; ac = 0; ; if (spb < 7) ; { ; for (q=21; q>=0; q--) ; { ; ac += (int)b[q]*(int)lo1k2[q]; ; b[q+1] = b[q]; ; } ; } ; else ; { ; for (q=21; q>=0; q--) ; { ; ac += (int)b[q]*(int)hi1k2[q]; ; b[q+1] = b[q]; ; } ; } ; if (ac>0) ; result = 1; ; else ; result = 0; ; ; // now we can build a uart ; // the data is delivered in ten bit chunks... ; // in order, ; // start bit (0) ; // bit 0 ; // ... ; // bit 7 ; // stop bit (1) ; ; ; // see what our state is ; if (status & IDLE) // we're idling ; { ; status &= ~RXFLAG; ; if (!result) // falling edge of start bit ; { ; status &= ~IDLE; // so we idle no longer ; status |= START; // we're started ; bit = 0; // reset bit counter ; ; ; ; ; ; ; ; ;
clock = 0;
// and the clock count
} // else we're still waiting for end of stop bit } else { if (status & START) // aha, we got the falling edge { if ((clock <= spb/2) && (result)) // oops, false
trigger...noise perhaps ; ; ; ; ; ;
{
;
if (clock == spb/2)
; ; ; ; ; ; ; ; ; ;
{
status &= ~START; status |= IDLE;
// so drop back to idle mode
} else clock++;
//
otherwise, one more clock // or are we now in mid
start-bit status &= ~START; status &= ~IDLE; status |= RUN; clock = 0;
// so now we're hot to trot // reset counter
} } else { if (status & RUN)
// we're reading data
(allegedly) ; ; ;
{ if (clock < spb-1) clock++;
// time for a sample? // not
yet ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
http://avr-asm.tripod.com/callid.html (1 of 2)1/20/2009 9:19:20 PM
else { if (bit != 8) // normal read { clock = 0; rx = rx>>1; if (result) rx |= 0x80; else rx &= 0x7f; bit ++; } else { if (! result) // frame error { status |= FRAMERR; } else { status &= ~FRAMERR; } status |= IDLE; status |= RXFLAG; status &= ~RUN; status &= ~START; } } } } } output = (status<<8)+rx;
16 BIT MATH (AVR 202)
; return(output); ;} ; ;int _stdcall NbFskDecodeBytes (unsigned char * audio, ; long length, ; unsigned char * decode, ; int samples_per_bit) ;{ ; // this routine takes a block of 8 bit audio data and decodes it ; // using the bel202 fsk standard ; // only bytes which decode without a frame error are saved in 'decode' ; // the calling routine is responsible for ensuring that the decode ; // buffer is sufficiently large - there are about 60-80 samples per ; // byte of output ; // if 'clear' is set then the filter buffer is cleared before use ; ; ;int q; ;int bytes = 0; ;struct rec1 { ; char rx; ; char status; ;} rec; ;union { ; short rex; ; rec1 rec; ;} r; ; ; for (q=0; q
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 016MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K In-System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/callid.html (2 of 2)1/20/2009 9:19:20 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
DTMF GENERATOR (AVR 314) HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24
; *************************************************************************** ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR314 ;* File Name : "dtmf.asm" ;* Title : DTMF Generator ;* Date : 00.06.27 ;* Version : 1.1 ;* Target MCU : Any AVR with SRAM, 8 I/O pins and PWM ;* ;* DESCRIPTION ;* This Application note describes how to generate DTMF tones using a single ;* 8 bit PWM output. ;* ; ***************************************************************************
DIV 3216
.include "4414def.inc"
FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII
; ************************************************************************** ; REGISTERS ; ************************************************************************** .def XL_Tmp = r1 ; low part temporary register .def XH_Tmp = r2 ; high part temporary register
HX2ASC AVG8 222 FFT7
; Number of Element (Position) in LUT in Extended format .def XL_LUTbExt = r3 ; number of LUT-Element of frequency a (low byte)
COPY 102 LPM 108 EPROM 100
.def XH_LUTbExt = r4 ; number of LUT-Element of frequency a (high byte) .def XL_LUTaExt = r5 ; number of LUT-Element of frequency b (low byte) .def XH_LUTaExt = r6 ; number of LUT-Element of
SER EPROM DFLASH AT45
frequency b (high byte)
FLASH CARD
.def OCR_RelValb = r7 ; low frequency reload value to
VFX SMIL
be written to OCR
VFX MEM
be written to OCR
.def OCR_RelVala = r8 ; High frequency reload value to
SORT 220 .def x_SWa = r9 ; step width in LUT to get high CRC 236
frequency .def x_SWb = r10 ; step width in LUT to get low
XMODEM REC UART 304
frequency
UART 305
.def count = r18 ; temporary counter register .def tmp = r16 ; temp register
UART 128 UART BUFF USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128
.def input = r17 ; input from portB ; ************************************************************************** ; ************************************************************************** .equ Xtal = 8000000 ; system clock frequency .equ prescaler = 1 ; timer1 prescaler .equ N_samples = 128 ; Number of samples in lookup table .equ Fck = Xtal/prescaler ; timer1 working frequency .equ delaycyc = 10 ; port B setup delay cycles ; ************************************************************************** ; PROGRAM START - EXECUTION STARTS HERE ; ************************************************************************** .cseg .org $0 rjmp start ; Reset handler .org OVF1addr rjmp tim1_ovf ; Timer1 overflow Handle
ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
; ************************************************************************** ; Interrupt timer1 ; ************************************************************************** tim1_ovf: push tmp ; Store temporary register in tmp,SREG push tmp ; Store status register push ZL push ZH ; Store Z-Pointer push r0 ; Store R0 Register
MUX 242 ;high frequency mov XL_Tmp,XL_LUTaExt mov XH_Tmp,XH_LUTaExt add XL_LUTaExt,x_SWa clr tmp ; (tmp is cleared, but not the carry flag) adc XH_LUTaExt,tmp ; Refresh pointer for the next
KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8
sample rcall getsample ; read from Sin Wave Sample Table mov OCR_RelVala,r0 ; OCR_RelVala = high frequency value
ALM CLK CLOCK 8564
;low frequency mov XL_Tmp,XL_LUTbExt mov XH_Tmp,XH_LUTbExt add XL_LUTbExt,x_SWb clr tmp ; (tmp is cleared, but not the carry flag) adc XH_LUTbExt,tmp ; refresh pointer for the next
90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH
sample rcall getsample ; read from Sin Wave Sample Table mov OCR_RelValb,r0 ; OCR_RelValb = low frequency value
PWM 10K ENCODE
; scale amplitude ldi tmp,2 add OCR_RelValb,tmp lsr OCR_RelValb lsr OCR_RelValb ; divide 4 and round off sub r0,OCR_RelValb ; 4/4 - 1/4 = 3/4 mov OCR_RelValb,r0 ; now OCR_RelValb has the right
STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK amplitude
clr out mov add out
tmp OCR1AH,tmp tmp,OCR_RelVala tmp,OCR_RelValb OCR1AL,tmp ; send the sum of the two amplitudes to
PWM pop r0 ; Restore R0 Register pop ZH pop ZL ; Restore Z-Pointer pop tmp out SREG,tmp ; Restore SREG pop tmp ; Restore temporary register; reti ;********************************* ; RESET Interrupt ;********************************* start: sbi DDRD,PD5 ; Set pin PD5 as output ldi tmp,low(RAMEND) out SPL,tmp ldi tmp,high(RAMEND) out SPH,tmp ; Initialize Stackpointer ;Initialization of the registers clr XL_LUTaExt clr XH_LUTaExt clr XL_LUTbExt clr XH_LUTbExt ; Set both table ponters to 0x0000 ;enable timer1 interrupt ldi tmp,(1< out TIMSK,tmp ; Enable Timer1_ovf interrupt ;set timer1 PWM mode ldi tmp,(1< out TCCR1A,tmp ; 8 bit PWM not reverse (Fck/510) ldi tmp,(1< out TCCR1B,tmp ; prescaler = 1 sei ; Enable interrupts ; ************************************************************************** ; MAIN ; Read from portB (eg: using evaluation board switch) which ; tone to generate, extract mixing high frequency ; (column) and low frequency (row), and then ; fix x_SWa and x_SWb ; row -> PINB high nibble ; column -> PINB low nibble ; ************************************************************************** main: ;high frequency (Esteem only high nibble that is row) ;PB_High_Nibble: ldi tmp,0x0F out DDRB,tmp ; High nibble Input / Low nibble. Outp. ldi tmp,0xF0 out PORTB,tmp ; High nibble PullUp / Low nibble Zero Outp. rcall delay clr count in input,PINB main10: inc count lsl input brcc main20 ldi tmp,4 cp count,tmp brne main10 clr x_SWb clr count rjmp main30 main20: dec count ldi ZL,low(frequencyL*2) ldi ZH,high(frequencyL*2) add ZL,count clr tmp adc ZH,tmp lpm mov x_SWb,r0 ; this is low frequency x_SW clr count ;low frequency ;PB_Low_Nibble: main30: ldi tmp,0xF0 out DDRB,tmp ; High nibble. Outp. / Low nibble Input ldi tmp,0x0F out PORTB,tmp ; High nibble Zero Outp. / Low nibble PullUp rcall delay in input,PINB swap input main40: inc count lsl input brcc main50 ldi tmp,4 cp count,tmp brne main40 clr x_SWa rjmp main main50: ; there is a zero bit in count-1 position dec count ldi ZL,low(frequencyH*2) ldi ZH,high(frequencyH*2) add ZL,count clr tmp adc ZH,tmp lpm mov x_SWa,r0 ; this is high frequency x_SW rjmp main
;****************** DELAY *********************************** ; **************************************************************** delay: ldi tmp,delaycyc loop: dec tmp brne loop ret
;****************** GET SAMPLE ****************************** ; **************************************************************** getsample: ldi tmp,0x0f and XH_Tmp,tmp ; ROUND - add four ldi tmp,4 add XL_Tmp,tmp clr tmp adc XH_Tmp,tmp ; shift (divide by eight): lsr XH_Tmp ror XL_Tmp lsr XH_Tmp ror XL_Tmp lsr XH_Tmp ror XL_Tmp ldi tmp,0x7f and XL_Tmp,tmp ; module 128 (samples number sine table) ldi ZL,low(sine_tbl*2) ldi ZH,high(sine_tbl*2) add ZL,XL_Tmp clr tmp adc ZH,tmp ; Z is a pointer to the correct ; sine_tbl value lpm ret ;*************************** SIN TABLE ************************************* ; Samples table : one period sampled on 128 samples and ; quantized on 7 bit ; ****************************************************************************** sine_tbl: .db 64,67 .db 70,73 .db 76,79 .db 82,85 .db 88,91 .db 94,96 .db 99,102 .db 104,106 .db 109,111 .db 113,115 .db 117,118 .db 120,121 .db 123,124 .db 125,126 .db 126,127 .db 127,127 .db 127,127 .db 127,127 .db 126,126 .db 125,124 .db 123,121 .db 120,118 .db 117,115 .db 113,111 .db 109,106 .db 104,102 .db 99,96 .db 94,91 .db 88,85 .db 82,79 .db 76,73 .db 70,67 .db 64,60 .db 57,54 .db 51,48 .db 45,42 .db 39,36 .db 33,31 .db 28,25 .db 23,21 .db 18,16 .db 14,12 .db 10,9 .db 7,6 .db 4,3 .db 2,1 .db 1,0 .db 0,0 .db 0,0 .db 0,0 .db 1,1 .db 2,3 .db 4,6 .db 7,9 .db 10,12 .db 14,16 .db 18,21 .db 23,25 .db 28,31 .db 33,36 .db 39,42 .db 45,48 .db 51,54 .db 57,60 ;******************************* x_SW *********************************** ;Table of x_SW (excess : x_SW = ROUND(8*N_samples*f*510/ Fck) ; ************************************************************************** ;high frequency (coloun) ;1209hz ---> x_SW = 79 ;1336hz ---> x_SW = 87 ;1477hz ---> x_SW = 96 ;1633hz ---> x_SW = 107 frequencyH: .db 107,96 .db 87,79 ;low frequency (row) ;697hz ---> x_SW = 46 ;770hz ---> x_SW = 50 ;852hz ---> x_SW = 56 ;941hz ---> x_SW = 61 frequencyL: .db 61,56 .db 50,46
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will http://avr-asm.tripod.com/dtmf314.html (1 of 2)1/20/2009 9:20:00 PM
16 BIT MATH (AVR 202)
occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/dtmf314.html (2 of 2)1/20/2009 9:20:00 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
SIX CHANNEL PWM FOR 128 HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD
; *************************************************************************** ; ; File Name :'pwm6.asm" ; Title :6 chanel Phase and Frequency Correct PWM ; Date :2003.11.15. ; Version :1.0.0 ; Support telephone :+36-70-333-4034, Old: +36-30-9541658 ; Support fax : ; Support Email :[email protected] ; Target MCU :ATmega128 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- ---------------------------------------------; 0.01 2003.11.15 VFX Creation ; ; ; *************************************************************************** ;Hardware ; *************************************************************************** ;* ;* Oscillator: f=external, 16.0000 MHz (T=62.5ns) == SYSCLK ;* ; *************************************************************************** ;* Const Def
VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC
; ************************************************************************** ;* Hardware Def. ;
UART 304 UART 305 UART 128 UART BUFF
; *************************************************************************** ;**** VARIABLES .DSEG
USB 232 AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128
; *************************************************************************** .ESEG ; *************************************************************************** ;**** I N T E R R U P T S ;**** ; *************************************************************************** .CSEG
I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232
; ************************************************************************ ; ************************************************************************ ;** PWM6_Init ;** ;** Timer1 & Timer3 setup ; PWM6_Init: ; ldi R16,0b00010000 ICES3 – WGM33 WGM32 CS32 CS31 CS30 ; out TCCR1B,R16 ; sts TCCR3B,R16
;ICNC3 ;Timers Stop
IRD 410 clr sts sts out out sts
R16 TCNT3H,R16 TCNT3L,R16 TCNT1H,R16 TCNT1L,R16 TCCR3C,R16
KBD PS2
sts
TCCR1C,R16
KBD PC/128
out out out out sts sts
OCR1AH,R16 OCR1AL,R16 OCR1BH,R16 OCR1BL,R16 OCR1CH,R16 OCR1CL,R16
sts sts sts sts sts sts
OCR3AH,R16 OCR3AL,R16 OCR3BH,R16 OCR3BL,R16 OCR3CH,R16 OCR3CL,R16
in andi out
R16,PORTB R16,0b00011111 PORTB,R16
in ori out
R16,DDRB R16,0b11100000 DDRB,R16
in andi out
R16,PORTE R16,0b11000111 PORTE,R16
in ori out
R16,DDRE R16,0b00111000 DDRE,R16
;PWM3..5 as
ldi
R16,0x03
;PWM width
sts ldi sts
ICR3H,R16 R16,0xFF ICR3L,R16
ldi out ldi out
R16,0x03 ICR1H,R16 R16,0xFF ICR1L,R16
in andi out
R16,TIMSK R16,0b11000011 TIMSK,R16
;Interrupt
ldi
R16,0b00000000
;TICIE3
sts
ETIMSK,R16
ldi out
R16,0b10101000 TCCR1A,R16
;COM1A1
sts
TCCR3A,R16
;COM3A1
ldi out sts
R16,0b00010001 TCCR1B,R16 TCCR3B,R16
;Start PWM
LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242
;Counter=0
;FOC3A
FOC3B FOC3C
PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID
;PWM = 0%
DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY
;PWM0..2 as
output
AVR BOOK
output
= 10 bit
disabled
OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C
COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30
ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/pmw6ch.html (1 of 2)1/20/2009 9:20:33 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/pmw6ch.html (2 of 2)1/20/2009 9:20:33 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
10K POT AND PWM ROUTINE FOR 8535 HOME RETRO_DAN ASM FORUM
A 10K Ohm potentiometer. The ADC directly controls the PWM function.
ASM MATH TUTORIAL #1
;----------------------------------; PWM FOR 8535 ;----------------------------------.include "m8535def.inc"
TUTORIAL #2 TUTORIAL #3 MATH 200
; Set the assembler program counter to point to program
MATH 200b MATH 201
code space .org 0x0000
;CSEG
MATH 202 MATH 32X
; Set the assembler program counter to point to PWM intrrupt handler
MATH YX
.org ADCCaddr
DIV16 XX
; Set the ADC intrrupt vector rjmp load_PWM ; ADCaddr also Defined as 0x00E
DIV 24 24 DIV 3216
; Set the reset vector rjmp INIT_MCU
FLOAT 128 SQRT16
; Microcontroller initialization sequence INIT_MCU: ldi r16, low(RAMEND) out SPL, r16 ldi r16, high(RAMEND) out SPH, r16
MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
; Initialize the ADC A_D: ; Set up Analog to Digital ldi r16, 0b01000001 ; AVCC REF, ADC channel 1 out ADMUX, r16 ldi r16, 0b10101111 ; ENA ADC, Auto Trigger, ADC
AVG8 222 FFT7 COPY 102 LPM 108
INT ENA, Clock div by 128 out ADCSRA, r16 sbi ADCSRA, ADSC
EPROM 100
; Start ADC conversions
SER EPROM Set_IO_PORTS: ; Set up PORTB for PWM output control ldi r16, 0b00100000 ; Sets PORTB for all inputs,
DFLASH AT45 FLASH CARD
OC1A (PORTB, Pin 5) out DDRB, r16 ldi r16, 0b00000000
VFX SMIL VFX MEM
resistors out PORTB, r16
SORT 220 CRC 236
; Initialize timer/counter 1 for 10 bit FAST PWM ; 10 bit "Fast PWM" (Mode 7), TOP = 0x3FF, Update OCR1A
XMODEM REC UART 304 UART 305
when TCNT = TOP ldi r16, 0b10000011 ; Clear AC1A on comp. match, WGM11 = 1, WGM10 = 1 out TCCR1A, r16 ldi r16, 0b00001001
UART 128 UART BUFF
; Disable internal pull up
; WGM13 = 0, WGM12 = 1, No CLK
prescaling
USB 232
out TCCR1B, r16
AVR ISP
sei
; Enable global intrrupts
ISP 2313 ; Main program loop. -----> Just a very tight loop main: ; Get the current ADC conversion data rjmp main
ISP 1200 AVR SPI I2C 300 I2C 302
; PWM control intrrupt handler load_PWM: ; Get the current ADC conversion data in r17, ADCL ; Must be read first!!! in r18, ADCH ; Output the current ADC conversion in TCNT1 for
I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W
PWM out OCR1AH, r18 out OCR1AL, r17 reti
DALLAS CRC ETHNET 8019
; Must be written first
TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240
Programming the AVR Microcontrollers in Machine Language
MUX 242 KBD PS2
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KBD PC/128 PS2 EMU © WebRing Inc.
BOOT MG8
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BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/pwm10k.html (1 of 2)1/20/2009 9:21:05 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/pwm10k.html (2 of 2)1/20/2009 9:21:05 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
AVR ASM ENCODER HOME RETRO_DAN I've been using this routine for ages, slight modification depending on the number of encoders and values I assign changed like a keyscan routine which is passed on to another routine to deal with.
ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2
It has every condition of the encoder accounted for, including invalid switch patterns which I happen from time to time.
TUTORIAL #3 MATH 200
It also can be polled from a main subroutine at a frequency of around 1ms but accuracy of timing is not important and never stays in there looping under any condition so fits well into a multitasking environment, so far I've never had any problems with it.
MATH 200b MATH 201 MATH 202 MATH 32X MATH YX
Ax, Bx and so on I use for R16, R17 change them to whatever you like, the variables used are below
DIV16 XX DIV 24 24
;;variables local Ax,Bx,Cx,Dx ; ;; global encoder1,scansqn,debounceon ; ;; encoder2,encoder3
DIV 3216 FLOAT 128
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; clr Bx ;;encoder1 left/right clr cx sbic PINC,PC_En1a ldi Bx,0x01 sbic PINC,PC_En1b ldi Cx,0x01 lds Ax,Encoder1 rcall EncoderSub brcs StoreEn1 ;;encoder 1 activated sts Encoder1,Ax
SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC AVG8 222 FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL
clr clr sbic ldi sbic ldi lds rcall brcs sts
Bx cx PINC,PC_En2a Bx,0x01 PINC,PC_En2b Cx,0x01 Ax,Encoder2 EncoderSub StoreEn2 Encoder2,Ax
;;encoder2 left/right
clr clr sbic ldi sbic ldi lds rcall brcs sts
Bx cx PINC,PC_En3a Bx,0x01 PINC,PC_En3b Cx,0x01 Ax,Encoder3 EncoderSub StoreEn3 Encoder3,Ax
;;encoder3 left/right
clr clr sbic ldi sbic ldi lds rcall brcs sts
Bx cx PINC,PC_En4a Bx,0x01 PINC,PC_En4b Cx,0x01 Ax,Encoder4 EncoderSub StoreEn4 Encoder4,Ax
;;encoder3 left/right
rjmp
PushButtons
;;encoder 2 activated
VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232
;;encoder 3 activated
AVR ISP ISP 2313 ISP 1200 AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8
;;encoder 3 activated
DALLAS-1W DALLAS CRC ETHNET 8019 TEA ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8
StoreEn1: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x29 Bx,0 Ax,0x28 Bx Encoder1,Bx KeyRegister
StoreEn2: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x2B ;;left value Bx,0 Ax,0x2A ;;right value Bx Encoder2,Bx KeyRegister
StoreEn3: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x2D ;;left value Bx,0 Ax,0x2C ;;right value Bx Encoder3,Bx KeyRegister
StoreEn4: sbrs ldi sbrc ldi clr sts rjmp
Bx,0 Ax,0x2F ;;left value Bx,0 Ax,0x2E ;;right value Bx Encoder4,Bx KeyRegister
;;left value ;;right value
BOOT DR8 ALM CLK CLOCK 8564 90 DAYS DELAYS CALL ID DTMF 314 Encodersub: ldi ldi add clr adc ijmp EncoderTable: rjmp rjmp rjmp rjmp rjmp
PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
Zl,low(EncoderTable) Zh,High(EncoderTable) Zl,ax Dx Zh,Dx
Encoder_1 Encoder_2 Encoder_3 Encoder_4 Encoder_5
;;from idle ;;clock wise point 1 ;;clockwise point 2 ;;anticlockwise point 1 ;;anticlockwise point 2
Encoder_1: sbrs rjmp sbrc rjmp ldi rjmp
Bx,0 test_cw Cx,0 NoEncoderChange Ax,0x01 ;;clockwise point 1 StoreEncoder
test_cw: sbrs rjmp ldi rjmp
Cx,0 NoEncoderChange Ax,0x03 ;;anti clockwise point 1 StoreEncoder
Encoder_2: sbrs rjmp sbrs rjmp Invalid_Switch: ldi rjmp
Encoder_2a: sbrc rjmp ldi rjmp Encoder_3: sbrs rjmp sbrs rjmp
Bx,0 Encoder_2a Cx,0 NoEncoderChange
;;no change
Ax,0x00 StoreEncoder
Cx,0 Invalid_Switch Ax,0x02 StoreEncoder
;;move to point 2
Bx,0 NoEncoderChange Cx,0 NoEncoderChange ;;;;valid clockwise turn Bx,0x01 EncoderActivate
ldi rjmp ;;;;;;;;;; Encoder_4: sbrs Cx,0 rjmp Encoder_4a sbrs Bx,0 rjmp NoEncoderChange rjmp Invalid_Switch Encoder_4a: sbrc Bx,0 rjmp Invalid_Switch ldi Ax,0x04 rjmp StoreEncoder
;;no change
;;move to point 2
Encoder_5: sbrs rjmp sbrs rjmp
Bx,0 NoEncoderChange Cx,0 NoEncoderChange ;;;;valid anticlockwise turn clr Bx rjmp EncoderActivate ;;;;;;;;;;;;;;;;;;;;;;;;;;;; StoreEncoder: clc ret NoEncoderChange: clc ret EncoderActivate: sec ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-Programmable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available low-speed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language http://avr-asm.tripod.com/encode.html (1 of 2)1/20/2009 9:21:38 PM
16 BIT MATH (AVR 202)
http://avr-asm.tripod.com/encode.html (2 of 2)1/20/2009 9:21:38 PM
16 BIT MATH (AVR 202)
The AVR Assembler Site
STH-11 CONVERSION ROUTINE HOME RETRO_DAN ASM FORUM ASM MATH TUTORIAL #1 TUTORIAL #2 TUTORIAL #3 MATH 200 MATH 200b MATH 201 MATH 202 MATH 32X MATH YX DIV16 XX DIV 24 24 DIV 3216 FLOAT 128 SQRT16 MATH 202 MATH 202 DEC ASCII INT ASCII HX2ASC
; *************************************************************************** ; ; File Name :'conv.asm" ; Title :STH-11 konverzios rutinok ; Date :2002.11.27. ; Version :1.0.0 ; Support telephone :+36-70-333-4034 VFX ; Support fax : ; Support Email :[email protected] ; Target MCU :AT90S8515 ; ; *************************************************************************** ; D E S C R I P T I O N ; ; ; ; *************************************************************************** ; M O D I F I C A T I O N H I S T O R Y ; ; ; rev. date who why ; ------------- -------------------------------------; 0.01 2002.11.27. VFX Creation ; ; ; ***************************************************************************
AVG8 222 ;********************************************** .DSEG Temperature: .byte 2 Humidity: .byte 2
FFT7 COPY 102 LPM 108 EPROM 100 SER EPROM DFLASH AT45 FLASH CARD VFX SMIL VFX MEM SORT 220 CRC 236 XMODEM REC UART 304 UART 305 UART 128 UART BUFF USB 232 AVR ISP
.CSEG ; *************************************************************************** ; Public Parts: ; ; CaltTemp - Homerseklet kiszamitasa A valtozat ; Calc_Temp B valtozat ; CalcHum - Paratartalom kiszamitasa ; ; *************************************************************************** ;* Const Def ; ; ; ; ; ************************************************************************** ;* Hardware Def.
ISP 2313 ISP 1200
.include "mat32.asm" .include "8515DEF.INC"
AVR SPI I2C 300 I2C 302 I2C TWI26 I2C/TWI 128 I2C/TWI AT8 DALLAS-1W DALLAS CRC ETHNET 8019 TEA
; ************************************************************************** ;** Homersekletet ASCIIban kiirja a ASCIIBuf-ba, 0-val lezarva ; PrintTemp: lds mant1,Temperature+0 lds mant1m,Temperature+1 clr mant1h clr mant1hh rcall ULTOA ret
ADC 128 ADC 10B ADC 400 ADC 401 THERM 232 IRD 410 LCD HD44 LCD 2313 LCD44 2313 KBD 240 MUX 242 KBD PS2 KBD PC/128 PS2 EMU BOOT MG8 BOOT DR8 ALM CLK CLOCK 8564
; ************************************************************************** ;* Y = mx+b fugveny, konstansok a programmemoriaban m,b sorrenden ;* Z - konstans tabla elso eleme ;* ACC1 = eredmeny ; LinearF: lpm adiw ZL,1 mov mant2,R0 lpm adiw ZL,1 mov mant2m,R0 lpm adiw ZL,1 mov mant2h,R0 lpm adiw ZL,1 mov mant2hh,R0 push ZL push ZH rcall UMUL pop ZH pop ZL
90 DAYS
lpm adiw mov lpm adiw mov lpm adiw mov lpm adiw mov push push rcall pop pop ret
DELAYS CALL ID DTMF 314 PWM 6CH PWM 10K ENCODE STH-11 ATMEL CORP AVR BUTTERFLY AVR BOOK
ZL,1 mant2,R0 ZL,1 mant2m,R0 ZL,1 mant2h,R0 ZL,1 mant2hh,R0 ZL ZH ADD32 ZH ZL
; ************************************************************************** ;* Homerseklet szamitas ;* ;* ;* Y = m * x + b ;* 10T = 0.1 * x - 400 /*65536
TRC:
.db 0x9A,0x19,0x00,0x00 ;m =
0x00001999 vagy 199A .db 0x00,0x00,0x70,0xFF ;b = 0xFF700000 Calc_Temp: clr clr
mant1h mant1hh
ldi ldi
ZL,Low(TRC*2) ZH,High(TRC*2)
rcall sts sts ret
LinearF Temperature+0,mant1h Temperature+1,mant1hh
;ACC1 = ADC
value 0..16383
YCalcEnd:
;konstansok
; ************************************************************************** ;* Paratartalom szamitas ;* ;* Adatlap alpjan 12 bitre ;* x - paratartalom binaris erteke (ADC) 0..4095 ;* T - homerseklet kiszamolt erteke C-ban ;* ; RHlin = -2.8*10^-6*x^2 + 4.05*10^-2 * x -4 ; RHtrue= (T-25)*(10^-2 + 8*10^-5*x) +RHlin ; ;mindket egyenletet 10zel felszorozzuk a kijelzes miatt (T erteket nem az eleve 10T) ; ;Resz szamitasok: ; a, (T-250) - sub32 ; b, ((10^-1 + 8*10^-4*x)) - linf ; c, 4.05*10^-1 * x - 40 - linf ; d, -2.8*10^-5*x^2 - negyzet eftedi ; ; e, a*b ; ; RHtrue=a*b+c+d ; ; ;* ;* ;* ;*
Y = m * x + b 'B' = 0.0008 * x + 0.1
PartB: 0x00000034
.db 0x34,0x00,0x00,0x00 ;m =
0.0008 *65536 .db 0x9A,0x19,0x00,0x00 ;b = 0x0000199A
0.1 * 65536 ;* ;*
Y = m * x + b 'C' = 0.405 * x - 40
PartC: 0x000067AE
.db 0xAE,0x67,0x00,0x00 ;m =
0.405 *65536 .db 0x00,0x00,0xD8,0xFF ;b = 0xFFD80000
-
40 * 65536
CalcHum: mov mov
R6,mant1 R7,mant1m
;
paratartalmat elmentjuk ; homerseklet mar kiszamolva memoriban van clr clr
mant1h mant1hh
;ACC1 = ADC
ldi
ZL,Low(PartB*2)
;konstansok
ldi rcall
ZH,High(PartB*2) LinearF
;ACC1-ben a
value 0..4095
a 'B' szamitashoz
'B' szamitas eredmenye ;itt az 'A' szamitasa jon ; T-250 lds lds clr clr
mant2,Temperature+0 mant2m,Temperature+1 mant2h mant2hh
;ACC2
subi sbci sbci sbci
mant2,250 mant2m,0 mant2h,0 mant2hh,0
;levontunk
rcall
UMUL
;acc1 = E =
push push push push
mant1 mant1m mant1h mant1hh
mov mov clr clr ldi
mant1,R6 mant1m,R7 mant1h mant1hh ZL,Low(PartC*2)
ldi rcall
ZH,High(PartC*2) LinearF
pop pop pop pop rcall
mant2hh mant2h mant2m mant2 add32
push push push push
mant1 mant1m mant1h mant1hh
mov mov clr clr
mant1,R6 mant1m,R7 mant1h mant1hh
mov mov clr clr rcall
mant2,R6 mant2m,R7 mant2h mant2hh UMUL
ldi ldi ldi ldi
mant2,0xD6 mant2m,0x01 mant2h,0x00 mant2hh,0x00
rcall
UMUL
clr mov mov mov
mant2hh mant2h,mant1hh mant2m,mant1h mant2,mant1m
pop pop pop pop rcall
mant1hh mant1h mant1m mant1 sub32
homerseklet
250-t
A * B
/*65536
;x erteke
;konstansok
a 'C' szamitashoz ;ACC1-ben a
'C' szamitas eredmenye
;x erteke
;x erteke
;ACC1 = X^2
;2.8*10^-5
* 65536*256
;256-tal
osztjuk az eredmenyt
;ACC1-ben a vegeredmeny sts sts
Humidity+0,mant1h Humidity+1,mant1hh
;65536 valo
szorzas miatt csak ; a felo 16 bit kell ret
Programming the AVR Microcontrollers in Machine Language
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semi-permanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are selfprogrammable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K InSystem Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many additional features for audio and video processing, intended to compete with ARM based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard architecture machine with programs and data stored and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for external memory (though still available on some devices). [edit] Program Memory Program instructions are stored in semipermanent Flash memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed using 16 bit word sizes. The size of the program memory is indicated in the naming of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data Memory and Registers The data address space consists of the register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are classified as 8-bit RISC devices. The working registers are mapped in as the first thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after both these sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case memory mapped I/O registers will occupy a portion of the SRAM.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often used for long-term parameter storage to be retrieved even after cycling the power of the device. [edit] Program Execution Atmel's AVRs have a single level pipeline design. The next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR family of processors were designed for the efficient execution of compiled C code. The AVR instruction set is more orthogonal than most eight-bit microcontrollers, however, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note though, that neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for [produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation usually requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Because many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are marketed under various names that share the same basic core but with different peripheral and memory combinations. Some models (notably, the ATmega range) have additional instructions to make arithmetic faster. Compatibility amongst chips is fairly good. See external links for sites relating to AVR development. [edit] Features Current AVRs offer a wide range of features: RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators Internal, SelfProgrammable Instruction Flash Memory up to 256K Inhttp://avr-asm.tripod.com/sth11.html (1 of 2)1/20/2009 9:22:12 PM
16 BIT MATH (AVR 202)
System Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/ USART) (As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller Support USB Controller Support Proper High-speed hardware & Hub controller with embedded AVR. Also freely available lowspeed (HID) software emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v Multiple PowerSaving Sleep Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR machine programming language
http://avr-asm.tripod.com/sth11.html (2 of 2)1/20/2009 9:22:12 PM
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