Avr Architecture [lect-03 Fall09]

Microprocessor Interfacing Lecture 03

y Memory, Data  y Address Space,  y Memory Types, y Memory Access Protocol y Buses y Memory Map

y Difference Between CISC & RISC y Difference Between Von Neumann Architecture & Harvard  Diff  B  V  N  A hi  & H d  y y y y

Architecture Register Set Instruction Set S U R P R I S E ATMEL AVR ATMega16 y y y y y y

Overview Non‐Volatile and Data Memory PORT System y Peripheral Features Physical and Operating Parameters Hardware Configuration

y RISC vs. CISC y The RISC machine executes instructions faster because it does not have to go 

through a microcode conversion layer. The RISC compiler generates more  instructions than the CISC compiler for the same processing. See microcode. CISC APPROACH MULT 2:3, 5:2 RISC APPROACH LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

y A von Neumann architecture has 

only one bus which is used for both  l    b   hi h i   d f  b h  data transfers and instruction  fetches, and therefore data transfers  and instruction fetches must be  scheduled ‐ they can not be  performed at the same time. y Harvard architecture has separate 

data and instruction busses, allowing  transfers to be performed  simultaneously on both busses.

y Accumulator y Data Registers y Address Registers y General Purpose Registers y Constant Registers y Floating Point Registers y Index Registers g y Stack Pointer y Control Registers y Program Counter Program Counter y Processor Flags ƒ Result Flags ƒ Control Flags Control Flags

y An instruction set is a group of instructions a machine 

‘‘understands’’ to execute.

; Add R1:R0 to R3:R2

MUL MOVW

r5,r4 ; Multiply unsigned r5 and r4 r4,r0 ; Copy result back in r5:r4

AND r2,r3 ; Bitwise and r2 and r3, result in r2 LDI r16,1 ; Set bitmask 0000 0001 in r16 AND r2,r16 ; Isolate bit 0 in r2

CLR Loop:

ADD r2,r0 ; Add low byte ADC r3,r1 ; Add with carry high byte r22 inc r22

; clear r22

r22,$4F L Loop

; Compare r22 to $4f

; increment r22

... CPI BRNE nop

; Branch if not equal ; Continue (do nothing)

1. Describe what are addressing Modes and why do we need them? Hint: Register Direct, Register Indirect, Program Counter-Based, Absolute Mode, Immediate Mode

2. Please Memorize the Function of each Register in the Register Set of ATMEGA16? [Register Set is provided in Datasheet of ATMega16] 3. Describe AVR ATMega16 Instruction Set Categorize? Hint: Arithmetic & Logic Unit, Branch Instruction, Data Transfer Instruction, Bit and BIT test Instructions,

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MCU Control Instructions Instruction Set is provided in Datasheet of ATMega16

4. Read Thoroughly ATMEL AVR Architecture Overview Hint: Reading Material is given, Please put a great attention on Highlighted text

Overview

y Reduced Instruction Set Computer y Assembly Language Instruction Set y ATMega16 Architecture Overview y External Connections y External Time Base y I/O Ports y Processor Reset y ADC y Interrupt Subsystem y Memory System y Communication Systems

y In‐system Programmable Flash EEPROM g y Byte Addressable EEPROM y Static Random Access Memory

y Four 8‐bit General Purpose, 

digital I/O Ports y Each port has three registers  associated with it y Data Register [PORTX] = used 

to write output data to the port y Data Direction Register [DDRX]  [ ] = used to set a specific port pin  to either output (1) or input (0) y Input Pin Address [PINX] =  used to read input data from  p port

y Time Base y Timing Subsystem y Pulse Width Modulation channels y Serial Communication y Serial USART y Serial Peripheral Interface p y Two Wire Serial Interface y Analog to Digital Converter y Interrupts I

y Packaging g g y Power Consumption y Speed Grades