8255

Computer Interfacing

8255

1

Computer Interfacing

• All ports are 8 bits • PA0 - PA7:

2

– 8 bits IN – 8 bits OUT – 8 bits IN/OUT

(modes 0 or 1) (modes 0 or 1) (mode 2)

• PB0-PB7 – 8 bits IN – 8 bits OUT

(modes 0 or 1) (modes 0 or 1)

Computer Interfacing

• PC0-PC7

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– CU (upper bits PC4 - PC7) – CL (lower bits PCO - PC3) – 8 bits IN (modes 0) – 8 bits OUT (modes 0) – Each bit separately (mode BSR) – Few pins (4,5) (?)

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CS

A1

A0

Selects

0

0

0

Port A

0

0

1

Port B

0

1

0

Port C

0

1

I

Control register

1

X

X

!

is not selected 8255

Computer Interfacing

Control Word Format (I/O Mode)

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Computer Interfacing

Mode selection of the 8255A

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• While ports A, B, and C are used for I/O data, it is the control register that must be programmed to select the operation mode of the three ports A, B, and C. The ports of the 8255 can be programmed in any of the following modes • It has three modes of operation

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Mode 0

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• Simple I/O mode • Any of the ports A, B, CL, and CU can be programmed as input or output • All bits are out or all are in (there is no control of individual bits)

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Mode 1

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• Simple I/O with handshaking capabilities • Ports A and B can be used as input or output ports with handshaking capabilities • Handshaking signals are provided by the bits of port C (the device provides the handshaking signals)

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Mode 2

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• Bidirectional port A with handshaking capabilities • Port A can be used as a bidirectional I/O port with handshaking capabilities whose signals are provided by port C. (the device provides the handshaking signals)

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BSR (bit set/reset) mode

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• Only the individual bits of port C can be programmed • The 8255 chip is programmed in any of the above modes by sending a byte (or what’s called control word) to the control register of the 8255.

Computer Interfacing

BSR (bit set/reset) mode

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• A unique feature of port C is that the bits can be controlled individually. BSR mode allows one to set to high or low any of PC0 to PC7 as shown in Figure below.

Example

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• Program PC4 of the 8255 in the following Figure to generate a pulse of 50 ms with 50% duty cycle.

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Computer Interfacing

Solution:

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• To program the 8255 in BSR mode, • bit D7 of the control word must be low. • For PC4 to be high, we need a control word of ‘0xxx1001". • Likewise, for low we would need “0xxx1000" as the control word. • The x's are for "don't care" and generally are set to zero. MOV AL, 00001001B OUT 93H,AL CALL DELAY MOV AL, 00001000 B OUT 93,AL CALL DELAY

; load the control byte (PC4=1) ;set PC4 to high, sent to control reg ;time for the high part of pulse ;load the control byte (PC4=0) ;set PC4 to low, sent to control reg ;time for the low part of pulse

Interrupts vs. polling •

Computer Interfacing

•

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• •

• •

The CPU services various devices. There are two ways for the CPU to provide service to those devices: interrupts and polling. In the interrupt method, whenever any device needs its service, the device informs the CPU by sending it an interrupt signal. The CPU interrupts whatever it is doing and serves the request for service. In polling, the CPU continuously monitors a status condition and when the conditions are met it will perform the service. The advantage of interrupts is that the CPU can serve many devices (of course, not all at the same time). Each device receives service from the CPU based on the priority assigned to it. It can also ignore (mask) a device request for service. The disadvantage of interrupts is that they require much more hardware and software. In contrast, polling is cheap and requires minimal software, but it ties down the CPU. To avoid tying down the CPU, interrupts are the preferred choice.

Computer Interfacing

Handshaking capabilities

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• Handshaking refers to the process of communicating back and forth between two intelligent devices • 8255 handles handshaking signals (a powerful built in features of the 8255)

• Printers are good example for a device with handshaking capabilities

Printer handshaking signals 8255

Computer Interfacing

PA

16

Printer D0 – D7

PC7

STROBE

PC6

ACK

Printer handshaking signals • Computer Interfacing

•

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• •

A byte of data is presented to the data bus of the printer. The printer is informed of the presence of a byte of data to be printed by activating its STROBE input signal. Whenever the printer receives the data it informs the sender by activating an output signal called ACK (acknowledge). The ACK signal initiates the process of providing another byte of data to the printer.

Computer Interfacing

Outputting data with handshaking signals (mode 1)

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Inputting data with handshaking signals (mode 1)

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Mode 1: I/O with handshaking signals

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• As shown, A and B can be used as output ports to send data to a device with handshaking signals. • The handshaking signals for both ports A and B are provided by the bits of port C.

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Outputting data with handshaking signals (mode 1)

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Computer Interfacing

OBFa (output buffer full for port A)

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• Active-low signal going out of PC7 • Indicate that the CPU has written a byte of data into port A, so the receiving equipment can read it • OBFa must be connected to STROBE of the receiving equipment (such as a printer)

Computer Interfacing

ACKa (acknowledge for port A)

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• Active-low signal (Has limited duration) • Received at PC6 of the 8255 • Indicates that the data at port A has been picked up by the receiving device • The 8255 in turn makes OBFa high, to indicate that the data at the port is old data • OBFa will not go low until the CPU writes a new byte of data to port A

Computer Interfacing

INTRa (interrupt request for port A)

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• Active-high signal coming out of PC3 • Activated by the rising edge of ACK which is active for a short period of time • Signal on INTRa can be used to get the attention of CPU (printer has received the last byte and is ready to receive another one) • INTRa interrupts the CPU to write the next byte to port A to be printed.

Computer Interfacing

INTEa (interrupt enable for port A)

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• 8255 can disable INTRa to prevent it from interrupting the CPU • INTEa is an internal flip-flop designed to mask (disable) INTRa • INTEa can be set or reset through port C in BSR mode since the INTEa flip-flop is controlled through PC6 • INTEb is controlled by PC2 in BSR mode

Computer Interfacing

Status word

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• 8255 enables monitoring the status of signals INTR, OBF, and INTE for both ports A and B • This is done by reading port C into the accumulator and testing the bits • This feature allows the implementation of polling

Interrupts vs. polling •

Computer Interfacing

•

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• •

• •

The CPU services various devices. There are two ways for the CPU to provide service to those devices: interrupts and polling. In the interrupt method, whenever any device needs its service, the device informs the CPU by sending it an interrupt signal. The CPU interrupts whatever it is doing and serves the request for service. In polling, the CPU continuously monitors a status condition and when the conditions are met it will perform the service. The advantage of interrupts is that the CPU can serve many devices (of course, not all at the same time). Each device receives service from the CPU based on the priority assigned to it. It can also ignore (mask) a device request for service. The disadvantage of interrupts is that they require much more hardware and software. In contrast, polling is cheap and requires minimal software, but it ties down the CPU. To avoid tying down the CPU, interrupts are the preferred choice.

Computer Interfacing

Mode 1: input ports with handshaking signals

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• The 8255 can be programmed to receive data through ports A and B using handshaking signals through port C • The signals are as follows:

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Inputting data with handshaking signals (mode 1)

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Computer Interfacing

STB (strobe)

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• Active-low input signal. When an external peripheral device provides a byte of the data to an input port (A or B), it informs the 8255 through the STB pin that it can load (latch in) the data into its internal register • STB is of limited duration. This signal goes low (active), stays low for a time, and goes back high. The amount of time it stays low depends on the device.

Computer Interfacing

IBF (input buffer full)

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• Active-high output signal. In response to STB, the 8255 latches into its internal register the data present at PA0-PA7 or PB0-PB7, and through IBF indicates that it has latched the data, but it has not been read by the CPU yet • To get the attention of the CPU to read the data, IBF activates INTR (sets it high).

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INTR (interrupt request)

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• Active-high output signal. • If INTE =1 • When IBF goes active, INTR is activated (set to high) to inform the CPU that there is a byte of data in the 8255. • Either an interrupt or polling the status word can be used to read the data from port A or B. • It is only when the CPU reads the data by activating the RD (going low) signal of the 8255 that INTR becomes inactive (the falling edge of RD makes INTR go low)

Computer Interfacing

INTR (interrupt request)

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• The RD signal from the CPU is of limited duration and when it goes high, the 8255 in turn makes IBF inactive by setting it low. • IBF informs the peripheral device that the byte of data was latched by the 8255 and transferred to the CPU as well. • By receiving IBF, the external device knows it can send another byte to the 8255's port A or port B. • Then it sets low STB, and the process is repeated. • Notice that INTR is set to one when all three signals STB, IBF, and INTE are high.

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• INTE (interrupt enable) • An internal flip-flop can be used to enable or disable (mask) INTR generation. It is controlled by PC4 and PC2 in BSR mode. • To control INTEa and INTEb, use PC4 and PC2, respectively. • Status word • To allow implementation of polling, the status of the handshaking signals provided by port C can be checked by reading port C.

Computer Interfacing

Outputting data with handshaking signals (mode 1)

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Computer Interfacing

Inputting data with handshaking signals (mode 1)

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Computer Interfacing

Mode 2: bidirectional I/O with handshaking

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• To transfer data both in and out via the same port with handshaking capability, port A is used in mode 2. • The handshaking signals for port A are provided by selected bits of port C. • In mode 2, in addition to bidirectional port A, we can also configure port B in either mode 0 or 1. This is shown in Figure below

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Mode 2

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8255 Programmable Peripheral Interface Features: •3 8-bit IO ports PA, PB, PC

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•PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for mode 0 and for BSR. Modes 1 and 2 are interrupt driven. •PC has 2 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently for I or O. Each PC bit can be set/reset individually in BSR mode. •PA and PCU are Group A (GA) and PB and PCL are Group B (GB) •Address/data bus must be externally demux'd. •TTL compatible. •Improved dc driving capability

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A1 0 0 1 1

A0 0 1 0 1

Select PA PB PC Control reg.

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Computer Interfacing

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BSR mode Bit set/reset, applicable to PC only. One bit is S/R at a time. Control word:

D7 0 (0=BSR)

D6 X

D5 X

D4 X

D3 B2

Computer Interfacing

Bit select: (Taking Don't care's as 0) B2 B1 B0 PC bit Control word (Set) 0 0 0 0 0000 0001 = 01h 0 0 1 1 0000 0011 = 03h 0 1 0 2 0000 0101 = 05h 0 1 1 3 0000 0111 = 07h 1 0 0 4 0000 1001 = 09h 1 0 1 5 0000 1011 = 0Bh 1 1 0 6 0000 1101 = 0Dh 1 431 1 7 0000 1111 = 0Fh

D2 B1

D1 B0

D0 S/R (1=S,0=R)

Control word (reset) 0000 0000 = 00h 0000 0010 = 02h 0000 0100 = 04h 0000 0110 = 06h 0000 1000 = 08h 0000 1010 = 0Ah 0000 1100 = 0Ch 0000 1110 = 0Eh

I/O mode

D6

1 (1=I/O)

GA mode select

Computer Interfacing

D7

D5

D4 D3

D2

PA PCU GB mode select

D1 D0

PB PCL

D6, D5: GA mode select: 00=mode0, 01=mode1, 1X=mode2 D4(PA), D3(PCU): 1=input 0=output D2: GB mode select: 0=mode0, 1=mode1 D1(PB), D0(PCL): 1=input 0=output Mode 0: No interrupts. Plain I/O. Two 8 bit ports PA, PB. Two 4 bit ports PCU and PCL. Outputs latched, inputs buffered. 44

3 to 8 Line decoder

Io/m’ o3

gnd Computer Interfacing

a7 a6

0 1 a5 1

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Cs’

LEDS

8255

a1 1 a0 0 Port address

011 x x x 00 Port A 011 x x x 01 Port B 011 x x x 10 Port C 011 x x x 11 ctrl

60h 61h 62h 63h

Program

Computer Interfacing

MVI a,80h Out 63h Mvi a,ofh Back: Out 62h Call delay Dcr a ani ofh Jmp back

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Delay:mvi a,0ah Back2: mvi b,64h Back1: mvi c, d1h Back: dcr c jnz back dcr b jnz back1 dcr a jnz back2 ret

3 to 8 Line decoder Port A Keys

Io/m’ o3

gnd Computer Interfacing

a7 0 0a6 a5 0

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Cs’

Port Cl keys

8255

Port ch LEDS

a1 1 a0 0 Port address

000 x x x 00 Port A 000 x x x 01 Port B 000 x x x 10 Port C 000 x x x 11 ctrl

Command word 1 00 1 0 0 0 1=91h

00h 01h 02h 03h

Port B LEDs

MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “handshaking” signals. In mode 1, port A and Port B use the lines on port C to generate or accept these “handshaking” signals.

Computer Interfacing

Mode 1 Basic Functional Definitions:

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• Two groups (Group A and Group B) •Each group contains one 8-bit data port and one 4-bit control/data port •The 8-bit data port can be either Inputs or output Both inputs and outputs are latched. • The 4-bit port is used for control and status of the 8-bit data port.

Computer Interfacing

INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. Output Operations OBF (Output Buffer Full). The OBF output will go “low” to indicate that the CPU has written data out to port A. ACK (Acknowledge). A “low” on this input enables the tri-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled by bit set/reset of PC6

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Input Operations STB (Strobe Interrupt) STB (Strobed Input). A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F). A “high” on this output indicates that data has been loaded into the input latch. INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled by bit set/reset of PC4.

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There are several combinations or modes when not all of the bits in Port C are used for control or status. The remaining bits can be used as follows: If Programmed as InputsAll input lines can be accessed during a normal Port C read. If programmed as OutputsBits in C upper (PC7-PC4) must be individually accessed using the bit set/reset function. Bits in C lower (PC3_Pco) can be accessed using the bit set/reset function or accessed as a threesome by writing into Port C.

Computer Interfacing

Source Current Capability on Port B and Port C

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Any set of eight output buffers, selected randomly from Ports B and Ports C can source 1mA at 1.5volts. This feature allows the 8255A to directly drive Darlington type drivers and high-voltage displays that require such source current.

Computer Interfacing

Reading Port C Status

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In Mode O, Port C transfers data to or from the peripheral device. When the 8255 is programmed to function in Modes 1 or 2, Port C generates or accepts “hand shaking” signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the “status” of each peripheral device and change the program flow accordingly. There is a special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function.

MODE 1 STATUS WORD FORMAT

D7

D6

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I/ I/ O O

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D5 I B F A

D4 IN T EA

IN T RA

D3 IN T EB

I B F B

D2 IN T RB

D1

D0

D7

D6

O

Computer Interfacing

B FA

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I N T E A

D5 I/ O

D4 I/ O

IN T RA

D3

INT EB

O B F B

D2

INT ERB

D1

D0

D7

O B FA

D6

IN T E1

I B F

D5 D1 IN T E2

D4 D0

D3

D2

IN T RA

Computer Interfacing

A

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DEFINE BY MODE 0 MODE 1 SELECTION

Computer Interfacing

INTR (Interrupt Request)

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A “high” on this output can be used to interrupt the CPU when an input device is requesting service, INTR is set by when the STB is a “one”, IBF is a “one “ and INTE is “one “. It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into port.

INTE A Controlled by bit set/reset of PC4 INTE B Controlled by set/reset PC2

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Computer Interfacing

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OBF (Output Buffer Full F/F). The OBF output will go “low” to indicate that the CPU has written data out to the specified port. The OBF F/F will be set by rising edge of the WR input being low. ACK (Acknowledge Input). A “low” on this input informs the 8255A that the data from port A or port B has been accepted. In essence, a response from the peripheral device indicating that it has received the data output by CPU. INTR (Interrupt Request). A “high” on the output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a “one”, OBF is a “one”, and INTE is a “one”. It is reset by the falling edge of WR. INTE A Controlled by bit set/reset of PC6. INTE B

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Computer Interfacing

Combination of MODE 1 Port A and B can be Individually defined as Input or output in Mode 1 to support a wide variety of strobed I/O application.

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Control word 1 01 1 0 1 0 0=b4h BSR word to set INTEA=0 000 100 1=09h Status word to check obfb’=xxxx xx1x=02h Mvi a,b4h Out ffh Mvi a,09h Ei Call print Lxi h,mem Mvi c,count Next: Mov a,m mov c,a Status: in feh ani 02h jz status mov a,c out fdh inx h dcr b jnz next ret

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ode 2 (Strobed Bidirectional Bus I/O). This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus I/O). “Handshaking” signals are provided to maintain proper bus flow discipline in a similar manner to MODE. .

Interrupt generation and enable/disable functions are also available.

MODE 2 Basic Functional Definitions:

Computer Interfacing

•

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Used in Group A only.

•One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C). •Both Inputs and Outputs are latched. •The 5-bit control port (Port C) is used for control and status for the 8-bit,bi-directional bus port (Port A).

INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations.

Output Operations

OBF output will go “low” to indicate that the CPU has written data out to port A. ACK (Acknowledge). A “low” on this input enables the iri-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled by bit set/reset of PC6

Computer Interfacing

OBF (Output Buffer Full). The

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