8051
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8051 Microcontroller
Designing with Microcontrollers
Friday, October 17, 2008
SFR
B
PC
DPTR DPH DPL
ROM
Port 3
Port 2
A
PSW
Port 1
ALU
Port 0
8051 BLOCK DIAGRAM I/O A0-A7 D0-D7
I/O
I/O A8-A15
I/O INT CNTR SERIAL RD/WR
Friday, October 17, 2008
~EA ALE PSEN XTAL1 XTAL2 RESET VCC
System Timing System Interrupt Timers Data Buffers Memory Controls
GND
BYTE / BIT ADDRESSIBLE
SFR
RB3
IP
RB2
PCON
RB1 RB0
IE
SBUF SCON TCON TMOD TL0 TH0 TL1 TH1
INTERNAL RAM STRUCTURE Friday, October 17, 2008
A* E0
B* F0
MATH REGISTERS
IP* B8
IE* A8
TMOD 89
INTERRUPT REGISTERS
THO 8C
TCON* 88
TIMER CONTROL REG
TLO 8A
TH1 8D
TL1 8B
TIMER / COUNTER REGISTERS
SCON* 98
SBUF 99
PCON 87
SERIAL DATA REGISTERS
SP 81
Friday, October 17, 2008
PSW* D0 FLAGS
DPTR DPH DPL 83 82
PORT 0* LATCH 80
Friday, October 17, 2008
PC
PORT 1* LATCH 90
PORT 2* LATCH A0
PORT 3* LATCH B0
PSW
CY
AC
F0
RS1
RS0
CY
Carry Flag used in arithmetic and Boolean operation
AC
Auxiliary Carry, used in BCD arithmetic
F0
User Flag 0
RS1
Register Bank select bit 1
RS0
Register Bank select bit 0
OV P
RS1
RS0
0
0
Select Register Bank 0
0 1 Select Register Bank 1 1 0 Select Register Bank 2 1 1 Select Register Bank 3 Overflow Flag used in arithmetic instructions Parity, shows parity of register A; 1 = Odd Parity
Friday, October 17, 2008
OV
-
P
TIMERS & COUNTERS THE TIMER CONTROL (TCON) 7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
1
TF1
Timer 1 Overflow flag. Set when timer rolls from all 1s to 0. Cleared when processor vectors to execute interrupt service routine located at program address 001Bh.
2
TR1
Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer.
3
TF0
Timer 0 Over flow flag. Set when timer rolls from all 1s to 0. Cleared when processor vectors to execute interrupt service routine located at program address 000Bh.
4
TR0
Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer.
5
IE1
6
IT1 External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external interrupt 1 to generate an interrupt.
7
IE0
0
External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin 3.3 (INT 1). Cleared when processor vectors to interrupt service routine located at program address 0013h. Not related to timer operations.
External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin 3.2 (INT 0). Cleared when processor vectors to interrupt service routine located at program address 0003h. Not related to timer operations.
IT0 External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt 0 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external interrupt 0 to generate an interrupt. Friday, October 17, 2008
THE TIMER MODE CONTROL (TMOD) 7
Gate
6
5
C/T
4
M1
3
M0
Gate
Timer 1
2
1
C/T
M1 Timer 0
7/3
Gate
OR gate enable bit which controls Run/ Stop of timer
6/2
C/T
Set to 1 by program to make timer act as counter
5/1
M1
Mode select bit 1
4/0
M0
Mode select bit 0
Friday, October 17, 2008
M1
M0
Mode
0
0
0
0
1
1
1
0
2
1
1
3
0
M0
Designing with Microcontrollers
Friday, October 17, 2008
SFR
B
PC
DPTR DPH DPL
ROM
Port 3
Port 2
A
PSW
Port 1
ALU
Port 0
8051 BLOCK DIAGRAM I/O A0-A7 D0-D7
I/O
I/O A8-A15
I/O INT CNTR SERIAL RD/WR
Friday, October 17, 2008
~EA ALE PSEN XTAL1 XTAL2 RESET VCC
System Timing System Interrupt Timers Data Buffers Memory Controls
GND
BYTE / BIT ADDRESSIBLE
SFR
RB3
IP
RB2
PCON
RB1 RB0
IE
SBUF SCON TCON TMOD TL0 TH0 TL1 TH1
INTERNAL RAM STRUCTURE Friday, October 17, 2008
A* E0
B* F0
MATH REGISTERS
IP* B8
IE* A8
TMOD 89
INTERRUPT REGISTERS
THO 8C
TCON* 88
TIMER CONTROL REG
TLO 8A
TH1 8D
TL1 8B
TIMER / COUNTER REGISTERS
SCON* 98
SBUF 99
PCON 87
SERIAL DATA REGISTERS
SP 81
Friday, October 17, 2008
PSW* D0 FLAGS
DPTR DPH DPL 83 82
PORT 0* LATCH 80
Friday, October 17, 2008
PC
PORT 1* LATCH 90
PORT 2* LATCH A0
PORT 3* LATCH B0
PSW
CY
AC
F0
RS1
RS0
CY
Carry Flag used in arithmetic and Boolean operation
AC
Auxiliary Carry, used in BCD arithmetic
F0
User Flag 0
RS1
Register Bank select bit 1
RS0
Register Bank select bit 0
OV P
RS1
RS0
0
0
Select Register Bank 0
0 1 Select Register Bank 1 1 0 Select Register Bank 2 1 1 Select Register Bank 3 Overflow Flag used in arithmetic instructions Parity, shows parity of register A; 1 = Odd Parity
Friday, October 17, 2008
OV
-
P
TIMERS & COUNTERS THE TIMER CONTROL (TCON) 7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
1
TF1
Timer 1 Overflow flag. Set when timer rolls from all 1s to 0. Cleared when processor vectors to execute interrupt service routine located at program address 001Bh.
2
TR1
Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer.
3
TF0
Timer 0 Over flow flag. Set when timer rolls from all 1s to 0. Cleared when processor vectors to execute interrupt service routine located at program address 000Bh.
4
TR0
Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer.
5
IE1
6
IT1 External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external interrupt 1 to generate an interrupt.
7
IE0
0
External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin 3.3 (INT 1). Cleared when processor vectors to interrupt service routine located at program address 0013h. Not related to timer operations.
External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin 3.2 (INT 0). Cleared when processor vectors to interrupt service routine located at program address 0003h. Not related to timer operations.
IT0 External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt 0 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external interrupt 0 to generate an interrupt. Friday, October 17, 2008
THE TIMER MODE CONTROL (TMOD) 7
Gate
6
5
C/T
4
M1
3
M0
Gate
Timer 1
2
1
C/T
M1 Timer 0
7/3
Gate
OR gate enable bit which controls Run/ Stop of timer
6/2
C/T
Set to 1 by program to make timer act as counter
5/1
M1
Mode select bit 1
4/0
M0
Mode select bit 0
Friday, October 17, 2008
M1
M0
Mode
0
0
0
0
1
1
1
0
2
1
1
3
0
M0
