8 Chapter-7 & 8 Chapter Solns

Design of High Speed CMOS Logic Networks (Chapter 8 of John.P.Uyemura and Chapter5 of EC74) In VLSI technology, switching speed of logic circuits is an important parameter and is closely related to the timing specifications. Modern CMOS technology is capable of fabricating MOSFETS with channel lengths smaller than 65 nm. Here, the aspect ratio (W/L) is the important critical parameter in high speed CMOS logic networks. Gate delays: Gate delay is defined as the time taken by the Logic gate to respond to the signal given at its input. As shown in fig.1, the NAND gate takes a fixed duration to give the output after the input is given. This time is the gate delay. The parameters associated with the gate delay are transistor resistance, Capacitance and the load capacitance, CL. Fig.2 illustrates the variation of the gate delay for different values of CL.

Vdd

3.3Vdc U1A

A B

1

3

2 7400

0

Vout

CL

0

1n

0

Fig.1 Circuit to illustrate the definition of of gate delay

FET unit Resistance is given by

Ru =

Fig.2 Graph of delay time v/s load capacitance 1

W k' L

 (V DD − VT ) 

Where Ru is unit transistor Resistance, W and L are the width and Length of the transistor, K’

is µ n C ox Rm =

Ru , C Gm = mC Gu , C Dm = mC D u , C Sm = mC S u m

-2-

VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

Wmin = Wu

Fig.3 Minimum-Size FET

Fig.4 3X Scaled- FET

Fig.3 shows the layout of FET and Fig.4 shows the scaled FET, 3 times the original size. The parasitic capacitances for unit size FET are given by C Gu =C OX (WL) u C Du = (C GD + C DB ) u C Su = (C GS + C SB ) u where CGu, CDu and Csu are the Gate, Drain and Source Capacitances. The width of unit size FET is the minimum size given by Wmin = Wu. Fig.4 shows the scaled FET with m = 3. The aspect ratio becomes 3 times the unit FET and the aspect ratio also become e times unit FET. In general, the size of scaled FETs are integer multiples of the minimum

(W ) 3 = 3Wu

W  W    = 3   L 3  L u

The FET parasitic resistance and capacitance becomes Ru = mRu , C Gu = mC Gu , C Du = mC D u , C Su = mC S u 2

-3-

VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

It can be seen from the above expressions that, the capacitances are increased 3 times and the resistance is decreased by 3 times. But, an important observation is that, the RC product remains same RmCm=RuCu. The Resistance and capacitance of 3X FET of fig.4 is given by

Rx = 3Ru , C Gx = 3C Gu , C Dx = 3C D u , C Sx = 3C S u t r = t LH t f = t HL R R3 = u 3 CG 3 = 3CGu C D 3 = 3C D u C S 3 = 3C S u The rise time and fall time of 3X FET are given by α pu t r 3 = t ro + CL 3 α t f 3 = t fo + n u C L 3 If we connect the minimum size FET for both PMOS and NMOS as shown in Fig.5, results in an inverter. The layout of the inverter is shown in Fig.6. V1 3.3Vdc M1

0

in

out M2

0

3

-4-

Fig.5 Schematic diagram of Inverter

Fig.6 Layout of Inverter

VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Steps that has to be followed in drawing the layout of an inverter: To make NMOS FET, n+ layer has to be placed on p-type substrate. A poly layer in between the n+ layer completes the NMOSFET. This is shown in the bottom of fig.6. The drain, gate and source are indicated by Dn, Gn and Sn. To make PMOS FET, p+ layer has to be placed on p-type substrate. A poly layer in between the p+ layer completes the PMOSFET. This is shown in the top of fig.6. The drain, gate and source are indicated by Dp, Gp and Sp. The metal1 layer has to be placed to get contact with the active layer and the p+ layer. The n-well has to be placed surrounding the p+ layer. The Cell layers used during the layout of VLSI circuits are shown in fig.7. The Text book by VLSI Design by Plucknell gives the details of cell layers and layouts for various logic circuits. Students can practice these by drawing the layouts in sketch pens. It is advisable to learn them by drawing the layouts by using any of the EDA tool.

Fig.7 Cell layers in VLSI Circuits Lambda Based Rules While drawing the layouts of VLSI circuits, Design rules has to be followed. Some of them has been narrated in fig.8 and it states that, 1) The width of n+/p+ diffusion should be of minimum width 2l and the gap between two diffusions should also be 2λ.

4

-5-

Fig.8 Diagrams to illustrate the Lambda Based Rules

VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore 2) The gap between diffusion and the poly has to be of minimum width λ. 3) The width of metal1 should be of minimum width 3λ and the gap between two metal1’s should be 4λ and similar other rules has to be followed while drawing the layouts in VLSI circuits. Cell Concepts: The basic building block s in physical design are called cells. A cell may be as simple as an FET, or as complex as an arithmetic logic unit (ALU). The basic cells of inverter, NAND2, and a cell consisting of inverter, NAND2 and one more inverter at the output are shown in fig.9. Also the complex cell showing only the inputs and output have been narrated. This is the usefulness of the cell concept. This becomes useful in writing VHDL code in behavioral mode. XNAND2

XNOT Vdd in1

Vdd 1

in

2

U2A

1

out

3

2

7406

Gnd

out

7400

in2 Gnd

Fig.9 Diagrams to illustrate the Concept of cells Vdd

Vdd U3A 1

A

U4A

1

2

3

2

7406

2

A 1

3

7400

B C

U5A U6A

out

B C

7428

Gnd

out

Gnd Primitive Cells

New Complex Cell

NAND2 Gate Scaling

10.00V

V1 10V M1

M2

IRF9140

IRF9140

0V

0 10.00V V1 = 0v V2 = 10v TD = 0US TR = 0.1us TF = 0.1US PW= 1Us PER = 2Us

R1 VA

M3

47K 0V

0V

0

0

IRF150 5.000V

0V

M4 IRF150 V1 = 0v V2 = 10v TD = 0US TR = 0.1us TF = 0.1US PW= 0.5Us PER = 1Us

VB

0V

0 0

5

-6-

Fig.10 Fig.11 Fig.12 Schematic Diagram Layout using unit size FET Layout using 3X Scaled FET Switching Equations Compared to the switching equations of the inverter, NAND2 gate switching equations gets modified. VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore This is because, tr0 and tf0 are proportional to the product of Ru and CFET. In the inverter, two FETs contribute to the capacitance. But, in NAND2 gate, there are 3 FETs that touch the output node, so a factor of 3/2 has to be introduced. The Resistances scale in a different manner. The pFET resistance Rp is the same as that for an inverter, while the nFET Resistance Rn between the output node and the ground is doubled because of the series connection. The switching equations for unit NAND2 gate are 3 t r =  t ro + α pu C L 2 t f = 3t fo + 2α n u C L If we scale the FETs with m = 3, then α factors are reduced by 1/m because of the decrease in Resistance. The decrease in resistance counteracts the in crease in CFET, so that the zero-load terms are unchanged. Thus, the switching equations for m-scaled NAND2 gate and for an N-input NAND2 gate using m-scaled FETs becomes α   α pu   3  N + 1  CL tr =   tro +  pu  CL tr =   tro +  3 2 m  2        2α  t f = 3t fo +  n u  CL  3 

 Nα  t f = ( N + 1)t fo +  nu  CL  3 

Analysis of NOR2 gate can be analyzed in a similar manner. The switching equations for m-scaled NAND2 gate and for an N-input NAND2 gate using m-scaled FET’s becomes  Nα  tr = 3tro + 2α puCL tr = ( N + 1)tro +  pu  CL  m 

 3 t f =   t fo + α nuCL  2

αn   N + 1 tf =   t fo +  u  CL  2   m

The above switching equations clearly demonstrate the dependence on the number of inputs (N) and the FET Scaling factor (m). Delay time: The above technique of gate design provides a structured approach for estimating delays. Fig.13 shows a logic chain with M-stages, the total delay, td is given by M

the summation of individual 0delays. Mathematically, t d = ∑ t i

1 in

1

2

C1

2

1 3

i =1

1

3

2

C2

C3

C= 4 Cmin 0

6

-7-

Fig.13 Example for Delay time

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Fig.13 shows a logic chain with Inverter, NAND and NOR gates in the 1st, 2nd and 3 stages and load capacitor in the 4th stage. The stages are scaled with increasing values of m. This is necessary to take the additional load of previous stages. The output capacitance has to have scaling of 4, as it is in the 4th stage in the chain. The total delay is given by, rd

t d = t NOT / m =1 + t NAND 2 / m= 2 + t NOR 2 / m = 3

For the given inputs to the logic chain, the switching equation for NOT gate is of tfo, This is because the output of the NOT gate is falling from HIGH to LOW. Similarly, it can be seen that, NAND gate switching equation is of tro and for NOR gate is that of tfo, as the output of NAND gate is rising from LOW to HIGH and that of NOR gate is falling from HIGH to LOW. Applying the corresponding switching time equations, we get,

t NOT / m =1 = t f 0 + αnu 2C min t NAND 2 / m =2 = t r 0 +

αpu 2

3C min

α 3 t NOR 2 / m =3 =  t f 0 + nu 3C min 2 2

So the total delay in the chain is, 5 3  10  3 t d =  t fo +  t ro +  α nu C min +  α pu C min 2 2 3 2 It is important to note that, the expression for td will change if different inputs are applied. Overall, the technique allows us to estimate delays through logic cascades in a uniform manner.

7

-8-

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Solutions to problems in Design of High speed CMOS Logic circuits 7th chapter of John P.Uyemura: 7.1 Given Data: VDD = 3.3V VTP = -0.8V VTn = 0.6V Kn’ = 100 µA/V2 Kp’ == 42 µA/V2 To find VM From Eqn.6.109 W  β n = k n '   = 100 x10 = 1000 µA / V 2  L n W  β p = k p '   = 42 x14 = 588µA / V 2  L p From Equation 7.14   1000   VDD − / VTP / + VTn x β n    3 . 3 − 0 . 8 + 0 . 7 βp    588  VM =  = 1.358V =  β 1000    n  1+ 1+    588 β  p   VM = 1.358 V 7.2 Given Data: VDD = 3 V VTP = -0.82 V VTn = 0.6 V VM = 1.3 V βn To find βp From Equation 7.14

8

-9     VDD − / VTP / + VTn x β n   3 − 0.82 + 0.6 x β n  βp   βp   VM =  =  = 1.3V βn βn     1+ 1+     βp βp     βn = 1.580 βp VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore 7.3 VDD = 5 V VTP = -0.7 V VTn = 0.6 V β n = 2.1µA / V 2

β p = 1.8µA / V 2 a) To find VM From Equation 7.14   2.1   VDD − / VTP / + VTn x β n    5 − 0 . 7 + 0 . 6 β  p  1.8   VM =  = 2.378V =  βn 2.1     1+ 1+    1 . 8 β  p   VM = 2.378 V b) To find Rn and Rp From Equation 7.28     1 1  =   = 108Ω Rn =   β n (VDD − VTn )   2.1( 5 − 0.6 )      1 1 =  = 129Ω Rp =   β (V − / V / )   1.8( 5 − / 0.7 / )  Tp  p DD  c) To find tr and tf When CL = 0 From Equation 7.52 t f = 2.2τ p From Equation 7.32 τ p = R p C out , C out = C L + C FET = 0 + 74 = 74 fF t r = 2.2 x129 x74 x10 −15 = 21.03 ps From Equation 7.48 t f = 2.2τ n From Equation 7.32 τ n = Rn C out , C out = C L + C FET = 0 + 74 = 74 fF

9

- 10 -

t f = 2.2 x108 x74 x10 −15 = 17.582 ps d) To find tr and tf When CL = 115fF From Equation 7.52 t r = 2.2τ p From Equation 7.32 τ p = R p C out , C out = C L + C FET = 115 + 74 = 189 fF t r = 2.2 x129 x189 x10 −15 = 53.638 ps VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore From Equation 7.48 t f = 2.2τ n From Equation 7.32 τ n = Rn C out , C out = C L + C FET = 115 + 74 = 189 fF t f = 2.2 x108 x189 x10 −15 = 44.9 ps e) To plot tr v/s CL and tf v/s CL Sl.no. CL in fF tr in ps 1 0 21.03 2 30 29.515 3 60 38.029 4 90 46.543 5 115 53.638

tf in ps 17.582 24.71 31.838 38.966 44.9

Rise time

Rise time V/S <>Load Capacitance 60 40 20 0 1

2

3

4

5

4

5

Load Capacitance

Fall time

fall tim e V/S Load Capacitance 50 0 1

2

3 Load Capacitance

7.4 Given Data: VDD = 5 V VTP = -0.7V 10

- 11 VTn = 0.6V Kn’ = 150 µA/V2 Kp’ == 60 µA/V2 To find VM, From Eqn.6.109 W  4 β n = k n '   = 150 x  = 600 µA / V 2  L n  1 n W  8 β p = k p '   = 42 x  = 480 µA / V 2  L p 1p VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore From Equation 7.14   600  VDD − / VTP / + VTn x β n   β p   5 − 0.7 + 0.6 480  VM =  = β 600    n 1+ 1+   480 βp   

   = 2.244V   

VM = 2.244 V 7.5 Given Data VDD = 5V VTP = -0. VTn = 0.6V Kn’ = 150 µA/V2 Kp’ == 60 µA/V2 From Eqn.6.109 W   4  2 β n = k n '   = 150 x  = 750 µA / V  L n  0.8  W   4  2 β p = k p '   = 60  = 600 µA / V  L p  0.8  a) To find Cin From Equation 6.115 C GP = C ox (WL ) p = 2.7( 8 x0.8) = 17.28 f F

C Gn = C ox (WL ) n = 2.7( 4 x0.8) = 8.64 f F From Equation 7.30 Cin = CGn + CGP = 25.72 fF b) To find Rn and Rp From Equation 7.28

11

- 12     1 1  =   = 303Ω Rn =  −6  β n (VDD − VTn )   750 x10 x( 5 − 0.6 )      1 1 =  = 387Ω Rp =   β (V − / V / )   600( 5 − / 0.7 / )  Tp  p DD  c) To find tr and tf From Equation 7.52 t f = 2.2τ p From Equation 7.32 τ p = R p C out , C out = C L + C FET VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore From Equation 7.33, CFET = CDp + CDn From Equation 7.29, CDp = Cp + CGp/2 From Equation 6.92, Cp = Cjp Abot+ Cjspw Psw, Psw = 2(W+X) Cp = Cjp Abot + Cjspw Psw = 1.05 x 8 x 2.1 + 0.32 x 2(8 + 2.1) = 24.1 fF CDp = Cp + CGp/2 = 24.1 + 17.28/2 = 32.74 fF Similarly, Cn = Cjn Abot + Cjsnw Psw = 0.86 x 8 x 2.1 + 0.24 x 2(4 + 2.1) = 10.15 fF CDn = Cn + CGn/2 = 10.15 + 8.64/2 = 14.47 fF ∴CFET = CDp + CDn = 32.74 + 14.47 = 47.21 fF tr = 2.2 x Rp (CL + CFET) = 2.2 x 387 (80 + 47.21) = 84.724 ps tf = 2.2 x Rn (CL + CFET) = 2.2 x 303 (80 + 47.21) = 108.212 ps 7.7 Given Data: VDD = 5 V VTP = -0.7 V VTn = 0.6 V βn = 2βp From Equation 7.95, Mid-point voltage of NAND2 gate is  2β p β    VDD − / VTP / + VTn x 1 x n   5 − 0.7 + 0.6 x 1 x N βp   2 βp  VM =  = β 2β p 1 1    1+ x n 1+ x     N βp 2 βp   

    = 2.523V   

VM = 2.523 V 7.8 Given Data: VDD = 3.3 V VTP = -0.8 V VTn = 0.65 V βp = 2.2βn From Equation 7.98, Mid-point voltage of NOR2 gate is 12

- 13     VDD − / VTP / + VTn xNx β n   3.3 − 0.8 + 0.65 x 2 x β n βp    2.2 β n VM =  = β βn    1 + Nx n 1 + 2x    βp 2.2 β n   

    = 1.438V   

VM = 1.438 V VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

7.9 Given Data: VDD = 5 V (W/L)n = 4 Kn’ = 120 µA/V2 VTn = 0.55 V VM = 2.4 V VTp = -0.9 V To find β p W  4 β n = k n '   = 120 x  = 480 µA / V 2  L n  1 n From Equation 7.95, Mid-point voltage of NAND3 gate is     VDD − / VTP / + VTn x 1 x β n   5 − 0.9 + 0.55 x 1 x 480 N βp   3 βp  VM =  = βn 1 480 1    1+ x 1 + x    3 βp N βp   

    = 2.4V   

Solving, β p = 60 µA/V2 7.10 Given Data: Cout = 130 fF C1 = 36 fF C2 = 36 fF βn = 2 mA/V2 VDD = 3.3 V VTn = 0.7 V From Equation 7.28     1 1  =   = 192Ω Rn =  −3  β n (VDD − VTn )   2 x10 x( 3.3 − 0.7 ) 

13

- 14 a) Applying the Elmore formula as illustrated in page 268 of Uyemura, we get the discharge circuit and the discharge time constant for fig.P7.1, Rn

Vout

Cout Rn

C2

Rn

τ n = C out ( Rn + Rn + Rn ) + C 2 ( Rn + Rn ) + C1 ( Rn ) τ n = 130( 3 x192 n ) + 36( 2 x192 n ) + 36(192 ) = 95.216 ps

0

C1

0

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, B’lore = 130 x3 x192 = 74.88 ps

0

0

b) τ n = C out ( Rn + Rn + Rn ) τ ( a ) − τ n ( b) % error = n x100% = 27.16% τ n (a)

Rn

Vout

Cout Rn

0 Rn

0

14

- 15 7.11 The logical circuit for the Boolean expression, f = a.b + c.d .e is given by

M2

a

M2

b

V1 3.3Vdc

0

M2

M2

d

M2

e

f M1

M1

a

c 0

M1

d

M1

0

M1

b

e

0

0 0 0

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore 7.12 The logical circuit for the Boolean expression, f = X ( Y + Z ) + XW is given by

15

- 16 -

M2

Y M2

X

M2

Z

M2

X

V1 3.3Vdc

0

M2

W

MbreakP

MbreakP

f X

M1

X

M1

0

Y

M1

Z

0

M1

W

0

0

M1

0

0

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Designing High-Speed CMOS Logic Networks 8.1 Expression for switching equations of Symmetrical Designs

16

- 17 a) Inverter t r = t ro + α p C L t f = t fo + α n u C L If β n = β p , then tr = tf = ts t s = t o + αC L Wn = Wmin and Wp = r Wmin, Cin = Cu(1 + r) = Cinv If the inverter is scaled by m, the rise/fall times becomes, α t s = to + CL m b) NAND/NOR gates If nFETs and pFETS are scaled equally in multi-input NAND/NOR gates, the rise and fall times will be unequal for gates with N > 1. Equalization of the switching times can be achieved only if the two FET types are of different sizes. If the size of the parallel connected FETs are increased by m, then the size of the series-connected transistors must be increased by a factor mN to obtain a symmetrical design.

Fig.14 Delay times as a function of fan-in N If N = 1, the multi-input becomes an inverter and delay time is given by t d = (A + Bn)τ min where A & B - dimensionless constants τ min = Rmin C min C n= L C min As the number of inputs are increased i.e. fan-in is increased by making N = 2, as in NAND2/NOR2 gates, worst-case delay time has a large zero-load value and a steeper slope. The same comment holds as we increase N. VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore An empirical fit may be obtained by including a factor x1 in the formula as follows. 17

- 18 t d , N = ( x1 )

N −1

(A + Bn)τ min

For Example, if the increase from N = 1 to N = 2 is 17% per input, this means that, x1 = 1.17 and N −1 t d , N = (1.17 ) (A + Bn)τ min If the FETs are scaled by a factor m = 1, 2, . . .. , then the delay time expression modifies to B N −1 t m d , N = ( x1 ) (A + n)τ min m For a complex N-input logic gate, the charging and discharging times will increase further by 5 to 20% and we can account that by including one more empirical fitting parameter x2 >1, to obtain B N −1 t m d , N = x 2 ( x1 ) (A + n)τ min m Applying these formulae to the logic chain of Fig.15, the 3 switching equations becomes

0 1 in

1

2

C1

1

3

2

C2

2 1

3

C3

C= 4 Cmin 0

Fig.15 An example of a Logic chain t d = t NOT !m =1 +t NAND 2 !m= 2 +t NOR 2 !m =3 t NOT !m =1 = ( A + B 2)t min B   t NAND 2 / m= 2 = x1  A + 3 t min 2   B   t NOR 2 / m =3 = x1  A + 4 t min 2   Rearranging, we get td  7   = ( x1 + 1) A +   x1 + 2 B t min  2   VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

18

- 19 td

if x1=1.17,

t min

= 2.17 A + 6.1B

is the delay compared to a single inverter. It may be noted from equation 8.32 that, td = A+ B the delay of a single inverter is t min In general, the design of high speed logic CMOS logic networks is done by using different algorithms and different types of logic cascade. This provides a basis for deciding on the design that will be the fastest. Driving Large Capacitive loads As the analysis of inverter circuits is the basis for high-speed design and as the analysis can be extended to other logic gates, an inverter circuit has been considered here. VCC

M1

Load

MbreakP Vin

Vout M2

CL

MbreakN

0

Fig.16 CMOS Inverter Circuit Fig.16 shows the inverter circuit. βn = βp =β (Assumed symmetric circuit) W  W  ∴   = r   L p  L n where r is the ratios of mobility given by  µ   k ' r =  n  =  n  >1  µ   k '  p  p  Rn = R p = R =

1

β (V DD − VT ) This design yields a voltage transfer characteristic (VTC) with a midpoint voltage of VM=VDD/2 and equal rise and fall times. For a 0-to-1 transition at the output, the output voltage across CL is of the form, Vout (t ) = V DD 1 − e −t / τ VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

[

]

19

- 20 while a 1-to-0 change is described by Vout (t ) = V DD e − t / τ where τ is the time constant given by

τ = RC out = R ( C FET + C L ) The rise/fall time equation becomes ts = tr = tf =to+αCL where to is the delay time with zero-load. to is invariant to changes in the circuit and α ∝ R. R is dependent on β, the transient response requirements can b e met by adjusting β. β can be adjusted during the device design and before sending to fab. Unit load: The load is said to be of unit value, if the gate’s load capacitance is the same as the gate’s own input capacitance. This situation exists, if the inverter of fig.16 is driving the symmetrical inverter as shown in fig.17. Cin = CGn + CGp = Cox(AGn+AGp) = CoxL(Wn + Wp) = (1 +r)(CoxLWn) = (1 + r) CGn Where AGn and AGp are the gate areas of the respective devices. VCC

VCC

Cin M1 MbreakP

M1 MbreakP

Vin

Vout M2 MbreakN

M2 MbreakN

Fig.17 Circuit to illustrate the concept of Unit Load As CL Cin ts W R . But . To keep ts small, α can be decreased. But as α increasing the value of β compensates for the larger load and demonstrates the speedversus-area trade-off. If the aspect ratio is increased by scaling, β increases. i.e. β’ = S β, R’ = R/S and α’ = α/S, C’in = SCin and W’n = SWn Then the switching time equation becomes, ts = tr = tf =to+(α/S)CL VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

20

- 21 -

If CL = SCin as in Fig.18, then the switching time is the same as for a unit load. Thus the compensation factor (1/S) allows us to drive larger CL. VCC

VCC

CL,d=Cin

M1

M1

MbreakP

Cin,d

MbreakP

Beeta large

Vin

M2

M2

MbreakN

CL large

MbreakN

Beeta large

Driving Stage Fig.18 Inverter Driving a Large Input Capacitance gate Delay minimization in inverter cascade:

Ci

1

2

1

2

β1

β2

1

2

β3

1

2

βN-1

βN

3

1

2 CL

0 Fig.19 A chain of inverters to illustrate the steps to minimize the delay Fig.19 shows the large capacitance CL driven by a large inverter gate (N), which is driven by a smaller gate (N-1) and so on. The first stage (β1) is a standard size inverter of unit size. The stages are monotonically increasing such β1 is the smallest and βN is the largest. The sizes of FETs are increased stage by stage by scaling with a factor of S, such that

21

- 22 -

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore β1 < β2 < β3 <……< βN-1 < βN , β2 = S β1, β3 = S β2 and son. The general expression is βj+1 = S βj, which relates the j-th and (j+1)-st stages and this also can be written as follows: β2 = S β1, β3 = S β2 = S2β1, β4 = S β3 = S2β2 = S3β1 and in general, βj = S(j-1)β1, As Cin ∝ β, Cj = S(j-1)C1 Further, As R ∝ (1/βj), j-th stage Resistance, Rj = R1/ S(j-1) As t d = ∑ t i , the total delay is given by td = td1 + td2 + td3 + ….. + td(N-1) + tdN td = 2.2 τ d , the time constants of each inverter is given by τ j = R j C j +1 for j = 1to N td = 2.2 (R1C2 + R2C3 + R3C4 +……. + RN-1CN + RNCL ) Applying equations 8.65 and 8.66, we get,  R1  2  R1  3 R1C2 = R1SC1, R 2 C 3 =  S C1 , R 3 C 4 =  2 S C1 ,..........  S  S  R1  2 R R S C 1 +  R21 S3 C1 + ……….+  N1-2 S N -1C1 +  N1-1 S N C1 td = 2.2(R1SC1 +   S  S  S   S  td = 2.2(R1SC1 + R1SC1 + R1SC1 + …….+ R1SC1 + R1SC1) =2.2 N S R1C1 = 2.2 NS τ r So to minimize the delay, the unit resistance and capacitance has to be kept minimum and also by properly selecting the scaling factor, S. To derive the condition for minimum delay From Equation 8.72, CL = SNC1 C  ln(S N ) = ln L   C1    CL    ln    C1   N =   ln(S)       C  S  t d = 2.2 ln L    . This is only a function of S.  C1   ln ( S ) 

22

- 23 -

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore To minimize the delay time, we apply the derivative condition ∂t d ∂  S  = =0 ∂S ∂S  ln ( S )  Differentiating, 1 S − ln( S ) S [ ln ( S ) ] 2 or ln(S) = 1 or S = e That is the euler e = 2.71… is the scaling factor for a minimum delay. C  ln L  C C  N =  1  = ln L  ln ( S )  C1   CL  τ r The total delay through the chain is τ d = e ln C  1

23

- 24 -

Designing High-Speed CMOS Logic Networks 8.2 Expression for Delay time constant of an inverter by considering parasitic capacitances

j-th Stage

(j+1)-st Stage

Rj (Beeta)j+1 Cj CF,j

Rj

1n

0

(Beeta)j+1

Cj+1 0

0

1n

0

Fig.20 Driver Chain with internal FET capacitance As FETs have to drive both CF,j and Cj+1, the delay time constant now becomes τ j = Rj ( C F, j and Cj + 1) As FET capacitance is proportional to the width of the FET, so that the scaling relation is C F , j = S ( j −1) C F ,1 where CF,j is the capacitance of the first stage The delay time constant for the entire chain is τ d = R1 ( C F,1 + C 2 ) + R2 ( C F, j + C 3 ) + ....... + R N ( C F,N + C L ) Using equations 8.65, 8.69 and 8.88, the above eqn. Becomes τ d = NR1C F ,1 + N ( SR1C1 ) Using eqn.8.75 for N  τ   S   CL τ d =  x  +τ r   ln  ln ( S )   ln ( S )   C1

  where τ x = R1C F ,1 

24

- 25 To get the condition for minimum delay, the above eqn. is differentiated with respect to S, τ S [ ln ( S ) −1] = x which is a transcendental equation and its solution is dependent on the τr τx ratio τr VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

8.3 Logical Effort: Logical Effort characterizes gates and it provides techniques for minimizing the delay by interacting with logic cascades. Its symbol is g, defined by the ratio of the input capacitance to that of the reference gate.

VDD r Cout

Cin = Cref 1

0

Fig.21 Circuit of 1x inverter used to define logical effort C g = in C ref where Cref is the same as the input capacitance of the 1x inverter. Electrical Effort: The symbol of Electrical effort is h and is defined by the ratio of the output capacitance to that of the input gate. It indicates the electrical drive strength that is required to drive its own input capacitance Cin. C h = out C in Delay time: The absolute delay time is given by d abs = kRref ( C p ,ref + C out ) sec With scaling, the resistance decreases by a factor of S and capacitance increases as follows:

25

- 26 -

R=

R ref and C p = SC p ,ref S

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

VDD Rref

Cp,ref Rref

0

Cout

1n

Parasitic internal

0

Fig.22 Circuit used to define the delay time of 1x inverter with parasitic capacitance The delay for the scaled inverter is then, Rref ( SC p,ref + Cout ) d abs = k S Rref  C out  Simplifying, d abs = kRref C p ,ref + k S  C ref

 C ref   Defining the reference time constant, τ = kRref C p ,ref d abs = τ ( h + p )

where h is the electrical effort and p =

τ par τ

=

Rref C p ,ref Rref C ref

the parasitic Capacitance. Normalized delay is given by

is the delay term associated with

d =

d abs

τ

=h+ p

Path Delay. Fig.23 shows 2-stage inverter chain. As with the normal inverters, the total path delay D is just the sum of the individual delays expressed by C C D = d1 + d 2 = ( h1 + p1 ) + ( h2 + p 2 ) , where h1 = 2 and h2 = 3 are the C1 C2 individual electrical effort values.

26

- 27 -

1

2

C1

1

2

C2

C3 C2

0

1n

Fig.23 shows 2-stage inverter chain VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore The path electrical effort is defined as the ratio of H =

C last and this can be expressed as C first

the product H = h1h2 Condition for minimum delay with parasitic capacitance It is derived by differentiating D with respect to h1 and equating it to zero. H  D = ( h1 + p1 ) +  + p 2   h1  H  ∂D ∂  = ( h1 + p1 ) +  + p 2  ∂h1 ∂h1   h1  The parasitic terms p1 and p2 are constants to the differentiation, ∂D H = 1− 2 = 0 ∂h1 h1 using H = h1h2, Thus the condition for minimum delay is h1 = h2 Logical effort for NAND2 and NOR2 gates Fig.24 shows a 1x NAND2 gate. The pFET transistors sizes are still r, since the worst case path from the output to the power supply is the same as an inverter. The nFETs, however, must be twice as large as the inverter values since they are in series. Their relative values are denoted as beiong 2. For either input, VDD

VDD r

2r

r Cout

2r r

2

Cin

Cin

1

1

Cout

2 0

0

0

27

- 28 Fig.24 1x NAND2 gate Fig.25 1x NOR2 gate Fig.22 shows a 1x NOR2 gate. The parallel-connected nFETs have a relative size of 1 while the pFETs are cjhoosen to have sizes of 2r to make Rp the same as Rref. The input capacitance is then C in = C Gn (2 + r ) , so that the logical effort for the NAND2 gate is C ( 2 + r) 2 + r g NAND2 = Gn = C ref 1+ r The input capacitance is then C in = C Gn (1 + 2r ) , so that the logical effort for the NOR2 gate is VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore C Gn (!+2r ) !+2r = C ref 1+ r Logical effort for n-input NAND and NOR gate The input capacitance is then C in = C Gn (n + r ) , so that the logical effort for the NAND2 gate is C ( 2 + r) n + r g NAND2 = Gn = C ref 1+ r The input capacitance is then g NOR2 =

C in = C Gn (1 + nr ) , so that the logical effort for the NOR2 gate is C (!+ nr ) !+ nr g NOR2 = Gn = C ref 1+ r Delay through a general gate

d i =g i hi +p i

for i = 1 to N, The total path delay is the sum N

N

i =1

i =1

D = ∑ d i = ∑ ( g i hi + pi ) The path logical effort is just the product of the individual factors N

G = ∏ g i =g1 g 2 ..g N i =1

The path electrical effort is just the product of the individual factors N

H = ∏ hi =h1 h2 ..hN i =1

Combining logical effort and electrical effort gives the path effort F = GH = ( g1 h1 )( g 2 h2 )( g 3 h3 )....( g N hN ) A minimum delay through the cascade is achieved if

gh =

^

f

for every i

28

- 29 This is consistent with our conclusions for the simple 2-stage inverter chain. The optimum path effort is thus F = f ^

^ N

so that the fastest design is where each stage has

1 N

gh = f = F This is the main equation of logical effort. The comparison of an Nstage logic chain allows us to find the value of F. Each staged can be sized to accommodate the optimum electrical effort value ^

N

1 f , The optimized path delay is then D = NF N + P where P = ∑ Pi . It is hi = i =1 gi the sum of the parasitic delays.

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore In general, Pref for an inverter is the smallest, with multiple-input gates exhibiting larger parasitic delay times. One simple estimate is to write P = nPref . It is the parasitic delay for an n-input gate. 8.3.3

Optimizing the number of stages: To decrease the total delay time in the logic chain, inverters are often introduced in between the stages. This is because of the fact that, logical effort of an inverter is ginv = 1 and as the product of g’s in the logical chain remains unaffected, as G= g1g2…gN remains same. Numerical value of the path effort, F = GH also does not change. ^

1

1

Delay time minimization is f = F N = ( GH ) N 1

Total path Delay is D = NF N + P As D decreases with increasing N, the inclusion of inverters is a useful technique. 8.3.4 Logical area: Logical area of a CMOS logic gate is defined by LAi = Wi xL Where L is the channel length and W is determined by sizing. The logical area of 1x inverter (NOT) is LANOT = 1 + r The logical area of scaled inverter (NOT) is LANOT = S (1 + r ) The logical area of NAND2 gate is LANAND 2 = S ( 2 + r ) The logical area of NOR2 gate is LANOR 2 = S (1 + 2r ) M

For a network with logical M gates , the logical area is LA = ∑ LAi i =1

It is important to note that, the above areas does not include the areas occupied by drain, source, well, interconnect wiring etc. 8.3.5

Branching: When the logic gate drives two or more gates, the data path splits. The capacitance contributed by the off path should also be considered in to account. Fig.21

29

- 30 -

2

(Node)2

1

In

1

3

Out

3 1

22 1 3

(Node)1

1

2

2

2 1 3

Fig.26 Illustration of the effect of branching on the total delay VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore The effect of branching is taken in to consideration by introducing the branching effort at CT b at every branching point. It is given by, b = where Cpath is the capacitance in the C path main logic path and CT = Cpath + Coff. Coff is the cpapcitance that are off the main path. b > 1 and accounts for the additional loading. The path branching effort is, B = ∏ bi i

where bi are the individual branching efforts. The branching effort at node1 of Fig.26is C + C NOR 2 ( 2 + r ) + (1 + 2r ) 3(1 + r ) b1 = NAND 2 = = (2 + r) (2 + r) C NAND 2 The branching effort at node2 of Fig.26is C + C NOR 2 1(1 + r ) + (1 + 2r ) ( 2 + 3r ) b2 = NOT = = (1 + r ) C NOT 1(1 + r ) The path branching effort for the selected path indicated by arrows is then, 3(1 + r )( 2 + 3r ) 3( 2 + 3r ) B= = ( 2 + r )(1 + r ) (2 + r) Once the branching effort has been calculated, the path effort gets modified to F=GHB and the remaining calculations proceeds in the same manner as without branching. 8.4

BiCMOS Drivers: BiCMOS is a modified CMOS technology that includes bipolar junction transistors as circuit elements. In digital design, BiCMOS stages are used to drive highcapacitance lines more efficiently than MOSFET only circuits. BiCMOS Circuits employ CMOS logic circuits that are connected a bipolar output driver stage, as shown in fig.22. The CMOS network provides logic operations and bipolar transistors are used to drive the output. Only one BJT is active at a time. BJT Q1 provides the high output voltage while Q1 discharges the output capacitance and gives the low output value.

30

- 31 -

VDD CMOS

Q1

inputs

logic and driving

Cout Q2

circuits

0

0

0

Fig.27 General form of a BiCMOS circuit VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore The inverting circuit shown in Fig.28 illustrates the operational details. The inversion is done by FETs Mp and Mn. The other two FETs M1 and M2 are used to provide paths to remove charge from the base terminals of Q1and Q2 respectively. This speeds up the switching of the circuit, enhancing its use as an output driver. VDD

Mp

Q1 M1 Vin

0

Mn

Vout

Cout Q2 0

0

M2 0

Fig.28 operational details of the BiCMOS driver circuit A BICMOS NAND2 circuit: The CMOS circuitry can be modified as shown in fig.23. The logic is performed by the parallel pFETs driving Q1, and the series nFETs between the collector and the base of Q2. The other FETs are used as pull-down devices to turn off the output transistors. Other logic functions cazn be designed using this as a basis. In general, the upper output transistor uses a standard-design CMOS circuit as a driver. The nFET section is replicated and placed in between the collector and base of the lower output transistor; adding a pull-down nFET to the base completes the design.

31

- 32 -

VDD Q1

Vout

Cout 0

B

0

A

Q2 0 0

Fig.29 A BICMOS NAND2 circuit: As additional devices are present, parasitic capacitance is larger in a BiCMOS circuit than CMOS. BiCMOS is only effective for larger values of CL. A typical plot of time delay V/S CL of fig.30 shows that, due to the higher parasitic device capacitance, the CMOS and BiCMOS behaviors cross at a value CL=Cx. For CL < Cx, a standard CMOS VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Design provides faster switching than a BiCMOS circuit. The speed increase is only for loads where CL is much larger than Cx. This restricts the application of BiCMOS circuits to applications such as driving long data buses. Moreover, the cost and problem of VBE drops are important factors in using the technology in digital VLSI. td CMOS

BiCMOS

Cx

CL

Fig.30 The Gate delay V/S external load capacitance

32

- 33 -

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

8.1

Solutions to problems in Design of High speed CMOS Logic circuits 8th chapter of John P.Uyemura: Given Data: CL = 100 fF tro =123.75 ps CL = 115 fF tro =138.60 ps β n = β p, VTn = VTp

a) For a symmetric inverter,     1 1  =   = 108Ω Rn =   β n (VDD − VTn )   2.1( 5 − 0.6 )      1 1 =  = 129Ω Rp =   β (V − / V / )   1.8( 5 − / 0.7 / )  Tp  p DD  The formula for rise time tr = tro + αp CL for Cl = 100 fF, 123.75 = tro + αp x 100 (1) for Cl = 115 fF, 138.6 = tro + αp x 115 (2) subtracting (2) from (1) 14.85 = 15αp

∴α p = 990

From Eqn. 7.71, As αp = 2.2 Rp Rn = Rp = 990/2.2 = 450 Ω 33

- 34 Multiplying Eqn (1) by 100 and eqn (2) by 115 and by solving we get, tro = 24.75 ps From Eqn. 7.70, As tr0 = 2.2 Rp CFET , ∴CFET = 24.75/2.2 x 450 = 25 fF b) The general Expression for rise/fall time is t s = t r = t f = t o + α CL Substituting the calculated values, ts = tr = 24.75 ps + 990 x CL c) As the width of transistors are increased by scaling the size by 3.2 times, the switching time equations for the new inverter becomes ts = tr = tf = to + (α/S) CL with α = 990, ts = tr = tf = to + 309.375 CL with CL = 50 fF, ts = tr = tf = to + (α/S) CL = 24.75 + 309.375 x 50 = 40.218 ps with CL = 140 fF, ts = tr = tf = to + (α/S) CL = 24.75 + 309.375 x 140 = 68.062 ps [NOTE: to does not change, as the product Rp x CFET remains same]. VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore 8.2 a) The calculated values of tr and tf for different values of CL are CL 0 50 100 150 200

tr 430 614 798 982 1166

tf 300 428 556 684 812

The graph of tr V/S CL and tf V/S CL are as shown.

34

- 35 -

Rise Time

Rise Time V/S Load Capacitance 1500 1000 500 0 1

2

3

4

5

Load Capacitance

Fall Time

Fall Time V/S Load Capacitance 1000 500 0 1

2

3

4

5

Load Capacitance

b) 1

1 0

1 0

1

2 1 CL

2 1

2

CL

CL

0 0 0 Fig.31 Circuit of problem 8.2 VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Three-inverter cascade is built using identical inverters. If the input to first stage of inverter is assumed to rise from low to high, the output of first stage falls from high to low. So, the switching equation of tf applies. As shown in fig.16, the switching equation of tr and tf applies to the second and third stage outputs. tNOT/m=1 = tfo + αnu 2CL tNOT/m=2 = tro + αpu 3CL tNOT/m=3 = tfo + αnu 4CL The total time delay is the sum of all the above individual gate delays. td = 2tf0 + tr0 + αnu 6CL + αpu 3CL From the given equations, tf0 = 300, tr0 = 430, αnu = 2.56, αpu = 3.68, CL = 45 fF td = 2 x 300 + 430 + 2.56 x 6 x 45 + 3.68 x 3 x 45 = 265.1 ps 35

- 36 8.3 As the input to first stage of inverter rises from high to low, the output of first stage falls from low to high. So, the switching equation of tr applies. As shown in fig.32, the switching equation of tf, tr and tf applies to the second, third and fourth stage outputs.

m=3 1

A

1

2 2 3

m=1

12

m= 2

31

2

m=1

10 Cmin 1

2

0

m=2 Fig.32 Circuit of problem 8.3 tNOT/m=1 = tr0 + αpu 2Cmin  α pu   2Cmin tNOR2/m=1 = 3tro +  2   tNAND2/m=2 =3tfo +2 αnu 3Cmin tNOT/m=3 = tr0 + αpu 4Cmin The total time delay is the sum of all the above individual gate delays. td = 3tf0 +5tr0 +8α nuCmin + 5α puCmin

8.4

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore Given Data: Cox = 8 fF/µm2 r = 2.6 L = 0.4 µm VTn = /VTp/ Wn = 2.2 µm CL = 35 fF a) For Idealized Scaling, the expression for input Capacitance as given by equation 8.51 is Cin = (1 + r) CGn, where CGn = Cox AGn = CoxLWn

36

- 37 ∴Cin = (1 + r)CoxLWn = (1 + 2.6) x 8 x 0.4 x 2.2 = 25.344 fF b) For Idealized scaling, S = e = 2.71 C  ln L  C C = N =  1  = ln L  ln( S )  C1  knowing the value of C1, the number of stages needed in the chain can be found out.  CL   R1C1 c) τ d = NSτ r = e ln  C1  To calculate the delay time in the chain, information about C1 and R1 is needed. 8.5

 CL   40 x10 −12   = ln  = 6.68 ≈ 7 As N = ln −15   50 x10   C1  The number of stages = 7 1

1 C N S =  L  = ( 800 ) 7 = 2.6  C1  The relative sizes are decided by the values of their β values β2 = (2.6)β1 β3 = (2.6)2β1 = 7 β1 β4 = (2.6)3β1 = 17 β1 β5 = (2.6)4β1 = 45 β1 β6 = (2.6)5β1 = 1167 β1 β7 = (2.6)6β1 = 302 β1 where we have rounded to the nearest integer.

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore 8.6

8.7

CL = 0.86 pF/cm, Cin = 52 fF βn = βp r = 2.8 It is to design a driver chain such that, the output is a non-inverting one. Equation 8.93 is S [ ln ( S ) −1] =

τx and for τ x = 0.72τ r , the eqn. Become τr

37

- 38 S [ ln ( S ) − 1] = 0.72 . This is a transcendental equation. This has a solution of S = 3.32. The following tabular column lists the values of the value of S for different τx ratios of τr Sl.no. 1 2 3 4 i.e. C2 = 8.8

C = 0.1 CL

τx τr 0.2 0.5 0.72 1 C1

Solution S 2.91 3.18 3.32 3.59

U5A

C3

C

1 2 13

C4

U2A U3A

12 1

U4A

2 3 2

7410

11 7400

3

2 7405

7402

r = 2.5

CL

Fig.33 Circuit of problem 8.7

Path logical effort as per equn.8.135 is

G = g NAND 3 g NAND 2 g NOR 2 g NOT

Substituting the values of g for all the gates from eqns 8.130, 8.131 & 8.103, we get 3 + r 2 + r 1 + 2r 5.5 4.5 6 G= x x x1 = x x x1 = 3.46 1+ r 1+ r 1+ r 3.5 3.5 3.5 CL CL = = 10 The path electrical effort is H = C1 0.1CL The path effort is F = GH = 3.46 x 10 =34.6 ^

1

1

The optimum stage effort is f = F N = ( 34.6) 4 = 2.43 VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore The total path delay as per eqn. 8.142 is D = 4( 2.43) + P Where P is the parasitic delay. As per eqn. 8.143, P = PNAND 3 PNAND 2 PNOR 2 PNOT and P of each gate is determined by the process specifications. The details about sizing are obtained by optimized quantities. Starting from NAND3 gate, the electrical effort as per eqn.8.141 is

38

- 39 ^

f 2.43 hi = , h1 = = 1.54 gi 1.5714 But as per eqn.8.116, the electrical effort is hi =

C i +1 , i = 1 to N Ci

C2 C2 = , so that, C2 = 0.154CL C1 0.1C L This NAND3 gate can be scaled by using eqn.8.125 as C in = S1C Gn ( 3 + r ) i.e. C1 = S15.5CGn The remaining gates are analyzed in the same manner.

∴ h1 =

^

f 2.43 As gNAND2 = 1.2857, hi = , h2 = = 1.8929 gi 1.2857 C C3 ∴ h2 = 3 = , so that, C3 = 0.291CL C 2 0.154C L This NAND2 gate can be scaled by using eqn.8.125 as C in = S 2 C Gn ( 2 + r ) i.e. C2 = S24.5CGn ^

f 2.43 As gNOR2 = 1.71, hi = , h3 = = 1.421 gi 1.71 C C4 ∴ h3 = 4 = , so that, C4 = 0.413CL C 3 0.291C L This NOR2 gate can be scaled by using eqn.8.127 as C in = S 3 C Gn (1 + 2r ) i.e. C3 = S36CGn ^

f 2.43 As gNOT = 1, hi = , h4 = = 1.421 gi 1.71 C CL ∴ h4 = L = , so that, CL = CL as required C 4 0.413C L This NOT gate can be scaled by using eqn.8.127 as C in = S 4 C ref i.e. C4 = S4Cref

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore We choose reference as the NOT gate with S4 = 1, C4 = CGn. The scaling factor of NOR2 gate is C  C 0.291C L S3 = 3 = = 0.485 L  6C Gn 6C Gn  C Gn  The scaling factor of NAND2 gate is C  C2 0.154C L S2 = = = 0.342 L  4.5C Gn 4.5C Gn  C Gn 

39

- 40 The scaling factor of NAND3 gate is C C1 0.1C L S1 = = = 0.018 L 5.5C Gn 5.5C Gn  C Gn

  

From Eqn.6.115, CGn = Cox(WnL), For the desired value of CL, the scaling factors S1 , S2, S3 and S4 can be determined. With these values, the channel width of the FETs can be determined. [NOTE: The students have been advised to study the example 8.4] 8.10 1 3

2

2

1 3

7400

2 1

10C1

3

C1

1 2 13

12

Fig.34Circuit of problem 8.10 When the logic gate drives two or more gates, the data path splits. The capacitance contributed by the off path should also be considered in to account. Once the branching effort B has been calculated, the path effort gets modified to F=GHB and the remaining calculations proceeds in the same manner as without branching. Path logical effort as per equn.8.135 is

G = g NOR 2 g NAND 2 g NOR 2

Substituting the values of g for all the gates from eqns 8.130, 8.131 & 8.103, we get 1 + 2r 2 + r 1 + 2r 6 4.5 6 G= x x = x x = 1.71x1.29 x1.71 = 3.78 1+ r 1+ r 1+ r 3.5 3.5 3.5 VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore The branching effort as per eqn.8.180is C + C NAND 3 ( 2 + r ) + ( 3 + r ) ( 5 + 2r ) 10 C B = T = NAND 2 = = = = 2.222 ( 2 + r ) 4.5 C path C NAND 2 (2 + r ) CL 10C1 = = 10 The path electrical effort is H = C1 C1 The path effort is F = GHB = 3.78 x 10x2.222 = 84

40

- 41 ^

1

1

The optimum stage effort is f = F N = ( 84 ) 3 = 4.38 The total path delay as per eqn. 8.142 is D = 3(4.38) + P Where P is the parasitic delay. As per eqn. 8.143, gate is determined by the process specifications.

P = PNOR 2 PNAND 2 PNOR 2 and P of each

The details about sizing are obtained by optimized quantities. Starting from input NOR2 gate, the electrical effort as per eqn.8.141 is ^

f 4.38 hi = , h3 = = 2.56 gi 1.71 But as per eqn.8.116, the electrical effort is hi =

C i +1 , i = 1 to N Ci

C4 , so that, C4 = 2.56C3, As C4 = 10C1, C3 = 3.9C1 C3 This NOR2 gate can be scaled by using eqn.8.125 as C in = S 3 C Gn (1 + 2r ) i.e. C3 = S36CGn The remaining gates are analyzed in the same manner.

∴ h3 = 2.56 =

^

f 4.38 As gNAND2 = 1.2857, hi = , h2 = = 3.41 gi 1.2857 C ∴ h2 = 3.431 = 3 , so that, C3 = 3.41C2 , As C3 = 3.9C1, C2 = 1.114C1 C2 This NAND2 gate can be scaled by using eqn.8.125 as C in = S 2 C Gn ( 2 + r ) i.e. C2 = S24.5CGn ^

f 4.38 As gNOR2 = 1.71, hi = , h1 = = 2.56 gi 1.71 C ∴ h1 = 2.56 = 2 , so that, C2 = 2.56C1, As C2 = 1.114C1, as required C1 VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore This NOR2 gate can be scaled by using eqn.8.127 as C in = S1C Gn (1 + 2r ) i.e. C1 = S16CGn The scaling factor of input NOR2 gate is C C 0.1C L S1 = 1 = = 0.0167 L 6C Gn 6C Gn  C Gn The scaling factor of NAND2 gate is

  

41

- 42 C C2 1.114 x0.1C L = = 0.0248 L 4.5C Gn 4.5C Gn  C Gn The scaling factor of output NOR2 gate is C  C 3.9 x0.1C L S3 = 3 = = 0.0709 L  6C Gn 5.5C Gn  C Gn  S2 =

  

From Eqn.6.115, CGn = Cox(WnL), For the desired value of CL, the scaling factors S1 , S2 and S3 can be determined. With these values, the channel width of the FETs can be determined.

VLSI Circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore

42