7 - Serial Io

Microprocessors & Microcomputers (Intel 8085) KL3193

SERIAL I/O BASIC CONCEPTS 1

Iskandar Yahya [email protected] 03-89216591

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INTRODUCTION We've discussed parallel I/O mode (eight bits transferred on eight data lines at the same time).   



Not always practical and sometimes impossible Can be expansive over long distances CRT terminal, cassette players, other analogue peripherals do not support parallel data transfer Need to use serial I/O mode



Serial mode: One bit at time transferred on the same (one) data line at a rate called Baud

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Processes: parallel-to-serial conversion, serial-toparallel conversion, and error checking

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INTRODUCTION Objectives:  





How serial data transfer work and the differences Explain the terms synchronous and asynchronous transmission, simplex, half and full duplex transmission, ASCII code, Baud rate and parity check. Understanding how data bits are transferred and the requirements Write instruction to transmit and receive data using serial lines (SID and SOD)

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SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

This section: Interfacing requirements  Alphanumeric codes  Transmission format  Error checks in data communication  Data communication over telephone lines  Standards in serial I/O  Software vs. programmable hardware approaches 

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SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Interfacing Requirements: 





 

The interfacing requirements for serial I/O is more or less the same as parallel I/O. MPU identifies the device through the port address and use Read and Write control signal to control it accordingly. But instead of using the entire data bus, serial I/O uses only one data line MPU select I/O device through Chip Select Address decoding can either be Peripheral I/O or Memory Mapped I/O 6

SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Alphanumeric Codes 





 

Binary representation of alphabets and numbers as on your keyboard Coding used: ASCII (American Standard Code for Information Interchange) 7-bit code with 128(27) combinations, each combination from 00H to 7FH is assigned to a letter, a decimal number, a symbol or a machine command Refer Appendix E page 735 of Gaonkar book Devices that use ASCII: Printers, teletype machines, keyboards 7

SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Transmission Format Synchronous Vs. Asynchronous Transmission 

Synchronous  Transmitter and receiver are synchronized  A block of characters is transmitted along with the synchronization information Clock

Tx

S ync

Rx

S ync

Data Start

Time

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SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Transmission Format Synchronous Vs. Asynchronous Transmission Asynchronous  Character oriented, one character is sent at a time  Each character carries the Start and Stop information  Framing - A low Start bit followed by eight character bits and ends with two Stop bits Marking

Tx CLK

Start



D0

D1

D2

D3 D4 D5 D6 D7 ASCII Character

Time

Stop Bits

Rx

CLK 9

SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Format

Synchronous

Asynchronous

Data Format Speed

Group of characters

Once character at a time 20 k bits/s or lower

High (20 k bits/s or higher)

Framing Sync characters are Start and Stop bits are Information sent with each group sent with each character Implement Hardware Hardware or Software ation Data Direction

Simplex, Half and Full Duplex

Simplex, Half and Full Duplex 10

SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Simplex and Duplex Transmission 

Simplex transmission - Data transmitted in one direction. E.g. Computer to printer



Duplex transmission - Data flow in both direction. In duplex, there is Half-Duplex where data goes one way at a time and Full Duplex, data goes both ways simultaneously. Communication between 2 computers are full duplex.

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SERIAL I/O

BASIC CONCEPTS OF SERIAL I/O

Rate of Transmission (BAUD)  In parallel I/O, data transfer takes place in three Tcycles  But for Serial I/O, the time a bit stays on or off is determined by the speed at which the speed it transmitted  BAUD is defined as signal change/second.  Transmitter and receiver must work at the same BAUD rate  Take the asynchronous transmission as an example:  Need to transmit 11 bits including the start and stop bits at 1200 baud  So effectively, 1200 bits are sent every 1 second  The delay between two successive bits are 1/1200 = 0.0008 s or 0.83 ms.

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SERIAL I/O

ERROR CHECK IN DATA COMMUNICATION

Parity Check  An ACSII code contains 8-bit character data. The number of 1's can either be an odd number or even number  D7 bit (MSB) is used to flag whether there is an odd or even number of 1's.  In Even parity system:  The total number of 1's must be even, including the D7 bit.  If the code has even number of 1's, D7 remains 0. Otherwise it will become 1.  E.g. Character I is 49H (01001001) with three 1's. So before transmission, D7 will be set to 1 so that there's even number of 1's (i.e. 11001001)

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SERIAL I/O

ERROR CHECK IN DATA COMMUNICATION





For even parity system, if the total number of 1's received at the receiver is an odd number, then it knows that error has occurred, therefore it will ask the transmitter to retransmit the data.

In Odd parity system:  The same principles as the even parity system, but with the number of 1's for every transmission should be odd.

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SERIAL I/O

ERROR CHECK IN DATA COMMUNICATION

Checksum 





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Used when blocks of data are sent - useful for simple synchronous transmission Involves adding all the bytes in a block without carries. The 2's compliment of the sum (negative of the sum) is transmitted as the last byte. The receiver adds all the bytes and the result should be zero if there is no error in the block 15

SERIAL I/O

ERROR CHECK IN DATA COMMUNICATION

Cyclic Redundancy Check (CRC) 

 

  

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Usually used in data transfer from and to a floppy disk - synchronous data communication Based on mathematical relationship of polynomials A stream of data is represented as a polynomial that is divided by a constant polynomial The remainder, unique to that set of bits is generated This remainder is sent out as a check for errors. The receiver use the remainder to detect errors in transmission Complex mathematical algorithm 16

SERIAL I/O

COMMUNICATION USING TELEPHONE LINE

Data Communication over Telephone Lines  Data can be sent over long distances through telephone lines  But, telephone lines are for voice transmission (bandwidth 300 Hz to 3300Hz)  Digital signals requires bandwidth of several megahertz  Data bits need to be converted into audio tones - use Modem  A modem (Modulator/Demodulator) translate between audio tones and digital signals  Two types of modulation techniques are used:  Frequency Shift Keying - FSK (low speed modems)  Phase Shift Keying - PSK (high speed modems)

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SERIAL I/O

STANDARDS IN SERIAL I/O 

 

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A standard may include such items as assignment of pins positions for signals, voltage levels, speed of data transfer etc. Serial I/O, data transmitted as current or voltage 20mA (or 60mA) current loops are used in teletype equipment:  When the signal is 1 (mark), current flow, when signal is 0 (space) current flow is interrupted  Current loop method is noise-free and can be used for long distance Data as voltage:  Standard called RS232C - max 20 kBaud and a distance of 50 ft  Primary focus is to have a compatibility between a terminal and a modem  For higher speed data transmission, use RS422A

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SERIAL I/O

STANDARDS IN SERIAL I/O

Specification

RS-232C

RS-422A

Speed

20 kBaud

10 Mbaud at 40 100 kBaud at ft 30 ft

 

 

100 kBaud at 4000 ft

1 kBaud at 4000 ft

Distance

50 ft

4000 ft

4000 ft

Logic 0

> +3 to +25 V

B > A*

+4 to +6 V

Logic 1

< -3 to -25 B < A V +- 15 V +- 7 V

Receiver Input Voltage

RS-423A

-4 to -6 V +- 12 V

* B and A are differential input to the Op amp. 19

SERIAL I/O

REVIEW OF IMPORTANT CONCEPTS





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Serial data transmission can either be implemented through Hardware (programmable I/O devices) or software Both are conceptually the same. In asynchronous data transmission:  Inform the receiver of the beginning and the end of the transmission and the parity check  Convert a parallel word into a stream of serial bits  Transmit one bit at a time with appropriate time delay, using one data line of an output port. The time delay is determined by the speed of the transmission

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SERIAL I/O

REVIEW OF IMPORTANT CONCEPTS



In data reception, the above steps are reversed:  Recognize the beginning of the transmission  Receive serial bits, one at a time, and convert them into parallel byte  Check for errors and recognize the end of the transmission

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SERIAL I/O

REVIEW OF IMPORTANT CONCEPTS

Software approach:  Speed of transmission is set up by using an appropriate delay between the transmission consecutive bits, set up by the software  The entire word is converted into a serial stream by rotating the byte and outputting one bit at a time, including the framing bits and the parity bits.  Suitable for slow-speed asynchronous data communication where timing requirements are not critical  Simple and inexpensive  Useful in understanding the concepts of serial I/O 22

SERIAL I/O

REVIEW OF IMPORTANT CONCEPTS

Hardware approach:  Use peripherals to (PPD) for data transfer  The device contain parallel-to-serial register and 1bit output port for transmission  For reception, use serial-to-parallel register and 11bit input port  Rate of transmission and reception is determined by the clock  Data framing and adding error checking information can be programmed on a control register  MPU only transfer data in parallel data bus, the programmable device/block does the serial I/O functions  Flexible and reprogrammable  Widely used in industrial and commercial products

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SERIAL I/O

SOFTWARE-CONTROLLED ASYNCHRONOUS SERIAL I/O

The program written must be able to do the following: Output a Start bit  Convert the character to be sent in a stream of serial bits with appropriate delay  Add parity information if necessary  Output one or two Stop bits 

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SERIAL I/O

SOFTWARE-CONTROLLED ASYNCHRONOUS SERIAL I/O

Serial Data Transmission  When no transmission, the transmit line of the output port stays high - Mark position  Transmission begins with Start bit - Active Low  Initialization block includes setting up counter to count eight character bits (D0 - D7) - Start and Stop bits are sent out separately  Program waits for bit time delay - 0.833 ms for 1200 Baud then send one character at a time over data line D0 

Rotates to the next bit - D1 into D0



Repeat sending all 8 bits, and then sends out the two Stop bits If output is a printer, then it waits until it receives the Stop 25 bits before printing Stop bits - To allow time for printer to print or process data ,

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

SERIAL I/O

SOFTWARE-CONTROLLED ASYNCHRONOUS SERIAL I/O

Serial Data Reception  Read input port, if no data received, input line stays high  Stays in the loop and continue to read the port until receives Start bit (active low)  When received Start bit, wait for half the bit time and samples the character bits in the middle of the pulse to avoid error  Initialize counter to count 8 bits and clears the register to save the partial reading  Continue reading the input port every interval of bit time until all 8 bit characters are read  Receives the D bit first 0 

D7 is used as the reception data line

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Transm it

Receiv e

•Set up Character Bit Counter •Send Start Bit

Read Output Port NO

Wait Bit Time

YES

Get Character in Accumulator

NO Return

Wait Bit Time

NO

Is It Last Bit?

(a) Transmission

Return

Wait For Half Bit Time

Output Bit Using D0

•Rotate Next Bit in D0 • Decrement Bit Counter

Is It Start Bit?

•Add Parity if Necessary •Send Two Stop Bits

•Check Parity if Necessary •Wait for Two Stop Bits

Is Bit Still Low

YES

YES •Set up Bit Counter •Clear Register to Save Bits • Wait Bit Time • Read Input Port • Save Bit

Is It Last Bit?

•Get Ready To Receive Next Bit •Decrement Counter

(b) Reception

NO

SERIAL I/O LINES SOD AND SID SERIAL I/O LINES

SOD and SID Lines 

The 8085 has two pins specially designed for software-controlled serial I/O. One is called SOD (Serial Output Data), and the other is called SID (Serial Input Data).



Data transfer is controlled through two instruction: SIM and RIM. These instructions are used for interrupt and serial I/O. We will look at the serial I/O uses.

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SERIAL I/O LINES SOD AND SID SERIAL I/O LINES

Serial Output Data (SOD)  The instruction SIM is necessary to output data serially from the SOD line  Example Instruction : MVI A,80H

;Set D7 in the accumulator = 1

RAR

;Set D6 = 1 and bring Carry into D7 ;Output D7

SIM

In the above set of instructions, the serial output line is enabled by rotating 1 into bit position D6; the instruction SIM outputs the Carry bit through bit position D7

Serial Output Data

D7

D6

SOD

SDE

D5

D4

D3

D2

D1

D0

For Interrupts 1 = Enable SOD 0 = Disable SOD

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SERIAL I/O LINES SOD AND SID SERIAL I/O LINES

Serial Input Data (SID)  The Instruction RIM is used to input serial data through the SID line.  Similar to instruction IN, except that RIM reads only one bit and places it in the accumulator at D7. 



The SID and SOD lines in 8085 eliminate the need to an input port and an output port in the software-controlled serial I/O Essentially, SID is a 1-bit input port and SOD is a 1-bit D7 D6 D5 D4 D3 D2 D1 D0 output port SID

Interrupt Status Serial Input Data

: Read the SID line and place the bit in the accumulator at D7

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SERIAL I/O LINES SOD AND SID SERIAL I/O LINES

Example Illustration: Data Transmission Using the SOD Line   Problem:  Write a subroutine to transmit an ASCII character, stored in register B, using the SOD line as a 1-bit output port   Solution  Subroutine:  The subroutine can follow the flowchart given on slide #  Set the counter for 11 bits and repeat the loop 11 times. The Start and Stop bits are included with the character. For Stop bits, the 2 1's are set up by instruction STC (set carry)  Example in transmitting the ASCII letter G stored in register B:

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SERIAL I/O LINES SOD AND SID SERIAL I/O LINES

*Content of register B: 47H (01000111) SODATA:

MVI C,0BH

;Set the counter C to count eleven bits

 

XRA A

;Reset Carry 0

NXTBIT:

MVI A,80H

;Set D7 = 1 in the accumulator

 

RAR

;Bring Carry in D7 and set D6 = 1 (shift)

 

SIM

;Output D7

 

CALL BITTIME

;Wait for 9.1 ms

 

STC

;Set Carry = 1

 

MOV A,B

;Place ASCII character in the accumulator

 

RAR

;Place ASCII bit D0 into the Carry, Shift 1 in D7,

 

 

; and continue shifting for each loop

 

MOV B,A

; Save current content of accumulator

 

DCR C

;One bit transmitted, decrement counter

 

JNZ NXTBIT

;If all the bits are not transmitted, go back to NXTBIT 32

 

RET

 

Description: letter G

0

1

0

0

0

1

1

1 --> ASCII of

CY D7 D6 D5 D4 D3 D2 D1 D0 (A) XRA MVI A,80H

0 0

1

0

0

0 0

0

0 0

1

0 0

0

0 0

0

0

0

0

0

0

0

RAR

0

SIM

0 ----> sent out (SOD) Start Bit

0

0

0

STC MOV A,B

1

0

1

0

0

0

RAR

1

1

0

1

0

0

MOV B,A

1

1

0

1

0 0

1

1

1

0

1

1

0

0

1

1

0

0

(B)

2nd iteration: MVI A,80H

1

1

0

0 1

0 1

0

RAR

0

0

0

0

0

0

SIM

1 ----> sent out (SOD) bit D0 of ASCII

0

STC MOV A,B

1

1

RAR

1

1

1

0

1

0

0

0

1

MOV B,A

1

1

1

0

1

0

0

0

1 (B)

 

0

1

0

0

0

1

1 33

SERIAL I/O LINES SOD AND SID SERIAL I/O LINES

What about for Data Reception using SID line?  Can use the same principle as the flowchart in slide #  The difference is in the procedure of saving a bit and forming a parallel word.  After the D is read, it is stored in CY using RAL 0  

Problem: Receive an ASCII character from an input port

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SERIAL I/O LINES SOD AND SID SERIAL I/O LINES 

Solution Subroutine:

SIDATA:

RIM

;Read SID line

 

RAL

;Place D7 into CY

 

JC SIDATA

 

CALL HAFBIT

;If D7 = 1, this is not a Start bit, go back and read again ;If D7 = 0, this is Start bit; wait for half bit period

 

MVI C,09H

;Counter for nine bits

NXTBIT:

CALL BITTIME

;Wait for one bit period

 

RIM

;Read SID line

 

RAL

;Save bit in CY

 

DCR C

;One bit is read, decrement counter

 

JZ RETURN

; If all bits are read, return to main program

 

MOV A,B

;Save the bits saved so far in A

 

RAR

;Place the bits saved in CY into position D7 and

 

 

;shift all other bits by one position

 

JMP NXTBIT

;Get the next bit in the next iteration

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SERIAL I/O

HARDWARE CONTROLLED SERIAL I/O 







The hardware approach has the same principle as discussed previously All the software-controlled functions and requirements are combined in one chip. These are:  Input and output ports are required for interfacing  In data transmission, MPU converts parallel data into stream of serial bits  In data reception, the MPU converts serial bits into a parallel word  Data transfer is synchronized between the MPU and slowresponding peripherals through time delays An IC called USART (Universal Synchronous/Asynchronous Receiver/Transmitter) includes all the requirements above in36 one chip Intel 8251A USART is a device widely used in serial I/O.

SERIAL I/O

HARDWARE CONTROLLED SERIAL I/O

8251A Programmable Communication Interface Programmable chip designed for synchronous and asynchronous serial data communication. With this device, all the softwarecontrolled instructions are carried out within the chip and also some other peripheral chips such as logic gates, decoders etc.      

This device includes 5 sections: Read/Write Control Logic Transmitter Receiver Data Bus Buffer Modem Control

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SERIAL I/O

HARDWARE CONTROLLED SERIAL I/O

Read/Write Control Logic:  R/W control logic  Six input signals  Control logic  And three buffer registers; data register, status register and control register Transmitter:  Accepts parallel data from 8085 and converts it to serial data stream  Two registers; a buffer register to hold the 8-bit data and an output register to converts the data into serial stream  MPU writes on the buffer, and if the output register is 38 available, the contents of buffer is transferred to the output register.

SERIAL I/O

HARDWARE CONTROLLED SERIAL I/O

Receiver:  Accepts serial data and converts them into parallel data.  Two registers; the receiver input register and the buffer register  When the input line goes low, it assumes it is a start bit, wait for half a bit and then samples the line again  Accepts the following bits, and loads it into the buffer register  Transfers the parallel byte to the MPU when requested

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SERIAL I/O

HARDWARE CONTROLLED SERIAL I/O

Initializing the 8251A:  MPU must inform 8251A of all details such as mode, baud, Stop bits, parity etc.  A set of control words must be loaded into the 16-bit control register of the 8251A  MPU must check the readiness of the device by reading the status register  Control Words:  Mode words - Specifies the general characteristics of operation (Baud, parity, Stop bits)  Command words - enables data transmission and/or reception 40