18009654 Circuits And Electronics

6.002

CIRCUITS AND

ELECTRONICS

Introduction and Lumped Circuit Abstraction

6.002 Fall 2000

Lecture 1

1

ADMINISTRIVIA

Lecturer: Prof. Anant Agarwal Textbook: Agarwal and Lang (A&L)

Readings are important! Handout no. 3 Assignments —

Homework exercises Labs Quizzes Final exam

6.002 Fall 2000

Lecture 1

2

Two homework assignments can be missed (except HW11). Collaboration policy Homework You may collaborate with others, but do your own write-up. Lab You may work in a team of two, but do you own write-up. Info handout Reading for today —

Chapter 1 of the book

6.002 Fall 2000

Lecture 1

3

What is engineering? Purposeful use of science

What is 6.002 about? Gainful employment of Maxwell’s equations From electrons to digital gates and op-amps

6.002 Fall 2000

Lecture 1

4

Nature as observed in experiments V

3

6

9

12

…

I

0.1

0.2

0.3

0.4

…

6.002

Physics laws or “abstractions” Maxwell’s abstraction for Ohm’s tables of data V=RI Lumped circuit abstraction +– V C L R

M

S

Simple amplifier abstraction Operational amplifier abstraction abstraction

+ -

Filters Analog system components: Modulators, oscillators, RF amps, power supplies 6.061

Digital abstraction Combinational logic

f

Clocked digital abstraction Instruction set abstraction Pentium, MIPS 6.004 Programming languages Java, C++, Matlab 6.001 Software systems 6.033 Operating systems, Browsers

Mice, toasters, sonar, stereos, doom, space shuttle 6.455 6.170 5

6.002 Fall 2000 Lecture 1

Lumped Circuit Abstraction

Consider

The Big Jump from physics to EECS I

+

V

-

?

Suppose we wish to answer this question: What is the current through the bulb?

6.002 Fall 2000

Lecture 1

6

We could do it the Hard Way… Apply Maxwell’s Differential form ∂B Faraday’s ∇× E = − ∂t ∂ρ Continuity ∇ ⋅ J = − ∂t Others

ρ ∇⋅E = ε0

6.002 Fall 2000

Lecture 1

Integral form ∂φ B ∫ E ⋅ dl = − ∂t ∂q ∫ J ⋅ dS = − ∂t q E ⋅ dS = ∫

ε0

7

Instead, there is an Easy Way…

First, let us build some insight: Analogy F

a?

I ask you: What is the acceleration? You quickly ask me: What is the mass? I tell you:

m

F You respond: a = m Done !! !

6.002 Fall 2000

Lecture 1

8

Instead, there is an Easy Way…

First, let us build some insight: Analogy

F a? In doing so, you ignored the object’s shape its temperature its color point of force application Point-mass discretization

6.002 Fall 2000

Lecture 1

9

The Easy Way…

Consider the filament of the light bulb. A B We do not care about

how current flows inside the filament

its temperature, shape, orientation, etc.

Then, we can replace the bulb with a

discrete resistor

for the purpose of calculating the current.

6.002 Fall 2000

Lecture 1

10

The Easy Way…

A B Replace the bulb with a

discrete resistor

for the purpose of calculating the current. A + V –

I R

and

B

V I= R

In EE, we do things the easy way…

R represents the only property of interest! Like with point-mass: replace objects F with their mass m to find a = m

6.002 Fall 2000

Lecture 1

11

The Easy Way…

A + V –

I

R

and

B

I=

V

R

In EE, we do things the easy way…

R represents the only property of interest!

R relates element v and i

V

I= R

called element v-i relationship

6.002 Fall 2000

Lecture 1

12

R is a lumped element abstraction for the bulb.

6.002 Fall 2000

Lecture 1

13

R is a lumped element abstraction for the bulb. Not so fast, though … I A + S A

V B

–

SB

black box Although we will take the easy way using lumped abstractions for the rest of this course, we must make sure (at least the first time) that our abstraction is reasonable. In this case, ensuring that V I are defined for the element 6.002 Fall 2000

Lecture 1

14

A

+

I SA

V

V B

–

I

must be defined for the element

SB

black box

6.002 Fall 2000

Lecture 1

15

I

must be defined. True when

= I out of S B ∂q True only when = 0 in the filament! ∂t I into S A

∫ J ⋅ dS

SA

∫ J ⋅ dS

SB

∂q ∫ J ⋅ dS − ∫ J ⋅ dS = ∂t SA SB

from ell w x a M

IA

IB

∂q =0 I A = I B only if ∂t So let’s assume this

6.002 Fall 2000

Lecture 1

16

V

Must also be defined.

see A&L

So let’s assume this too

∂φ B =0 ∂t outside elements

VAB defined when

So

VAB = ∫AB E ⋅ dl

6.002 Fall 2000

Lecture 1

17

Lumped Matter Discipline (LMD) Or self imposed constraints:

More in Chapter 1 of A & L

∂φ B = 0 outside ∂t ∂q = 0 inside elements ∂t bulb, wire, battery

Lumped circuit abstraction applies when elements adhere to the lumped matter discipline.

6.002 Fall 2000

Lecture 1

18

Demo only for the sorts of questions we as EEs would like to ask!

Demo

6.002 Fall 2000

Lumped element examples whose behavior is completely captured by their V–I relationship.

Exploding resistor demo can’t predict that! Pickle demo can’t predict light, smell

Lecture 1

19

So, what does this buy us?

Replace the differential equations with simple algebra using lumped circuit abstraction (LCA). For example —

V + –

a b

R1 R2

R3

R4

d R5

c

What can we say about voltages in a loop under the lumped matter discipline?

6.002 Fall 2000

Lecture 1

20

What can we say about voltages in a loop under LMD?

a b

V + –

R1

R3

R4

d

R2

R5

c ∂φ B under DMD ∫ E ⋅ dl = − ∂t 0 ∫ E ⋅ dl + ∫ E ⋅ dl + ∫ E ⋅ dl = 0

ca

ab

bc

+ Vca + Vab + Vbc

= 0

Kirchhoff’s Voltage Law (KVL): The sum of the voltages in a loop is 0. 6.002 Fall 2000

Lecture 1

21

What can we say about currents?

Consider

I ca

S a

I da I ba

6.002 Fall 2000

Lecture 1

22

What can we say about currents?

I ca

S a

I da I ba

∂q ∫S J ⋅ dS = − ∂t

under LMD 0

I ca + I da + I ba = 0 Kirchhoff’s Current Law (KCL): The sum of the currents into a node is 0. simply conservation of charge

6.002 Fall 2000

Lecture 1

23

KVL and KCL Summary

KVL:

∑ jν j = 0 loop

KCL:

∑jij = 0 node

6.002 Fall 2000

Lecture 1

24

6.002

CIRCUITS AND

ELECTRONICS

Amplifiers -Small Signal Model

6.002 Fall 2000

Lecture 10

1

Review „

MOSFET amp VS RL

vO vI

„

iDS

Saturation discipline — operate MOSFET only in saturation region

„Large signal analysis 1. Find vO vs vI under saturation discipline.

2. Valid vI , vO ranges under saturation discipline.

Reading: Small signal model -- Chapter 8

6.002 Fall 2000

Lecture 10

2

Large Signal Review 1

vO vs vI K (vI −1)2 RL

2

valid for vI ≥ VT and vO ≥ vI – VT K 2 (same as iDS ≤ vO ) 2

vO = VS −

6.002 Fall 2000

Lecture 10

3

Large Signal Review

2

Valid operating ranges

V S

v O

5V

corresponding interesting region for vO

vO > vI −VT

vO = vI −VT vO < vI −VT

1V

vI

VT

1V

2V

“interesting” region for vI . Saturation discipline satisfied.

6.002 Fall 2000

Lecture 10

4

But… VS 5V

vO

vO = vI −VT

vO 1V

vI VT

1V

Demo

vI

2V

Amplifies alright, but distorts

vI

vO

t

Amp is nonlinear … / 6.002 Fall 2000

Lecture 10

5

Small Signal Model vO

~ 5V VS

Focus on this line segment

(VI , VO )

~ 1V vI

VT 1V

~ 2V 2 K (vI − VT ) vO = VS − RL 2 Amp all right, but nonlinear! Hmmm … So what about our linear amplifier ???

Insight: But, observe vI vs vO about some point (VI , VO) … looks quite linear ! 6.002 Fall 2000

Lecture 10

6

Trick ∆vO

vo VO

vi

(VI ,VO )

looks linear

VI ∆vI ™

Operate amp at VI , VO Æ DC “bias” (good choice: midpoint of input operating range)

™ Superimpose small signal on top of VI

™ Response to small signal seems to be approximately linear

6.002 Fall 2000

Lecture 10

7

Trick ∆vO

vo VO

vi

(VI ,VO )

looks linear

VI ∆vI

™

Operate amp at VI , VO Æ DC “bias” (good choice: midpoint of input operating range)

™ Superimpose small signal on top of VI ™ Response to small signal seems to be approximately linear Let’s look at this in more detail — I graphically II mathematically III from a circuit viewpoint 6.002 Fall 2000

Lecture 10

next week 8

I Graphically

We use a DC bias VI to “boost” interesting input signal above VT, and in fact, well above VT .

VS RL

interesting input signal

∆vI + – VI + –

vO

Offset voltage or bias

6.002 Fall 2000

Lecture 10

9

Graphically

VS RL

interesting input signal

vO

∆vI + – VI + –

VS

vO

operating point

VO

0

VI , VO

VT

Good choice for operating point:

midpoint of input operating range

6.002 Fall 2000

vO = vI −VT

vI

Lecture 10

VI

10

Small Signal Model

aka incremental model aka linearized model

Notation — Input:

vI = VI + vi

total DC small variable bias signal (like ∆vI) bias voltage aka operating point voltage Output: vO = VO + vo Graphically, vI

vO

vi

vo

VI

VO

0

6.002 Fall 2000

t

0

Lecture 10

t

11

II Mathematically

(… watch my fingers)

RL K 2 vO = VS − (vI −VT ) VO = VS − RL K (VI −VT )2

2

2 “

substituting vI = VI + vi vi << VI

RL K vO = VS − 2

( [VI + vi ] − vT )2

RL K 2

( [VI −VT ] + vi )2

= VS −

(

RL K [VI −VT ]2 + 2 [VI − vT ]vi + vi 2 = VS − 2

RL K VO + vo = VS − (VI − VT )2 − RL K (VI −VT ) vi

2 From “,

)

vo = −RL K (VI −VT ) vi

gm

6.002 Fall 2000

related to

Lecture 10

VI

12

Mathematically vo = −RL K (VI −VT ) vi

gm

related to

VI

vo = −g m RL vi

For a given DC operating point voltage VI,

VI – VT is constant. So,

vo = − A vi

constant w.r.t. vi

In other words, our circuit behaves like a linear amplifier for small signals

6.002 Fall 2000

Lecture 10

13

Another way RL K vO = VS − (vI −VT )2

2

(

)

R K 

 2 L v −V VS −  I T 2 d   vo = dv I

⋅ vi

v = V

I I

slope at VI

vo = −RL K (VI −VT ) ⋅ vi

g m = K (VI −VT ) A = −g m RL

amp gain

Also, see Figure 8.9 in the course notes for a graphical interpretation of this result 6.002 Fall 2000

Lecture 10

14

More next lecture … Demo

iDS load line

input signal response operating point VI

VO

vO

How to choose the bias point: 1. Gain component g m ∝ VI 2. vi gets big Æ distortion. So bias carefully 3. Input valid operating range. Bias at midpoint of input operating range for maximum swing. 6.002 Fall 2000

Lecture 10

15

6.002

CIRCUITS AND ELECTRONICS

Small Signal Circuits

6.002 Fall 2000

Lecture 11

1

Review: „

Small signal notation vA = VA + va total operating point

„

small signal

vOUT = f (vI ) d f (vI ) ⋅ vi vout = dv I v I =VI VS

„

vI = VI + vi vi VI

RL

vO = VO + vo

+ – + –

6.002 Fall 2000

Lecture 11

2

Review: I Graphical view (using transfer function)

vO behaves linear for small perturbations

vI

6.002 Fall 2000

Lecture 11

3

Review: II Mathematical view

K (vI − VT ) vO = VS − RL 2 2

V − K (v − V )2 R  T L d  S 2 I  vo = dv I

⋅ vi v I =VI

vo = − K (VI − VT ) RL ⋅ vi gm

6.002 Fall 2000

related to VI constant for fixed DC bias

Lecture 11

4

How to choose the bias point, using yet another graphical view based on the load line i DS

i DS <

Demo

K 2 vO 2

V S vO i = load line DS R − R L L

input signal response VI

VO

− 1 + 1 + 2 KR LV S v I = VT + KR L

vO v I = VT

Choosing a bias point: 1. Gain

g m RL ∝ VI

2. Input valid operating range for amp. 3. Bias to select gain and input swing. 6.002 Fall 2000

Lecture 11

5

III The Small Signal Circuit View We can derive small circuit equivalent models for our devices, and thereby conduct small signal analysis directly on circuits e.g. large signal circuit model for amp

vI + –

R

VS

vOUT K 2 iD = (vI − VT ) 2

+ – 1

We can replace large signal models with small signal circuit models. Foundations: Section 8.2.1 and also in the last slide in this lecture.

6.002 Fall 2000

Lecture 11

6

Small Signal Circuit Analysis 1

Find operating point using DC bias inputs using large signal model.

2

Develop small signal (linearized) models for elements.

3

Replace original elements with small signal models.

Analyze resulting linearized circuit… Key: Can use superposition and other linear circuit tools with linearized circuit!

6.002 Fall 2000

Lecture 11

7

Small Signal Models A

MOSFET

large signal

vGS

Small signal?

6.002 Fall 2000

D iDS =

K (vGS − VT )2 2

S

Lecture 11

8

Small Signal Models A

MOSFET

large signal

D

vGS

iDS =

Small signal: K 2 iDS = (vGS − VT ) 2

∂ ids = ∂vGS

K (vGS − VT )2 2

S

 K (v − V )2  ⋅ v gs T  2 GS  vGS =VGS

ids = K (VGS − VT ) ⋅ v gs

ids is linear in vgs !

gm small signal

v gs

D ids = K (VGS − VT ) v gs S

6.002 Fall 2000

ids = g m v gs

Lecture 11

9

B

DC Supply VS

large signal

iS + vS = VS –

Small signal

∂VS vs = ∂iS is + vs –

6.002 Fall 2000

vS = VS

⋅ is iS = I S

vs = 0 DC source behaves as short to small signals.

Lecture 11

10

C

Similarly, R

large signal

iR + vR R –

v R = R iR

vr =

∂ ( RiR ) ⋅ ir ∂iR iR = I R

vr = R ⋅ ir

small signal

6.002 Fall 2000

ir + vr R –

Lecture 11

11

Amplifier example: Large signal RL vO

+ v – I

iDS

Small signal

+ vi –

iDS

K 2 = (vI − VT ) 2

vO = VS −

RL vo

+ V – S

ids

ids = K (VI − VT ) ⋅ vi

K (vI − VT )2 RL 2

ids RL + vo = 0 vo = −ids RL vo = − K (VI − VT )RL ⋅ vi = − g m RL ⋅ vi

Notice, first we need to find operating point voltages/currents. Get these from a large signal analysis. 6.002 Fall 2000

Lecture 11

12

III The Small Signal Circuit View

To find the relationship between the small signal parameters of a circuit, we can replace large signal device models with corresponding small signal device models, and then analyze the resulting small signal circuit.

Foundations: (Also see section 8.2.1 of A&L) KVL, KCL applied to some circuit C yields:

" + v A + " + vOUT + " + vB + "

1

Replace total variables with operating point variables plus small signal variables

" + VA + v a " + VOUT + vout + VB + vb + " Operating point variables themselves satisfy the same KVL, KCL equations

" + VA

" + VOUT

+ VB

+"

so, we can cancel them out Leaving

"

+ va "

+ vout

+ vb + "

2

But 2 is the same equation as 1 with small signal variables replacing total variables, so 2 must reflect same topology as in C, except that small signal models are used. Since small signal models are linear, our linear tools will now apply…

6.002 Fall 2000

Lecture 11

13

6.002

CIRCUITS AND ELECTRONICS

Capacitors and First-Order Systems

6.002 Fall 2000

Lecture 12

1

Motivation Demo

5V

5V

B

C

A

5V 0V

5 A 0 5

Expect this, right? But observe this!

B 0 5

Expected Observed

C 0 Delay! 6.002 Fall 2000

Lecture 12

Reading: Chapters 9 & 10 2

The Capacitor D n-channel MOSFET symbol

G S drain gate

m+ e+ t + a+ l + +

n

o x i d e

source

s i l n-channel p i MOSFET n-channel c o n n D G CGS

6.002 Fall 2000

S

Lecture 12

3

Ideal Linear Capacitor + + A ++++ -----

E

d EA d obeys DMD! total charge on capacitor = +q − q = 0 C=

i C

q

+ v –

q = C v coulombs farads volts

6.002 Fall 2000

Lecture 12

4

Ideal Linear Capacitor i q

C

q = C v

+ v –

dq i= dt d (Cv ) = dt dv =C dt  E = 1 Cv 2    2

A capacitor is an energy storage device Æ memory device Æ history matters! 6.002 Fall 2000

Lecture 12

5

Analyzing an RC circuit Thévenin Equivalent:

vI (t ) + –

R

C

+ vC (t ) –

Apply node method: vC − vI dvC +C =0 R dt dvC RC + vC = vI dt

t ≥ t0

vC (t0 ) given

units of time 6.002 Fall 2000

Lecture 12

6

Let’s do an example: +

v I (t )

R

+ –

C

vC (t ) –

vI (t ) = VI

vC (0 ) = V0 given

dvC RC + vC = VI dt

6.002 Fall 2000

Lecture 12

X

7

Example… vI (t ) = VI

vC (0 ) = V0 given dvC RC + vC = VI dt

X

vC (t ) = vCH (t ) + vCP (t ) total homogeneous

particular

Method of homogeneous and particular solutions: 1

Find the particular solution.

2 Find the homogeneous solution. 3 The total solution is the sum of the particular and homogeneous solutions. Use the initial conditions to solve for the remaining constants. 6.002 Fall 2000

Lecture 12

8

1 Particular solution

dvCP + vCP = VI dt

RC

vCP = VI RC

works

dVI + VI = VI dt

0 In general, use trial and error.

vCP : any solution that satisfies the original equation X

6.002 Fall 2000

Lecture 12

9

2 Homogeneous solution

dvCH RC + vCH = 0 dt

Y

vCH : solution to the homogeneous equation Y (set drive to zero) vCH = A e st

assume solution of this form. A,

s?

dA e st RC + A e st = 0 dt R CA s e st + A e st = 0

Discard trivial A = 0 solution, Characteristic equation

R C s +1 = 0 s= − or

1 RC

vCH = Ae

6.002 Fall 2000

−t RC

RC called time constant

Lecture 12

τ

10

3 Total solution

vC = vCP + vCH vC = VI + A e

−t RC

Find remaining unknown from initial conditions: at t = 0

Given,

vC = V0

so,

V0 = VI + A

or

A = V0 − VI

thus

vC = VI + (V0 − VI ) e

also

6.002 Fall 2000

iC = C

−t RC

dvC (V − VI ) =− 0 e R dt

Lecture 12

−t RC

11

vC = VI + (V0 − VI ) e

−t RC

vC VI

V0 0

t

RC

6.002 Fall 2000

Lecture 12

12

Examples vC

vC

5V

5V

5 + 5e

−t RC

5e

t

0V VO = 0V VI = 5V

5 0

−t RC

t

0V VO = 5V VI = 0V

5 0

τ = RC

Remember B demo

6.002 Fall 2000

Lecture 12

13

6.002

CIRCUITS AND ELECTRONICS

Digital Circuit

6.002 Fall 2000

Lecture

13

1

Review vI

R

vI + –

VI

+ vC –

C

t

0

vC (0 ) = VO vC = VI + (VO − VI ) e

−t RC

1

vC VI

VO RC

6.002 Fall 2000

time constant RC t

Lecture

13

2

Let’s apply the result to an inverter. B

A X

First, rising delay tr at B

VS

VS

A vA 5V

0 1 Æ 0 at A

6.002 Fall 2000

B CGS

X t

Lecture

13

3

First, rising delay tr at B VS

A

VS

B vA 5V

CGS

X

0 1 Æ 0 at A

t

vB

5V

ideal observed

t

0

6.002 Fall 2000

Lecture

13

4

First, rising delay tr at B VS

A vA 5V

VS

B CGS

X

0 1 Æ 0 at A

t 5V VOH

rising delay of X

6.002 Fall 2000

Lecture

vB

0

tr

13

t

5

Equivalent circuit for 0Æ1 at B

vI = VS

RL

+ –

vI = VS vB (0 ) = 0

From

CGS

+ vB –

for t ≥ 0

1 vB = VS + (0 − VS ) e

−t RL CGS

Now, we need to find t for which vB = VOH .

6.002 Fall 2000

Lecture

13

6

Or vOH = VS − VS e

Find tr : VS e

−t r RL CGS

−t RL CGS

= VS − VOH

VS − VOH − tr = ln RL CGS VS

VS − VOH t r = − RL CGS ln VS

6.002 Fall 2000

Lecture

13

7

Or vOH = VS − VS e

Find tr : VS e

−t r RL CGS

−t RL CGS

= VS − VOH

VS − VOH − tr = ln RLCGS VS VS − VOH t r = − RL CGS ln VS e.g.

RL = 1K

VS = 5V

CGS = 0.1 pF

VOH = 4V

t r = −1 × 10 × 0.1 × 10 3

= 0.16 ns

−12

5−4 ln 5

RC = 0.1 ns ! 6.002 Fall 2000

Lecture

13

8

Falling Delay tf Falling delay tf is the t for which vB falls to VOL

Equivalent circuit for 1 Æ 0 at B vB (0 ) = VS (5V )

RL

VS + –

CGS

RON

+ vB –

X

6.002 Fall 2000

Lecture

13

9

Falling Delay tf

Equivalent circuit for 1 Æ 0 at B vB (0 ) = VS (5V )

RL

VS + – RON

CGS

+ vB –

CGS

+ vB –

X Thévenin replacement … RTH

VTH + –

RTH = RL || RON VTH 6.002 Fall 2000

RON = VS RON + RL Lecture

13

10

From

1 vB = VTH + (VS − VTH ) e

−t RTH CGS

Falling decay tf is the t for which vB falls to VOL −t f

VOL = VTH + (VS − VTH ) e RTH CGS or

VOL − VTH t f = − RTH CGS ln VS − VTH

6.002 Fall 2000

Lecture

13

11

t f = − RTH CGS ln

e.g.

RL = 1K

VS = 5V

CGS = 0.1 pF RTH ≈ 10Ω,

VOL − VTH VS − VTH RON = 10Ω

VOL = 1V

VTH ≈ 0V

t f = −10 ⋅ 0.1 ⋅10 = 1.6 ps

−12

1 ln 5

RC = 1 ps !

6.002 Fall 2000

Lecture

13

12

For recitation: Slow may be better

Problem

chip

pin 2 pin 1

v CL

v:

ideal

observed

slow!

So the engineers decided to speed it up…

RL RON

6.002 Fall 2000

made RL small made RON small

Lecture

13

13

For recitation: Slow may be better

Problem

chip

pin 2 pin 1

v CL

v:

ideal

…

observed

slow!

but, disaster!

v:

observed expected

6.002 Fall 2000

VIL

Lecture

13

14

Why? Consider Case

1

…

Demo

R1

pin1

R0 ok

6.002 Fall 2000

Lecture

13

15

Why? Consider Case 2

…

Demo

CP

R1

pin1

pin2

R0

R2

crosstalk! CP

R model for crosstalk:

+ v

+ –

–

6.002 Fall 2000

Lecture

13

16

Case 3

…

6.002 expert saw the solution R1

CP

R0

R2

+ –

slower transitions!

Detailed analysis in recitation.

6.002 Fall 2000

Lecture

13

17

6.002

CIRCUITS AND ELECTRONICS

State and Memory

6.002 Fall 2000

Lecture 14

1

Review Recall

vI + – v I = VI

for

R

C

+ vC – vC (0 )

t ≥0 −t

vC = VI + (vC (0)− VI ) e RC

1

Reading: Sections 10.3, 10.5, and 10.7

6.002 Fall 2000

Lecture 14

2

This lecture will dwell on the memory property of capacitors. For the RC circuit in the previous slide

vI

VI

t ≥0

vI

t

0

vC VI −t

vC = VI + (vC (0)− VI ) e RC

vC (0 ) 0

t

Notice that the capacitor voltage for t ≥ 0 is independent of the form of the input voltage before t = 0 . Instead, it depends only on the capacitor voltage at t = 0 , and the input voltage for t ≥ 0 .

6.002 Fall 2000

Lecture 14

3

State State : summary of past inputs relevant to predicting the future

q=CV for linear capacitors, capacitor voltage V is also state variable state variable, actually

6.002 Fall 2000

Lecture 14

4

State Back to our simple RC circuit 1

vC = f (vC (0 ), vI (t )) vC = VI + (vC (0 ) − VI ) e

−t RC

Summarizes the past input relevant to predicting future behavior

6.002 Fall 2000

Lecture 14

5

State

We are often interested in circuit response for zero state vC (0) = 0 zero input

vI (t) = 0

Correspondingly, zero state response or ZSR vC = VI − VI e

−t RC

2

zero input response or ZIR vC = vC (0 ) e

6.002 Fall 2000

−t RC

Lecture 14

3

6

One application of STATE

DIGITAL MEMORY Why memory? Or, why is combinational logic insufficient?

Examples Consider adding 6 numbers on your calculator 2+9+6+5+3+8 M+ “Remembering” transient inputs

6.002 Fall 2000

Lecture 14

7

Memory Abstraction A 1-bit memory element

d IN store M d OUT

The 6.004 view

The NEC View

$

¥

☺

Remembers input when store goes high. Like a camera that records input (dIN) when the user presses the shutter release button. The recorded value is visible at dOUT .

d IN store d OUT 6.002 Fall 2000

remembers the 1 Lecture 14

8

Building a memory element … A First attempt

dIN

*

dOUT C

storage node

store

6.002 Fall 2000

Lecture 14

9

Building a memory element … A

vC d OUT

dIN

*

store = 1

C vC d OUT

dIN

*

store = 0

C vC

Stored value leaks away

vC = 5 ⋅ e

−t RL C

T = − RLC ln

VOH 5

RL

5V VOH

from 2

T

t

store pulse width >> RON C 6.002 Fall 2000

Lecture 14

10

Building a memory element … B Second attempt

dIN

buffer

dOUT

* C

RIN

buffer

store Input resistance RIN VOH T = − RIN C ln 5 RIN >> RL Better, but still not perfect.

Demo

6.002 Fall 2000

Lecture 14

11

Building a memory element … C Third attempt

buffer + refresh

store dIN

dOUT

* store

C Does this work?

No. External value can influence storage node.

6.002 Fall 2000

Lecture 14

12

Building a memory element … D Fourth attempt

buffer + decoupled refresh

store dIN

dOUT

* store

C Works!

6.002 Fall 2000

Lecture 14

13

A Memory Array 4-bit memory

Decoder 00

01

10

11

OUT

A

d IN S M d OUT

B

d IN S M d OUT

A

C

d IN S M d OUT

B

D

d IN S M d OUT

C

a0 a1

2 Address

IN

store Address

IN store D

6.002 Fall 2000

Lecture 14

OUT

14

Truth table for decoder

a0 0 0 1 1

a1 0 1 0 1

6.002 Fall 2000

A 1 0 0 0

B 0 1 0 0

Lecture 14

C 0 0 1 0

D 0 0 0 1

15

Agarwal’s top 10 list on memory 10 9 8 7 6 5

I have no recollection, Senator. I forgot the homework was due today. Adlibbing ≡ ZSR I think, therefore I am. I think that was right. I forgot the rest …

6.002 Fall 2000

Lecture 14

16

6.002

CIRCUITS AND ELECTRONICS

Second-Order Systems

6.002 Fall 2000

Lecture

15

1

Second-Order Systems 5V

5V

Demo 2KΩ

50Ω

2KΩ

S

A + –

C

B large loop

CGS

Our old friend, the inverter, driving another. The parasitic inductance of the wire and the gate-to-source capacitance of the MOSFET are shown

[Review complex algebra appendix for next class] 6.002 Fall 2000

Lecture

15

2

Second-Order Systems 5V

5V

Demo

50Ω

2KΩ

2KΩ

S

C A + –

Relevant circuit:

B large loop

2KΩ

CGS

L

5V + –

6.002 Fall 2000

B CGS

Lecture

15

3

Observed Output

2kΩ

5 vA 0

vB 0

t

2kΩ

t

vC 0

t

Now, let’s try to speed up our inverter by closing the switch S to lower the effective resistance 6.002 Fall 2000

Lecture

15

4

Observed Output

~50Ω

5 vA 0

t

vB 0

50Ω

t

vC 0

t Huh!

6.002 Fall 2000

Lecture

15

5

First, let’s analyze the LC network

vI (t )

i (t )

L

+ –

C

+ v(t ) –

Node method:

i (t ) = C

dv dt

Recall

vI − v = L

t

dv 1 (vI − v) dt = C ∫ L −∞ dt

1 (v I − v ) L

di dt

1 t (vI − v) dt = i ∫ L −∞

d 2v =C 2 dt

d 2v LC 2 + v = vI dt time2 6.002 Fall 2000

v, i state variables Lecture

15

6

Solving Recall, the method of homogeneous and particular solutions: 1

Find the particular solution.

2

Find the homogeneous solution. L 4 steps

3

The total solution is the sum of the particular and homogeneous. Use initial conditions to solve for the remaining constants.

v = vP (t ) + vH (t )

6.002 Fall 2000

Lecture

15

7

Let’s solve d 2v LC 2 + v = vI dt For input

V0

vI

t

0 And for initial conditions v(0) = 0 i(0) = 0 [ZSR]

6.002 Fall 2000

Lecture

15

8

1

Particular solution

d 2 vP LC 2 + vP = V0 dt is a solution.

vP = V0

6.002 Fall 2000

Lecture

15

9

2

Homogeneous solution Solution to

d 2 vH LC 2 + vH = 0 dt

Recall, vH :

solution to homogeneous equation (drive set to zero)

Four-step method:

A Assume solution of the form* vH = Ae st , A, s = ? so,

LCAs 2 e st + Ae st = 0 1 s =− LC

B

characteristic equation

2

1 s=±j LC C Roots

j = −1

ωo =

s = ± jω o

1 LC

General solution,

D

vH = A1e jωot + A2 e − jωot

6.002 Fall 2000

Lecture

Differential equations are commonly solved by guessing solutions

*

15

10

3

Total solution v(t ) = vP (t ) + vH (t )

v( t ) = V0 + A1e jωot + A2 e − jωot Find unknowns from initial conditions. v(0) = 0 0 = V0 + A1 + A2 i ( 0) = 0 dv i (t ) = C dt

i( t ) = CA1 jωo e jωot − CA2 jωo e − jωot so,

0 = CA1 jωo − CA2 jωo

or,

A1 = A2

− V0 = 2 A V0 A1 = − 2 so,

V0 jωot v( t ) = V0 − (e + e − jωot ) 2

6.002 Fall 2000

Lecture

15

11

3

Total solution

Remember Euler relation e jx = cos x + j sin x

(verify using Taylor’s expansion)

e jx + e − jx = cos x 2 so,

v( t ) = V0 − V0 cos ωot

where

i( t ) = CV0ωo sin ωot

1 ωo = LC

The output looks sinusoidal

6.002 Fall 2000

Lecture

15

12

v(t )

Plotting the Total Solution

2V0

V0

0

π

π

3π 2

2 CV0ωo

0

2π

ωo t

i (t )

π

π

2

3π 2

2π

ωo t

− CV0ωo 6.002 Fall 2000

Lecture

15

13

Summary of Method 1

Write DE for circuit by applying node method.

2

Find particular solution vP by guessing and trial & error.

3

Find homogeneous solution vH A Assume solution of the form Aest . B Obtain characteristic equation. C Solve characteristic equation for roots si . D Form vH by summing Ai esit terms.

4

Total solution is vP + vH , solve for remaining constants using initial conditions.

6.002 Fall 2000

Lecture

15

14

Example What if we have:

L

iC

+ C vC –

vC (0) = V iC (0) = 0

We can obtain the answer directly from the homogeneous solution (V0 = 0).

6.002 Fall 2000

Lecture

15

15

Example iC

L

+ C vC –

vC (0) = V iC (0) = 0

We can obtain the answer directly from the homogeneous solution (V0 = 0).

vC ( t ) = A1e jωot + A2 e − jωot vC (0) = V

V = A1 + A2

iC (0) = 0

0 = CA1 jωo − CA2 jωo or A1 = A2 = or

vC =

V 2

V jω o t ( e + e − jω o t ) 2

vC = V cos ωot iC = −CV ωo sin ωot 6.002 Fall 2000

Lecture

15

16

Example vC

V

2π

ωo t

CVωo iC 2π

ωo t

− CVωo

6.002 Fall 2000

Lecture

15

17

Energy EC C:

1 CV 2 2

1 2 CvC 2

2π

ωo t

EL

1 2 L : LiC 2

1 CV 2 2 2π

Notice

ωo t

1 1 1 2 2 CvC + LiC = CV 2 2 2 2

Total energy in the system is a constant, but it sloshes back and forth between the Capacitor and the inductor

6.002 Fall 2000

Lecture

15

18

RLC Circuits R

L

vI (t ) + –

i (t ) C

+ v(t ) –

v(t ) no R add R

t Damped sinusoids with R – remember demo!

See A&L Section 12.2 6.002 Fall 2000

Lecture

15

19

6.002

CIRCUITS AND

ELECTRONICS

Sinusoidal Steady State

6.002 Fall 2000

Lecture

16

1

Review „

We now understand the why of: 5V

v

R L C

„Today, look at response of networks to sinusoidal drive. Sinusoids important because signals can be represented as a sum of sinusoids. Response to sinusoids of various frequencies -- aka frequency response -- tells us a lot about the system

6.002 Fall 2000

Lecture

16

2

Motivation

For motivation, consider our old friend, the amplifier: V S

+ –

vi VBIAS

+ –

vO

vC

R

Demo

CGS

Observe vo amplitude as the frequency of the input vi changes. Notice it decreases with frequency. Also observe vo shift as frequency changes (phase). Need to study behavior of networks for sinusoidal drive. 6.002 Fall 2000

Lecture

16

3

Sinusoidal Response of RC Network

Example:

vI + –

iC

R

vI (t ) = Vi cos ω t =0 vC (0) = 0

+ vC –

for t ≥ 0 (Vi real) for t < 0 for t = 0

vI t

0

6.002 Fall 2000

Lecture

16

4

Our Approach Example:

vI + –

iC

+

vC

–

R

Effort

Determine vC(t)

agony

Usual approach

sneaky approach very sneaky

t

Th is

lec tu re 11 : 0

0 11 : 2 0

1 2 N :0 ex 0 t

le ct ur e

easy

!

e m e g l u d In

6.002 Fall 2000

Lecture

16

5

Let’s use the usual approach…

1

Set up DE.

2

Find vp.

3

Find vH.

4

vC = vP + vH,

6.002 Fall 2000

solve for unknowns using initial conditions

Lecture

16

6

Usual approach…

1

Set up DE

RC

dvC + vC = vI dt = Vi cos ω t

That was easy!

6.002 Fall 2000

Lecture

16

7

2

Find vp dvP + vP = Vi cos ωt RC dt

First try:

Æ nope

vP = A

Second try:

vP = A cos ωt

Third try:

vP = A cos(ωt + φ ) frequency amplitude phase

Æ nope

− RCAω sin(ωt + φ ) + A cos(ωt + φ ) = Vi cos ωt − RCAω sin ωt cos φ − RCAω cos ωt sin φ + A cos ωt cos φ − A sin ωt sin φ = Vi cos ωt

.. .

gasp !

works, but trig nightmare!

6.002 Fall 2000

Lecture

16

8

Let’s get sneaky! Find particular solution to another input…

dvPS + vPS = vIS RC dt = Vi e st st v = V e Try solution PS p RC

dV p e st

(S: sneaky :-))

+ V p e st = Vi e st

dt sRCV p e st + V p e st = Vi e st

Nice property of exponentials

( sRC + 1 )V p = Vi Vi Vp = 1 + sRC Vi ⋅ e st 1 + sRC is particular solution to Vi e st Thus, vPS =

ly

Vi ⋅ e jω t 1 + jωRC

jω t V e solution for i where we replace s = jω

complex amplitude

Vp 6.002 Fall 2000

easy!

Lecture

16

9

2

Fourth try to find vP… using the sneaky approach

Fact 1: Finding the response to Vi e jω t was easy. Fact 2: vI = Vi cos ωt

= real[Vi e jω t ] = real[vIS ]

from Euler relation, e jω t = cos ωt + j sin ωt

real part

vI response vP

vIS response vPS

real part

an inverse superposition argument, assuming system is real, linear. 6.002 Fall 2000

Lecture

16

10

2 Fourth try to find vP… so,

complex vP = Re[vPS ] = Re[V p e jωt ]

 Vi  = Re  ⋅ e jω t   1+ jωRC

Vi (1 − jωRC ) jω t   = Re ⋅e  1 + ω 2 R 2C 2  Vi  j φ jω t  = Re  ⋅ e e  , tan φ = −ωRC 2 2 2   1+ω R C Vi  j( ωt +φ )  = Re  ⋅ e   1 + ω 2 R 2C 2

vP =

Vi 1+ω R C 2

2

2

⋅ cos( ωt + φ )

Recall, vP is particular response to Vi cos ωt . 6.002 Fall 2000

Lecture

16

11

3

Find vH

Recall,

6.002 Fall 2000

vH = Ae

−t RC

Lecture

16

12

4

Find total solution

vC = vP + vH vC =

Vi 1+ω R C 2

2

2

cos( ωt + φ ) + Ae

−

t RC

where φ = tan −1 ( −ωRC )

Given vC(0) = 0 for t = 0 so, Vi A=− cos(φ ) 2 2 2 1+ ω R C Done!

6.002 Fall 2000

Phew !

Lecture

16

13

Sinusoidal Steady State

We are usually interested only in the particular solution for sinusoids, i.e. after transients have died. Notice when t → ∞, vC → vP as e vC =

Vi 1+ω R C 2

2

2

−

t RC

cos( ωt + φ ) + Ae

−

→0 t RC

0

where φ = tan −1 ( −ωRC ) Vi A=− cos(φ ) 2 2 2 1+ ω R C

Vp

∠Vp

Described as SSS: Sinusoidal Steady State

6.002 Fall 2000

Lecture

16

14

Sinusoidal Steady State

All information about SSS is contained in Vp , the complex amplitude! Steps 3 , 4 were a waste of time!

Vi Vp = 1 + jωRC

Recall

Vp

1 = Vi 1+ jωRC Vp Vi

magnitude

=

Vp

phase φ : ∠

Vi Vp Vi

6.002 Fall 2000

1 1 + ω 2 R 2C 2

=

e jφ where

φ = tan −1 − ωRC

1 1 + ω 2 R 2C 2

= − tan −1 ωRC

Lecture

16

15

Sinusoidal Steady State

Visualizing the process of finding the particular solution vP

Vi cos ωt drive

D.E. + nightmare trig.

V p cos[ωt + ∠V p ] particular solution

algebraic take equation real + part complex algebra V p e jω t

sneak in Vi e jωt drive

the sneaky path! 6.002 Fall 2000

Lecture

16

16

Magnitude Plot

transfer function Vp H ( jω ) = Vi

Vp Vi

Vp Vi

=

1 1 + ω 2 R 2C 2

1

log scale log scale

1 ω= RC

ω

From demo: explains vo fall off for high frequencies!

6.002 Fall 2000

Lecture

16

17

Phase Plot

φ = tan −1 − ωRC φ =∠

Vp Vi

ω= 0

− −

1 RC

ω

log scale

π 4

π

2

6.002 Fall 2000

Lecture

16

18

6.002

CIRCUITS AND ELECTRONICS

The Impedance Model

6.002 Fall 2000

Lecture 17

1

Review „

Sinusoidal Steady State (SSS) Reading 13.1, 13.2

vI = Vi cos ωt + –

C

+ vO –

„

Focus on steady state, only care about vP as vH dies away.

„

Focus on sinusoids.

SSS

„

R

Sinusoidal Steady State (SSS) Reading 13.1, 13.2

Reading: Section 13.3 from course notes. 6.002 Fall 2000

Lecture 17

2

Review

vP

Vi cos ωt

1 usual circuit model

sneak in Vi e jωt drive

set up DE

complex algebra

V p cos[ωt + ∠V p ] nightmare trig.

Vp 2

The Sneaky Path

3 vH take 4 real total part

V p e jω t Vi 1 + jωRC

Vp contains all the information we need:

Vp ∠V p 6.002 Fall 2000

Amplitude of output cosine phase Lecture 17

3

Review

vO = V p cos(ωt + ∠V p ) Vp Vi

Vp

=

1 = H ( jω ) transfer function 1 + jωRC remember demo

1

Vi

1 2

1

1 ωRC

1 + ω 2 R 2C 2

Bode plot ∠

Vp

ω=

Vi

ω

1 ω= RC break frequency

0

1 RC

ω

⎛ − ωRC ⎞ π tan −1 ⎜ ⎟ − ⎝ 1 ⎠ 4 −

π 2

The Frequency View 6.002 Fall 2000

Lecture 17

4

Is there an even simpler way to get Vp ? Vi Vp = 1 + jωRC

Divide numerator and denominator by jωC.

1 V p = Vi

jω C 1 +R jω C

Hmmm… looks like a voltage divider relationship.

ZC V p = Vi ZC + R Let’s explore further…

6.002 Fall 2000

Lecture 17

5

The Impedance Model Is there an even simpler way to get Vp ? Consider: + vR –

+ vC –

iR

i R = I r e jω t

vR = RiR

R

vR = Vr e jω t

Vr e jω t = RI r e jω t

Resistor

iC

C

iC = I C e

jω t

vC = VC e jω t

Vr = RI r

dvC iC = C dt I C e jω t = CVC jωe jω t

Capacitor

+ vL –

VC =

diL vL = L dt

jω t

iL

iL = I l e

L

vL = Vl e jω t

Vl e jω t = LI l jωe jω t

Inductor 6.002 Fall 2000

1 IC j ωC ZC

Lecture 17

Vl = jωL I l ZL

6

The Impedance Model In other words, capacitor

Ic + Vc –

ZC

Vc = Z C I c 1 ZC = j ωC impedance

inductor

resistor

Il + Vl –

+ Vr –

ZL

Ir ZR

Vl = Z l I l Z l = j ωL

Vr = Z r I r Zr = R

For a drive of the form Vc e jωt , complex amplitude Vc is related to the complex amplitude Ic algebraically, by a generalization of Ohm’s Law. 6.002 Fall 2000

Lecture 17

7

Back to RC example… R + C vC –

vI + –

Impedance model: ZR = R

Ic + Vc –

Vi + –

1 ZC = jωC

1 ZC jωC Vc = Vi = Vi 1 ZC + Z R +R jωC Vc =

1 Vi 1 + jωRC

Done!

All our old friends apply! KVL, KCL, superposition… 6.002 Fall 2000

Lecture 17

8

Another example, recall series RLC: Remember, we want only the steady-state response to sinusoid

Ir

L Vi e jω t

Vi + –

C R

Vi cos ωt Vr =

Vi Z R Z L + ZC + Z R

+ Vr –

Vr e jω t

Vr cos(ωt + ∠Vr )

Vi R Vr = 1 j ωL + +R jωC Vr =

Vi jωCR − ω 2 LC + 1 + jωCR

We will study this and other functions in more detail in the next lecture. 6.002 Fall 2000

Lecture 17

9

The Big Picture… V p cos[ωt + ∠V p ]

Vi cos ωt usual circuit model

6.002 Fall 2000

set up DE

Lecture 17

nightmare trig.

10

The Big Picture… V p cos[ωt + ∠V p ]

Vi cos ωt usual circuit model

Vi e jωt drive

6.002 Fall 2000

set up DE

nightmare trig.

complex algebra

Lecture 17

take real part

11

The Big Picture… V p cos[ωt + ∠V p ]

Vi cos ωt usual circuit model

Vi e jωt drive

set up DE

nightmare trig.

complex algebra

impedance-based circuit model

take real part

complex algebra

No D.E.s, no trig! 6.002 Fall 2000

Lecture 17

12

Back to

Ir

Vr jωRC = Vi 1 + jωRC − ω 2 LC

Vi

L + –

C R

+ Vr –

Let’s study this transfer function Vr jωRC = Vi 1 + jωRC − ω 2 LC

( jωRC 1 − ω 2 LC ) − jωRC = ⋅ 2 (1 − ω LC ) + jωRC (1 − ω 2 LC ) − jωRC

Vr = Vi

(1 − ω

ωRC

2

LC ) + (ωRC ) 2

2

Observe

Low ω : ≈ ωRC R High ω : ≈ ωL ω LC = 1 : ≈ 1

6.002 Fall 2000

Lecture 17

13

Graphically Vr = Vi

ωRC

(1 − ω

2

LC ) + (ωRC ) 2

2

Low ω : ≈ ωRC R High ω : ≈ ωL ω LC = 1 : ≈ 1

Vr Vi

“Band Pass”

1

R ωL

ωRC 1 LC

ω

Remember this trick to sketch the form of transfer functions quickly. More next week… 6.002 Fall 2000

Lecture 17

14

6.002

CIRCUITS AND ELECTRONICS

Filters

6.002 Fall 2000

Lecture

18

1

Review R vI

+ –

C

+ vC –

ZR

Vi + –

+ Vc –

ZC

ZC Vc = ⋅ Vi ZC + Z R 1 Vc 1 j ωC = = 1 Vi + R 1 + jωRC j ωC Reading: Section 14.5, 14.6, 15.3 from A & L. 6.002 Fall 2000

Lecture

18

2

A Filter ZR

Vi + –

+ Vc –

ZC

ZC 1 ⋅ Vi = Vc = ZC + Z R 1 + jωRC Vc H (ω ) = Vi

1

“Low Pass Filter”

ω

Demo with audio 6.002 Fall 2000

Lecture

18

3

Quick Review of ImpedancesJust as

I ab

A

R1

+

Vab

RAB

Vab = = R1 + R2 I ab

Z AB

Vab = = R1 + jωL I ab

R2

B

I ab

A

R1

–

+

Vab

j ωL B

–

6.002 Fall 2000

Lecture

18

4

Quick Review of Impedances Similarly

A

Z AB = R1 + Z C || R2 + Z L

R1 R2

C L

= R1 +

Z C R2 + ZL Z C + R2

= R1 +

R2 + jωL 1 + jωCR2

B

6.002 Fall 2000

Lecture

18

5

We can build other filters by combining impedances Z (ω )

L Z

R C

6.002 Fall 2000

Lecture

18

ω

6

We can build other filters by combining impedances Z (ω)

L Z

R C

ω

H (ω )

HPF High Pass Filter

+ –

ω H (ω )

LPF Low Pass Filter ω

+ –

H (ω )

HPF

+ –

ω

6.002 Fall 2000

Lecture

18

7

Check out:

C

L

+ R Vr –

Vi + – Intuitively:

Vr 1 Vi C

k bloc

q fre w s lo

L bloc

ωo =

1

(1 − ω

6.002 Fall 2000

ω RC

2

freq

ω

LC

R Vr = 1 Vi jω L + +R jω C j ω RC = 1 − ω 2 LC + j ω RC Vr = Vi

ks hig h

LC ) + (ω RC ) 2

Lecture

2

18

At resonance, ω = ωo and ZL + ZC = 0, so Vi sees only R! More later… 8

What about:

Vi + –

Vlc Vi 1

Vlc

+

L

–

C

R

Band Stop Filter

C open

L open

ω

Check out Vl and Vc in the lab.

6.002 Fall 2000

Lecture

18

9

Another example:

R +

Vi + –

L

C

Vo –

Vo Vi ort h s L

BPF Cs

ωo

ho rt

ω

Application: see AM radio coming up shortly

6.002 Fall 2000

Lecture

18

10

AM Radio Receiver

antenna

R Vi + –

L

C

demodulator amplifier

Thévenin antenna model crystal radio demo

6.002 Fall 2000

Lecture

18

11

AM Receiver R Vi + –

L

C

signal strength

demodulator amplifier

filter 10 KHz

WBZ News Radio

f 540 …1000 1010 1020 1030 … 1600 KHz

“Selectivity” important — relates to a parameter “Q” for the filter. Next… 6.002 Fall 2000

Lecture

18

12

Selectivity: Look at series RLC in more detail C

L

Vi + – Recall,

Vr Vi

+ Vr –

R Vr R = Vi R + jω L + 1 jω C

1

higher Q

1 2

Δω

bandwidth

ω

ωo ωo Define Q = Δω

quality factor

high Q ⇒ more selective 6.002 Fall 2000

Lecture

18

13

Quality Factor Q Q=

ωo Δω

ωο: Vr R = Vi R + jω L +

1 = 1 L 1 ⎞ ⎛ 1 + j⎜ ω − ⎟ jω C ω R CR ⎝ ⎠

at ωο =0 1 ωo = LC Δω ?

6.002 Fall 2000

Lecture

18

14

Quality Factor Q ωo Q= Δω Δω : Note that abs magnitude is when

Vr = Vi

i.e. when

1 2

1 1 = ⎛ L 1 ⎞ 1 ± j1 1 + j⎜ ω − ⎟ ⎝ R ω CR ⎠ ωL 1 − = ±1 R ω CR

ω2 m

ωR L

−

1 =0 LC

Looking at the roots of both equations, R 1 R2 4 ω1 = + + 2 L 2 L2 LC

R 1 ω2 = − + 2L 2

R2 4 + L2 LC

R Δω = ω1 − ω2 = L

6.002 Fall 2000

Lecture

18

15

Quality Factor Q ωo Q= Δω Q=

ωo R L

=

ωo L

1 ωo = LC

R

The lower the R (for series R), the sharper the peak

6.002 Fall 2000

Lecture

18

16

Quality Factor Q Another way of looking at Q : energy stored Q = 2π energy lost per cycle = 2π

1 L Ir 2

2

1 2 2π Ir R ω0 2 ωo L Q= R

6.002 Fall 2000

Lecture

18

17

6.002

CIRCUITS AND ELECTRONICS

The Operational Amplifier Abstraction

6.002 Fall 2000

Lecture 19

1

Review „

MOSFET amplifier — 3 ports +

+ vO output port –

+ input vI port – „

VS

power port

–

Amplifier abstraction VS

+

+ vI –

–

6.002 Fall 2000

+ v – O

vI

Lecture 19

vO Function of vI

2

Review vI

vO Function of vI

„

Can use as an abstract building block for more complex circuits (of course, need to be careful about input and output).

„

Today Introduce a more powerful amplifier abstraction and use it to build more complex circuits.

Reading: Chapter 15 from A & L.

6.002 Fall 2000

Lecture 19

3

Operational Amplifier Op Amp VS

input port

power port

+

+ – output port

–

+ –

−VS More abstract representation: + vIN –

6.002 Fall 2000

+ –

Lecture 19

vOUT

4

Circuit model (ideal): vO

+ i=0

v+

+ v –

v–

– i=0

+ –

Av A→∞

i.e.  ∞ input resistance  0 output resistance  “A” virtually ∞  No saturation

6.002 Fall 2000

Lecture 19

5

Using it… 12V

+ –

VS = 12V

vO

+

vIN

– 12V

RL

− VS = −12V

– +

Demo 12V

− 10 μV

vO active region saturation

10μV

− 12V

vIN

A ~ 106 but unreliable, temp. dependent

(Note: possible confusion with MOSFET saturation!) 6.002 Fall 2000

Lecture 19

6

Let us build a circuit… Circuit: noninverting amplifier v+ v−

vIN + –

+

vO

–

R1 R2

Equivalent circuit model + i=0

vIN + –

op amp

v+ v

−

vO + A(v + − v − ) –

R1

– i=0 R2 6.002 Fall 2000

Lecture 19

7

Let us analyze the circuit: Find vO in terms of vIN, etc.

vO = A(v + − v − ) R2 ⎞ ⎛ = A⎜ vIN − vO ⎟ R1 + R2 ⎠ ⎝ ⎛ AR2 ⎞ vO ⎜ 1 + ⎟ = AvIN ⎝ R1 + R2 ⎠

AvIN vO = AR2 1+ R1 + R2 What happens when “A” is very large?

6.002 Fall 2000

Lecture 19

8

Let’s see… When A is large AvIN AvIN ≈ vO = AR2 AR2 1+ R1 + R2 R1 + R2 ≈ vIN Suppose

(R1 + R2 )

A = 10 6 R1 = 9 R R2 = R

R2 gain

10 6 ⋅ vIN vO = 10 6 R 1+ 9R + R

10 6 ⋅ vIN = 1 6 1 + 10 ⋅ 10 vO ≈ vIN ⋅ 10

Demo

Gain: „ determined by resistor ratio „ insensitive to A, temperature, fab variations 6.002 Fall 2000

Lecture 19

9

Why did this happen? Insight: 5V v+

vIN + –

5V

v−

+ –

10V A 6V

6V

negative feedback

– i =0

12V

vO = 2vIN

R vO 2 R

e.g. vIN = 5V Suppose I perturb the circuit…

(e.g., force vO momentarily to 12V somehow). Stable point is when v+ ≈ v- .

Key: negative feedback Æ portion of output fed to –ve input. e.g. Car antilock brakes Æ small corrections. 6.002 Fall 2000

Lecture 19

10

Question: How to control a high-strung device? Antilock brakes is it turning?

no

di s

yes release apply

Michelin

it’s all about control

c

yes/no k c a db e e f

v. v. powerful brakes

6.002 Fall 2000

Lecture 19

11

More op amp insights: Observe, under negative feedback, ⎛ R1 + R2 ⎞ ⎜ ⎟vIN R1 ⎠ v v+ − v− = O = ⎝ →0 A A

v+ ≈ v− We also know i+ ≈ 0 i -≈ 0 Æyields an easier analysis method (under negative feedback).

6.002 Fall 2000

Lecture 19

12

Insightful analysis method under negative feedback v+ ≈ v− i+ ≈ 0 i− ≈ 0 a vIN

vIN + –

g vO = vIN +

vO

b vIN – c vIN

R1 f

e i=0

vIN d R2

6.002 Fall 2000

R1 + R2 R2

Lecture 19

vIN R2

R2

13

Question: a vIN v +

vIN + –

b vIN

v

−

+ –

c vIN

vO

?

vO ≈ vIN

or

R1 + R2 vO = vIN R2 with R1 = 0 R2 = ∞

6.002 Fall 2000

Lecture 19

14

Why is this circuit useful? +

vIN + –

–

vO

vO ≈ vIN

Buffer

voltage gain = 1 input impedance = ∞ output impedance = 0 current gain = ∞ power gain = ∞

6.002 Fall 2000

Lecture 19

15

6.002

CIRCUITS AND ELECTRONICS

Basic Circuit Analysis Method (KVL and KCL method)

6.002 Fall 2000

Lecture 2

1

Review Lumped Matter Discipline LMD:

Constraints we impose on ourselves to simplify our analysis

∂φ B =0 ∂t ∂q =0 ∂t

Outside elements Inside elements wires resistors sources

Allows us to create the lumped circuit abstraction

6.002 Fall 2000

Lecture 2

2

Review

LMD allows us to create the lumped circuit abstraction i

+

v

Lumped circuit element

power consumed by element = vi

6.002 Fall 2000

Lecture 2

3

Review Review Maxwell’s equations simplify to algebraic KVL and KCL under LMD! KVL:

∑ jν j = 0 loop

KCL:

∑jij = 0 node

6.002 Fall 2000

Lecture 2

4

Review a R1

+ –

b

R4

R3

R2

d R5

c

DEMO

6.002 Fall 2000

vca + vab + vbc = 0

KVL

ica + ida + iba = 0

KCL

Lecture 2

5

Method 1: Basic KVL, KCL method of Circuit analysis Goal: Find all element v’s and i’s 1. write element v-i relationships (from lumped circuit abstraction) 2. write KCL for all nodes 3. write KVL for all loops

lots of unknowns lots of equations lots of fun solve

6.002 Fall 2000

Lecture 2

6

Method 1: Basic KVL, KCL method of Circuit analysis

Element Relationships For R,

V = IR

For voltage source, V = V0

R +–

V0 For current source, I = I 0 J Io 3 lumped circuit elements

6.002 Fall 2000

Lecture 2

7

KVL, KCL Example a +

ν1 +

ν 0 = V0 –

–

+ –

+

ν2 –

+

R1

R3

b

+ν 3 – R2

ν4 –

R4

d +

ν5 –

R5

c The Demo Circuit

6.002 Fall 2000

Lecture 2

8

Associated variables discipline i

+ ν

Element e

Current is taken to be positive going into the positive voltage terminal

Then power consumed by element e

6.002 Fall 2000

Lecture 2

= νi is positive

9

KVL, KCL Example a +

+

ν 0 = V0 –

+ –

ν1

i0

L1

–

+

ν2 –

i4 i1 L 2 + R1 ν 4 R4 – R3 b i3 d +ν 3 – i2 i5 + R2 ν 5 R5 L3 –

c The Demo Circuit

6.002 Fall 2000

Lecture 2

L4

10

Analyze ν 0 …ν 5 ,ι0 …ι5 1. Element relationships (v, i ) given v3 = i3 R3 v0 = V0 v4 = i4 R4 v1 = i1 R1 v5 = i5 R5 v2 = i2 R2

12 unknowns 6 equations

2. KCL at the nodes a: i0 + i1 + i4 = 0 3 independent b: i2 + i3 − i1 = 0 equations d: i5 − i3 − i4 = 0 e: − i0 − i2 − i5 = 0 redundant 3. KVL for loops L1: − v0 + v1 + v2 = 0 3 independent equations L2: v1 + v3 − v4 = 0 L3: v3 + v5 − v2 = 0 s L4: − v0 + v4 + v5 = 0 redundant n o i t ns a w u o n k eq n u 1 2 12

/

ugh @#! 6.002 Fall 2000

Lecture 2

11

Other Analysis Methods Method 2— Apply element combination rules

A B

C

D

R1

R2 R3

G1

G2

V1

V2

+–

+–

GN

⇔

⇔

⇔

⇔

R1 + R2 +

G1 + G2

1 Gi = Ri

+ RN

+ GN

V1 + V2 +–

J

I2

J

J

I1

…

RN

I1 + I 2

Surprisingly, these rules (along with superposition, which you will learn about later) can solve the circuit on page 8

6.002 Fall 2000

Lecture 2

12

Other Analysis Methods Method 2— Apply element combination rules

I =?

Example

R1

V + –

R3

R2

I

I V + –

R1

R2 R3 R2 + R3

V + –

R = R1 +

R R2 R3 R2 + R3

V I= R 6.002 Fall 2000

Lecture 2

13

Method 3—Node analysis Particular application of KVL, KCL method 1. Select reference node ( ground) from which voltages are measured. 2. Label voltages of remaining nodes with respect to ground. These are the primary unknowns. 3. Write KCL for all but the ground node, substituting device laws and KVL. 4. Solve for node voltages. 5. Back solve for branch voltages and currents (i.e., the secondary unknowns)

6.002 Fall 2000

Lecture 2

14

Example: Old Faithful plus current source

V0

Step 1

6.002 Fall 2000

e2

R2

R5

J

+ V e1 – 0

R4

R1 R 3

I1

Step 2

Lecture 2

15

Example: Old Faithful plus current source

V0

R2

R4 e2

R5

J

+ V e1 – 0

R1 R 3

for I1 convenience, write 1 Gi = Ri

KCL at e1 (e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0

KCL at e2 (e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0 Step 3

6.002 Fall 2000

Lecture 2

16

Example: Old Faithful plus current source

V0 e2

R2

R5

J

+ V e1 – 0

R4

R1 R 3

I1

Gi =

KCL at e1 (e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0

1 Ri

KCL at l2 (e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0 move constant terms to RHS & collect unknowns

e1 (G1 + G2 + G3 ) + e2 (−G3 ) = V0 (G1 ) e1 (−G3 ) + e2 (G3 + G4 + G5 ) = V0 (G4 ) + I1 2 equations, 2 unknowns (compare units) 6.002 Fall 2000

Lecture 2

Solve for e’s Step 4 17

In matrix form: G1 + G2 + G3  − G3 

− G3   e1   G1V0  = G V + I  G3 + G4 + G5  e2   4 0 1

conductivity matrix

sources

unknown node voltages

Solve G3 G3 + G4 + G5   G1V0  G3 G1 + G2 + G3  G4V0 + I1   e1   e  = (G1 + G2 + G3 )(G3 + G4 + G5 ) − G3 2  2

(

)(

) ( )(

)

G +G +G G V + G G V + I 3 4 5 1 0 3 4 0 1 e = 1 G G +G G +G G +G G +G G +G G +G 2 +G G +G G 1 3 1 4 1 5 2 3 2 4 2 5 3 3 4 3 5 e2 =

(G3 )(G1V0 ) + (G1 + G2 + G3 )(G4V0 + I 1 ) 2

G1G3 + G1G4 + G1G5 + G2G3 + G2G4 + G2 G5 + G3 + G3G4 + G3G5

(same denominator)

Notice: linear in V0 , I1 , no negatives in denominator 6.002 Fall 2000

Lecture 2

18

Solve, given G1  1 =  G5  8.2 K

G2  1 = G4  3.9 K

1 G3 = 1.5 K

I1 = 0

(

)(

)

G G V + G +G +G G V + I e = 3 10 1 2 3 40 1 2 G + G + G + G + G + G −G 2 1 2 3 3 4 5 3 1 1 1 G +G +G = + + =1 1 2 3 8.2 3.9 1.5

(

G3 + G4 + G5 =

)(

)

1 1 1 + + =1 1.5 3.9 8.2

1 1 1 × + 1× 3.9 V e2 = 8.2 1.5 0 1 1− 2 1.5

Check out the DEMO

e2 = 0.6V0

If V0 = 3V , then e2 = 1.8V0 6.002 Fall 2000

Lecture 2

19

6.002

CIRCUITS AND ELECTRONICS

Operational Amplifier Circuits

6.002 Fall 2000

Lecture 20

1

Review „

Operational amplifier abstraction + –

 ∞ input resistance  0 output resistance  Gain “A” very large

„

Building block for analog systems

„

We will see these examples: Digital-to-analog converters Filters Clock generators Amplifiers Adders Integrators & Differentiators

Reading: Chapter 15.5 & 15.6 of A & L.

6.002 Fall 2000

Lecture 20

2

Consider this circuit: i i

R1

v2 + – v1 + –

R2 v = v1 R1 + R2 ≈ v− +

v2 − v − i= R1

R1

R2

v− – v+ +

+ vOUT –

R2

vOUT = v − − iR2 − v − v = v− − 2 ⋅ R2 R1

R ⎡ R ⎤ = v − ⎢1 + 2 ⎥ − v2 2 R1 ⎣ R1 ⎦ = v1

R2 R + R2 R ⋅ 1 − v2 2 R1 + R2 R1 R1

R2 = (v1 − v2 ) R1 6.002 Fall 2000

subtracts!

Lecture 20

3

Another way of solving — use superposition v1 → 0

v2 → 0 R1

R2 R1 v2 +

–

v1 +

–

–

v+ + R2

–

vOUT2

+

vOUT2

vOUT1

R1 + R2 =v ⋅ R1 +

v1 ⋅ R2 R1 + R2 = ⋅ R1 + R2 R1 = v1

vOUT = vOUT1 + vOUT2 R2 = (v1 − v2 ) R1 6.002 Fall 2000

R2

R1

R1 || R2

R2 = − v2 R1

vOUT1

Lecture 20

R2 R1

Still subtracts! 4

Let’s build an intergrator… vI + –

+ vO –

∫ dt

Let’s start with the following insight: i

+ i + –

C

vO –

t

1 vO = ∫ i dt C −∞ vO is related to ∫ i dt But we need to somehow convert voltage vI to current. 6.002 Fall 2000

Lecture 20

5

First try… use resistor + vR –

vI + –

i

+

R C

vO

vI →i R

– But, vO must be very small compared to vR, or else v i≠ I R When is vO small compared to vR ? dv larger the RC, RC O + vO = vI dt smaller the vO vR dvO when RC >> vO for good dt integrator dvO RC ≈ vI ωRC >> 1 dt t 1 or vO ≈ vI dt ∫ RC −∞ Demo 6.002 Fall 2000

Lecture 20

6

There’s a better way… i

Notice i

– +

v − ≈ 0V under negative feedback vI i = so, R – R vI + – +

vI R

+

vC

–

– vI

+ –

R

+

vO = −vC

+ t vO 1 vI – vO = − ∫ dt C −∞ R

We have our integrator. 6.002 Fall 2000

Lecture 20

7

Now, let’s build a differentiator… + vO –

d dt

vI + –

Let’s start with the following insights: i vI

+ –

C

dvI i=C dt

dvI i is related to dt But we need to somehow convert current to voltage.

6.002 Fall 2000

Lecture 20

8

Differentiator… Recall

i i

– + R

i

– + vO –

+ 0V

i

C vI + –

+ vC –

Demo 6.002 Fall 2000

R – +

vO = −iR

current to voltage

vO vI = vC dvI i=C dt

dvI vO = − RC dt Lecture 20

9

6.002

CIRCUITS AND ELECTRONICS

Op Amps Positive Feedback

6.002 Fall 2000

Lecture

21

1

Negative vs Positive Feedback Consider this circuit — negative feedback vIN R1 R2 – R1 vIN + + R – + vOUT = − 2 vIN – R1 is s e y l g a a an t p e ex e s n on + R2 vOUT = − vIN ” “ – R1

and this — positive feedback

vIN + –

R1

+

R2

–

What’s the difference? Consider what happens when there is a pertubation… Positive feedback drives op amp into saturation:

vOUT → ±VS

6.002 Fall 2000

Lecture

21

2

Static Analysis of Positive Feedback Ckt v IN

v IN + –

+ –

R1

+ –

R2

vOUT

v + R2

R1

v

−

vOUT

+ –

A(v + − v − )

vOUT = A(v + − v − ) = Av +

 v − vIN  = A OUT ⋅ R1 + vIN   R1 + R2  =

AR1vIN AR1 vOUT − + AvIN R1 + R2 R1 + R2

  AR1  R1  vOUT 1 − v A 1 = −  IN  R + R    R1 + R2  1 2

vOUT

6.002 Fall 2000

1 − R1   R +R  R2 1 2 Av vIN ⋅ = − =  IN AR R1 1 −   R1 + R2 

Lecture

21

3

Representing dynamics of op amp…

v+ + – v−

6.002 Fall 2000

+ v*

R

C (v + − v − )

Lecture

vo + –

Av*

–

21

4

Representing dynamics of op amp… Consider this circuit and let’s analyze its dynamics to build insight. R2 R1 +

vo

– R4

R3 Circuit model R1

v+ v−

R3

vo A

R2

+ –

R

C (v + − v − )

+ v*

+ –

–

+ vo –

R4

Let’s develop equation representing time behavior of vo . 6.002 Fall 2000

Lecture

21

5

Dynamics of op amp… vo = Av

*

vo or v = A *

dv* * RC + v = v+ − v_ dt

vo R1 + = γ vo R1 + R2 vo R3 − v = =− γ vo R3 + R4

v+ =

RC dvo vo + = v+ − v_ A dt A + = ( γ − −γ ) vo neglect

or

dvo  1 A − +  + + ( γ − γ ) vo = 0   dt  RC RC dvo A − + + ( γ − γ ) vo = 0 dt RC time −1

or

dvo vo RC + = 0 where T = − + A( γ − γ ) dt T

vo ( 0 ) = 0 6.002 Fall 2000

Lecture

21

6

Consider a small disturbance to vo (noise). + − if γ > γ

T is positive vo = K e

if

+ γ > γ−

−

+ − γ = γ

vo

K

stable

T is negative vo = K e

if

t T

t T

unstable

T is very large vo = K neutral unstable

neutral stable

t

disturbance

Now, let’s build some useful circuits with positive feedback. 6.002 Fall 2000 Lecture 21

7

One use for instability: Build on the basic op amp as a comparator + VS

v+

+

v−

–

vo

− VS

+ VS

vo

v+ − v−

0

− VS

vo −

v →0

6.002 Fall 2000

v

+

t Lecture

21

8

Now, use positive feedback vi

–

vo

+

R2

vo R1 v = R1 + R2 +

+

v = 7.5

R1

vo = 15

vi

( vi = v − ) > 7.5

v− < v+ v − < −7.5

v − > 7.5 vo = −15

6.002 Fall 2000

e.g. R1 = R2 VS = 15

Lecture

v − = −7.5

21

9

Now, use positive feedback vi

–

vo

+

R2

vo R1 v = R1 + R2 +

VS R1 v = R1 + R2 +

R1

vo = +VS

15

vi

( vi = v − ) > v +

e.g. R1 = R2 VS = 15

v− < v+ v − < −7.5

v − > 7.5

vo = −VS − 15 v − =

6.002 Fall 2000

Lecture

21

− VS R1 R1 + R2

10

vo

15

VS

hysteresis − 7 .5

Demo

0

vi

7 .5

− 15

− VS

Why is hysteresis useful? vi v o

e.g., analog to digital

7.5

t − 7.5

Demo 6.002 Fall 2000

Lecture

21

11

Without hysteresis

vi 7.5

analog to digital

vo

vi

t − 7.5

6.002 Fall 2000

Lecture

21

12

Oscillator — can create a clock R

vC

–

C

vo

+

R1

vo 2

R1

vo VS VS 2

v+ v− vC

VS − 2 − VS

Demo 6.002 Fall 2000

v

t

−

v+

Assume Lecture

vo = VS vC = 0 21

at t = 0 13

Clocks in Digital Systems „ We built an oscillator using an op amp.

t can use as a clock „ Why do we use a clock in a digital system?

(See page 735 of A & L)

1

1

0

sender

receiver

clock a

1,1,0?

b

When is the signal valid? common timebase -- when to “look” at a signal (e.g. whenever the clock is high)

Æ Discretization of time one bit of information associated with an interval of time (cycle) 6.002 Fall 2000

Lecture

21

14

6.002

CIRCUITS AND ELECTRONICS

Energy and Power

6.002 Fall 2000

Lecture

22

1

Why worry about energy?

-

small batteries Æ good

Today: How long will the battery last? in standby mode in active use „ Will the chip overheat and self-destruct? „

6.002 Fall 2000

Lecture

22

2

Look at energy dissipation in MOSFET gates VS R + + vI –

C

vO –

C: wiring capacitance and CGS of following gate Let us determine standby power active use power Let’s work out a few related examples first. 6.002 Fall 2000

Lecture

22

3

Example 1:

I

V + –

Power

R

+ V –

V2 P = VI = R

Energy dissipated in time T

E = VIT

6.002 Fall 2000

Lecture

22

4

Example 1: for our gate

VS

VS RL

RL

vO

vI high

vI low

RON

RON

2

VS P= RL + RON

6.002 Fall 2000

Lecture

vO

P=0

22

5

Example 2: Consider R1 S1

VS + –

S2 R2

C

T T1

T2

S1 closed S1 open S 2 open

S 2 closed t

Find energy dissipated in each cycle. Find average power P. 6.002 Fall 2000

Lecture

22

6

T1 : S1 closed, S2 open i VS + –

R1

+ vC –

C

vC

i

VS R1

VS

t

6.002 Fall 2000

assume vC = 0 at t = 0

Lecture

VS e R1

−t R1C

t

22

7

Total energy provided by source during T1 T1

E = ∫ VS i dt 0

T1

2

VS e R1 0

=∫

−t R1C

dt

2

=−

VS R1C e R1

−t T1 R1C 0

−T1   2 R C 1 = C VS  1 − e      2

≈ C VS if T1 >> R1C

I.e., if we wait long enough

1 2 C VS stored on C , 2 1 2 E1 = C VS dissipated in R1 2 6.002 Fall 2000

Lecture

22

Independent of R!

8

T2 : S2 closed, S1 open + vC –

C

R2

Initially, vC = VS

(recall T1 >> R1C)

So, initially,

1 2 energy stored in capacitor = CVS 2 Assume T2 >> R2C So, capacitor discharges ~fully in T2 So, energy dissipated in R2 during T2

1 2 E2 = CVS 2 E1, E2 independent of R2 ! 6.002 Fall 2000

Lecture

22

9

Putting the two together: Energy dissipated in each cycle E = E1 + E2 1 1 2 2 = CVS + CVS 2 2

E = CVS

2

energy dissipated in charging & discharging C

Assumes C charges and discharges fully. Average power

P=

E T

CVS = T

2

2

= CVS f

frequency f = 6.002 Fall 2000

Lecture

22

1 T 10

Back to our inverter — VS RL

vO vIN

RON

C

What is P for the following input?

vIN T 2

T 2 T

6.002 Fall 2000

t 1 T= f

Lecture

22

11

Equivalent Circuit RL

VS + –

C RON

What is P for the following input? vIN

T 2

T 2 T

6.002 Fall 2000

t 1 T= f

Lecture

22

12

What is P for gate? We can show (see section 12.2 of A & L) 2

P=

2

VS RL 2 + CVS f 2( RL + RON ) (RL + RON )2

when RL >> RON 2

VS 2 P= + CVS f 2 RL

r e b m e m re

P STATIC independent of f. MOSFET ON half the time.

6.002 Fall 2000

e b m e rem

r

P DYNAMIC related to switching capacitor

Lecture

22

13

What is P for gate? when RL >> RON 2

VS 2 P= + CVS f 2 RL In standby mode, half the gates in a chip can be assumed to be on. So P STATIC per gate is still VS2 .

In standby mode, fÆ0, so dynamic power is 0

2RL Relates to standby power.

6.002 Fall 2000

Lecture

22

14

Some numbers… a chip with 106 gates clocking C =1f F at 100 MHZ RL = 10 kΩ f = 100 × 10 6 VS = 5 V 25 −15 6 P = 10 6  10 25 100 10 + × × × 4   2 × 10 = 10 6 [1.25 milliwatts + 2.5 microwatts ]

problem !

1.25KW!

must get rid of this

α VS 2 α f reduce VS

next lecture 6.002 Fall 2000

2.5W not bad

5 V → 1V 2.5 W → 150 mW Lecture

22

15

6.002

CIRCUITS AND ELECTRONICS

Energy, CMOS

6.002 Fall 2000

Lecture

23

1

Review „

VS RL

2

VS P= RL + RON

vO

vI

RON

„

T1: closed T2: open R

open closed

1

VS + –

S1

S2

C

R2

1 T = T1 + T2 = f 2

P = CVS f

Reading: Section 11.5 of A & L. 6.002 Fall 2000

Lecture

23

2

Review

VS RL

Inverter —

vO

vI

RON

C

1 Square wave input T= f 2 VS 2 P= + CVS f 2 RL

Demo

P STATIC

independent of f. MOSFET ON half the time.

P DYNAMIC

RL >> RON T >>" RC" 2 time constant

related to switching capacitor. In standby mode, fÆ0, so dynamic power is 0

In standby mode, half the gates in a chip can be assumed to be on. So P STATIC per gate is still VS2 . 2RL

6.002 Fall 2000

Lecture

23

3

Review

2

P=

VS 2 + CVS f 2 RL

Chip with 106 gates clocking at 100 MHz

C = 1 f F, RL = 10 KΩ , f = 100 × 10 6 , VS = 5 V 2 ⎡ 5 6 −15 2 6⎤ P = 10 ⎢ + 10 × 5 × 100 × 10 ⎥ 3 gates ⎣ 2 × 10 × 10 ⎦

= 10 6 [1.25 milliwatts + 2.5 μ watts ]

1.25KWatts problem ! • independent of f • also standby power (assume ½ MOSFETs ON if f Æ 0) • must get rid of this!

6.002 Fall 2000

Lecture

2.5Watts not bad

+

• αf • αVS2

reduce VS 5VÆ1V 2.5VÆ150mW

23

4

How to get rid of static power Intuition: VS i

VS RL

RL

vO low

vI high

vI low

RON

vO high

MOSFET off

idea !

VS

vI high

6.002 Fall 2000

vO low

Lecture

23

5

New Device PFET • N-channel MOSFET (NFET)

D G S

on when vGS ≥ VTN off when vGS < VTN e.g. VTN = 1V

• P-channel MOSFET (PFET) S G

on when vGS ≤ VTP off when vGS > VTP e.g. VTP = -1V

D

5V ON when less than 4V

6.002 Fall 2000

Lecture

23

6

Consider this circuit: VS

vI

+ –

G

S D

G

D S

PU = pull up

vO PD = pull down

works like an inverter!

IN

6.002 Fall 2000

OUT

Lecture

23

7

Consider this circuit: works like an inverter!

OUT

IN

vI = 5V (input high)

vI = 0V (input low)

VS = 5V

VS = 5V RON p

+ vI = 5V –

vO RON n

= 0V

+ vI = 0V –

vO = 5V

Complementary MOS (our previous logic was called “NMOS”)

Called “CMOS logic”

6.002 Fall 2000

Lecture

23

8

Key: no path from VS to GND! no static power! Let’s compute P DYNAMIC VS

vI T

vI

vO

C

closed for vI high

closed for vI low

RON p

VS + – From

6.002 Fall 2000

t

1 f = T

RON n

C

2

P = CVS f

Lecture

23

9

For our previous example — C = 1 f F, VS = 5 V , f = 100 MHz , 1 2

P = CV S f = 10

− 15

× 5 2 × 100 × 10 6

= 2 . 5 μwatts per gate P = 2 . 5 μwatts for 10 6 gate chip Gates

f

P

106

100 ~2.5 MHz watts

Pentium?

2x106

300 ~15 MHz watts

PII?

2x106

600 ~30 MHz watts

PII?

8x106

~240 1.2 GHz watts

25x106

~1875 3 GHz watts

6.002 Fall 2000

Lecture

PIII?

“keep all else same”

! p s ga

PIV?

23

10

How to reduce power A VS 5V Æ 3V Æ 1.8V Æ 1.5V ~PIV Æ 170 watts Æ better, but high

and use big heatsink B Turn off clock when not in use. C Change VS depending on need. Æ Æ next time: power supply

6.002 Fall 2000

Lecture

23

11

CMOS Logic NAND: VS A

A B 0 0 0 1 1 0 1 1

B

Z 1 1 1 0

Z A B

5V 0V G

6.002 Fall 2000

S on D

Lecture

5V 5V G

23

S off D

12

In general, if we want to implement F e.g. F = A ⋅ B = A + B

VS

short when A = 0 or B = 0, open otherwise

short when F is true, else open

A B

Z short when F is true, else open

short when A · B is true, else open

r e b m reme gan’s law r o M e D

6.002 Fall 2000

Lecture

23

13

6.002

CIRCUITS AND ELECTRONICS

Power Conversion Circuits and Diodes

6.002 Fall 2000

Lecture 24

1

Power Conversion Circuits (PCC) PCC

+ – 5V DC

PCC

+ – 5V DC

110V 60Hz

solar cells, battery

3V DC

DC-to-DC UP converter Power efficiency of converter important, so use lots of devices: MOSFET switches, clock circuits, inductors, capacitors, op amps, diodes

R

Reading: Chapter 16 and 4.4 of A & L. 6.002 Fall 2000

Lecture 24

2

First, let’s look at the diode

⎛ VvD ⎞ T ⎜ iD = I S e − 1 ⎟ ⎜ ⎟ ⎠ ⎝ I S = 10 −12 A

iD

+ vD –

VT = 0.025V Boltzmann’s constant temperature in Kelvins charge of an electron

kT VT = q iD

iD

vD

− IS

vD V

mV

Can use this exponential model with analysis methods learned earlier „

analytical

„

graphical

„

incremental

(Our fake expodweeb was modeled after this device!)

6.002 Fall 2000

Lecture 24

3

Another analysis method: piecewise–linear analysis P–L diode models: iD iD ≥ 0 Æ vD = 0

“short” or on

vD < 0 Æ iD = 0

0

vD

“open” or off

Ideal diode model

6.002 Fall 2000

Lecture 24

4

Another analysis method: piecewise–linear analysis “Practical” diode model ideal with offset

+–

0.6V

iD Short segment Open segment

iD = 0

6.002 Fall 2000

vD = 0

0.6V

Lecture 24

vD

5

Another analysis method: piecewise–linear analysis

Piecewise–linear analysis method „ „

Replace nonlinear characteristic with linear segments. Perform linear analysis within each segment.

6.002 Fall 2000

Lecture 24

6

Example (We will build up towards an AC-to-DC converter)

0.6V +–

Consider + vI + –

R

vO –

vI

is a sine wave

6.002 Fall 2000

Lecture 24

7

Example 0 .6 V +–

Equivalent circuit

+

vI + –

vO

R

– “Short segment”: iD = (vI − 0.6 ) / R vI ≥ 0.6

+–

+

0.6V

+ vI –

R

vO = vI − 0.6

– “Open segment”: iD = 0

vI < 0.6

+ vI –

+– 0.6V

+

R

vO = 0

– 6.002 Fall 2000

Lecture 24

8

Example vI

vO 0.6 t

6.002 Fall 2000

Lecture 24

9

Now consider — a half-wave rectifier 0.6V

+– vI + –

C

+ R

vO

–

6.002 Fall 2000

Lecture 24

10

A half-wave rectifier

vI

diode on

diode off

vO

Demo

t

C current pulses charging capacitor

MIT’s supply shows “snipping” at the peaks (because current drawn at the peaks) 6.002 Fall 2000

Lecture 24

11

se Do not u resistive s! el em en t

DC-to-DC UP Converter i

+ VI + DC –

vS

C vO

switch

S

load

–

vS S

S

closed

T

open

t Tp

The circuit has 3 states: I. II. III.

S is on, diode is off i increases linearly S turns off, diode turns on C charges up, vO increases S is off, diode turns off C holds vO (discharges into load)

6.002 Fall 2000

Lecture 24

12

More detailed analysis I. Assume i(0) = 0, vO(0) > 0 S on at t = 0, diode off L i

VI + –

VI T i (T ) = L

vO C

i

di VI = L dt

VI slope = L

i is a ramp

t

T

1 ΔE = energy stored at t = T : Li( T )2 2 2

VI T 2 ΔE = 2L 6.002 Fall 2000

Lecture 24

13

II. S turns off at t = T

diode turns on (ignore diode voltage drop) L

vO

i

VI + –

S

State III starts here

i

VI T L

C

0 T T′

TP

t

1 ωO = LC

Diode turns off at T′ when i tries to go negative.

6.002 Fall 2000

Lecture 24

14

II. S turns off at t = T, diode turns on Let’s look at the voltage profile

i

VI T L

0 T T′

1 ωO = LC

Capacitor voltage ignore diode drop

ωO =

TP

vO

III.

vO (T ) 1 LC

t

ΔvO

0 T T′

TP

t

Diode turns off at T′ when I tries to go negative. 6.002 Fall 2000

Lecture 24

15

II. S turns off at t = T, diode turns on Let’s look at the voltage profile

i

VI T L

0 T T′

1 ωO = LC

Capacitor voltage ignore diode drop

ωO =

TP

vO

III.

vO (T ) 1 LC

t

ΔvO

0 T T′

TP

t

Diode turns off at T′ when I tries to go negative. 6.002 Fall 2000

Lecture 24

16

III. S is off, diode turns off Eg, no load

+ VI + –

S

C vO

– C holds vO after T′ i is zero Capacitor voltage

vO

0

6.002 Fall 2000

T′

Lecture 24

TP

t

17

III. S is off, diode turns off Eg, no load

+ VI + –

S

C vO

– C holds vO after T′ i is zero until S turns ON at TP, and cycle repeats I II III I II III … Thus, vO increases each cycle, if there is no load.

vO vO (n)

TP 2TP 3TP 6.002 Fall 2000

Lecture 24

t 18

What is vO after n cycles Æ vO(n) ? Use energy argument … (KVL tedious!) Each cycle deposits ∆E in capacitor. 1 2 Δ E = L i ( t = T ) 2 2 1 VI T 2 ΔE = 2 1 ⎛ VI T ⎞ 2 L = L⎜ ⎟ 2 ⎝ L ⎠ After n cycles, energy on capacitor 2

nVI T 2 nΔE = 2L 1 This energy must equal CvO ( n )2 2 so, or

2

2 1 nV T 2 CvO ( n ) = I 2 2L 2

nVI T 2 vO ( n ) = LC

1 ωO = LC

vO ( n ) = VI T ωO n 6.002 Fall 2000

Lecture 24

19

How to maintain vO at a given value? + VI

+ –

vO

load

–

vO

pwm

control change T

T

Tp recall

compare + vref –

2

VI T 2 ΔE = 2L

Another example of negative feedback: if if

(v (v

O O

− vref ) ↑

− vref ) ↓

6.002 Fall 2000

then T ↓ then T ↑

Lecture 24

20

6.002

CIRCUITS AND ELECTRONICS

Violating the Abstraction Barrier

6.002 Fall 2000

Lecture 25

1

Case 1: The Double Take

Problem

R

VO

“0” Æ “1” Vi

expected

observed

VO “1”

VO “1” huh?

“0”

6.002 Fall 2000

t

t “0” in forbidden region!

Lecture 25

2

(a) DC case R

VO

V1

Vi

Vi = 5V DC

VO = 5V DC V1 = 5V DC

6.002 Fall 2000

Lecture 25

very high impedance, like open circuit

OK

3

(b)

Step R

VO

V1

Vi

very high impedance, like open circuit

5V Vi b.1

0V b.3

5V

t

t=0 VO

not ok!

VO = 2.5V t=0 b.2

2T

t

5V V1 looks ok!

t=0 T 6.002 Fall 2000

Lecture 25

t 4

2.5

R

....

5

R→

Vi

characteristic impedance

instantaneous R divider finite propagation speed of signals

5V

5V

5V

2T

0

0

6.002 Fall 2000

Lecture 25

0 T

5

Question: So why did our circuits work?

5V V1 rce u o S “ tion” a n i Term

1. Look only at V1

0

O DEM

2. Keep wires short O M ire E w D l l ma s e us

3. Termination O DEM at the R add end

0

t

T

5V VO 0

0

le l Paral ation in term

5V VO 2.5V

t

0

t

More in 6.014 6.002 Fall 2000

Lecture 25

6

Case 2: The Double Dip

Problem Æ strange spikes on supply

V

0

1

1

0

OK driving a 50 Ω resistor!

0 V

driving a 50 Ω resistor!

6.002 Fall 2000

input

Why? Lecture 25

7

Drop across inductor Ldi dt

VS V

Inverter current

v inductor VS solution

1. short wires 2. low inductance wires 3. avoid big current swings

6.002 Fall 2000

Lecture 25

8

Case 3: The Double Team, or, Slower may be faster! Problem

a given chip worked, but was slow. ideal

C

actual

Let’s try speeding it up by using stronger drivers ideal

ω L

actual

Disaster! 6.002 Fall 2000

Lecture 25

9

Why?

DEMO

Consider

ok

C

R1

R0

DEMO

R2

dV α dt dV C dt

crosstalk! 6.002 Fall 2000

Lecture 25

10

How does this relate to chip?

Solution

DEMO

small

Load output!

6.002 Fall 2000

dV dt

— put cap on outputs of chip — jitter edges — slew edges Lecture 25

11

Case 4: The Double Jump

Careful abstraction violation for the better… Recall

Vo Vi

expect

Vo Vi but, observe

Vo Vi 6.002 Fall 2000

Lecture 25

12

Case 4: The Double Jump

Careful abstraction violation for the better…

5V

Vi

5V + 3V

5V 0V

6.002 Fall 2000

3V

Lecture 25

So, pullup has stronger drive as output rises

13

6.002

CIRCUITS AND ELECTRONICS

Superposition, Thévenin and Norton

6.002 Fall 2000

Lecture 3

1

Review Circuit Analysis Methods z KVL:

∑Vi = 0

loop

KCL: ∑ Ii = 0

VI

node

z Circuit composition rules z Node method – the workhorse of 6.002

KCL at nodes using V ’s referenced from ground (KVL implicit in “ (ei − e j ) G ”)

6.002 Fall 2000

Lecture 3

2

Linearity

V

+ –

R2

e J

R1

Consider

I

Write node equations –

e −V e + −I =0 R1 R2 Notice: linear in e,V , I No eV ,VI terms

6.002 Fall 2000

Lecture 3

3

Linearity

R1

Consider + –

J

V

R2

Write node equations -e −V e + −I =0 R1 R2 Rearrange -1 1  R + R e  1 2 conductance matrix

G

6.002 Fall 2000

=

I

linear in e,V , I

V + I R1

node linear sum voltages of sources

e

Lecture 3

=

S

4

Linearity Write node equations -e −V e + −I =0 R1 R2 Rearrange -1 1  R + R e  1 2 conductance matrix

G or

e=

=

linear in e,V , I

V + I R1

node linear sum voltages of sources

e

=

S

R2 RR V+ 1 2 I R1 + R2 R1 + R2

e = a1V1 + a2V2 + … + b1 I1 + b2 I 2 + …

Linear! 6.002 Fall 2000

Lecture 3

5

Linearity

6.002 Fall 2000

⇒

Homogeneity Superposition

Lecture 3

6

⇒

Linearity

Homogeneity Superposition

Homogeneity x1 x2 . .

y

.

⇓ αx1 αx2 .. .

6.002 Fall 2000

αy

Lecture 3

7

Linearity

⇒

Homogeneity Superposition

Superposition

x1a x2 a . ..

ya

x1b x2 b . ..

yb

⇓ x1a + x1b x2 a + x2 b . ..

6.002 Fall 2000

y a + yb

Lecture 3

8

Linearity

⇒

Homogeneity Superposition

Specific superposition example: V1 0

0 V2

y1

y2

⇓ V1 + 0 0 + V2

6.002 Fall 2000

y1 + y2

Lecture 3

9

Method 4: Superposition method The output of a circuit is determined by summing the responses to each source acting alone. s e c r u so t n e nd e p e ind only

6.002 Fall 2000

Lecture 3

10

i

V =0 + –

i + v

+ v

-

short

I =0

J

i

i + v

+ v

-

-

open

6.002 Fall 2000

Lecture 3

11

Back to the example Use superposition method

V

+ –

6.002 Fall 2000

e

R2

Lecture 3

J

R1

I

12

Back to the example Use superposition method V acting alone

e

R1

V

I = 0 eV =

R2

+ –

I acting alone

e

V =0

sum

J

R1 R2

R2 V R1 + R2

I

R1 R2 eI = I R1 + R2

superposition

R2 R1 R2 e = eV + eI = V+ I R1 + R2 R1 + R2 6.002 Fall 2000

Lecture 3

Voilà ! 13

Demo salt water

constant + –

?

+ –

output shows superposition

sinusoid

6.002 Fall 2000

Lecture 3

14

Yet another method…

Consider

By superposition v =

∑ α mVm + ∑ β n I n + Ri m

n

no resistance units units By setting ∀n I n = 0, ∀mVm = 0, i = 0 i = 0

i

+ v -

J

y network r a r t i N Arb resistors Vm In + – J

i

also independent of external excitement & behaves like a resistor

All ∀n I n = 0, ∀mVm = 0

independent of external excitation and behaves like a voltage “ vTH ” 6.002 Fall 2000

Lecture 3

15

Or

v = vTH + RTH i

As far as the external world is concerned (for the purpose of I-V relation), “Arbitrary network N” is indistinguishable from: RTH Thévenin equivalent network

vTH RTH

+ vTH –

+ v

J

N

i

-

open circuit voltage at terminal pair (a.k.a. port) resistance of network seen from port ( Vm ’s, I n ’s set to 0)

6.002 Fall 2000

Lecture 3

16

Method 4: The Thévenin Method J

i

N

+ v -

+ –

+ –

E

Thévenin equivalent RTH

+ vTH –

i + v

E

-

Replace network N with its Thévenin equivalent, then solve external network E. 6.002 Fall 2000

Lecture 3

17

Example: + V –

R2

J

i1 R1

I

i1 R1 RTH

+ V –

VTH

i1 =

6.002 Fall 2000

+ I –

V − VTH R1 + RTH

Lecture 3

18

VTH : VTH = IR2

RTH : RTH = R2

6.002 Fall 2000

+ VTH -

R2

+ RTH -

R2

Lecture 3

J

Example:

I

19

Graphically,

v = vTH + RTH i

i 1 RTH v vTH

“V ” OC

− I SC

Open circuit (i ≡ 0)

v = vTH

Short circuit (v ≡ 0)

− vTH i = RTH

6.002 Fall 2000

Lecture 3

VOC − I SC

20

in recitation, see text

Method 5:

The Norton Method

J + –

+ –

+ v -

IN

J

i

RTH = RN

Norton equivalent

IN =

6.002 Fall 2000

Lecture 3

VTH RTH

21

Summary „Discretize matter LMD Physics

LCA EE

„

R, I, V

Linear networks

„

Analysis methods (linear) KVL, KCL, I — V Combination rules Node method Superposition Thévenin Norton

„

Next Nonlinear analysis Discretize voltage

… 6.002 Fall 2000

Lecture 3

101100

… 22

6.002

CIRCUITS AND ELECTRONICS

The Digital Abstraction

6.002 Fall 2000

Lecture 4

1

Review z Discretize matter by agreeing to

observe the lumped matter discipline

Lumped Circuit Abstraction zAnalysis tool kit: KVL/KCL, node method, superposition, Thévenin, Norton (remember superposition, Thévenin, Norton apply only for linear circuits)

6.002 Fall 2000

Lecture 4

2

Today

Discretize value

Digital abstraction

Interestingly, we will see shortly that the tools learned in the previous three lectures are sufficient to analyze simple digital circuits

Reading: Chapter 5 of Agarwal & Lang

6.002 Fall 2000

Lecture 4

3

But first, why digital? In the past … Analog signal processing R1 V0

R2

V1 + –

V1

and V2 might represent the outputs of two sensors, for example.

+ –

V2

By superposition, V0 =

R2 R1 V1 + V2 R1 + R2 R1 + R2

If R1 = R 2 , V0 =

V1 + V2 2

The above is an “adder” circuit. 6.002 Fall 2000

Lecture 4

4

Noise Problem t

add noise on this wire

Receiver: huh?

…

noise hampers our ability to distinguish between small differences in value — e.g. between 3.1V and 3.2V.

6.002 Fall 2000

Lecture 4

5

Value Discretization Restrict values to be one of two HIGH

LOW

5V

0V

TRUE

FALSE

1

0

…like two digits

0 and 1

Why is this discretization useful? (Remember, numbers larger than 1 can be represented using multiple binary digits and coding, much like using multiple decimal digits to represent numbers greater than 9. E.g., the binary number 101 has decimal value 5.)

6.002 Fall 2000

Lecture 4

6

Digital System sender

noise VN

VS

VR

VN = 0V

receiver

VS

VR

5V “0” “1” “0” HIGH

“0” “1” “0” 5V

t

2.5V

0V

LOW

0V

t

2.5V

With noise

VS

VN = 0.2V

“0” “1” “0” 5V

“0” “1” “0”

0.2V

t

2.5V

VS

t

t

2.5V

0V 6.002 Fall 2000

Lecture 4

7

Digital System

Better noise immunity Lots of “noise margin” For “1”: noise margin 5V to 2.5V = 2.5V For “0”: noise margin 0V to 2.5V = 2.5V

6.002 Fall 2000

Lecture 4

8

Voltage Thresholds and Logic Values

5V

1

1

sender 0

1 2.5V receiver

0

0 0V

6.002 Fall 2000

Lecture 4

9

But, but, but … What about 2.5V? Hmmm… create “no man’s land” or forbidden region For example, 5V

1 sender

3V 2V

0

1

VH

forbidden region

receiver

VL

0

0V

“1”

V

“0”

0V

6.002 Fall 2000

H

Lecture 4

5V V

L 10

But, but, but …

Where’s the noise margin? What if the sender sent 1:

VH ?

Hold the sender to tougher standards! 5V 1

V 0H

1 V IH

sender

V IL

0

receiver 0

V 0L

0V

6.002 Fall 2000

Lecture 4

11

But, but, but …

Where’s the noise margin? What if the sender sent 1:

VH ?

Hold the sender to tougher standards! 5V 1

V 0H

1

sender

Noise margins

V IH

receiver

V IL

0

0

V 0L

0V “1” noise margin: V

- V

“0” noise margin:

-

6.002 Fall 2000

Lecture 4

IH V IL

0H V 0L 12

5V V 0H V IH V IL V 0L 0V

5V V 0H V IH V IL V 0L 0V

0

1

0

1

sender

t

0

1

0

1

receiver

t

Digital systems follow static discipline: if inputs to the digital system meet valid input thresholds, then the system guarantees its outputs will meet valid output thresholds. 6.002 Fall 2000

Lecture 4

13

Processing digital signals Recall, we have only two values —

1,0

Map naturally to logic: T, F Can also represent numbers

6.002 Fall 2000

Lecture 4

14

Processing digital signals Boolean Logic If X is true and Y is true Then Z is true else Z is false. Z = X AND Y

X, Y, Z are digital signals “0” , “1”

Z = X • Y Boolean equation X Y

AND gate

Z

Truth table representation: X Y Z 0 0 1 1

0 1 0 1

0 0 0 1

Enumerate all input combinations 6.002 Fall 2000

Lecture 4

15

Combinational gate abstraction „ Adheres to static discipline „ Outputs are a function of

inputs alone.

Digital logic designers do not have to care about what is inside a gate.

6.002 Fall 2000

Lecture 4

16

Demo

X

Y

Z Noise X Y

Z

Z = X • Y 6.002 Fall 2000

Lecture 4

17

Examples for recitation X

t Y

t Z

t Z = X • Y 6.002 Fall 2000

Lecture 4

18

In recitation… Another example of a gate If (A is true) OR (B is true) then C is true else C is false C = A + B A B

Boolean equation OR C

OR gate

More gates B

B Inverter

X Y

Z NAND

Z = X • Y

6.002 Fall 2000

Lecture 4

19

Boolean Identities X X X X

• 1 = X • 0 = X + 1 = 1 +0 = X

1 = 0 0 = 1 AB + AC = A • (B + C)

Digital Circuits Implement: B C

output = A + B • C B•C output

A

6.002 Fall 2000

Lecture 4

20

6.002

CIRCUITS AND ELECTRONICS

Inside the Digital Gate

6.002 Fall 2000

Lecture 5

1

Review The Digital Abstraction z Discretize value 0, 1 z Static discipline

meet voltage thresholds sender VOH VOL

receiver VIH VIL

forbidden region

Specifies how gates must be designed

6.002 Fall 2000

Lecture 5

2

Review Combinational gate abstraction outputs function of input alone satisfies static discipline

A B

C NAND

6.002 Fall 2000

Lecture 5

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

3

For example: a digital circuit A B

Demo

A⋅ B D

C D = (C ⋅ (A ⋅ B )) 3 gates here

„ A Pentium III class microprocessor is a circuit with over 4 million gates !! „ The RAW chip being built at the Lab for Computer Science at MIT has about 3 million gates. 6.002 Fall 2000

Lecture 5

4

How to build a digital gate Analogy l ik e power supply

A

(li taps

s) e h c t i ke sw

B C

if A=ON AND B=ON C has H20 else C has no H20 Use this insight to build an AND gate.

6.002 Fall 2000

Lecture 5

5

How to build a digital gate

OR gate

A C B

6.002 Fall 2000

Lecture 5

6

Electrical Analogy B

A

V + –

C

Bulb C is ON if A AND B are ON, else C is off Key: “switch” device

6.002 Fall 2000

Lecture 5

7

Electrical Analogy equivalent ckt

Key: “switch” device

in

control

C =0

in

out

C

in

out

C=1

3-Terminal device if C = 0 else

out

short circuit between in and out open circuit between in and out

For mechanical switch, control mechanical pressure 6.002 Fall 2000

Lecture 5

8

Consider RL

VOUT

IN

C

+ VS – VS =

OUT

VS RL

VOUT C

“1”

VS

VOUT C =0

Truth table for C VOUT 0 1 1 0

VS

VOUT C =1

6.002 Fall 2000

Lecture 5

9

What about? VS

Truth table for c1 c2 VO 0 0 1 0 1 1 1 0 1 1 1 0

VOUT

c1 c2

Truth table for

VS

VOUT c1

6.002 Fall 2000

c2

Lecture 5

c1 c2 VO 0 0 1 0 1 0 1 0 0 1 1 0

10

What about? can also build compound gates

VS D A

C

D = (A ⋅ B) + C

B

6.002 Fall 2000

Lecture 5

11

The MOSFET Device Metal-Oxide Semiconductor Field-Effect Transistor

drain D

G gate

≡ S source

3 terminal lumped element behaves like a switch

G : control terminal D, S : behave in a symmetric manner (for our needs) 6.002 Fall 2000

Lecture 5

12

The MOSFET Device Understand its operation by viewing it as a two-port element —

out k k c e Ch extboo l the t s interna for it ture. iG c u r t s

G

+ vGS –

D

iDS

vDS S

–

D off

G vGS < VT

G vGS ≥ VT

S

+

D iDS on S

VT ≈ 1V typically

“Switch” model (S model) of the MOSFET

6.002 Fall 2000

Lecture 5

13

Demo

Check the MOS device on a scope. i DS

+ vDS

+ vGS –

–

iDS vGS ≥ VT

vGS < VT iDS vs vDS 6.002 Fall 2000

Lecture 5

vDS

14

A MOSFET Inverter VS = 5V RL

vOUT

A

B

IN

A

B

Note the power of abstraction. The abstract inverter gate representation hides the internal details such as power supply connections, RL, GND, etc. (When we build digital circuits, the and are common across all gates!) 6.002 Fall 2000

Lecture 5

15

Example

vOUT

5V

vOUT

vIN

0V V T =1V

5V

v IN

The T1000 model laptop desires gates that satisfy the static discipline with voltage thresholds. Does out inverter qualify?

1:

0:

VOL = 0.5V

VIL = 0.9V

VOH = 4.5V

VIH = 4.1V

sender 5 4.5 V OH

0.5 0

VOL

receiver

5 4.1 0.9

0 Our inverter satisfies this. 6.002 Fall 2000

Lecture 5

1 VIH VIL

0

16

E.g.: Does our inverter satisfy the static discipline for these thresholds: VOL = 0.2V

VIL = 0.5V

VOH = 4.8V

VIH = 4.5V

yes

x VOL = 0.5V

VIL = 1.5V

VOH = 4.5V

VIH = 3.5V

6.002 Fall 2000

Lecture 5

no

17

Switch resistor (SR) model of MOSFET …more accurate MOS model D

D G

G

G S

D

vGS < VT

S

RON

vGS ≥ VT S e.g. RON = 5 KΩ

6.002 Fall 2000

Lecture 5

18

SR Model of MOSFET D

D G

G

G S

vGS < VT

S

MOSFET S model

iDS

vGS ≥ VT

RON

vGS ≥ VT S

MOSFET SR model

vGS ≥ VT iDS

vGS < VT

1 RON

vGS < VT

vDS

6.002 Fall 2000

D

vDS

Lecture 5

19

Using the SR model RL

vOUT

IN

C

+ VS – VS =

OUT

VS RL

vOUT C

“1”

Truth table for

VS RL

vOUT

C VOUT 0 1 1 0

RON C =0

VS

RL C =1

vGS ≥ VT

vOUT

RON

6.002 Fall 2000

Choose RL, RON, VS such that: V R v = S ON ≤ V OL OUT R +R L ON

Lecture 5

20

6.002

CIRCUITS AND ELECTRONICS

Nonlinear Analysis

6.002 Fall 2000

Lecture 6

1

Review Discretize matter t LCA m1 X KVL, KCL, i-v m2 X Composition rules m3 X Node method m4 X Superposition m5 X Thévenin, Norton

6.002 Fall 2000

Lecture 6

any circuit linear circuits

2

Review Discretize value t Digital abstraction X Subcircuits for given “switch” setting are linear! So, all 5 methods (m1 – m5) can be applied

VS

VS

A =1 B =1

RL

RL

C A

C RON

B

RON

SR MOSFET Model

6.002 Fall 2000

Lecture 6

3

Today Nonlinear Analysis X Analytical method based on m1, m2, m3 X Graphical method X Introduction to incremental analysis

6.002 Fall 2000

Lecture 6

4

How do we analyze nonlinear circuits, for example:

V

+ vD -

+ –

Hypothetical nonlinear D device (Expo Dweeb ☺) iD

+ vD -

D

iD

iD

iD = aebvD

a vD

0,0

(Curiously, the device supplies power when vD is negative)

6.002 Fall 2000

Lecture 6

5

Method 1: Analytical Method Using the node method,

(remember the node method applies for linear or nonlinear circuits)

vD − V + iD = 0 R iD = aebvD

2 unknowns

1 2

2 equations

Solve the equation by trial and error numerical methods

6.002 Fall 2000

Lecture 6

6

Method 2: Graphical Method Notice: the solution satisfies equations 1 and 2 iD

2

iD = aebvD

a vD

iD

V vD 1 iD = − R R

V R

1 slope = − R

V 6.002 Fall 2000

Lecture 6

vD

7

Combine the two constraints iD

V 1 R ~ 0 .4 a ¼

called “loadline” for reasons you will see later

~ 0.5

e.g.

V =1 R =1

V 1

vD

vD = 0.5V iD = 0.4 A

1 4 b =1 a=

6.002 Fall 2000

Lecture 6

8

Method 3: Incremental Analysis Motivation: music over a light beam Can we pull this off? iD

+ vD LED light intensity I D ∝ iD vI music signal

vI (t ) + –

iR

t

vI (t )

iD (t )

light

AMP iR ∝ I R light intensity IR in photoreceiver LED: Light Emitting expoDweep ☺

iR (t )

sound

nonlinear

linear problem! will result in distortion

6.002 Fall 2000

Lecture 6

9

Problem:

The LED is nonlinear

distortion iD

iD vD vD = vI

t vD t

iD

6.002 Fall 2000

vD

Lecture 6

t

10

If only it were linear … iD

iD

vD

vD t

it would’ve been ok.

What do we do? Zen is the answer … next lecture! 6.002 Fall 2000

Lecture 6

11

6.002

CIRCUITS AND ELECTRONICS

Incremental Analysis

6.002 Fall 2000

Lecture 7

1

Review

Nonlinear Analysis X Analytical method X Graphical method Today X Incremental analysis Reading: Section 4.5

6.002 Fall 2000

Lecture 7

2

Method 3: Incremental Analysis Motivation: music over a light beam Can we pull this off? iD

+ vD LED light intensity I D ∝ iD vI music signal

vI (t ) + –

iR

t

vI (t )

iD (t )

light

AMP iR ∝ I R light intensity IR in photoreceiver LED: Light Emitting expoDweep ☺

iR (t )

sound

nonlinear

linear problem! will result in distortion

6.002 Fall 2000

Lecture 7

3

Problem:

The LED is nonlinear

distortion iD

iD vD vD = vI

t vD t

iD

6.002 Fall 2000

vD

Lecture 7

t

4

Insight:

iD

small region looks linear (about VD , ID)

ID

VD

vD

DC offset or DC bias

Trick:

vI

vi (t ) + – VI

+ –

iD = I D + id + vD LED vD = VD + vd VI

6.002 Fall 2000

Lecture 7

vi 5

Result iD

id ID

vD

VD

6.002 Fall 2000

Lecture 7

vd

very small

6

Result vD = vI

vd

vD

VD

t

iD

id

iD

~linear!

ID

t

Demo 6.002 Fall 2000

Lecture 7

7

The incremental method: (or small signal method)

1. Operate at some DC offset or bias point VD, ID . 2. Superimpose small signal vd (music) on top of VD . 3. Response id to small signal vd is approximately linear. Notation:

iD = I D + id

total DC small variable offset superimposed signal

6.002 Fall 2000

Lecture 7

8

What does this mean mathematically? Or, why is the small signal response linear? nonlinear iD = f (vD )

We replaced

vD = VD + ∆vD

large DC

vd

increment about VD

using Taylor’s Expansion to expand f(vD) near vD=VD :

iD = f (VD ) + +

df (vD ) ⋅ ∆vD dvD vD =VD 1 d 2 f (v D ) 2! dvD 2 v

2

⋅ ∆vD + " D =VD

neglect higher order terms because ∆vD is small 6.002 Fall 2000

Lecture 7

9

iD ≈ f (VD ) + constant w.r.t. ∆vD

d f (v D ) ⋅ ∆vD d vD vD =VD constant w.r.t. ∆vD slope at VD, ID

We can write X : I D + ∆iD ≈ f (VD ) +

d f (v D ) ⋅ ∆ vD d vD vD =VD

equating DC and time-varying parts, I D = f (VD )

operating point

d f (v D ) ∆iD = ⋅ ∆vD d vD vD =VD constant w.r.t. ∆vD so, ∆ iD ∝ ∆vD 6.002 Fall 2000

Lecture 7

By notation, ∆ iD = id ∆ v D = vd

10

In our example,

iD = a e

bv D

From X : I D + id ≈ a e bVD + a e bVD ⋅ b ⋅ vd Equate DC and incremental terms,

I D = a ebVD

operating point aka bias pt. aka DC offset

id = a ebVD ⋅ b ⋅ vd id = I D ⋅ b ⋅ vd constant

6.002 Fall 2000

Lecture 7

small signal behavior linear!

11

Graphical interpretation operating point

I D = a ebVD

id = I D ⋅ b ⋅ vd A

slope at VD, ID

iD ID

id

B

VD

operating point vd vD

we are approximating A with B

6.002 Fall 2000

Lecture 7

12

graphically mathematically now, circuit

We saw the small signal Large signal circuit: VI

ID

+ LED VD -

+ –

I D = a ebVD

Small signal response: id = I D b vd + vd -

behaves like:

id

R=

small signal circuit:

vi

+ –

+ vd -

1 ID b

id 1 I Db Linear!

6.002 Fall 2000

Lecture 7

13

6.002

CIRCUITS AND ELECTRONICS

Dependent Sources and Amplifiers

6.002 – Fall 2002: Lecture 8

1

Review

„

Nonlinear circuits — can use the node method

„

Small signal trick resulted in linear response

Today „

Dependent sources

„

Amplifiers

Reading: Chapter 7.1, 7.2

6.002 – Fall 2002: Lecture 8

2

Dependent sources Seen previously Resistor Independent Current source

+ i + i

v

–

R v – I

v i= R

i=I

2-terminal 1-port devices New type of device: Dependent source iI i O

+ control port

f ( vI )

+

vI

vO

–

–

output port

2-port device E.g., Voltage Controlled Current Source Current at output port is a function of voltage at the input port 6.002 – Fall 2002: Lecture 8

3

Dependent Sources: Examples

Example 1: Find V + R V –

independent current source

I = I0

V = I0R

6.002 – Fall 2002: Lecture 8

4

Dependent Sources: Examples Example 2: Find V + R V –

voltage controled current source

+ R V –

K I = f (V ) = V

iI +

f (vI ) =

K vI

iO +

vI

vO

–

–

6.002 – Fall 2002: Lecture 8

5

Dependent Sources: Examples Example 2: Find V voltage controled current source

+ R V –

K I = f (V ) = V e.g. K = 10-3 Amp·Volt R = 1kΩ

K V = IR = R V or V 2 = KR or V = KR = 10 −3 ⋅ 10 3 = 1 Volt

6.002 – Fall 2002: Lecture 8

6

Another dependent source example

RL iIN

vI + –

iD

+

+

vIN

vO

–

–

e.g.

VS + –

iD = f (vIN ) iD = f (vIN ) K 2 = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise

Find vO as a function of vI .

6.002 – Fall 2002: Lecture 8

7

Another dependent source example VS RL iIN

vI + –

iD

+

+

vIN

vO

–

–

iD = f (vIN ) e.g.

iD = f (vIN ) K 2 = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise

Find vO as a function of vI .

6.002 – Fall 2002: Lecture 8

8

Another dependent source example VS RL vI vI

+ –

vO K 2 iD = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise

Find vO as a function of vI .

6.002 – Fall 2002: Lecture 8

9

Another dependent source example VS RL vI vI

+ –

vO K 2 iD = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise

KVL

− VS + iD RL + vO = 0 vO = VS − iD RL K 2 vO = VS − (vI − 1) RL 2 vO = VS

for vI ≥ 1 for vI < 1

Hold that thought

6.002 – Fall 2002: Lecture 8

10

Next, Amplifiers

6.002 – Fall 2002: Lecture 8

11

Why amplify? Signal amplification key to both analog and digital processing. Analog: AMP

IN

Input Port

OUT

Output Port

Besides the obvious advantages of being heard farther away, amplification is key to noise tolerance during communication

6.002 – Fall 2002: Lecture 8

12

Why amplify? Amplification is key to noise tolerance during communication No amplification

useful signal

1 mV

e nois

10 mV

huh?

6.002 – Fall 2002: Lecture 8

13

Try amplification e nois

AMP

not bad!

6.002 – Fall 2002: Lecture 8

14

Why amplify? Digital: Valid region 5V

5V

VIH IN VIL 0V

5V

OUT Digital System

IN

5V

VOL

OUT

V OH

VIH VIL

0V

0V

VOH

t

6.002 – Fall 2002: Lecture 8

V OL

t

0V

15

Why amplify? Digital:

Static discipline requires amplification! Minimum amplification needed: VIH VIL

6.002 – Fall 2002: Lecture 8

VOH VOL

VOH − VOL VIH − VIL

16

An amplifier is a 3-ported device, actually Power port Input port

iO

iI

+v – I

Amplifier

+ v Output – O port

We often don’t show the power port. Also, for convenience we commonly observe “the common ground discipline.” In other words, all ports often share a common reference point called “ground.”

POWER IN OUT

How do we build one? 6.002 – Fall 2002: Lecture 8

17

Remember? VS RL vI vI

+ –

vO K 2 iD = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise

KVL

− VS + iD RL + vO = 0 vO = VS − iD RL K 2 vO = VS − (vI − 1) RL 2 vO = VS

for vI ≥ 1 for vI < 1

Claim: This is an amplifier

6.002 – Fall 2002: Lecture 8

18

So, where’s the amplification? Let’s look at the vO versus vI curve. mA e.g. VS = 10V , K = 2 2 , RL = 5 kΩ V K 2 vO = VS − RL (vI − 1) 2 2 2 = 10 − ⋅10 −3 ⋅ 5 ⋅ 103 (vI − 1) 2 vO = 10 − 5 (vI − 1) vO VS

2

∆vO

1

∆vO >1 ∆v I 6.002 – Fall 2002: Lecture 8

∆vI

vI

amplification 19

Plot vO versus vI vO = 10 − 5 (vI − 1)

2

0.1 change in vI

Demo

vI

vO

0.0 1.0 1.5 2.0 2.1 2.2 2.3 2.4

10.00 10.00 8.75 5.00 4.00 2.80 1.50 ~ 0.00

1V change in vO

Gain!

Measure vO .

6.002 – Fall 2002: Lecture 8

20

One nit … vO

What happens here? 1

vI

Mathematically, K 2 vO = VS − RL (vI − 1) 2 So

is mathematically predicted behavior

6.002 – Fall 2002: Lecture 8

21

One nit … vO

K 2 vO = VS − RL (vI − 1) 2 What happens here? vI

1 However, from

iD =

K (vI − 1)2 2 VS

for vI ≥ 1

RL vO

VCCS

iD

For vO>0, VCCS consumes power: vO iD For vO<0, VCCS must supply power! 6.002 – Fall 2002: Lecture 8

22

If VCCS is a device that can source power, then the mathematically predicted behavior will be observed —

vO

K 2 i.e. vO = VS − RL (vI − 1) 2 vI

where vO goes -ve

6.002 – Fall 2002: Lecture 8

23

If VCCS is a passive device, then it cannot source power, so vO cannot go -ve. So, something must give! Turns out, our model breaks down.

K 2 iD = (vI − 1) 2 will no longer be valid when vO ≤ 0 . e.g. iD saturates (stops increasing) and we observe: Commonly

vO

1

6.002 – Fall 2002: Lecture 8

vI

24

6.002

CIRCUITS AND ELECTRONICS

MOSFET Amplifier Large Signal Analysis

6.002 Fall 2000

Lecture 9

1

Review „

Amp constructed using dependent source control a a′ port

„

DS

b output b ′ port

Dependent source in a circuit + –

a +

b

v

i = f (v )

a′ –

b′

„

Superposition with dependent sources: one way tleave all dependent sources in; solve for one independent source at a time [section 3.5.1 of the text]

„

Next, quick review of amp …

Reading: Chapter 7.3–7.7 6.002 Fall 2000

Lecture 9

2

Amp review VS RL

vO VCCS

vI

K 2 iD = (vI − 1) 2

+ –

for vI ≥ 1V = 0 otherwise vO = VS − iD RL K (vI − 1)2 2

6.002 Fall 2000

Lecture 9

3

Key device Needed: v A

B i = f (v )

voltage controlled current source

C

Let’s look at our old friend, the MOSFET …

6.002 Fall 2000

Lecture 9

4

Key device Needed: Our old friend, the MOSFET … First, we sort of lied. The on-state behavior of the MOSFET is quite a bit more complex than either the ideal switch or the resistor model would have you believe.

D G vGS < VT

D

S

S

?

G vGS ≥ VT

6.002 Fall 2000

Lecture 9

5

Graphically

Demo

+ vGS –

iDS

egio n

iDS

vGS ≥ VT

vGS < VT

vGS < VT

vDS

S MODEL

vDS

SR MODEL

6.002 Fall 2000

vDS = vGS − VT vGS 1 Saturation region

vGS 2

vGS3 ...

vGS ≥ VT

T ri o de r

iDS

v+DS –

iDS

Lecture 9

vGS < VT Cutoff

vDS

region

6

Graphically + vGS –

iDS

iDS

egio n

S MODEL

vDS

SR MODEL

6.002 Fall 2000

vGS 2

vGS3 ...

vGS < VT

Saturation region

T ri o de r

vGS ≥ VT

vDS

vDS = vGS − VT vGS 1

iDS

vGS ≥ VT

vGS < VT

v+DS –

iDS

vGS < VT

Lecture 9

vDS

when

vDS ≥ vGS − VT Notice that MOSFET behaves like a current source 7

MOSFET SCS Model When

vDS ≥ vGS − VT

the MOSFET is in its saturation region, and the switch current source (SCS) model of the MOSFET is more accurate than the S or SR model

D G vGS < VT S

D

D

G S vGS

G ≥ VT

iDS = f (vGS ) K 2 = (vGS − VT ) 2 S

6.002 Fall 2000

Lecture 9

when

vDS ≥ vGS − VT

8

Reconciling the models… iDS

iDS

vGS ≥ VT

vGS < VT

vDS

S MODEL for fun!

vGS < VT

Saturation region

vGS 2

vGS3 ...

vGS ≥ VT

T ri o de r

egio n

iDS

vDS = vGS − VT vGS 1

vDS

SR MODEL for digital designs

vGS < VT

vDS

SCS MODEL for analog designs

When to use each model in 6.002? Note: alternatively (in more advanced courses)

vDS ≥ vGS − VT vDS < vGS − VT

use SCS model use SR model

or, use SU Model (Section 7.8 of A&L)

6.002 Fall 2000

Lecture 9

9

Back to Amplifier VS vI

AMP

vO

VS RL vI

G

D S

vO K 2 iDS = (vI − VT ) 2 in saturation region

To ensure the MOSFET operates as a VCCS, we must operate it in its saturation region only. To do so, we promise to adhere to the “saturation discipline”

6.002 Fall 2000

Lecture 9

10

MOSFET Amplifier VS RL vI

G

D S

vO K 2 iDS = (vI − VT ) 2 in saturation region

To ensure the MOSFET operates as a VCCS, we must operate it in its saturation region only. We promise to adhere to the “saturation discipline.” In other words, we will operate the amp circuit such that vGS ≥ VT and vDS ≥ vGS – VT vO ≥ vI – vT 6.002 Fall 2000

Lecture 9

at all times.

11

Let’s analyze the circuit First, replace the MOSFET with its SCS model.

VS RL

vO G

vGS = vI

+ –

+ vI –

6.002 Fall 2000

D

iDS

S

Lecture 9

K 2 = (vI − VT ) 2

A

for vO ≥ vI − VT

12

Let’s analyze the circuit VS

RL

vO G

vGS = vI

+ –

+ vI –

D

iDS =

K (vI − VT )2 2

A

for vO ≥ vI − VT

S

(vO = vDS in our example)

1

Analytical method: vO vs vI vO = VS − iDS RL B K 2 or vO = VS − (vI − VT ) RL for vI ≥ VT 2 vO ≥ vI − VT

vO = VS

6.002 Fall 2000

vI < VT (MOSFET turns off) for

Lecture 9

13

Graphical method vO vs vI K 2 From A : iDS = (vI − VT ) , 2 vO ≥ vI − VT 2

for

⇓ 2iDS vO ≥ K ⇓ K 2 iDS ≤ vO 2

B : iDS

6.002 Fall 2000

VS v0 = − RL RL

Lecture 9

14

2

Graphical method vO vs vI K 2 K 2 A : iDS = (vI − VT ) , for iDS ≤ vO 2 2 VS vO = − i B : DS RL RL

iDS VS RL

iDS B

Lo ad

K 2 ≤ vO 2 A

li n e

vI = vGS

VS Constraints 6.002 Fall 2000

A

and

B

Lecture 9

vO

must be met

15

2

Graphical method vO vs vI

iDS VS RL

iDS ≤

K 2 vO 2 A

B

vI

VI

I DS

VO

VS

vO

Constraints A and B must be met. Then, given VI, we can find VO, IDS .

6.002 Fall 2000

Lecture 9

16

Large Signal Analysis of Amplifier (under “saturation discipline”) 1

vO versus vI

2

Valid input operating range and valid output operating range

6.002 Fall 2000

Lecture 9

17

Large Signal Analysis vO versus vI

1

vO

K 2 VS − (vI − VT ) RL 2

VS

VT

6.002 Fall 2000

vO = vI − VT gets into triode region vI

Lecture 9

18

Large Signal Analysis What are valid operating ranges under the saturation discipline?

2

Our Constraints

vI ≥ VT

iDS ≤

vO ≥ vI − VT

iDS VS RL

iDS

K 2 vO 2

K 2 ≤ vO 2

K 2 iDS = (vI − VT ) 2 vI v V iDS = S − O RL RL

VS

? 6.002 Fall 2000

vO

vI = VT vO = VS and iDS = 0 Lecture 9

19

Large Signal Analysis 2

What are valid operating ranges under the saturation discipline?

iDS

iDS

K 2 ≤ vO 2

K 2 iDS = (vI − VT ) 2 vI VS vO iDS = − RL RL vO − 1 + 1 + 2 KRLVS vI = VT + KRL − 1 + 1 + 2 KRLVS vO = KRL VS vO iDS = − RL RL 6.002 Fall 2000

Lecture 9

vI = VT vO = VS and iDS = 0

20

Large Signal Analysis Summary 1

vO versus vI vO = VS −

2

K (vI − VT )2 RL 2

Valid operating ranges under the saturation discipline? Valid input range:

vI : VT

to

− 1 + 1 + 2 KRLVS VT + KRL

corresponding output range:

vO : VS to

6.002 Fall 2000

− 1 + 1 + 2 KRLVS KRL

Lecture 9

21