16 Bit Counter

 16 Bit Counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sixteenbitcounter is Port ( j : in std_logic_vector(15 downto 0); k : in std_logic_vector(15 downto 0); reset : in std_logic; clk : in std_logic; q : inout std_logic_vector(15 downto 0); qbar : inout std_logic_vector(15 downto 0)); end sixteenbitcounter; architecture Behavioral of sixteenbitcounter is component jkff port(reset,clk,j,k : in std_logic; q,qbar : inout std_logic); end component; begin a1: jkff port map(reset,clk,j(0),k(0),q(0),qbar(0)); a2: jkff port map(reset,q(0),j(1),k(1),q(1),qbar(1)); a3: jkff port map(reset,q(1),j(2),k(2),q(2),qbar(2)); a4: jkff port map(reset,q(2),j(3),k(3),q(3),qbar(3)); a5: jkff port map(reset,q(3),j(4),k(4),q(4),qbar(4)); a6: jkff port map(reset,q(4),j(5),k(5),q(5),qbar(5)); a7: jkff port map(reset,q(5),j(6),k(6),q(6),qbar(6)); a8: jkff port map(reset,q(6),j(7),k(7),q(7),qbar(7)); a9: jkff port map(reset,q(7),j(8),k(8),q(8),qbar(8)); a10: jkff port map(reset,q(8),j(9),k(9),q(9),qbar(9)); a11: jkff port map(reset,q(9),j(10),k(10),q(10),qbar(10)); a12: jkff port map(reset,q(10),j(11),k(11),q(11),qbar(11)); a13: jkff port map(reset,q(11),j(12),k(12),q(12),qbar(12)); a14: jkff port map(reset,q(12),j(13),k(13),q(13),qbar(13)); a15: jkff port map(reset,q(13),j(14),k(14),q(14),qbar(14)); a16: jkff port map(reset,q(14),j(15),k(15),q(15),qbar(15)); end Behavioral;

--------------------------------- SUB PROGRAMME – JK FF ------------------------------------

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j : in std_logic; k : in std_logic; clk : in std_logic; reset : in std_logic; q : inout std_logic; qbar : inout std_logic); end jkff; architecture Behavioral of jkff is begin process(clk,reset) begin if reset='0' then q<= '0'; elsif clk='0' and clk'event then q<= (j and (not(q)) ) or ( (not j) and q); end if; end process; qbar<= not q; end Behavioral;

Device utilization summary:Selected Device : v50bg256-4 Number of Slices: 19 out of 768 2% Number of Slice Flip Flops: 16 out of 1536 1% Number of 4 input LUTs: 33 out of 1536 2% Number of bonded IOBs: 49 out of 184 26% Number of GCLKs: 1 out of 4 25%

TIMING REPORT:-

Clock Information: -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ a15_q:Q | NONE |1 | a14_q:Q | NONE |1 | a13_q:Q | NONE |1 | a12_q:Q | NONE |1 | a3_q:Q | NONE |1 | a11_q:Q | NONE |1 | clk | BUFGP |1 | a10_q:Q | NONE |1 | a9_q:Q | NONE |1 | a2_q:Q | NONE |1 | a8_q:Q | NONE |1 | a4_q:Q | NONE |1 | a7_q:Q | NONE |1 | a6_q:Q | NONE |1 | a1_q:Q | NONE |1 | a5_q:Q | NONE |1 | -----------------------------------+------------------------+-------+

Timing Summary:Speed Grade: -4 Minimum period: 4.635ns (Maximum Frequency: 215.750MHz) Minimum input arrival time before clock: 3.757ns Maximum output required time after clock: 10.787ns Maximum combinational path delay: No path found

Timing Detail:All values displayed in nanoseconds (ns) ------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'a15_q:Q' Delay: 4.503ns (Levels of Logic = 1) Source: a16_q (FF) Destination: a16_q (FF) Source Clock: a15_q:Q falling Destination Clock: a15_q:Q falling

Data Path: a16_q to a16_q Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDC_1:C->Q 3 1.372 1.628 a16_q (a16_q) LUT2_L:I1->LO 1 0.738 0.000 a16__n00001 (a16__n0000) FDC_1:D 0.765 a16_q ---------------------------------------Total 4.503ns (2.875ns logic, 1.628ns route) (63.8% logic, 36.2% route) ------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'a14_q:Q' Delay: 4.635ns (Levels of Logic = 1) Source: a15_q (FF) Destination: a15_q (FF) Source Clock: a14_q:Q falling Destination Clock: a14_q:Q falling Data Path: a15_q to a15_q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDC_1:C->Q 4 1.372 1.760 a15_q (a15_q) LUT2_L:I1->LO 1 0.738 0.000 a15__n00001 (a15__n0000) FDC_1:D 0.765 a15_q ---------------------------------------Total 4.635ns (2.875ns logic, 1.760ns route) (62.0% logic, 38.0% route) ------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'a13_q:Q' Delay: 4.635ns (Levels of Logic = 1) Source: a14_q (FF) Destination: a14_q (FF) Source Clock: a13_q:Q falling Destination Clock: a13_q:Q falling

SAME FOR OTHER PATH. FOR A14 to A0. Total memory usage is 54348 kilobytes.

RTL Schematic:-