Z80 Reference

Complete Z80 OP-Code Reference Devin Gardner, 29th April 2000 email: [email protected] LATEX formatting by David Sinclair Check the end of the document for explanations of abbreviations used below.

Mnemonic

Clck

Siz

SZJPNC

Op-Code

ADC A,r ADC A,N ADC A,(HL) ADC A,(IX+N) ADC A,(IY+N) ADC HL,BC ADC HL,DE ADC HL,HL ADC HL,SP ADD A,r ADD A,N ADD A,(HL) ADD A,(IX+N) ADD A,(IY+N) ADD HL,BC ADD HL,DE ADD HL,HL ADD HL,SP ADD IX,BC ADD IX,DE ADD IX,IX ADD IX,SP ADD IY,BC ADD IY,DE ADD IY,IY ADD IY,SP AND r AND N AND (HL) AND (IX+N) AND (IY+N) BIT b,r BIT b,(HL) BIT b,(IX+N) BIT b,(IY+N) CALL NN CALL C,NN CALL NC,NN CALL M,NN CALL P,NN CALL Z,NN CALL NZ,NN CALL PE,NN CALL PO,NN CCF

4 7 7 19 19 15 15 15 15 4 7 7 19 19 11 11 11 11 15 15 15 15 15 15 15 15 4 7 7 19 19 8 12 20 20 17 17/1 17/1 17/1 17/1 17/1 17/1 17/1 17/1 4

1 2 1 3 3 2 2 2 2 1 2 1 3 3 1 1 1 1 2 2 2 2 2 2 2 2 1 2 1 3 3 2 2 4 4 3 3 3 3 3 3 3 3 3 1

***V0*

88+rb CE XX 8E DD 8E XX FD 8E XX ED 4A ED 5A ED 6A ED 7A 80+rb C6 XX 86 DD 86 XX FD 86 XX 09 19 29 39 DD 09 DD 19 DD 29 DD 39 FD 09 FD 19 FD 29 FD 39 A0+rb E6 XX A6 DD A6 XX FD A6 XX CB 40+8*b+rb CB 46+8*b DD CB XX 46+8*b FD CB XX 46+8*b CD XX XX DC XX XX D4 XX XX FC XX XX F4 XX XX CC XX XX C4 XX XX EC XX XX E4 XX XX 3F

**?V0*

***V0*

?0*

?0*

?0*

***P00

?*1?0

 

?0*

Description

A←A+s+CY

Add with Carry

HL←HL+ss+CY

Add (8-bit)

A←A+s

Add (16-bit)

HL←HL+ss

Add (IX register)

IX←IX+pp

Add (IY register)

IY←IY+rr

Logical AND

A← A ∧ s

Test Bit

m∧2b

Unconditional Call Conditional Call

Complement Carry Flag 1

Notes

Add with Carry

(SP)←PC,PC←nn If Carry = 1 If Carry = 0 If Sign = 1 (negative) If Sign = 0 (positive) If Zero = 1 (ans.=0) If Zero = 0 (non-zero) If Parity = 1 (even) If Parity = 0 (odd) CY ← CY −

Mnemonic

Clck

Siz

SZJPNC

CP r CP N CP (HL) CP (IX+N) CP (IY+N) CPD CPDR CPI CPIR CPL DAA DEC A DEC B DEC C DEC D DEC E DEC H DEC L DEC (HL) DEC (IX+N) DEC (IY+N) DEC BC DEC DE DEC HL DEC SP DEC IX DEC IY DI DJNZ $N+2 EI EX (SP),HL EX (SP),IX EX (SP),IY EX AF,AF' EX DE,HL EXX HALT IM 0 IM 1 IM 2 IN A,(N) IN (C) IN A,(C) IN B,(C) IN C,(C) IN D,(C) IN E,(C) IN H,(C) IN L,(C)

4 7 7 19 19 16 21/1 16 21/1 4 4 4 4 4 4 4 4 4 11 23 23 6 6 6 6 10 10 4 13/8 4 19 23 23 4 4 4 4 8 8 8 11 12 12 12 12 12 12 12 12

1 2 1 3 3 2 2 2 2 1 1 1 1 1 1 1 1 2 1 3 3 1 1 1 1 2 2 1 1 1 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2

***V1*

****1 ****1 ****1 ****1 11 ***P* ***V1



      ******      ***P0 ***P0

Op-Code

B8+rb FE XX BE DD BE FD BE ED A9 ED B9 ED A1 ED B1 2F 27 3D 05 0D 15 1D 25 2D 35 DD 35 FD 35 0B 1B 2B 3B DD 2B FD 2B F3 10 XX FB E3 DD E3 FD E3 08 EB D9 76 ED 46 ED 56 ED 5E DB XX ED 70 ED 78 ED 40 ED 48 ED 50 ED 58 ED 60 ED 68

Description

XX XX

XX XX

Compare A-s

Compare and Decrement Compare, Dec., Repeat Compare and Increment Compare, Inc., Repeat Complement Decimal Adjust Acc. Decrement (8-bit)

A−(HL),HL←HL−1,BC←BC−1 CPD until A=(HL)or BC=0 A−(HL),HL←HL+1,BC←BC−1 CPI until A=(HL)or BC=0 A←A A←BCD format (dec.) s←s−1

Decrement (16-bit)

ss←ss−1

Decrement

xx←xx−1

Disable Interrupts Dec.,Jump Non-Zero Enable Interrupts Exchange

Exchange Halt Interrupt Mode Input Input† Input

2

Notes

Compare

B←B−1 til B=0,PC←PC+e (SP)↔HL (SP)↔xx AF↔AF' DE↔HL qq↔qq' (except AF) (n=0,1,2) A←(n) (Unsupported) r←(C)

Mnemonic

Clck

Siz

SZJPNC

INC A INC B INC C INC D INC E INC H INC L INC BC INC DE INC HL INC SP INC IX INC IY INC (HL) INC (IX+N) INC (IY+N) IND INDR INI INIR JP $NN JP (HL) JP (IX) JP (IY) JP C,$NN JP NC,$NN JP M,$NN JP P,$NN JP Z,$NN JP NZ,$NN JP PE,$NN JP PO,$NN JR $N+2 JR C,$N+2 JR NC,$N+2 JR Z,$N+2 JR NZ,$N+2 LD I,A LD R,A LD A,I LD A,R LD A,r LD A,N LD A,(BC) LD A,(DE) LD A,(HL) LD A,(IX+N) LD A,(IY+N) LD A,(NN) LD B,r LD B,N LD B,(HL) LD B,(IX+N) LD B,(IY+N)

4 4 4 4 4 4 4 6 6 6 6 10 10 11 23 23 16 21/1 16 21/1 10 4 8 8 10/1 10/1 10/1 10/1 10/1 10/1 10/1 10/1 12 12/7 12/7 12/7 12/7 9 9 9 9 4 7 7 7 7 19 19 13 4 7 7 19 19

1 1 1 1 1 1 1 1 1 1 1 2 2 1 3 3 2 2 2 2 3 1 2 2 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 1 2 1 1 1 3 3 3 1 2 1 3 3

***V0



 ***V0 ***V0 ?*??1 ?1??1 ?*??1 ?1??1    

 

 **0*0 

Op-Code

3C 04 0C 14 1C 24 2C 03 13 23 33 DD 23 FD 23 34 DD 34 FD 34 ED AA ED BA ED A2 ED B2 C3 XX E9 DD E9 FD E9 DA XX D2 XX FA XX F2 XX CA XX C2 XX EA XX E2 XX 18 XX 38 XX 30 XX 28 XX 20 XX ED 47 ED 4F ED 57 ED 5F 78+rb 3E XX 0A 1A 7E DD 7E FD 7E 3A XX 40+rb 06 XX 46 DD 46 FD 46

Description

XX XX

XX

XX XX XX XX XX XX XX XX

XX XX XX

XX XX

3

Notes

Increment (8-bit)

r←r+1

Increment (16-bit)

ss←ss+1

Increment

xx←xx+1

Increment (indirect) Increment

(HL)←(HL)+1 (xx+d)←(xx+d)+1

Input and Decrement Input, Dec., Repeat Input and Increment Input, Inc., Repeat Unconditional Jump Unconditional Jump Unconditional Jump

(HL)←(C),HL←HL−1,B←B−1 IND until B=0 (HL)←(C),HL←HL+1,B←B−1 INI until B=0 PC←nn PC←(HL) PC←(xx)

Conditional Jump

Relative Jump Cond. Relative Jump

If Carry = 1 If Carry = 0 If Sign = 1 (negative) If Sign = 0 (positive) If Zero = 1 (ans.= 0) If Zero = 0 (non-zero) If Parity = 1 (even) If Parity = 0 (odd) PC←PC+e If cc JR(cc=C,NC,NZ,Z)

Load†

dst←src

Load†

dst←src

Load (8-bit)

dst←src

Mnemonic

Clck

Siz

LD C,r LD C,N LD C,(HL) LD C,(IX+N) LD C,(IY+N) LD D,r LD D,N LD D,(HL) LD D,(IX+N) LD D,(IY+N) LD E,r LD E,N LD E,(HL) LD E,(IX+N) LD E,(IY+N) LD H,r LD H,N LD H,(HL) LD H,(IX+N) LD H,(IY+N) LD L,r LD L,N LD L,(HL) LD L,(IX+N) LD L,(IY+N) LD BC,(NN) LD BC,NN LD DE,(NN) LD DE,NN LD HL,(NN) LD HL,NN LD SP,(NN) LD SP,HL LD SP,IX LD SP,IY LD SP,NN LD IX,(NN) LD IX,NN LD IY,(NN) LD IY,NN LD (HL),r LD (HL),N LD (BC),A LD (DE),A LD (NN),A LD (NN),BC LD (NN),DE LD (NN),HL LD (NN),IX LD (NN),IY LD (NN),SP LD (IX+N),r LD (IX+N),N LD (IY+N),r LD (IY+N),N LDD LDDR LDI LDIR

4 7 7 19 19 4 7 7 19 19 4 7 7 19 19 4 7 7 19 19 4 7 7 19 19 20 10 20 10 20 10 20 6 10 10 10 20 14 20 14 7 10 7 7 13 20 20 16 20 20 20 19 19 19 19 16 21/1 16 21/1

1 2 1 3 3 1 2 1 3 3 1 2 1 3 3 1 2 1 3 3 1 2 1 3 3 4 3 4 3 3 3 4 1 2 2 3 4 4 4 4 1 2 1 1 3 4 4 3 4 4 4 3 4 3 4 2 2 2 2

SZJPNC





0*0 000 0*0 000

Op-Code

48+rb 0E XX 4E DD 4E XX FD 4E XX 50+rb 16 XX 56 DD 56 XX FD 56 XX 58+rb 1E XX 5E DD 5E XX FD 5E XX 60+rb 26 XX 66 DD 66 XX FD 66 XX 68+rb 2E XX 6E DD 6E XX FD 6E XX ED 4B XX 01 XX XX ED 5B XX 11 XX XX 2A XX XX 21 XX XX ED 7B XX F9 DD F9 FD F9 31 XX XX DD 2A XX DD 21 XX FD 2A XX FD 21 XX 70+rb 36 XX 02 12 32 XX XX ED 43 XX ED 53 XX 22 XX XX DD 22 XX FD 22 XX ED 73 XX DD 70+rb DD 36 XX FD 70+rb FD 36 XX ED A8 ED B8 ED A0 ED B0

Description

XX

Notes

Load (16-bit)

dst←src

Load (Indirect)

dst←src

Load and Decrement Load, Dec., Repeat Load and Increment Load, Inc., Repeat

(DE)←(HL),HL←HL−1,# LDD until BC=0 (DE)←(HL),HL←HL+1,# LDI until BC=0

XX

XX

XX XX XX XX

XX XX XX XX XX XX XX XX XX

4

Mnemonic

Clck

Siz

SZJPNC

Op-Code

NEG NOP OR r OR N OR (HL) OR (IX+N) OR (IY+N) OUT (N),A OUT (C),0 OUT (C),A OUT (C),B OUT (C),C OUT (C),D OUT (C),E OUT (C),H OUT (C),L OUTD OTDR OUTI OTIR POP AF POP BC POP DE POP HL POP IX POP IY PUSH AF PUSH BC PUSH DE PUSH HL PUSH IX PUSH IY RES b,r RES b,(HL) RES b,(IX+N) RES b,(IY+N) RET RET C RET NC RET M RET P RET Z RET NZ RET PE RET PO RETI RETN

8 4 4 7 7 19 19 11 12 12 12 12 12 12 12 12 16 21/1 16 21/1 10 10 10 10 14 14 11 11 11 11 15 15 8 15 23 23 10 11/5 11/5 11/5 11/5 11/5 11/5 11/5 11/5 14 14

2 1 1 2 1 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 1 1 1 1 2 2 2 2 4 4 1 1 1 1 1 1 1 1 1 2 2

***V1*  ***P00

ED 44 00 B0+rb F6 XX B6 DD B6 XX FD B6 XX D3 XX ED 71 ED 79 ED 41 ED 49 ED 51 ED 59 ED 61 ED 69 ED AB ED BB ED A3 ED B3 F1 C1 D1 E1 DD E1 FD E1 F5 C5 D5 E5 DD E5 FD E5 CB 80+8*b+rb CB 86+8*b DD CB XX 86+8*b FD CB XX 86+8*b C9 D8 D0 F8 F0 C8 C0 E8 E0 ED 4D ED 45

  

?*??1 ?1??1 ?*??1 ?1??1 ******   

      

 

Description

A← −A

Output Output† Output

(n)←A (Unsupported) (C)←r

Output and Decrement Output, Dec., Repeat Output and Increment Output, Inc., Repeat Pop

(C)←(HL),HL←HL−1,B←B−1 OUTD until B=0 (C)←(HL),HL←HL+1,B←B−1 OUTI until B=0 qq←(SP)+

Pop

xx←(SP)+

Push

−

Push

−

Reset bit

m=m∧¬2b

Return Conditional Return

PC←(SP)+ If Carry = 1 If Carry = 0 If Sign = 1 (negative) If Sign = 0 (positive) If Zero = 1 (ans.=0) If Zero = 0 (non-zero) If Parity = 1 (even) If Parity = 0 (odd) PC←(SP)+ PC←(SP)+

Return from Interrupt Return from NMI

5

Notes

Negate No Operation Logical inclusive OR

A ← A∨s

(SP)←qq

(SP)←xx

Mnemonic

RLA RL r RL (HL) RL (IX+N) RL (IY+N) RLCA RLC r RLC (HL) RLC (IX+N) RLC (IY+N) RLD RRA RR r RR (HL) RR (IX+N) RR (IY+N) RRCA RRC r RRC (HL) RRC (IX+N) RRC (IY+N) RRD RST 0 RST 08H RST 10H RST 18H RST 20H RST 28H RST 30H RST 38H SBC r SBC A,N SBC (HL) SBC A,(IX+N) SBC A,(IY+N) SBC HL,BC SBC HL,DE SBC HL,HL SBC HL,SP SCF SET b,r SET b,(HL) SET b,(IX+N) SET b,(IY+N) SLA r SLA (HL) SLA (IX+N) SLA (IY+N) SRA r SRA (HL) SRA (IX+N) SRA (IY+N)

Clck

Siz

SZJPNC

Op-Code

4 8 15 23 23 4 8 15 23 23 18 4 8 15 23 23 4 8 15 23 23 18 11 11 11 11 11 11 11 11 4 7 7 19 19 15 15 15 15 4 8 15 23 23 8 15 23 23 8 15 23 23

1 2 2 4 4 1 2 2 4 4 2 1 2 2 4 4 1 2 2 4 4 2 1 1 1 1 1 1 1 1 1 2 1 3 3 2 2 2 2 1 2 2 4 4 2 2 4 4 2 2 4 4

00* **0P0*

17 CB 10+rb CB 16 DD CB XX 16 FD CB XX 16 07 CB 00+rb CB 06 DD CB XX 06 FD CB XX 06 ED 6F 1F CB 18+rb CB 1E DD CB XX 1E FD CB XX 1E 0F CB 08+rb CB 0E DD CB XX 0E FD CB XX 0E ED 67 C7 CF D7 DF E7 EF F7 FF 98+rb DE XX 9E DD 9E XX FD 9E XX ED 42 ED 52 ED 62 ED 72 37 CB C0+8*b+rb CB C6+8*b DD CB XX C6+8*b FD CB XX C6+8*b CB 20+rb CB 26 DD CB XX 26 FD CB XX 26 CB 28+rb CB 2E DD CB XX 2E FD CB XX 2E

00* **0P0*

**0P0 00* **0P0*

00* **0P0*

**0P0 

***V1*

**?V1*

001 

**0P0*

**0P0*

Description

6

Notes

Rotate Left Acc. Rotate Left

A←{CY,A}⇐ m←{CY,m}⇐

Rotate Left Cir. Acc. Rotate Left Circular

A← A ⇐ m← m ⇐

Rotate Left 4 bits Rotate Right Acc. Rotate Right

{A,(HL)}← {A,(HL)} ⇐## A←⇒{CY,A} m←⇒{CY,sm}

Rotate Right Cir.Acc. Rotate Right Circular

A←⇒A m←⇒m

Rotate Right 4 bits Restart

{A,(HL)} ←⇒{A,(HL)}## (p←0H,8H,10H,...,38H)

Subtract with Carry

A←A−s−CY

Subtract with Carry

HL←HL−ss−CY

Set Carry Flag Set bit

CY←1 m← m ∨ 2 b

Shift Left Arithmetic

m←m*2

Shift Right Arith.

m←m/2

Mnemonic

SLL SLL SLL SLL SRL SRL SRL SRL SUB SUB SUB SUB SUB XOR XOR XOR XOR XOR

r (HL) (IX+N) (IY+N) r (HL) (IX+N) (IY+N) r N (HL) (IX+N) (IY+N) r N (HL) (IX+N) (IY+N)

Clck Siz SZHPNC Op-Code b r rb

Clck

Siz

SZJPNC

8 15 23 23 8 15 23 23 4 7 7 19 19 4 7 7 19 19

2 2 4 4 2 2 4 4 1 2 1 3 3 1 2 1 3 3

**0P0*

**0P0*

***V1*

***P00

Op-Code

CB 30+rb CB 36 DD CB XX FD CB XX CB 38+rb CB 3E DD CB XX FD CB XX 90+rb D6 XX 96 DD 96 XX FD 96 XX A8+rb EE XX AE DD AE XX FD AE XX

Description

36 36 3E 3E

Notes

Shift Left Logical*

m←{0,m,CY}⇐ (SLL instructions are Unsupported)

Shift Right Logical

m←⇒{0,m,CY}

Subtract

A←A−s

Logical Exclusive OR

A←A×s

The time it takes to execute the instruction in CPU cycles. How many bytes the instruction takes up in a program. How the different bits of the Flag byte (the F in the AF register) are affected. Check the graph below this for more. The instruction’s equivalent in hexadecimal. A bit. It can be 0-7. Increase the last byte of the OP-code with 8*b. Used in SET, BIT and RES. A register. It can be A,B,C,D,E,H, or L. Add this to last byte of OP-code:

Reg A B C D E H L (HL)

Regbits 7 0 1 2 3 4 5 6

= = = = = = = =

In “LD (IX+N),r” and “LD (IY+N),r” you add these to the byte before the last. If there are two numbers given for Clock, then the highest is when the jump is taken, the lowest is when it skips the jump. † For unsupported instructions, use the hexadecimal OP-Codes with the assembler instruction “.db”

EX: SLL (HL) instead of this, use:

.db $CB,$36

7

F -*01? S S Z Z HC H P/V P N N CY C n nn e (nn) (xx+d) r (rr) b p A B C D E AF BC DE HL F I IX IY PC R SP b cc d dst e m n nn pp qq qq
r rr s src ss xx + - * / ∧ ¬ ∨ × ⇐ ⇒

( ) ( )+ −( ) { } # ## = ← ↔

Flag unaffected/affected/reset/set/unknown Sign flag (Bit 7) Zero flag (Bit 6) Half carry flag (Bit 4) Parity/Overflow flag (Bit 2,V=overflow) Add/Subtract flag (Bit 1) Carry flag (Bit 0) Immediate addressing Immediate extended addressing Relative addressing (PC=PC+2+offset) Extended addressing Indexed addressing Register addressing Register indirect addressing Implied addressing Bit addressing Modified page zero addressing (see RST) Registers (8-bit) Register pairs(16-bit) Flag register(8-bit) Interrupt page address register(8-bit) Index registers(16-bit) Program Counter register(16-bit) Memory Refresh register Stack Pointer register(16-bit) One bit (0 to 7) Condition (C,M,NC,NZ,P,PE,PO,Z) One-byte expression (-128 to +127) Destination s, ss, (BC), (DE), (HL), (nn) One-byte expression (-126 to +129) Any register r, (HL) or (xx+d) One-byte expression (0 to 255) Two-byte expression (0 to 65535) Register pair BC, DE, IX or SP Register pair AF, BC, DE or HL Alternative register pair AF, BC, DE or HL Register A, B, C, D, E, H or L Register pair BC, DE, IY or SP Any register r, value n, (HL) or (xx+d) Source s, ss, (BC), (DE), (HL), nn, (nn) Register pair BC, DE, HL or SP Index register IX or IY Add/subtract/multiply/divide Logical AND/NOT/inclusive OR/exclusive OR Rotate left/right Indirect addressing Indirect addressing auto-increment/decrement Combination of operands Also BC=BC-1,DE=DE-1 Only lower 4 bits of accumulator A used Equality/Assignment/Swap values

8