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All digital PLL for RF transmitter Liangge Xu, Jukka-Pekka Pöyhtäri, Saska Lindfors Electronic Circuit Design Laboratory Helsinki University of Technology
CROPS Workshop, Trondheim 19.-20. 9. 2006
1
Outline
Introduction All digital PLL (ADPLL) Key building blocks
Gain normalization block Digitally-controlled oscillator (DCO) Time-to-digital converter (TDC) Loop filter
Implementation results Conclusions
2
Introduction
Traditional RF transmitters are based on charge-pump PLL’s
analog intensive circuit technology and design flow
3
All digital PLL (ADPLL)
All digital PLL (ADPLL) as a new solution for RF transmitters
Architecture first proposed by TI All building blocks have digital interfaces loop circuitry implemented in a fully digital manner 4
All digital PLL (ADPLL)
5
All digital PLL (ADPLL)
PLL transverse three modes of operation during settling
PVT-calibration mode : to calibrate large frequency uncertainty due to process-voltage-temperature (PVT) variations Acquisition mode : to acquire the requested operational channel Tracking mode : to track the frequency reference and perform data modulation
6
All digital PLL (ADPLL)
Two-point modulation employed for data modulation
Truly wide-band modulation
7
Gain normalization block
8
Gain normalization block
Normalized DCO has unity gain in terms of reference frequency DCO gain continuously tracked and calibrated during modulation phase with a simple hardware implemented LMS algorithm
9
Digitally controlled oscillator (DCO)
10
Digitally controlled oscillator (DCO)
A digital equivalent of highly linear VCO with wide dynamic frequency range
Feasible dynamic range >800MHz @2.4GHz center frequency
DCO as a system includes a DCO ASIC cell with the tightly coupled peripheral digital circuitry
11
Digitally controlled oscillator (DCO)
DCO core is a differential LC tank oscillator Digital control realized by switching capacitance devices
12
Digitally controlled oscillator (DCO)
DCO core implementation
PVT bank uses switched fringe capacitors Acquisition bank and tracking bank use MOS varactors Cross-coupled NMOS gain stage as negative resistance Digital control for both frequency tuning and current biasing
13
DCO interface logic Dynamic element matching (DEM) to improve linearity in digital-to-frequency conversion
Sigma-delta modulation to enhance frequency resolution
14
DCO interface logic
15
Time-to-digital converter (TDC)
16
Time-to-digital converter (TDC)
TI architecture
Timing critical paths
Our architecture 17
Time-to-digital converter (TDC)
18
Time-to-digital converter (TDC)
The TDC is to give the fractional part of a fixed-point representation of the DCO output frequency
19
Time-to-digital converter (TDC)
TI architecture
Architecture we use 20
Loop filter
21
Loop filter
Digital Low-pass filter with configurable two branches
Unconditional stable 4th order cascade-form IIR filter as the main branch Integral accumulator branch to further suppress the DCO flicker noise
22
Implementation results Input to DCO PVT bank
PLL total settling time about 15us with 26MHz reference clock
about 1us used in PVT mode about 4us used in ACQ mode about 10us for tracking mode settling
155 150 145 dp
140 135 130 0
100
200
300
400
500
600
500
600
500
600
Input to DCO acquisition bank 134
Initial synthesis results (excluding DCO and TDC core) using 65nm technology
Cell area : approx. 0.05 mm2 Cell count : approx. 10,000 Total dynamic power : approx. 17mW Cell leakage power : approx. 0.18mW
130 128 126
0
100
200
300
400
Input to DCO tracking bank 138 136 dt (dti+dtf)
da
132
134 132 130 128 126
0
100
200
300 400 CKR clock cycle
23
Implementation results
TDC core implementation results (after first layout)
Area ~0.001mm², power consumption ~2mW, time resolution ~18-20 ps
DCO core implementation results (after first layout)
Occupied area : 200umX320um Frequency tuning range : approx. 2.3~2.6GHz Phase noise : 127dBc @ 1MHz relative frequency with 6mA biasing current 24
Implementation results
DCO core layout
25
Conclusions
An ADPLL architecture has been presented Our implementation status
Initial RTL synthesis for the digital logic Initial layout for the DCO core Initial layout for the TDC core
Next step in implementation
More iterations of RTL synthesis for further optimization Layout of the digital logic Optimization of TDC and DCO core layout
26
References [1] R. B. Staszewski et al., “A first digitally controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications, ” IEEE 2003 [2] R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE 2004 [3] R. B. Staszewski et al., “All-digital PLL and transmitter for mobile phones,” IEEE 2005 [4] R. B. Staszewski et al., “All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” IEEE 2005
27
CROPS Workshop, Trondheim 19.-20. 9. 2006
1
Outline
Introduction All digital PLL (ADPLL) Key building blocks
Gain normalization block Digitally-controlled oscillator (DCO) Time-to-digital converter (TDC) Loop filter
Implementation results Conclusions
2
Introduction
Traditional RF transmitters are based on charge-pump PLL’s
analog intensive circuit technology and design flow
3
All digital PLL (ADPLL)
All digital PLL (ADPLL) as a new solution for RF transmitters
Architecture first proposed by TI All building blocks have digital interfaces loop circuitry implemented in a fully digital manner 4
All digital PLL (ADPLL)
5
All digital PLL (ADPLL)
PLL transverse three modes of operation during settling
PVT-calibration mode : to calibrate large frequency uncertainty due to process-voltage-temperature (PVT) variations Acquisition mode : to acquire the requested operational channel Tracking mode : to track the frequency reference and perform data modulation
6
All digital PLL (ADPLL)
Two-point modulation employed for data modulation
Truly wide-band modulation
7
Gain normalization block
8
Gain normalization block
Normalized DCO has unity gain in terms of reference frequency DCO gain continuously tracked and calibrated during modulation phase with a simple hardware implemented LMS algorithm
9
Digitally controlled oscillator (DCO)
10
Digitally controlled oscillator (DCO)
A digital equivalent of highly linear VCO with wide dynamic frequency range
Feasible dynamic range >800MHz @2.4GHz center frequency
DCO as a system includes a DCO ASIC cell with the tightly coupled peripheral digital circuitry
11
Digitally controlled oscillator (DCO)
DCO core is a differential LC tank oscillator Digital control realized by switching capacitance devices
12
Digitally controlled oscillator (DCO)
DCO core implementation
PVT bank uses switched fringe capacitors Acquisition bank and tracking bank use MOS varactors Cross-coupled NMOS gain stage as negative resistance Digital control for both frequency tuning and current biasing
13
DCO interface logic Dynamic element matching (DEM) to improve linearity in digital-to-frequency conversion
Sigma-delta modulation to enhance frequency resolution
14
DCO interface logic
15
Time-to-digital converter (TDC)
16
Time-to-digital converter (TDC)
TI architecture
Timing critical paths
Our architecture 17
Time-to-digital converter (TDC)
18
Time-to-digital converter (TDC)
The TDC is to give the fractional part of a fixed-point representation of the DCO output frequency
19
Time-to-digital converter (TDC)
TI architecture
Architecture we use 20
Loop filter
21
Loop filter
Digital Low-pass filter with configurable two branches
Unconditional stable 4th order cascade-form IIR filter as the main branch Integral accumulator branch to further suppress the DCO flicker noise
22
Implementation results Input to DCO PVT bank
PLL total settling time about 15us with 26MHz reference clock
about 1us used in PVT mode about 4us used in ACQ mode about 10us for tracking mode settling
155 150 145 dp
140 135 130 0
100
200
300
400
500
600
500
600
500
600
Input to DCO acquisition bank 134
Initial synthesis results (excluding DCO and TDC core) using 65nm technology
Cell area : approx. 0.05 mm2 Cell count : approx. 10,000 Total dynamic power : approx. 17mW Cell leakage power : approx. 0.18mW
130 128 126
0
100
200
300
400
Input to DCO tracking bank 138 136 dt (dti+dtf)
da
132
134 132 130 128 126
0
100
200
300 400 CKR clock cycle
23
Implementation results
TDC core implementation results (after first layout)
Area ~0.001mm², power consumption ~2mW, time resolution ~18-20 ps
DCO core implementation results (after first layout)
Occupied area : 200umX320um Frequency tuning range : approx. 2.3~2.6GHz Phase noise : 127dBc @ 1MHz relative frequency with 6mA biasing current 24
Implementation results
DCO core layout
25
Conclusions
An ADPLL architecture has been presented Our implementation status
Initial RTL synthesis for the digital logic Initial layout for the DCO core Initial layout for the TDC core
Next step in implementation
More iterations of RTL synthesis for further optimization Layout of the digital logic Optimization of TDC and DCO core layout
26
References [1] R. B. Staszewski et al., “A first digitally controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications, ” IEEE 2003 [2] R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE 2004 [3] R. B. Staszewski et al., “All-digital PLL and transmitter for mobile phones,” IEEE 2005 [4] R. B. Staszewski et al., “All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” IEEE 2005
27
