Xiaowei.pdf

Key Engineering Materials ISSN: 1662-9795, Vols. 562-565, pp 311-316 doi:10.4028/www.scientific.net/KEM.562-565.311 © 2013 Trans Tech Publications, Switzerland

Online: 2013-07-15

A Fourth-order MASH Sigma-delta Modulator in Inertial Sensors Liu Xiaowei1,2, Li Qiang1,a , Sun Guannan1,3, and Liu Wenyan1 1

MEMS Center, Harbin Institute of Technology, Harbin, Heilongjiang, China

2

Key Laboratory of Micro-Systems and Micro-Structures Manufacturing, Ministry of Education, China 3

Harbin Power System Engineering & Research Institute Co., Itd. a

[email protected]

Keywords: Inertial sensors; Sigma-delta modulator; MASH; Analog-digital hybrid; SNR

Abstract. The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor. 1. Introduction With rapid development of microelectronics technology, inertial sensors have attracted more and more attentions, high-performance inertial sensors are needed in many fields such as astronautics and medical science. As converting the analog signal of the sensor into digital signal is a key process to improve the sensor performance, sigma-delta conversion with a high resolution is widely used in inertial sensors. Sigma-delta ADC needs high OSR and high order to achieve the high resolution. However, a high OSR can make the sampling frequency too high for achievement and the high-order single-loop sigma-delta modulator is prone to instability [1-3]. In this case, converters use MASH structure of sigma-delta modulator to solve these problems [4-6]. Performance and circuit complexity of the modulator is taken into consideration and a MASH structure which is a feedback MASH 2-1-1 structure is used in this paper. The ENOB of a sigma-delta modulator is 20-bit, so the dynamic range of it is about 120dB. Because the signal bandwidth of the inertial sensor is low, usually several kilo Hertz, a higher OSR can be used. One bit quantizer can reduce nonlinear factors. The dynamic range of the L-order one bit Sigma-Delta modulator can be represented as follows: DR|dB =10 log10（2L + 1）− 20 L log10 π + 10(2 L + 1) log10 (OSR ) (1) Fig. 1 shows the relationship among the OSR, the order and the ENOB of the modulator [7]. Where X-axis represents the OSR, Z-axis represents the ENOB, and Y-axis represents the order of the modulator. From Fig. 1, we can see that an ideal modulator has a high ENOB when the OSR is greater than 64. The OSR is chosen as 128 in this paper. By calculating Eq. 1, if the ENOB of the modulator is more than 20, the circuit needs at least forth order noise shaping. To avoid the unnecessary circuit complexity and power consumption, a fourth-order sigma-delta modulator is used in this paper. The most common structure of the forth order sigma-delta modulator is 2-2 cascade structure and 2-1-1 cascade structure. As 2-1-1 structure has much better performance and more simple noise cancellation logic compared with the 2-2 structure, it is selected as the structure of sigma-delta modulator.

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40 30 20 10

0 150 6

100 4 50

2 0

0

Figure1. Relationship among the OSR, the order and the ENOB of the modulator [7].

Figure 2. Structure of the feedback cascaded 2-1-1 sigma-delta modulator 2. Architecture of The Sigma-delta Modulator Fig. 2 shows the basic structure of a feedback cascaded 2-1-1 sigma-delta modulator which is composed of three stages of low-order modulators. Digital cancellation logic operates on the digital output of each level of the modulator, to offset the quantization noise of the modulator. Where, g1’ g2’ g3’ g4’ are the inter-stage coupling coefficients, g1 g2 g3 g4 are the gain attenuation factors of each integrator, H1(z) H2(z) H3(z) H4(z) are the noise cancellation logic. The last stage of modulator only contains quantization noise of the last quantizer, which can be shaped at the output. The relationship of various parameters of the sigma-delta modulator is shown in Table 1.

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Table 1. The relationship of various parameters of the modulator g 2' = 2 g1' g 2

g3'

d0 =

g1' g 2 g3

g 4' = g 3'' g 4

−1

d1 =

d2 = 0

d3 =

g3'' g1' g 2 g3

g 4'' g1' g 2 g3 g 4

H 1 ( z ) = z −1

H 2 ( z ) = (1 − z −1 ) 2

H 3 ( z ) = z −1

H 4 ( z ) = (1 − z −1 )3

The final output of the modulator contains only the quantization noise of the third quantizer. The noise of the front quantizer is completely eliminated, and the remaining quantization noise is shaping by the last modulator. The final output of the sigma-delta modulator is: Y ( z) =

g1 −4 z X ( z ) + d3 (1 − z −1 )4 E3 ( z ) g1'

(2)

First Integrator Output

Second Integrator Output 300 Occurrences

Occurrences

600

400

200

0 -1

-0.5

0 0.5 Voltage [V] Third Integrator Output

-0.5

0 0.5 Voltage [V] Fourth Integrator Output

1

300 Occurrences

Occurrences

100

0 -1

1

300

200

100

0 -1

200

-0.5

0 0.5 Voltage [V]

1

200

100

0 -1

-0.5

0 0.5 Voltage [V]

1

Figure3. Output level histogram of the first to fourth integrators of the modulator.

Figure 4 Simulation results in system level The system of the sigma-delta modulation is simulated with Matlab. When the bandwidth of the signal is 1 kHz, and the center frequency of it is 250 Hz with an OSR of 128, the simulation results are shown in Fig. 3, Fig. 4. The outputs of integrators in Fig. 3 are all between ± 1, which have not overloaded. It can be seen from Fig. 4 that the signal to noise ratio (SNR) of the modulator is 147.7dB, and the effective number of bits (ENOB) for it is 24.24.

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Figure 5 Circuit of the amplifier

Figure 6 Circuit of the comparator 3. Principle and realization of improved bandgap voltage reference In circuit-level design, the sigma-delta modulator is composed by switched-capacitor integrators, comparators, sequential circuits and noise cancellation logic circuits. The operational amplifier is using a two stage Miller-compensation op-amp, and the comparator is using a latched comparator. Fig. 5 shows the amplifier used in the modulator. In order to get a large gain, folded cascade structure is used in the first stage of the amplifier. The second stage of the amplifier uses the classic common source structure to provide the maximum output swing. The comparator can be used because the s sigma-delta modulator uses a one bit quantizer in this paper. Noise cancellation logic is the specific module of the cascade structure of the sigma-delta modulator, and its role is to cancel he quantization noise of the output of the modulator by digital logic, so that the final output of the modulator contains only the noise of the last quantizer. The circuit is composed entirely by digital circuits, which is integrated by Verilog language. Simulated by Modelsim, its simulation waveform is shown in Fig. 7.

Figure 7 The behavioral level simulation diagram of the noise canceling logical.

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The complete system structure is shown in Fig. 8.

Figure 8 Overall configuration of the modulator.

Figure 9. The overall simulation diagram of the modulator.

Figure 10. PSD of the output signal. The analog-digital mixed simulation of the sigma-delta modulator is based on Cadence, and the frequency spectrum analysis is based on Matlab. When the bandwidth of the signal is 1 kHz and the OSR is 128, the SNR of the modulator achieves 125.4dB and its ENOB is 21.1. Compared with the system level simulation results, the SNR of the modulator has a 7dB drop, which can satisfy the precision demand of the sensor.

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Summary A MASH sigma-delta modulator for inertial devices is proposed in this paper. The results of system-level simulation by Simulink and circuit-level simulation by Hspice and Cadence show that the designed modulator achieves the expected requirement. References [1]

[2] [3]

[4] [5] [6]

[7]

I.Fujimori, L.Longo, A.Hairapetian, K.Seiyama, S.Kosic and J.Cao, “A 90-dB SNR 2.5-MHzoutput-rate ADC using cascaded multibit deltasigmamodulation at 8x oversampling ratio,” IEEE J. Solid-State Circuits, 2000, pp. 1820-1828. K.Vleugels, S.Rabii and B.Wooley, “A 2.5-V sigma-delta modulator for broadband communications applications,” IEEE J. Solid-State Circuits, 2001, pp. 1887-1899. J.Silva, U.Moon, and G.Temes, “Low-distortion delta-sigma topologies for MASH architectures,” Proceedings - IEEE International Symposium on Circuit and Systems, 2004, pp. I1144-I1147. Z.Sohrabi and M.Yavari, “A 13 bit 10MHz bandwidth MASH 3-2 Σ∆ modulator in 90 nm CMOS,” International Journal of Circuit Theory and Applications, 2012. K.Peter, A.Wiesbauer, T.Sun, U.Moon, J.Stonick and G.Temes, “Adaptive digital correction of analog errors in MASH ADC,” IEEE Transations on Circuit and System, 2000, pp. 629-638. A.Oquz, K.Jinseok, A.Philip, “A 1.5V multirate multibit sigma-delta modulator for GSM/WCDMA in a 90nm digital CMOS process,” Proceedings – IEEE International Symposium on Circuit and Systems, 2005, pp. 5577-5580. Y.Geerts,S.J.Steyaert and W.Sansen, “A Hign-performance Multibit Sigma-Delta CMOS ADC,” IEEE Journal of Solid-State Circuit, 2000, pp. 1432-1444.

Micro-Nano Technology XIV 10.4028/www.scientific.net/KEM.562-565

A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors 10.4028/www.scientific.net/KEM.562-565.311