Wipro Fpga Design Flow

EagleWision FPGA Design Flow

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EagleWison FPGA Design Flow

The FPGA Design Flow is given in the figure below.

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EagleWision FPGA Design Flow

Architecture WIPRO's FPGA Design Centre leverages on domain expertise in telecommunica tions, networking and embedded systems, to define the functional architecture of the design. This, coupled with the FPGA /ASIC Design expertise, enables the team to come out with efficient optimized architecture, which can easily fit into the se lected FPGA, meeting the timing and other criteria). Key aspects of this phase include: !

Architectural simulations for proof of concept, performance evaluation and to gather data for functional definition of architecture and/or high level design definition

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Definition of FPGA architecture: Data and Control Flow, On-chip buses, Buffering strategies, Register implementation, clocking and synchronization schemes, IO definition, functional / physical partitioning, integration of soft/hard IP blocks.

EagleWise ASIC Design Handbook along with ETCH (Early Timing Closure Hacker.) & FACT (FPGA Area Closure Tracker focusing on Architecture/Design Optimization techniques catering to FPGA Designs) enables “best practices” framework by capturing guidelines on Architecture, design partitioning, RTL coding, low power designs, high performance designs etc. These guidelines enable the chosen architecture to achieve the performance goals with no or minimum number of iterations.

Part Selection & I/O Planning Part Selection & I/O Planning at this early stage (after the Architecture phase) provides necessary input for the board design so that the system design can proceed parallel.

Key aspects of this phase include: !

Selecting the FPGA device based on Systematic approach. FPGA Device Selection Guide provides set of guidelines and considerations

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FACT Methodology for controllability over FPGA resources right from architecture stage. It provides a comprehensive set of area estimation guidelines coupled with a tracker to control FPGA area within budget. It aids the designer with an exhaustive collection of area optimization techniques

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Assigning the I/Os, obeying the electrical DRC and to ease out the Board Layout. I/O Planning makes use of in-house tools to generate top level RTL with dummy logic and vendor specific tools, to do the pin assignments and DRC checking.

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Based on the pin assignment, FPGA Schematic Part Symbols are generated automatically using in-house scripts.

FPGA Configuration Strategy is planned as per the system requirement.

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EagleWison FPGA Design Flow

Logic Design ! Design definition captured in detailed design documents ! Guidelines recommended in FACT & ETCH are followed during design. ! Documents prepared with appropriate template to have uniformity. ! Checklists are used for reviewing the design and checklists cover various

aspects like Timing, Area, I/O assignments etc. ! Review process concentrates on various aspects like requirement compli

ance, performance, optimization and documentation and so on to ensure the completeness of the design. ! EagleWise ASIC Design Handbook that defines guidelines and mandates

standards for logic design. ! Proven ETCH methodology (Early Timing Closure Hacker) for early timing

closure of FPGA designs. The principle behind ETCH is that of Design for Timing Closure. ETCH provides powerful set of Design guidelines for timing closure norms, guidelines and techniques. ! FACT (FPAG Area Closure Tracker) provides comprehensive list of Area

optimization guidelines

Design Environment Setup ! Directory structure that is suitable for design, verification, synthesis and FPGA

fitting. ! Effective Version Control System using tools like CVS, Clearcase. ! Efficient use of defect tracking system and configuration management

system throughout the course of the project ! Repositories and user accounts backed up on tape/CD at regular intervals

and sent for disaster recovery backup ! Special relationship with tool vendors helps to support peak tool demand

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EagleWison FPGA Design Flow

Verification Planning ! Early identification of verification strategy ! Successful deployment of several verification methodologies such as ! SAVE (Self checking Automated Verification Environment), ! C model Predictor based verification ! Efficient, High level tool based verification using Vera or Specman ! Verification aims at achieving a high level of functional and code coverage ! All levels of verification planned: block level, multi-block module level, Full

Chip/ FPGA level. Depending on the need, system level as well as hard ware-software co-verification is also planned. ! Traceability matrix to link verification test cases with each attribute of design

under test ! Extensive use of EagleWise Verification Handbook guidelines and thorough

review mechanism in place

RTL Coding ! Coding in Verilog or VHDL ! RTL files created with project specific template ! HDL Coding Guidelines (as defined in the EagleWise ASIC Design Hand

book) to ensure consistent style of coding ! Coding Tips from FACT & ETCH to achieve the best design performance. ! Mandatory code purification using SCOUR, Wipro's own linting and having

interface to HDL lint tools like ExploreRTL. Linting is performed to weed out coding problems of synthesizability, testability, simulation-synthesis mis match, and coding guidelines violations. ! Code review for critical modules to identify issues like synchronization,

meta-stability that can't be detected during RTL simulations, along with functionality checking etc.

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EagleWison FPGA Design Flow

Verification Design !

Design of Verification Environment and test cases

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Use of verification guidelines & checklists

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Extensive test cases to check each feature of the design

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Extensive and thoroughly structured reviews to identify test scenarios

Verification Coding !

Creation of components and test cases for the verification environment

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Use of HDL, Specman, Vera and C/Perl Coding Guidelines

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High level abstraction using languages like C, Vera, Specman etc. that allows faster development of test cases

Functional Verification Hierarchical Functional Verification using different levels of abstraction. !

Unit Level Verification using simple HDL Based environment. Usage of Unit Level Test Plan and Code Coverage metrics as exit criteria.

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Code coverage framework called HDLCov (based on tools like HDL Score, Verification navigator) to run code coverage of Design Under Test

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Full Chip/FPGA Level verification using sophisticated environment, C Predictors or HVLs like Specman or Vera depending on the Verification strategy and planning.

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Verification framework that allows automated collection of verification metrics; verification metrics are captured to ensure adequacy of functional coverage and to ensure that code coverage goals are satisfied.

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Making use of in house Verification IPs including interface protocol compli ance checkers and traffic generators, that can easily be customized to any verification environment

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Use of metrics (test completeness, earned value, defect arrival trend, etc.) to enable decision making and resource planning

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Verification checklist for completeness and exhaustiveness of verification.

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EagleWison FPGA Design Flow

Preliminary Synthesis & Fitting !

Preliminary Synthesis and Top level integration is executed after unit testing to asses the performance and to modify any pinout changes, if necessary.

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Industry standard synthesis tools like Synplify, FPGA Compiler and Vendor specific Fitting tools are used.

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Familarity with leading FPGA vendors like Xilinx, ALTERA & LUCENT

Synthesis & Floor planning !

Done after completing the unit testing and 60-70% of the functional verification is complete.

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Floor planning coupled with Synthesis depending on the frequency of opera tion and performance requirement.

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Usage of Industry standard tools like Amplify (Floor planning & Synthesis), Synplify and FPGA Compiler FACT & ETCH provides some tool specific optimization techniques.

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Also captures some tool specific optimization techniques.

Fitting & STA !

Vendor Specific Fitting tool and timing engines are made use of

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Based on the results, the performance requirements and other constraints are validated.

Gate Simulations & Formal Verification !

Gate level simulation is done for some representative test cases

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Depending on the requirement, formal verification is carried out between RTL and the fitted netlist.

Bit Stream Generation & Formatting !

Depending on the chosen mode of configuration and system requirement, bit stream is generated & formatted

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Vendor specific fitting tools are made use of, for this purpose

On Board Configuration & Testing !

Formatted bit stream is downloaded (i.e. configured) to the onboard FPGA (depending on the system).

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Testing and Debugging is done as per system level test plan to validate the FPGA Design.

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