Vlsi Systems Design Rr321202

Set No. 1

Code No: RR321202

III B.Tech II Semester Regular Examinations, Apr/May 2007 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following logic functions using CMOS logic (a) Y = {AB + (C + D)}1 (b) Y = {A(B + C) + D}1

[8+8]

2. An p-MOS transistor is operating in the triode region with the following parameters µn Cox = 95 µ A/V 2 W/L ( ratio) = 90 V gs = −4V, Vtn = −1.1V, Vds = −2V . Find its drain current & drain -Source resistance. [16] 3. Explain with neat sketches CMOS fabrication using P - well process.

[16]

4. Implement 2-input NOR and NAND gates using static complementary logic. [16] 5. Explain with suitable example the details of single - Row layout design method. [16] 6. Draw the structure of a carry skip adder and explain its working principle.

[16]

7. Clearly discuss about power distribution and clock distribution routing procedure. [16] 8. Explain clearly about technology independent logic optimization. ⋆⋆⋆⋆⋆

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Set No. 2

Code No: RR321202

III B.Tech II Semester Regular Examinations, Apr/May 2007 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following gates with CMOS Logic and explain its working (a) 2- Input NAND gate. (b) 3- Input NOR gate.

[8+8]

2. (a) Why CMOS technology is most suitable for VLSI ICs? (b) Compare between CMOS and bipolar technologies. 3. Design a stick diagram for CMOS logic shown below. Y = (AB + CD)1 4. Design a layout for CMOS inverter.

[6+10] [16] [16]

5. How cross-talk appears in ICs and explain how this cross-talk can be minimized in ICs. [16] 6. Design a logic gate network for full adder (a) Using Two-level logic (b) Using multi-level logic

[8+8]

7. Explain how power - down modes reduces the power consumption of the design. [16] 8. Explain clearly about technology independent logic optimization. ⋆⋆⋆⋆⋆

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[16]

Set No. 3

Code No: RR321202

III B.Tech II Semester Regular Examinations, Apr/May 2007 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following logic functions using CMOS logic (a) Y = {(A + B).C}1 (b) Y = {(A.B + C).D}1

[8+8]

2. What are the key advantages of ICs? And explain how these advantages of ICs translate in to advantages at the system level. [16] 3. Explain with neat sketches CMOS fabrication using P - well process.

[16]

4. Implement EX-OR and EX-NOR gates using static complementary logic.

[16]

5. Explain how wire delay are calculate using El-more - delay model and RC Trees. [16] 6. Draw the structure of a carry skip adder and explain its working principle.

[16]

7. (a) Explain about Register - transfer abstraction of the Design. (b) Why does not an output pad require Electrostatic discharge protection circuitary? [8+8] 8. Write a register-transfer description of one four-digit timer. ⋆⋆⋆⋆⋆

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[16]

Set No. 4

Code No: RR321202

III B.Tech II Semester Regular Examinations, Apr/May 2007 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following logic functions using CMOS logic (a) Y = {AB + CD}1 (b) Y = {A.B.C + D}1

[8+8]

2. (a) Why CMOS technology is most suitable for VLSI ICs? (b) Compare between CMOS and bipolar technologies.

[6+10]

3. With respect to IC fabrication explain about Design-rules and scalable design rules [16] 4. Explain about Pseudo-logic and draw the circuit topology of a three-input NOR gate designed in Pseudo - NMOS. [16] 5. Explain with suitable example the details of single - Row layout design method. [16] 6. Draw the structure of Wallace-tree multiplier and explain its working.

[16]

7. Explain clearly block placement phase of the Floor planning of the chip with suitable examples. [16] 8. With suitable example explain any one of the placement algorithm. ⋆⋆⋆⋆⋆

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[16]