Vlsi Design May2006 Rr320405

Set No. 1

Code No: RR320405

III B.Tech II Semester Regular Examinations, Apr/May 2006 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Derive an equation for IDS of an n-channel Enhancement MOSFET operating in Saturation region. (b) An nMOS transistor is operating in saturation region with the following parameters. VGS = 5V ; Vtn = 1.2V ; W/L = 110; µnCox = 110 µA/V 2 . Find Transconductance of the device. [8+8] 2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] 3. Design a stick diagram for two input n-MOS NAND and NOR gates.

[16]

4. Design a layout diagram for nMOS inverter.

[16]

5. Two nMOS inverters are cascaded to drive a capacitive load CL =14Cg as shown in Figure 1. Calculate the pair delay Vin to Vout in terms of τ for the given data. Inverter -A LP.U = 12λ , WP.U = 4 λ , LP.d = 1 λ , WP.d = 1 λ Inverter -B LP.U = 4λ , WP.U = 4 λ , LP.d = 2 λ , WP.d = 8 λ

[16]

Figure 1: 6. Explain about the following gate array based ASICS (a) Channel gate arrays (b) Channel less gate arrays (c) Structured gate arrays

[5+5+6]

7. With respect to synthesis process explain the following terms.

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Set No. 1

Code No: RR320405 (a) Flattening (b) Factoring. (c) Mapping.

[6+5+5]

8. Explain about the following packaging design considerations. (a) VLSI design rules. (b) Thermal design consideration.

[8+8]

⋆⋆⋆⋆⋆

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Set No. 2

Code No: RR320405

III B.Tech II Semester Regular Examinations, Apr/May 2006 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Clearly Explain the sub-threshold conduction of the MOSFET. (b) Show that switching speed of an enhancement MOSFET various inversely as the square of channel length. [8+8] 2. With neat sketches explain how Diodes and Resistors are fabricated in nMOS process. [16] 3. Design a stick diagram for the NMOS logic shown below Y = (A + B + C)

[16]

4. Explain about the following (a) Lambda - based design rules (b) Double metal process rules.

[8+8]

5. Calculate on resistance of the circuit shown in Figure 1 from VDD to GND. If nchannel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance Rsp = 2.5 × 104 Ω per square. [16]

Figure 1: 6. Using PLA Implement JK Flip flop circuit. 7. With respect to synthesis process explain the following terms. (a) Flattening (b) Factoring. 1 of 2

[16]

Set No. 2

Code No: RR320405 (c) Mapping.

[6+5+5]

8. With neat sketches explain the electron lithography process. ⋆⋆⋆⋆⋆

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[16]

Set No. 3

Code No: RR320405

III B.Tech II Semester Regular Examinations, Apr/May 2006 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) With neat sketches explain the formation of the inversion layer in n-channel enhancement MOSFET. (b) A PMOS Transistor is operated in the triode region with the following parameters. VGS = −4.5V ; Vtp = −1V ; VDS = −2.2V ; W/L = 95; µnCox = 95 µA/V 2 Find its drain current and drain source resistance. [8+8] 2. With neat sketches explain how Diodes and Resistors are fabricated in Bipolar process. [16] 3. Design a stick diagram for n-MOS Ex-NOR gate.

[16]

4. Design a layout diagram for nMOS inverter.

[16]

5. Calculate the gate capacitance value of 2µm technology minimum size transistor with gate to channel capacitance value is 8 × 10−4 pF/µm2 . [16] 6. With neat sketches explain the architecture of PAL.

[16]

7. Explain the following processes in the ASIC design flow. (a) Post - layout timing simulation. (b) Post synthesis simulation.

[8+8]

8. With neat sketches explain Atmospheric- pressure chemical vapor deposition method. [16] ⋆⋆⋆⋆⋆

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Set No. 4

Code No: RR320405

III B.Tech II Semester Regular Examinations, Apr/May 2006 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Define threshold voltage of a MOS device and explain its significance. (b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8] 2. (a) With neat sketches explain CMOS fabrication using n-well process. (b) Explain how capacitors are fabricated in CMOS process. 3. Design a stick diagram for the PMOS logic shown below Y = (A + B).C

[10+6] [16]

4. Design a layout diagram for the PMOS logic shown below Y = (AB) + (CD) [16] 5. Explain clearly about different parastic capacitances of an nMOS transistor. [16] 6. With neat sketches explain the architecture of PAL.

[16]

7. What are the inputs that are provided to the synthesis tool? And explain completely about synthesis process in the ASIC design. [16] 8. With neat sketches explain the oxidation process in the IC fabrication process. [16] ⋆⋆⋆⋆⋆

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