Vlsi Coding Of Multiplexer

LAB NO 3 A Object: To implement two one mux

Circuit diagram:

Coding: module twoonemux(out,s,I0,I1); input s,I0,I1; output out; wire a,b,c; not g1(a,s); and g2(b,a,I0); and g3(c,s,I1); or g4(out,b,c); endmodule module test; reg s,I0,I1; wire out; twoonemux abc(out,s,I0,I1); initial begin s=1'b0;I0=1'b0;I1=1'b0; #15 s=1'b0;I0=1'b1;I1=1'b0; #15

s=1'b1;I0=1'b0;I1=1'b1; #15 s=1'b1;I0=1'b1;I1=1'b1; $finish; end endmodule

Result:

LAB NO 3(B) Object: To implement four to one mux

Circuit diagram:

Coding: module fouronemux(out,s0,s1,I0,I1,I2,I3); input s0,s1,I0,I1,I2,I3; output out; wire a,b,c,d,e,f; not g1(a,s0); not g2(b,s1); and g3(c,a,b,I0); and g4(d,a,s1,I1); and g5(e,s0,b,I2); and g6(f,s0,s1,I3); or g7(out,c,d,e,f); endmodule module test; reg s0,s1,I0,I1,I2,I3; wire out; fouronemux abc(out,s0,s1,I0,I1,I2,I3); initial begin s0=1'b0;s1=1'b0;I0=1'b0;I1=1'b0;I2=1'b0;I3=1'b0; #15 s0=1'b0;s1=1'b0;I0=1'b1;I1=1'b0;I2=1'b0;I3=1'b0; #15

s0=1'b0;s1=1'b1;I0=1'b0;I1=1'b0;I2=1'b0;I3=1'b0; #15 s0=1'b0;s1=1'b1;I0=1'b0;I1=1'b1;I2=1'b0;I3=1'b0; #15 s0=1'b1;s1=1'b0;I0=1'b0;I1=1'b0;I2=1'b0;I3=1'b0; #15 s0=1'b1;s1=1'b0;I0=1'b0;I1=1'b0;I2=1'b1;I3=1'b0; #15 s0=1'b1;s1=1'b1;I0=1'b0;I1=1'b0;I2=1'b0;I3=1'b0; #15 s0=1'b1;s1=1'b1;I0=1'b0;I1=1'b0;I2=1'b0;I3=1'b1; #15 $finish; end endmodule

Result :

LAB NO:4A OBJECT: Using two buffer simulate 2-1 mux.

CIRCUIT DIAGRAM:-

TRUTH TABLE:s 1 0

CODING:module buffer(i1,i2,s,out); output out; input i1,i2,s; bufif1 b1(out,i1,s); bufif0 b2(out,i2,s); endmodule module test; reg s,i1,i2; wire out; buffer abc(i1,i2,s,out); initial begin s=1'b0;i1=1'b0;i2=1'b0; #25 s=1'b0;i1=1'b0;i2=1'b1; #25 s=1'b1;i1=1'b0;i2=1'b0; #25 s=1'b1;i1=1'b1;i2=1'b0; #25

output I1 I2

$finish; end endmodule

RESULTANT WAVEFORM:-

LAB NO.4-B OBJECT:Using two inverters simulate 2-1 mux.

CIRCUIT DIAGRAM:-

TRUTH TABLE:s 1 0

CODING:module buffer(i1,i2,s,out); output out; input i1,i2,s; notif1 n1(out,i1,s); notif0 n2(out,i2,s); endmodule module test; reg s,i1,i2; wire out; buffer abc(i1,i2,s,out); initial begin s=1'b0;i1=1'b0;i2=1'b0; #25 s=1'b0;i1=1'b0;i2=1'b1; #25

output I1’ I2’

s=1'b1;i1=1'b0;i2=1'b0; #25 s=1'b1;i1=1'b1;i2=1'b0; #25 $finish; end endmodule

RESULTING WAVEFORM:-

LAB NO.4-C OBJECT:Implement 4-2 Rom using decoder and gate as memory element.

CIRCUIT DIAGRAM:-

TRUTH TABLE:I0 0 0 1 1

I1 0 1 0 1

CODING:module fourtworom(x,y,i1,i0); input i1,i0; output x,y; wire a,b,c,d,e,f; not g1(a,i1); not g2(b,i0); and g3(c,i0,i1); and g4(d,i0,a); and g5(e,b,i1); and g6(f,a,b); or g7(x,c,d);

G3 1 0 0 0

G4 0 1 0 0

G5 0 0 1 0

G6 0 0 0 1

or g8(y,e,f); endmodule module test; reg i1,i0; wire x,y; fourtworom abc(x,y,i1,i0); initial begin i1=1'b0;i0=1'b0; #25 i1=1'b0;i0=1'b1; #25 i1=1'b1;i0=1'b0; #25 i1=1'b1;i0=1'b1; #25 $finish end endmodule

RESULT:-

LAB NO.4-D OBJECT:Implement 8-2 Rom using decoder and gate as memory element.

CIRCUIT DIAGRAM:-

TRUTH TABLE:I2 0 0 0 0 1 1 1 1

I1 0 0 1 1 0 0 1 1

I0 0 1 0 1 0 1 0 1

G4 1 0 0 0 0 0 0 0

G5 0 1 0 0 0 0 0 0

G6 0 0 1 0 0 0 0 0

G7 0 0 0 1 0 0 0 0

G8 0 0 0 0 1 0 0 0

G9 0 0 0 0 0 1 0 0

G10 0 0 0 0 0 0 1 0

G11 0 0 0 0 0 0 0 1

CODING:module fourtworom(x,y,i2,i1,i0); input i2,i1,i0; output x,y; wire a,b,c,d,e,f,g,h,i,j,k; not g1(a,i2); not g2(b,i1); not g3(c,i0); and g4(d,i0,i1,i2); and g5(e,c,i1,i2); and g6(f,b,i0,i2); and g7(g,b,c,i2); and g8(h,a,i0,i1); and g9(i,a,c,i1); and g10(j,a,b,i0); and g11(k,a,b,c); or g12(x,d,e,f,g); or g13(y,h,i,j,k); endmodule module test; reg i2,i1,i0; wire x,y; fourtworom abc(x,y,i2,i1,i0); initial begin i2=1'b0;i1=1'b0;i0=1'b0; #25 i2=1'b0;i1=1'b0;i0=1'b1; #25 i2=1'b0;i1=1'b1;i0=1'b0; #25 i2=1'b0;i1=1'b1;i0=1'b1; #25 i2=1'b1;i1=1'b0;i0=1'b0; #25 i2=1'b1;i1=1'b0;i0=1'b1; #25 i2=1'b1;i1=1'b1;i0=1'b0; #25 i2=1'b1;i1=1'b1;i0=1'b1; #25 $finish; end endmodule

RESULT:-