Virtual Memory1 March2007
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MEMORY MANAGEMENT & VIRTUAL MEMORY
Lecture Series By : Website ::
Er. Kanwalvir Singh Dhindsa www.dhindsa.info
http://groups.google.com/group/os-2007 E-Mail ::
[email protected] 1
O.S. by Er. K.S.Dhindsa © 2007
Logical Vs Physical address space LOGICAL ADDRESS – An address generated by CPU PHYSICAL ADDRESS – An address as seen by the memory unit (Loaded into MAR of the memory) ROLE OF MMU (Converts L.A’s into P.A’s) 2
O.S. by Er. K.S.Dhindsa © 2007
Base and Limit Registers • A pair of base and limit registers define the logical address space
3
O.S. by Er. K.S.Dhindsa © 2007
Schematic View of Swapping Priority-based Scheduling (roll out,roll in) Role of : CPU Schedular,Dispatcher & Memory manager
4
O.S. by Er. K.S.Dhindsa © 2007
Contiguous Allocation • Main memory usually divided into two partitions: – Resident operating system, usually held in low memory with interrupt vector – User processes then held in high memory • Relocation registers used to protect user processes from each other, and from changing operating-system code and data – Base register contains value of smallest physical address – Limit register contains range of logical addresses – each logical address must be less than the limit register – MMU maps logical address dynamically 5
O.S. by Er. K.S.Dhindsa © 2007
I. SINGLE-PARTITION ALLOCATION II. MULTIPLE-PARTITION ALLOCATION – Hole – block of available memory; holes of various size are scattered throughout memory – When a process arrives, it is allocated memory from a hole large enough to accommodate it – Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS
OS
OS
OS
process 5
process 5
process 5
process 5
process 9
process 9
process 8 process 2
process 10 process 2
process 2
process 2 6
O.S. by Er. K.S.Dhindsa © 2007
Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes ?? • •
•
First-fit: Allocate the first free block of memory that is big enough Best-fit: Allocate the smallest free block of memory that is big enough; must search entire list, unless ordered by size – Produces the smallest leftover hole Worst-fit: Allocate the largest free block of memory ; must also search entire list – Produces the largest leftover hole Firstfit and bestfit better than worstfit in terms of speed and storage utilization
7
O.S. by Er. K.S.Dhindsa © 2007
PAGING • Divide logical memory into blocks of same size called pages • Divide physical memory into fixed-sized blocks called frames • Keep track of all free frames • To run a program of size n pages, need to find n free frames and load program • Set up a page table to translate logical to physical addresses
8
O.S. by Er. K.S.Dhindsa © 2007
Paging Model of Logical and Physical Memory
9
O.S. by Er. K.S.Dhindsa © 2007
Address Translation Scheme
• Address generated by CPU is divided into: – Page number (p) – used as an index into a page table which contains base address of each page in physical memory – Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
10
O.S. by Er. K.S.Dhindsa © 2007
Paging Hardware
11
O.S. by Er. K.S.Dhindsa © 2007
Paging Model of Logical and Physical Memory
12
O.S. by Er. K.S.Dhindsa © 2007
Implementation (Structure) of Page Table • Page table is kept in main memory • Page-table base register (PTBR) points to the page table • Page-table length register (PRLR) indicates size of the page table • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs) • Consists of : A key and a Value in TLB
13
O.S. by Er. K.S.Dhindsa © 2007
Paging Hardware With TLB
14
O.S. by Er. K.S.Dhindsa © 2007
HIT RATIO
HIT RATIO Percentage of times that a page number is found in the associative registers
80% Hit Ratio
15
O.S. by Er. K.S.Dhindsa © 2007
Memory Protection • Memory protection implemented by associating protection bit with each frame • Valid-invalid bit attached to each entry in the page table: – “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page – “invalid” indicates that the page is not in the process’ logical address space 16
O.S. by Er. K.S.Dhindsa © 2007
Valid (v) or Invalid (i) Bit In A Page Table
17
O.S. by Er. K.S.Dhindsa © 2007
Thrashing • If a process does not have “enough” pages, the page-fault rate is very high • Leading to: – low CPU utilization – operating system thinks that it needs to increase the degree of multiprogramming – another process added to the system • Thrashing ≡ a process is busy swapping pages in and out (If it is spending more time paging than executing) 18
O.S. by Er. K.S.Dhindsa © 2007
Thrashing (Cont.)
19
O.S. by Er. K.S.Dhindsa © 2007
Working-Set Model • Works on the assumption of locality ∀ ∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction • WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time) – if ∆ too small will not encompass entire locality – if ∆ too large will encompass several localities – if ∆ = ∞ ⇒ will encompass entire program • D = Σ WSSi ≡ total demand frames • • • •
If D > m (no. of available frames) ⇒ Thrashing Policy if D > m, then suspend one of the processes Prevents thrashing while keeping degree of multiprogramming as high as possible Optimizes CPU Utilization
20
O.S. by Er. K.S.Dhindsa © 2007
Working-set model
21
O.S. by Er. K.S.Dhindsa © 2007
Segmentation • Memory-management scheme that supports user view of memory • A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays 22
O.S. by Er. K.S.Dhindsa © 2007
User’s View of a Program
23
O.S. by Er. K.S.Dhindsa © 2007
Logical View of Segmentation 1 4
1 2 3
4
2 3
user space
physical memory space
24
O.S. by Er. K.S.Dhindsa © 2007
Segmentation Architecture • Logical address consists of a two tuple: <segment-number, offset> • Segment table – maps two-dimensional physical addresses; each table entry has: – base – contains the starting physical address where the segments reside in memory – limit – specifies the length of the segment • Segment-table base register (STBR) points to the segment table’s location in memory • Segment-table length register (STLR) indicates number of segments used by a program; 25
O.S. by Er. K.S.Dhindsa © 2007
Segmentation Hardware
26
O.S. by Er. K.S.Dhindsa © 2007
Example of Segmentation
27
O.S. by Er. K.S.Dhindsa © 2007
MEMORY MANAGEMENT & VIRTUAL MEMORY
Lecture Series By : Website ::
Er. Kanwalvir Singh Dhindsa www.dhindsa.info
http://groups.google.com/group/os-2007 E-Mail ::
[email protected] 28
O.S. by Er. K.S.Dhindsa © 2007
Lecture Series By : Website ::
Er. Kanwalvir Singh Dhindsa www.dhindsa.info
http://groups.google.com/group/os-2007 E-Mail ::
[email protected] 1
O.S. by Er. K.S.Dhindsa © 2007
Logical Vs Physical address space LOGICAL ADDRESS – An address generated by CPU PHYSICAL ADDRESS – An address as seen by the memory unit (Loaded into MAR of the memory) ROLE OF MMU (Converts L.A’s into P.A’s) 2
O.S. by Er. K.S.Dhindsa © 2007
Base and Limit Registers • A pair of base and limit registers define the logical address space
3
O.S. by Er. K.S.Dhindsa © 2007
Schematic View of Swapping Priority-based Scheduling (roll out,roll in) Role of : CPU Schedular,Dispatcher & Memory manager
4
O.S. by Er. K.S.Dhindsa © 2007
Contiguous Allocation • Main memory usually divided into two partitions: – Resident operating system, usually held in low memory with interrupt vector – User processes then held in high memory • Relocation registers used to protect user processes from each other, and from changing operating-system code and data – Base register contains value of smallest physical address – Limit register contains range of logical addresses – each logical address must be less than the limit register – MMU maps logical address dynamically 5
O.S. by Er. K.S.Dhindsa © 2007
I. SINGLE-PARTITION ALLOCATION II. MULTIPLE-PARTITION ALLOCATION – Hole – block of available memory; holes of various size are scattered throughout memory – When a process arrives, it is allocated memory from a hole large enough to accommodate it – Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS
OS
OS
OS
process 5
process 5
process 5
process 5
process 9
process 9
process 8 process 2
process 10 process 2
process 2
process 2 6
O.S. by Er. K.S.Dhindsa © 2007
Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes ?? • •
•
First-fit: Allocate the first free block of memory that is big enough Best-fit: Allocate the smallest free block of memory that is big enough; must search entire list, unless ordered by size – Produces the smallest leftover hole Worst-fit: Allocate the largest free block of memory ; must also search entire list – Produces the largest leftover hole Firstfit and bestfit better than worstfit in terms of speed and storage utilization
7
O.S. by Er. K.S.Dhindsa © 2007
PAGING • Divide logical memory into blocks of same size called pages • Divide physical memory into fixed-sized blocks called frames • Keep track of all free frames • To run a program of size n pages, need to find n free frames and load program • Set up a page table to translate logical to physical addresses
8
O.S. by Er. K.S.Dhindsa © 2007
Paging Model of Logical and Physical Memory
9
O.S. by Er. K.S.Dhindsa © 2007
Address Translation Scheme
• Address generated by CPU is divided into: – Page number (p) – used as an index into a page table which contains base address of each page in physical memory – Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
10
O.S. by Er. K.S.Dhindsa © 2007
Paging Hardware
11
O.S. by Er. K.S.Dhindsa © 2007
Paging Model of Logical and Physical Memory
12
O.S. by Er. K.S.Dhindsa © 2007
Implementation (Structure) of Page Table • Page table is kept in main memory • Page-table base register (PTBR) points to the page table • Page-table length register (PRLR) indicates size of the page table • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs) • Consists of : A key and a Value in TLB
13
O.S. by Er. K.S.Dhindsa © 2007
Paging Hardware With TLB
14
O.S. by Er. K.S.Dhindsa © 2007
HIT RATIO
HIT RATIO Percentage of times that a page number is found in the associative registers
80% Hit Ratio
15
O.S. by Er. K.S.Dhindsa © 2007
Memory Protection • Memory protection implemented by associating protection bit with each frame • Valid-invalid bit attached to each entry in the page table: – “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page – “invalid” indicates that the page is not in the process’ logical address space 16
O.S. by Er. K.S.Dhindsa © 2007
Valid (v) or Invalid (i) Bit In A Page Table
17
O.S. by Er. K.S.Dhindsa © 2007
Thrashing • If a process does not have “enough” pages, the page-fault rate is very high • Leading to: – low CPU utilization – operating system thinks that it needs to increase the degree of multiprogramming – another process added to the system • Thrashing ≡ a process is busy swapping pages in and out (If it is spending more time paging than executing) 18
O.S. by Er. K.S.Dhindsa © 2007
Thrashing (Cont.)
19
O.S. by Er. K.S.Dhindsa © 2007
Working-Set Model • Works on the assumption of locality ∀ ∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction • WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time) – if ∆ too small will not encompass entire locality – if ∆ too large will encompass several localities – if ∆ = ∞ ⇒ will encompass entire program • D = Σ WSSi ≡ total demand frames • • • •
If D > m (no. of available frames) ⇒ Thrashing Policy if D > m, then suspend one of the processes Prevents thrashing while keeping degree of multiprogramming as high as possible Optimizes CPU Utilization
20
O.S. by Er. K.S.Dhindsa © 2007
Working-set model
21
O.S. by Er. K.S.Dhindsa © 2007
Segmentation • Memory-management scheme that supports user view of memory • A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays 22
O.S. by Er. K.S.Dhindsa © 2007
User’s View of a Program
23
O.S. by Er. K.S.Dhindsa © 2007
Logical View of Segmentation 1 4
1 2 3
4
2 3
user space
physical memory space
24
O.S. by Er. K.S.Dhindsa © 2007
Segmentation Architecture • Logical address consists of a two tuple: <segment-number, offset> • Segment table – maps two-dimensional physical addresses; each table entry has: – base – contains the starting physical address where the segments reside in memory – limit – specifies the length of the segment • Segment-table base register (STBR) points to the segment table’s location in memory • Segment-table length register (STLR) indicates number of segments used by a program; 25
O.S. by Er. K.S.Dhindsa © 2007
Segmentation Hardware
26
O.S. by Er. K.S.Dhindsa © 2007
Example of Segmentation
27
O.S. by Er. K.S.Dhindsa © 2007
MEMORY MANAGEMENT & VIRTUAL MEMORY
Lecture Series By : Website ::
Er. Kanwalvir Singh Dhindsa www.dhindsa.info
http://groups.google.com/group/os-2007 E-Mail ::
[email protected] 28
O.S. by Er. K.S.Dhindsa © 2007
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