Verilog.doc

1) %%%% Basic Gates %%%% module gates(a,b,c,d,e,f,g,h,i); input a,b; output c,d,e,f,g,h,i; and(c,a,b); or(d,a,b); not(e,a); nand(f,a,b); nor(g,a,b); xor(h,a,b); xnor(i,a,b); endmodule 2) %%%% Prgram for logic expression F=xy+yz+zx %%%% module ckt(a,b,c,d,e,f,g); input a,b,c; inout d,e,f; output g; and(d,a,b); and(e,b,c); and(f,c,a); or(g,d,e,f); endmodule 3) %%%% Half adder Program %%%% module halfadd(a,b,sum,carry); input a, b; output sum, carry; assign sum = a ^ b; assign carry = a & b; endmodule 4) %%%% Full adder Program %%%% module fulladd (x, y, z, sum, carry); input x, y, z; output sum, carry; assign sum = x ^ y ^ z; assign carry = (x & y) | (y & z) | (z & x);

endmodule 5) %%%% One Bit Comparator %%%% module onebitcomparator(a,b,abar,bbar,less,equal,greater); input a,b; inout abar,bbar; output less,equal,greater; not(abar,a); not(bbar,b); and(less,abar,b); and(greater,a,bbar); nor(equal,c,e); endmodule 6) %%%% A 3:8 decoder described by "if" statement %%%% module decoder_with_if (Code, Data); output [7:0] Data; input [2:0] Code; reg [7:0] Data; always @ (Code) begin if (Code == 0) Data = 8'b00000001; else if (Code == 1) Data = 8'b00000010; else if (Code == 2) Data = 8'b00000100; else if (Code == 3) Data = 8'b00001000; else if (Code == 4) Data = 8'b00010000; else if (Code == 5) Data = 8'b00100000; else if (Code == 6) Data = 8'b01000000; else if (Code == 7) Data = 8'b10000000; else Data = 8'bx; end endmodule 7) %%%% 8:3 encoder %%%% module encoder_with_priority_03 (Data, Code, valid_data); input [7:0] Data; output [2:0] Code; output valid_data; reg [2:0] Code;

assign valid_data = |Data; always @ (Data) casex(Data) 8'b1xxxxxxx :Code =7; 8'b01xxxxxx :Code =6; 8'b001xxxxx :Code =5; 8'b0001xxxx :Code =4; 8'b00001xxx :Code =3; 8'b000001xx :Code =2; 8'b0000001x :Code =1; 8'b00000001 :Code =0; default: Code =3'bx; endcase endmodule 8) %%%% four-chanelled mux using "if" branching %%%% module mux_4bits (y, sel, a, b, c, d); input [3:0] a, b, c, d; input [1:0] sel; output [3:0] y; reg [3:0] y; always @ (sel) if (sel == 0) y = a; else if (sel == 1) y = b; else if (sel == 2) y = c; else if (sel == 3) y = d; else y = 4'bx; endmodule 9) JK-Flip Flop input j, k, clock, rst; output q, qb; reg q; assign qb = ~q; always @ (posedge clock or posedge rst) begin if(rst== 1'b1) q=1'b0; else case ({j,k})

2'b00: q = q; 2'b01: q=1'b0; 2'b10: q=1'b1; 2'b11: q=~q; endcase end endmodule 10) D-Flip Flop module dff (Q, D, CLK); output Q; input D, CLK; reg Q; always @(posedge CLK) Q = D; endmodule 11) Synchronous Counter module counter(COUNTER, CLK, RESET); parameter SIZE = 'd4; output [SIZE-1:0] COUNTER; input CLK, RESET; reg [SIZE-1:0] COUNTER; always @(posedge CLK or posedge RESET) begin if (RESET) COUNTER = 'd0; else COUNTER = COUNTER + 'd1; end endmodule 12) Ring Counter module ring_counter (enable, reset, clock, count); input enable, reset, clock; output [7:0] count; reg [7:0] count; always @ (posedge reset or posedge clock) if (reset == 1'b1) count <= 8'b0000_0001; else if (enable == 1'b1) count <= {count[6:0], count[7]}; endmodule