Use Of Mos Multiplier

Modelling mismatch effects in CMOS translinear loops and current mode multipliers Mirko Gravati∗, Maurizio Valle ∗ Abstract − MOS translinear circuits can be effectively employed in systems and applications demanding very low power consumption and low operating frequency ranges (i.e. few kHzs) e.g. in bioelectronics and neuroengineering. Nevertheless weak inversion mismatch modelling for design applications is still lacking. In this paper we present a mismatch model for MOS translinear loops and current mode multipliers which accounts for non linearity and accuracy. The model has been experimentally validated and the results are reported. We report also an example of the application of the model to the statistical accuracy analysis of the MOS current mode Gilbert multiplier in the circuit design phase.

phase, the linearity and accuracy of circuit topologies on the basis of device matching. In Section 2, the weak inversion region mismatch model for translinear loops is introduced. In Section 3, the model is extended to the four quadrant current mode Gilbert multiplier and the results of the experimental validation are reported. Moreover, an example of a statistical analysis for the evaluation of the output current accuracy due to device matching is shown. The conclusions are drawn in Section 4.

1

To model mismatch effects in CMOS translinear loops, we refer to the following expression of the channel current in a MOS transistor biased in weak inversion [5]:

INTRODUCTION

In modern integrated circuits the need of very low power consumption (and usually also of low supply voltage) has moved the region of operation of devices to the weak inversion region. Besides low power consumption, in weak inversion the gm/IDS value (i.e. the efficiency of the transistor) at a given bias current is the maximum available. On the other hand, the frequency performances are limited. Nevertheless bioelectronics and neuroengineering systems exhibit specifications which match the performances achievable with circuits operating in the weak inversion region of MOS transistors. In this perspective, a promising circuit implementation approach is based on the translinear principle [1]. Analog current mode four – quadrant multipliers which exploit the translinear principle have been presented in the literature and they exhibit very interesting performances (see, among others, [2]). One of the major limiting factors of weak inversion biased translinear circuits is the device matching [3]. Many papers dealing with the modeling of mismatch in MOS devices, even in the weak inversion region, have been presented (see, among others, [4]). Unfortunately, silicon foundries characterize their technology usually only in strong inversion and then mismatch models are often of limited applicability in the weak inversion region. The goal of our work is to develop a mismatch model for MOS translinear circuits e.g. translinear loops and current mode multipliers (i.e. the Gilbert multiplier). The model is meant to evaluate, during the design ∗

2 MODELLING MISMATCH EFFECTS IN MOS TRANSLINEAR LOOPS

VGS −VTH

I DS = I DC ⋅ e

nφ t

V  − DS 1 − e φ t 

  

(1)

where IDC is a current term, VTH is the threshold voltage, n is the weak inversion slope factor. The mismatch causes random variations of the values of IDC and VTH [6]. With reference to Eq. (1) and to a generic transistor i of a translinear loop, we can define:

δ i = δ (VDS ) = 1 − e

−

VDSi

φt

i

as a generic error

term whose value depends on the drain to source voltage value. If, due to mismatch between devices, the terms IDC and VTH experience variations (i.e. errors) of ∆IDC and ∆VTH respectively from their nominal/typical values, then we can write for a generic device i:

(

)

I DSi = 1 + ∆I DCi I DC ⋅ e

VGSi −VTH nφ t

⋅e

−

∆VTH i

nφ t

δi

(2)

Please note that in Eq. (2), the term ∆IDC represents a percentage variation with respect of the nominal value; on the other hand ∆VTH represents an absolute variation. In other words:

Department of Electronic and Biophysical Engineering, University of Genova, Italy, e-mail: [email protected], [email protected], tel.: +39 010 3532775, fax: +39 010 3532096.

I DC _ real = (1 + ∆I DC ) I DC , VTH _ real = VTH + ∆VTH Let us take into account the (basic) translinear loop shown in Fig. 1. By applying the Kirchhoff voltage law, we obtain:

VGS1 − VGS 2 + VGS 3 − VGS 4 = 0 IDS1

(3)

IDS2

M1

I DS3

M2

IDS4

M3

non linearity term γ from the statistical features of the terms ∆IDC and ∆ VTH. We have derived the statistical features of γ through a Monte Carlo simulation. The terms ∆IDC and ∆VTH can be modelled as stochastic variables with Gaussian distribution and average value equal to zero. The values of their variance can be computed on the basis of the sizes of the transistors of the translinear loop [7]:

σ

M4

2 ∆I DC

=

Aβ2 2WL

,

σ

2 ∆VTH

=

AV2TH 2WL

where Aβ2 and A2VTH

In the previous equation, we introduce a “non linearity” factor γ which takes into account the effects of mismatch between the devices of the translinear loop. Then we can write:

are technological parameters. In the technology that we used (AMI Semiconductor CMOS 0.35µm), their values are: Aβ2=6 [%2 µm2 ] and A2 VTH = 130 [mV2 µm2]. Usually the term ∆IDC is neglected in the weak inversion region of operation (please remember that in a MOS translinear loop, all transistors work in the weak inversion region of operation): in fact the value of ∆IDC is usually much smaller than the one of ∆ VTH. This is the reason why only the ∆VTH is used to model the effect of the spread of MOS transistor parameters in the weak inversion region [8], [9]. Through a Monte Carlo analysis we found that γ has mean value equal to one and variance given by:

I DS 1 ⋅ I DS 3 = γ I DS 2 ⋅ I DS 4

σ γ2 = 0.68 .

From Eq. (2) and (3) one can obtain: I DS1 e

∆VTH 1 nφt

⋅

I DS3 e

∆VTH 3 nφt

=

I DS2 e

∆VTH 2 nφt

⋅

I DS4 e

∆VTH 4 nφt

(1 + ∆I )δ (1 + ∆I )δ (1 + ∆I )δ (1 + ∆I )δ 1

DC1

DC3

3

DC 2

2

DC4

4

where we have approximated n to the value of one.

where the term γ is defined as follows:

γ=

(1 + ∆I )(1 + ∆I ) δ δ (1 + ∆I )(1 + ∆I ) δ δ DC1

DC3

1 3

DC 2

DC 4

2 4

e

−

∆VTH1 + ∆VTH 3 − ∆VTH 2 − ∆VTH 4 nφt

(4)

The non linearity factor γ is given, besides by the spread of the technological parameters ∆IDC and ∆VTH, by the bias point value through the terms

δ i = 1− e

−

VDS 1

φt

. In the following we will consider all

terms δi equal to 1. The error given by this approximation is fairly low: in fact if, let say, VDS is equal to only 100 mV, the error is in the order of magnitude of about 0.05%. Following the previous considerations, the non linearity term γ depends on the spread of technological (and geometric) variables which induce variation on the terms IDC e VTH. Please note that the non linearity term γ depends on the topology of the circuit too. 2.1

Statistical analysis of the non linearity term γ

Statistical features of the non linearity term γ are not a priori known. Due to the complexity of the expression (4), it is not straightforward to mathematically derive the statistical properties of the

The histogram of γ, as result of the

Monte Carlo analysis, is shown in Figure 2 (the number of simulations is 106). The histogram is an estimation of the probability density function of γ. 5

Frequency percentage occurcence

Figure 1: Generic (alternate) translinear loop.

4

3

2

1

0 -1

0

1

2

3

4

5

γ

Figure 2: Histogram of γ. On the x-axis the value of γ is reported, on the y-axis the percentage frequency of occurrence is reported.

3 MODELLING MISMATCH EFFECTS IN THE MOS CURRENT MODE GILBERT MULTIPLIER To demonstrate our model in a real circuit implementation we refer to the four quadrant MOS Gilbert multiplier reported in [2]. The input and output signals are differential and balanced current mode signals:

I IB , − I X = (1 − x ) B 2 2 I I − IW+ = (1 + w) B , IW = (1 − w) B 2 2 where x and w are the information carrying variables (please note that -1 ≤ x ≤+1, -1 ≤w ≤+1) and IB is a bias (reference) current. The output variable can be expressed as: + − IOUT = IOUT − I OUT = xwI B The circuit is based on two translinear loops as shown in Figure 3. To each translinear loop, we apply the model introduced in Section 2: I X+ = (1 + x)

translinear loop 1

IOUT -

IOUT +

M6

I XM9

M7

M5

M8

M10

2

1

IW -

Following Section 2, the non linearity terms γ1 and γ2 can be expressed as:

γ1

DC6

γ2

DC5

DC7

functions of the x input variable and depend on the spread of the technological parameters through the non linearity terms γ1 and γ2:

(1 − x ) (1 + x ) + 2 + (1/ γ 1 − 1)(1 + x ) 2 + (γ 1γ 2 − 1)(1 − x ) (1 − x ) (1 + x ) − nγ′ 1 ,γ 2 ( x ) = 2 + (1 / γ 1 − 1)(1 + x ) 2 + (γ 1γ 2 − 1)(1 − x )

nγ 1,γ 2 ( x) =

n'γ 1,γ 2 ( x) = − x and the output current is exactly

3.1

Figure 3: Basic circuit topology of the Gilbert multiplier reported in [2]. The two translinear loops are highlighted.

DC5

where nγ 1,γ 2 ( x) and n'γ 1,γ 2 ( x) are non linear

equal to the product of the two inputs i.e.: I OUT = xwI B .

IW +

(1 + ∆I = (1 + ∆I (1 + ∆I = (1 + ∆I

]

It is then worth noting that the output current is a non linear function of the x input and a linear function of the w one; in other words, the non linear behaviour of the circuit only depends on the x input (see Section 3.1). Please note that in case of ideal matching γ1 = γ2 =1. Then: nγ 1,γ 2 ( x) = 1 ,

I M 6 I M 8 = γ 2 I M 7 I M 9 translinear loop 2 IX+

[

)(1 + ∆I )(1 + ∆I )(1 + ∆I )(1 + ∆I

DC9

DC10 DC8

DC10

) ⋅e ) ) ⋅e )

−

Experimental validation of the model

We performed an experimental validation of the model on the basis of the measurements on a test chip. In Figure 4, the model (line) and the measurements (symbols) are shown (w is the input and x the parameter).

∆VTH 5 +∆VTH 9 −∆VTH 6 −∆VTH 10 nφt

300

200

−

∆VTH 5 +∆VTH 8 −∆VTH 7 −∆VTH 10 nφt

After some mathematical derivations, the differential multiplier output current, when taking into account the translinear loop transistor mismatch effect, can be expressed as:

100

I_out [nA]

I X+ I M 9 = γ 1I M 6 I X−

γ2 become very relevant thus increasing the overall non linear behaviour of the multiplier. We can further express the output current as follows: + − I OUT = I OUT − I OUT = 1 − nγ 1 ,γ 2 ( x ) − n'γ 1 ,γ 2 ( x) w I B

x = -1 x = -0.6 x = -0.3 x = +0.3 x = +0.6 x = +1

0

-100

-200

-300 -300

-200

-100

0

100

200

300

I_w [nA]

I OUT = IW+ + IW− −

2 I X− IW+ 2 I X+ IW− (5) − + I B + (1 / γ 1 − 1)I X I B + (γ 1γ 2 − 1)I X−

Please note that the two translinear loops are not independent on each other; in fact transistors M6 and M9 belong both translinear loops. This fact causes the presence of the term γ1γ2 whose value can be greater than the values of γ1 and γ2 (if γ1 > 1, γ2 > 1). From Eq. (5), one can note that, when I+X or I-X increases, the effect of the non linearity terms γ1 and

Figure 4: Comparison between the measured and computed output current values.

In Figure 5, the model (line) and the measurements (symbols) are shown for a test chip (x is the input and w the parameter).

4

300

200

I_out [nA]

100

w = -1 w =-0.6 w = -0.3 w = +0.3 w = +0.6 w = +1

0

-100

-200

-300 -300

-200

-100

0

100

200

300

I_x [nA]

Figure 5: Comparison between the measured and computed output current values.

The percentage error is below 4%. The measured values of γ1 and γ2 vary between 0.55 and 1.62. The maximum percentage error in all measurements is below 6%. Please note that the translinear loop has been implemented using simply only interdigitized structures: this account for the fairly high values of γ1 and γ2. 3.2

Statistical accuracy analysis of the Gilbert multiplier

The model of the mismatch effects in translinear loops applied to an analog current mode multiplier, can be used during the design phase to statistically evaluate mismatch effects. In fact, on the basis of the statistical analysis of the non linearity terms (see Section 2) related to translinear loops, and following the mathematical expression developed in Section 3, it is possible to perform a Monte Carlo simulation which gives as output the statistical distribution (i.e. estimated probability density function) of the output current due to mismatch effects. The result of such analysis is shown in Figure 6 for the Gilbert multiplier of Section 3. Please note that the average of the output current is the ideal expected value (i.e. the current value with zero mismatch): in Figure 6 the variance of the output current is reported as function of the two inputs x and w. The behaviour is due obviously by the technology spread but, what is more, once fixed the technology, it depends on the topology of the circuit and on the size of the devices as shown in the analysis reported in Section 3.

Figure 6: Variance of the output current of the multiplier of Section 3.

CONCLUSIONS

In this paper a mismatch model for MOS translinear loops and current mode multipliers is reported. The model has been experimentally validated and an example of the application of the model to the statistical accuracy analysis of the MOS current mode Gilbert multiplier is reported. Future work will concern also a more accurate modelling of the γ statistics. Acknowledgments

The authors wish to thank Prof. Andrea Trucco for the fruitful discussions. References

[1] C. Toumazou, et al. “Analogue IC Design: the current mode approach” IEE Circuits and Systems. [2] F. Diotalevi, M. Valle, An analog CMOS four quadrant current-mode multiplier for low power artificial neural networks implementation, 15th European Conference on Circuit Theory and Design, ECCTD’01, 2001, pp. III – 325 – III 328 156 (ISBN: 951 – 22 – 5572 – 3). [3] A.G. Andreou and K.A. Boahen, “Translinear Circuits in Subthreshold MOS,” Journal of Analog Integrated Circuits and Signal Processing, Vol. 9, pp. 141-166, March 1996. [4] Drennan and McAndrew, Understanding MOSFET Mismatch for Analog Design, IEEE JSSC 38(3):450-456, March 2003. [5] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, Mc Graw Hill, 1996. [6] B. Razavi, Design of Analog Integrated Circuits, Mc Graw Hill, 2001. [7] M. J. M. Pelgrom, et al., “Matching properties of MOS transistor,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1439, Oct. 1989. [8] A. Pavasonic, et al., “Chacterization of subthreshold MOS mismatch in transistor for VLSI systems,” Analog Integr. Circuits Signal Process., vol. 6, no. 6, pp. 75–85, 1994. [9] A.Graupner, et. al., Statistical Analysis of Parallel Analog Structures, in Proc. of Workshop on System Design Automation - SDA 2000, March 13th-14th, 2000, Rathen, Germany.