Unit 4: Vhdl Signal Model

Unit 4 VHDL SIGNAL MODEL

•bus

•waveforms •Transport and inertial delay •Assignment statements • more on Variables and signals

•delta and simulation

•How VHDL simulator works

Event Driven Simulation and the first encounter with delta

Simulation Loop is based on executing signals from time queue

Process Triggering

Some Rules for Processes

These rules have to be remembered. Our next slides will explain better why it is so…

An Infinite Loop

Remember: processes repeat indefinitely with new data coming. But here is not new data

A Common Error of users

• It is safe to add all input signals from your circuit to the sensitivity list. You may only slow down the simulator.

Delta Time

Two-Dimensional Time

A Delta-Time Infinite Loop

• This is wrong way to make a clock.

Behavioral Modeling in VHDL • VHDL behavior – Sequential Statements – Concurrent Statements

These are two fundamental behaviors from which all simulation and synthesis models work

VHDL behavior models:

concurrent

sequential

Sequential v.s. Concurrent Statements • VHDL is inherently a concurrent language – All VHDL processes execute concurrently – Concurrent signal assignment statements are actually one-line processes – Processes are re-executed if any signal in its sensitivity list is changed

• VHDL statements execute sequentially within a process • Concurrent processes with sequential execution within a process offers maximum flexibility – Supports various levels of abstraction – Supports modeling of concurrent and sequential events as observed in real systems

VHDL behavior: Concurrent, sequential and processes

Concurrent Statements

Concurrent Statements •

Basic granularity of concurrency is the process

– Processes are executed concurrently – Concurrent signal assignment statements are one-line processes •

Mechanism for achieving concurrency : – Processes communicate with each other via signals – Signal assignments require delay before new value is assumed – Simulation time advances when all active processes complete – Effect is concurrent processing • i.e. order in which processes are actually executed by simulator does not affect behavior

•

Other than in last slide Concurrent VHDL statements include : – Block, process, assert, component instantiation

Processes

Behavioral sequential statements

What specifically are the sequential statements?

Initialization of processes

Execution of parallel processes

•

The processes here have no sensitivity list but have wait statements

Model of Processes: waiting for events to occur

Signals and variables in Processes

Communication Between Processes via Signals

These are executed when first process allows

All these assignments executed in no time

Many assignment Statements D1 Many assignment statements

Wait until D=‘1’

Wait 10nS Diagrams like this are useful to visualize time in processes and how they interact

Process FIRST

Process NEXT

Another example

A <= 8 V=1

D1

Wait until D=‘1’

Wait 10nS From next iteration of process NEXT

D0

From first iteration of process NEXT

Wait 10nS

V0 Process FIRST

2

10

D=1

D=1

D=0

A=8

A=8

A=8

V=1 -> 0

V=0

V=1

0

Wait 2nS

From next iteration of process NEXT

Process NEXT

V=0

D=1

2nS 10nS

10nS

D=0

A=8,V=1

Signals Communicate in Between the Processes: signals propagate when processes are waiting

Signals propagate within processes and between processes!

Signals Assigned After Processes Run: waiting processes can awake another processes

Example of role of WAIT in a process

No delay of elements

Assignment of value to signal C will be discussed in next slides

Observe that there is no sensitivity list here. When A or B change, new value of variable TEMP is immediately calculated. It is used to calculate output signal C, not shown. This is just a trivial example. More will come.

Process with Signals

Sensitivity List

It is important to understand that change of c will not initiate the process here!

Process with Sensitivity List We declare arbitrary delays

You can use variables to simplify description or define exact timing

Compilation and Simulation of VHDL Code •

Compiler (Analyzer) – checks the VHDL source code – does it conforms with VHDL syntax and semantic rules – are references to libraries correct

• •

Intermediate form used by a simulator or by a synthesizer Elaboration – create ports, allocate memory storage, create interconnections, ... – establish mechanism for executing of VHDL processes

compilation Internal data structures

synthesis

VHDL Modeling Concepts • Semantics (meaning) of VHDL is heavily based on SIMULATION • A design is described as a set of interconnected modules

• A module could be another design (component) or could be described as a sequential program (process)

VHDL Program Structure: visualization of concurrency These modules are simulated concurrently through signals

This means that they are all simulated in the same time before next delta comes

A general VHDL design with modules: another visualization of concurrency I1 I2

s1 I1

Entity … is … End entity;

O1 IO1

concurrent assignment

component

O1 architecture … of … is ... begin … end;

s2 s3

s8

s4

s6 I2

process 1

s5

process 2

s9

concurrent assignment

IO1

s7

This diagram helps to visualize how process communication works - concurrency

VHDL Simulator stop

start

Init t=0

more event

get earliest event

delta delay

advance time

update signals

during process execution, new events may be added

execute triggered processes

This diagram helps to visualize how process communication works concurrency

Process Statements • FORMAT PROCESS_LABEL: process Flow of -- declarative part declares functions, procedures, types, constants, variables, control etc begin -- Statement part sequential statement; sequential statement; wait statement; -- eg. Wait for 1 ms; or wait on ALARM_A; sequential statement; … wait statement; This diagram helps to end process; visualize how process communication works concurrency

Modeling Timing in VHDL •

VHDL can be used to specify different aspects of timing characteristics of hardware devices: – propagation delay of signals – operational time

• Why we need timing? – The type “time” is a pre-defined physical type. – Mainly useful for modeling device timing characteristics – Can also be used to specify timing requirements, e.g., setup and hold times of devices. – You can parameterize timing properties of an entity.

EXAMPLE: Process Declaration of Clock Generator Clock_gen: process (clk) is begin if clk = ‘0’ then 2*T_pw

clk <= ‘1’ after T_pw, ‘0’ after 2*T_pw; endif;

end process clock_gen; T_pw

Waveform and Driver • Simulator uses drivers for signals • A driver of a signal contains a current value and a waveform representing projected future values. • Waveform elements are appended to a driver whenever a signal assignment is executed.

How to describe a waveform? Use “after”

Using Nested IFs and ELSEIFs Simulator has also to understand semantics of statements like IF Advise is to draw yourself flowchart like this to understand better

What Happens in Simulation?

After examples discussed, we now understand better what are events and how they are scheduled. Details of implementation are not important at this time.

Timing Model in VHDL

Timing Model in VHDL • VHDL uses a simulation cycle to model the stimulus and response nature of digital hardware Start Simulation

Update Signals

We will introduce 3 models for delay

Delay Execute Processes End Simulation

Types of Delay in VHDL •

All VHDL signal assignment statements prescribe an amount of time that must transpire before the signal assumes its new value

•

This prescribed delay can be in one of three forms: •

• •

Transport -- prescribes propagation delay only Inertial -- prescribes minimum input pulse width and propagation delay Delta -- the default if no delay time is explicitly specified

Input dela y

Output

Concepts of Delays and Timing • The time dimension in the signal assignment refers to simulation time in a discrete event simulation • There is a simulation time clock • When a signal assignment is executed, the delay specified is added to current simulation time to determine when new value is applied to signal – Schedules a transaction for the signal at that time

output

input

More on inertial and transport models •

Inertial delay – Model the time lag between stable inputs and valid output of a device – Representative of combinational logic elements – Pulses smaller than transmission delay are suppressed

– Default model for VHDL descriptions

•

Transport delay – Model a pure delay mechanism – All pulses are transmitted – Used for transmission lines or elements with clock- cycle latency

Inertial versus transport delay

How small should be the glitch to be distinguished by inertial and transport? We will answer in next slides Observe the spike is lost in A when we use AFTER

Observe the spike is NOT lost in B when we use TRANSPORT

Transport Delay • Delay must be explicitly specified by user – Keyword “TRANSPORT” must be used

Under this model, ALL input signal changes are reflected at the output

• Signal will assume its new value after specified delay -- TRANSPORT must be specified Output <= TRANSPORT NOT Input AFTER 10 ns;

Input

Output Input

As we see, spikes are not lost

Output 0 35

5

10

15

20

25

30

Specifying Delays: Inertial Model • Inertial Delay Model – reflects physical inertia of physical systems – glitches of very small duration not reflected in outputs

• SIG_OUT <= not SIG_IN after 7 nsec --implicit • SIG_OUT <= inertial ( not SIG_IN after 7 nsec ) • Logic gates exhibit lowpass filtering 10ns

3 ns

SIG_IN

2ns SIG_OUT 9 ns

19 ns

Inertial Delay • Provides for specification of input pulse width, i.e. ‘inertia’ of output, and propagation delay : target <= [REJECT time_expression] INERTIAL waveform;

• Inertial delay is default and REJECT is optional : Output <= NOT Input AFTER 10 ns; -- Propagation delay and minimum pulse width are 10ns

Input

Here reject is not used

Output Input Output

Here we do not write INERTIAL because it is a default. Signal shorter than 10ns is avoided

0 35

5

10

15

20

25

30

Inertial Delay with REJECT •Note that REJECT feature is new to VHDL 1076-1993

• Example of gate with ‘inertia’ smaller than propagation delay – e.g. Inverter with propagation delay of 10ns which Output <= REJECT INERTIAL suppresses pulses5ns shorter thanNOT 5nsInput AFTER 10ns; Example of gate with ‘inertia’ smaller than propagation delay e.g. Inverter with propagation delay of 10ns which suppresses pulses shorter than 5ns

Input Output 0 35

5

10

15

20

25

30

Because here we clearly specify REJECT 5ns, only signals 5ns or shorter are rejected and 7ns is not rejected

A problem with inertial delay Output has propag ation delay of 4ns

buffer

How the simulator works. Delta

Delta Delay • Delta Delay is the default signal assignment propagation delay in case that no delay is explicitly prescribed – VHDL signals assignment cannot take place immediately – Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at some future time – E.g. Output <= NOT Input; -- Output assumes new value in one delta cycle

• Delta delay supports a model of concurrent VHDL process execution – Order in which processes are executed by simulator does not affect simulation output

Delta Delay An Example without Delta Delay • What is the behavior of C? IN: 1->0

A

C We do not like such idea of simulator

B 1 NAND gate evaluated first: IN: 1->0 A: 0->1 B: 1->0 C: 0->0

AND gate evaluated first: IN: 1->0 A: 0->1 C: 0->1 Glitch generated B: 1->0 C: 1->0

Delta Delay An Example with Delta Delay • What is the behavior of C? A

IN: 1->0

C

B 1 Using delta delay scheduling Time 0 ns

Delta 1

2 3 4 1 ns

Event IN: 1->0 eval INVERTER A: 0->1 eval NAND, AND B: 1->0 C: 0->1 eval AND C: 1->0

Gates that are successors of gate that changed signal value are evaluated

Clock changes from 0 to 1

As we see in this example the result of simulation depends on order of evaluating gates. This is bad.

Time modellingdelta delay . 1. What is wrong with old simulators? With this order of evaluation a glitch in signal D is created which means clocking One more clock is generated - this is bad.

As we see, timing behavior simulated depends on the gate evaluation order

AND first evaluation

NAND first evaluation

This is good again

This is levelized evaluation from inputs to outputs

Time modellingdelta delay . Delta delay of VHDL solves the problem. • Many delta units of time passed but only one unit of time reported to the user delta

Delta is as close to zero as we want

Delta Delay: instability time • If no delay time is specified, a delta delay is assumed for any signal assignment. • Delta delay represents an infinitesimal delay, less than any measurable time (i.e., femtoseconds), but still larger than zero. • An example These are moments of time

This example shows use of delta to simulate latch. Here delay is declared using after

5ns Black are instability times

Signals vs Variables: signal used for Out_1 • A key difference between variables and signals is the assignment delay ARCHITECTURE sig_ex OF test IS SIGNAL a, b, c, out_1, out_2 : BIT; BEGIN PROCESS (a, b, c, out_1) BEGIN a out_1 <= a NAND b; out_2 <= out_1 XOR c; b END PROCESS; END sig_ex; c Time

a

b

c

out_1

out_2

0 1 1+d 1+2d

0 1 1 1

1 1 1 1

1 1 1 1

1 1 0 0

0 0 0 1

Symbol d represents delta

signal Out_1 Out_2 time

a b c out_1 out_2 0

1

1+d

1+2d

Signals vs Variables (Cont.): Variable used for out_3 ARCHITECTURE var_ex OF test IS SIGNAL a,b,c,out_4 : BIT; BEGIN PROCESS (a, b, c) VARIABLE out_3 : BIT; BEGIN out_3 := a NAND b; out_4 <= out_3 XOR c; END PROCESS; END var_ex; Time

a

b

c

out_3

out_4

0 1 1+d

0 1 1

1 1 1

1 1 1

1 0 0

0 0 1

variable a b

Out_3 Out_4

c

Out_3 is a variable so the change is immediate as shown by red arrow

This example has no any other meaning, it just has to explain the timing of variables and signals in a simulator

a b c out_3

a,b,c,out_4 are signals but out_3 is a variable

out_4 0

1

1+d

Delta Delay and the simulator in more detail • If no future time is specified, VHDL automatically assumes a small time delay. – This delay is the delta delay. – The smallest unit of time i.e. 0 fs.

• Delta causes changes to occur only in the future • Delta is consistent with the definition of signals. • Mechanism – Assignment schedules a transaction – The transaction is applied after the process suspends. – Process does not see the effect until it resumes next time.

How it works? • Recollect simulator kernel. • Two phases : – Signal update phase

– Process execution phase.

• Signal update phase updates the values of the signals at the current simulation time.

• This may trigger events. • Process execution phase responds to the events and they execute.

Why Delta Delay? • Assignments are done in the process execution phase. Eg. X <= 10; • Transaction is not applied immediately.

• It can be done only in the signal update phase. • When all processes are suspended, simulation time is updated. • Only now is the transaction applied.

Simulation Cycle Revisited Sequential vs Concurrent Statements • VHDL is inherently a concurrent language – All VHDL processes execute concurrently – Concurrent signal assignment statements are actually one-line processes

• VHDL statements execute sequentially within a process

• Concurrent processes with sequential execution within a process offers maximum flexibility – Supports various levels of abstraction – Supports modeling of concurrent and sequential events as observed in real systems

This example will illustrate simulating a 4-bit Adder

Here is the structural description of 4-bit Adder

4-bit Adder – Simulation and analysis of deltas

Next example will show Modeling Flip-Flops Using VHDL Processes General form of process

• Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time

JK Flip-Flop Model

Animation and details in next slide

Notes to the JK Flip-Flop Model

Another simulation example to Recall on Delta Delay • Default signal assignment propagation delay if no delay is explicitly prescribed – VHDL signal assignments do not take place immediately – Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at a future time – E.g. Output <= NOT Input; -- Output assumes new value in one delta cycle

• Supports a model of concurrent VHDL process execution – Order in which processes are executed by simulator does not affect simulation output

Simulation Example illustrating delta

Queue for A

Queue for B

Illustration of force and timing diagram in Simulation of the VHDL Model Simulation command file: Force clk

Force X

Waveforms:

All forced signals here

Structural Model of State Machine

Package bit_pack is a part of library BITLIB – includes gates, flip-flops, counters

Simulation of the Structural Model Simulation command file:

Waveforms:

One More Simulation Example: gate timing

Continued

VHDL simulation of gates with delays

From force

The same circuit but another description for simulation Now simulator reacts to changes of si signals

• Order does not matter because we are in architecture and we are executing concurrent statements and not inside a process!

Now we see internal delays

Third description of this example

Change of si creates no event for this process

Differences between CSA and Process Change of out1, out2 repeats simulation

Change of out1, out2 does not repeat simulation

X is signal

Signals and Variables X is variable X is variable so changes immediately and next equation takes new value and not old value as in the code from the left

Variables • Can be altered using variable assignment statements • Updating takes place immediately • Can be declared only within Processes and Functions

• Variables Inside Processes • Variables inside processes are static • Assigned value is stored till next call. • Variables inside functions and procedures are not static

Signals • Represent data values on physical lines in circuits. • Models the response in actual circuits accurately – Does not change values immediately.

• Assignment does not affect the value immediately. – Always occurs sometime in the future – can be at the same simulation time though.

• Future time at which signal is affected can be explicitly stated. Waveform can also be specified.

•Variable assignment statement •Signal assignment •wait

Sequential Statements • Variable assignment statement • Signal assignment • If statement • Case statement • Loop statement • Next statement

• Exit statement • Null statement • Procedure call statement • Return statement • Assertion statement

Variable assignment statement Variable_assignment_statement ::= target:=expression; architecture RTL of VASSIGN is signal A, B, J : bit_vector(1 downto 0); signal E, F, G : bit; begin p0 : process (A, B, E, F, G, J) variable C, D, H, Y : bit_vector(1 downto 0); variable W, Q : bit_vector(3 downto 0); variable Z : bit_vector(0 to 7); variable X : bit; variable DATA : bit_vector(31 downto 0); begin ... end process end RTL;

We declare various types of variables inside the process

Variable assignment statement signal A, B, J : bit_vector(1 downto 0); signal E, F, G : bit;

• p0 : process (A, B, E, F, G, J) • -- A, B, J, D, H : bit_vector -- E, F, G : bit • begin Variable assigned to a signal • C := "01"; • X := E nand F; The same signal concatenation • Y := H or J; G (a bit) goes to • Z(0 to 3) := C & D; two bits • Z(4 to 7) := (not A) & (A nor B); • D := ('1', '0'); • W := (2 downto 1 => G, 3 => '1', others => '0'); • DATA := (others => '0'); • end process; Here we assign signals to variables

Make note of mapping notation.. Bit G assigned to two bits.

Formal Syntax of a signal assignment statement VHDL syntax description in metalanguage Signal_assignment_statement ::= target<=[transport]waveform_element{,waveform_element};

waveform_element::= value_expression[after time_expression]|null[after time_expression]

WAIT STATEMENT AND TIMING Perhaps the most difficult to understand statement of VHDL. If you do not understand it , you will have troubles to interpret timing results from simulation and you will be not able to do good behavioral descriptions

WAIT statement Three types of WAIT

Common student mistake, may be because of syntax mistake

Example of WAIT statement

The wait statement

Equivalent Processes

“Wait Until” and “Wait for”

Signal Declarations • Signals must not be declared inside a process or subprogram.

• Ports must always be signals. • Models sub-system communication correctly.

Example: Variables vs signals • Signal X is changing outside the process, not shown how.

Wait Statements • ... an alternative to a sensitivity list – Note: a process cannot have both wait statement(s) and a sensitivity list • Generic form of a process with wait statement(s) process begin sequential-statements wait statement sequential-statements wait-statement ... end process;

How wait statements work? • Execute seq. statement until a wait statement is encountered. • Wait until the specified condition is satisfied. • Then execute the next set of sequential statements until the next wait statement is encountered. • ... • When the end of the process is reached start over again at the beginning.

Forms of Wait Statements wait on sensitivity-list; wait for time-expression; wait until boolean-expression;

• Wait on – until one of the signals in the sensitivity list changes

• Wait for – waits until the time specified by the time expression has elapsed

– What is this: wait for 0 ns;

• Wait until – the Boolean expression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUE

p0 : process (A, B) begin Y <= A nand B after 10 ns; X <= transport A nand B after 10 ns; end process; p1 : process begin A <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; B <= '0', '1' after 30 ns, '0' after 35 ns, '1' after 50 ns; wait for 80 ns; end process;

Signal assignment statements and wait for Switching time of circuit p0

80nS

A B X Y

A pulse with a duration shorter than the switching time of the circuit (10nS) will be transmitted in transport.

Recall waveforms , transport and inertial delay. Recall that default is intertial, as shown for signal X

Signal assignment statement A pulse (5 nS) with a duration shorter than the switching time of the circuit (10nS) will be transmitted in transport.

Inertial and Transport Delays

entity DELAY is end DELAY; architecture RTL of DELAY is signal A, B, X, Y : bit; begin p0 : process (A, B) begin Y <= A nand B after 10 ns; X <= transport A nand B after 10 ns; end process;

X Y

p1 : process begin A <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; B <= '0', '1' after 30 ns, '0' after 35 ns, '1' after 50 ns; wait for 80 ns; end process; end RTL;

Role of wait for in discarding signals Waiting 30ns to start next assignment

30ns

entity DRIVER is end DRIVER; architecture RTL of DRIVER is signal A : integer; begin pa : process begin

Waiting 50ns to start next assignment. 30 + 50 = 80

20ns

A <= 3, 5 after 20 ns, 7 after 40 ns, 9 after 60 ns; Discarded by the end of first assignment to A wait for 30 ns; A <= 2, 4 after 20 ns, 6 after 40 ns, 8 after 60 ns; wait for 50 ns; end process; Discarded by the end of end RTL; the second assignment

This slide explains the role of wait for to discard part of assignment statement

to A. Time 30+50=80 has passed

Differences between variables and signals There are differences where declared and when updated

1. Where declared – Local variables are declared and only visible inside a process or a subprogram. – Signals cannot be declared inside a process or a subprogram.

2. When updated • A local variable is immediately updated when the variable assignment statement is executed. • A signal assignment statement updates the signal driver. • The new value of the signal is updated when the process is

Differences between variables and Signal assignment statement signals 3. Variables are cheaper to implement in VHDL simulation since the evaluation of drivers is not needed. – Variables require less memory.

4. Signals communicate among concurrent statements. – Ports declared in the entity are signals. – Subprogram arguments can be signals or variables.

5. A signal is used to indicate an interconnect (net in a schematic). – A local variable is used as a temporary value in a function

Signals versus variables 6. A local variable is very useful to factor out common parts of complex equations to reduce the mathematical calculation. 7. Right-hand sides: – The right-hand side of a variable assignment statement is an expression. – There is no associated time expression. – The right-hand side of a signal assignment statement is a sequence of waveform elements with associated time expressions.

Signals and variables in timing diagrams entity SIGVAL is port ( CLK, D : in bit; FF2, FF3 : out bit; Y : out bit_vector(7 downto 0)); end SIGVAL; architecture RTL of SIGVAL is signal FF1, SIG0, SIG1 : bit; begin p0 : process (D, SIG1, SIG0) variable VAR0, VAR1 : bit;

Variables and signals on left

begin VAR0 := D; Variables and signals on VAR1 := D; right SIG0 <= VAR0; SIG1 <= VAR1; Y(1 downto 0) <= VAR1 & VAR0; Y(3 downto 2) <= SIG1 & SIG0; VAR0 := not VAR0; VAR1 := not VAR1; SIG0 <= not VAR0; SIG1 <= not D; Y(5 downto 4) <= VAR1 & VAR0; Y(7 downto 6) <= SIG1 & SIG0; end process;

Timing of variables versus timing of signals FF2 is old value of FF1 according to signal semantics

p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process; p2 : process variable V3 : bit; begin wait until CLK'event and CLK = '1'; V3 := D; FF3 <= V3; end process; end RTL; •Variable V3 changes at the same time as FF1, and so FF3 • FF3 unlike FF2

CLK

D VAR0 VAR1

SIG0 SIG1

Y FF1 FF2 V3 FF3

MORAL: Signals are scheduled, variables change immediately

p0 : process (D, SIG1, SIG0

WAIT

variable VAR0, VAR1 : bit;

D

D Q

D Q

FF1

FF2

c

c Process 1

clk

var0

D

clk

V3

D Q FF3

c Process 2

Process Po

begin VAR0 := D; VAR1 := D; SIG0 <= VAR0; SIG1 <= VAR1; Y(1 downto 0) <= VAR1 & VAR0; Y(3 downto 2) <= SIG1 & SIG0; VAR0 := not VAR0; VAR1 := not VAR1; SIG0 <= not VAR0; SIG1 <= not D; Y(5 downto 4) <= VAR1 & VAR0; Y(7 downto 6) <= SIG1 & SIG0; end process;

p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process;

p2 : process variable V3 : bit; begin wait until CLK'event and CLK = '1'; V3 := D; FF3 <= V3; end process; end RTL;

Using FF1, a signal, the old value is substituted

Using V3, a variable, the new value is substituted

p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process; p2 : process variable V3 : bit; begin wait until CLK'event and CLK = '1'; V3 := D; FF3 <= V3; end process; end RTL; Compare FF2 (from signal change) and FF3 (from variable change)

CLK

D VAR0 VAR1

SIG0 SIG1

Y FF1 FF2 V3 FF3

p0 : process (D, SIG1, SIG0)

variable VAR0, VAR1 : bit; begin VAR0 := D; VAR1 := D; SIG0 <= VAR0; SIG1 <= VAR1; Y(1 downto 0) <= VAR1 & VAR0; Y(3 downto 2) <= SIG1 & SIG0; VAR0 := not VAR0; VAR1 := not VAR1; SIG0 <= not VAR0; SIG1 <= not D; Y(5 downto 4) <= VAR1 & VAR0; Y(7 downto 6) <= SIG1 & SIG0; end process;

Input signals

• • • • •

p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process;

SIG0 changes with D, no delay, in process 1 D, SIG0 and SIG1 are in sensitivity list

p2 : process variable V3 : bit; begin wait until CLK'event and CLK = '1'; V3 := D; FF3 <= V3; end process; end RTL;

FF1 takes old D V3 takes new D

Three architectures entity TEMP is end TEMP; architecture RTL of TEMP is signal A, B, C, D, E, F, G, Y, Z : integer; begin p0 : process (A, B, C, D, E, F, G) begin Y <= A + (B*C + D*E*F + G); Z <= A - (B*C + D*E*F + G); end process; end RTL; architecture RTL1 of TEMP is signal A, B, C, D, E, F, G, Y, Z : integer; begin p0 : process (A, B, C, D, E, F, G)

v calculated variable V : integer; immediately begin V := (B*C + D*E*F + G); Y <= A + V; Z <= A - V; The same end process; statements end RTL1; architecture RTL2 of TEMP is signal A, B, C, D, E, F, G, Y, Z : integer; signal V : integer; begin p0 : process (A, B, C, D, E, F, G) begin V <= (B*C + D*E*F + G); Uses old value Y <= A + V; Z <= A - V; of v, because it end process; is a signal end RTL2;

First architecture has no variables Second architecture uses variable V Third architecture uses additional signal V Their operation is different because signal V is scheduled and variable immediately assigned

Signal Declarations • Signals must not be declared inside a process or subprogram.

• Ports must always be signals. • Models sub-system communication correctly.

Signals - Drivers • Value holder for a signal. • Created when signal assignments schedule some value at some future time. • Every signal has a separate driver. – Can be thought of as a source for a signal.

• Driver maintains an ordered list of transactions. – Recollect transaction is assignment made to a signal.

• Simulator uses the value of the signal stored in the driver.

Multiple Drivers • Signals may be updated in more than 1 process at the same time. • There may be more than 1 driver for the same signal, one for each process. • The values assigned may be same or different. • What to do if the values are different?

Multiple Drivers - Resolution • 􀂃 Resolution function is the solution. • 􀂃 This function resolves the value of the signal. • 􀂃 This function must resolve all possible pairs of values that two drivers may assign. • 􀂃 The signal being resolved is called the resolved signal. • 􀂃 The resolution function can be attached to – 􀂃 – 􀂃

A signal directly or A data-type itself.

Homework Problem #1 • Using the labels, list the order in which the following signal assignments are evaluated if in2 changes from a '0' to a '1'. Assume in1 has been a '1' and in2 has been a '0' for a long time, and then at time t in2 changes from a '0' to a '1'.

entity not_another_prob is port (in1, in2: in bit; a: out bit); end not_another_prob;

architecture oh_behave of not_another_prob is signal b, c, d, e, f: bit; begin L1: d <= not(in1); L2: c<= not(in2);

L3: f <= (d and in2) ; L4: e <= (c and in1) ; L5: a <= not b; L6: b <= e or f; end oh_behave;

Homework Problem #2 • Under what conditions do the two assignments below result in the same behavior? Different behavior? Draw waveforms to support your answers. out <= reject 5 ns inertial (not a) after 20 ns;

out <= transport (not a) after 20 ns;