Unit 3
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Topics Basic fabrication steps. Transistor structures. Basic transistor behavior behavior. Latch up.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Fabrication services
Educational services: – U.S.: MOSIS – EC: EuroPractice – Taiwan: CIC – Japan: VDEC
Foundry = fabrication line for hire. – Foundries are major source of fab capacity today. Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Fabrication processes
IC built on silicon substrate: – some structures diffused into substrate; – other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO2) is insulator.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Simple cross section SiO2
metal3 metal2 metal1
transistor
via
poly n+
p+
n+ substrate substrate Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Photolithography Mask patterns are put on wafer using photosensitive material:
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub
p-tub substrate
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Process steps, cont’d. Pattern polysilicon before diffusion regions: gate oxide
poly
poly
p-tub
p-tub
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Process steps, cont’d Add diffusions, performing self-masking:
poly n+
p-tub
poly n+
p+
p-tub
p+
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Process steps, cont’d Start adding metal layers: metal 1
metal 1 vias
poly n+
p-tub
Modern VLSI Design 3e: Chapter 2
n+
poly p+
p-tub
p+
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Transistor structure n-type transistor:
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Modern VLSI Design 3e: Chapter 2
0.25 micron transistor (Bell Labs) gate oxide silicide source/drain poly
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Modern VLSI Design 3e: Chapter 2
Transistor layout n-type (tubs may vary): L w
Modern VLSI Design 3e: Chapter 2
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Drain current characteristics
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Modern VLSI Design 3e: Chapter 2
Drain current
Linear region (Vds < Vgs - Vt): – Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2)
Saturation region (Vds >= Vgs - Vt): d > – Id = 0.5k’ (W/L)(Vgs - Vt) 2
Modern VLSI Design 3e: Chapter 2
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0.5 μm transconductances From a MOSIS process: n-type: – kn’ = 73 μA/V2 – Vtn = 0.7 V
p-type: – kp’ = 21 μA/V2 – Vtp = -0.8 V
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Current through a transistor Use 0.5 μm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. g Vgs = 2V: Id = 0.5k’(W/L)(Vgs-Vt)2= 93 μA
Vgs = 5V: Id = 1 mA Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Basic transistor parasitics Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.
Modern VLSI Design 3e: Chapter 2
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Basic transistor parasitics, cont’d Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgdd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.
– Cgs = Col W
Gate/bulk overlap capacitance.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up up, SCRs can turn on, on creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Parasitic SCR
circuit Modern VLSI Design 3e: Chapter 2
I-V behavior Copyright © 1998, 2002 Prentice Hall PTR
Parasitic SCR structure
Modern VLSI Design 3e: Chapter 2
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Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.
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Modern VLSI Design 3e: Chapter 2
Tub tie layout
p+ metal (VDD) p-tub
Modern VLSI Design 3e: Chapter 2
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Topics
Derivation of transistor characteristics.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
MOSFET gate as capacitor
Basic structure of gate is parallel-plate capacitor: gate +
SiO2
Vg
xox
-
substrate
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Modern VLSI Design 3e: Chapter 2
Parallel plate capacitance
Formula for parallel plate capacitance: Cox = εox / xox
Permittivity of silicon: εox = 3.46 x 10-13 F/cm2
Gate capacitance helps determine charge in channel which forms inversion region.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Threshold voltage Components of threshold voltage Vt: Vfb = flatband voltage; depends on difference in work function between gate and substrate and on fixed surface charge. φs = surface potential (about 2φf). Voltage on paralell plate capacitor. Additional ion implantation. Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Body effect Reorganize threshold voltage equation: Vt = Vt0 + ΔVt Threshold voltage is a function of source/substrate voltage Vsb. Body effect γ is the coefficienct for the Vsb dependence factor.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Example: threshold voltage of a transistor Vt0 = Vfb + φs + Qb/Cox + VII = -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0 92 V 0.92 = 0.68 V Body effect γn = sqrt(2qεSiNA/Cox) = 0.1 ΔVt = γn[sqrt(φs + Vsb) - sqrt(Vs)] = 0.16 V Modern VLSI Design 3e: Chapter 2
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More device parameters Process transconductance k’ = μCox. Device transconductance β = k’W/L.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Channel length modulation length parameter λ describes small dependence of drain corrent on Vds in saturation. Factor is measured empirically. empirically New drain current equation:
– Id = 0.5k’ (W/L)(Vgs - Vt) 2(l - λ Vds)
Equation has a discontinuity between linear and saturation regions---small enough to be ignored. Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Gate voltage and the channel gate source
current
drain
Vds < Vgs - Vt
Id
gate source
current
drain
Vds = Vgs - Vt
drain
Vds > Vgs - Vt
Id
gate source Id Modern VLSI Design 3e: Chapter 2
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Leakage and subthreshold current A variety of leakage currents draw current away from the main logic path. The subthreshold current is one particularly important type of leakage current.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Types of leakage current. Weak inversion current (a.k.a. subthreshold current). Reverse Reverse-biased biased pn junctions. junctions Drain-induced barrier lowering. Gate-induced drain leakage; Punchthrough currents. Gate oxide tunneling. Hot carriers.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Subthreshold current
Subthreshold current: – Isub = ke[(Vgs - Vt)/(S/ln 10)][1-e-qVds/kT]
Subthreshold slope S characterizes weak inversion current. Subthreshold current is a function of Vt.
– Can adjust Vt by changing the substrate bias to control leakage.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
The modern MOSFET Features of deep submicron MOSFETs: – epitaxial layer for heavily-doped channel; – reduced area source/drain contacts for lower capacitance; – lightly-doped drains to reduce hot electron effects; – silicided poly, diffusion to reduce resistance.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Circuit simulation Circuit simulators like Spice numerically solve device models and Kirchoff’s laws to determine time-domain circuit behavior. Numerical solution allows more sophisticated models, non-functional (tabledriven) models, etc.
Modern VLSI Design 3e: Chapter 2
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Spice MOSFET models Level 1: basic transistor equations of Section 2.2; not very accurate. Level 2: more accurate model (effective channel length, etc.). Level 3: empirical model. Level 4 (BSIM): efficient empirical model. New models: level 28 (BSIM2), level 47 (BSIM3).
Modern VLSI Design 3e: Chapter 2
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Some (by no means all) Spice model parameters L, W: transistor length width. KP: transconductance. GAMMA: body bias factor factor. AS, AD: source/drain areas. CJSW: zero-bias sidewall capacitance. CGBO: zero-bias gate/bulk overlap capacitance.
Modern VLSI Design 3e: Chapter 2
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Topics Wire and via structures. Wire parasitics. Transistor parasitics parasitics.
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Modern VLSI Design 3e: Chapter 2
Wires and vias metal 3
metal 2
vias metal 1 poly n+
p-tub
Modern VLSI Design 3e: Chapter 2
poly n+
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Metal migration Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.
Modern VLSI Design 3e: Chapter 2
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Metal migration problems and solutions Marginal wires will fail after a small operating period—infant mortality. Normal wires must be sized to accomodate maximum current flow:
Imax = 1.5 mA/μm of metal width.
Mainly applies to VDD/VSS lines.
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Modern VLSI Design 3e: Chapter 2
Diffusion wire capacitance
Capacitances formed by p-n junctions: sidewall capacitances
depletion region
n+ (ND)
substrate (NA)
bottomwall capacitance
Modern VLSI Design 3e: Chapter 2
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Depletion region capacitance
Zero-bias depletion capacitance: – Cj0 = εsi/xd.
Depletion region width: – xd0 = sqrt[(1/NA + 1/ND)2εsiVbi/q].
Junction capacitance is function of voltage across junction: – Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)
Modern VLSI Design 3e: Chapter 2
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Poly/metal wire capacitance
Two components: – parallel plate; – fringe. fringe plate
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Modern VLSI Design 3e: Chapter 2
Metal coupling capacitances
Can couple to adjacent wires on same layer, wires on above/below layers: metal 2
metal 1
metal 1
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Modern VLSI Design 3e: Chapter 2
Example: parasitic capacitance measurement n-diffusion: bottomwall=2 fF, sidewall=2 fF. 1.5 μm metal: plate plate=00.15 15 fF fF, fringe=0.72 fF.
3 μm
0.75 μm
Modern VLSI Design 3e: Chapter 2
1 μm
2.5 μm
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Wire resistance
Resistance of any size square is constant:
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Modern VLSI Design 3e: Chapter 2
Mean-time-to-failure MTF for metal wires = time required for 50% of wires to fail. Depends on current density:
– proportional to j-n e Q/kT – j is current density – n is constant between 1 and 3 – Q is diffusion activation energy
Modern VLSI Design 3e: Chapter 2
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Skin effect At low frequencies, most of copper conductor’s cross section carries current. As frequency increases, increases current moves to skin of conductor.
– Back EMF induces counter-current in body of conductor.
Skin effect most important at gigahertz frequencies.
Modern VLSI Design 3e: Chapter 2
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Skin effect, cont’d
Isolated conductor:
Conductor and ground:
Low frequency Low frequency
High frequency High frequency Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Skin depth
Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: δ = 1/sqrt(π f μ σ) – f = signal frequency μ = magnetic permeability σ = wire conducitvity
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Modern VLSI Design 3e: Chapter 2
Effect on resistance
Low frequency resistance of wire: – Rdc = 1/ σ wt
High frequency resistance with skin effect: – Rhf = 1/2 σ δ (w + t)
Resistance per unit length: – Rac = sqrt(Rdc 2 + κ Rhf 2)
Typically κ = 1.2.
Modern VLSI Design 3e: Chapter 2
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Transistor gate parasitics
Gate-source/drain overlap capacitance: gate t source
drain
overlap
Modern VLSI Design 3e: Chapter 2
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Transistor source/drain parasitics Source/drain have significant capacitance, resistance. Measured same way as for wires. wires Source/drain R, C may be included in Spice model rather than as separate parasitics.
Modern VLSI Design 3e: Chapter 2
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Topics Design rules and fabrication. SCMOS scalable desgn rules. Stick diagrams diagrams.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Why we need design rules Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.
Modern VLSI Design 3e: Chapter 2
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Manufacturing problems Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.
Modern VLSI Design 3e: Chapter 2
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Transistor problems
Varaiations in threshold voltage: – oxide thickness; – ion implanatation; – poly variations.
Changes in source/drain diffusion overlap. Variations in substrate.
Modern VLSI Design 3e: Chapter 2
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Wiring problems Diffusion: changes in doping -> variations in resistance, capacitance. Poly, Poly metal: variations in height, height width -> > variations in resistance, capacitance. Shorts and opens:
Modern VLSI Design 3e: Chapter 2
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Oxide problems
Variations in height. Lack of planarity -> step coverage. metal t l2 metal 2
Modern VLSI Design 3e: Chapter 2
metal 1
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Via problems Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short. short
Modern VLSI Design 3e: Chapter 2
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MOSIS SCMOS design rules Designed to scale across a wide range of technologies. Designed to support multiple vendors. vendors Designed for educational use. Ergo, fairly conservative.
Modern VLSI Design 3e: Chapter 2
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λ and design rules λ is the size of a minimum feature. Specifying λ particularizes the scalable rules rules. Parasitics are generally not specified in λ units.
Modern VLSI Design 3e: Chapter 2
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Wires 6
metal 3
3
metal 2
3
metal 1
3
pdiff/ndiff
2
poly Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Transistors 2 2
3
3 1 5
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Modern VLSI Design 3e: Chapter 2
Vias
Types of via: metal1/diff, metal1/poly, metal1/metal2. 4
4 1 2
Modern VLSI Design 3e: Chapter 2
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Metal 3 via Type: metal3/metal2. Rules:
– cut: 3 x 3 – overlap by metal2: 1 – minimum spacing: 3 – minimum spacing to via1: 2
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Modern VLSI Design 3e: Chapter 2
Tub tie
4 1
Modern VLSI Design 3e: Chapter 2
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Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4
Modern VLSI Design 3e: Chapter 2
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Overglass Cut in passivation layer. Minimum bonding pad: 100 μm. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15
Modern VLSI Design 3e: Chapter 2
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Stick diagrams A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties) ties), relative placement placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
Modern VLSI Design 3e: Chapter 2
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Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff
Modern VLSI Design 3e: Chapter 2
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Dynamic latch stick diagram VDD
in
out
VSS phi
phi’
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Modern VLSI Design 3e: Chapter 2
Sticks design of multiplexer
Start with NAND gate: +
out b
Modern VLSI Design 3e: Chapter 2
a
Copyright © 1998, 2002 Prentice Hall PTR
NAND sticks VDD a
out
b
VSS Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
One-bit mux sticks VDD ai bi
a
a
N1 (NAND)
a outt
select
select’
outt
out
N1 (NAND)
b
N1 (NAND)
b
b
VSS Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
3-bit mux sticks select’
select select’
b2
ai bi
a1
ai
b1
bi
a0
ai
b0
bi
a2
select
m2(one-bit-mux)
select’
select
m2(one-bit-mux) select’
Modern VLSI Design 3e: Chapter 2
select
m2(one-bit-mux)
VDD oi VSS
o2
VDD oi VSS
o1
VDD oi VSS
o0
Copyright © 1998, 2002 Prentice Hall PTR
Layout design and analysis tools Layout editors are interactive tools. Design rule checkers are generally batch--identify DRC errors on the layout. layout Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Automatic layout Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea-of-gates cell/sea of gates layout creates layout from predesigned cells + custom routing.
– Sea-of-gates allows routing over the cell.
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Modern VLSI Design 3e: Chapter 2
Standard cell layout
Modern VLSI Design 3e: Chapter 2
routing area
routing area
routing area
routing g area
Copyright © 1998, 2002 Prentice Hall PTR
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Fabrication services
Educational services: – U.S.: MOSIS – EC: EuroPractice – Taiwan: CIC – Japan: VDEC
Foundry = fabrication line for hire. – Foundries are major source of fab capacity today. Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Fabrication processes
IC built on silicon substrate: – some structures diffused into substrate; – other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO2) is insulator.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Simple cross section SiO2
metal3 metal2 metal1
transistor
via
poly n+
p+
n+ substrate substrate Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Photolithography Mask patterns are put on wafer using photosensitive material:
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub
p-tub substrate
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Process steps, cont’d. Pattern polysilicon before diffusion regions: gate oxide
poly
poly
p-tub
p-tub
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Process steps, cont’d Add diffusions, performing self-masking:
poly n+
p-tub
poly n+
p+
p-tub
p+
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Process steps, cont’d Start adding metal layers: metal 1
metal 1 vias
poly n+
p-tub
Modern VLSI Design 3e: Chapter 2
n+
poly p+
p-tub
p+
Copyright © 1998, 2002 Prentice Hall PTR
Transistor structure n-type transistor:
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
0.25 micron transistor (Bell Labs) gate oxide silicide source/drain poly
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Transistor layout n-type (tubs may vary): L w
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Drain current characteristics
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Drain current
Linear region (Vds < Vgs - Vt): – Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2)
Saturation region (Vds >= Vgs - Vt): d > – Id = 0.5k’ (W/L)(Vgs - Vt) 2
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
0.5 μm transconductances From a MOSIS process: n-type: – kn’ = 73 μA/V2 – Vtn = 0.7 V
p-type: – kp’ = 21 μA/V2 – Vtp = -0.8 V
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Current through a transistor Use 0.5 μm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. g Vgs = 2V: Id = 0.5k’(W/L)(Vgs-Vt)2= 93 μA
Vgs = 5V: Id = 1 mA Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Basic transistor parasitics Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Basic transistor parasitics, cont’d Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgdd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.
– Cgs = Col W
Gate/bulk overlap capacitance.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up up, SCRs can turn on, on creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Parasitic SCR
circuit Modern VLSI Design 3e: Chapter 2
I-V behavior Copyright © 1998, 2002 Prentice Hall PTR
Parasitic SCR structure
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Tub tie layout
p+ metal (VDD) p-tub
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Topics
Derivation of transistor characteristics.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
MOSFET gate as capacitor
Basic structure of gate is parallel-plate capacitor: gate +
SiO2
Vg
xox
-
substrate
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Parallel plate capacitance
Formula for parallel plate capacitance: Cox = εox / xox
Permittivity of silicon: εox = 3.46 x 10-13 F/cm2
Gate capacitance helps determine charge in channel which forms inversion region.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Threshold voltage Components of threshold voltage Vt: Vfb = flatband voltage; depends on difference in work function between gate and substrate and on fixed surface charge. φs = surface potential (about 2φf). Voltage on paralell plate capacitor. Additional ion implantation. Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Body effect Reorganize threshold voltage equation: Vt = Vt0 + ΔVt Threshold voltage is a function of source/substrate voltage Vsb. Body effect γ is the coefficienct for the Vsb dependence factor.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Example: threshold voltage of a transistor Vt0 = Vfb + φs + Qb/Cox + VII = -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0 92 V 0.92 = 0.68 V Body effect γn = sqrt(2qεSiNA/Cox) = 0.1 ΔVt = γn[sqrt(φs + Vsb) - sqrt(Vs)] = 0.16 V Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
More device parameters Process transconductance k’ = μCox. Device transconductance β = k’W/L.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Channel length modulation length parameter λ describes small dependence of drain corrent on Vds in saturation. Factor is measured empirically. empirically New drain current equation:
– Id = 0.5k’ (W/L)(Vgs - Vt) 2(l - λ Vds)
Equation has a discontinuity between linear and saturation regions---small enough to be ignored. Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Gate voltage and the channel gate source
current
drain
Vds < Vgs - Vt
Id
gate source
current
drain
Vds = Vgs - Vt
drain
Vds > Vgs - Vt
Id
gate source Id Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Leakage and subthreshold current A variety of leakage currents draw current away from the main logic path. The subthreshold current is one particularly important type of leakage current.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Types of leakage current. Weak inversion current (a.k.a. subthreshold current). Reverse Reverse-biased biased pn junctions. junctions Drain-induced barrier lowering. Gate-induced drain leakage; Punchthrough currents. Gate oxide tunneling. Hot carriers.
Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Subthreshold current
Subthreshold current: – Isub = ke[(Vgs - Vt)/(S/ln 10)][1-e-qVds/kT]
Subthreshold slope S characterizes weak inversion current. Subthreshold current is a function of Vt.
– Can adjust Vt by changing the substrate bias to control leakage.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
The modern MOSFET Features of deep submicron MOSFETs: – epitaxial layer for heavily-doped channel; – reduced area source/drain contacts for lower capacitance; – lightly-doped drains to reduce hot electron effects; – silicided poly, diffusion to reduce resistance.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Circuit simulation Circuit simulators like Spice numerically solve device models and Kirchoff’s laws to determine time-domain circuit behavior. Numerical solution allows more sophisticated models, non-functional (tabledriven) models, etc.
Modern VLSI Design 3e: Chapter 2
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Spice MOSFET models Level 1: basic transistor equations of Section 2.2; not very accurate. Level 2: more accurate model (effective channel length, etc.). Level 3: empirical model. Level 4 (BSIM): efficient empirical model. New models: level 28 (BSIM2), level 47 (BSIM3).
Modern VLSI Design 3e: Chapter 2
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Some (by no means all) Spice model parameters L, W: transistor length width. KP: transconductance. GAMMA: body bias factor factor. AS, AD: source/drain areas. CJSW: zero-bias sidewall capacitance. CGBO: zero-bias gate/bulk overlap capacitance.
Modern VLSI Design 3e: Chapter 2
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Topics Wire and via structures. Wire parasitics. Transistor parasitics parasitics.
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Modern VLSI Design 3e: Chapter 2
Wires and vias metal 3
metal 2
vias metal 1 poly n+
p-tub
Modern VLSI Design 3e: Chapter 2
poly n+
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Metal migration Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.
Modern VLSI Design 3e: Chapter 2
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Metal migration problems and solutions Marginal wires will fail after a small operating period—infant mortality. Normal wires must be sized to accomodate maximum current flow:
Imax = 1.5 mA/μm of metal width.
Mainly applies to VDD/VSS lines.
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Modern VLSI Design 3e: Chapter 2
Diffusion wire capacitance
Capacitances formed by p-n junctions: sidewall capacitances
depletion region
n+ (ND)
substrate (NA)
bottomwall capacitance
Modern VLSI Design 3e: Chapter 2
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Depletion region capacitance
Zero-bias depletion capacitance: – Cj0 = εsi/xd.
Depletion region width: – xd0 = sqrt[(1/NA + 1/ND)2εsiVbi/q].
Junction capacitance is function of voltage across junction: – Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)
Modern VLSI Design 3e: Chapter 2
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Poly/metal wire capacitance
Two components: – parallel plate; – fringe. fringe plate
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Modern VLSI Design 3e: Chapter 2
Metal coupling capacitances
Can couple to adjacent wires on same layer, wires on above/below layers: metal 2
metal 1
metal 1
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Modern VLSI Design 3e: Chapter 2
Example: parasitic capacitance measurement n-diffusion: bottomwall=2 fF, sidewall=2 fF. 1.5 μm metal: plate plate=00.15 15 fF fF, fringe=0.72 fF.
3 μm
0.75 μm
Modern VLSI Design 3e: Chapter 2
1 μm
2.5 μm
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Wire resistance
Resistance of any size square is constant:
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Modern VLSI Design 3e: Chapter 2
Mean-time-to-failure MTF for metal wires = time required for 50% of wires to fail. Depends on current density:
– proportional to j-n e Q/kT – j is current density – n is constant between 1 and 3 – Q is diffusion activation energy
Modern VLSI Design 3e: Chapter 2
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Skin effect At low frequencies, most of copper conductor’s cross section carries current. As frequency increases, increases current moves to skin of conductor.
– Back EMF induces counter-current in body of conductor.
Skin effect most important at gigahertz frequencies.
Modern VLSI Design 3e: Chapter 2
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Skin effect, cont’d
Isolated conductor:
Conductor and ground:
Low frequency Low frequency
High frequency High frequency Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Skin depth
Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: δ = 1/sqrt(π f μ σ) – f = signal frequency μ = magnetic permeability σ = wire conducitvity
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Modern VLSI Design 3e: Chapter 2
Effect on resistance
Low frequency resistance of wire: – Rdc = 1/ σ wt
High frequency resistance with skin effect: – Rhf = 1/2 σ δ (w + t)
Resistance per unit length: – Rac = sqrt(Rdc 2 + κ Rhf 2)
Typically κ = 1.2.
Modern VLSI Design 3e: Chapter 2
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Transistor gate parasitics
Gate-source/drain overlap capacitance: gate t source
drain
overlap
Modern VLSI Design 3e: Chapter 2
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Transistor source/drain parasitics Source/drain have significant capacitance, resistance. Measured same way as for wires. wires Source/drain R, C may be included in Spice model rather than as separate parasitics.
Modern VLSI Design 3e: Chapter 2
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Topics Design rules and fabrication. SCMOS scalable desgn rules. Stick diagrams diagrams.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Why we need design rules Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.
Modern VLSI Design 3e: Chapter 2
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Manufacturing problems Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.
Modern VLSI Design 3e: Chapter 2
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Transistor problems
Varaiations in threshold voltage: – oxide thickness; – ion implanatation; – poly variations.
Changes in source/drain diffusion overlap. Variations in substrate.
Modern VLSI Design 3e: Chapter 2
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Wiring problems Diffusion: changes in doping -> variations in resistance, capacitance. Poly, Poly metal: variations in height, height width -> > variations in resistance, capacitance. Shorts and opens:
Modern VLSI Design 3e: Chapter 2
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Oxide problems
Variations in height. Lack of planarity -> step coverage. metal t l2 metal 2
Modern VLSI Design 3e: Chapter 2
metal 1
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Via problems Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short. short
Modern VLSI Design 3e: Chapter 2
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MOSIS SCMOS design rules Designed to scale across a wide range of technologies. Designed to support multiple vendors. vendors Designed for educational use. Ergo, fairly conservative.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
λ and design rules λ is the size of a minimum feature. Specifying λ particularizes the scalable rules rules. Parasitics are generally not specified in λ units.
Modern VLSI Design 3e: Chapter 2
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Wires 6
metal 3
3
metal 2
3
metal 1
3
pdiff/ndiff
2
poly Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
Transistors 2 2
3
3 1 5
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Modern VLSI Design 3e: Chapter 2
Vias
Types of via: metal1/diff, metal1/poly, metal1/metal2. 4
4 1 2
Modern VLSI Design 3e: Chapter 2
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Metal 3 via Type: metal3/metal2. Rules:
– cut: 3 x 3 – overlap by metal2: 1 – minimum spacing: 3 – minimum spacing to via1: 2
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Modern VLSI Design 3e: Chapter 2
Tub tie
4 1
Modern VLSI Design 3e: Chapter 2
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Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4
Modern VLSI Design 3e: Chapter 2
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Overglass Cut in passivation layer. Minimum bonding pad: 100 μm. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15
Modern VLSI Design 3e: Chapter 2
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Stick diagrams A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties) ties), relative placement placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
Modern VLSI Design 3e: Chapter 2
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Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff
Modern VLSI Design 3e: Chapter 2
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Dynamic latch stick diagram VDD
in
out
VSS phi
phi’
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Modern VLSI Design 3e: Chapter 2
Sticks design of multiplexer
Start with NAND gate: +
out b
Modern VLSI Design 3e: Chapter 2
a
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NAND sticks VDD a
out
b
VSS Modern VLSI Design 3e: Chapter 2
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One-bit mux sticks VDD ai bi
a
a
N1 (NAND)
a outt
select
select’
outt
out
N1 (NAND)
b
N1 (NAND)
b
b
VSS Copyright © 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2
3-bit mux sticks select’
select select’
b2
ai bi
a1
ai
b1
bi
a0
ai
b0
bi
a2
select
m2(one-bit-mux)
select’
select
m2(one-bit-mux) select’
Modern VLSI Design 3e: Chapter 2
select
m2(one-bit-mux)
VDD oi VSS
o2
VDD oi VSS
o1
VDD oi VSS
o0
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Layout design and analysis tools Layout editors are interactive tools. Design rule checkers are generally batch--identify DRC errors on the layout. layout Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists.
Modern VLSI Design 3e: Chapter 2
Copyright © 1998, 2002 Prentice Hall PTR
Automatic layout Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea-of-gates cell/sea of gates layout creates layout from predesigned cells + custom routing.
– Sea-of-gates allows routing over the cell.
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Modern VLSI Design 3e: Chapter 2
Standard cell layout
Modern VLSI Design 3e: Chapter 2
routing area
routing area
routing area
routing g area
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