Two Stage Operational Amplifier Design Design a 2-stage, single-ended op-amp with PMOS inputs with the following design specifications. The first stage is a differential pair with a current mirror load. The second stage is a common source amplifier. You can use a simple current source with a diode-connected PMOS load as the bias circuit. Use Miller compensation and if necessary use zero canceling resistor. VDD = 3.3V DC Gain ≥ 60 dB GBW = as high as possible Phase Margin ≥ 60 degrees Slew Rate: as high as possible Power Consumption ≤ 1.65 mW excluding bias circuit CL = 5 pF Input Voltage Swing: 0V to 1.4V Output Voltage Swing: 0.3V to 2.7V Input-referred Offset Voltage: as low as possible Common Mode Rejection Ratio (CMRR): as high as possible Power Supply Rejection Ratio (PSRR+/ PSRR-): as high as possible Use the TSMC 0.35µm process. The model files will be provided at the website. Simulate your design over typical, fast and slow process corners. The process corners are defined as: • • •
The ‘slow’ corner (slow NMOS/slow PMOS parameters, 70 °C, 3.0 V) The ‘fast’ corner (fast NMOS/fast PMOS parameters, 0 °C, 3.6 V) Typical conditions (typical parameters, 27 °C, 3.3 V)
The project report should include a brief summary and a clearly labeled circuit schematic with widths, lengths for all transistors and a table that lists your op-amp’s DC gain, gain bandwidth, phase margin, slew rate, static current consumption, PSRR+/ PSRR-, and CMRR. Include clearly labeled plots of • • • •
Open loop gain vs. frequency Phase vs. frequency Output Swing Noise spectrum
You can use the MOS Operational Amplifier Design tutorial by P. Gray and R. Meyer provided at the website.