Substrate Noise Coupling Analysis In Mixed Signal Ics
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Substrate Noise Coupling Analysis In Mixed-Signal ICs François J. R. Clément [email protected]
© Copyright 2001 Simplex Solutions, Inc.
1
/ Substrate in Signal Integrity / HSubstrate HInterconnects VSource HPackage
© Copyright 2001 Simplex Solutions, Inc.
ZVictim
2
/ Lightly-Doped Substrate Isolation / VNOISE P+
d R1 R2
VGND P+
VVICTIM
d
R1 R2
P+
10k
20
d [microns] 60
100
180
23
R1
R3 P- Bulk •
Lightly doped material
•
Maximum isolation when source and victim are closer to the guard band
•
Bonding inductance will affect isolation
] V 25 B d [ 27 n o i t a l o s I
29 31 33
Isolation= 20log
Vvictim [dBV] Vnoise
© Copyright 2001 Simplex Solutions, Inc.
3
/ Noise Dependence on Distance to Ground /
Source
dSR
Receiver
Test chip with lightly-doped substrate
© Copyright 2001 Simplex Solutions, Inc.
4
/ Outline /
Introduction – – –
Problem Summary Various Parasitic Components Impact on the Design
•
Technology
•
Modeling
© Copyright 2001 Simplex Solutions, Inc.
5
/ Substrate Crosstalk: the Problem /
3-D Complexity Technology Dependence
Trial & Error Lost Time-to-Market
© Copyright 2001 Simplex Solutions, Inc.
6
/ Device Parasitics / Physical structure Oxide
Equivalent model
Polysilicon Bonding Wire Diffusion (substrate contact) Substrate
With a total capacitance of 10 [pF] and an inductance of 4 [nH], fR is 800 [MHz] © Copyright 2001 Simplex Solutions, Inc.
7
/ Crosstalk: Parasitic Return Path / Perturbed Cell
Oxide
Signal Source
Forward Signal Path
Parasitic Return Path
Metal
Signal Receiver
Substrate
© Copyright 2001 Simplex Solutions, Inc.
8
/ Crosstalk: Path to AC Ground / Noise Source
Parasitic Path to AC Ground
Diffusion (Substrate Contact) Substrate
© Copyright 2001 Simplex Solutions, Inc.
9
/ WARNING !!! / • Noise coupling is context dependant • All presented test cases have specific backgrounds • Given examples are not provided as final design rules
© Copyright 2001 Simplex Solutions, Inc.
10
/ Outline / •
Introduction Technology – – –
•
Semiconductor Physics Wafer Impact Fabrication Process
Modeling
© Copyright 2001 Simplex Solutions, Inc.
11
/ Assumptions / •
•
Circuit is functioning normally
–
Well-substrate junctions are reverse biased
–
No parasitic surface inversion
–
Latch-up under control
Inductive coupling is neglected inside silicon
–
Much smaller than resistive or capacitive coupling
© Copyright 2001 Simplex Solutions, Inc.
12
/ Basic Properties /
• Permitivity:
εSi =
• Permeability:
µSi = 4π
• Resistivity:
σ = q(pµp+nµn)
© Copyright 2001 Simplex Solutions, Inc.
1.035 [pF/cm] [nH/cm]
13
/ Outline / •
Introduction Technology – – –
•
Semiconductor Physics Wafer Impact Fabrication Process
Modeling
© Copyright 2001 Simplex Solutions, Inc.
14
/ Lightly-Doped Wafer /
d
re fa w
T
)s n or ic m 0 0 4 ~ ( ei d
)s n or ic m 00 8 ~ ( re f a w
ρ
:
ρ
silicon
lightly doped (~12 ohm-cm)
epoxy
:
conductive or isolating
ε
oxide
© Copyright 2001 Simplex Solutions, Inc.
15
/ Lightly-Doped Wafer Resistivity / 1 2
d«T
Wafer
T
Wafer
1 R(d) = R
1
RSubstrate
2
; R(2*d) = R : R < 2 * R 2
2
1
Non-conductive Backside © Copyright 2001 Simplex Solutions, Inc.
16
/ Lightly-Doped Substrate Isolation / VNOISE P+
d R1 R2
VGND P+
VVICTIM
d
R1 R2
P+
10k
d [microns]
20
60
100
180
23
] V 25 B d [ 27
R1
n o i t a l o s I
R3 P- Bulk •
Lightly doped material
•
Maximum isolation when source and victim are closer to the guard band
•
Bonding inductance will affect isolation
29 31 33
Isolation= 20log
Vvictim [dBV] Vnoise
© Copyright 2001 Simplex Solutions, Inc.
17
/ Lightly-Doped Wafer Resistivity / 5
Non-conductive Epoxy Conductive Epoxy 4
] Ω k[ 3 ec na ts is eR 2 1
0
0
200
© Copyright 2001 Simplex Solutions, Inc.
400
Distance [µm]
600
800
18
/ Epitaxial Wafer (Heavily-Doped Bulk) /
d i pe
ρsilicon:
T
lightly doped (~12 ohm-cm)
ρsilicon:
kl ub
T
ρepoxy:
heavily doped (~0.01 ohm-cm)
conductive or isolating
εoxide © Copyright 2001 Simplex Solutions, Inc.
19
/ Parasitic Return Path: Skin Effect /
Oxide
Forward Signal Path
Metal
0 Signal Source
Parasitic Return Path
Signal Receiver
Jsurface 0 e
Jsurface
Tskin
2*Tskin Substrate
Tskin
=
ρ [cm] πµ f
© Copyright 2001 Simplex Solutions, Inc.
with r [W⋅cm], m [H] and f [Hz] 20
/ Skin Effect /
© Copyright 2001 Simplex Solutions, Inc.
21
/ Wafer Impact Summary /
• Lightly Doped – Isolation increase with distance with non-conductive backside – Backside contact with limited efficiency – Resistive mesh model
• Heavily-Doped – Distance doesn’t provide isolation – Careful substrate grounding – Backside contact efficient (at high frequency?) – Simple model © Copyright 2001 Simplex Solutions, Inc.
22
/ Outline /
•
•
Introduction Technology –
Semiconductor Physics
–
Wafer Impact
–
Fabrication Process
Modeling
© Copyright 2001 Simplex Solutions, Inc.
23
/ Process Parameters /
sinker (~0.005 ohm-cm)
contact (~0.005 ohm-cm) p
deep trench
+
well (~1 ohm-cm)
p p
buried layer (~0.005 ohm-cm)
field implant (~0.2 ohm-cm)
p
+
n n
+
p substrate (~12 ohm-cm) -
+
)s no rci m 5~ (s se co rp
T
F.Clement in J. Huijsing et al, KAP, ‘99 © Copyright 2001 Simplex Solutions, Inc.
24
/ Lightly-Doped: Channel Stop Break / depletion
p channel stop
region
dd
V
n well
-
p
Substrate Current
substrate
Depletion increases with Vdd causing well-substrate capacitance to decrease © Copyright 2001 Simplex Solutions, Inc.
25
/ Breaking the Buried Layer / deep trench
n well (~1 ohm-cm)
p epitaxial layer (~1 ohm-cm)
Tepi (~3 um) p buried layer (~0.005 ohm-cm
Tburied (~1 um)
+
Tbulk (~400 um) p wafer (~12 ohm-cm) -
n buried layer (0.005 ohm-cm) +
© Copyright 2001 Simplex Solutions, Inc.
26
/ NMOST: Triple Well Isolation /
n sinker (~0.005 ohm-cm)
T
N+
epi
p epitaxial layer (~1 ohm-cm)
N+
(~3 um)
T
(~1 um)
T
(~400 um)
buried
bulk
p buried layer (~0.005 ohm-cm) +
p wafer (~12 ohm-cm) -
n buried layer (~0.005 ohm-cm) +
© Copyright 2001 Simplex Solutions, Inc.
27
/ Triple Well Isolation /
• Behavior changes with buried layer doping – Heavily doped layer • Partially depleted • Can be biased through sinkers – Lightly doped layer • Fully depleted
Noise Junction Noise source capacitances victim
• Beyond 1 GHz isolation depends on – Respective doping levels – Junction biasing
© Copyright 2001 Simplex Solutions, Inc.
Psubstrate
N well
P well
28
/ Technology: Conclusion /
•
Significant Wafer Influence
– Doping Variations – Backside Connection •
Fabrication Process
– Surface Implants – Well-Substrate Junctions – Buried Layers
© Copyright 2001 Simplex Solutions, Inc.
29
/ Available Processes /
•
Memory, RF Processes
– Lightly-Doped Bulk
• aka High-Resistivity or Bulk CMOS
•
Digital Processes
– Heavily-Doped Bulk with Lightly-Doped Epitaxial Layer
• aka Low-Resistivity or Epitaxial Substrate or Standard CMOS
•
Bipolar / BiCMOS Processes
– Lightly-Doped Bulk and Epitaxial Layer with Heavily-Doped Buried Layers
© Copyright 2001 Simplex Solutions, Inc.
30
/ Available Foundry Processes /
• Lightly-Doped Bulk – All TSMC & UMC Processes – IBM (7SF) • Heavily-Doped Bulk – Option for All TSMC & UMC Processes – STMicroelectronics (HCMOS9) – IBM (5SF, 6SF) • Lightly-Doped with Heavily-Doped Buried Layers – STMicroelectronics (BICMOS6G) – IBM (4S, 5S, 5HP, 6HP) http://www.tsmc.com/technology/index.html http://www.umc.com/english/process/ http://eu.st.com/stonline/prodpres/dedicate/asic/liban.htm http://www-3.ibm.com/chips/techlib/techlib.nsf/pages/main
© Copyright 2001 Simplex Solutions, Inc.
31
/ Outline /
•
Introduction
•
Technology
Modeling –
Generation
–
Isolation
–
Sensitivity
© Copyright 2001 Simplex Solutions, Inc.
32
/ Sources of Substrate Noise /
•
Inductive Noise (di/dt, 100 mV)
•
Capacitive Coupling (dv/dt, 10 mV)
• Bonding wires • Large di/dt on power supplies • Non-ideal power supplies connecting directly to the substrate • Interconnect capacitance to substrate • Junction capacitances
•
Impact Ionization (Idrain, Vgs & Vds, 2 mV)
• High electric field near the drain of saturated MOS devices • Substrate current injection
© Copyright 2001 Simplex Solutions, Inc.
33
/ Inductive Noise /
bond wire
package trace chip
package
di dt
Board Gnd
• L changes with:
di V =L dt Chip Gnd
L
• Type of package • Number of pins for a connection © Copyright 2001 Simplex Solutions, Inc.
34
/ Capacitive Noise /
Line CL-S
MOST dv dt
CL-L Line
CN-P
i=C
dv dt
CL-W Well CW-S
Substrate
Large capacitance to substrate (supply, buses, output drivers, clock, etc.):
Shielding reduces some values
© Copyright 2001 Simplex Solutions, Inc.
35
/ Reducing Noise Generation /
•
Avoid switching of large capacitive nodes
– The direct coupling into the substrate may be decreased – At the same time supply bounce is reduced – Shielding helps reducing injection into the substrate •
Minimize the instantaneous current
– Slow rise and fall times – Stagger the timing of output drivers or large blocks of circuitry – Lower the voltage swing – Keep package inductance as low as possible – Use separate power supply for largest current drivers •
Turn off functions not in use
© Copyright 2001 Simplex Solutions, Inc.
36
/ Equivalent Switching-Capacitance Model /
V(f)
P
N+
CEquiv
f = frequency of noise rise and fall times are important
substrate
T. Blalack in J. Huijsing et al, KAP, ‘99 P. T. M. van Zeijl in proceedings of 38th DAC, IEEE, ‘01 © Copyright 2001 Simplex Solutions, Inc.
37
/ Noise Generation: Macro Model /
Detailed Model
Macro Model
SPICE Simulation
M. van Heijningen et al, DAC‘00
© Copyright 2001 Simplex Solutions, Inc.
38
/ Outline /
•
Introduction
•
Technology
Modeling –
Generation
–
Isolation
–
Sensitivity
© Copyright 2001 Simplex Solutions, Inc.
39
/ Isolation /
•
Techniques vary dramatically between heavily and lightly-doped substrates.
•
Distance isolation is difficult to achieve in both cases.
•
Separate analog and digital supplies.
– Multiple sets of supplies may be necessary to further divide circuit blocks – Package inductance together with pin assignment is critical
© Copyright 2001 Simplex Solutions, Inc.
40
/ Heavily-Doped Bulk Acts as Single Node /
Well PMOST Contact N+
P+
N-well P- Epitaxial layer
NMOST P+
N+
N+
Substrate Contact P+
P+ channel stop implant
P+ Bulk Well Contact
Substrate Contact Cwell Repi1
Repi3
Repi2 Bulk Node
D. Su et al., JSSC, April 1993
© Copyright 2001 Simplex Solutions, Inc.
41
/ Heavily-Doped Substrate Connections /
Vsub
Vsub P+
Substrate Contact
Substrate Contact Repi1
Substrate P+ Bulk
P- Epitaxial layer
Repi2
Bulk Node
•
Connect substrate to “quiet” supply only
•
Minimize inductance
© Copyright 2001 Simplex Solutions, Inc.
P+
42
/ Guard Rings in an Heavily-Doped Bulk /
Vss
Vss P+
N+
A
N+
P+
P+
•
P- Epi
Separate pin provides some benefit
P+ Bulk Vss P+
N+
B
N+
P+
P+
P- Epi
• Connection to substrate contacts can make things worse
P+ Bulk © Copyright 2001 Simplex Solutions, Inc.
43
/ Lightly-Doped Substrate Connections / Substrate Contacts
Vsub
P+
Substrate Contacts
P+
P+
Rbulk
P- Bulk •
Vsub
P+
Rbulk Risolation
Use multiple supplies to isolate areas
• Minimize inductance © Copyright 2001 Simplex Solutions, Inc.
44
/ Guard Rings in a Lightly-Doped Process / AVdd
AGnd P+
N+
N+
P+
N+
N Well
DGnd P+
P channel stop implant
P- Bulk •
Guard rings are more effective in a lightly doped process
• A well region will increase the isolation © Copyright 2001 Simplex Solutions, Inc.
45
/ Noise Dependence on Distance to Ground /
Noise
[V]
Source
dSR
dSG Contact to Ground
Receiver dRG
Ring Osc. SG +d RG [µm]
d
Test chip with lightly-doped substrate
© Copyright 2001 Simplex Solutions, Inc.
SR [µm] d
46
/ Other Conductive Path /
R2
Sensitive
Asub Dsub
R1 ANALOG
Substrate contacts
DIGITAL Noisy
Equivalent behavior with pad or seal ring !!! © Copyright 2001 Simplex Solutions, Inc.
47
/ Careful Floorplanning /
• Package inductance needs to be minimized for power supplies directly connected to substrate • Seal and pad rings affect noise transfer • Digital signals should not – be routed over or through the analog portion of the chip – be routed next to sensitive lines
• The floorplan should ensure that the package pin assignments do not route sensitive analog signals near digital I/Os, supplies, or clock signals © Copyright 2001 Simplex Solutions, Inc.
48
/ Heavily-Doped Bulk Simplified Model /
b
Epitaxial layer (repi ~ 20 ohm-cm)
a Tepi
Repi
Heavily doped bulk (~ 0.01 ohm-cm)
Area: A = (a + d)(b + d) Perimeter: P = 2(a + b + 2d) • Repi = Rarea + Rperimeter = (k1 repi / A) // (k2 repi / P) • k1, k2 and d from measurement •
D. Su et al., JSSC, April 1993
© Copyright 2001 Simplex Solutions, Inc.
49
Model Extraction Strategy
Technology Technology description description
Layout Layout IN
3-D 3-DModel Model OUT Electrical Electrical simulation simulation
© Copyright 2001 Simplex Solutions, Inc.
Visual Visual analysis analysis
50
/ Modeling the Substrate /
Bonding Wire
Noise Source
Noise Victim
P+ contacts •
Nwell
Substrate Abstract View Definition -
•
N+ contact
Process regions (wells, buried layers, deep trenches, …) Ports connecting the ideal circuit to the substrate Equivalent ideal circuit model for interactive visual analysis
RC Model Extraction
© Copyright 2001 Simplex Solutions, Inc.
51
}
/ Automated 3D Modeling /
poly p+ y
nwell x
z
LAYOUT
interconnect contact device p+ nwell p-substrate
© Copyright 2001 Simplex Solutions, Inc.
)s S leif So E rp Cg Oni Rp P od ( 52
/ RC Extraction /
•
Finite elements (FEM)
– Exact solution using Poisson and Continuity Equations •
Finite differences (FDM)
– No carrier diffusion – Simple RC model applied on 3D Mesh •
Boundary element method (BEM)
– No carrier diffusion – No lateral doping variation – Only port-to-port relationship needs to be modeled © Copyright 2001 Simplex Solutions, Inc.
53
/ FDM vs. BEM: Triple-Well Model /
FDM
BEM
Triple-well bias
© Copyright 2001 Simplex Solutions, Inc.
Triple-well bias
P-
P+
N+
electrical node 54
/ Outline /
•
Introduction
•
Technology
Modeling –
Generation
–
Isolation
–
Sensitivity
© Copyright 2001 Simplex Solutions, Inc.
55
/ Effects of Substrate Noise /
•
Operating conditions
• Threshold voltage • Junction capacitance • Bias current •
Degradations
• Gain, bandwidth • Jitter, phase noise • Noise figure, RF intermodulation •
Failures
• Latchup © Copyright 2001 Simplex Solutions, Inc.
56
/ Desensitizing the Listener / • • • •
Fully differential circuitry High common-mode rejection (CMRR) High power supply rejection (PSRR) Layout symmetry – common-centroid may be required for matching of critical components
• Analog clocks – minimize supply noise for last stage clock drivers
© Copyright 2001 Simplex Solutions, Inc.
57
/ Input Gate Capacitance /
Gate-to-Channel Capacitance Source
© Copyright 2001 Simplex Solutions, Inc.
Gate
Gate-to-Source Overlap Capacitance Drain
58
/ Clock Noise Coupling into the Signal Path /
φ
φ
Ap
2.6 V
Ap
4.0 V
VCM
2.4 V
VCM
1.0 V
Am φ
Am φ
Common-Mode Coupling
Differential Coupling
© Copyright 2001 Simplex Solutions, Inc.
59
/ Supply Noise Coupling to Clock Lines /
φ vi
φ
© Copyright 2001 Simplex Solutions, Inc.
60
/ Modeling: Conclusion /
•
Generation
– Performance & capacity issue – Gate-level modeling •
Isolation
– Technology characterization – Simple model for heavily doped bulk – Mesh required for lightly doped •
Sensitivity
– Accuracy – Transistor-level modeling
© Copyright 2001 Simplex Solutions, Inc.
61
/ References /
BOOKS • • • • • • • •
E. Carbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, A. L. Sangiovanni-Vincentelli, Substrate Noise Analysis and Optimization for IC Design, Kluwer Academic Publishers, 2001. X. Aragonès, J. L. González and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Academic Publishers, 1999. T. Blalack, “Design Techniques to Reduce Substrate Noise,” Analog Circuit Design, pp. 193-218, J. Huijsing et al. - Editors, Kluwer Academic Publishers, 1999. F. J. R. Clément, “Technology Impact on Substrate Noise,” Analog Circuit Design, pp. 173-192, J. Huijsing et al. - Editors, Kluwer Academic Publishers, 1999. T. Schmerbeck, “Noise coupling in mixed-signal ASICs,” Low-power HF microelectronics: a unified approach, pp. 373-430, G. Machado - Editor, IEE, 1996. N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for MixedSignal Coupling in Integrated Circuits, Kluwer Academic Publishers, 1995. R. W. Dutton and Z. Yu, Technology CAD - Computer Simulation of IC Processes and Devices. Kluwer Academic Publishers, 1993. R. M. Warner and B. L. Grung, Semiconductor-Device Electronics, Rinehart and Winston, Inc., 1991.
© Copyright 2001 Simplex Solutions, Inc.
62
/ References / • •
J. Y. Chen, CMOS Devices and Technology for VLSI, Prentice-Hall, 1990. R. R. Troutman, Latchup on CMOS Technology - The Problem and Its Cure, Kluwer Academic Publishers, 1986.
THESIS DISSERTATIONS • • • •
R. Singh, “Efficient modelling of substrate noise and coupling in mixed-signal Spice designs”, Thesis Dissertation, University of Newcastle upon Tyne Department of Electrical and Electronic Engineering, October 1997. T. Blalack, “Switching Noise in Mixed-Signal Integrated Circuits”, Thesis Dissertation, Stanford University Department of Electrical Engineering, December 1997. X. Aragonès, “A Contribution to the Study of Substrate Coupling in Mixed-Signal Integrated Circuits”, Thesis Dissertation, Universitat Politècnica de Catalunya, Barcelona, October 1997. F. Clément, “Computer Aided Analysis of Parasitic Substrate Coupling in Mixed Digital-Analog CMOS Integrated Circuits”, Thesis Dissertation No. 1449, Swiss Federal Institute of Technology, Lausanne, 1996.
© Copyright 2001 Simplex Solutions, Inc.
63
/ References /
JOURNAL AND CONFERENCE PAPERS • • • • • • •
D. Belot, “A DCS1800/GSM900 RF to Digital Fully Integrated Receiver in SiGe 0.35um BiCMOS”, Bipolar/BiCMOS Circuits and Technology Meeting, October 2001. P. T. M. van Zeijl, “One-Chip Bluetooth ASIC Challenges”, 38th IEEE Design Automation Conference, p. 262, June 2001. M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels and I. Bolsens, “High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling”, 37th IEEE Design Automation Conference, pp. 446-451, June 2000. R. Singh, “A Review of Substrate Coupling Issues and Modeling Strategies”, IEEE Custom Integrated Circuit Conference, pp.491-498, May 1999. M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, “Modeling of Digital Substrate Noise Generation and Experimental Verification Using a Novel Substrate Noise Sensor,” in Proceedings of the ESSCIRC, pp. 186–189, 1999. R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal and J. P. Mattia, “R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model”, IEEE International Electron Devices Meeting, pp. 309-312, December 1997. R. Gharpurey and S. Hosur, “Transform Domain Techniques for Efficient Extraction of Substrate Parasitics”, IEEE International Conference on Computer-Aided Design, pp. 461-467, December 1997.
© Copyright 2001 Simplex Solutions, Inc.
64
•
/ References /
J. Casalta, X. Aragones, and A. Rubio, “Substrate Coupling Evaluation in BiCMOS Technology,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 598-603, April 1997 A. Pun, T. Yeung, J. Lau, F. J. R. Clement and D. Su, “Experimental Results and Simulation of Substrate Noise Coupling via Planar Spiral Inductor in RF ICs”, IEEE International Electron Device Meeting, pp. 325-328, December 1997. M. Pfost, H. Rein, and T. Holzwarth, “Modeling Substrate Effects in the Design of High-Speed SiBipolar ICs,” IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1493-1501, October 1996. T. Blalack, J. Lau, F. Clement, and B. Wooley, “Experimental Results and Modeling of Noise Coupling in a Lightly Doped Substrate,” IEEE International Electron Device Meeting, pp. 623-626, December 1996. K. Makie-Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, “Measurement of Digital Noise in MixedSignal Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 87-92, February 1995. T. Blalack and B. A. Wooley, “The Effects of Switching Noise on an Oversampling A/D Converter”, IEEE International Solid-State Circuit Conference, pp. 200-201, February 1995. R. Merrill, W. Young, and K. Brehmer, “Effect of Substrate Material on Crosstalk in Mixed Analog/Digital Integrated Circuits,” IEEE International Electron Devices Meeting, pp. 433-436, December 1994. .
• • • • • •
© Copyright 2001 Simplex Solutions, Inc.
65
/ References / • • • • • • •
D. Su, M. Loinaz, S. Masui, and B. Wooley, “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420-430, April 1993. K. Kwan, I. Wemple, and A. Yang, “Simulation and Analysis of Substrate Coupling in Realistically-Large Mixed-A/D Circuits,” IEEE Symposium on VLSI Circuits, pp. 184-185, June 1996. R. Gharpurey and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 344-353, March 1996. N. K. Verghese, D. J. Allstot and M. A. Wolfe, “Verification Techniques for Substrate Coupling and Their Application to Mixed-Signal IC Design”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 354-365, March 1996. A. Viviani, J. P. Raskin, D. Flandre, J. P. Colinge and D. Vanhoenacker, “Extended study of crosstalk in SOI-SIMOX substrates,” IEEE International Electron Devices Meeting, pp. 713-716, December 1995. J. P. Raskin, D. Vanhoenacker, J. P. Colinge and D. Flandre, “Coupling Effects in HighResistivity Simox Substrates for VHF and Microwaves Applications”, IEEE International SOI Conference, pp. 62-63, October 1995. I. L. Temple and A. T. Yang, “Mixed-Signal Switching Noise Analysis Using Voronoi-Tesselated Substrate Macromodels”, 32nd IEEE Design Automation Conference, pp. 439-444, June 1995.
© Copyright 2001 Simplex Solutions, Inc.
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/ References / • • • • • • •
T. Smedes, N.P. van der Meijs, A.J. van Genderen, P.J.H. Elias and R.R.J. Vanoppen, “Layout Extraction of 3D Models for Interconnect and Substrate Parasitics”, 25th European Solid-State Device Research Conference, pp. 397-400, September 1995. S. Mitra, R. A. Rutenbar, L. R. Carley and D. J. Allstot, “A Methodology for Rapid Estimation of Substrate-Coupled Switching Noise”, IEEE Custom Integrated Circuit Conference, pp.129-132, May 1995. K. Joardar, “A Simple Approach to Modeling Cross-Talk in Integrated Circuits,” IEEE J. SolidState Circuits, vol. 29, no. 10, pp. 1212-1219, October 1994. J. Olmstead and S. Vulih, “Noise Problems in Mixed Analog-Digital Integrated Circuits,” IEEE Custom Integrated Circuits Conference, pp. 659-662, May 1987. M. Nagata and A. Iwata, “A Macroscopic Substrate Noise Model for Full Chip Mixed-Signal Design Verification,” IEEE Symposium on VLSI Circuits, pp. 37- 38, June 1997. R. Senthinathan and J. Prince, “Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1383-1388, December 1993. D. Cox, D. Guertin, C. Johnson, B. Rudolph, R. Williams, R. Piro, and D. Stout, “VSLI Performance Compensation for Off-Chip Drivers and Clock Generation,” IEEE Custom Integrated Circuits Conference, pp. 14.3.1-14.3.4, May 1989.
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67
/ References / • • • • • • •
M. Ingels and M. Steyaert, “Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode ICs,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1136-1141, July 1997. K. Makie-Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, “Measurement of Digital Noise in MixedSignal Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 87-92, February 1995. Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology: an Introduction, pp. 220-236, McGraw- Hill, 1996. R. Pease, “Comments on ‘Analog Layout Using ALAS!’”, IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1364-1365, September 1996. M. Ismail and T. Fiez, Analog VLSI: Signal and Information Processing, pp. 699-726, McGraw- Hill, 1994. E. van der Zwan and E. Dijkmans, “A 0.2-mW CMOS Sigma-Delta Modulator for Speech Coding with 80-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1873-1880, December 1996. E. van der Zwan, “A 2.3-mW CMOS Sigma-Delta Modulator for Audio Applications,” IEEE International Solid-State Circuits Conference, vol. 40, pp. 220-221, February 1997.
© Copyright 2001 Simplex Solutions, Inc.
68
© Copyright 2001 Simplex Solutions, Inc.
1
/ Substrate in Signal Integrity / HSubstrate HInterconnects VSource HPackage
© Copyright 2001 Simplex Solutions, Inc.
ZVictim
2
/ Lightly-Doped Substrate Isolation / VNOISE P+
d R1 R2
VGND P+
VVICTIM
d
R1 R2
P+
10k
20
d [microns] 60
100
180
23
R1
R3 P- Bulk •
Lightly doped material
•
Maximum isolation when source and victim are closer to the guard band
•
Bonding inductance will affect isolation
] V 25 B d [ 27 n o i t a l o s I
29 31 33
Isolation= 20log
Vvictim [dBV] Vnoise
© Copyright 2001 Simplex Solutions, Inc.
3
/ Noise Dependence on Distance to Ground /
Source
dSR
Receiver
Test chip with lightly-doped substrate
© Copyright 2001 Simplex Solutions, Inc.
4
/ Outline /
Introduction – – –
Problem Summary Various Parasitic Components Impact on the Design
•
Technology
•
Modeling
© Copyright 2001 Simplex Solutions, Inc.
5
/ Substrate Crosstalk: the Problem /
3-D Complexity Technology Dependence
Trial & Error Lost Time-to-Market
© Copyright 2001 Simplex Solutions, Inc.
6
/ Device Parasitics / Physical structure Oxide
Equivalent model
Polysilicon Bonding Wire Diffusion (substrate contact) Substrate
With a total capacitance of 10 [pF] and an inductance of 4 [nH], fR is 800 [MHz] © Copyright 2001 Simplex Solutions, Inc.
7
/ Crosstalk: Parasitic Return Path / Perturbed Cell
Oxide
Signal Source
Forward Signal Path
Parasitic Return Path
Metal
Signal Receiver
Substrate
© Copyright 2001 Simplex Solutions, Inc.
8
/ Crosstalk: Path to AC Ground / Noise Source
Parasitic Path to AC Ground
Diffusion (Substrate Contact) Substrate
© Copyright 2001 Simplex Solutions, Inc.
9
/ WARNING !!! / • Noise coupling is context dependant • All presented test cases have specific backgrounds • Given examples are not provided as final design rules
© Copyright 2001 Simplex Solutions, Inc.
10
/ Outline / •
Introduction Technology – – –
•
Semiconductor Physics Wafer Impact Fabrication Process
Modeling
© Copyright 2001 Simplex Solutions, Inc.
11
/ Assumptions / •
•
Circuit is functioning normally
–
Well-substrate junctions are reverse biased
–
No parasitic surface inversion
–
Latch-up under control
Inductive coupling is neglected inside silicon
–
Much smaller than resistive or capacitive coupling
© Copyright 2001 Simplex Solutions, Inc.
12
/ Basic Properties /
• Permitivity:
εSi =
• Permeability:
µSi = 4π
• Resistivity:
σ = q(pµp+nµn)
© Copyright 2001 Simplex Solutions, Inc.
1.035 [pF/cm] [nH/cm]
13
/ Outline / •
Introduction Technology – – –
•
Semiconductor Physics Wafer Impact Fabrication Process
Modeling
© Copyright 2001 Simplex Solutions, Inc.
14
/ Lightly-Doped Wafer /
d
re fa w
T
)s n or ic m 0 0 4 ~ ( ei d
)s n or ic m 00 8 ~ ( re f a w
ρ
:
ρ
silicon
lightly doped (~12 ohm-cm)
epoxy
:
conductive or isolating
ε
oxide
© Copyright 2001 Simplex Solutions, Inc.
15
/ Lightly-Doped Wafer Resistivity / 1 2
d«T
Wafer
T
Wafer
1 R(d) = R
1
RSubstrate
2
; R(2*d) = R : R < 2 * R 2
2
1
Non-conductive Backside © Copyright 2001 Simplex Solutions, Inc.
16
/ Lightly-Doped Substrate Isolation / VNOISE P+
d R1 R2
VGND P+
VVICTIM
d
R1 R2
P+
10k
d [microns]
20
60
100
180
23
] V 25 B d [ 27
R1
n o i t a l o s I
R3 P- Bulk •
Lightly doped material
•
Maximum isolation when source and victim are closer to the guard band
•
Bonding inductance will affect isolation
29 31 33
Isolation= 20log
Vvictim [dBV] Vnoise
© Copyright 2001 Simplex Solutions, Inc.
17
/ Lightly-Doped Wafer Resistivity / 5
Non-conductive Epoxy Conductive Epoxy 4
] Ω k[ 3 ec na ts is eR 2 1
0
0
200
© Copyright 2001 Simplex Solutions, Inc.
400
Distance [µm]
600
800
18
/ Epitaxial Wafer (Heavily-Doped Bulk) /
d i pe
ρsilicon:
T
lightly doped (~12 ohm-cm)
ρsilicon:
kl ub
T
ρepoxy:
heavily doped (~0.01 ohm-cm)
conductive or isolating
εoxide © Copyright 2001 Simplex Solutions, Inc.
19
/ Parasitic Return Path: Skin Effect /
Oxide
Forward Signal Path
Metal
0 Signal Source
Parasitic Return Path
Signal Receiver
Jsurface 0 e
Jsurface
Tskin
2*Tskin Substrate
Tskin
=
ρ [cm] πµ f
© Copyright 2001 Simplex Solutions, Inc.
with r [W⋅cm], m [H] and f [Hz] 20
/ Skin Effect /
© Copyright 2001 Simplex Solutions, Inc.
21
/ Wafer Impact Summary /
• Lightly Doped – Isolation increase with distance with non-conductive backside – Backside contact with limited efficiency – Resistive mesh model
• Heavily-Doped – Distance doesn’t provide isolation – Careful substrate grounding – Backside contact efficient (at high frequency?) – Simple model © Copyright 2001 Simplex Solutions, Inc.
22
/ Outline /
•
•
Introduction Technology –
Semiconductor Physics
–
Wafer Impact
–
Fabrication Process
Modeling
© Copyright 2001 Simplex Solutions, Inc.
23
/ Process Parameters /
sinker (~0.005 ohm-cm)
contact (~0.005 ohm-cm) p
deep trench
+
well (~1 ohm-cm)
p p
buried layer (~0.005 ohm-cm)
field implant (~0.2 ohm-cm)
p
+
n n
+
p substrate (~12 ohm-cm) -
+
)s no rci m 5~ (s se co rp
T
F.Clement in J. Huijsing et al, KAP, ‘99 © Copyright 2001 Simplex Solutions, Inc.
24
/ Lightly-Doped: Channel Stop Break / depletion
p channel stop
region
dd
V
n well
-
p
Substrate Current
substrate
Depletion increases with Vdd causing well-substrate capacitance to decrease © Copyright 2001 Simplex Solutions, Inc.
25
/ Breaking the Buried Layer / deep trench
n well (~1 ohm-cm)
p epitaxial layer (~1 ohm-cm)
Tepi (~3 um) p buried layer (~0.005 ohm-cm
Tburied (~1 um)
+
Tbulk (~400 um) p wafer (~12 ohm-cm) -
n buried layer (0.005 ohm-cm) +
© Copyright 2001 Simplex Solutions, Inc.
26
/ NMOST: Triple Well Isolation /
n sinker (~0.005 ohm-cm)
T
N+
epi
p epitaxial layer (~1 ohm-cm)
N+
(~3 um)
T
(~1 um)
T
(~400 um)
buried
bulk
p buried layer (~0.005 ohm-cm) +
p wafer (~12 ohm-cm) -
n buried layer (~0.005 ohm-cm) +
© Copyright 2001 Simplex Solutions, Inc.
27
/ Triple Well Isolation /
• Behavior changes with buried layer doping – Heavily doped layer • Partially depleted • Can be biased through sinkers – Lightly doped layer • Fully depleted
Noise Junction Noise source capacitances victim
• Beyond 1 GHz isolation depends on – Respective doping levels – Junction biasing
© Copyright 2001 Simplex Solutions, Inc.
Psubstrate
N well
P well
28
/ Technology: Conclusion /
•
Significant Wafer Influence
– Doping Variations – Backside Connection •
Fabrication Process
– Surface Implants – Well-Substrate Junctions – Buried Layers
© Copyright 2001 Simplex Solutions, Inc.
29
/ Available Processes /
•
Memory, RF Processes
– Lightly-Doped Bulk
• aka High-Resistivity or Bulk CMOS
•
Digital Processes
– Heavily-Doped Bulk with Lightly-Doped Epitaxial Layer
• aka Low-Resistivity or Epitaxial Substrate or Standard CMOS
•
Bipolar / BiCMOS Processes
– Lightly-Doped Bulk and Epitaxial Layer with Heavily-Doped Buried Layers
© Copyright 2001 Simplex Solutions, Inc.
30
/ Available Foundry Processes /
• Lightly-Doped Bulk – All TSMC & UMC Processes – IBM (7SF) • Heavily-Doped Bulk – Option for All TSMC & UMC Processes – STMicroelectronics (HCMOS9) – IBM (5SF, 6SF) • Lightly-Doped with Heavily-Doped Buried Layers – STMicroelectronics (BICMOS6G) – IBM (4S, 5S, 5HP, 6HP) http://www.tsmc.com/technology/index.html http://www.umc.com/english/process/ http://eu.st.com/stonline/prodpres/dedicate/asic/liban.htm http://www-3.ibm.com/chips/techlib/techlib.nsf/pages/main
© Copyright 2001 Simplex Solutions, Inc.
31
/ Outline /
•
Introduction
•
Technology
Modeling –
Generation
–
Isolation
–
Sensitivity
© Copyright 2001 Simplex Solutions, Inc.
32
/ Sources of Substrate Noise /
•
Inductive Noise (di/dt, 100 mV)
•
Capacitive Coupling (dv/dt, 10 mV)
• Bonding wires • Large di/dt on power supplies • Non-ideal power supplies connecting directly to the substrate • Interconnect capacitance to substrate • Junction capacitances
•
Impact Ionization (Idrain, Vgs & Vds, 2 mV)
• High electric field near the drain of saturated MOS devices • Substrate current injection
© Copyright 2001 Simplex Solutions, Inc.
33
/ Inductive Noise /
bond wire
package trace chip
package
di dt
Board Gnd
• L changes with:
di V =L dt Chip Gnd
L
• Type of package • Number of pins for a connection © Copyright 2001 Simplex Solutions, Inc.
34
/ Capacitive Noise /
Line CL-S
MOST dv dt
CL-L Line
CN-P
i=C
dv dt
CL-W Well CW-S
Substrate
Large capacitance to substrate (supply, buses, output drivers, clock, etc.):
Shielding reduces some values
© Copyright 2001 Simplex Solutions, Inc.
35
/ Reducing Noise Generation /
•
Avoid switching of large capacitive nodes
– The direct coupling into the substrate may be decreased – At the same time supply bounce is reduced – Shielding helps reducing injection into the substrate •
Minimize the instantaneous current
– Slow rise and fall times – Stagger the timing of output drivers or large blocks of circuitry – Lower the voltage swing – Keep package inductance as low as possible – Use separate power supply for largest current drivers •
Turn off functions not in use
© Copyright 2001 Simplex Solutions, Inc.
36
/ Equivalent Switching-Capacitance Model /
V(f)
P
N+
CEquiv
f = frequency of noise rise and fall times are important
substrate
T. Blalack in J. Huijsing et al, KAP, ‘99 P. T. M. van Zeijl in proceedings of 38th DAC, IEEE, ‘01 © Copyright 2001 Simplex Solutions, Inc.
37
/ Noise Generation: Macro Model /
Detailed Model
Macro Model
SPICE Simulation
M. van Heijningen et al, DAC‘00
© Copyright 2001 Simplex Solutions, Inc.
38
/ Outline /
•
Introduction
•
Technology
Modeling –
Generation
–
Isolation
–
Sensitivity
© Copyright 2001 Simplex Solutions, Inc.
39
/ Isolation /
•
Techniques vary dramatically between heavily and lightly-doped substrates.
•
Distance isolation is difficult to achieve in both cases.
•
Separate analog and digital supplies.
– Multiple sets of supplies may be necessary to further divide circuit blocks – Package inductance together with pin assignment is critical
© Copyright 2001 Simplex Solutions, Inc.
40
/ Heavily-Doped Bulk Acts as Single Node /
Well PMOST Contact N+
P+
N-well P- Epitaxial layer
NMOST P+
N+
N+
Substrate Contact P+
P+ channel stop implant
P+ Bulk Well Contact
Substrate Contact Cwell Repi1
Repi3
Repi2 Bulk Node
D. Su et al., JSSC, April 1993
© Copyright 2001 Simplex Solutions, Inc.
41
/ Heavily-Doped Substrate Connections /
Vsub
Vsub P+
Substrate Contact
Substrate Contact Repi1
Substrate P+ Bulk
P- Epitaxial layer
Repi2
Bulk Node
•
Connect substrate to “quiet” supply only
•
Minimize inductance
© Copyright 2001 Simplex Solutions, Inc.
P+
42
/ Guard Rings in an Heavily-Doped Bulk /
Vss
Vss P+
N+
A
N+
P+
P+
•
P- Epi
Separate pin provides some benefit
P+ Bulk Vss P+
N+
B
N+
P+
P+
P- Epi
• Connection to substrate contacts can make things worse
P+ Bulk © Copyright 2001 Simplex Solutions, Inc.
43
/ Lightly-Doped Substrate Connections / Substrate Contacts
Vsub
P+
Substrate Contacts
P+
P+
Rbulk
P- Bulk •
Vsub
P+
Rbulk Risolation
Use multiple supplies to isolate areas
• Minimize inductance © Copyright 2001 Simplex Solutions, Inc.
44
/ Guard Rings in a Lightly-Doped Process / AVdd
AGnd P+
N+
N+
P+
N+
N Well
DGnd P+
P channel stop implant
P- Bulk •
Guard rings are more effective in a lightly doped process
• A well region will increase the isolation © Copyright 2001 Simplex Solutions, Inc.
45
/ Noise Dependence on Distance to Ground /
Noise
[V]
Source
dSR
dSG Contact to Ground
Receiver dRG
Ring Osc. SG +d RG [µm]
d
Test chip with lightly-doped substrate
© Copyright 2001 Simplex Solutions, Inc.
SR [µm] d
46
/ Other Conductive Path /
R2
Sensitive
Asub Dsub
R1 ANALOG
Substrate contacts
DIGITAL Noisy
Equivalent behavior with pad or seal ring !!! © Copyright 2001 Simplex Solutions, Inc.
47
/ Careful Floorplanning /
• Package inductance needs to be minimized for power supplies directly connected to substrate • Seal and pad rings affect noise transfer • Digital signals should not – be routed over or through the analog portion of the chip – be routed next to sensitive lines
• The floorplan should ensure that the package pin assignments do not route sensitive analog signals near digital I/Os, supplies, or clock signals © Copyright 2001 Simplex Solutions, Inc.
48
/ Heavily-Doped Bulk Simplified Model /
b
Epitaxial layer (repi ~ 20 ohm-cm)
a Tepi
Repi
Heavily doped bulk (~ 0.01 ohm-cm)
Area: A = (a + d)(b + d) Perimeter: P = 2(a + b + 2d) • Repi = Rarea + Rperimeter = (k1 repi / A) // (k2 repi / P) • k1, k2 and d from measurement •
D. Su et al., JSSC, April 1993
© Copyright 2001 Simplex Solutions, Inc.
49
Model Extraction Strategy
Technology Technology description description
Layout Layout IN
3-D 3-DModel Model OUT Electrical Electrical simulation simulation
© Copyright 2001 Simplex Solutions, Inc.
Visual Visual analysis analysis
50
/ Modeling the Substrate /
Bonding Wire
Noise Source
Noise Victim
P+ contacts •
Nwell
Substrate Abstract View Definition -
•
N+ contact
Process regions (wells, buried layers, deep trenches, …) Ports connecting the ideal circuit to the substrate Equivalent ideal circuit model for interactive visual analysis
RC Model Extraction
© Copyright 2001 Simplex Solutions, Inc.
51
}
/ Automated 3D Modeling /
poly p+ y
nwell x
z
LAYOUT
interconnect contact device p+ nwell p-substrate
© Copyright 2001 Simplex Solutions, Inc.
)s S leif So E rp Cg Oni Rp P od ( 52
/ RC Extraction /
•
Finite elements (FEM)
– Exact solution using Poisson and Continuity Equations •
Finite differences (FDM)
– No carrier diffusion – Simple RC model applied on 3D Mesh •
Boundary element method (BEM)
– No carrier diffusion – No lateral doping variation – Only port-to-port relationship needs to be modeled © Copyright 2001 Simplex Solutions, Inc.
53
/ FDM vs. BEM: Triple-Well Model /
FDM
BEM
Triple-well bias
© Copyright 2001 Simplex Solutions, Inc.
Triple-well bias
P-
P+
N+
electrical node 54
/ Outline /
•
Introduction
•
Technology
Modeling –
Generation
–
Isolation
–
Sensitivity
© Copyright 2001 Simplex Solutions, Inc.
55
/ Effects of Substrate Noise /
•
Operating conditions
• Threshold voltage • Junction capacitance • Bias current •
Degradations
• Gain, bandwidth • Jitter, phase noise • Noise figure, RF intermodulation •
Failures
• Latchup © Copyright 2001 Simplex Solutions, Inc.
56
/ Desensitizing the Listener / • • • •
Fully differential circuitry High common-mode rejection (CMRR) High power supply rejection (PSRR) Layout symmetry – common-centroid may be required for matching of critical components
• Analog clocks – minimize supply noise for last stage clock drivers
© Copyright 2001 Simplex Solutions, Inc.
57
/ Input Gate Capacitance /
Gate-to-Channel Capacitance Source
© Copyright 2001 Simplex Solutions, Inc.
Gate
Gate-to-Source Overlap Capacitance Drain
58
/ Clock Noise Coupling into the Signal Path /
φ
φ
Ap
2.6 V
Ap
4.0 V
VCM
2.4 V
VCM
1.0 V
Am φ
Am φ
Common-Mode Coupling
Differential Coupling
© Copyright 2001 Simplex Solutions, Inc.
59
/ Supply Noise Coupling to Clock Lines /
φ vi
φ
© Copyright 2001 Simplex Solutions, Inc.
60
/ Modeling: Conclusion /
•
Generation
– Performance & capacity issue – Gate-level modeling •
Isolation
– Technology characterization – Simple model for heavily doped bulk – Mesh required for lightly doped •
Sensitivity
– Accuracy – Transistor-level modeling
© Copyright 2001 Simplex Solutions, Inc.
61
/ References /
BOOKS • • • • • • • •
E. Carbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, A. L. Sangiovanni-Vincentelli, Substrate Noise Analysis and Optimization for IC Design, Kluwer Academic Publishers, 2001. X. Aragonès, J. L. González and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Academic Publishers, 1999. T. Blalack, “Design Techniques to Reduce Substrate Noise,” Analog Circuit Design, pp. 193-218, J. Huijsing et al. - Editors, Kluwer Academic Publishers, 1999. F. J. R. Clément, “Technology Impact on Substrate Noise,” Analog Circuit Design, pp. 173-192, J. Huijsing et al. - Editors, Kluwer Academic Publishers, 1999. T. Schmerbeck, “Noise coupling in mixed-signal ASICs,” Low-power HF microelectronics: a unified approach, pp. 373-430, G. Machado - Editor, IEE, 1996. N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for MixedSignal Coupling in Integrated Circuits, Kluwer Academic Publishers, 1995. R. W. Dutton and Z. Yu, Technology CAD - Computer Simulation of IC Processes and Devices. Kluwer Academic Publishers, 1993. R. M. Warner and B. L. Grung, Semiconductor-Device Electronics, Rinehart and Winston, Inc., 1991.
© Copyright 2001 Simplex Solutions, Inc.
62
/ References / • •
J. Y. Chen, CMOS Devices and Technology for VLSI, Prentice-Hall, 1990. R. R. Troutman, Latchup on CMOS Technology - The Problem and Its Cure, Kluwer Academic Publishers, 1986.
THESIS DISSERTATIONS • • • •
R. Singh, “Efficient modelling of substrate noise and coupling in mixed-signal Spice designs”, Thesis Dissertation, University of Newcastle upon Tyne Department of Electrical and Electronic Engineering, October 1997. T. Blalack, “Switching Noise in Mixed-Signal Integrated Circuits”, Thesis Dissertation, Stanford University Department of Electrical Engineering, December 1997. X. Aragonès, “A Contribution to the Study of Substrate Coupling in Mixed-Signal Integrated Circuits”, Thesis Dissertation, Universitat Politècnica de Catalunya, Barcelona, October 1997. F. Clément, “Computer Aided Analysis of Parasitic Substrate Coupling in Mixed Digital-Analog CMOS Integrated Circuits”, Thesis Dissertation No. 1449, Swiss Federal Institute of Technology, Lausanne, 1996.
© Copyright 2001 Simplex Solutions, Inc.
63
/ References /
JOURNAL AND CONFERENCE PAPERS • • • • • • •
D. Belot, “A DCS1800/GSM900 RF to Digital Fully Integrated Receiver in SiGe 0.35um BiCMOS”, Bipolar/BiCMOS Circuits and Technology Meeting, October 2001. P. T. M. van Zeijl, “One-Chip Bluetooth ASIC Challenges”, 38th IEEE Design Automation Conference, p. 262, June 2001. M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels and I. Bolsens, “High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling”, 37th IEEE Design Automation Conference, pp. 446-451, June 2000. R. Singh, “A Review of Substrate Coupling Issues and Modeling Strategies”, IEEE Custom Integrated Circuit Conference, pp.491-498, May 1999. M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, “Modeling of Digital Substrate Noise Generation and Experimental Verification Using a Novel Substrate Noise Sensor,” in Proceedings of the ESSCIRC, pp. 186–189, 1999. R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal and J. P. Mattia, “R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model”, IEEE International Electron Devices Meeting, pp. 309-312, December 1997. R. Gharpurey and S. Hosur, “Transform Domain Techniques for Efficient Extraction of Substrate Parasitics”, IEEE International Conference on Computer-Aided Design, pp. 461-467, December 1997.
© Copyright 2001 Simplex Solutions, Inc.
64
•
/ References /
J. Casalta, X. Aragones, and A. Rubio, “Substrate Coupling Evaluation in BiCMOS Technology,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 598-603, April 1997 A. Pun, T. Yeung, J. Lau, F. J. R. Clement and D. Su, “Experimental Results and Simulation of Substrate Noise Coupling via Planar Spiral Inductor in RF ICs”, IEEE International Electron Device Meeting, pp. 325-328, December 1997. M. Pfost, H. Rein, and T. Holzwarth, “Modeling Substrate Effects in the Design of High-Speed SiBipolar ICs,” IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1493-1501, October 1996. T. Blalack, J. Lau, F. Clement, and B. Wooley, “Experimental Results and Modeling of Noise Coupling in a Lightly Doped Substrate,” IEEE International Electron Device Meeting, pp. 623-626, December 1996. K. Makie-Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, “Measurement of Digital Noise in MixedSignal Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 87-92, February 1995. T. Blalack and B. A. Wooley, “The Effects of Switching Noise on an Oversampling A/D Converter”, IEEE International Solid-State Circuit Conference, pp. 200-201, February 1995. R. Merrill, W. Young, and K. Brehmer, “Effect of Substrate Material on Crosstalk in Mixed Analog/Digital Integrated Circuits,” IEEE International Electron Devices Meeting, pp. 433-436, December 1994. .
• • • • • •
© Copyright 2001 Simplex Solutions, Inc.
65
/ References / • • • • • • •
D. Su, M. Loinaz, S. Masui, and B. Wooley, “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420-430, April 1993. K. Kwan, I. Wemple, and A. Yang, “Simulation and Analysis of Substrate Coupling in Realistically-Large Mixed-A/D Circuits,” IEEE Symposium on VLSI Circuits, pp. 184-185, June 1996. R. Gharpurey and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 344-353, March 1996. N. K. Verghese, D. J. Allstot and M. A. Wolfe, “Verification Techniques for Substrate Coupling and Their Application to Mixed-Signal IC Design”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 354-365, March 1996. A. Viviani, J. P. Raskin, D. Flandre, J. P. Colinge and D. Vanhoenacker, “Extended study of crosstalk in SOI-SIMOX substrates,” IEEE International Electron Devices Meeting, pp. 713-716, December 1995. J. P. Raskin, D. Vanhoenacker, J. P. Colinge and D. Flandre, “Coupling Effects in HighResistivity Simox Substrates for VHF and Microwaves Applications”, IEEE International SOI Conference, pp. 62-63, October 1995. I. L. Temple and A. T. Yang, “Mixed-Signal Switching Noise Analysis Using Voronoi-Tesselated Substrate Macromodels”, 32nd IEEE Design Automation Conference, pp. 439-444, June 1995.
© Copyright 2001 Simplex Solutions, Inc.
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/ References / • • • • • • •
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