Signals And Variables

Signals and Variables Ir djogi lubis M.A.P FTIK-UHT

Signals and Variables • Two non-static data values:  SIGNAL and  VARIABLE. • CONSTANT and SIGNAL can be global (that is, seen by the whole code), and can be used in either type of code, concurrent or sequential. • VARIABLE is local, can only be used inside a piece of sequential code, (in a PROCESS, FUNCTION, or PROCEDURE)

CONSTANT • CONSTANT serves to establish default values • CONSTANT name : type := value; • Examples: CONSTANT set_bit : BIT := '1'; CONSTANT datamemory : memory := (('0','0','0','0'), ('0','0','0','1'), ('0','0','1','1'));

• A CONSTANT can be declared in a PACKAGE, ENTITY, or ARCHITECTURE

SIGNAL • • • •

SIGNAL serves to pass values in and out the circuit, between its internal units. signal represents circuit interconnects (wires) all PORTS of an ENTITY are signals by default Syntax SIGNAL name : type [range] [:= initial_value];

• Examples: SIGNAL control: BIT := '0'; 1. SIGNAL count: INTEGER RANGE 0 TO 100; 2. SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); •

assignment operator for a SIGNAL is ‘‘<=’’ (Ex.: count<=35;).

Example : Count Ones #1 (not OK) • This code has multiple assignments to the same signal, temp, in lines 15 (once) and 18 (eight times). (line 18 conflicts with line 15),Code1 --------------------------------------1. LIBRARY ieee; 2. USE ieee.std_logic_1164.all; 3. --------------------------------------4. ENTITY count_ones IS 5. PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0); 6. ones: OUT INTEGER RANGE 0 TO 8); 7. END count_ones; 8. ---------------------------------------

Count Ones #1

(not OK)

Code2

10. ARCHITECTURE not_ok OF count_ones IS 11. SIGNAL temp: INTEGER RANGE 0 TO 8; 12. BEGIN 13. PROCESS (din) 14. BEGIN 15. temp <= 0; -- one time 16. FOR i IN 0 TO 7 LOOP 17. IF (din(i)='1') THEN 18. temp <= temp + 1; -- eihts times 19. END IF; 20. END LOOP; 21. ones <= temp; 22. END PROCESS; 23. END not_ok; 24. ---------------------------------------

VARIABLE • VARIABLE represents only local information • can only be used inside a PROCESS, FUNCTION, or PROCEDURE (that is, in sequential code), • its value can not be passed out directly • its update is immediate, so the new value can be promptly used in the next line of code.

• Syntax • VARIABLE name : type [range] [:= init_value];

• Examples: VARIABLE control: BIT := '0'; VARIABLE count: INTEGER RANGE 0 TO 100; VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";

• VARIABLE can only be used in sequential code • its declaration can only be done in the declarative part of a PROCESS, FUNCTION, or PROCEDURE. • assignment operator for a VARIABLE is ‘‘:=’’ (Ex.: count:=35;).

Example : Count Ones #2 1. 2. 3. 4. 5. 6. 7. 8. 9.

(OK) code1

--------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------ENTITY count_ones IS PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0); ones: OUT INTEGER RANGE 0 TO 8); END count_ones; ---------------------------------------

Count Ones #2

(OK) code2

10.ARCHITECTURE ok OF count_ones IS 11.BEGIN 12. PROCESS (din) 13. VARIABLE temp: INTEGER RANGE 0 TO 8; 14. BEGIN 15. temp := 0; -- variable 16. FOR i IN 0 TO 7 LOOP 17. IF (din(i)='1') THEN 18. temp := temp + 1; -- variable 19. END IF; 20. END LOOP; 21. ones <= temp; 22. END PROCESS; 23.END ok; 24.---------------------------------------

SIGNAL x VARIABLE Assignment

SIGNAL

VARIABLE

<=

:=

Utility

Represents circuit interconnects (wires)

Represents local information

Scope

Can be global (seen by entire code)

Local (visible only inside the corresponding PROCESS, FUNCTION, or PROCEDURE)

Behavior

Update is not immediate in sequential code (new value generally only available at the conclusion of the PROCESS, FUNCTION, or PROCEDURE)

Updated immediately (new value can be used in the next line of code)

In a PACKAGE, ENTITY, or ARCHITECTURE. In an ENTITY, all PORTS are SIGNALS by defaul

Only in sequential code, that is, in a PROCESS, FUNCTION, or PROCEDURE

Usage

Bad versus Good Multiplexer, some difference using SIGNAL and VARIABLE.

a classical example regarding the choice of a SIGNAL versus a VARIABLE. an assignment to a VARIABLE is immediate, but that is not the case with a SIGNAL.

1-- Solution 1: using a SIGNAL ( not ok ) -2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ----------------------------------------5 ENTITY mux IS 6 PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; 7 y: OUT STD_LOGIC); 8 END mux; 9 ----------------------------------------10 ARCHITECTURE not_ok OF mux IS 11 SIGNAL sel : INTEGER RANGE 0 TO 3; 12 BEGIN 13 PROCESS (a, b, c, d, s0, s1) 14 BEGIN 15 sel <= 0; 16 IF (s0='1') THEN sel <= sel + 1; 17 END IF; 18 IF (s1='1') THEN sel <= sel + 2; 19 END IF; 20 CASE sel IS 21 WHEN 0 => y<=a; 22 WHEN 1 => y<=b; 23 WHEN 2 => y<=c; 24 WHEN 3 => y<=d; 25 END CASE;

1 -- Solution 2: using a VARIABLE (ok) ---2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ----------------------------------------5 ENTITY mux IS 6 PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; 7 y: OUT STD_LOGIC); 8 END mux; 9 ----------------------------------------10 ARCHITECTURE ok OF mux IS 11 BEGIN 12 PROCESS (a, b, c, d, s0, s1) 13 VARIABLE sel : INTEGER RANGE 0 TO 3; 14 BEGIN 15 sel := 0; 16 IF (s0='1') THEN sel := sel + 1; 17 END IF; 18 IF (s1='1') THEN sel := sel + 2; 19 END IF; 20 CASE sel IS 21 WHEN 0 => y<=a; 22 WHEN 1 => y<=b; 23 WHEN 2 => y<=c; 24 WHEN 3 => y<=d; 25 END CASE; 26 END PROCESS; 27 END ok; 28 ---------------------------------------

Common mistake • A common mistake when using a SIGNAL is not to remember that it might require a certain amount of time to be updated. • This is not a problem when using a VARIABLE, for its assignment is always immediate. • A second aspect that might be a problem in solution 1 is that “more than one assignment is being made to the same SIGNAL (sel, lines 15, 16, and 18)”, which might not be acceptable. (Generally, only one assignment to a SIGNAL is allowed within a PROCESS,)

Solution 1

Solution 2

only solution 2 works properly.

1 ---- Solution 1: not OK --------------2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 --------------------------------------5 ENTITY dff IS 6 PORT ( d, clk: IN STD_LOGIC; 7 q: BUFFER STD_LOGIC; 8 qbar: OUT STD_LOGIC); 9 END dff; 10 --------------------------------------11 ARCHITECTURE not_ok OF dff IS 12 BEGIN 13 PROCESS (clk) 14 BEGIN 15 IF (clk'EVENT AND clk='1') THEN 16 q <= d; 17 qbar <= NOT q; 18 END IF; 19 END PROCESS; 20 END not_ok; 21 --------------------------------------Bersamaan di dalam process (16-17)

1 ---- Solution 2: OK ------------------2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 --------------------------------------5 ENTITY dff IS 6 PORT ( d, clk: IN STD_LOGIC; 7 q: BUFFER STD_LOGIC; 8 qbar: OUT STD_LOGIC); 9 END dff; 10 --------------------------------------11 ARCHITECTURE ok OF dff IS 12 BEGIN 13 PROCESS (clk) 14 BEGIN 15 IF (clk'EVENT AND clk='1') THEN 16 q <= d; 17 END IF; 18 END PROCESS; 19 qbar <= NOT q; 20 END ok; 21 --------------------------------------Tdk bersamaan & di luar process (19)

Shift Register

• One uses a SIGNAL to generate the flip-flops, while the other uses a VARIABLE. • In solution 1, registers are created because an assignment to a signal is made at the transition of another signal (lines 17–18). • In solution 2, the assignment at the transition of another signal is made to a variable (lines 17–18), • but since its value does leave the process (that is, it is passed to a port in line 20), it too infers registers.

1 ---- Solution 1: With an internal SIGNAL --2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -------------------------------------------5 ENTITY shiftreg IS 6 PORT ( d, clk, rst: IN STD_LOGIC; 7 q: OUT STD_LOGIC); 8 END shiftreg; 9 -------------------------------------------10 ARCHITECTURE behavior OF shiftreg IS 11 SIGNAL internal: STD_LOGIC_VECTOR (3 DOWNTO 0); 12 BEGIN 13 PROCESS (clk, rst) 14 BEGIN 15 IF (rst='1') THEN 16 internal <= (OTHERS => '0'); 17 ELSIF (clk'EVENT AND clk='1') THEN 18 internal <= d & internal(3 DOWNTO 1); 19 END IF; 20 END PROCESS; 21 q <= internal(0); 22 END behavior; 23 --------------------------------------------

1 -- Solution 2: With an internal VARIABLE --2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -------------------------------------------5 ENTITY shiftreg IS 6 PORT ( d, clk, rst: IN STD_LOGIC; 7 q: OUT STD_LOGIC); 8 END shiftreg; 9 -------------------------------------------10 ARCHITECTURE behavior OF shiftreg IS 11 BEGIN 12 PROCESS (clk, rst) 13 VARIABLE internal: STD_LOGIC_VECTOR (3 DOWNTO 0); 14 BEGIN 15 IF (rst='1') THEN 16 internal := (OTHERS => '0'); 17 ELSIF (clk'EVENT AND clk='1') THEN 18 internal := d & internal(3 DOWNTO 1); 19 END IF; 20 q <= internal(0); 21 END PROCESS; 22 END behavior; 23 --------------------------------------------

Latihan • •

VHDL ‘‘Numerical’’ Objects Given the following VHDL objects:

o o o o

CONSTANT max : INTEGER := 10; SIGNAL x: INTEGER RANGE -10 TO 10; SIGNAL y: BIT_VECTOR (15 DOWNTO 0); VARIABLE z: BIT;

•

Determine which among the assignments below are legal

o o o o o o o o

x <= 5; x <= y(5); z <= '1'; z := y(5); WHILE i IN 0 TO max LOOP... FOR i IN 0 TO x LOOP... G1: FOR i IN 0 TO max GENERATE... G1: FOR i IN 0 TO x GENERATE...

programmable data delay circuit

•

The input (d) and output (q) are 4-bit buses. Depending on the value of sel (select), q should be one, two, three, or four clock cycles delayed with respect to d. a) Write a VHDL code for this circuit; b) How many flip-flops do you expect your solution to contain? c) Synthesize your solution and open the report file. Verify whether the actual number of flip-flops matches your prediction.