Shashi Sdh

OTA000004 SDH Principle Issue 2.1

Confidential Information of Huawei. No Spreading without Permission.

1

Objectives

Upon completion of this course, you will be able to: Understand the basic of SDH multiplexing standard

‰

Know the features, applications and advantages of SDH based equipment ‰

Internal Use

Chapter1 SDH Overview Chapter2 Frame Structure & Multiplexing

Methods Chapter3 Overhead & Pointers Chapter4 Logical Functional Blocks

Internal Use

References

‰

SDH Principle Manual

‰

ITU-T G.701, G.702, G.707

Internal Use

Emergence of SDH

What is SDH? ---- Synchronous Digital Hierarchy ---- It defines frame structure, multiplexing method, digital rates hierarchy and interface code pattern. Why did SDH emerge? ---- Need for a system to process increasing amounts of information. ---- New standard that allows mixing equipment from different suppliers.

Internal Use

Disadvantages of PDH 1. Interfaces Plesiochronous Digital Hierarchy

Electrical interfaces --- Only regional standards. 3 PDH rate hierarchies for PDH: European (2.048 Mb/s), Japanese, North American (1.544 Mb/s). Optical interfaces --- No standards for optical line equipments, manufacturers develop at their will.

Internal Use

Disadvantages of PDH 2. Multiplexing methods Asynchronous Multiplexing for PDH The location of low-rate signals in high-rate signals is not regular nor predictable.

Internal Use

Disadvantages of PDH

140 Mb/s

140 Mb/s 34 Mb/s

34 Mb/s 8 Mb/s

8 Mb/s

de-multiplexer multiplexer

de-multiplexer de-multiplexer

multiplexer

2 Mb/s

level by level Not suitable for huge-volume transmission Internal Use

multiplexer

Disadvantages of PDH

3. OAM function --- Weak Operation, Administration & Maintenance function.

4. No universal network management interface --- Capabilities to setup a TMN is limited.

Telecommunications Management Network Internal Use

Advantages of SDH

1. Interfaces Electrical interfaces ---

Can be connected to all existing PDH signals.

Optical interfaces --Can be connected to multiple vendors’ optical transmission equipments.

Internal Use

Advantages of SDH 2. Multiplexing method --- Basic rate is STM-1, other rates are multiples of the basic rate --- PDH signal to/from SDH signal --- Low level SDH to/from high level SDH

STM-1

622 Mbit/s Multiplexing

De-multiplexing

622 Mbit/s

STM-1

STM-4

STM-1

2 Mbit/s Internal Use

STM-1

Low rate SDH

High rate SDH

Advantages of SDH

Low rate SDH to higher rate SDH

STM-1 155 Mb/s

Internal Use

×4

STM-4 622 Mb/s

×4

STM-16 2.5 Gb/s

×4

STM-64 10 Gb/s

Advantages of SDH byte interleaved multiplexing method

One Byte from STM-1 B

STM-1 A STM-1 B STM-1 C STM-1 D Internal Use

A

4:1

B

C

D

A

B

STM-4

C

D

A

B

…

Advantages of SDH

--- Synchronous multiplexing mapping structure

method

and

flexible

--- Use multistage pointer to align PDH loads in SDH frame, thus, dynamic drop-and-insert capabilities

Internal Use

Advantages of SDH

3. OAM function --- Abundant overheads bytes for operation, administration and maintenance. --- About 5% of the total bytes are being used

Internal Use

Advantages of SDH

4. Compatibility PDH, SDH, ATM, FDDI Signals packing

package

SDH network

STM-N

Processing

transmit

STM-N receive

package Processing unpacking PDH, SDH, ATM, FDDI Signals

Internal Use

Disadvantages of SDH Low bandwidth utilization ratio. Signal

Digital Bit Rate

Channels

E0

64 kbit/s

One 64 kbit/s

E1

2.048 Mbit/s

32 E0

E2

8.448 Mbit/s

128 E0

E3

34.368 Mbit/s

16 E1

E4

139.264 Mbit/s

64 E1

PDH Hierarchy

Bit Rate

Abbreviated

SDH

SDH Capacity

155.52 Mbit/s

155 Mbit/s

STM-1

63 E1, 3 E3 or 1 E4

622.08 Mbit/s

622 Mbit/s

STM-4

252 E1, 12 E3 or 4 E4

2488.32Mbit/s

2.5 Gbit/s

STM-16

1008 E1, 48 E3 or 16 E4

9953.28Mbit/s

10 Gbit/s

STM-64

4032 E1, 192 E3, 64 E4

SDH Hierarchy Internal Use

Questions

1. Why did SDH emerge? 2. What are the advantages & disadvantages of SDH? 3. What is the basic transmission rate in SDH and what are the other common ones?

Time to think Soon Coffee Time!

Internal Use

Chapter1 SDH Overview Chapter2 Frame Structure & Multiplexing

Methods Chapter3 Overhead & Pointers Chapter4 Logical Functional Blocks

Internal Use

Part 2 SDH Frame Structure From ITU-T G.707: 1.

2.

3. 4.

One frame lasts for 125 microseconds (8000 frames/s) Rectangular block structure 9 rows and 270 columns(STM-1) Each unit is one byte (8 bits) Transmission mode: Byte by byte, row by row, from left to right, from top to bottom

Frame = 125 us

1 2 3 4 5 6 7 8 9

9 rows

270 Columns

Bit rate of STM-1= 9*270*8*8000 Internal Use

SDH Frame Structure

Frame = 125 us

Three parts: 1. Information Payload 2. Section Overhead 3. AU-PTR

1 2 3 4 5 6 7 8 9

RSOH AU-PTR

Information Payload

MSOH

9 270 Columns

Internal Use

9 rows

Information Payload Information Payload √ √ √ √

Also known as Virtual Container level 4 (VC-4) Used to transport low speed tributary signals Contains low rate signals and Path Overhead (POH) Location: rows #1 ~ #9, columns #10 ~ #270

LPOH, TU-PTR RSOH package 9 rows

HPOH

AU-PTR

low rate signal

Payload

MSOH

package

LPOH, TU-PTR 9 Internal Use

1 270 Columns

Data package

Section Overhead Fulfills the section layer OAM functions 1 2 3

RSOH

Types of Section Overhead

AU-PTR 5 6 7 8 9

Information Payload

MSOH

9 270 Columns

Internal Use

9 rows

1.

RSOH monitor the regenerator section 2. MSOH monitor the multiplexing section Location: 1. RSOH: rows #1 ~ #3, columns #1 ~ #9 2. MSOH: rows #5 ~ #9, columns #1 ~ #9

AU-PTR Indicates the first byte of VC4 ► Location: row #4, columns #1 ~ #9

RSOH 4 AU-PTR

Information Payload

MSOH

9 270 Columns

Internal Use

9 rows

SDH Multiplexing SDH Multiplexing includes: √ Low to high rate SDH signals (STM-1 Æ STM-N) √ PDH to SDH signals (2M, 34M & 140M Æ STM-N) √ Other hierarchy signals to SDH Signals (ATM Æ STM-N)

Some terms and definitions: ► Mapping ► Aligning ► Multiplexing

Internal Use

SDH Multiplexing Structure ×1 STM-64 STM-16 STM-4

×1 ×1 ×1

STM-1

AUG-64 ×4

Mapping Aligning Multiplexing

AUG-16 ×4

Pointer processing

AUG-4 ×4

×1 AU-4

AUG-1

VC-4

C-4

139264 kbit/s

×3

TUG-3

×1

TU-3

VC-3

C-3

34368 kbit/s

TU-12

VC-12

C-12

2048 kbit/s

×7 TUG-2

×3 Internal Use

SDH Tributary Multiplexing (140M) 140 Mbit/s to STM-N C4

VC4 1

140M

Rate adaptation

H P O H

Add HPOH

9 Mapping 1

Internal Use

260 125 μs

1

1

Next page 9 125μs

261

SDH Tributary Multiplexing (140M) AU-4 10 Add AU-PTR

STM-1

AUG-1 1

270

AU-PTR

×1

RSOH

Add SOH

AU-PTR

9

Aligning

1

Add SOH 9

Internal Use

Info Payload

MSOH STM-N

Multiplexing AUG-N

One STM-1 frame can load only one 140Mbit/s Signal

270

270X N

SDH Tributary Multiplexing (34M) 34 Mbit/s to STM-N

C3

VC3 1

34M

Rate Adaptation

L P O H

Add LPOH

9 84

1 125μs

Internal Use

Mapping

1

1

Next page 9 125μs

85

SDH Tributary Multiplexing (34M)

TU-3 1 H1 H2 H3

TUG-3 1

86

Fill gap

9

Aligning

Internal Use

86

1

3

261

1

1 H1 H2 H3

1

1st align

VC-4

P O R R H

×3 R

9

9

Multiplexing

Same procedure as 140M

SDH Tributary Multiplexing (2M) 2 Mbit/s to STM-N

1

1 LPOH

4 1

2M

Rate Adaptation

Add LPOH

125μs

4

1 1

9

Internal Use

TU12

VC12

C12

1 Next page

Add TU-PTR

9

Mapping

4

Aligning

9 TU-PTR

SDH Tributary Multiplexing (2M) TUG-3

TUG-2 1

86

1

12 1

1 ×7

×3

R

9

Multiplexing

Internal Use

Multiplexing

R

9

Same procedure as 34M

Questions

Internal Use

1.

What are the main parts of the SDH Frame structure?

2.

What is the transmission speed of STM-4? How to calculate it?

Glossary

► Mapping - A process used when tributaries are adapted into VCs by adding POH information ► Aligning - This process takes place when a pointer is included in a Tributary Unit (TU) or an Administrative Unit (AU), to allow the 1st byte of the VC to be located ► Multiplexing - This process is used when multiple loworder path signals are adapted into a higher-order path signal, or when high-order path signals are adapted into a Multiplexing Section

Internal Use

Glossary

C = Container VC = Virtual Container TU = Tributary Unit AU = Administrative Unit TUG = Tributary Unit Group AUG = Administrative Unit Group STM = Synchronous Transfer Module

Internal Use

Chapter1 SDH Overview Chapter2 Frame Structure & Multiplexing

Methods Chapter3 Overhead & Pointers Chapter4 Logical Functional Blocks

Internal Use

Part 3 Section Overheads R S O H

A1

A1

A1

A2

A2

A2

J0

B1

∆

∆

E1

∆

F1

D1

∆

∆

D2

∆

D3

AU-PTR B2 M S O H

D4 D7 D10 S1

B2

B2

K1 D5 D8 D11

STM-1 Internal Use

K2 D6 D9 D12 M1 E2 ∆ = Media dependent bytes

A1 and A2 Bytes ‹ Framing Bytes – Indicate the beginning of the STM-N frame ‹ The A1, A2 bytes are unscrambled ‹ A1 = f6H (11110110), A2 = 28H (00101000) ‹ In STM-N: (3XN) A1 bytes, (3XN) A2 bytes

STM-N

STM-N

STM-N

STM-N

Finding frame head Internal Use

STM-N

STM-N

A1 and A2 Bytes Framing

Find A1,A2 Y

N

OOF over 3ms LOF

Next process Internal Use

AIS

D1 ~ D12 Bytes

Data Communications Channels (DCC) Bytes ‹ RS-DCC – D1 ~ D3 – 192 kbit/s (3X64 kbit/s) ‹ MS-DCC – D4 ~ D12 – 576 kbit/s (9X64kbit/s)

NE

NE

NE

NE

DCC channel TMN

Internal Use

OAM Information: Operation, Administration and maintenance

E1 and E2 Bytes

‹ Orderwire Bytes ‹ E1 – RS Orderwire Byte – RSOH orderwire message ‹ E2 – MS Orderwire Byte – MSOH orderwire message

NE

NE

NE E1 and E2

Digital telephone channel E1-RS, E2-MS

Internal Use

NE

B1 Byte Bit interleaved Parity Code (BIP-8) Byte – ‹ A parity code (even parity), used to check the transmission errors over the RS ‹ B1 BBE is represented by RS-BBE( performance event)

BIP-8

A1 A2 A3 A4

00110011 11001100 10101010 00001111

B 01011010

Internal Use

STM-N

Rx

Tx

1#STM-N 2#STM-N

Calculate B1, B2

2#STM-N Verify B1 B2

1#STM-N

B2 Byte

Bit interleaved Parity Code (MS BIP-24) Byte ‹ This bit interleave parity NX24 code is used to check the bit errors over the MS ‹ B2 BBE is represented by MS-BBE( performance event) ‹ The mechanism of B2 is same like B1

Internal Use

M1 Byte Multiplexing Section Remote Error Indication Byte ‹ A return message from Rx to Tx ,when Rx find B2 bit errors ‹ A count of BIP-24xN (B2) bit errors ‹ Tx generate corresponding performance event MS-FEBBE

Traffic

Rx

Tx Return M1 Generate MS-FEBBE Internal Use

Find B2 bit errors Generate MS-BBE

K1 and K2( b1-b5)

Automatic Protection Switching (APS ) bytes

Transmitting APS protocol

Used for network multiplexing protection switch function

Internal Use

K2 (b6 ~ b8) ¾Rx detects K2 (b6b8)="111" generate MS-AIS alarm ¾ Rx detects K2 (b6b8)="110" generate MS-RDI alarm

Start

Detect K2(b6b8)

110

111 Generate MS-AIS

Return MSRDI Internal Use

Generate MS-RDI

S1 Byte Synchronization Status Message Byte (SSMB): S1 (b5~ b8) ¾ Value indicates the sync. level bits 5 ~ 8

Internal Use

Meaning

0000

Quality unknown (existing sync. Network)

0010

G.811 PRC

0100

SSU-A (G.812 transit)

1000

SSU-B (G.812 local)

1011

G.813 (Sync. Equipment Timing Clock)

1111

Do not use for sync.

Path Overheads 1

2 3 4 5 6 7

8 9

10 J1 B3 C2

VC-n Path Trace Byte Path BIP-8 Path Signal Label

G1

Path Status

F2

Path User Channel

H4

TU Multiframe Indi

F3

Path User Channel

K3

AP Switching

N1

Network Operator

Higher Order Path Overhead Internal Use

Path trace byte: J1

Detect J1

The first byte of VC-4 > User-programmable > The received J1 should match with the expected J1 >

N

HP-TIM

Internal Use

Match

Y

Next process

B3 Byte

> Path bit parity code byte (even parity code) Verify B3

> Used to detect bit errors ¾Mechanism is same like B1and B2

N

HP-BBE

Internal Use

correct

Y

Next process

Signal label byte: C2

> Specifies the mapping type in the VC-N

Detect C2

> 00 H Æ Unequipped 02 H Æ TUG structure 13 H Æ ATM mapping ¾The received C2 should match with the expected C2

N Y

Next process

Match

00H

N

Y

HP-UNEQ

HP-SLM

Insert AIS downward

Internal Use

Path Status Byte: G1

Detect receiving VC4

¾Return performance message from Rx to Tx > HP-REI Æ b1 ~ b4 N

> HP-RDI Æ b5 N

Next process

Internal Use

HPBBE

HPUNEQ HP-TIM HP-SLM

Y

Return HP-REI

Y

Return HP-RDI

Path Overheads Low Order Path Overhead

1

4

1 V5

J2

VC-12

N2

VC-12

K4

VC-12

9 500μs VC-12 multiframe Internal Use

VC-12

Path Overhead Bytes

V5 > First byte of the multiframe > Indicated by TU-PTR > Functions: Error checking, Signal Label and Path Status of VC-12 z b1 ~ b2 z b3 z b4 RFI) z b5 ~ b7 z b8

Internal Use

Æ Error Performance Monitoring (BIP-2) Æ Return Error detected in VC-12 (LP-REI) Æ Return Failure declared in VC-12 (LPÆ Signal Label for VC-12 Æ Indicate Defect in VC-12 path (LP-RDI)

Path Overhead Bytes

Detect V5 Detect b5-b7

N

Verify b1 b2

Y N

000

match Y

Match

N

LP-UNEQ

LP-BBE Next process

LP-SLM

Return LPRDI (b8) Internal Use

Y

Return LPREI (b3)

Next process

Pointers

Pointers

AU-PTR

Internal Use

TU-PTR

AU-PTR 1

RSOH Negative justification

4

H1YYH2FF H3H3H3

Positive justification

0— —

1—

—

------ 86— —

MSOH 9 1

435— — 436— — ------ 521— — 522— — 523— — -----608— —

RSOH

125us

696— — 697— — ------782— — 4

H1YYH2FFH3H3H3

0— —

1—

—

------ 86— —

MSOH 9 1

Internal Use

9

250us 270

TU-PTR 1

4

1

VC-12

9

VC-12

V1

VC-12

V2 500μs VC-12 multiframe TU POINTERS

Internal Use

VC-12

V3

V4

Questions ‰

Which byte is used to monitor the MS-AIS and MS-RDI?

‰

What is the mechanism for R-LOF generation?

‰

Which bytes implement the RS(MS/HP) error monitoring?

Internal Use

Chapter1 SDH Overview Chapter2 Frame Structure & Multiplexing

Methods Chapter3 Overhead & Pointers Chapter4 Logical Functional Blocks

Internal Use

Part 4 Common SDH NE TM (Terminal Multiplexer) z Two ports device: Line Port (Optical Port), Tributary Port z Used in the terminal station of a network z Cross-connect function: TU ÅÆ LU

TM STM-N

W E4

E1

Hua Wei Default Internal Use

E3

STM-M

Note: M
Common SDH NE

ADM (Add and Drop Multiplexer) z Three ports device: Tributary Port, Line Port West (Left), Line Unit East (Right) z Used as an intermediate station, the most important NE type z Cross-connect function: TU ÅÆ LU (W/E), LU (W) ÅÆ LU (E)

ADM STM-N

W

E E4

E1 E3 Internal Use

STM-M

STM-N

Note: M
Common SDH NE Applications of TM & ADM ADM W

STM-N

E E1

STM-N

E4 E3

Note: M
STM-M

ADM

TM

ADM

ADM

TM

ADM

ADM

chain ring Internal Use

ADM

Common SDH NE REG z Two ports device: LU (W) & LU (E) zUsed due to the long distance between Multiplexers z O/E, Signal regenerating

W

E REG

STM-N

Internal Use

STM-N

Common SDH NE DXC z Multi-port device z Used to interconnect larger number of STM-N signals z Can be used for the grooming (consolidating & segregating) of STM-Ns z Used in complex & backbone network z DXC m/n (m ≥ n) m represent highest cross-connect rate n represent lowest cross-connect rate

m or n

0

1

2

3

rate

64kb/s

2Mb/s

8Mb/s

34Mb/s 140Mb/s 155Mb/s

Internal Use

4

5

6

622Mb/s 2.5Gb/s

SDH Logical Functional Blocks

ITU-T recommends a unified basic functional block standard

Internal Use

Logical Functional Block for SDH Equipment TTF

w STM

A

SPI

B

RST

C

MST

D

MSP

E

MSA

F

HOI 140Mb/s

G.703

M

PPI

L

G

LPA

HPC

HPT F

LOI 2Mb/s 34Mb/s

G.703 K

PPI

HOA

J LPA

I

LPT

H LPC H

Note: Taking 2Mb/s as example

G

SEMF OHA

OHA Interface

SETS Internal Use

HPA

Q Interface F Interface

MCF

P D4—D12 SETPI

F HPT

N D1—D3

External Synchronous Signal Interface

SPI Functional Block SPI: Synchronous Physical Interface Æ Implements interface function Æ O/E, extracts timing signal from STM-N Æ Monitors corresponding alarm

SPI

Receiving AÆB

O/E Extract Timing Signal

Internal Use

Receive Fail R-LOS

Transmitting BÆA

E/O

RST Functional Block Receiving

BÆC

R-LOS

Framing

Put all “1” at C

A1, A2

RST: Regenerator Section Termination Æ Processes RS overheads Æ Processes RSOH in Rx direction Æ Writes RSOH in Tx direction Internal Use

Fail

Normal

R-OOF, R-LOF

Unscramble

All “1” at C

Process E1, D1~D3

Verify B1

RS-BBE

RST Functional Block

Transmitting CÆB

Internal Use

Writes

Scrambles

RSOH

STM-N frame

Calculates

Add E1

B1

D1-D3

MST Functional Block MST: Multiplex Section Termination Æ Processes MSOH

Receiving

CÆD

Extract APS

Detect

Detect

K1, K2 (b1-b5)

K2 (b6-b8)

B2

110 MS-RDI

Internal Use

111

Abnormal

MS-AIS All “1” at D

MS-BBE

Overflow MS-EXC (B2)

All “1” at D

MST Functional Block

Transmitting D→C

Write MSOH

Internal Use

Receiving MS-BBE

Receiving MS-AIS

Return M1ÆMS-REI

Return K2Æ110 MS-RDI

MST Functional Block

Concept of RS, MS

MST

RST

SPI

SPI RS (regenerator section) MS (multiplex section)

Internal Use

RST

MST

MSP Functional Block

MSP: Multiplex Section Protection Æ Implements MS layer protection switch Æ Switch conditions: R-LOS, R-LOF, MS-AIS alarm

Network topology

Functional Block Main Signal Path

Main TM

TM Stand-by

M S A

M S P

MST

MST

M S

MST

MST

P

Stand-by Signal Path

Internal Use

M S A

MSA Functional Block Receiving

MSA: Multiplexing Section Adaptation Æ Implements AUG to VC-4 or VC-4 to AUG conversion

EÆF

De-interleaved AUG Æ N×AU-4

Read AU-PTR

H1H2H3 are all “1” AU-AIS All “1” at F Internal Use

Invalid pointer or 8 NDF AU-LOP All “1” at F

MSA Functional Block

Transmitting FÆE

Internal Use

Writes

Byte interleaved

AU-PTR

N×AU- 4 Æ AUG

Functional Blocks

HPC: High-Order Path Cross-connection HPT: High-Order Path Termination Æ Processes HPOH in VC-4

Internal Use

HPT Functional Block

Receiving FÆG

Verify B3 Invalid Æ HP-BBE

Internal Use

Detect J1 Mismatch Æ HP-TIM

Detect C2 Mismatch Æ HP-SLM Æ 00H: HP-UNEQ

All “1” at G

All “1” at G

Transmit H4 to HPA

HPT Functional Block Transmitting GÆF

Write HO-POH

Internal Use

Receiving HP-BBE Return HP-REI (G1)

Receiving HP-TIM, HP-SLM, HP-UNEQ Return HP-RDI (G1)

Functional Block

z HOI: High-Order Interface (HPT, LPA, PPI) Æ 140 M --- VC-4 z HOA: High-Order Assemble (HPT, HPA) Æ VC-12 --- VC-4 z LPC: Low-Order Path Connection Æ For VC-12 & VC-3 Cross-connect Matrix Æ Only chooses route, does not process signals z LPT: Low-Order Path Adaptation Æ Real-Time Monitoring of Low-Order VC-12

Internal Use

Functional Block

LPA: Low-Order Path Adaptation Æ Implements pack/unpack and restores original signal Æ PDH <---> C PPI: PDH Physical Interface Æ Extract PDH tributary signal timing Æ Code pattern conversion Æ Interface between device and PDH line

Internal Use

PPI Functional Block

PPI

Receiving

Transmitting

LÆM

MÆL

JÆK

KÆJ

Code pattern conversion

Internal Use

Code pattern

No input signal

conversion

T-ALOS,

Extract timing

EX-TLOS

HPA Functional Block Receiving

HPA: High order Path Adaptation Æ Implements C4 to VC-12 conversion

GÆH

De-interleaved C4 Æ 63XTU-12

Read

TU-PTR

Internal Use

V1V2V3 are all “1”

Invalid pointer or 8 NDF

TU-AIS

TU-LOP

All “1” at H

All “1” at H

HPA Functional Block

Transmitting HÆG

Write Pointer TU-PTR, VC-12ÆTU12

Internal Use

Byte Interleave TU12ÆC-4

LPT Functional Block

LPT: Low-Order Path Termination Æ Process LO-POH

LPT

Receiving HÆI

Transmitting IÆH

Detect V5 LP-BBE LP-SLM, LP-UNEQ

Write LO-POH Receive LP-BBE, Return LP-REI Receive LP-SLM, UNEQ, Return LP-RDI

Internal Use

Auxiliary Functional Blocks

SEMF: Synchronous Equipment Management Function Æ Monitoring center of the whole equipment Æ Implements OAM of local equipment and other equipment MCF: Message Communication Function Æ Provides D1~D3 Interface for communication Æ Implements network management termination interface to equipment: f/Qx

Internal Use

Auxiliary Functional Blocks

SETS: Synchronous Equipment Timing Source Æ Provides local timing clock signal to other functional blocks Æ Provides timing clock signal to other equipment SETPI: Synchronous Equipment Timing Physical Interface Æ Provides external interface of SETS Æ External timing clock signal and output timing clock signal OHA: Overhead Access Æ Processes order wire messages E1, E2, F1

Internal Use

Alarm Flow Chart

R-LOF

R-LOS

MS-EXC

AU-LOP

MS-AIS

AU-AIS

HP-UNEQ

TU-AIS Internal Use

HP-TIM

HP-SLM

Internal Use