Seu_sram As A Process Monitor

)

... . . . .

To be presented at the International Conference on Microelectronic lest Structures (March 23, 1993)

SEU/SRAM AS A PROCESS MONITOR B. R, Ellaes and M. G. Buehler Jet Propulsion latlora~ory 300-329 4800 Oak Grove Drive Pasadena, CA 91109 ABSTRACT lhe SEU/SRAM is a 4-kbit Static Random Access Mmory (SRAM) designed to detect Single-Event Upsets (SEUS) produced by high energy par(icles. This device was used to dcternline the memory Cell the distribution in The variance in spontaneous flip potential. this potential was dctcrrnincci to be due to the variation in the n-MOSFEl threshold voltage. For a l.?-prn CMOS process, the standard deviation was found to be 8 nOJ. Using cumulative distribution and residual plots, and non-normally cells stuck distrit)uted cells are easily identified.

INTRODUCTION: lhc usc of matrixed test structures has [men shown to tJe an effective approach (0 collecting statistical data with respect to inverter threshold voltages [1], mrtal steps [?] , linewidths [2], and contact resistances requi re analog structures [3] . such instruments such as a digital voltmrter to determine the measured value. The SEU/SRAM can be used to obtain analog information using externally forced voltages and on-chip latches (nmory cells). ?his allows nlorc rapid measurements of analog parameters. The structure used in this study is the RADMON (RADiation MONitor), shown in Figure 1. Its primary purpose is to detect single-event upset particles and total dose radiation. lhe version used in this study [lr(!VicJllsly updated is an version of a fabricated 1.6-~mI CMOS chip [4]. It consists of an SEU/SRAM and two total dose P-FEIs. In this study the SEU/SRAM is evaluated as a process control test structure. The size of the RADMON, as shown in Figure 1, is small po;tion, 2.7 rnrr?, of the stepper field of 200 lhc nmory cell layout is shown in mm . Figure ?, TIN? SRAM was fatrricated with 1.2pm n-well CMOS process at a MOSIS brokered foundry, lhc SRAM cell schematic, shown in Figure 3, has a six-transistor memory cell with an

offset voltage, Vo, that is used to evaluate lhc the spontaneous cell flip potential. dimensions of the MOSFE_ls in the cell are The timing diagram for listed in lable 1. the operation of the cell is shown in Figure 4. This diagram shows that the cell has three modes of operation: Read, Write, and In the Read and Write cycles, V. = 5 Stare. v. ]nitially all the cells are written into ttlc initial state which is described in Figure 3. lhen the cells are operated in the Stare cycle in which V. is gradually lowered In this state to a potential Vo(stare). ionizing particles that deposit sufficient If V. is charge will flip individual cells. lowered sufficiently, the nmnory cells will lhis is the behavior flip spontaneously. that will be analyzed in this paper for its It will be usefulness as a process monitor. shown that the spontaneous flip potential is a measure of the uniformity of the threshold voltage of invcrter #1, Vlil.

MEMDRY CELL MODE1: flip behavior is lhe spontaneous cell explained hy the SRAM transfer curves shown in Figure 5. lhese curves were generat.cd using a simple model for the MOSFE1 drain current which does not include channel length lhe inverter has an input modulation [5]. 1 he voltage, Vin, and output voltage, Vout. CMOS invcrtcr transfer curve is divided into These regions five arc regions [G] . descrik]ed with respect to Vlrl = rl-fEl = p-FET threshold voltage, VT threshold -P inverter threshold voltage, and VTi voltage. in Region I, O < V irl ~ VTrl and Irl = IF] = O In Region 11, Vln s Vin ~ and Vout = VDD. In Region 111, Virl = Vli and lnsat ~ Iplin. In Region IV, VTi < Virl ‘out? ‘nsat ‘ lpsat” < VDO - VTF), Irllin = IF,sat. In Region V, VDD - Vlp ~ Virl s VDDI Irl = IF) = O and Vou t = O. lhe MOSFE1 drain currents arc: ( 1 ) ‘nlin ‘ F3n(Vin-Vln-Vout/2)Vout ( 2 ) lnsat ‘ (~n/~) (Virl-Vln)2

. cumulative distribution is: (3) lpl in = 0P(VDD-Vin-V_IP-(VDD-Vout)/2)

(6) N = Nt{l - crf[(Vo - Vol,)/Voo4?] }/2

. (VDD-Vout) (4) lp~at = (~P/2) (VDD-Vin-Vlp)2 where B = KP” We/Lc and VT is the threshold voltage. For p-FETs V1 is the magnitude of the threshold voltage. Also KP = PoCOX where 11 is the channel mobility, and C ~ is the Final fy We = Wgate oxide capacitancclarea. AW and LQ = l-AL where W and L are the asdrawn channel width and length respectively, AW and AL are the channel width and length correction factors, respectively. lhe MOSFET values used in the following analysis are shown in Table 2. The memory cell has two stable states located at the upper-left and lower-right corners of the chart shown in Figure 5. As VQ decreases from 5 V, the upper-left stable point follows a path dcscribcd by the circles shok’n in Figure 5. When V. = 1.5 V, the cell flips to the lower-left stable point.

EXPERIMENIA1 RESULTS: The memory cell V. distributions are shown in figure 6 for eleven chips from Wafer #l. As seen in Figure 6, the SRAMS have a distritwtion of offset voltages at which the The data was acquired by cells flip. lowering the offset voltage, Vo, and counting the numt)cr of flipped cells at that V. value. lhe memory was then reset and the offset voltage lowered to a V. that is 1 nlV lower than the previous value and again the number of flipped cells dctemlined. ?his process is Note repeated until all 4096 cells flip. that arc curves these Corrlplctcly That is for a given Vo, the deterministic. same cells flip. The distributions shown in Figure 6 arc Gaussian in nature and can bc characterized by the normal distribution with a mean of Vol{ and a standard deviation of Voo. The cumulative distribution plots for the chips shown in Figure 6 arc shown in Figure 7. lhe data is characterized by the cumulative probability function using: (5)

P(Voi>Vo)

‘ 1OO”(N - 0.5)/N[

where N is the number of flipped cells at V. and for this memory Nt = 4096. Ihc formula that dcscrihcs analytical the

where crf is the error function. The result of a least squares fit to each of the curves shown in Figure 7 is listed in Tat)lc 3. -fhe entire range of data was fitted. Notice that the with the curves largest standard deviations, namely chips #2 and #4, have CC1lS that deviate significantly from the The standard deviations main distribution. distributions is the for the tightest date Eming about observed to 8 mV. Previously observed standard deviation values for a 1.6-pm CMOS process were shout 10 mV [4] , Sclectcd chips are examined in detail in Figures 8 to 10 where the cumulative and distributions arc shown. residual 1 hc cumulative distribution allows a critical examination of the tails of the distributic)n. lhc residual distribution allows a critictil examination of the cells near the mean of the distritmtion. An example of a stuck colunm is shown in Figure 8 and a stuck cell is Acceptable behavior is shown in Figure 9. shown is shown in Figure 10. The results were simulated with a nomlally distributed sample. As seen in Figure 11., several data points fall slightly below the fitted line in the tails of the distributicjn. This sarnc behavior is shown in Figure 10. A sunmary of the results from all the wafers included in this study are shown in Figure 1?. These samples came from four wafers and arc tightly clustcrcd. Ihc mean offset voltage has a span of 30 rnV and the standard deviation of the offset voltage varies from 7 to 9 nO1. This is considered excellent CCI1 distributions for CC1lS located (a) within a chip, (b) bctwccn chips, and (c) t,ctwccn wafers.

DAIA ANAIYSIS: lhc interpretation of results follows from otlscrving the nature of the transfer curves shown in figure 5, A close examination of this figure reveals that the spontaneous flip point is dctcrmincd when V. reaches the threshold voltage of invcrtcr #l, VTil. lhc CMOS invcrtcr threshold voltage is determined tly the conditions given 111 in Region descrihcd above:

( 7 )

VDD + VTn{Br - VTP Vii=- ~+~r

where V1” is the n-MOSFEl threshold voltage, and VTP is the magnitude of the p-MOSFET threshold voltage. The Beta factor is:

The standard deviation of Vo , V “ “ duc to the variation in the n- ?fi :Iru;i:]j This conclusion was rcachcd as voltage. follows. Introducing the FET model parameters listed in lablc 2 into Eqs. (9) and (10) leads to:

(11) VTio2 = 0.055”VTpo2+0.586”VTrlo2+ 0.008.G KPn(Wn - AWn)(LP - ALP) (8) Br=!n=. KPP(WP - AWp)(ln - Aln) ‘P

for inverter #1. lhis equation shows that Vlno is the dominant parameter.

The invertcr threshold equation is plotted in Figure 13 and shows that for Br + 0, Vli = VDD - ‘Tp and ‘or ‘r + ‘$ ‘Ti = ‘Tn.

Now the results in Figure 12 and lable 3 can The mean offset he intcrprctcd as follows. voltage is:

Using propagation of error analysis, the variance of the inverter threshold voltage is:

(12) Vo,{ = Vlil

‘Tpo2

(9) Vli02 ‘-

,

-BrvTno7

(1 + hr)z (1 + {i,.)? Br(VDD - Vln - VIP)? i.G 4(1 + @)4

and

(13) V

oo

z VTnol

given in Eq. (13), is lhe conclusion, determined by the layout of lNV#l where Elr] = Thus by changing the layout of the 10.7. cells, various features of the cells can he sensed.

where CONCLUSION:

wno~ , ‘p02 , !no? ( 1 0 ) G=wer~

w,:

Lpo2

le:+i,[:

lhcse equations show that for Br = O, Vli = (VDD - Vlp,,)*VTpo and for E3r = Dj, VTi = ‘ln~l*vTno. flip was spontaneous point, Vo , determined to km equal to the invcrter voltage of lhis threshold invertcr #l. conclusion was reached as follows. The Beta factors for the two inverters in the memory = E3rl 10.7 and Br2 = 15.1. cell arc: Introducing these values into Eq, (7) leads to the invcrter thresholds: VTil = 1.48 V and Vli2 : 1.39 V. The VTil = 1.48 V is the flip shown in point spontaneous the sinwlation given in Figure 5. This value is close to the experimentally observed V. values C1OSC to 1.72 V sunmlarized in Figure 1?, ‘Ihc discrepancy between 1.48 and 1.72 is easily explained hy the sinplislic MOSIET model given in Eqs, (l)-(4). If channel length modulation was included in the MOSFE1 model , then the transfer curve for INVT#’1 would have a finite slope at the mid-point. lhis will increase the modeled spontaneous flip point from 1.48 V and bring the result closer to the experimental value of 1.72 V.

1 he

lhe SEU/SRAM provides data on the unifomlity lhe 4-ktJit SRAM memory of a CMOS process. voltages were found to t)e cell offset nomlally distributed. lhe offset voltage depends on the threshold voltage of invertcr #l and its distribution depends on the variation in VTnl. Cumulative distribution plots reveal SRAMS with stuck bits which appear in the tails of the distributicln, Residual plots reveal SRAMS with bits that do not flip according to a nomlal distribution 1 he near the rncan of the distribution. lhis observed variances were about 8 n$l. result is behavior considered excellent within a chip, chip-to-chip, and wafer-towafer. ?his result provides a measure of excellence to be met by future CMOS founclry runs.

REFERENCES:

1. D, J. Ilannaman, ct. al., “lnverter Matrix: A vehicle for assessing ttlc process quality () f parameter through invcrtcr analysis variance”, ICMIS Vol. 4, 107-111 (March 1991).

,.

?. H. Sayah and M. Eluchlcr, “lincwidth and resistance distribution mcasurcmcnts step using and addressable array”, ICMTS, Vol 3. 89-9? (1990). M. G. Buchlcr and Il. R. Sayah, “Contact 3. resistance mcasurcrncnts using an addressable array”, Proc. VLSI Multilevel lntcrconncct Confercncc , ??7-2’37 (1987). M. G. !3uchler, B. R. Blats, G. A. Soli, 4. N. 7amani, and K. A. Ilicks, “Design and Qualification of the SEU/lD Radiation Monitor Chip”, JPL Publication 92-18 (October 1, 1992) . Y. P. Tsividis, Operation and Modeling of the MOS transistor, McGraw-Hill (New York, 1987) .

5.

N. Wcste and K. Eshraghian, Principles of CMOS VISI Design, A systems Perspective, Addison-Wesley (Reading, MA, 1985).

Table 2. MOSFLT Model Parameters (Run N260, 1 0 = 20”C)0 ‘ARAM

I

UNIIS

MEAN

SIDEV

rl-FEl RESULIS VT O KP O Aw AL

‘ 2 /iA/V pm pm

p-FE’

RESULTS

0.69 69.00 0.46 0.46

f * f i

0.0101 1.2000 0.0200 0.0116

0.95 * 0.0087 0.5200 0.30 $ 0.0310 0.35 ~ 0.0180

Vl o KPO

23.00 !

AW Al

6.

Tatllc 3.

SEU/SkAM V. results. WAFER NO.1

CIIIP

ACKNOWLEDGMENT: The research described in this paper was the Center for Space performed by Microelectronics technology, Jet Propulsion Institute of laboratory, California technology, and was sponsored by the Strategic Defense Initiative Organization. lhc 1.2!-~mI CMOS SEU/SRAM is a part of RADMON designed for use on the SIRV (Space technology Research Vehicle) to be launched in 1994. The authors are indebted to MOSIS for brokering the CMOS fabrication and to Gcnma Tardio for the MOSFET model parameter data.

#l #2 #3 {4

#5 #6 f? #8

I

$9

#lo #11

Vopfvoo

1.7?46+0.0076 1.7202?0.0091 1.7226f0.0081 1.731930.0092 1.7209~0.0078 1.7224$0.0075 1.7247i0.0077 1.7099f0.0089 1.7236%0.0084 1.7108*O.OO79 1.7205*0.0078

File: lCM13322.doc

Table 1.

Dimensions of SEU/SRAM MOSFEIS.

FET

[(pm)

W (~ml)

Mnl Mrr?

1.? 1.2

Mpl MI)? Mtl

3,2 3.? 1.2

Mt?

1.2

2.4 3.? 2.4 ?,4 2.4 2.4

17.92 74.88 14,08 12,16 ---..--.-

180.8 16.9 255.5 16.9

Figure 1.

RADMON: 1.6 rrnl x 1.7 nml.

,– * lk- - - - - 4

~ , , ,T ,., , ,_T , ,.., , , , , Vo 1 V02

F. 4 )--2 hi

23 !1 ~ q? CY 2

Lll

c> yl

--

Memory cell: 33.6 pm x 36.0 pm. and n- and p-select layers are

V03

SF’ONIANEOUS FLIP POINT

V04

t , ., t1

d. 1

1

Mpl-(f3Ff)

i

M(1

-

lNV/2 Mp2’(ON)

“

-

VI

L.

~.l -

E@?

- 1f - -1 c+

~ /

~ 0 c) L, I n Q t+ ~ 2

VO

PMmclf S1 &S4&M 1

-i

“ L MCI

I Mnl(ON) Mr .,-/

L - r ” r Kx

-.

l.r

xx

Xxxm

L L }

xx

1

SIARE CYCIF s. (VDD

=

L

-.S

L L

liyure 4.

Figure 6. SEU/SRAM spontaneous flip response from eleven chi~s taken from 1.6-mrl CMOS Wafcr#l.

99.99 ~ 99.9 ‘ 1 99, 2 ,@ s go n) $ -/0 c1 50 Q 30 c> ‘ ! 10 01 > :, 1 c) 0,1

1.69

r

E-1 V. -w n,,.,,Ar

Dtllk-,, w> \

i

1 .7Ei

1.72 1.74 OrFSET VOLTAGE, VO (V)

0.01

W)

L

1s00

1.70

WF
2000

$mf,x,,%

..__.

.XxXx

R. Q-

2500

0

!

[ :OFt) ‘..1

SRAM memory cell circuit.

r

3000

4 fpulse



AXXXXXXX E.

--, t. CHIP41

500 Cfn?

Figure 3.

I

1000

v?

C4 Dnl

1

35EKf

).~I [“ +3

T

4000’

VLm

‘1”

—f-a::, :2= A—J._L ,. , t (A—, ., ... ., ~ 3 2 4 NODF NO, 1 VOLIAGE, V1 (V)

Figure 5. SRAM transfer curves showing the variation in the stable point, indicated by circles, as the offset voltage, VA. is lowered-to the $~JOntaneOUs flip p;i;t. ‘-

.—.

lNV# 1

lNv~l

-.

4 mo IVOF~D LINE

;:; : :;:; V04 = ?.OV V05 = 1.7V V06L 1.5V V07 = 1.3V

W&q?

0 MT.-M m+

Figure 2. n-well omitted.

I t ,-,-

V“7

o

lhe

1

Vol = 5.0 v

/VO(store)

SRAM memory cell timing diagram.

1.-/0

1.71 1 .7? 1.73 1,74 OF ISII VOITAC;f, VO (V)

1.75

Figure 7. Cumulative distribution plots for the chips shown in Figure 6.

~ 99.99 : 99.9

r

c1

99

.5 0

>

A

>

‘“i6 - - - - - --.5

-

--

so 30

n

u

c1

n -1 L

\ ‘k

r

10

~

1 0.1

m >

$-5 : N?6D -1o-

b

70

;

‘ Vh

,

it

90

-0

v WLu# I I :NlP#4 --

‘H t.??

1 .?0

““

1.74

Of}Sfl WLT,kGf,

WU4*$UJT.

2

H 1.76

VQ (V)

figure 8. Results from Chip#4 showing a stuck column.

0.01 1.69 1.-/0 1.71

Wrlx?,m Figure

6)

1.72 1.73

1.74

1.75 1.76

Of FSLl VOLIAGE, VO (V)

Figure 11, Ideal cumulative distribution plot for Vol[ = 1.72 V and Voo = 8mV.

,,, , ., —–—–, .––, .,,

0.010 e. > \/b

0

0

‘. 00 . 0 0 9 ~ t VI ~; o.~f3 ,<

0

o

I

1 . . . . ..

v

°

v

. . ‘---. . .. .. . 1 I

VW

4

$

I

t, 0.007 in II L1 c1

,

0.006 1.69 **14*1

w

OF~SO

Figure 9. Results showing a stuck bit.

99.99 99.9 >“ ~

‘

9

90 . . . . . . . . . . . . . . . . . .

Fij

: ““’”’’”’”

““’””’”””””

31 0.1 ‘“7A .8

,,

j

o

r ~

W3LTAGC,

from

,

4{/ :‘[1; I

,

,

,

,

_,_

ti.,, m-.

I

,.

1.71

1.77 1.73 OFFSEI VOLTAGE MEAN, VOP (V)

Ve (v)

Chip#2 .(Fiqurc 6)

,

1.70

1.74

Figure 1?. Standard deviation vs mean offset voltage for chips fabricated on four wafers. The lines are linear re~ression fits to data from each wafer,

, ,,, ,,,,,

! ,,, ,,,,,

r

,1,

!, IT.

,

,,, ,,,,,

,

rr,

,,,,~

,

,,,

,,

i

. .

+

b%

$

-5

Ej - I v .~ *W,,,,*

N?6D

fft R#l HIP#l 11.70 t .72

1,74

1.76

t

Ciool

,

,,,,,,,1

0.01

t

,,,,,,,1 ,

,,,,,,,1 ,

,,, ,,,,, ,

0.1

10

OFf Wl WLTACX V. (v)

Figure 10. Results from Chip#l (Figure 6) showing acceptable behavior.

W.’,,, ca m% Figure 1 3 . dependence

,,, ,,,,, ,

100

,,, ,,

1000

fir’ (b, lnverter threshold voltage o n tile MOSFE1 geonwtry f a c t o r I?Ir.