Semiconductor Manufacturing Technology: Oxidation

Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall

Chapter 10

Oxidation Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2000 2001 by Prentice Hall

Objectives After studying the material in this chapter, you will be able to: 1. Describe an oxide film for semiconductor manufacturing, including its atomic structure, how it is used and its benefits. 2. State the chemical reaction for oxidation and describe how oxide grows on silicon. 3. Explain selective oxidation and give two examples. 4. State the three types of thermal processing equipment, describe the five parts of a vertical furnace, and give the attributes of a fast ramp vertical furnace. 5. Explain what is a rapid thermal processor, its usage and design. 6. Describe the critical aspects of the oxidation process, its quality measures and some common troubleshooting problems. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Diffusion Area of Wafer Fabrication

Wafer fabrication (front-end) Wafer start Thin Films

Polish

Photo

Etch

Unpatterned wafer Diffusion

Completed wafer

Test/Sort

Implant

Used with permission from Advanced Micro Devices

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.1

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Oxide Film • Nature of Oxide Film • Uses of Oxide Film – – – – –

Device Protection and Isolation Surface Passivation Gate Oxide Dielectric Dopant Barrier Dielectric Between Metal Layers

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

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Atomic Structure of Silicon Dioxide Silicon

Oxygen

Used with permission from International SEMATECH Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.2

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Field Oxide Layer

Field oxide isolates active regions from each other.

p-well

n-well p- Epitaxial layer p+ Silicon substrate

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.3

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Gate Oxide Dielectric

Polysilicon gate Gate Oxide

p-well

n-well p- Epitaxial layer p+ Silicon substrate

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.4

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Oxide Layer Dopant Barrier

Phosphorus implant Barrier oxide n-well p- Epitaxial layer p+ Silicon substrate

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.5

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Table 10.1 Oxide Applications: Native Oxide Purpose:

This oxide is a contaminant and generally undesirable. Sometimes used in memory storage or film passivation.

Silicon dioxide (oxide)

p+ Silicon substrate

Comments: Growth rate at room temperature is 15 per hour up to about 40 Å. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1A

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Table 10.1 Oxide Applications: Field Oxide Purpose:

Serves as an isolation barrier between individual transistors to isolate them from each other.

Field oxide

Transistor site

p+ Silicon substrate

Comments: Common field oxide thickness range from 2,500 Å to 15,000 Å. Wet oxidation is the preferred method. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1B

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Table 10.1 Oxide Applications: Gate Oxide Purpose:

Serves as a dielectric between the gate and sourcedrain parts of MOS transistor.

Gate oxide

Gate

Source

Drain Transistor site

p+ Silicon substrate

Comments: Growth rate at room temperature is 15 Å per hour up to about 40 Å. Common gate oxide film thickness range from about 30 Å to 500 Å. Dry oxidation is the preferred method. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1C

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Table 10.1 Oxide Applications: Barrier Oxide Purpose:

Protect active devices and silicon from follow-on processing.

Barrier oxide

Metal

Diffused resistors p+ Silicon substrate

Comments: Thermally grown to several hundred Angstroms thickness. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1D

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Table 10.1 Oxide Applications: Dopant Barrier Purpose:

Masking material when implanting dopant into wafer. Example: Spacer oxide used during the implant of dopant into the source and drain regions.

Dopant barrier spacer oxide

Ion implantation Gate

Spacer oxide protects narrow channel from high-energy implant

Comments: Dopants diffuse into unmasked areas of silicon by selective diffusion. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1E

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Table 10.1 Oxide Applications: Pad Oxide

Purpose: Provides stress reduction for Si3N4

Nitride

Pad oxide

Passivation Layer Bonding pad metal ILD-5

M-4 ILD-4 M-3

Comments: Thermally grown and very thin. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1F

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Table 10.1 Oxide Applications: Implant Screen Oxide Purpose:

Sometimes referred to as “sacrificial oxide”, screen oxide, is used to reduce implant channeling and damage. Assists creation of shallow junctions.

Ion implantation

Screen oxide

p+ Silicon substrate High damage to upper Si surface + more channeling

Low damage to upper Si surface + less channeling

Comments: Thermally grown Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1G

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Table 10.1 Oxide Applications: Insulating Barrier between Metal Layers Purpose: Serves as protective layer between metal lines.

Interlayer oxide Passivation layer Bonding pad metal ILD-5

M-4 ILD-4 M-3

Comments: This oxide is not thermally grown, but is deposited. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.1H

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Thermal Oxidation Growth • Chemical Reaction for Oxidation – Dry oxidation – Wet oxidation

• Oxidation Growth Model – Oxide silicon interface • Use of chlorinated agents in oxidation

– – – –

Rate of oxide growth Factors affecting oxide growth Initial growth phase Selective oxidation • LOCOS • STI

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

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Oxide Thickness Ranges for Various Requirements

Semiconductor Application

Typical Oxide Thickness, Å

Gate oxide (0.18 m generation) Capacitor dielectrics

20 – 60 5 – 100 400 – 1,200 (Varies depending on dopant, implant energy, time & temperature) 150 200 – 500 2,500 – 15,000

Dopant masking oxide STI Barrier Oxide LOCOS Pad Oxide Field oxide

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.2

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Dry Oxidation Time (Minutes) 10.0

Oxide thickness (m)

(100) Silicon

1.0

0.1

0.01 10

102

103

104

Time (minutes)

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Figure 10.6

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Wet Oxygen Oxidation Exhaust Scrubber Burn box

Gas panel

HCl

N2

O2

H2

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Furnace

Figure 10.7

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Consumption of Silicon during Oxidation

t

0.55t 0.45t

After oxidation

Before oxidation

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.8

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Liquid-State Diffusion

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.9

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Charge Buildup at Si/SiO2 Interface Silicon

Oxygen

SiO2 Positive charge

Silicon

Used with permission from International SEMATECH Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.10

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Diffusion of Oxygen Through Oxide Layer

Oxygen supplied to reaction surface

O, O2

Oxygen-oxide interface SiO2 Oxide-silicon interface

Si

Used with permission from International SEMATECH

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.11

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Linear & Parabolic Stages for Dry Oxidation Growth at 1100ºC

Oxidation thickness

4,000 Å

3,000 Å

2,000 Å

1,000 Å Approximate linear region

}

100

200

300

400

500

Oxidation time (minutes)

Used with permission from International SEMATECH Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.12

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LOCOS Process 2. Nitride mask & etch

1. Nitride deposition

Nitride

Pad oxide (initial oxide)

3. Local oxidation of silicon SiO2 growth

Silicon

SiO2 SiO2 Nitride

4. Nitride strip Silicon

Cross section of LOCOS field oxide (Actual growth of oxide is omnidirectional)

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.13

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Selective Oxidation and Bird’s Beak Effect

Silicon oxynitride Nitride oxidation mask

Bird’s beak region Selective oxidation

Silicon dioxide Pad oxide

Silicon substrate

Used with permission from International SEMATECH

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.14

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STI Oxide Liner 1. Nitride deposition

2. Trench mask and etch Nitride

Silicon

3. Sidewall oxidation and trench fill Oxide over nitride

Pad oxide (initial oxide) 4. Oxide planarization (CMP)

5. Nitride strip

Trench filled with deposited oxide Oxide

Sidewall liner

Silicon

Cross section of shallow trench isolation (STI) Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.15

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Furnace Equipment

• Horizontal Furnace • Vertical Furnace • Rapid Thermal Processor (RTP)

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Horizontal and Vertical Furnaces Performance Factor Typical wafer loading size Clean room footprint

Performance Objective

Horizontal Furnace

Vertical Furnace

Small, for process flexibility Small, to use less space Ideal for process flexibility

200 wafers/batch

100 wafers/batch

Larger, but has 4 process tubes Not capable

Gas flow dynamics (GFD)

Optimize for uniformity

Boat rotation for improved film uniformity Temperature gradient across wafer Particle control during loading/unloading

Ideal condition

Worse due to paddle and boat hardware. Bouyancy and gravity effects cause non-uniform radial gas distribution. Impossible to design

Smaller (single process tube) Capable of loading/unloading wafers during process, which increases throughput Superior GFD and symmetric/uniform gas distribution

Parallel processing

Quartz change Wafer loading technique Pre-and postprocess control of furnace ambient

Ideally small

Large, due to radiant shadow of paddle

Small

Minimum particles

Relatively poor

Easily done in short time Ideally automated

More involved and slow

Improved particle control from top-down loading scheme Easier and quicker, leading to reduced downtime Easily automated with robotics Excellent control, with options of either vacuum or neutral ambient

Control is desirable

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Easy to include

Difficult to automate in a successful fashion Relatively difficult to control

Table 10.3

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Horizontal Diffusion Furnace

Photograph courtesy of International SEMATECH Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Photo 10.1

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Vertical Diffusion Furnace

Photograph courtesy of International SEMATECH Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Photo 10.2

© 2001 by Prentice Hall

Block Diagram of Vertical Furnace System Microcontroller

Wafer handler controller

Temperature controller

Gas flow controller

Boat loader

Exhaust controller

Quartz process chamber Three-zone heater Gas panel

Heater 1 Heater 2

Heater 3

Quartz boat Process gas cylinder

Wafer load/unload system Boat motor drive system

Pressure controller

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Figure 10.16

Exhaust

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Vertical Furnace Process Tube

Heating jacket

Three-zone heating elements

Quartz tube End cap Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.17

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Heater Element Power Distribution 204 - 480 VAC 3f

Heater element transformer

Trigger circuit

SCRs

SCRs

SCRs Zone 3 Zone 2 Furnace heater elements

Zone 1

Used with permission from International SEMATECH Figure 10.18 Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

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Locations of Thermocouples in the Furnace Chamber Thermocouple measurements

Temperature controller Control TCs

Profile TCs

Heater 1

Overtemperature TCs

System controller

Heater 2

Heater 3 TC

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.19

© 2001 by Prentice Hall

Common Gases used in Furnace Processes Gases

Bulk

Specialty

Classifications

Examples

Inert gas

Argon (Ar), Nitrogen (N2)

Reducing gas

Hydrogen (H2)

Oxidizing gas

Oxygen (O2)

Silicon-precursor gas

Silane (SiH4), dichlorosilane (DCS) or (H2SiCl2)

Dopant gas

Arsine (AsH3), phosphine (PH3) Diborane (B2H6)

Reactant gas

Ammonia (NH3), hydrogen chloride (HCl)

Atmospheric/purge gas

Nitrogen (N2), helium (He)

Other specialty gases

Tungsten hexafluoride (WF6)

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Table 10.4

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Burn Box to Combust Exhaust To facility’s exhaust system Wet scrubber

Excess combustible gas burns in hot oxygen rich chamber Combustion chamber (burn box or flow reactor) O

Filter

2

Gas from furnace process chamber

O 2

Residue

Recirculated water Used with permission from International SEMATECH Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.20

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Thermal Profile of Conventional Versus Fast Ramp Vertical Furnace Conventional

Fast Ramp

1000

1000

Temperature (°C)

1200

Temperature (°C)

1200

800

600

800

600

400

400 0

20

40

60

80 100 120 140 160 180

Time (minutes)

0

20

40

60

80 100 120 140 160 180

Time (minutes)

Reprinted from the June 1996 edition of Solid State Technology, copyright 1996 by PennWell Publishing Company. Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.21

© 2001 by Prentice Hall

The Main Advantages of a Rapid Thermal Processor • Reduced thermal budget • Minimized dopant movement in the silicon • Ease of clustering multiple tools • Reduced contamination due to cold wall heating • Cleaner ambient because of the smaller chamber volume • Shorter time to process a wafer (referred to as cycle time)

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Comparison of Conventional Vertical Furnace and RTP Vertical Furnace

RTP

Batch

Single-wafer

Hot wall

Cold wall

Long time to heat and cool batch

Short time to heat and cool wafer

Small thermal gradient across wafer

Large thermal gradient across wafer

Long cycle time

Short cycle time

Ambient temperature measurement

Wafer temperature measurement

Issues:

Issues:

Large thermal budget

Temperature uniformity

Particles

Minimize dopant movement

Ambient control

Repeatability from wafer to wafer Throughput Wafer stress due to rapid heating Absolute temperature measurement

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.5

© 2001 by Prentice Hall

Rapid Thermal Processor Setpoint voltages

Heater head

Temperature controller

Wafer

Axisymmetric lamp array

Pyrometer

Reflector plate Optical fibers

Feedback voltages

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Figure 10.22

© 2001 by Prentice Hall

Rapid Thermal Processor

Photograph courtesy of Advanced Micro Devices, Applied Materials 5300 Centura RTP Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Photo 10.3

© 2001 by Prentice Hall

RTP Applications • Anneal of implants to remove defects and activate and diffuse dopants • Densification of deposited films, such as deposited oxide layers • Borophosphosilicate glass (BPSG) reflow • Anneal of barrier layers, such as titanium nitride (TiN) • Silicide formation, such as titanium silicide (TiSi2)

• Contact alloying Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Oxidation Process

• Pre Oxidation Cleaning – Oxidation process recipe

• Quality Measurements • Oxidation Troubleshooting

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Critical Issues for Minimizing Contamination • Maintenance of the furnace and associated equipment (especially quartz components) for cleanliness • Purity of processing chemicals • Purity of oxidizing ambient (the source of oxygen in the furnace) • Wafer cleaning and handling practices

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Thermal Oxidation Process Flow Chart Oxidation Furnace

Wet Clean • Chemicals • % solution • Temperature • Time

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• O2, H2 , N2 , Cl • Flow rate • Exhaust • Temperature • Temperature profile • Time

Figure 10.23

Inspection • Film thickness • Uniformity • Particles • Defects

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Process Recipe for Dry Oxidation Process

Step

Time (min)

Process Gas O2 HCl

Temp (ºC)

N2 Purge Gas (slm)

(slm)

(slm)

(sccm)

850

8.0

0

0

0

Idle condition Load furnace tube

0

N2

Comments

1

5

850

8.0

0

0

2

7.5

Ramp 20ºC/min

8.0

0

0

3

5

1000

8.0

0

0

Temperature stabilization

4

30

1000

0

2.5

67

Dry oxidation

5

30

1000

8.0

0

0

Anneal

6

30

8.0

0

0

Ramp temperature down

7

5

8.0

0

0

Unload furnace tube

Ramp -5ºC/min 850

Ramp temperature up

8 850 8.0 0 0 0 Idle Note: gas flow units are slm (standard liters per minute) and sccm (standard cubic centimeters per minute)

Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

Table 10.6

© 2001 by Prentice Hall

Wafer Loading Pattern in Vertical Furnace Calibration parameters:

Boat size: 160 wafers Boat pitch: 0.14 inch Wafer size: 8 inches Elevator speed: 9.29 cm/min Cool down delay: 20 minutes

160 4 Filler (dummy) wafers 1 Test wafer

75 Production wafers

1 Test wafer

75 Production wafers

1 Test wafer 4 Filler (dummy) wafers 1

Used with permission from International SEMATECH Figure 10.24 Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda

© 2001 by Prentice Hall

Chapter 10 Review • • • • • • •

Quality Measures Troubleshooting Summary Key Terms Review Questions Equipment Suppliers’ Web Sites References

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