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4 .11 BLOQUES ARITMÉTICOS Elena Valderrama Universidad Autónoma de Barcelona

4 .1 Los bloques aritméticos constituyen una parte importante en caso cualquier circuito  digital. Estudiaremos circuitos capaces de implementar las 4 operaciones básicas: 1. SUMA 2 RESTA 2. RESTA 3. MULTIPLICACIÓN 4. DIVISIÓN

2

4 .1 1. Suma binaria Sumador paralelo: Ver lecciones 2.2 y 2.3 de la semana 2. xi

yi

n n

acarreo0

1

Sumador          n+1 n bits

Sumador    1 bit

acarreoOUT

acarreoIN Full_Adder (FA)

zi xn-1

acarreoOUT

yn-1

Sumador    1 bit

zn-1

xn-2

Sumador    1 bit

zn-2

x1

yn-2

…

y1

Sumador    1 bit

z1

x0

y0

Sumador    1 bit

acarreoIN

z0 3

4 .1 2. Resta binaria Un restador binario realiza el cálculo:  n n

donde: 

acarreo0: 1 bit  (habitualmente igual a 0) (habitualmente igual a 0) 

acarreo0

1

n+1 Restador Restador           n bits

¿Cómo representamos un número negativo? , se representa por un número de n+1  p p Si D<0, D bits llamado el “complemento a 2” de D: 

4

4 .1 2. Resta binaria Algoritmo “manual”: 

1 1 0 0

1 0 0 1

1 0 0 1

1 1 0 0

n pasos, en cada paso calculamos:   El bit “resta”:  El acarreo hacia la etapa  siguiente: g

5

4 .1 2. Resta binaria Algoritmo‐1 de la resta acarreo(0) <= acarreo_inicial;  ‐‐ (habitualmente 0) for i in 0 to n‐1 loop in 0 to n 1 loop d(i) <= (x(i) + y(i) + acarreo(i)) mod 2; acarreo(i+1) <= sign(x(i) ‐ y(i) ‐ acarreo(i)); p; end loop; s(n) <= acarreo(n);

Algoritmo‐2 de la resta acarreo(0) <= acarreo_inical; ;  ‐‐ (habitualmente 0) for i in 0 to n‐1 loop d(i) <= x(i) xor y(i) xor acarreo(i); acarreo(i+1) <=  (not(x(i)) and y(i)) or (not(x(i)) and acarreo(i)) (not(x(i)) and y(i)) or (not(x(i)) and acarreo(i))  or (y(i) and acarreo(i)); end loop; s(n) <= acarreo(n);

6

4 .1 2. Resta binaria

n

Restador           n+1 n bits

n

xi

acarreoOUT

yi

1

acarreo0

Restador    1 bit

 

acarreoIN

Full_Substractor ((FS)) di xn-1

dn=acarreoOUT

yn-1

xn-2

FS

FS

dn-1

dn-2

d(i) <= x(i) xor y(i) xor acarreo(i); acarreo(i+1) <=  (not(x(i)) and y(i)) or (not(x(i)) and acarreo(i)) or (y(i) and acarreo(i)) or (y(i) and acarreo(i))

x1

yn-2

…

y1

x0

y0

FS

FS

d1

d0

acarreoIN

7

4 .1 (Ejercicio) Construir un circuito que calcule D = x ‐ y (x, y de n bits) y devuelva el valor de D en la  representación clásica de “signo representación clásica de  signo y magnitud y magnitud”,, es decir, como D es decir, como D = ((‐1) 1)sign∙|D |D| Sugerencia: Calcula en paralelo x – y and y– x y selecciona el |D| dependiendo del signo de x – y.

8

4 .1 (Solución del ejercicio) (Solución del ejercicio) Construir un circuito que calcule D = x ‐ y (x, y de n bits) y devuelva el valor de D en la  p g y g , , = (‐1) ( )sign∙|D| | | representación clásica de “signo y magnitud”, es decir, como D Sugerencia: Calcula en paralelo X – Y and Y – X y selecciona el |D| dependiendo del signo de X – Y. x

y

subtract. Restador

y

0

subtract. Restador

d’ d

0

d’’ d 0

sign

x

1

d 9

4 .1 3. Multiplicador binario Un multiplicador realiza el cálculo: 

donde:  Algoritmo1:

Mayor valor de P: 

p0 = X∙y X 0; p1 = X∙y1∙2; p2 = X∙y2∙22; ∙∙∙ pm‐1 = X∙ym‐1∙2m‐1; P = p0 + p1 + p2 + ∙∙∙ + pm‐1 .

 P es un número de n+m bits 10

3. Multiplicador binario

4 .1

Algoritmo1: p0 = X∙y0; p1 = X∙y1∙2; p2 = X∙y2∙22; ∙∙∙ pm‐1 = X∙ym‐1∙2m‐11; P = p0 + p1 + p2 + ∙∙∙ + pm‐1 .

Ej Ejemplo:  l 101101 x 1011 ‐‐‐‐‐‐‐‐‐ 101101   p0 101101     p1 000000 000000       p2  101101         p3 ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ 111101111    P 11

3. Multiplicador binario

4 .1

p0 = X∙y0; p1 = X∙y1∙2; p2 = X∙y2∙22; ∙∙∙ pm‐1 = X∙ym‐1∙2m‐1; P = p0 + p1 + p2 + ∙∙∙ + pm‐1 . Algoritmo2: “Right‐to left algorithm” acc <= 0; for i in 0 to m‐1 loop acc <= acc + X*(2**i)*y(i); end loop; P< P <= acc; 12

4. Divisor binario

4 .1

Dados dos números X e Y naturales (X < Y),  dividir X entre Y (X/Y ) consiste en calcular  Q yy R tales que:  q dos números Q

Para calcular X/Y cuando X  Y será necesario alinear previa y convenientemente los operandos.

13

4 .1

4. Divisor binario Algoritmo de división binaria r(0) <= x; for i in 1 to p loop in 1 to p loop d <= 2*r(i‐1) ‐ y; if d < 0 then q(i) <= 0; r(i) <= 2*r(i‐1); else q(i) <= 1; r(i) < else q(i) < 1; r(i) <= d; d; end if; end loop; Resultado: Q = (q1 q2 ∙∙∙ qp‐1 qp)∙2‐p,   R = r = rp∙2‐pp.

Ejemplo:  X = 21, Y = 35, p = 6 iteración  0 1  2  3 4  5  6 

r  21 7  14  28 21  7  14 

q  ‐ 1  0  0 1  1  0 

d  ‐ 7  ‐21  ‐7 7 21  7  <0 

comentarios  ‐ D = 42‐35 = 7  D = 14‐35 = ‐21 D = 28‐35 = ‐7 D = 56‐35 = 21 D = 42‐35 = 7 D = 28‐35 < 0

Q =  [100110]2 . 2‐p = 38/64 = [0,100110]2, R = 14/64 = [0,001110]2 

14

4. Divisor binario

4 .1

Algoritmo de división binaria r(0) <= x; for i in 1 to p loop in 1 to p loop d <= 2*r(i‐1) ‐ y; if d < 0 then q(i) <= 0; r(i) <= 2*r(i‐1); else q(i) <= 1; r(i) < else q(i) < 1; r(i) <= d; d; end if; end loop;

15

4 .1 RESUMEN 

Hemos visto un conjunto de circuitos capaces de ejecutar las operaciones aritméticas  básicas de suma, resta, multiplicación y división.



Hemos introducido, aunque muy brevemente, la representación de números negativos  mediante el complemento a 2.

16

4 .22 Short introduction to VHDL Lluís Terés Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC) Universitat Autònoma de Barcelona (UAB)

CONTENTS 1. 1 2. 3. 4 4. 5. 6. 7 7.

4 .2

Main goals & Expected learning M i l &E t dl i Basics on VHDL lexical & syntax VHDL Design Units VHDL Sequential Sentences (selection) VHDL Sequential Sentences (selection) VHDL Concurrent Sentences (selection) VHDL usage for modelling, simulation and synthesis  Summary

18

Main goals & Expected learning

4 .2

M i Main goals l • •

•

VHDL syntax, main units and structure Fundamentals on sequential and concurrent statements • Processes • Component instances • Signal assignments VHDL usage: modelling, simulation and synthesis

Expected learning • Basic knowledge about VHDL language and its usage (based on examples already seen in this course) • Be able to read and understand simple VHDL code • Be able to write specific portions of VHDL code • Understand the role of hardware languages in digital systems design 19

4 .2

Basics on VHDL lexical & syntax Lexical elements: Reserved Words, Identifiers, Symbols, Literals , , y , Language Reserved Words abs array bus exit if new open

access assert case file in next or

after attribute component for inout nor others

alias begin else function is not out

all block elsif generate label null process

and body end generic library of procedure

architecture buffer entity guarded nand on ...

Identifiers to provide specific names to VHDL elements and objects - Based on character set {‘a’…’z’, ’A’…’Z’, ’0’…’9’, ’_’} - First character shall be alphabetical and ‘_’ at the end or two ‘__’ are forbidden - Upper/lower-case are indifferent and reserved words are forbidden Examples: COUNT, aBc, X, f123, VHDL, VH_DL, ABC, q1, Q0

Symbols

Literales

- 1 or 2 characters Base - operators, punctuation, comments, part of sent. 2#110_1010# 16#CA# + - * / ( ) . , : & ‘ < > = 16#f.ff#e+2 | # ; -- => ** := /= >= <= <> “ Decimal 12 0 1E6

Character ‘a’ ‘A’ ‘@’ String “Tiempo” “110101”

Physical 10 ns 2.2 V 50 pF Bit String X”F0f” B”111_100”

4 .2

Basics on VHDL lexical & syntax VHDL Objects  j • •

constant constant constant constant t t

VHDL object is any language element able to contain a value Types of VHDL objects:  Constant  Variable Object definition: :
signal Clk : bit := ‘0’; ... Clk <= < ‘1’ ‘1’;

Signal declaration & initialization

type> [:= Initial value];

variable Counter : integer :=0; variable Increment : integer;

Variables declaration

Increment I t := 2; 2 Counter := Counter + Increment;

Variables V i bl assignment

Si Signal l assignment i t file Estimuli : FileTypeName1 open read_mode is “data.in”; file Dataout : FileTypeName2 open write_mode is “data.out”; 21

Basics on VHDL lexical & syntax

4 .2

VHDL Data Types  • The VHDL is a strongly typed language • A data type defines a set of fixed and static values • Any language object belongs to a specific data type • Object values shall belong to related data type STANDARD package: is (false, true); •boolean New data types could be user defined Predefined Types of VHDL

type type bit is (‘0’, ‘1’); type severity_level is (note, warning, error, failure); type character is (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DEL, DC1, DC2, DC3, DC4, DC5, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ‘ ‘, ‘!’, ‘”’, ‘#’, ‘$’, ‘%’, ‘&’, ‘’’, ‘(‘, ‘)’, ‘*’, ‘+’, ‘,’. ‘-’, ‘.’, ‘/’, ‘0’, 0 , ‘1’, , ‘2’, , ‘3’, 3 , ‘4’, , ‘5’, 5 , ‘6’, 6 , ‘7’, , ‘8’, 8 , ‘9’, 9 , ‘:’, : , ‘;’, ; , ‘<‘, , ‘=‘, ‘>’, ‘?’, ‘@’, ‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’, ‘G’, ‘H’, ‘I’, ‘J’, ‘K’, ‘L’, ‘M’, ‘N’, ‘O’, ‘P’, ‘Q’, ‘R’, ‘S’, ‘T’, ‘U’, ‘V’, ‘W’, ‘X’, ‘Y’, ‘Z’, ‘[‘, ‘\’, ‘]’, ‘^’, ‘_’, ‘`’, ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, ‘f’, ‘g’, ‘h’, ‘i’, ‘j’, ‘k’, ‘l’, ‘m’, ‘n’, ‘o’, ‘p’, ‘q’, ‘r’, ‘s’, ‘t’, ‘u’, ‘v’, ‘w’, ‘x’, ‘y’, ‘z’, ‘{‘, ...); type integer is range -2.147.483.647 to 2.147.483.647; type real is range -1.0e38 to 1.0e38; …/…

22

Basics on VHDL lexical & syntax

4 .2

VHDL Data Types  yp • • • • •

The VHDL is a strongly typed language A data type defines a set of fixed and static values Any language object belongs to a specific data type Any language object belongs to a specific data type Object values shall belong to related data type New data types could be user defined

type time is range 0 to 1e20 units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; h = 60 min; hr i end units time; 23

4 .2

Basics on VHDL lexical & syntax VHDL Operators and expressions  • • •

Operators are symbols identifying specific operations Types: arithmetic, logic, relational and concatenation Operands: • Expressions: Relational

Logic

Arithmetic

= /= < <= > >=

and or nand nor xor not

+ * / ** mod rem abs

Concatenation

&

Arithmetic (-b + sqrt(b**2 - 4.0*a*c))/(2.0*a)

Relational delay >= 20 ns name < “Smith”

Logic (a xor b) and not c;

Concatenation BitSign & VectorValue

•

Expressions could be assigned to:  p g  Constants (const := expression;)  Variables  (var := expression;) 24  Signals (sig <= expression;)

4 .2

VHDL Design Units VHDL is organized on different “Design Units”: • • • •

Entity Architecture Package (declaration & body) Configuration

Architecture 1

Architecture n

Package Declaration

Package g Body Secund dary

Architecture 2

Configuration D l Declaration i

Prim mary

Entity Declaration

25

4 .2

VHDL Design Units ENTITY • •

Like a “black‐box” just describing external interface for a module while  hiding its internal architecture Syntax: Entity name (module name)

entity is []; [<ports>]; p [<declarations>]; [begin <sentences>]; end [entity] [];

Generic parameters Input/Output ports (electrical interface) Global declarations (common to any potential architecture of this entity) Passive sentences (common to any potential architecture of this entity)

entity MUX21 is port( A : B : Ct l : Ctrl Z : end MUX21;

in in i in out

bit; bit; bit bit; bit;

A B Ctrl

MUX21

Z 26

4 .2

VHDL Design Units ENTITY • •

Like a “black‐box” just describing external interface for a module while  hiding its internal behaviour and architecture Syntax: Entity name (module name)

entity is []; [<ports>]; p [<declarations>]; [begin <sentences>]; end [entity] [];

Generic parameters Input/Output ports (electrical interface) Global declarations (common to any potential architecture of this entity) Passive sentences (common to any potential architecture of this entity)

entity MUX21n generic( n port( A B Ctrl Z end MUX21;

is : integer := 2); : in bit_vector(n-1 downto 0); : in bit_vector(n bit vector(n-1 1 downto 0); : in bit; : out bit_vector(n-1 downto 0));

Bus size as generic parameter

A B Ctrl

n n

MUX21

n

Z 27

4 .2

VHDL Design Units ARCHITECTURE • • •

Details what is behind an “Entity” while describing its behaviour at functional,  data‐flow, structural or mixed levels Multiple Architectures fo a single Entity are possible Syntax: Architecture name architectura of is [<declarations>]; begin ; end [architecture] [];

E tit name Entity Signals, variables, components … Concurrent sentences: • Concurrent assignments • Instances to components • Processes • Blocks

28

4 .2

VHDL Design Units: Entity & Architectures entity MUX21 is port( A, B, Ctrl : in bit; Z : out bit); end MUX21; architecture Functional of MUX21 is begin process(A, B, Ctrl) begin beg if Ctrl = ‘0’ then Z <= A; else Z <= B; end if; end process; end Functional;

A B Ctrl

MUX21 Z

entity MUX21n is generic ( n: natural); port( A : in bit_vector(n-1 downto 0); B : in bit_vector(n-1 downto 0); Ctrl : in bit; Z : out bit_vector(n-1 downto 0)); end MUX21; architecture Functional of MUX21n is begin process(A, B, Ctrl) begin if Ctrl = ‘0’ then Z <= A; ; else Z <= B; n end if; end process; A n end d Functional; F ti l B MUX21n

Ctrl

n

29

Z

VHDL Design Units : Entity & Architectures entity MUX21 is port( A : B : Ctrl : Z : end MUX21; ;

in i in in out

bit; i bit; bit; bit;

architecture DataFlow of MUX21 is signal Ctrl_n, N1, N2 : bit; b i begin Ctrl_n <= not Ctrl; N1 <= Ctrl_n and a; N2 <= Ctrl and b; Z <= (N1 or N2); end DataFlow; Concurrent Statements

4 .2 architecture structural of MUX21 is signal Ctrl_n, N1, N2 : bit; component INV port( Y : in bit; Z : out bit); end component; component AND2 port( p ( X, , Y : in bit; ; Z : out bit); end component; component OR2 port( X, Y : in bit; Z : out bit); end component; begin U0: INV port map (Ctrl, Ctr_n); U1: AND2 port map (Ctrl_n, A, N1); U2: AND2 port map (Ctrl, B, N2); U3: OR2 port map (N1, N2, Z); end structural; 30

4 .2

VHDL Design Units PACKAGE • •

Useful for code reuse as it could contain definitions of data types, functions and  language objects (constants, variables, signals or files) for its use on different codes Two units:  P k Package name  “Package declaration”  package [<declarations>]; end [package] []

Declarations of: • Data types • Constants • Functions & procedures Package name

 “Package body” g y

•

package body []; end [package body] []

Package usage g g use .<package name>.[ | all];

Assignments & definitions of: • Constants • Functions & procedures Usual packages: - STANDARD & TEXTIO - Std_logic_1164 31 - Std_logic_arith

4 .2

VHDL Design Units PACKAGE

VHDL constant object package VSuP_Pack is

Constant Id. Id

Constant data type

Comment

-- Processor basic dimensions constant ProcWordBits : integer; -- Processor word lenght (bits) constant MemAdrBits : integer; -- Memory address lenght (bits) constant CtrlBusNumBits : integer; -- Number of bits for control bus constant StatusBusNumBits : integer; -- Number of bits for status and flags bus constant ALUopNumBits : integer; -- Number of bits to especify the ALU operation code constant OpCodeNumBits p : integer; g -- Number of bits to especify p y the instruction OpCode p constant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 0’s constant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 1’s constant One : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant value ‘1’; -- Mnemonics for ALU operations constant NoOp,Add,Sub,IncL,IncR,DecL,DecR,AndL, OrL,NotL,LSh,RRot,GoL,GoR,Out0,Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0); -- Processor instruction set OpCodes constant t t LDA, S STA,MOV,SAV,CLR,SET,LAND,LNOT,LOR,SHIL,ROTR, O S C S O O S O ADD,SUB,INC,DEC,CMP,BRZ,BRN,JMP,NOP,EOP : std_ulogic_vector (OpCodeNumBits-1 downto 0); end package VSuP_Pack;

32

VHDL Design Units Constant values definition.

4 .2

package body VSuP_Pack is PACKAGE -- Processor basic dimensions constant ProcWordBits : integer := 16; -- Processor word lenght (bits) constant MemAdrBits : integer := 16; -- Memory address lenght (bits) constant CtrlBusNumBits : integer := 25; -- Number of bits for control bus constant StatusBusNumBits : integer := 5; -- Number of bits for status and flags bus constant ALUopNumBits : integer := 4; -- Number of bits to especify the ALU operation code constant OpCodeNumBits : integer := 5; -- Number of bits to especify the instruction OpCode constant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>‘0’); constant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>‘1’); g _vector ( (ProcWordBits-1 downto 0) ) := conv_std_logic g _vector ( (1, , constant One : std_ulogic ProcWordBits); -- Mnemonics for ALU operations -- No operation cycle constant NoOp : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0000"; -- Addition: Out <- A + B;[C B;[C,N,Z] N Z] constant Add : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0001"; -- Subtraction: Out <- A - B;[C,N,Z] constant Sub : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0010"; … / … -- Put all ll output bi bits at '1': 1 Out <- "1...1";[N] 1 1 [ ] constant Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0) := "1111"; end package body VSuP_Pack;

33

VHDL Summary (part-I)

4 .2

Session summary •

Basics on VHDL lexical and syntax  Language lexical elements  Objects (constant, variable, signal and files) Objects (constant variable signal and files)  Data types, Operators and expressions

•

VHDL design units  Entity and Architecture  Configuration  Package (declaration & body) Package (declaration & body)

•

Simplified formal VHDL design units descriptions but example based learning

34

4 .33 Short introduction to VHDL Lluís Terés Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC) Universitat Autònoma de Barcelona (UAB)

(cont.)

VHDL Sentences (selected subset)

4 .3

Sequential vs. Concurrent Sentences •

Sequential  Algorithmic sentences like for SW languages (if, case, loop, exit, return, …)  Interpreted sequentially  Order of sentences is important for the results  Only used in functions, procedures and Processes

•

Concurrent  Devoted to express hardware structure (Hw components and blocks are doing concurrently)  and processes working simultaneously  d ki i l l  Some sequential sentences have its equivalent concurrent ones  Selected sentences: Process, Signal assignments, Components instantiation  Mainly used in Architectures Mainly used in Architectures

•

Concurrent to Sequential for simulation  Each concurrent statement could be translated to its equivalent Process based on sequential  statements.  For simulation purposes all the concurrent statements are translated to related processes.  VHDL event driven simulation will manage just a lot of processes.

36

VHDL Sentences (small selection)

4 .3

Sequential Sentences •

Where are possible? process begin -- sequential -- sentences end process;

•

procedure P() is begin -- sequential -- sentences end P;

function F() return begin -- sequential -- sentences end F;

Which are the selected sentences? • • • • • • •

Variable & Signal assignments Wait If … then … else … endif Case Loop, Exit and Next Functions & Procedures Functions & Procedures Assert…report…severity 37

VHDL Sentences (small selection)

4 .3

Sequential Sentences: Variable Assignment • •

Immediate replacement of variable value. Syntax: [label:] := <expression>;

•

Examples: Var := ‘0’; Vector := “00011100”; string := “Message is: ”; A := B; B := my_function(3,databus) C := my_function(4,adrbus) my function(4 adrbus) + A;

38

4 .3

VHDL Sentences (small selection) Sequential Sentences: Signal Assignment • •

Projects a new event (value, time) on the signal driver. Syntax:

t

t0

t1

…

ti

v

v0

v1

…

vi

[label:] <signal_name> <= [delay_type] <expression> {after <delay>};

•

• •

Next sentence sequences will exchange the values  between signal “A” and “B”: Delay types: “inertial” or “ transport” Examples: p

A <= B; B <= A;

B <= A; A <= B;

=

B1 B2 B3

B1 <= transport A after 10 ns; B2 <= A after 10 ns; B3 <= reject 5 ns A after 10 ns;

A 0

10

20

30

40

A <= ‘0’, ‘1’ after 10 ns, ‘0’ after 15 ns, ‘1’ after 20 ns, A  ‘0’ after 28 ns, ‘1’ after 40 ns, ‘0’ after 50 ns; driver

50

60

70

((ns))

t

0

10

15

20

28

40

50

v

0

1

0

1

0

1

0

VHDL Sentences (small selection) Sequential Sentences: Wait • •

•

4 .3

Indicates the point where a process execution shall be suspended, as well as the  Indicates the point where a process execution shall be suspended as well as the conditions for its reactivation. More than one “wait” sentence per process is possible. Syntax: [label:] wait [on <signal> {, ...}] [until ] [for ];

B i Basic examples: l process begin <sequential sentences> wait; end process;

Without reactivation condition

process begin c <= a and b; wait on a, b; end process;

Sensible to events on signals “a” “b”

process begin Clock <= not Clock; wait for 10 ns; end process;

Suspends and fixes a time for reactivation 10ns Suspends and fixes a time for reactivation 10ns process begin q <= d; wait until Clock = ‘1’; end process; 40

Sensible to events on signals & condition=True

4 .3

VHDL Sentences (small selection) Sequential Sentences: If … then … else … endif; • •

Selects the group of sentences to execute depending on a Boolean condition. Syntax: [label:] if then <sentencias secuenciales> {elsif then <sentencias secuenciales} [else <sentencias secuenciales>] end if [ [label]; ]

•

Examples: Latch: process begin if load =‘1’ then Q <= D; end if; wait on load, D; end process;

Latch

Process (A, (A B B, Ctrl) Begin if Ctrl = ‘0’ then Q <= A; else Q <= B; end if; end process;

Mux

Buffer Triestate process begin if Enable =‘1’ then S lid <= Entrada; Salida d else Salida <= ‘Z’; end if; wait on Enable, Entrada; end process; 41

VHDL Sentences (small selection)

4 .3

Sequential Sentences: Case • •

Selects the group of sentences to execute  depending on a expression value. Syntax:  Or of values: when “00” | “01”  Values range: when 5 to 12 (integers)  Last option: when others

•

[label:] case is {when => <sequential sentences>;} [when others => <sequential sentences>;] end case [label];

type weekdays t kd : (Monday, (M d T Tuesday, d W d Wednesday, d Th Thursday, d F id Friday, S t d Saturday, S d ) Sunday); type typeofday : (Workingday, Holiday); Signal Day : Weekdays; process process Signal Daytype : typeofday; begin begin case ValEnt V lE t is i case Day D i is when 0 => Res := 5; when Monday to Friday => when 1 | 2 | 8 => Res := ValEnt; Daytype <= Workingday; when 3 to 7 => Res := ValEnt + 5; when Saturday | Saunday => when others => Res := 0; Daytype <= Holiday; end case; end case; wait on ValEnt; wait on Day; end process; end process; 42

Examples:

VHDL Sentences (small selection) Sequential Sentences: If & Case •

Previous example with two “Process”:  Mux  Latch

LatMux A B

X

Y

C D

4 .3

entity LatMux is port( Load : in bit; A B A, B, C C, D : in bit; Ctrl : in bit_vector(0 to 1); Y : out bit); end LatMux; architecture TwoProc of LatMux is Signal X : bit; Concurrent Statements begin Mux: process (Ctrl, A, B, C, D); begin case Ctrl is when “00” => X <= A; when “01” => X <= B; when “10” => X <= C; when “11” => X <= D; end case; ; end process;

Sequential Statements

Ctrl Load

Latch: process (Load, X); begin if Load=‘0’ then Y <= X; end if; end process; end TwoProc;

43

VHDL Sentences (small selection)

4 .3

Sequential Sentences: Loop • • •

Sequential sentences in the loop region are repeated for a number of times. Types of loops: “while”, “for” and “without iterations control (infinite loop)”. Syntax: [[label:] abe :] [ [while e d t o | for o ] t o ]

loop <sequential sentences>} end loop [label]; achitecture Functional of ParallelAdder is begin process (X, Y, Cin); • Examples: “Full‐adder” variable C : std_logic_vector(n downto 0); variable tmp : std_logic; variable I : integer; entity ParallelAdder is begin g generic (n : natural :=4 ); C(0) := Cin; port ( X, Y : in for I in 0 to n-1 loop std_logic_vector(n-1 downto 0); tmp := X(I) xor Y(I); Cin : in std_logic; Z(I) <= tmp xor C(I); Z : out std_logic_vector(n-1 downto 0); C(I+1) := (tmp and C(I)) or (X(I) and Y(I)); Cout : out std_logic); end loop; End ParallelAdder ; Cout <= C(n); end process; 44 end Functional;

VHDL Sentences (small selection)

4 .3

Sequential Sentences: Exit (inside a loop) • •

Ends the loop execution when “boolean_condition” is “true” and goes to next sentence  after the loop. Syntax: [label:] exit [loop_label] [when ];

Needed N d d for f neested t d loops l t id tif which to identify hi h is i the th loop to be “exited” or “nexted” 

Sequential Sentences: Next (inside a loop) • •

Stops current loop iteration when “boolean_condition” is “true” and goes for the next iteration  St tl it ti h “b l diti ” i “t ” d f th t it ti (skips current iteration after this sentence). Syntax: [label:] next [loop_label] [when ];

45

VHDL Sentences (small selection)

4 .3

Sequential Sentences: Functions (same as software languages) • •

A piece of code devoted to specific computation of input parameters to return a value. Syntax for function declaration:  function [(<parameters list>)] return ;

•

Syntax for function definition:  function [(<parameters list>)] return is {<declarative part>} begin {<sequential sentences>} [label:] return [expresion]; end [function] [];

•

Example: p function bv2int (bs: bit_vector(7 downto 0)) return integer;

Var : := base + bv2int(adrBus(15 downto 8));

Function usage Sig <= base + bv2int(adrBus(7 downto 0)); or reference

46

VHDL Sentences (small selection)

4 .3

Sequential Sentences: Procedures (same as software languages) • •

A piece of code devoted to specific computation of input parameters to return a value. Syntax for procedure declaration:  procedure [(<parameters list>)];

•

Syntax for procedure definition:  procedure [(<parameters list>)] is {<declarative part>} begin {<sequential sentences>} end [function] [];

•

Example: p procedure bv2int (bs: bit_vector(7 downto 0); x: out integer );

Procedure usage or reference

bv2int(adrBus(15 downto 8); Var); Var := base + Var; 47

4 .3

VHDL Sentences (small selection) Sequential Sentences: Assert • •

A kind of validation sentence:  when  is FALSE the <string of characters>  is printed out and actions related to specified severity level are done. [label:] assert p Syntax:  y [report <string of characters>] [severity (note | warning | error |failure);

•

Examples: p assert not(addr < X"00001000" or addr > X"0000FFFF“) report “Address in range" severity note; assert (J /= C) report "J = C" severity note;

Sequential Sentences: Report •

Syntax: 

•

Example: 

[label:] [report < string of characters >] [severity (note | warning | error |failure);

report “Check point 13”;

=

assert FALSE “Check point 13” severity note;

4 .3

VHDL Summary (part-II) Session summary •

Sequential vs. Concurrent worlds in VHDL 

•

VHDL sequential sentences (inside a process, function or procedure)  Selected sentences: Selected sentences: • •

Variable & signal assignments Wait

• •

If … then … else … endif Case

• •

Loop, Exit and Next Assert, Functions & Procedures

 Examples based VHDL learning

49

50

4 .44 Short introduction to VHDL Lluís Terés Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC) Universitat Autònoma de Barcelona (UAB)

(cont.)

4 .4

Previous comment General structure of a VHDL model entity X is begin … end X;

architecture Y of X is … begin …

only concurrent sentences

… S<=A when Sel=‘0’ else B; Clock <= not clock after 20 ns; … P1: process (clock, S); begin …

only sequential sentences end process;

end Y;

P2: p process …

52

CONTENTS 1. 1 2. 3. 4 4. 5. 6. 7 7.

4 .4

Main goals & Expected learning M i l &E t dl i Basics on VHDL lexical & syntax VHDL Design Units VHDL Sequential Sentences (selection) VHDL Sequential Sentences (selection) VHDL Concurrent Sentences (selection) VHDL usage for modelling, simulation and synthesis  Summary

53

4 .4

VHDL Sentences (small selection) Concurrent Sentences •

All the concurrent sentences are being evaluated simultaneously

•

Where are possible? • • •

•

Entity (passive sentences) Block (collects concurrent sentences) Architecture

Which are the selected sentences? • •

Process Signal assignments Signal assignments • • •

• •

•

Direct Assignment Conditional Assignment Selected Assignment

entity X is begin

Concurrent sentences

end X;

architecture Y of X is begin

B : block begin

end block; end Y;

Components Generate

Each concurrent sentence will be translated to its equivalent process before its simulation

54

4 .4

VHDL Sentences (small selection) Concurrent Sentences: Process • • • • •

Contains sequential sentences to define its own behaviour  Communicates with other processes and concurrent sentences by means of signals The process is an infinite execution loop able to contain “stop/wait” conditions (at least ONE!!) Each process is sensible to events on specific signals or conditions to launch again its execution  Syntax: [