Sa
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MODELLING TYPES
TYPES OF MODELLING • DATA FLOW MODELLING • STRUCTURAL MODELLING • BEHAVIORAL MODELLING
• SIGNAL ASSIGNMENTS * CONCURRENT SIGNAL ASSIGNMENT * SEQUENTIAL SIGNAL ASS. * CONDITIONAL SIGNAL ASS. * SELECTED SIGNAL ASS.
CONCURRENT SIGNAL ASSIGNMENT library ieee; use ieee.std_logic_1164.all; entity testcsa is port(b : in std_logic; z : out std_logic); end testcsa; architecture test of testcsa is signal a : std_logic; begin a<= b; z<= a; end test;
CONCURRENT SIGNAL ASSIGNMENT…
SEQUENTIAL SIGNAL ASSIGNMENT entity testssa is port(a : in std_logic; b,c,d:inout std_logic; z : out std_logic); end testssa; architecture test of testssa is --signal b,c,d:std_logic; begin process(a) begin b<= a; c<= b; d<=c; z<=d; end process; end test;
ASSIGNMENT…
CONDITIONAL SIGNAL ASSIGNMENT library ieee; use ieee.std_logic_1164.all; entity cond is port( in0,in1,in2,in3,s0,s1 : in std_logic; z : out std_logic); end cond; architecture delay of cond is begin z<= in0 after 10 ns when s0 = '0' and s1 = '0' else in1 after 10 ns when s0 = '0' and s1 = '1' else in2 after 10 ns when s0 = '1' and s1 = '0' else
CONDITIONAL SIGNAL ASSIGNMENT
TYPES OF MODELLING • DATA FLOW MODELLING • STRUCTURAL MODELLING • BEHAVIORAL MODELLING
• SIGNAL ASSIGNMENTS * CONCURRENT SIGNAL ASSIGNMENT * SEQUENTIAL SIGNAL ASS. * CONDITIONAL SIGNAL ASS. * SELECTED SIGNAL ASS.
CONCURRENT SIGNAL ASSIGNMENT library ieee; use ieee.std_logic_1164.all; entity testcsa is port(b : in std_logic; z : out std_logic); end testcsa; architecture test of testcsa is signal a : std_logic; begin a<= b; z<= a; end test;
CONCURRENT SIGNAL ASSIGNMENT…
SEQUENTIAL SIGNAL ASSIGNMENT entity testssa is port(a : in std_logic; b,c,d:inout std_logic; z : out std_logic); end testssa; architecture test of testssa is --signal b,c,d:std_logic; begin process(a) begin b<= a; c<= b; d<=c; z<=d; end process; end test;
ASSIGNMENT…
CONDITIONAL SIGNAL ASSIGNMENT library ieee; use ieee.std_logic_1164.all; entity cond is port( in0,in1,in2,in3,s0,s1 : in std_logic; z : out std_logic); end cond; architecture delay of cond is begin z<= in0 after 10 ns when s0 = '0' and s1 = '0' else in1 after 10 ns when s0 = '0' and s1 = '1' else in2 after 10 ns when s0 = '1' and s1 = '0' else
CONDITIONAL SIGNAL ASSIGNMENT
