Rr321202-vlsi-systems-design

Set No. 1

Code No: RR321202

III B.Tech Supplimentary Examinations, Aug/Sep 2008 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following gates with p-MOS transistors only and explain its working (a) 2 Input NAND gate. (b) 3 Input NOR gate.

[8+8]

2. With neat sketches explain the drain characteristics of n-MOS transistor and mark different operating regions of this device. [16] 3. Design a stick diagram for CMOS logic shown below. Y = (A + B + C + D)1 4. Design a layout for CMOS inverter.

[16] [16]

5. (a) Explain the power calculation procedure of CMOS inverter. (b) Explain the speed - power product significance of a logic family. 6. Draw the structure of carry select adder and explain its working principle.

[8+8] [16]

7. Explain how Architecture driven voltage scaling technique reduces the power consumption of the design. [16] 8. Explain about different types in the register file based data-path. ⋆⋆⋆⋆⋆

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[16]

Set No. 2

Code No: RR321202

III B.Tech Supplimentary Examinations, Aug/Sep 2008 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following logic functions using CMOS logic (a) Y = {AB + (C + D)}1 (b) Y = {A(B + C) + D}1

[8+8]

2. Explain working principal of P-MOS transistor with sketches of its structure. [16] 3. Explain with neat sketches CMOS fabrication using n - well process.

[16]

4. Compute the high-to-low delay of a two-input static complementary NOR gate with minimum-sized transistor driving these loads. (a) An inverter with minimum-sized pull up and pull down. (b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ. [8+8] 5. Explain with suitable example the details of single - Row layout design method. [16] 6. Draw the structure of carry select adder and explain its working principle.

[16]

7. Explain clearly the global routing phase of the floor planning of the chip with few examples by considering all constraints. [16] 8. Write a register-transfer description of one four-digit timer. ⋆⋆⋆⋆⋆

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[16]

Set No. 3

Code No: RR321202

III B.Tech Supplimentary Examinations, Aug/Sep 2008 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following gates with CMOS Logic and explain its working (a) 2 Input OR gate. (b) 4 Input NAND gate.

[8+8]

2. Explain working principal of n-MOS transistor with sketches of its structure. [16] 3. Explain with neat sketches CMOS fabrication using P - well process.

[16]

4. Design a layout for CMOS 2-input NOR gate.

[16]

5. Explain with suitable example how to design the layout of a gate to maximize performance and minimize area. [16] 6. Draw the basic structure of serial-Parallel multiplier and explain its working principle. [16] 7. Explain how power - down modes reduces the power consumption of the design. [16] 8. Explain about switch - level simulation and give rules for evaluating switch - level simulation. [16] ⋆⋆⋆⋆⋆

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Set No. 4

Code No: RR321202

III B.Tech Supplimentary Examinations, Aug/Sep 2008 VLSI SYSTEMS DESIGN (Information Technology) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Implement the following gates with p-MOS transistors only and explain its working (a) 2 Input AND gate. (b) 4 Input NOR gate.

[8+8]

2. An p-MOS transistor is operating in the triode region with the following parameters µn Cox = 95 µ A/V 2 W/L ( ratio) = 90 V gs = −4V, Vtn = −1.1V, Vds = −2V . Find its drain current & drain -Source resistance. [16] 3. Explain about different spice - parameters of MOS transistor and their significance. [16] 4. Implement 3-input NOR gate and 2 input AND gates using static complementary logic. [16] 5. Explain clearly the Job of the four types of simulators that are most commonly used for combinational logic design. [16] 6. Draw the circuit diagram of resistive load SRAM cell and explain its working principle. [16] 7. Explain clearly the detailed routing phase of the floor planning of the chip with few examples by considering all constraints. [16] 8. Draw the ASM chart for the kitchen timer controller. ⋆⋆⋆⋆⋆

1 of 1

[16]