Publication 3

Digital Circuit Design for Reception of 155.52 Mbps, LVPECL Data for Optical Inter-Satellite Link Kaushik Nagaraj, Abhishek S. M., Adawaita Goswami, A. S. Laxmi Prasad

Indian Space Research Organization (ISRO) Laboratory for Electro-Optics Systems (LEOS) Bangalore, India. Abstract. Optical Inter-satellite links can be established between two Geo-stationary (GEO) satellites, between a Low Earth Orbiting (LEO) satellite and a GEO, or between a deep space probe and a GEO or LEO. The use of optical signals as information carriers in satellite communication system becomes attractive because of their ability to provide very high-speed communications with data rates in the order of Gbps (Giga bit per second) without any mutual interference. Data generated on the LEO satellite needs to be converted to high data rates in order for it to be compatible with the optical devices being used for communication. At the receiver end, the data from the optical devices is produced at the high speed at which it was fed at the transmitter end. This paper gives the circuit design issues related to the conversion of the data being received at the receiver, such that it is fit to be displayed on the computer screen. The data received is at a rate of 2.48 Gbps. This is De-Multiplexed using an 8 channel DeMultiplexer to generate 155.52 Mbps data rate on each of the output channels which is converted to TTL and then fed into the computer through the PCI Bus.

1 Introduction Applications of Low Earth Orbit (LEO) and geostationary earth orbit (GEO) satellites are increasing day by day. Over the last decade number of transponders in GEO satellites and number of instruments and their resolution in (LEO) satellites has increased resulting in enormous increase in data generation in such applications. The huge volumes of data need to be transmitted in short time and in some applications immediate transmission is required for instant monitoring. However, the visibility of LEO satellite to ground is limited. Inter Satellite communication between a remote sensing satellite in the LEO and a communication satellite in the GEO can be used to overcome this problem. The data from the LEO satellite can be transferred to the GEO satellite which is constantly visible to the ground. Subsequently, the GEO satellite relays the data to ground station. This inter satellite link can be RF or optical. In optical inter satellite link (OISL) [2, 3, 4, 5] data is transmitted using modulated optical signal with starting and ending information bursts. The advantages of an inter satellite optical communication system as compared to RF link in free space are: 1) Smaller size and weight of the overall system 2) Reduced transmitter power 3) Increased bandwidth 4) Secure communication (narrow beam with low probability of intercept and negligible interlink interference) 5) Jam resistance (small receive FOV) 6) Provides base forever expanding space activities. Optical Inter Satellite links can be established between two Geo-stationary (GEO) satellites, between a Low Earth Orbiting (LEO) satellite and a GEO, or between a deep space probe and a GEO or LEO. Link establishment, link maintenance, and data transfer are the three critical basic functions of any optical inter-satellite communication system. Link establishment and maintenance is critical task because of the low laser beam divergence, the large distance and the vibration of the satellites caused by satellite internal subsystems (such as thruster firing and solar array drive mechanism). LEOS has developed a laboratory concept model operating at 1.25Gbps data rate and efforts are in progress towards the development of space born Optical Inter-satellite communication system. The block diagram of the Optical Inter-Satellite System is shown in Figure 1. The data source is assumed to be a computer and this data needs to be transmitted from the Transmitter end to the Receiver end as shown in the diagram. The data from the computer is converted to a data rate of 155.52 Mbps which is fed as the input at one of the channels

of the 16-channel multiplexer. The output data rate of the multiplexer is 155.52*16=2.48Gbps. This data rate is sufficient to be given as the input to the Laser Drivers which bring about the conversion of the digital data to the laser pulses. These are than transmitted at the transmitter end into free space with the help of a Transmitter Antenna. The Receiver Antenna receives this data and converts it to the digital data with the help of a detector. The data rate is 2.48 Gbps which is given as the input to the De-Multiplexer which outputs the data at each of its 16 output channels at a data rate of 155.52 Mbps. This data needs to be read by the computer at the receiver end and displayed in the machine readable form.

A c q u is itio n , P o in tin g & T ra c k in g

T r a n s m itte r

L a s e r D riv e r

L aser D io d

O p tic s

M u ltip le x e r

L im itin g A m p lifie r

D e te c to r (A P D )

O p tic s

D e m u ltip le x e r

R e c e iv e r

A c q u is itio n , P o in tin g & T ra c k in g

Fig. 1. Block Diagram of the OISL System

This paper discusses a method to bring about the data rate conversion from the rate at which the data is received to a lower data rate such that it is readable by the computer. Also, the received data is LVPECL [1]. This needs to be converted to TTL since the data is fed into the computer through the PCI Bus and the PCI Bus does not support ECL Data. The received data is serial data that is obtained at the rate of 2.48Gbps [1]. This is passed through an DeMultiplexer, thereby, bringing about a data rate conversion to 155.52 Mbps at the output of each of the channels of the De-Multiplexer. Also, the data needs to be converted from LVPECL to TTL. This scheme is explained in figure 2. The 155.52 Mbps, LVPECL Data from the De-Multiplexer is given to a Parallel-In-Serial-Out Shift Register. The clock

input to this shift register is 155.52 MHz which is tapped from the on-board oscillator in the De-Multiplexer. The input to the PISO is serial and the output is parallel. Each output of the PISO is 19.44 Mbps, ECL. This is given in parallel to an 8-channel ECL-to-TTL Translator which brings about the conversion from ECL to TTL. The output of the Translator is given to 8 parallel channels of the DIO card which is driven by a clock of 19.44 MHz. This clock is obtained from the counter that divides the tapped clock by 8. The output of DIO is in parallel and is given to the computer through 8-channels of the PCI Bus. An ECL-to-TTL Translator is required to convert the 19.44MHz clock generated by the 4-bit counter to TTL since The clock is in ECL and the DIO supports only TTL.

19.44 MBPS 8 – CHANNEL PARALLEL DATA

155.52 MBPS LVPECL DATA

DE-

PISO SHIFT

MULTIPLEXER

REGISTER

19.44 MBPS 8-BIT PARALLEL TTL DATA

ECL-TO-TTL TRANSLATOR 19.44 MHz

155.52 MHZ CLOCK INPUT

4 - BIT COUNTER

DIO CARD 19.44 MHz

ECL-TO-TTL TRANSLATOR

Fig. 2. Block Diagram of Circuit

2 HARDWARE DESCRIPTION The De-Multiplexer card has an on-board clock source which is 155.52 MHz crystal, which is being tapped to give as the clock input to each of the block mentioned above. Some of the blocks require a clock input of 155.52/8=19.44 Mbps which can be brought about with the help of the 4 bit counter.

2.1 CIRCUIT Receiver section is used to convert the data received from the de-multiplexer to computer compatible data. The main steps involved in converting to computer compatible data are as follows 1. Converting LVPECL logic to TTL logic. 2. Converting serial data into packets of 1 byte data. 3. Received data will be in 155.52Mbps. It has to be converted to 19.44MBps. This circuit contains 1. Serial in and parallel out register. 2. An ECL to TTL translator. 3. A counter used as clock divider. Serial in parallel out register - This IC is ECL compatible. It is driven by a clock of 155.52MHz tapped from the De-Multiplexer. The register is configured in shift left operation. For every clock pulse data from De-Multiplexer is shifted 1 bit to left of output of this register. After 8 clock pulse it is configured such that translator reads data at output of this register. Translator has a time span of 1 clock cycle to read the data from this register. This is done by proper synchronization of signals generated. Input of this register should be ECL logic. LVPECL to ECL conversion is brought about by register pull up and pull down network.

PC

Fig. 3. Circuit diagram. Input from De-Multiplexer is fed from the right and output read to DIO at the left. ECL to TTL translator - This IC converts the ECL input to TTL output at the same rate as its input. This IC cannot work at high speeds as other ICs because its input or output will be TTL logic. TTL logic circuits can only work at a maximum of 20MHz. Here this IC is worked at 19.44MHz. This IC translates 8 bit ECL data to 8 bit TTL data simultaneously. Clock given to this IC is the output of counter which is a divide-by-8 clock (Note: All the divideby-x is with respect to 155.52 MHz). Output of this IC is latched, i.e., until the next clock pulse, the output data does not change. The output of the counter is used as clock input to the DIO card and the translator. The counter is also used to set-reset the select lines required for Parallel load and serial shift in the shift register.

Fig.4. Four bit counter with outputs C0, C1, C2,and C3. Counter - Counter is a 4 bit ECL counter. The output of the counter is C0, C1, C2, and C3. C3 is left unused since the tapped clock needs to be divided by 8 and not by 16. It is driven by clock of 155.52MHz tapped from DeMultiplexer. It is configured in count down mode by giving suitable signals to select lines. This IC output are used to

generate different control signals and also used as clock divider. Divide-by-8 clock is given to the translator and also to the DIO card. The 19.44MHz clock generated by the counter is in ECL Logic level. Since this clock is to be given to DIO card which deals with only TTL data, it is necessary to convert the clock to TTL. This is brought about by using only 1 bit of a 6-bit ECL-to-TTL.

Fig. 5. Circuit to generate the Handshake signal to DIO The circuit given in Figure 3 shows the Translator and the PISO Shift Register. A four bit counter is shown in figure 4 which has outputs C0, C1, C2, and C3. Out of this C3 is left unused. Figure 4 shows the cicuit diagram for generation of handshake signals to the DIO card. Flow of the Circuit - The data from the De-Multiplexer is given to a Parallel-In-Serial-Out Shift Register which has a serial input and a parallel output. The input is at the rate of 155.52 Mbps and the output at each of the 8 channels is at the rate of 19.44 Mbps. These 8 channels of data are fed to an 8 bit ECL-to-TTL Translator. The output of this is read through the 8 input ports of the DIO Card with the help of the control signals to ensure timely reading of data. The DIO outputs the data into the computer through the PCI Bus at the rate of 19.44 Mbps. This rate is supported by the PCI Bus and hence is suitable to be read by the computer. Since the clock is tapped from an external source, there is very high possibility of distortion in the clock pulses obtained on the circuit. Therefore, a pulse shaper which is a fanout buffer is also provided. All the inputs pertaining to change in states are terminated using resistors network for proper swing of levels. Voltage inputs are given to ICs with decoupling capacitors to avoid reflections due to high speed operation.

2.2 TIMING DIAGRAM The Timing Diagram for the above circuit is shown in Figure 6. Clk and clkb are the main signals which are stable that is tapped from De-Multiplexer, which is used to generate many other signals and also to drive all ICs directly or indirectly. Clk and clkb are not enough to generate all signals required to drive all ICs, hence a 4 bit counter is used to generate divide by 2, 4, 8 and 16 clocks. These supplement signals along with clk and clkb are used to generate select lines and signals for other ICs like translator and shift register. In timing diagram construction is done by taking into account of all maximum and minimum propagation delay of all ICs. Allowances are provided in timing diagram for varying propagation delay. Shift register is used to convert serial data to parallel 8 bit data. Shift register is driven by clkb. Data is shifted left after every clkb pulse. Parallel data is read by translator after 8 pulses. Data is translated to TTL logic by translator after 8 pulses and this is synchronized by generating a suitable select line. This is given by C2 output of counter. C2 output of counter is given as handshake signal to DIO card so as to enable DIO card to receive the data from the interface card. This is given through a translator. Setup and hold time of minimum 20 n sec is required along with 50 n sec of handshake signal.

Fig.6. Timing Diagram of the circuit

3 SOFTWARE INVOLVED[1] The DIO card is software programmable and needs to be programmed to control the data input/output. The ports on the DIO can be configured as all input ports or all output ports or some as input ports and some as output ports. There will be specific registers for this purpose. It is necessary to program 8 ports as input and 8 ports as output. Also, there is a need to generate the necessary control signals and the handshake signals so that the output is at the data rate of 19.44 Mbps. The data needs to be read into the DIO when data is ready, given, the previous data has been sent out through the output ports. Another possibility is the occurrence of the overflow of the buffer in the DIO resulting in the reading of wrong data at the output ports. When the input data rate is less than the output data rate, there is a possibility of buffer underflow. So, to prevent this, handshake signals must be generated between the DIO card and the circuit. DIO has many modes of operation. The modes selected should be operable at 19.44 MHz. Data from the computer can be of many format types. All these formats have certain headers that contain information pertaining to the data it contains. The information from these headers must be extracted and used for retrieval of data at the receiver end. This is once again done by software.

4 CONCLUSION A digital circuit has been designed to bring about an interface between the computer and the laser detectors at the Receiver end for Optical Inter-Satellite Link. The various high speed circuit design issues have been highlighted and ways to counter some of these problems have also been briefly discussed. The development activity at LEOS has also been briefly discussed.

REFERENCES [1] Kaushik Nagaraj, Abhishek S.M., Adwaita Goswami, A.S. Laxmi Prasad, “Digital Circuit Design for Generation of 155.52 Mbps, LVPECL data for Optical InterSatellite Link”. [2] R.B Deadrick and W.F Deckelman, “Laser Cross Link Subsystem- A Overview”, SPIE Vol.1635,225-235 (1992). [3] Christoph Noldeke, “Survey of Optical Communication System Technology for Free-Space Transmission”, SPIE Vol.1635, 200-212 (1992)

[4] J. E. Mulholland and S. A. Cadogan, “Intersatellite laser crosslink,” IEEE Trans. Aerospace and Electron. Sys., vol. 32, no. 3, pp. 1011 – 1020, Jul.1996. [5] W.R. Leeb, “Prospects of laser communications in space,” in Selected Papers on Free-Space Laser Communications II, D.L. Begley, Ed.,vol. MS100 of SPIE Milestone series, pp. 64–74. SPIE, May 1984. [6] Ryan J. Pirkl, “ECL Design Guide”, Propagation Group, Georgia Institute of Technology, May 18, 2005. [7] Paul Shockman, “Termination of ECL Devices with EF (Emitter Follower)Output Structure, ON Semiconductor Logic Applications Engineering. [8] Ranjith.R, Adwaita Goswami, P.Raghu Babu and A.S.Laxmiprasad, “Technology and Design needs for Optical Inter-Satellite Link (OISL)”. [9] Laxmiprasad A.S., R.Ranjith, P.Raghubabu, J.A.Kamalakar, “Optical Inter-Satellite Link (OISL) for Remote Sensing Satellites” in SPIE Proceedings on Asia Pacific Remote Sensing, Panaji, Goa, India, November – 2006.