CHAPTER 1 INTRODUCTION 1.1Introduction Filters are essential to the operation of most electronic circuit .In circuit theory; a filter is an electrical network that alters the amplitude and/or phase characteristics of a signal with respect to frequency. Ideally, a filter will not add new frequencies to the input signal, nor will it change the component frequencies of that signal, but it will change the relative amplitudes of the various frequency components and/or their phase relationships. A filter can exist either in an analog or digital form, however DIGITAL FILTERING is important in almost all aspects of modern day applications. Digital filtering is one of the most powerful tools of DSP and FPGA. Apart from the obvious advantages of virtually eliminating errors in the filter associated with passive component fluctuations over time and temperature, op-amp drift (active filters), etc., digital filters are capable of performance specifications that would, at best, be extremely difficult, if not impossible, to achieve with an analog implementation. In addition, the characteristics of a digital filter can be easily changed under software control. Therefore, they are widely used in adaptive filtering applications in communications such as echo cancellation in modems, noise cancellation, and speech recognition. The actual procedure for designing digital filters has the same fundamental elements as that for analog filters. First, the desired filter responses are characterized, and the filter parameters are then calculated. Characteristics such as amplitude and phase response are derived in the same way. The key difference between analog and digital filters is that instead of calculating resistor, capacitor, and inductor values for an analog filter, coefficient values are calculated for a digital filter. So for the digital filter, numbers replace the physical resistor and capacitor components of the analog filter. These numbers reside in a memory as filter coefficients and are used with the sampled data values from the ADC to perform the filter calculations. Also due to the flexibility in the design that these digital filters offer they can be readily implemented on DSP processor chips and 1
FPGA’s to serve the application. It is therefore in the interest of anyone involved in the electronic circuit design to have the ability to develop filter circuits capable of a given set of specifications. Unfortunately many in the electronics field are uncomfortable with the subject, whether due to a lack of familiarity with it, or a reluctance to grapple with the mathematics involved in a complex filter design. The present project deals with the software approach of designing a digital filter where the code representing the filter operation is implemented on the VIRTEX-4 FPGA using a high-level language like ‘C’ in a different environment called as the EDK (embedded development kit) to represent the filter operation and then implementing that code on the XTREME DSP DEVELOPMENT PLATFORM KIT IV using a VHDL code written in a different environment known as ISE (integrated software environment).
1.2Aim of project The aim of project is to Design and Implement an FIR Band Pass Filter in VIRTEX4 FPGA. The filter operates in the pass band of 40MHz to 50MHz.
1.3Methodology Digital filters process digitized or sampled signals. A digital filter computes a quantized time-domain representation of the convolution of the sampled input time function and a representation of the weighting function of the filter. They are realized by an extended sequence of multiplications and additions carried out at a uniformly spaced sample interval. Simply said, the digitized input signal is mathematically influenced by the VHDL program. These signals are passed through structures that shift the clocked data into summers, adders, delay blocks and multipliers. These structures change the mathematical values in a predetermined way; the resulting data represents the filtered or transformed signal. It is important to note that distortion and noise can be introduced into digital filters simply by the conversion of analog signals into digital data, also by the digital filtering process itself by conversion of processed data back into analog. When fixedpoint processing is used, additional noise and distortion maybe added during the filtering 2
process because the filter consists of large numbers of multiplications and additions, which produce errors, creating truncation noise. Increasing the bit resolution beyond 16bits will reduce this filter noise. For most applications, as long as the A/D and D/A converters have high enough bit resolution, distortions introduced by the conversations are less of a problem. Theoretically, note that the ratio of the RMS value of a full-scale sine wave, to the RMS value of the quantization noise (expressed in dB) is SNR= 6.02N+1.76dB,where N is the number of bits in the ideal A/D converter. A digital hardware filter can be constructed from logic elements such as registers and gates, or an integrated hardware block such as an FPGA (Field Programmable Gate Array), although they have limited design flexibility and higher cost, they are desirable for high bandwidth applications. Especially due to the advantages of FPGA such as its instantaneous output and because it is widely used for real time applications we are going for FPGA to design a band pass filter and the Virtex series of FPGA has in addition to the normal FPGA logic fabric embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores. The number of multipliers ranges from a few tens to several hundreds, depending on the device and since we require logic cells in the range of 23,000 to 55,000 we choose Virtex4 FPGA.
1.4Significance of Work The importance of digital filters is well established. Digital filters, and more generally digital signal processing algorithms, are classified as discrete-time systems. They are commonly implemented on a general-purpose computer or on a dedicated digital signal-processing (DSP) chip. But there are certain drawbacks of DSP’s such as Processing through DSP chips is not instantaneous. DSP chips are not widely used for real time applications. To overcome these drawbacks, using FPGA’s, we opt for designing a Band Pass filter in VIRTEX4 FPGA. Due to their well-known advantages, digital filters are often replacing classical analog filters. 3
Digital filters are used in a wide variety of signal processing applications, such as spectrum analysis, digital image processing, and pattern recognition. Digital filters eliminate a number of problems associated with their classical analog counterparts and thus are preferably used in place of analog filters. Digital filters belong to the class of discrete-time LTI (linear time invariant) systems, which are characterized by the properties of causality, recursibility and stability.
1.5Overview of Project The below shown is the block diagram for FIR Band Pass Filter implemented on FPGA. It is divided into 3 parts. ADC (Analog to Digital Converter) Virtex-4 FPGA DAC (Digital to Analog Converter) JTAG from System
PROM
14 bit Digital i/p's to FPGA
Signal Generator ADC
14 bit Digital i/p's to DAC
VIRTEX-4 FPGA
DAC Digital Oscilloscope
105 MHz Sampling Frequency
Fig. 1.1 Block Diagram Input signal in the range of 40 MHz to 50 MHz from a function generator and a sampling clock of 105 MHz are simultaneously given as input to the 14-bit ADC (AD 6645). Here the analog signal is converted into digital signal. The digital output from ADC is given as input to the FPGA. A code in ‘C’ language and VHDL is written and 4
subsequently ported into FPGA so that it acts as Band pass filter in the range of 40MHz to 50 MHz, that is it passes signal in the given range and rejects all others. The output of FPGA is given as input to the DAC where the digital signal is converted back to analog signal. The output from the DAC and the input signal are simultaneously viewed on the digital oscilloscope. Here IMPACT is the process to download bit files into FPGA through the PC using a JTAG cable. JTAG stands for JOINT TEST ACTION GROUP. This cable is used to connect the FPGA board to the PC. If the FPGA is to be programmed permanently PROM (programmable read-only memory) is used.
1.6Organization of the Project The chapters are arranged in the following manner Chapter 2 discuss about the Digital Filters and their importance in Signal processing. And also explains the advantages of Digital Filters over Analog Filters Chapter 3 explains the FIR and IIR filters and there features. And also explains the importance of FIR filter over IIR filter and the various comparisons between the FIR and IIR filters. Chapter 4 explains the design of FIR filter. This chapter explains various design methods for designing FIR. Chapter 5 explains the Hardware details of XtremeDSP Development Kit IV. It also explains about the hardware details of ADC, DAC, FPGA and clocks. Chapter 6 deals with softwares used, .i.e. EDK (Embedded Development Kit), Chipscope Pro, ISE (Integrated Software Environment) Chapter 7 includes project code and simulated output. Chapter 8 conclusions and the scope of further development are discussed in this chapter and the references used are listed.
5
CHAPTER 2 DIGITAL FILTERS
2.1Introduction In signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range. The following block diagram illustrates the basic idea.
Raw (unfiltered) Signal
Filtered
FILTER
Signal
Figure 2.1 Block Diagram of a filter There are two main kinds of filter, analog and digital. They are quite different in their physical makeup and in how they work. An analog filter uses analog electronic circuits made up from components such as resistors, capacitors and op-amps to produce the required filtering effect. Such filter circuits are widely used in such applications as noise reduction, video signal enhancement, graphic equalizers in hi-fi systems, and many other areas. There are well-established standard techniques for designing an analog filter circuit for a given requirement. At all stages, the signal being filtered is an electrical voltage or current, which is the direct analogue of the physical quantity (e.g. a sound or video signal or transducer output) involved. A digital filter uses a digital processor to perform numerical calculations on sampled values of the signal. The processor may be a general-purpose computer such as a PC, or a specialized FPGA (Field Programmable Gate Array).
6
The analog input signal must first be sampled and digitized using an ADC (analog to digital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to the processor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary the results of these calculations, which now represent sampled values of the filtered signal, are outputted through a DAC (digital to analog converter) to convert the signal back to analog form. Note that on a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current. The following diagram shows the basic setup of such a system.
ADC Unfiltered analog signal
Sampled Digitized Signal
VIRTEX4 FPGA
DAC Digitally filtered Signal
Filtered analog signal
Figure 2.2 Representing basic filter operation
2.2Basic Filter Terminology The terms transfer function, magnitude response, phase response, pass band ripples, stop band attenuation, cut-off frequencies and Q-factor etc. are used to describe the performance of any filter. These are briefly explained as follows •
TRANSFER FUNCTION: The transfer function of the filter is nothing but ratio of output response of the filter with respect to input response of the filter given by the equation H[w] = Y[w] / X[w] …………… [2.1]
7
Where H[w] represents the output frequency response and X[w] represents of an arbitrary input signal over the filter, which is generally chosen as sinusoidal. •
MAGNITUDE RESPONSE: The magnitude response of the filter is a graph indicating transfer function magnitude vs frequency. The significance of this graph is that it helps in determining how well the filter can differentiate signals at different frequencies.
•
PHASE RESPONSE: The phase response of a filter is a graph indicating the amount of phase shift introduced in a sinusoidal signal as a function of frequency.
•
PASS BAND RIPPLES: The pass band of a filter is the range of frequencies that the filter readily passes. The fluctuations occurring in the signal while passing through a filter in pass band is called pass band ripples. For better filter response the pass band ripples should me minimum.
•
STOP BAND ATTENUATION: It is the attenuation which the filter offers to a signal when its frequency if out of the range of pass band. For perfect filter characteristic it should be as high as possible, ideally infinity.
•
CUT OFF FREQUENCY: Often, the pass band limits will be defined by system requirements, however with no explicit pass band limits, the pass band limits are usually assumed to be the frequencies where the gain has dropped by 3 decibels (0.707 of its maximum voltage gain). These frequencies are therefore called the 3 dB frequencies or the cutoff frequencies.
•
CENTER FREQUENCY: The center frequency is equal to the geometric mean of the --3dB frequencies: fc = √f1* fh …………… [2.2] Where fc is the center frequency fl is the lower 3dB frequency fh is the higher 3dB frequency 8
•
Q-FACTOR: Another quantity used to describe the performance of a filter is the filter’s “Q”. This is a measure of the “sharpness” of the amplitude response. The Q of a band-pass filter is the ratio of the center frequency to the difference between the –3 dB frequencies (also known as the –3dB bandwidth). Therefore Q factor Q = Fc / (Fc1-Fc2) …………… [2.3] Where Fc = Center Frequency Fc1, Fc2=Cut Off frequencies
•
FILTER ORDER: The order of a digital filter is the number of previous inputs (stored in the processor’s memory) used to calculate the current output. For example
yn = xn + xn-1 represents a filter with order 1 as only one previous input value Xn-1. Other examples are follows: Zero order
:
yn = aoxn
First order
:
yn = aoxn + a1xn-1
Second order : •
yn = a0xn + a1xn-1 + a2xn-2
IMPULSE RESPONSE: The impulse response of a digital filter is nothing but the transfer function of the digital filter when the input is an impulse.
•
NO OF TABS (N): The no. Of tabs ‘N’ is a crucial element in design of digital filtering. It is specifically used on digital filter terminology and represents the number of output coefficients and the value of ‘N-1’ represents the order if the filter. Higherorder filters will obviously be more expensive to build, since they use more components, and they will also be more complicated to design. However, higherorder filters more effectively discriminate between signals at different frequencies. Hence the factor N is a crucial element in designing and cost effectiveness of any digital filter.
9
2.3Basic Filter types Both analog and digital filter class types consist of five basic filters, which are classified depending on their response. They are Band pass Filter Notch Filter Low pass Filter High pass Filter All pass Filter 2.3.1
Band Pass Filter A Band pass Filter is one that allows only a particular band of frequencies to pass
through it but attenuates all other frequencies. The magnitude and phase response of such filter is as shown in figure 2.3 below.
Fig. 2.3 Band Pass Filter The curve in 2.3 (a) is what might be called an “ideal” band pass response, with absolutely constant gain within the pass band, zero gain outside the pass band, and an abrupt boundary between the two. This response characteristic is impossible to realize in practice, but it can be approximated to varying degrees of accuracy by real filters. Curves (b) through (f) are examples of a few band pass amplitude response curves that approximate the ideal curves with varying degrees of accuracy. 10
Note that while some band pass responses are very smooth, other has ripple (gain) variations in their pass bands. Other have ripple in their stop bands as well. Band pass filters are used in electronic systems to separate a signal at one frequency or within a band of frequencies from signals at other frequencies. 2.3.2
Notch Filter A filter with effectively the opposite function of the band pass is the band-reject
or notch filter. The response of notch filter is ideally zero for a particular band of frequency and unity for all other frequencies. A number of notch filter amplitude response curves are shown in Figure 2.4. As in Figure 2.3, curve (a) shows an “ideal” notch response, while the other curves show various approximations to the ideal characteristic.
Fig. 2.4
Notch Filter
Notch filter are used to remove an unwanted frequency from a signal, while affecting all other frequencies as little as possible. 2.3.3Low Pass Filter A third filter type is the low-pass. A low-pass filter passes low frequency signals, and rejects signals at frequencies above the filter’s cutoff frequency. Figure 2.5 represents various low pass filter amplitude response curves. 11
Figure 2.5 Low Pass Filter Figure 2.5 (a) represents ideal low pass filter characteristics, while 2.5 (b)- (f) represents various other responses of the filter. Low-pass filters are used whenever high frequency components must be removed from a signal. 2.3.4High pass Filter The opposite of the low-pass is the high-pass filter, which rejects signals below its cutoff frequency. When an input signal of frequency below a particular cut off is passed through a high pass filter it will get attenuated, while all other filters are passed through the filter.
Figure 2.6 High pass Filter Figure2.6 (a) represents ideal high pass filter characteristics, while 2.6(b) – (f) represents various other responses of the filter. Note that the amplitude response of the high-pass is a “mirror image” of the low-pass response. High-pass filters are used in applications requiring the rejection of low-frequency signals. 12
2.3.5All pass Filter The fifth and final filter response type has no effect on the amplitude of the signal at different frequencies. Instead, its function is to change the phase of the signal without affecting its amplitude. This type of filter is called an all-pass or phase-shift filter. The effect of a shift on phase is illustrated in Figure 2.7. Two sinusoidal waveforms, one drawn on dashed lines, the other a solid line, are shown. The curves are identical except that the peaks and zero crossings of the dashed curve occur at later times than those of the solid curve. Thus, we can say that the dashed curve has undergone some delay relative to the solid curve
Figure 2.7 All pass Filter Since we are dealing here with periodic waveforms, time and phase can be interchanged, the time delay can also be interpreted, as a phase shift here is equal to radians. The relation between time delay and phase shift is Td= θ/2Πω so if phase shift is constant with frequency, time delay will decrease as frequency increases. All-pass filters are typically used to introduce phase shifts into signals in order to cancel or partially cancel any unwanted phase shifts previously imposed upon the signals by other circuitry or transmission media.
13
2.4
Digital versus Analog Filtering DIGITAL FILTERS
High Accuracy-Tolerances Linear Phase (FIR Filters) No Drift due to Component Variations
ANALOG FILTERS Less Accuracy-Component Non-Linear Phase Drift due to component Variations
Flexible, Adaptive Filtering Possible
Adaptive Filter Difficult
Easy to simulate and design
Difficult to simulate and design
Computation Must be completed in Sampling Period – Limits Real Time
Analog Filters are required at Operation High Frequencies and for Anti aliasing Filters
Requires High Performance ADC, DAC and processor.
No ADC, DAC or processor required.
Table 2.1 Digital versus Analog Filtering
Analog versus Digital Filter Frequency Response Comparison:
Figure 2.8 Analog vs Digital Filter Frequency Response Comparison 14
2.5
Advantages of Filtering
The following list gives some of the main advantages of digital over analog filters. 1. A digital filter is programmable, i.e., a program stored in the processor’s memory determines its operation. This means the digital filter can easily be changed without affecting the circuitry (hardware). Redesigning the filter circuit can only change an analog filter. 2. Digital filters are easily designed, tested and implemented on a general-purpose computer or workstation. 3. The characteristics of analog filter circuits (particularly those containing active components) are subject to drift and are dependent on temperature. Digital filters do not suffer from these problems, and so are extremely stable with respect both to time and temperature. 4. Unlike their analog counterparts, digital filters can handle low frequency signals accurately. As the speed of FPGA technology continues to increase, digital filters are being applied to high frequency signals in the RF (radio frequency) domain, which in the past was the exclusive preserve of analog technology. 5. Digital filters are very much more versatile in their ability to process signals in a variety of ways, this includes the ability of some types of digital filter to adapt to changes in the characteristics of the signal.
2.6
Operation of Digital Filters In this section, we will develop the basic theory of the operation of digital filters.
This is essential to an understanding of how digital filters are designed and used. Suppose the “raw” signal, which is to be digitally filtered, is in the form of a voltage waveform described by the function V = x(t) Where t is time This signal is sampled at time intervals h (the sampling interval). The sampled value at time t = ih is Xi = x(ih) 15
Thus the digital values transferred from the ADC to the processor can be represented by the sequence x0, x1, x2, x3, …… Corresponding to the values of the signal waveform at t = 0, h, 2h, 3h, …. And t=0 is the instant at which sampling begins. At time t=nh (where n is some positive integer), the values available to the processor, stored in memory, are x0, x1, x2 x3, ….xn Note that the sampled values xn-1,xn-2 etc. are not available, as they haven’t happened yet! The digital output from the processor to the DAC consists of the sequence of values y0 ,y1 , y2 , y3 , … yn In general, the value of yn is calculated from the values x0, x1, x2 x3, ….xn. The way in which the y’s are calculated from the x’s determines the filtering action of the digital filter.
2.7
General Applications of Digital Filters Traditionally, most digital filter applications have been limited to audio and high-
end image processing. With advances in process technologies and digital signal processing methodologies digital filters are now cost-effective in the IF range and in almost all video markets. Digital filters are commonly used for audio frequencies for two reasons. Digital filters for audio are superior in price and performance to the analog alternative.
16
Audio Analog-to-Digital Converters (A/Ds) and Digital-to-Analog Converters (D/As) can be manufactured with high accuracy rate and available at low cost. Thus, the combined cost of filtering and conversion (if necessary) is low. The cost trades are much more difficult in the 1MHz to 100MHz signal range, such as the IF ranges of many radio receivers. While digital signal processing technology can now produce cost effective digital filters for IF, the cost or even the availability of data conversion products are limiting factors. Many IF digital filtering applications are band limiting and decimating. In these cases the design engineer must not only know digital filters, but also understand the effects of narrow-band-filtering, processing-gain on A/D requirements. Additionally, power dissipation must be considered. Currently, digital IF filter solutions are excluded from low power applications such as personal communication devices. In contrast, audio frequency digital filters are essential.
2.8
Conclusion Digital filter is a linear time-invariant discrete time system. Digital filters are far
better than Analog filters. Unlike Analog filter, component ageing does not influence the Digital filter performance, temperature and power supply variations. A Digital filter is highly immune to noise and possess considerable parameter stability. Digital filters afford a variety of shapes for the magnitude & phase response. There are no problems of amplitude and impedance matching with Digital filters. The Coefficients of Digital filter can be programmed and altered any time to obtain desired filter characteristics. Multiple filtering is possible only in Digital Filters.
17
CHAPTER 3 FIR AND IIR FILTERS 3.1Introduction There are two fundamental types of digital filters: Finite Impulse Response (FIR) and Infinite Impulse Response (IIR). As the terminology suggests, these classifications refer to the filter’s impulse response. By varying the weight of the coefficients and the number of filters taps, virtually any frequency response characteristic can be realized with an FIR filter. FIR filters can achieve performance levels, which are not possible with analog filter techniques (such as perfect linear phase response). However high performance FIR filters generally require a large number of multiply-accumulates and therefore requires fast and efficient processors. On the other hand, IIR filters tend to mimic the performance of traditional analog filters and make use of feedback. Therefore their impulse response is over an infinite period of time. Because of feedback, IIR filters can be implemented with fewer coefficients than for an FIR filter.
3.2Finite Impulse Response (FIR) Filters Finite impulse response (FIR) filters are digital filters, which have a finite impulse response. FIR filters do not employ any feedbacks and are also known as nonrecursive filters, convolution filters, or moving-average (MA) filters because you can express the output of a FIR filter as a finite convolution. n-1
yi = ∑ h k x i-k
…………………..
(3.0)
k=0
Where x represents the input sequence to be filtered, y represents the output-filtered sequence and h represents the FIR filter coefficients. By saying finite impulse response we mean that the infinite impulse response obtained from the desired frequency response Hd[w] is made finite by taking the required 18
number of samples to represent the filter characteristics closest to the desired. The number of samples to represent number of tabs ‘N’ which is a crucial element in determining the overall performance and cost of the FIR filter. An FIR “tap” is simply a coefficient/delay pair. The number of FIR taps ‘N’ is an indication of The amount of memory required to implement the filter. The number of calculations required. The amount of “filtering” the filter can do, more taps means more stop band attenuation, less ripple, narrower filters, etc. The generalized form of an N-tap FIR filter is shown in Figure 3.1. An FIR filter must perform the following convolution equation: N-1
y(n) = h(k)*x(n) = ∑ h(k)x(n-k) …………………..(3.1) k=0
Where h(k) is the filter coefficient array and x(n-k) is the input data array to the filter. The number N, in the equation, represents the number of taps of the filter and relates to the filter performance as has been discussed above. An N-tap FIR filter requires N multiply-accumulate cycles. By designing the filter taps to be symmetrical about the center tap position, a FIR filter can be guaranteed to have linear phase. This guaranteed to preserve the phase of the signal makes FIR filter a more desirable entity for filtering than any other entity in its class such as analog or IIR filers. Also because no feedback is involved they tend to be realize the desired transfer function H(f). Various algorithms are available to translate the frequency response H(f) into a set of FIR coefficients. Most of this software is commercially available and can be run on PCs. The key theorem of FIR filter design is that the coefficients h(n) of the FIR filter are simply the quantized values of the impulse response of the frequency transfer function H(f). Conversely, the impulse response is the discrete Fourier transform of H(f). The other important features of FIR filters are given in context 3.3 19
FIGURE 3.1 N-Taps Finite Impulse Response (FIR) Filter
x(n)
x(n-1) Z
h(0)
x(n-N+2)
-1
X
h(1)
Z
-1
Z
h(N-2)
X
x(n-N+1)
X
-1
h(N-1)
X y(n)
y(n) = h(n) * x(n) = ∑ h(k) x(n-k) k=0 * = Symbol for Convolution
3.3Features of the FIR Filter Some of the general features of the FIR filters are summarized here as follows: Exact linear phase, a characteristic very useful in speech processing. Question of physical reliability never arises; with a finite delay it is always realizable. Filter design problems with an arbitrary magnitude response can be tackled using FIR sequences. However, a higher order filter is required if same sharpness in magnitude characteristics as IIR filters is desired. Errors arising from quantization are usually less round-off noise that can be made small by employing non-recursive technique of realization.
3.4Infinite Impulse Response (IIR) Filters 20
Another type of digital filter is the Infinite Impulse Response (IIR) filter. IIR filters use feedback, so when you input an impulse the output theoretically rings indefinitely. Infinite impulse response filters get their name because they are recursive i.e., they utilize feedback although they can be implemented with fewer computations than FIR filters. IIR filters do not match the performance achievable with FIR filters, and do not have linear phase. Also, there is no computational advantage achieved when the output of an IIR filter is decimated because each output value must always be calculated. The difference equations that represent the IIR filters in general can be described as follows: M
K
y(n) = ∑ am x(n-m) + ∑ bk x(n-m) …………….(3.2) m=0
k=0
Where am and bm are suitable constants, and x(n) and y(n) represent the input and output sequences respectively. FIR filters have no real analog counterparts, the closest analogy being the weighted moving average. In addition, FIR filters have only zeros and no poles. On the other hand, IIR filters have traditional analog counterparts (Butterworth, Chebyshev, Elliptic, and Bessel) and can be analyzed and synthesized using more familiar traditional filter design techniques.
3.5Features of the IIR Filters: The important features of an IIR FILTER are: Uses Feedback (Recursion). Impulse Response has Infinite Duration. Potentially Unstable. Non-Linear phase. More Efficient than FIR filters. No Computational Advantage when Decimating the Output. Usually Designed to Duplicate Analog Filter Response. 21
Usually Implemented as Cascaded Second-Order Sections (Biquads). As it has been seen above, the FIR filter can only have a time domain response to a pulse equal to the number of terms (or taps). With an IIR filter the response of the filter can be infinite. An IIR filter is effectively made up of two FIR filters, one in the forward path and one in a feedback path. This allows the transfer function to have Z terms above and below the line, e.g. T = (a0 + a1 Z-1 +a2 Z-2 +a3 Z-3 +a4 Z-4...) / (1 + b1 Z-1 +b2 z-2 + b3 Z-3 +b4 z-4...)
3.6FIR versus IIR Filters Choosing between FIR and IIR filter designs can be somewhat of a challenge, but a few basic guidelines can be given. Typically, IIR filters are more efficient than FIR filters because they require less memory and fewer multiply-accumulates are needed. IIR filters can be designed based upon previous experience with analog filter designs. IIR filters may exhibit instability problems, but this is much less likely to occur if higher order filters are designed by cascading second-order systems. On the other hand, FIR filters require more taps and multiply-accumulates for a given cutoff frequency response, but have linear phase characteristics. Since FIR filters operate on a finite history of data, if some data is corrupted (ADC sparkle codes, for example) the FIR filter will ring for only N-1 samples. Because of the feedback, however, an IIR filter will ring for a considerably longer period of time. If sharp cutoff filters are needed and processing time is at a premium, IIR elliptic filters are a good choice. If the number of multiply-accumulates is not prohibitive, and linear phase is a requirement, then the FIR should be chosen.
3.7Comparison between FIR and IIR Filters When compared to IIR filters, FIR filters offer the following advantages: They can easily be designed to be “linear phase” (and usually are).
22
They are simple to implement. On most FPGA & DSP microprocessors, looping a single instruction can do the FIR calculation. They are suited to multi-rate applications. By multi-rate, we mean “decimation” (reducing the sampling rate), “interpolation” (increasing the sampling rate), or both. Whether decimating or interpolating, the use of FIR filters allows some of the calculations to be omitted, thus providing an important computational efficiency. In contrast, if IIR filters are used, each output must be individually calculated, even if it that output is discarded (so the feedback will be incorporated into the filter). They have desirable numeric properties. In practice, all FPGA & DSP filters must be implemented using “finite-precision” arithmetic, that is, a limited number of bits. The use of finite-precision arithmetic in IIR filters can cause significant problems due to the use of feedback, but FIR filter have no feedback, so they can usually be implemented using fewer bits, and the designer has fewer practical problems to solve related to non-ideal arithmetic. They can be implemented using fractional arithmetic. Unlike IIR filters, is always possible to implement a FIR filter using coefficients with magnitude of less than 1.0. (The overall gain of the FIR filter can be adjusted at its output, if desired.)
3.8Conclusion On comparing the different types of the Digital Filters, their advantages and disadvantages, the Design of FIR Filter is an efficient and easiest technique. The output response i.e., the magnitude and phase response obtained by this technique is more realizable. FIR filter is employed in applications where there is a requirement of linear phase within the pass band. Unlike IIR filters, FIR filters are always stable and flexible to design. There are excellent design procedures for designing FIR filter as compared to IIR filter and also for a filter to be causal, it needs to be FIR. Compared to IIR filters, FIR filters sometimes have the disadvantage that they require more memory and/or calculation to achieve a given filter response characteristic. Also, certain responses are not practical to implement with FIR filters. 23
In contrast, IIR filters tend to mimic the performance of traditional analog filters and make use of feedback. They do not maintain the phase constant and are generally non-causal. FIR filters are more flexible, stable and less prone to errors. Because of these advantages FIR filter is chosen to be designed.
CHAPTER 4 24
DESIGN OF DIGITAL FIR FILTER
4.1Introduction The two forms of Digital filters are FIR (Finite Impulse Response) and IIR (Infinite Impulse Response). The former one is commonly referred to as Recursive and the latter one as Non-recursive filters. The difference equations that represent the IIR and FIR filters in general can be described as follows: y ( n) =
M
K
m=0
k =0
Σ am x(n − m) + Σ bk x(n − m)..................................(4.0)
Where am and bm are suitable constants, and x(n) and y(n) represent the input and output sequences respectively, for the Recursive IIR filter. If the Recursive term is absent, that is bk=0, then we have, an FIR digital filter. The Design of these two forms is explained here. y ( n) =
M
Σa
m=0
m
x(n − m).........................................................(4.1)
4.2Design of IIR Filter The conventional approach to the design of IIR digital Filter involves the transformation of an analog filter into a digital filter meeting the prescribed specifications. The following two methods are used to design IIR filter. Impulse Invariance method Bilinear transformation method
4.3Design of FIR Filter
25
There are three well-known methods of design techniques for linear phase FIR filters Fourier series method and windows Frequency sampling method Optimal filter design methods
4.4Impulse Response of ideal FIR-BPF For an ideal filter in the pass band the frequency response of the filter is eual to one and is stopband the frequency response of the filter is zero. For the bandpass filter the pass band is wc1 < |w| <wc2 and the stop band regions are 0 <= |w| <= wc1 and wc2 <= | w| <= ∏. jw
H(e
)
1.0
-w
c2
-w
c1
0
w
c1
w
c2
Fig 4.1 Frequency Response of Bandpass Filter
H( h(n)
jω
) = 1 for
ωc1 ≤ |ω| ≤ ωc2 jωn
= =
[
-jωc1
jωn
dω + -jωc2
jωc2 n
dω jωc1 n
]
26
=
h(n)
[sin ωc2n - sin ωc2n]
=
-∞ ≤ n ≤ ∞
Filter co-efficients of FIR BPF Co-effiecients of Zero Phase Filter hd(0)
=
hd(0) =
sin (ωc2n)- sin (ωc2n)]|n| > 0
Co-effiecients of Linear Phase Filter with delay α = hd(n)
= =
for n = α sin ωc2(n- α)- sin ωc2(n- α)]
CHAPTER 5 27
HARDWARE DETAILS OF XTREME DSP DEVELOPMENT KIT IV PLATFORM
5.1Introduction Xtreme DSP Development kit IV development platform for virtex-4 FPGA technology is used for porting the algorithm written for the band pass filter in ‘C’ language and subsequently ported into FPGA. Xtreme DSP development kit contains one user FPGA XC4VSX35-10FF668- a virtual-4 family FPGA, two independent ADC channels AD6645 ADC and two independent DAC channels AD9772 DAC and 105MHz clock for sampling ADC. The Xtreme DSP Development Kit serves as an ideal development platform for Xilinx Virtex Series FPGAs. Its dual channel high performance ADCs and DACs, as well as the user programmable Xilinx Virtex series device are ideal to implement high performance signal processing applications such as Software Defined Radio, 3G Wireless, Networking, HDTV or Video Imaging. The FPGA provided depends on the version of the Kit.
XTREME DSP DEVELOPMENT KIT IV BLOCK DIAGRAM The Xtreme DSP Development Kit-IV features three Xilinx FPGAs - a Virtex-4 User FPGA, a Virtex-II FPGA for clock management and a Spartan-II Interface FPGA. The Virtex-4 device is available exclusively for user designs whilst the Spartan-II is supplied pre-configured with firmware for PCI/USB interfacing. The Interface FPGA communicates directly with the larger User FPGA (XC4VSX35-10FF668) via a dedicated communication bus that is made up of the LBUS and ADJOUT busses shown in Figure 5.1. The Virtex-4 XC4VSX35-10FF668 device is intended to be used for the main part of a user’s design. The Virtex-IIXC2V80-4CS144 is intended to be used as a clock configuration device in a design.
28
2x tri-color User LEDs
2 banks ZBT Memory
Power Supply Status LEDs
2 pin User Header (J16)
105 MHz Crystal Oscillator
MCX External Clock Input
Adjacent Out Bus (ADJOUT) Spartan-II Interface FPGA Local Bus (LBUS) Configured with Appropriate Interface Control Firmware (i.e. USB/PCI)
Programmable Clock Source A
Virtex-II (XC2V80-4CS144) User Clock FPGA
Virtex-4 (XC4VSX35-10FF668) Main User FPGA
Programmable Clock Source C
32bit 33MHz PCI Interface
Flying lead JTAG Header
Comms PLink 0
P-Link 0 Digital I/O Header
USB nterface
Adj In [0:27] Digital I/O Header
2x ADC (MCX Inputs) Parallel-IV JTAG Header
Programmable Clock Source B Adjacent In Bus (ADJIN)
2x DAC (MCX Outputs)
Nallatech Test Headers (JTAG + RS232)
uP JTAG Header
KEY Connected bus Inter-FPGA Clock nets source clocks, generated clocks and feedback clock nets)
Signals predominantly associated with the general kit, i.e. JTAG access. User Signals part or in whole associated with the FPGAs.
* Note that clock C is NOT initially available in the Kit. It is a socket to allow users to populate their own crystals if required.
Figure 5.1 Xtreme DSP Development Kit-IV Functional Diagram
29
Main User FPGA (XC4SX35) Oscillator 105MHz
uP JTAG
2 Pin User I/O Header
Parallel-IV JTAG Header General JTAG
User LEDs
Power Supply Status LEDs Standalone Power Supply ADC2 MCX Input ADC1 MCX Input USB Connection
External MCX Clock Input DAC2 MCX Input DAC1 MCX Input Power Supply Status LEDs
User FPGA with Fan Fitted
ZBT Memory
Interface FPGA (XC25200)
PCI Connection
Figure 5.2 XtremeDSP Development Kit-IV
5.2Hardware Xtreme DSP development board consisting of a motherboard populated with a module (daughter card) in a blue stand-alone board case. The motherboard is referred to as the "BenONE-Kit Motherboard" and the module is referred to as the "BenADDA DIME-II module". BenONE-Kit Motherboard •
Supports the supplied BenADDA DIME-II module only
•
Spartan-II FPGA for 3.3V/5V PCI or USB interface
•
Host interfacing via 3.3V/5V PCI 32-bit/33-MHz or USB v1.1 interfaces
•
Status LEDs
•
JTAG configuration headers
•
User 0.1" pitch pin headers connected directly to user programmable FPGA I/O
30
Ben ADDA DIME-II module •
Virtex-4 User FPGA: XC4VSX35-10FF668
•
2 independent ADC channels: AD6645 ADC (14-bits up to 105 MSPS)
•
2 independent DAC channels: AD9772 DAC (14-bits up to 160 MSPS)
•
Support for external clock, on board oscillator and programmable clocks
•
Two banks of ZBT-SRAM (133MHz, 512Kx32-bits per bank)
•
Multiple Clocking Options: Internal & External
•
Status LEDs
External power supply. Wide ranging input (90 - 264Vac), multiple output, power supply, generating; •
+5 Volts @ 5A, +12 Volts @ 2A, -12 Volts @ 800mA
USB v1.1 compatible cable, 2 metres long 5 MCX to BNC cables for connecting to the ADC / DAC and external clock connectors Large blue Kit carrying case
5.3ADC 6645 (Analog to digital Convertor) The BenADDA DIME-II module used in the XtremeDSP Development Kit-IV has two analog input channels, with each channel providing independent data and control signals to the FPGA. Two sets of 14-bit wide data are fed from two ADCs (AD6645) devices, each of which has an isolated supply and ground plane. Figure 5.3 illustrates the interfacing between one of the ADCs and the FPGA. The AD6645 is a high speed, high performance, and monolithic 14-bit analog to digital Converter.
31
Figure 5.3 ADC to FPGA Interface
5.3.1Features of the on board ADC channels 14-bit ADC resolution, 2's complement format. 105MSPS sampling data rate. Single-ended 50Ω impedance analog inputs. ADCs clocked differentially. SNR = 75 dB, fIN 15 MHz up to 105 MSPS SNR = 72 dB, fIN 200 MHz up to 105 MSPS 1.5 W Power Dissipation Twos Complement Digital Output Format All necessary functions, including track-and-hold (T/H) and reference are included on the chip to provide a complete conversion solution. 5.3.2ADC Architecture The ADC (AD6645) is straightforward to operate - the user is only required to apply data and a clock input. There are no set-up or control signals. Figure 5.3 shows the internal architecture of the ADC. 32
Figure 5.4 ADC (AD6645) Internal Architecture The AD6645 has complementary analog inputs; each input is centered at 2.4V and should swing +/ - 0.55V around this 2.4V reference. This means that the differential analog input signal will be 2.2Vpp as both input signals (AIN and AIN#) are 180 degrees out of phase with each other. When data arrives at the AD6645, both analog inputs are buffered prior to the first track-and-hold (TH1). The analog signals are held in TH1 while the ENCODE (CLK) pulse is high and then data is applied to the input of a 5-bit coarse ADC (ADC1). The digital output of ADC1 is fed into the 5-bit DAC1. The output from the DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. The purpose of TH2 is to provide a pipeline delay to compensate for the digital delay of ADC1. This first residue signal is then applied to the second conversion stage. Again a similar process is achieved through this stage, which finally leads onto obtaining a second residue signal that is applied to a third 6-bit ADC. Finally the digital outputs of ADC1, ADC2 and ADC3 are added together and corrected in the digital error correction logic to generate the final output.
33
5.3.3ADC Clocking Each ADC device is clocked directly by an independent differential, LVPECL signal. This LVPECL signal is driven from the Virtex-II XC2V80-4CS144 FPGA (Clock FPGA), which is dedicated to managing the various methods for clocking each ADC and DAC device in the Kit. The way the ADCs are clocked depends on the bit file that is assigned to the dedicated Clock FPGA. A number of clock sources can be used through the Clock FPGA including: On board 105 MHz crystals. External clock input via the middle MCX connector. Clocks from the programmable oscillators available in the Kit.
5.4AD9772 DAC (Digital to Analog Convertor) The BenADDA DIME-II module used in the XtremeDSP Development Kit-IV has two analog output channels, with each channel having independent data and control signals from the FPGA. Two sets of 14-bit wide data busses are fed to the two DACs (AD9772A devices), each of which has an isolated supply and ground plane. Figure 5.4 illustrates the interfacing between one of the DACs and the FPGA. The DAC device offers 14-bit resolution and a maximum conversion rate of 160MSPS. Additional control signals exist between the DAC and the FPGA to enable full control of the DAC’s functionality. 5.4.1Features of the AD9772A (DAC) 14-bit DAC resolution. 160MSPS max input data rate. LVPECL clock inputs from the XC2V80-4CS144 Clock FPGA. Internal Phase-Locked Loop (PLL) clock multiplier device feature. Single ended (DC coupled) 50Ω outputs via MCX connectors as standard. 34
Figure 5.5 DAC Interface 5.4.2DAC Architecture The AD9772A's architecture comprises four key areas as shown in Figure 5.5. Figure 5.5 shows the internal architecture of the AD9772A. Initially, the user feeds 14bits of data into the AD9772A. This data is latched into edge-triggered latches on the rising edge of the reference lock, interpolated by a factor of 2 by the digital filter, and then fed to the 14-bit DAC. The filter characteristic can be set to either low pass or high pass for baseband and IF applications respectively. The MOD0 input is used to control this function of the AD9772A.
35
Figure 5.6 AD9772 Architecture The interpolated data can feed the DAC directly or undergo a "zero-stuffing" process, enabled using MOD1. This process involves inserting a mid-scale sample after every data sample originating from the digital filter, which improves the pass-band flatness of the DAC and also allows for the extraction of higher frequency images. The AD9772A generates a variety of clock frequencies to operate its elements at the correct rates. To achieve these frequencies, it utilizes an internal PLL whose VCO can generate clock rates of up to 400MSPS. The AD9772A can be operated with the PLL enabled or disabled (both operations are supported on the BenADDA DIME-II module used in the Kit). The combination of the MOD ad DIV input control signals determines the effective operation of the DAC devices. The hardware section, which follows, provides more details on the MOD and DIV pins. 5.4.3DAC Clocking Each DAC device is clocked directly by an independent differential, LVPECL signal. This LVPECL signal is driven from Virtex-II XC2V80-4CS144 FPGA (Clock FPGA), which is solely dedicated to managing the various methods for clocking each ADC and DAC device in the Kit. The way the DACs are clocked depends on the bit file that is assigned to the dedicated Clock FPGA. A number of clock sources can be used through the Clock FPGA including: On board 105 MHz Crystal. 36
External clock input via the middle MCX connector. Clocks from the programmable oscillators available in the Kit. 5.5 FPGA (FIELD PROGRAMMABLE GATE ARRAY) Field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or simple mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. Logic blocks and interconnects can be programmed by the customer or designer, after the FPGA is manufactured, to implement any logical function —hence the name "field-programmable".
5.5.1 Architecture The typical basic architecture consists of an array of configurable logic blocks (CLBs) and routing channels. Multiple I/O pads may fit into the height of one row or the width of one column in the array. Generally, all the routing channels have the same width (number of wires). An application circuit must be mapped into an FPGA with adequate resources. A classic FPGA logic block consists of a 4-input lookup table (LUT), and a flip-flop, as shown below. In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance.
37
Figure 5.7 Typical logic block diagram There is only one output, which can be either the registered or the unregistered LUT output. The logic block has four inputs for the LUT and a clock input. Since clock signals (and often other high-fan-out signals) are normally routed via special-purpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed. Xilinx has two main FPGA families: the high performance Virtex series and the low cost Spartan series.
5.5.2Spartan series The Spartan series are low cost parts, roughly parallel to the Virtex 2 series. They are slower than the corresponding Virtex parts.
5.5.3Virtex series The Virtex series has in addition to the normal FPGA logic fabric embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores. The number of multipliers ranges from a few tens to several hundred, depending on the device. Likewise, the amount of block RAM’ s ranges from a few hundred kilobits to tens of megabits. While all models include some block RAM and multipliers, embedded PowerPC cores. Starting with the Virtex-4, Xilinx transitioned to having multiple versions of their product with different features, optimized for different purposes. They are
Virtex-4 models
Logic cells
Virtex-4 LX
14 000 to 20 000 38
Description Optimised for logic, up to 200 000 logic cells.
Includes embedded Virtex-4 FX
12 000 to 14 000
PowerPC cores on the die, and serial connectivity. Optimised for DSP and
Virtex-4 SX
23 000 to 55 000
memory-intensive applications
Table 5.1 Virtex-4 Models Because we require logic cells in the range of 23000 to 55000, we opt for virtex-4 SX.
5.5.4
Xilinx XC4VSX35-10FF668 Virtex-4 FPGA Features
10/100 Ethernet PHY USB-UART bridge 64MB DDR SDRAM 4MB Flash LVDS Interface Clock synthesizer 2 x 16 character LCD User LEDs and switches P240 standard Interface System ACE Interface
5.6 Clocks The XtremeDSP Development Kit-IV has a comprehensive and flexible clock management system. The features available are as follows: A 105MHz crystal source on the module primarily to provide a low jitter clock source for the analog devices. An external clock input via one of the MCX connectors. 39
Two software programmable clock sources on the motherboard, which can be set to a number of frequencies. These provide two general-purpose system clocks for user designs. Single fixed oscillator socket on the motherboard. 5.6.1
DIME-II System Clocks The BenADDA DIME-II module can make use of three system clocks fed from
the motherboard to the User FPGA. These are called CLKA, CLKB and CLKC. The clock signals are generated on the DIME-II motherboard and routed into the module site where the BenADDA DIME-II module is placed. These clocks can be controlled by the user and are routed to Global Clock pins to provide maximum flexibility on the User FPGA. However, note that the functionality of these DIME-II clocks is determined by the motherboard. When the BenADDA DIME-II module is fitted to the BenONE-Kit Motherboard, as in the XtremeDSP Development Kit-IV configuration, the available DIME-II clocks are: CLKA - available programmable oscillator on the BenONE-Kit Motherboard CLKB - available programmable oscillator on the BenONE-Kit Motherboard CLKC - connected to a socket to support a crystal oscillator. 5.6.2
Clocking Configuration The Figure 5.7 provides an overview of the XtremeDSP Development Kit-IV
clock structure.
40
Figure 5.8 Clock Structure
41
5.6.3
Source Descriptions
Programmable Oscillators The Programmable Oscillators are controlled via FUSE Software, through any of the available interfaces/APIs. The available operating frequencies of the programmable oscillators are as follows: 20 MHz; 25 MHz; 30 MHz; 33.33 MHz; 40 MHz; 45 MHz; 50 MHz; 60 MHz; 66.66 MHz; 70 MHz; 75 MHz; 80 MHz; 90 MHz; 100 MHz; 120 MHz Module On board 105 MHz Oscillator An on board crystal oscillator that generates an LVTTL clock signal is supplied with the standard build of the BenADDA DIME-II module. The LVTTL clock signal generated by this oscillator is driven directly into the Clock FPGA. This clock signal can then be used to derive the differential clock signals used to clock both the DACs and the ADCs. The crystal oscillator supplied with the BenADDA DIME-II module has a low jitter characteristic and its speed will be matched to the sampling frequency of the ADCs. For the ADC AD6645, a 105MHz crystal oscillator is supplied. 5.6.4
Inter-FPGA Clock Management
Overview There are a number of clock nets between the main User FPGA (XC4VSX3510FF668) and the Clock FPGA (XC2V80-4CS144). These clock nets allow for a flexible routing of clock signals between the two FPGAs to support the range of clocking structures and clock sources. There are signals for passing generated clock signals from the main FPGA to the Clock FPGA and also feedback signals from the Clock FPGA to the main FPGA.
42
Generated Clock Signals from User FPGA Another method of clocking the DACs and ADCs is to use clock signals generated by the User FPGA. Within the User FPGA there are three DIME-II system clocks: CLKA, CLKB and CLKC. In this Kit, only CLKA and CLKB clock sources are programmable and CLKC is connected to a socket for a crystal oscillator. These system clocks can be used to derive an appropriate clock frequency within the User FPGA and then driven into the Clock FPGA where they can be forwarded out to the appropriate DACs and/or ADCs. These generated clock signals are forwarded from the User FPGA to the Clock FPGA as four single-ended signals. From the Clock FPGA, the forwarded clock signals can then be sent out to the DACs/ADCs as differential signals. 5.6.5
Clocking the ADCs and DACs There are a number of ways in which the ADCs and DACs can be clocked and a
degree of flexibility due to the inter-FPGA clocking structure between the main User FPGA (XC4VSX35-10FF668) and the Clock FPGA (XC2V80-4CS144). Using the Module 105MHz Crystal or External MXC Clock Both these clocks are directly input to the Clock FPGA. They do not directly connect to the main User FPGA; therefore a design is required in the Clock FPGA to send the clock input down to the main User FPGA as well as to the ADCs and DACs. Figure 5.8 shows a suggested design.
43
Figure 5.9 Using the Crystal or MCX Input to Clock the ADCs and DACs
44
CHAPTER 6 PROGRAMMING OF FPGA
To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic design automation tool, a technology-mapped net list is generated. The net list can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated is used to reconfigure the FPGA. There are three different software’s used for writing the code and viewing the output of our filter design. They are 1.
Xilinx ISE 8.2
2. Chip Scope Pro 8.2 3.
Xilinx EDK 8.2
6.1XILINX ISE 8.2 ISE stands for Integrated Software Environment. The Xilinx ISE system is an integrated design environment that that consists of a set of programs to create (capture), simulate and implement digital designs in a FPGA or CPLD target device. It is Compatible with VHDL and Verilog. In our project VHDL is used. 6.1.1Design Flow Overview The following steps are involved in the realization of a digital system using Xilinx FPGAs, as illustrated by the following figure. 45
Figure 6.1 Overview of the various steps involved in the design flow of a digital system 6.1.2Design Entry The first step is to enter your design. This can be done by creating “Source” files. Source files can be created in different formats such as a schematic, or a Hardware Description Language (HDL) such as VHDL or Verilog. A project design will consist of a top-level source file and various lower-level source files. Any of these files can be either a schematic or a HDL file. 6.1.3Design Synthesis The synthesis process will check code syntax and analyze the hierarchy of your design, which ensures that your design is optimized for the design architecture you have selected. The synthesis step creates netlist files from the various source files. The netlist files can serve as input to the implementation module.
46
6.1.4Design Verification (simulation) This is an important step that should be done at various stages of the design. The simulator is used to verify the functionality of a design (functional simulation), the behavior and the timing (timing simulation) of your circuit. Timing simulation is run after implementing your circuit in the FPGA since it needs to know the actual placement and routing to find out the exact speed and timing of the circuit. 6.1.5
Design Implementation After generating the netlist file (synthesis step), the implementation will convert
the logic design into a physical file that can be downloaded on the target device (e.g. Virtex FPGA). This step involves three sub-steps: Translating the netlist, Mapping and Place & Route. Translate, which merges the incoming netlists and constraints into a Xilinx design file. Map, which fits the design into the available resources on the target device. Place and Route, which places and routes the design to the timing constraints. Programming file generation, which creates a bitstream file that can be downloaded to the device. 6.1.6
Device Configuration This refers to the actual programming of the target FPGA by downloading the programming file to the Xilinx FPGA.
6.2
CHIPSCOPE PRO 8.2
6.2.1Overview As the density of FPGA devices increases, so does the impracticality of attaching test equipment probes to these devices under test. The ChipScope™ Pro tools integrate key logic analyzer hardware components with the target design inside Xilinx Virtex™, 47
Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3 and Spartan-3E devices. The ChipScope Pro tools communicate with these components and provide the designer with a complete logic analyzer. The Chipscope Pro tools communicate with these components
during system
operation and in effect provide the designer with a logic analyzer for nodes inside the Xilinx FPGA. Chipscope provides a deep trace memory, fast clock speeds and multiple trigger options, which can vary in complexity. It is possible to capture and view signal activity inside an FPGA without having to dedicate critical logic space, come up with complex capture schemes, or allocate additional I/O pins. Data samples are captured based on user-defined trigger conditions and stored in internal block memory. All control and data transfer is done via the JTAG port eliminating the need to drive data off-chip using I/O pins. The ChipScope Pro Analyzer tool supports the following download cables for communication between the PC and the devices in the JTAG Boundary Scan chain: Platform Cable USB Parallel Cable IV (used in our project) Parallel Cable III
Figure 6.2 ChipScope Pro System Block Diagram
48
ChipScope Pro is used in ISE software to configure the device and capture the signals from “Board-Under-test” (i.e., XtremeDSP Kit for our project). Following are the steps for usage of ChipScope Pro in ISE Software. Add Chipscope to ISE project Double click on added Chipscope file and select the number of triggering signals to be captured, depth of signals to be stored and select the signals. In our project we have selected 16 DAC signals to be captured and depth is 512. After Completion of Synthesis, Implement Design, Generate Programming File, double click on “Analyze Design Using Chipscope” and configure the target device. After the Analyzer has successfully communicated with a download cable, it automatically queries the Boundary Scan (JTAG) chain to find its composition. All Xilinx Virtex/-E/-II/-II Pro/-4, Spartan-II/-IIE/-3/-3E,/XL, 9500/XL/XV, 4000XL/XLA, 18V00, Platform FLASH PROMs, CoolRunner™, CoolRunner-II, and System ACE™ devices are automatically detected. To view the chain composition, select JTAG Chain → JTAG Chain Setup. A dialog box appears with all detected devices in order.
Figure 6.3 Boundary Scan (JTAG) Setup Window Now Configure the Devices which are used in your project 49
If the target device is to be programmed using a download cable by way of the JTAG port, select the Device menu, select the device you wish to configure, and select the Configure menu option. Only valid target devices can be configured and are, therefore, the only devices that have the Configure option available. Alternatively, you can right-click on the device in the project tree to get the same menu as Device.
Figure 6.4 Device Menu Options Now trigger the signals and export them into a file.
Figure 6.5 Main ChipScope Pro Analyzer Toolbar Display The toolbar buttons (from left to right) correspond to the following equivalent menu options: Open Cable/Search JTAG Chain: Automatically detects the cable, and queries the JTAG chain to find its composition Turn On/Off Auto Core Status Polling: Green icon means polling is on; red icon means polling is off. Same as JTAG Chain → Auto Core Status Poll 50
Run: Same as Trigger Setup → Run (F5) Stop: Same as Trigger Setup → Stop Acquisition (F9) Trigger Immediate: Same as Trigger Setup → Trigger Immediate (Ctrl+F5) Go To X Marker: Same as Waveform → Go To → Go To X Marker Go To O Marker: Same as Waveform → Go To → Go To O Marker Go To Previous Trigger: Same as Waveform → Go To → Trigger → Previous Go To Next Trigger: Same as Waveform → Go To → Trigger → Next Zoom In: Same as Waveform → Zoom → Zoom In Zoom Out: Same as Waveform → Zoom → Zoom Out Fit Window: Same as Waveform → Zoom → Zoom Fit
6.3
XILINX EDK 8.2 EDK stands for Embedded Development Kit. It is an integrated software solution,
which implements high performance DSP designs on XILINX FPGA. It is Compatible with ‘C’ language. The ‘C’ code in EDK is implemented in Microblaze processor 6.3.1
Design flow
’C’ code libgen generate netlist generate bitstream Update bit stream configure device output on kit. Libgen: Base addresses of the hardware pins are generated. Generate Netlist: Checks for the errors. Generate Bitstream: Bit files for the VHDL code are generated. Update bitstream: Bit files are updated. Assign package pins: Pins of the hardware are locked. Configure design: Device is programmed so as to function according to the code. Finally output is viewed using Xtreme DSP development kit IV platform.
51
6.3.2
MicroBlaze Architecture The MicroBlaze embedded processor soft core is a reduced instruction set
computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs). Figure 6.6 shows a functional block diagram of the MicroBlaze core. Features The MicroBlaze soft-core processor is highly configurable, allowing users to select a specific set of features required by their design. The processor’s fixed feature set includes: Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline
52
CHAPTER 7 PROJECT CODE AND SIMULATION RESULT 7.1PROJECT CODE 7.1.1
VHDL code in ISE (for collecting the ADC samples from kit and for viewing final output)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity final_ise is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; adc : in STD_LOGIC_VECTOR (13 downto 0); dac : out STD_LOGIC_VECTOR (13 downto 0); clk_out : out STD_LOGIC); end final_ise; architecture Behavioral of final_ise is COMPONENT system PORT ( fpga_0_DIP_Switches_GPIO_in_pin: IN std_logic_vector (13 downto 0); sys_clk_pin : IN std_logic; sys_rst_pin : IN std_logic; fpga_0_LEDS_GPIO_d_out_pin: OUT std_logic_vector (13 downto 0) ); END COMPONENT; COMPONENT fifo_gen PORT ( din: IN std_logic_VECTOR(13 downto 0); rd_clk: IN std_logic; rd_en: IN std_logic; wr_clk: IN std_logic; 53
wr_en: IN std_logic; dout: OUT std_logic_VECTOR(13 downto 0); empty: OUT std_logic; full: OUT std_logic); END COMPONENT; signal c_adc: std_logic_vector(13 downto 0); signal s_dac: std_logic_vector(13 downto 0); signal f_adc: std_logic_vector(13 downto 0); signal g_clk: std_logic; signal r_clk: std_logic; signal w_clk: std_logic; signal f_empty: std_logic; signal f_full: std_logic; begin w_clk <= g_clk; BUFG_inst : BUFG port map ( O => g_clk, I => clk ); BUFR_inst : BUFR generic map (BUFR_DIVIDE => "3") port map ( O => r_clk, CE => '1', CLR => '0', I => g_clk ); U0 : fifo_gen port map ( din => c_adc, rd_clk => r_clk, rd_en => '1', wr_clk => w_clk, wr_en => '1', dout => f_adc, empty => f_empty, full => f_full); Inst_system: system PORT MAP ( fpga_0_LEDS_GPIO_d_out_pin => s_dac, fpga_0_DIP_Switches_GPIO_in_pin => f_adc, sys_clk_pin => g_clk, sys_rst_pin => rst ); process(adc) begin if adc(13)='1' then c_adc <= ((not adc) + 1); 54
else c_adc <= adc; end if; end process; process(r_clk) begin if r_clk'event and r_clk='1' then dac <= s_dac; end if; end process; end Behavioral; User Constraint File (UCF) of above Program for locking the pins NET "adc<0>" LOC = "c17" ; NET "adc<10>" LOC = "a17" ; NET "adc<11>" LOC = "a18" ; NET "adc<12>" LOC = "a19" ; NET "adc<13>" LOC = "a20" ; NET "adc<1>" LOC = "d19" ; NET "adc<2>" LOC = "d20" ; NET "adc<3>" LOC = "c21" ; NET "adc<4>" LOC = "b18" ; NET "adc<5>" LOC = "d18" ; NET "adc<6>" LOC = "c19" ; NET "adc<7>" LOC = "c20" ; NET "adc<8>" LOC = "b20" ; NET "adc<9>" LOC = "b17" ; NET "clk" LOC = "b15" ; NET "dac<0>" LOC = "a7" ; NET "dac<10>" LOC = "d6" ; NET "dac<11>" LOC = "a6" ; NET "dac<12>" LOC = "a5" ; NET "dac<13>" LOC = "b4" ; NET "dac<1>" LOC = "c7" ; NET "dac<2>" LOC = "b7" ; NET "dac<3>" LOC = "c5" ; NET "dac<4>" LOC = "d4" ; NET "dac<5>" LOC = "c4" ; NET "dac<6>" LOC = "a4" ; NET "dac<7>" LOC = "b3" ; NET "dac<8>" LOC = "b6" ; NET "dac<9>" LOC = "e6" ; NET "rst" LOC = "h3" ; 55
7.1.2
Flow Chart for ‘C’ code in EDK (for Convolution of input samples with Bandpass Filter co-efficients)
Start
Set Data Direction to input by placing 1 in SetDataReg for collection of samples from ISE
Take Input x(n) in GetDataReg which are ADC samples collected from ISE
Take input hd(n) as Bandpass filter co-efficients
Convolve x(n) * hd(n)
Pass the convoluted samples to ISE to view the output
Stop
56
7.1.3
C code in EDK (to convolve ADC samples obtained from ISE Platform and filter coefficients, for N= 256 samples)
#include "xparameters.h" #include "stdio.h" #include "xgpio_l.h" #include "xutil.h" #include "math.h" #define N 256 Xuint32 i=0,j,x[N-1]; int yo[2*N-1]; float y[2*N-1]; float hd[]={0.0002,-0.0002,0.0014,-0.0032,0.0045,-0.0046,0.0033, -0.0011, -0.0009, 0.0019, -0.0014, -0.0000, 0.0015, -0.0020, 0.0010, 0.0012, -0.0036, 0.0051, -0.0051, 0.0036, -0.0016, 0.0002, -0.0002, 0.0017, -0.0038, 0.0054, -0.0056, 0.0040, -0.0014, -0.0011, 0.0023, -0.0018, -0.0000, 0.0018, -0.0024, 0.0012, 0.0014, -0.0044, 0.0063, -0.0063, 0.0045, -0.0020, 0.0003, -0.0003, 0.0021, -0.0048, 0.0068, -0.0070, 0.0051, -0.0017, -0.0014, 0.0030, -0.0023, -0.0000, 0.0023, -0.0031, 0.0016, 0.0019, -0.0058, 0.0083, -0.0083, 0.0060, -0.0027, 0.0003, -0.0003, 0.0028, -0.0064, 0.0093, -0.0096, 0.0069, -0.0024, -0.0020, 0.0041, -0.0032, -0.0000, 0.0033, -0.0044, 0.0023, 0.0027, -0.0083, 0.0120, -0.0121, 0.0088, -0.0040, 0.0005, -0.0005, 0.0042, -0.0099, 0.0143, -0.0149, 0.0109, -0.0038, -0.0032, 0.0066, -0.0052, -0.0000, 0.0056, -0.0076, 0.0039, 0.0047, -0.0149, 0.0219, -0.0225, 0.0166, -0.0077, 0.0010, -0.0010, 0.0088, -0.0211, 0.0315, -0.0339, 0.0256, -0.0092, -0.0081, 0.0178, -0.0147, -0.0000, 0.0178, -0.0264, 0.0149, 0.0201, -0.0717, 0.1241, -0.1575, 0.1562, -0.1151, 0.0426, 0.0418, -0.1145, 0.1559, -0.1575, 0.1244, -0.0722, 0.0205, 0.0146, -0.0262, 0.0178, 0.0000, -0.0147, 0.0180, -0.0083, -0.0090, 0.0255, -0.0338, 0.0315, -0.0211, 0.0089, -0.0010, 0.0010, -0.0076, 0.0166, -0.0225, 0.0220, -0.0150, 0.0049, 0.0038, -0.0076, 0.0055, 0.0000, -0.0052, 0.0067, -0.0032, -0.0037, 0.0108, -0.0149, 0.0143, -0.0099, 0.0043, -0.0005, 0.0005, -0.0039, 0.0088, -0.0121, 0.0120, -0.0084, 0.0028, 0.0022, -0.0044, 0.0033, 0.0000, -0.0032, 0.0041, -0.0020, -0.0023, 0.0069, -0.0095, 0.0093, -0.0065, 0.0028, -0.0003, 0.0003, -0.0027, 0.0060, -0.0083, 0.0083, -0.0058, 0.0019, 0.0016, -0.0031, 0.0023, 0.0000, -0.0023, 0.0030, 57
-0.0015, -0.0003, 0.0015, -0.0011, -0.0002, 0.0012, -0.0009, -0.0002,
-0.0017, 0.0002, 0.0012, -0.0013, 0.0002, 0.0010, -0.0011, 0.0002,
0.0050, -0.0020, -0.0024, 0.0040, -0.0016, -0.0020, 0.0033, -0.0013,
-0.0070, 0.0068, 0.0045, -0.0063, 0.0018, 0.0000, -0.0056, 0.0054, 0.0036, -0.0051, 0.0015, 0.0000, -0.0046, 0.0045, 0.0030};
-0.0048, 0.0063, -0.0018, -0.0038, 0.0051, -0.0015, -0.0032,
0.0021, -0.0044, 0.0023, 0.0017, -0.0036, 0.0019, 0.0014,
int main(void) { while(1) { for(i=0;i<256;i++) { x[i]=XGpio_mGetDataReg ( XPAR_DIP_SWITCHES_BASEADDR,1 ); } for(i=0;i<=2*N-1;i++) { y[i]=0; } for(i=0;i<=2*N-1;i++) { for(j=0;j=0) { if((i-j)
XGpio_mSetDataReg ( XPAR_LEDS_BASEADDR,1,yo[i] ); } } return 0; } 7.1.4
VHDL code for Virtex-II for Clock configuration
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity OSC_CLOCK is Port ( OSC_IN : in std_logic; DAC0_CLKp : out std_logic; DAC0_CLKn : out std_logic; DAC1_CLKp : out std_logic; DAC1_CLKn : out std_logic; ADC0_CLKp : out std_logic; ADC0_CLKn : out std_logic; ADC1_CLKp : out std_logic; ADC1_CLKn : out std_logic; CLK1_OUTp : out std_logic ); end OSC_CLOCK; architecture Behavioral of OSC_CLOCK is component BUFG port ( I: in std_logic; O: out std_logic ); end component; component OBUFDS_LVPECL_33 port ( O: out std_logic; OB: out std_logic; I: in std_logic ); end component; component OBUF 59
port ( I: in std_logic; O: out std_logic ); end component; signal OSC_OUT: std_logic; signal OSC_OUTl: std_logic; begin H6: BUFG port map (I => OSC_IN, O => OSC_OUT); H1: OBUFDS_LVPECL_33 port map (I => OSC_OUT, O => DAC0_CLKp, OB => DAC0_CLKn); H2: OBUFDS_LVPECL_33 port map (I => OSC_OUT, O => DAC1_CLKp, OB => DAC1_CLKn); H3: OBUFDS_LVPECL_33 port map (I => OSC_OUT, O => ADC0_CLKp, OB => ADC0_CLKn); H4: OBUFDS_LVPECL_33 port map (I => OSC_OUT, O => ADC1_CLKp, OB => ADC1_CLKn); H5: OBUF port map (I => OSC_OUT, O => CLK1_OUTp); end Behavioral;
User Constraint File (UCF) for above program # Clock Signals sent to ADCs/ DACs #ADC1 NET ADC0_CLKn LOC NET ADC0_CLKp LOC ADC
= =
D1; #Connected to ENCODE pin of ADC E4; #Connected to Complement of ENCODE pin of
#ADC2 NET ADC1_CLKp LOC NET ADC1_CLKn LOC ADC
= =
G1; #Connected to ENCODE pin of ADC F1; #Connected to Complement of ENCODE pin of
=
D13; #Connected to Noninverting Input of
=
D12; #Connected to Inverting Input of Differential
#DAC1 NET DAC0_CLKp LOC Differential CLK NET DAC0_CLKn LOC CLK
60
#DAC1 NET DAC1_CLKp LOC Differential CLK NET DAC1_CLKn LOC CLK
=
G10; #Connected to Noninverting Input of
=
F12; #Connected to Inverting Input of Differential
# Various Clock Signals arriving in Virtex-II #Onboard Oscillator NET OSC_IN LOC
=
M6; #Connected to a Primary Global CLK Pin
# FEEDBACK Clock Signals to large Virtex-II NET CLK1_OUTp LOC = H4;
7.2VERIFICATION IN MATLAB 7.2.1
Algorithm for MATLAB Program
Indicate the required sampling frequency and no of tabs and points required. Indicate the upper and lower cut off frequencies for the filter to be designed (40 MHz and 50 MHz respectively in our project) Take input x[n] which are the samples collected from ADC. Convolve input signal ‘x(n)’ with filter transfer function ‘h(n)’ to get ‘y(n)’. Finally fast fourier transform on ‘y(n)’ is performed to give output ‘z(n)’.
7.2.2
MATLAB program to verify the Output of Bandpass filter in Virtex-4 FPGA
clc clear all fs=105e6 N=256 P=255 a=(P-1)/2 esp=.001
% Sampling Frequency of 105M Hz % Number of Samples % Number of Taps
fc1=40e6; wc1=(fc1*2*pi)/fs fc2=50e6; wc2=(fc2*2*pi)/fs
% 1st cutoff Frequency % 2nd cutoff Frequency 61
%....................... Input Samples..........................% fid = fopen('samples45m.prn','r'); inputdata = fscanf(fid,'%s'); fclose(fid); m=0; for k=0:P m=k+1; arr1(m,1:14)=inputdata(14*k+1:14*k+14); if (arr1(m,1)=='1') x(m)=-(bin2dec(arr1(m,2:14))); else x(m)=bin2dec(arr1(m,2:14)); end end z0=fft(x); subplot(1,2,1); plot((2:N/2)*fs/N, abs(z0(2:N/2))); %.............................Main Prgram.................................% for n=1:P if n==a h(n)=(wc2-wc1)/pi; else h(n)=(sin(wc2*(n-a+esp))-sin(wc1*(n-a+esp)))./(pi*(n-a)); end; end; y= conv(x,h);
%Convolution of input n transfer function
z1 = fft(y); %FFT of convoluted signal 'y' subplot (1,2,2); plot ((2:(N+P-1)/2)*fs/(N+P-1), abs (z1(2:(N+P-1)/2)));
62
7.3SIMULATION RESULTS 7.3.1
Output waveform Captured from Chipscope pro software
Fig 7.1 Output from chipscope 7.3.2
Output Samples Captured from Chipscope pro software (Convoluted samples from ISE)
-0001 -0082 -0011 0040 0066 0004 -0040
-0000 -0009 0013 -0009 -0012 0057 -0017 -0030 0062 -0075 0003 -0006 0007 -0009 -0002 -0072 0088 -0090 0062 -0018 -0046 0022 -0010 0007 -0016 -0007 -0011 0042 -0080 0100 0079 -0091 ………………
0038 0063 0009 -0034 0021 -0103
63
-0068 -0046 -0008 0068 -0023 0071
0081 0024 -0012 -0081 0007 -0019
7.3.3
Plot of Convoluted samples obtained from Chipscope Pro in MATLAB
Fig 7.2 Matlab output of chipscope samples
7.3.4
Output Samples obtained from MATLAB for verification
1.0e+003 * -0.0014 -0.0824 -0.0112 0.0402 0.0665
-0.0000 -0.0098 0.0131 -0.0092 -0.0123 0.0387 -0.0682 0.0810 0.0570 -0.0173 -0.0304 0.0620 -0.0756 0.0631 -0.0467 0.0244 0.0030 -0.0064 0.0077 -0.0093 -0.0027 0.0095 -0.0086 -0.0120 -0.0729 0.0886 -0.0906 0.0627 -0.0184 -0.0342 0.0686 -0.0819 …………………………………………
64
7.3.5
Plot for above MATLAB samples
Fig 7.3 Output of MATLAB samples Conclusion: Thus we can see that the plots for Samples collected in Chipscope Pro and MATLAB are similar
65
7.3.6
Oscilloscope Outputs
a) For Input Frequency 45 MHz:
Fig 7.4 Oscilloscope output for frequency 45MHz Result: Input Frequency
=
45MHz
Input Amplitude
=
1.969V
Output Frequency
=
44.25 MHz
Output Amplitude
=
280mV
66
b) For Input Frequency 35 MHz:
Fig 7.5 Oscilloscope output for frequency 35MHz Result: Input Frequency
=
35MHz
Input Amplitude
=
1.156V
Output Frequency
=
not found
Output Amplitude
=
200mV
Conclusion: Thus we can see from above two waveforms that, when input is 45MHz the signal is passed and for input signal 35MHz only noise is present.
67
CHAPTER 8 CONCLUSION AND FUTURE SCOPE
8.1 Conclusion The Project has been successfully implemented in VIRTEX-4 FPGA and tested using the live signal from the signal source. The results show that the requirements of Bandpass frequency have been achieved. The implementation using the Digital BPF has provided very much flexibility because the same hardware can be used for design of BPF for different band, which could not have been possible with analog BPF. The filtering algorithm has been implemented in real time using the EDK software We can conclude that implementation of FIR digital BPF in FPGA has distinct advantage over the DSP processor in terms of processing time, which is very important for EW applications.
8.2Future scope of the project: The processing speed of FIR filter in FPGA can be improved by directly using the co-efficient with digital logic instead of EDK. As the sampling frequency of ADC is increasing to GHz range it posses the requirement of higher processing speed which can be achieved by suitably modifying the filter implementation.
68
APPENDIX - A
Picture of our Project Kit
69
BIBLIOGRAPHY 1. Digital signal processing, A. Oppenheim & R. Schafer, (Prentice-Hall,1975,ISBN 0-13-
214635-5)
2. Digital signal processing, Ramesh babu 3. Digital signal processing,Salivahana 4. Programming in C by Yashwanth Kanetkar 5. Internet resources: www.mathworks.com www.xilinx.com www.dspprojects.com www.dspvillage.com www.google.com
70