Pci Express Interface

Group Members:

Muhammad Yousaf Khan Syed Aqeel Ahmad Masood-ur-Rahman Muhammad Shahzad

Introduction PCI Express Bus I/O

Technology

Brief History Conventional PCI

Initial PCI 1.0 proposal by Intel in 1991 Introduced by PCI-SIG as PCI 2.0 in 1993 Version 2.1 approved in 1995 Recent version 2.3 approved in March 2002 PCI-X Version 1.0 approved in September 1999 Version 2.0 approved in July 2002 PCI Express Formerly known as 3GIO Version 1.0 approved in July 2002

Design Consideration  System design System architecture, Embedded CPU h/w design  PCB design Functional design, PCB timing

 PCB physical design PCB place and route, design for manufacturing  FPGA design Verilog HDL development

 DSP design  Algorithm development  Embedded software development

Why chose PCI Express PCI has limitation such as o Multidrop timeshared concept o Power and ground noise o Stubs o Trace skews o Skin effect o Dielectric loss

PCI Express is dual simplex point to point

serial differential low voltage interconnect Bit rate is 2.5Gbit/sec/lan/dir Signal is 8b or 10b encoded with embedded clock Each layer has two pair of differential signal Switches to interconnect devices Hot Plug Support

High Speed Design Issues Interconnect losses Crosstalk Mode conversion

Layered architecture of PCI Express

Transaction Layer

Transaction Layer

Data Link Layer

Data Link Layer

Physical Layer

Physical Layer

TX

RX

TX

RX

Packet flow through layers Start

Seq.#

Header

Data

ECRC

LCRC

End

Transaction layer  The upper Layer of the architecture is the

Transaction Layer.  The Transaction Layer’s primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).  TLPs are used to communicate transactions, such as read and write, as well as certain types of events.  The Transaction Layer is also responsible for managing credit-based flow control for TLPs.

Data Link Layer  The middle Layer in the stack, the Data Link

Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer.  The primary responsibilities of the Data Link Layer include Link management and data integrity, including error detection and error correction

Physical Layer  The Physical Layer includes all circuitry for interface

operation, including driver and input buffers, parallel-toserial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry.  It includes also logical functions related to interface initialization and maintenance.  The Physical Layer exchanges information with the Data Link Layer in an implementation-specific format.  This Layer is responsible for converting information received from the Data Link Layer into an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the device connected to the other side of the Link.

Cyclic Redundancy Check  While traveling a cross a link data can loose

integrity and my be prone to errors.  Cyclic redundancy codes are used to preserve the integrity of data in storage and transmission applications.  It is an error coding technique which involves addition of a certain amount of redundancy to the data in a controlled fasion.  In simple hardware applications CRCs are implemented by simply using shift register circuit in which one bit is processed at a time .

Addition of Redundancy  Following is an overview of how the redundancy is

added given block of data. # .Seq bits 16

TLP bits 16

LCRC value bits 32

Link Layer Packetizing

LCRC Generator Circuit

Schemati cs

Applicatio ns: Desktop Mobile Server Storage Embedded

Communications Military Use