Hybrid Silicon Nanoelectronics Oda Laboratory Tokyo Institute of Technology
Fusion of top-down & bottom-up nanotechnology 100
hp65
hp32
hp45
hp22
Lg (nm)
•High-k •FUSI
Low -pow er High -per form Strained Si a
ITRS2003 predicts 9 nm gate MOSFETs in 2016.
Dual metal gate
nce
FD SOI Multiple gate(3D)
10
Quasi ballistic
2005
2015 Year
2010
TOP-DOWN SILICON
BOTTOM-UP SILICON
Source
Si nanodot (SiND) Drain
Si (111)
Si nanorod (SiNR)
SiO2
30nm
10nm
In collaboration with Cambridge Univ.
Hybrid Silicon Nanoelectronics １ Structural control of nanocrystalline Si structures Si nanodots
Si nanorods
ナノシリコンドット
ドットサイズ を揃える
In collaboration with Cambridge Univ. トンネル膜厚 を揃える
Substrate UHV Chamber
To TMP Orifice (φ ∼ 5 mm)
位置を揃える
Structural control
evaporation
SiH4 gas H2 or Ar gas
10nm nc-Si dot
VHF (144MHz) Plasma Cell
Dispersion solution LB film
PC control
VHF Plasma CVD system (room temperature deposition)
100n m
nc-Si dot assembly technique
Hybrid Silicon Nanoelectronics ２ Nanocrystalline Si based New functional devices Collector 電子
Acceleration voltage 100V
Thin Au
50 nm
nc-Si layer
50nm
電流 (A/c m 2)
10-3
1
10-5
10-2
10-7
効率 (%)
Si substrate Al electrode
Diode voltage
10-4 ダイオード 放出電子
10-9
効率
10
0
20
10-6 30
引出電圧 (V)
BSD (ballistic electron surface emitting display) Bending SiO2 beam with Si nanodots
Nanodot flash memory
Si nanodots
G e-
Air gap S
e -
e -
e-
MOSFET channel
D
2μm
Nanoelectromechanical devices
Hybrid Silicon Nanoelectronics Vg2(V)
３ Quantum information devices based on nc-Si 15nm Source
Vg2 (V)
nc-Si dot 10 nm
0.04
15 nm
Vsd (V)
0.02 -8 0 -9 -0.02 -10 3.5
4
Vg1
0 -1
VVg1(V) (V) g1
T = 20K
3
1
-3 -4 -3 -2 -1 0 1 2 3 4
-7
-0.04
4.5
Anti-bonding
-2
Vg1 (V)
Observation of quantum-mechanical interaction between two nc-Si dots （ in collaboration with CU ） Current (A) (Log Scale)
30 nm
0.4 meV
Bonding
2
Drain
20 nm
Vg2
Initialization
Read-out
Control
5
Gate Voltage (V)
Single-electron charging effects
Design & fabrication of nc-Si quantum information devices for solid-state quantum computers
Hybrid Silicon Nanoelectronics ４ Multi-scale nc-Si material & device simulation Pseudopotential
Atomistic nanostructure DFT （ LCAO base ） simulation H = i − ∇ + V ( ρ ) j 2
i, j
2
eff
HOMO
2m
LUMO
Icosahedral structure SiND (d=1.56nm)
H Nanoscale quantum transport simulation
D Nonequilibrium Green’s function
[
G(E ) = E − H −
∑
(E)
]
−1
Nonequilibrium quantum transport through SiNR
Equilibrium distribution & linear response parameters
Mesoscale device ・ circuit simulation
Quantum device simulation （ DG method ） Hybrid circuit simulation
Ids (A)
D e n s ity ( c m -2 ) 2.0D 11
1.0D 11
Vg2 (V)
0.0D
0 .5
20
X (n m )
-.5
40 60
-1 .0
1 .0
0
k ( n m -1 )
Wigner distribution
Vg1 (V)
Quantum equivalent circuit modelling
Hybrid Silicon Nanoelectronics ５ High-k dielectric thin films for next generation ULSIs •
•HfO2
Pr-oxide/silicate Si-O-Si/H-O-H
HfO2 3.2 nm
equivalent thickness ~ 1.2 nm
界面層 0.8 nm 5 nm
Si基板
3.5 nm
Normalized Intensity[a.u.]
SiO2
Pr-O-Pr
Pr silicate formation
TOA 90° 52° 30° 15°
537
535
533
531
529
527
Binding Energy [eV]
Cross sectional TEM
XPS spectrum （ in collaboration with Musashi Tech.)
Purge gas
O2 gas
Material gas
Change in ellipsometric angle ∆ エリプソメトリ角Δの変化
Fabrication and characterization of high-k dielectric gate insulator 1 1サイクル cycle
∆ [deg]
167.5
HfO2/Si 約 1.1Å
165.5
Sample Heater
1 degree 1度
166.5
Ellipsometer
s 原料 3秒 パージ 酸素
20秒 s 40秒 s
164.5 Novel stacked memory 時間 100 100 秒 time sec 1950 2050 2150 2250 In-situ real-time spectroscopic ellipsometry study time [s] drai n