Nidhi > Em > Lecture_6_xe38emb-c

6. ANALOG-TO-DIGITAL AND DIGITAL-TO - ANALOG CONVERTERS principle of sampling and quantizing (sampling theorem, S/H circuit and its parameters) DACs - basic principle integrating ADCs (dual-slope integration, suppression of AC interference, U → f conversion, Σ − ∆) compensating ADCs (successive approximation, using, parameters) comparating ADCs (principle, using, parameters)

38EMB – P6

1

Principle of quantizing and sampling u

u 7 6 5 4 3 2 1 0

Quantization step (LSB) Min. error of conversion = ½ of the quantization step

t

t

TP TS

TP < TS

TP – conversion time (some converters require change of input during conversion less than ½ LSB) TS – sampling period; fS = 1/TS

Sampling (Shannon-Kotelnikov) theorem: í If a band-limited signal with maximum frequency fM (e.g. frequency of the highest harmonic component of periodical signal which cannot be disregarded) is sampled with sampling frequency fS, then if there is fS ≥ 2 fM, then the original signal can be completely reconstructed.

38EMB – P6

2

Sample-hold (S/H) circuit (some ADCs require that input voltage changes by less than ½ LSB during the conversion) S

R1

u1

+

uR

OZ

τ1 = R1C - as low as possible

u2

τ2 = Rin C – as high as possible RZ

C

In practice - special IOs

∆UU

u

u2(t)

Basic parameters of the S/H circuit:

tU – acquisition time for error equal ∆UU

∆UP

∆UP – change of S/H output in „hold“ during tP (droop rate: (∆UP)/tP )

tU u1(t) 0 0

tP

tS

t

HOLD Sample (track)

38EMB – P6

3

Digital-to-analog converters (DACs) Examples of 4-bit DAC R

LSB

MSB

+ 1

0

1

z3

0

1

Ur/4

R

1

U O = − R ∑ 2i I zi ; i =0

2R

2R z1

0

Ur

Ur/8

R

2R z2

0

I

2I

Ur/2

z3

z0 n −1

2R

2R

UO

0

z1

4I

R

1

0

z2

8I

Ur

1

0

1

z0 0

RO

38EMB – P6

RO n−1 i U O = −U r 2 zi ; ∑ 16 R i =0 zi = 0, 1

1

+ MSB

zi = 0, 1

LSB

UO 4

Analog-to-digital converters (ADCs) Integrating ADC a) dual-slope integration UX

ui1 P1

Integrator

R

ui2

VK

+

Ur

Series mode dist., (for T1 = k TDIST no influence)

ui1 UX' UX 0

C

T2' T1

T2

t

Ur 0

P2

t CL

CO

f

G

DC

UO UO'

u i 2(1)

1 1 U t U Xt ; = d = X ∫ RC RC

u i 2( 2) = U O −

1 1 U t U U rt d = − r O RC ∫ RC

Nulling of counter

ui2

N1

Ur

t

N2 T2 1 1 Ur U U = = U X T1 ; 0 = U O − U X T2 ; X r → N1 T1 RC RC Conversion time: tens of ms; Using: DMMs (modifications according to resolution)

UO =

38EMB – P6

5

Integrating ADC b)using U/f conversion Ur

R1

U1

t0

C U2i

R2

+

+

t0 + T

0

VK

T f2

I

Ur Ug UP

tP

u2i

PG

0

t

−

tP

1 1 U d t − − U P dt = 0 1 R1C T∫ R2 C t∫P

Measurement of voltage: f2

H

Cont

Decoder + display.

U 1T U P t P = R1 R2

R2 U 1 1 = f = 2 → T R1 U P t P

TN Measurement of integral of input voltage: f2 (N2)

Divider

Coun

. Decoder + display

Inst. output frequency: f2 = ∆N2 / ∆t, ∆t → 0 t2

t2

t2

t2

t1

t1

t1

t1

N 2 = ∑ ∆N 2 =∑ f 2 ∆t =∑ ku1∆t =& k ∫ u1dt ¨

Using: Digital wattmeters and watt-hour meters 38EMB – P6

6

Integrating ADC c) with Σ−∆ modulator R U1

fS

C

R

+

ui

+

NK

C Q

fS/N

DS

D

fS

TS t

ČF

a) U1= 0 ui

I

t One-bit DAC DS +Ur (1) (0) -Ur

T1

Charge balancing – total charge from input is equal To the charge from the 1-bit DAC

t

T2

b) U1= -Ur/2 ui

States for U1= 0 and for U1= - Ur /2 a) U1= 0 →

TS − TS 0 Ur = Ur = 0 2TS TS + TS

b) U1= - Ur /2 →

− 2TS TS − 3TS U Ur = Ur = − r TS + 3TS 4TS 2

t DS T1

38EMB – P6

T2

t 7

c) U1> 0 fS

TS

t

LSB

ui t

DS

t T1,1 T2,1 T1,2

T2,2

T1,3 T2,3

T1,8

T2,8

Digital filter evaluates occurences of log 0 a log 1 („mean value“) during N clock pulses Typical numbers of bits: 12 - 24 (according to over-sampling N) Typical conversion time: hundreds of ns to tens of µs (according to over-sampling N) Using: acoustic applications, AD modules of control computers, sensor signals digitization

38EMB – P6

8

Compensation ADC UX VK

CO

AR

Balancing algorithm: Successive approximation UČAP

MSB LSB UDAC

DAC

Ur

VR

Input voltage cannot change during conversion more than ADC resolution (i.e. voltage corresponding to the ½ LSB) Number of bits n:

12 - 14 (resolution Ur/2n)

Conversion time: tens of µs Using: AD modules of control computers, sensor signals digitization

38EMB – P6

3Ur/4 UX Ur/2 Ur/4 1

0

0

1

MSB

U UX = r 2

1

0 LSB

n −1

i 2 ∑ zi ; i =0

t

zi = 0, 1

1 0  38 1 0 0 1 + + = UX = Ur + + + Ur  2 4 8 16 32 64  64

9

Comparison ADC – parallel comparison (FLASH) Ur R/2 R ULSB

R

R

UX Typical bits number n: 8 (255 comparators)

VK1 VK2 VK3

Conversion time: 0,4 to 50 ns

Decoder m from k Binary output to binary

(higher sampling rate achieved by cyclic sampling of more converters)

k = 2n - 1

Using: Digital storage oscilloscope

VKk

R/2

Comparison ADC – series-parallel comparison Typical bit numbers n: 10 až 14 Conversion time: 10 ns až 1 µs

38EMB – P6

10