New

//module of D_FF module dff(q,qbar,d,clear,clk); output q,qbar; input d,clear,clk; wire s,sbar,r,rbar,cbar; assign cbar= ~clear; //create complement // of signal clear assign sbar= ~(s & rbar), //ff using 3 SR s= ~(sbar & cbar & ~clk), // Latches r= ~(s & rbar & ~clk), rbar= ~(r & cbar & d); assign q= ~(s & qbar), qbar= ~(q & cbar & r); endmodule // module of t_flipflop module tff(q,clk,clear); output q; input clk,clear; dff df(q, ,~q,clear,clk); endmodule // 4-bit counter using bottomup approach module counterbottomup(out,clk,clear); output [3:0]out; input clk,clear; tff tff0(out[0],clk,clear); //instantiate tff tff1(out[1],out[0],clear); //t_flipflops tff tff2(out[2],out[1],clear); tff tff3(out[3],out[2],clear); endmodule module tcounterb();//stimulus module reg clk,clear; wire [3:0]out;//4 bit output counterbottomup cbu(out,clk,clear); initial clear =1;s always #100 clear=!clear; initial clk=0; always #2 clk=!clk; endmodule

//ALU:

module alu(out,in1,in2,control); input [3:0] in1,in2; //define 4 bit inputs input [2:0] control; //define 3bit input control output [4:0] out; reg [4:0] out=0; //initialize 5bit output out always @ (in1,in2,control) case(control) 3'd0:out=in1; 3'd1:out=in1+in2; 3'd2:out=in1-in2; 3'd3:out=in1*in2; 3'd4:out=in1/in2; 3'd5:out=in1%4; 3'd6:out=in2%8; 3'd7:out=in1<
//Bcd to 7 Segment Double display module bcd(out,in,clk); input [3:0] in; //define 4 bit input in input clk; output [6:0] out; reg [6:0] out=0; //initialize 7 bit output out always @ (posedge clk) case(in) 4'd0:out=7'b1000000; 4'd1:out=7'b1111001; 4'd2:out=7'b0100100; 4'd3:out=7'b0110000; 4'd4:out=7'b0011001; 4'd5:out=7'b0010010; 4'd6:out=7'b0000010; 4'd7:out=7'b1111000; 4'd8:out=7'b0000000; 4'd9:out=7'b0011000; endcase

always @ (negedge clk) //o/p change at –ve case(in) //edge of clk pulse 4'd0:out=7'b1000000; 4'd1:out=7'b1111001; 4'd2:out=7'b0100100; 4'd3:out=7'b0110000; 4'd4:out=7'b0011001; 4'd5:out=7'b0010010; 4'd6:out=7'b0000010; 4'd7:out=7'b1111000; 4'd8:out=7'b0000000; 4'd9:out=7'b0011000; endcase endmodule module testbcd(); //stimulus module reg [3:0] in; reg clk; wire [6:0] out; bcd tbcd(out,in,clk); initial clk=0; always#2 clk=!clk; initial in=0; always#5 in=in+1; endmodule //Bcd to 7 Segment module bcd(out,in); input [3:0] in; //4-bit input output [6:0] out; //7-bit output reg [6:0] out=0; reg com; initial com=1; always @ (in) case(in) 4'd0:out=7'b1000000; 4'd1:out=7'b1111001; 4'd2:out=7'b0100100; 4'd3:out=7'b0110000; 4'd4:out=7'b0011001; 4'd5:out=7'b0010010; 4'd6:out=7'b0000010; 4'd7:out=7'b1111000; 4'd8:out=7'b0000000; 4'd9:out=7'b0011000; endcase endmodule module testbcd(); //stimulus module reg [3:0] in; wire [6:0] out; bcd tbcd(out,in); initial in=0; always #1 in=in+1; endmodule

//Mux module muxb(out,in1,in2); output out; input in1,in2; reg out; initial out=0; always begin #1 out=in1; #1 out=in2; end endmodule module testmb(); //stimulus module wire out; reg in1,in2; muxb a(out,in1,in2); initial in1=0; initial in2=1; endmodule //Mux with case statement module muxc(out,in0,in1,in2,in3,s0,s1); input in0,in1,in2,in3,s0,s1; output out; reg out; always @ (in0,in1,in2,in3) begin case({s0,s1}) 2'd0: out=in0; 2'd1: out=in1; 2'd2: out=in2; 2'd3: out=in3; endcase end endmodule module tmuxc(); //stimulus module reg in0,in1,in2,in3,s0,s1; wire out; muxc mux(out,in0,in1,in2,in3,s0,s1); initial in0=0; always #5 in0=!in0; initial in1=0; always #10 in1=!in1; initial in2=0; always #15 in2=!in2; initial in3=0; always #20 in3=!in3; initial s0=0; always #1 s0=!s0; initial s1=0; always #2 s1=!s1; endmodule

//Positive edge 8 bit UPDown counter

module counter(out,clk,reset,select); input clk,reset,select; output [7:0] out; reg [7:0] out=0; always @ (posedge clk) begin if (reset==0&&select==0) out=out+1; //up counter else if(reset==0&&select==1) out=out-1; //down counter else out=0; end endmodule module testc8(); //stimulus module wire [7:0] out; reg clk,reset,select; counter c8(out,clk,reset,select); initial clk=0; always #1 clk=!clk; initial begin reset=0; #5 reset=1; #10 reset=0; end initial begin select=0; #15 select=1; #20 select=0; end endmodule

//Negative edge 8 bit Up counter

module counter(out,clk); input clk; output [7:0] out; reg [7:0] out=0; always @ (negedge clk) //Negative edge out=out+1; // up counter endmodule module testc8(); //stimulus module wire [7:0] out; reg clk; counter c8(out,clk); initial clk=0; always #1 clk=!clk; endmodule //Positive edge 8 bit down counter

module counter(out,clk); input clk; output [7:0] out; reg [7:0] out=0; always @ (posedge clk) out=out-1; endmodule module testc8(); //stimulus module wire [7:0] out; reg clk; counter c8(out,clk); initial clk=0; always #1 clk=!clk; endmodule

//Positive edge 8 bit Upcounter

module counter(out,clk); input clk; output [7:0] out; //8-bit output reg [7:0] out=0; always @ (posedge clk) out=out+1; // up counter endmodule module testc8(); //stimulus module wire [7:0] out; reg clk; counter c8(out,clk); initial clk=0; always #1 clk=!clk; endmodule

//D_ff:

module dff(q,q0,d,clk,reset); input d,clk,reset; output q,q0; reg q,q0; always @(negedge clk) if (reset==0) begin q=d; q0=!d; end else begin q=0; q0=1; end endmodule

module tdff(); //stimulus module reg d,clk,reset; wire q,q0; dff dff0(q,q0,d,clk,reset); initial d=0; always #2 d=!d; initial clk=0; always #1 clk=!clk; initial reset=0; always #5 reset=!reset; endmodule //T_FF: module tff(q,q0,qt1,t,clk,reset); input t,clk,reset; output q,q0,qt1; reg q,q0,qt1; initial qt1=0; always @(negedge clk) begin if(t==0&&reset==0) begin q=qt1; q0=!q; end else if(t==1&&reset==0) begin q=!qt1; q0=!q; end else begin q=0; q0=1; end qt1=q; end endmodule module ttff(); reg t,clk,reset; wire q,q0,qt1; tff tff0(q,q0,qt1,t,clk,reset); initial clk=0; always #1 clk=!clk; initial t=0; always #2 t=!t;

initial reset=0; always #3 reset=!reset; endmodule

// traffic signals module traffic(Ra,Ya,Ga,Rb,Yb,Gb, Rc,Yc,Gc,Rd,Yd,Gd); output reg Ra,Ya,Ga,Rb,Yb,Gb,Rc, Yc,Gc,Rd,Yd,Gd; initial begin //initially all red lights ON Ra=1; Rb=1; Rc=1; Rd=1; Ya=0; Ga=0; Yb=0; Gb=0; Yc=0; Gc=0; Yd=0; Gd=0; end always begin Ra<=#1 0;#1 Ya= 1; Ya<=#1 0;#1 Ga= 1; Ga<=#10 0;#10 Ya=1; Ra<=#1 1;#1 Ya=0; Rb<=#0 0;#0 Yb=1; Yb<=#1 0;#1 Gb=1; Gb<=#10 0;#10 Yb=1; Rb<=#1 1;#1 Yb=0; Rc<=#0 0;#0 Yc=1; Yc<=#1 0;#1 Gc=1; Gc<=#10 0;#10 Yc=1; Rc<=#1 1;#1 Yc=0; Rd<=#0 0;#0 Yd=1; Yd<=#1 0;#1 Gd=1; Gd<=#10 0;#10 Yd=1; Rd<=#1 1;#1 Yd=0; end endmodule module testtraffic(); //stimulus module wire Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd; traffic t (Ra,Ya,Ga,Rb,Yb,Gb, Rc,Yc,Gc,Rd,Yd,Gd); endmodule

// traffic signals with control input module traffic(Ra,Ya,Ga,Rb,Yb,Gb, Rc,Yc,Gc,Rd,Yd,Gd,cont); Output reg Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd; input cont; initial begin //initially all red lights ON Ra=1; Rb=1; Rc=1; Rd=1; Ya=0; Ga=0; Yb=0; Gb=0; Yc=0; Gc=0; Yd=0; Gd=0; end always begin Ra<=#1 0;#1 Ya= 1; Ya<=#1 0;#1 Ga= 1; if(cont==0) begin Ga<=#10 0;#10 Ya=1; end if(cont==1) begin Ga<=#5 0;#5 Ya=1; end Ra<=#1 1;#1 Ya=0; Rb<=#0 0;#0 Yb=1; Yb<=#1 0;#1 Gb=1; if(cont==0) begin Gb<=#10 0;#10 Yb=1; end if(cont==1) begin Gb<=#5 0;#5 Yb=1; end Rb<=#1 1;#1 Yb=0; Rc<=#0 0;#0 Yc=1; Yc<=#1 0;#1 Gc=1;

if(cont==0) begin Gc<=#10 0;#10 Yc=1; end if(cont==1) begin Gc<=#5 0;#5 Yc=1; end Rc<=#1 1;#1 Yc=0; Rd<=#0 0;#0 Yd=1; Yd<=#1 0;#1 Gd=1; if(cont==0) begin Gd<=#10 0;#10 Yd=1; end if(cont==1) begin Gd<=#5 0;#5 Yd=1; end Rd<=#1 1;#1 Yd=0; end endmodule module testtraffic(); //stimulus module wire Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd; reg cont; traffic t(Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd,cont); initial cont=0; always #50 cont=!cont; endmodule