Net Delays

NET DELAYS

Interconnect Models 3. Lumped capacitance model 4. RC tree model 5. RLC tree model 6. Transmission line models (RC, LC, RLC) 7. RC / RLC Network model

Analysis of Simple RC Circuiti(t) R

R ⋅ i (t ) +v (t ) = vT (t ) d (Cv (t )) dv (t ) i (t ) = =C dt dt dv (t ) ⇒RC +v(t ) = vT (t ) dt state variable Input waveform

vT(t) ±

C

first-order linear differential equation with constant coefficients

v(t)

Analysis of Simple RC Circuit Zero-input response: (natural response)

Step-input response:

v0

v0u(t) v0(1-e-t/RC)u(t)

dv (t ) RC + v (t ) = 0 dt 1 dv(t) 1 −t =− ⇒v N (t) = Ke RC v(t) dt RC dv (t ) + v (t ) = v0u (t ) dt −t vF (t ) = v0u (t ) ⇒v (t ) = Ke RC + v0u (t )

RC

match initial state: v (0) = 0 ⇒ K + v0u (t ) = 0 output response for step-input:

v (t ) = v0 (1 −e

−t

RC

)u (t )

You can get the same result by Laplace Transform

Delays of Simple RC Circuit • v(t) = v0(1 - e-t/RC) -- waveform under step input v0u(t) • v(t)=0.5v0 ⇒ t = 0.7RC – i.e., delay = 0.7RC

(50% delay)

v(t)=0.1v0 ⇒ t = 0.1RC v(t)=0.9v0 ⇒ t = 2.3RC – i.e., rise time = 2.2RC (if defined as time from 10% to

Elmore Delay for RC Trees 

Definition   



H(t) = step response h(t) = impulse response = rate of change of H(t) T50%= median of h(t)

Elmore Delay [Elmore, 1948] ∞



TD = mean of h(t) = ∫ h(t) ⋅ t dt 0

Approximates the median of h(t) by the mean of h(t)  Computation: T (s , s ) = ∑ R ⋅ Cap(k) 

D

o

i

k

node k in src-to-sink path



s0 = source



si = sink



Rk = resistance at node k



Cap(k) = total of subtree rooted at k [Rubinstein et al, TCAD 1983]

Elmore delay of simple circuit Area A =  V , for some Elmore observed that the center of the area of the region under the curve (x(t) – y(t))’, would serve as a reasonable estimate of the 50% delay.

Elmore Delay… • First order time constant at node is a sum of RC components. • All the upstream resistances are taken into account. • Thus each node contributes to the delay. • Amount of contribution is the product of the cap at the node and the amount of resistance from source to the node.

Delay in distributed RC line • Elmore analyzed the distributed model and came up with the figures for delay.

Elmore Delay in a RC Tree: Example R 3 1

R1

2 4

1

C1

R2

C2

3

2

3

C3 R4

4

C4 Delay to node 3 = R1 (C1 + C 2 + C 3 + C 4 ) + R2 (C 2 + C 3 + C 4 ) + R3 C 3 Delay to node 4 = R1 (C1 + C2 + C3 + C4 ) + R2 (C2 + C3 + C4 ) + R4C4

Alternatively: Delay to node 3 = R1C1 + ( R1 + R2 )C 2 + ( R1 + R2 + R3 )C 3 + ( R1 + R2 )C 4 Delay to node 4 = R1C1 + ( R1 + R2 )C 2 + ( R1 + R2 )C 3 + ( R1 + R2 + R4 )C 4

Properties of Elmore Delay 

Advantages 







Simple closed-form expression − Useful for interconnect optimization Upper bound of 50% delay [Gupta et al, 97] − Actual delay asymptotically approaches Elmore delay as input signal rise time increases High fidelity [Boese et al., 93],[Cong-He,96] − Good solutions under Elmore delay are good solutions under actual (SPICE) delay

Disadvantages  

Low accuracy, no waveform information Inherently cannot handle inductance effect

Wire Model Assume: Wire modeled by N equal-length segments

For large values of N: