Nested Miller Compensation

Nested Miller Compensation

Need for high gain amplifiers

Cascode

I/O isloation wide BW high output resistance

high

gain large supply voltage ( > 5 V )

Cascading 3 or more stages

Modeling

NMC

(Nested Miller Compensation)

CC 2 CC1CC 2 2 1− s− s g m3 g m 2 g m3 AV ( s ) = A0  s  1 1 2 CC 2 C L   1 + 1 + sCC 2 ( − )+ s g m 2 g m3 g m 2 g m3   ω P1 

CC1 s gm3 AV = A0  s  1 1 2 (1 − g m 2 g m 3 ) CC 2C L   1 + 1 + sCC 2 ( − )+s g m 2 g m3 g m 2 g m3  ωP1   1+

For high freq poles to be LHP : gm3 > gm2 In power amplifiers we have so the effect of zeros can be neglected But in low power CMOS design, satisfying the preceding condition is not straightforward

Zeros of the transfer function Z1, 2

− g m 2  4 g m 3CC1 = 1 ± 1 + 2CC1  g m 2CC 2

LHP > RHP

   

NMCNR ( NMC with Nulling resistor)

to eliminate RHP zero, setRC

= 1 g m3

CC1 1+ s g m3 AV = A0  s  1 1 2 (1 − g m 2 g m 3 ) CC 2CL    1 +  1 + sCC 2 ( − )+ s g m 2 g m3 g m 2 gm3  ω P1  

ωz =

g m3

CC1

1+

s

ω x

+

s

2

2 ω xk

To avoid overshoot in the freq response , K (seperation factor) must be gr. than or eq. to 2 Setting K=2 and comparing the coeffs. in 2 quadratic polynomials , gives :

ωT ω x −1 ω T ϕ = 90° − tg ( ) + tg 2 1 − 0.5(ω T ω x ) ωZ −1

φB

Design Equations 1 − 0.5(ωT ω x ) tg (ϕ − φ B ) = ωT ω x

2

So, compensation capacitors were calculated !

CONDITIONS

CC 2 > 0 ⇒ GNm2 < 1 ⇒ g m3 > g m 2 g m 3 g m1 ωZ > ωT ⇒ < ⇒ g m 3 > g m1 CC1 CC1

DZPC (Double Pole-Zero Cancellation)

•S

Setting :

A0

Av = s 1+

ω P1

CONDITIONS Indeed, after pole-zero cancellation a parasitic pole remains

Making this pole much higher than GBW, yields

MNMC ( multi-path NMC)

• Assuming constraint gm3 >> gm1 , gm2 high freq. zeros can be neglected :

New LHP zero

• As seen

Our goal is to cancel out the second non-dominant pole by LHP zero. setting ωz=ωp2 , gives :

DISADVANTAGES 1. It is effective only when gm3 >> gm1 , gm2 2. Increase in power dissipation

3. Cc2 is very large :

Which greatly affects SR and area occupation

NGCC ( Nested Gm-C Compensation)

Zeros can be eliminated by setting gmf1=gm1 , gmf2=gm2

Design Equations

Main disadvantage : Extra circuitry

The Figure Of Merit

Transistor area Trade off Bias current

FOM expressions

Observations • Basic NMC always exhibits the lowest FOM • NGCC shows a FOM comparable to NMC for low values of GNm2 and is better than NMC only for higher values of GNm2 • The lower the value of GNm2 the higher the FOM • In contrast with the other cases, the FOM of NMCNR increases increasing GNm1

SPICE Simulation 0.35µ technology and a 2V supply

• All of the amplifiers were designed for a load capacitance of 100 pF and PM of 70 deg (except DZPC which is the only technique showing an inherent PM of 90 ̊ )

gm1 = 112  μA/V gm2 = 86.2  μA/V gm3 = 853   μA/V

Simulation Results

!!!

Click for Reason