My Report Completed Master Thesis
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LEIBNIZ UNIVERSITÄT HANNOVER INSTITUT FÜR ANTRIEBSSYSTEME UND LEISTUNGSELEKTRONIK FACHGEBIET LEISTUNGSELEKTRONIK ERARBEITUNG UND REALISIERUNG VON KONZEPTEN ZUR MEHRKANALMESSWERTERFASSUNG IN LEISTUNGSELEKTRONISCHEN GERÄTEN
MASTERARBEIT
PIPAT EUMTHURAPOT 2219560 ERSTPRÜFER:
PROF. DR.-ING AXEL MERTENS
ZWEITPRÜFER:
PROF. DR-ING. HABIL. BERND R. OSWALD
BETREUER:
DR.-ING MATTHIAS RICHTER, PILLER POWER SYSTEMS GMBH
BETREUER:
DIPL.-ING GUNTER WAKAN, PILLER POWER SYSTEMS GMBH
BETREUER:
DIPL.-ING NIKLAS RÜGER
Abstract
I
Abstract The main focus of power electronic applications in this work is on a UPS application. The power converters in a UPS system need to be controlled by a controller unit. For controlling the power converters, a measurement system is used to mention the signals and transmit the measured signals to a controller unit. The purpose of this work is to develop a concept of measurement system of three-phase voltages and three-phase currents that can improve the safety and reliability of data transmission in a UPS system. For improving the safety and reliability of data transmission through a noisy environment in a UPS system, the developed concept of measurement system transmits the measured data by a digital transmission method including an error control code. The digital part of the developed concept is physically implemented on a FPGA which is programmed by VHDL and uses the LVDS technology for data transmission. Keywords: measurement system, digital transmission, error control code
Contents
II
Contents Abstract..............................................................................................................................I Contents........................................................................................................................... II Abbreviations..................................................................................................................IV 1
Introduction ............................................................................................................. 1 1.1
2
3
Objectives and Requirements of this Work ............................................................ 3
1.1.1
Objectives ............................................................................................................................ 3
1.1.2
Requirements ....................................................................................................................... 3
1.2
Thesis Description...................................................................................................... 4
1.3
Characteristic of Voltages and Currents in the Measurement Points .................. 5
1.3.1
Approximated Voltages and Currents at the Measurement Points....................................... 6
1.3.2
Required Bandwidth ............................................................................................................ 8
1.3.3
The Result of Approximated Voltages and Currents at the Measurement Points ................ 9
Currently Used Measurement System ................................................................... 11 2.1
Voltage Measurement Path..................................................................................... 12
2.2
Current Measurement Path.................................................................................... 13
2.3
Disadvantages of the Currently Used Measurement System............................... 14
My Concept of Measurement System .................................................................... 16 3.1
Analog Part .............................................................................................................. 20
3.1.1
Sensor................................................................................................................................. 21
3.1.2
Signal Conditioning ........................................................................................................... 24
3.2
Digital Part ............................................................................................................... 25
3.2.1
Analog to Digital Conversion Section ............................................................................... 26
3.2.2
Digital Transmission Section ............................................................................................. 26
3.3
Error Control Codes................................................................................................ 28
3.3.1
Error correction.................................................................................................................. 29
3.3.2
Linear Block Codes............................................................................................................ 30
3.3.3
Hamming Code .................................................................................................................. 36
3.3.4
Performance of Error Correction Codes............................................................................. 38
3.4 3.4.1
3.5
Digital Line Codes ................................................................................................... 40 The Popular Line Codes..................................................................................................... 41
Data Transmission Technologies............................................................................ 42
3.5.1
Single-Ended vs. Differential............................................................................................. 43
3.5.2
LVDS Transmission........................................................................................................... 45
3.6
Transmission Mediums ........................................................................................... 46
3.7
My Concept .............................................................................................................. 50
Contents
4
Physical Implementation ....................................................................................... 52 4.1
ADC BOARD .................................................................................................................... 53
4.1.2
FPGA BOARD .................................................................................................................. 54
4.1.3
LVDS BOARD .................................................................................................................. 55
4.1.4
DAC BOARD .................................................................................................................... 55
4.1.5
DISPLAY-ERROR BOARD ............................................................................................. 56 Clock Control Generating .................................................................................................. 58
4.2.2
Data Loading...................................................................................................................... 59
4.2.3
Hamming Coding............................................................................................................... 60
4.2.4
NRZ Coding and Serializing.............................................................................................. 66
4.2.5
Simulation Results ............................................................................................................. 68
Experimental Results............................................................................................... 70
4.3.1
Laboratory Environment Testing ....................................................................................... 70
4.3.2
Operational Environment Testing ...................................................................................... 76
Conclusion and Future Considerations................................................................ 81 5.1
Conclusion ................................................................................................................ 81
5.2
Future Considerations............................................................................................. 82
Appendix................................................................................................................. 83 6.1
Appendix A............................................................................................................... 83
6.2
Appendix B............................................................................................................... 85
6.3
Appendix C............................................................................................................... 87
6.3.1
TOP_LEVEL.vhd .............................................................................................................. 87
6.3.2
CLK_DIVIDER.vhd .......................................................................................................... 91
6.3.3
LOADER_DATA.vhd ....................................................................................................... 92
6.3.4
ECC_EN.vhd ..................................................................................................................... 93
6.3.5
NRZ_EN.vhd ..................................................................................................................... 95
6.3.6
NRZ_DE.vhd ..................................................................................................................... 98
6.3.7
ECC_DE.vhd ................................................................................................................... 100
6.3.8
BIN_TO_SSEG.vhd......................................................................................................... 105
6.3.9
TB_TOP_LEVEL.vhd ..................................................................................................... 107
6.3.10
TB_ECC_DE.vhd ............................................................................................................ 110
6.4
7
FPGA Design............................................................................................................ 57
4.2.1
4.3
6
Test System............................................................................................................... 52
4.1.1
4.2
5
III
Appendix D............................................................................................................. 113
References ............................................................................................................ 114
Abbreviations
IV
Abbreviations AC
Alternating Current
ADC
Analog-to-Digital Converter
AM
Amplitude Modulation
ARQ
Automatic Retransmission Request
AWGN
Additive White Gaussian Noise
BER
Bit Error Rate
DC
Direct Current
DES
Deserializer
ECC
Error Control Code
EMI
Electromagnetic Interference
FEC
Forward Error Correcting
FPGA
Field Programmable Gate Array
GF
Galois Fields
IC
Integrated Circuit
ISI
Intersymbol Interference
LED
Light Emitting Diode
LSB
Least Significant Bit
LVDS
Low Voltage Differential Signaling
MSB
Most Significant Bit
NRZ
Never Return to Zero
PCB
Printed Circuit Board
PLL
Phase Locked Loop
PWM
Pulse-Width Modulation
RZ
Return to Zero
SEC-DED
Single-error correction and double-error detection
SER
Serializer
THD
Total Harmonic Distortion
UPS
Uninterruptible Power Supply
VHDL
Very-high-speed-integrated-circuit Hardware Description Language
XOR
Exclusive-OR
1 Introduction
1
1 Introduction An Uninterruptible Power Supply (UPS) is a system which provides uninterrupted, reliable and high-quality power for vital loads such as airline computer, life-support systems in hospitals and communication systems, among others. It, in fact, protects sensitive loads against power outages as well as over-voltage and under-voltage conditions.
Figure 1.1: Measurement systems in the UPS system
In UPS system as shown in Figure 1.1, the power is converted twice [1]. First it is converted from alternating current (AC) to direct current (DC) at the rectifier, and then it is converted back from DC to AC at the inverter. In power conversion, the purpose of an AC/DC rectifier in the UPS system is to produce DC voltage with quality sufficient for proper operation of the DC/AC inverter at the back end of the UPS system. The inverter is put in parallel to the mains delivered to the load. The inverter must then compensate for defects of the mains when present, and generate the sinusoidal output from the battery when AC-mains are absent.
1 Introduction
2
The power converters in the UPS system need to be controlled by a controller unit because the performance of UPS can be considerably improved if the current and voltage is effectively controlled. This is clear from the fact that to deliver a good AC power during emergency, the UPS systems that include the feedback controlled pulse-width modulation (PWM) inverter and L-C output filter have to convert a DC voltage source (battery) to a sinusoidal AC voltage with low steady state voltage error, low voltage total harmonic distortion (THD) and fast transient response under load disturbances. Furthermore, the good performance mention of the controller unit should be guaranteed under power pollution which leads to voltage distortion due to increasing applications of power converters or nonlinear loads in industry. As shown in Figure 1.1, the system between the measurement point and the controller unit is the measurement system, which is the objective of this work. The measurement system is a system which measures three-phase voltages and three-phase currents at the measurement points (the input of the rectifier and the output of the inverter) and transmits the measured signals to the controller unit. Voltage and current sensing in digitally controlled power converters in general requires sensing devices with galvanic isolation between the sensing point and the control electronics, transmission of measured signals through a noisy environment with high levels of Electromagnetic Interference (EMI) in UPS systems and appropriate analog-to-digital conversion for the controller unit.
1 Introduction
3
1.1 Objectives and Requirements of this Work 1.1.1 Objectives The measurement system of three-phase voltages and three-phase currents for a UPS system has to be developed. It has to provide a safe and reliable solution for data transmission and can be developed in a subsequent step. For a suitable concept, it should be defined and specified in functional units. The individual functional units should be developed in a Field Programmable Gate Array (FPGA) which is programmed in Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
1.1.2 Requirements •
Safe solution of data transmission through a noisy environment in a UPS system has to be created.
•
Six measurement channels for three-phase voltages and three-phase currents are considered as in one unit.
•
Voltage measurement with and without galvanic isolation.
•
Current measurement with galvanic isolation.
•
Digital information with 12-bit or 10-bit word length has to be presented in the range of 500 ns to 10 µs in a signal processing unit (microcontroller or FPGA).
•
Latency of the developed concept of the measurement system should be in the range of 1 µs.
•
Recurrent Interfaces should be defined.
The developed concept of the measurement system has to be considered in cost-effectiveness, data rate, noise immunity and reusability for different applications.
1 Introduction
4
1.2 Thesis Description A UPS system is an application that requires controlling the power converters. For controlling the power converters, i.e. rectifier and inverter, the measurement system is used to mention the signals and transmit the measured signals to the controller unit. The developed concept of measurement system in this work is a measurement system with galvanic isolation. The galvanic isolation is a complete physical separation between the high power circuit and the electronic circuit. It is needed to protect the measurement system from potentially damaging high power signals and to eliminate ground loops between the high power circuit and the electronic circuit. In the developed concept of the measurement system, the accuracy measured value, the latency of system, the safety and reliability of data transmission and the cost effectiveness of the system are the important parameters that need to be considered. This thesis report is organized as follows. Chapter 1 will show the introduction of this work, including the characteristic of voltages and currents in the measurement point. Chapter 2 will roughly explain the currently used measurement system and show some disadvantages of it. Chapter 3 will present my concept of the measurement system, which can solve the disadvantages of the currently used measurement system and also achieve the requirements of this work, including explanation of electronics devices and digital processing methods which are used in my concept, i.e. voltage and current sensors, signal conditioning circuits, digital transmission system, digital line codes, error control codes, data transmission technologies and transmission mediums. Next, Chapter 4 will implement the digital part of my concept of measurement system to the test system and show the simulation results and the experimental results of it. Finally, Chapter 5 concludes and discusses this work.
1 Introduction
5
1.3 Characteristic of Voltages and Currents in the Measurement Points For the three-phase voltages and currents measurement, the voltage and current must be approximated in a general mathematical model. An example of the worst case of the voltages and currents at the measurement point is shown in Figure 1.2. They are the voltage and current at the output of inverter with L-C filter. The signals are not the pure sinusoidal waveform [2]. The signals contain several harmonic components caused by the switching of the inverter.
(a)
(b) Figure 1.2: Examples of the input signals (a) voltage (b) current
As seen in Figure 1.2, the shapes of the voltage and current waveforms are a combination of a high-frequency triangular waveform and a low-frequency sine waveform. The voltages and currents at the measurement points can be closely approximated by amplitude modulation (AM) where the carrier signal of AM is a low-frequency sine wave and the modulating signal is a high-frequency triangular wave. The approximated voltages and currents at the measurement points are shown in Figure 1.3.
1 Introduction
6
Figure 1.3: Approximated input signals
1.3.1 Approximated Voltages and Currents at the Measurement Points As shown in Figure 1.3, the voltages and currents at the measurement points can be closely approximated by AM where the carrier signal of AM is a low-frequency sine wave and the modulating signal is a high-frequency triangular wave. Carrier signal is a sine wave vc (t) = Ac sin (ωc t) where Ac
=
amplitude of carrier signal For Voltage
Ac = 325 V
For Current
Ac = 250 A
(1.1)
1 Introduction
7
ωc
=
angular frequency of carrier signal, ωc = 2πf c
fc
=
frequency of carrier signal in Hertz, f c = [40 Hz … 60 Hz]
t
=
time in second.
Modulating signal is a triangular wave Description in Fourier series ∞
v s (t ) = ∑ (a n cos(nωt ) + bn sin(nωt ))
(1.2)
n =1
an = bn =
1
π 1
π
2π
∫ v(t ) cos(n ω t ) d(ω t )
(1.3)
0
2π
∫ v(t ) sin(n ω t ) d(ω t )
(1.4)
0
The triangular wave is a waveform with quarter-cycle symmetry, only the odd harmonics with sine components will appear. ∞
v s (t ) = As ∑ bn sin(nω s t )
(1.5)
n =1
bn = bn =
4
π
2π
∫ v(t ) sin(nω t ) d(ω t ) s
s
⎧(−1) ( n −1) / 2 , n = odd 8 × ⎨ , n = even π 2n2 ⎩ 0
where As
=
(1.6)
0
amplitude of modulating signal For Voltage
As = 50 V
For Current
As = 80 A
n
=
order n of the harmonic of ω s
ωs
=
angular frequency of modulating signal, ω s = 2πf s
fs
=
frequency of modulating signal in Hertz, f s ≤ 25 kHz
t
=
time in second
(1.7)
1 Introduction
8
Amplitude Modulated signal
The mathematical model of the approximated signal is given by = [ Ac + v s (t )]sin(ω c t )
vam (t )
∞ ⎡ ⎤ = ⎢ Ac + As ∑ bn sin(nω s t )⎥ sin(ω c t ) n =1 ⎣ ⎦
(1.8)
1.3.2 Required Bandwidth For signal measurement, the specified frequency range or the required bandwidth of the input signal is an important parameter. In practice, it is impossible to measure the signals with all harmonic components because the bandwidth of measurement system will be infinity. For resolving the question of how much bandwidth is required for acceptable measurement quality, it can be determined by calculating the magnitude of harmonics. The approximated signal, as shown in Figure 1.3, is the amplitude modulated signal combined by the carrier signal, which is a low-frequency sine wave, and the modulating signal, which is a high-frequency triangular wave. The fundamental frequency of the modulating signal is 25 kHz. From equation (1.5), the acceptable harmonics of the modulating signal are the harmonics which have a magnitude more than 0.1 % of the fundamental frequency magnitude.
bn =
8 π n2 2
b b33 = 12 = 0.00092 × b1 33
(1.9)
The equation (1.9) shows the magnitude of the 33rd harmonic of the modulating signal is below than 0.1 % of the fundamental frequency magnitude. Therefore, the required bandwidth is up to the 33rd harmonic of the modulating signal. The frequency of the 33rd harmonic of the modulating signal is 33 × 25 kHz = 825 kHz. Therefore, the required bandwidth of the approximated signal is 825 kHz
1 Introduction
9
1.3.3 The Result of Approximated Voltages and Currents at the Measurement Points As discussed above, the three-phase voltages and currents at the measurement points can be approximated by amplitude modulation. This section shows the mathematical models of the approximated three-phase voltages and currents which are identified at V _ X , I _ X by X is the order of phase {1, 2, 3}.
Three-Phase Voltages
V _ 1 ,V _ 2 ,V _ 3 From equation (1.8), the voltage at the measurement points is expressed by ∞ ⎡ ⎤ V _ X = ⎢ Ac + As ∑ bn sin(nω s t )⎥ sin(ω c t ) n =1 ⎣ ⎦
(1.10)
where
Ac
=
amplitude of carrier signal
Ac = 325 V
As
=
amplitude of modulating signal
As = 50 V
ωc
=
angular frequency of carrier signal
ω c = 2πf c
fc
=
frequency of carrier signal in Hertz
f c = [40Hz…60Hz]
n
=
order n of the harmonic of ω s
ωs
=
angular frequency of modulating signal
ω s = 2πf s
fs
=
frequency of modulating signal in Hertz
f s ≤ 25 kHz
t
=
time in second
bn =
⎧(−1) ( n −1) / 2 , n = odd 8 × ⎨ , n = even π 2n2 ⎩ 0
The required bandwidth is 825 kHz.
Three-Phase Currents
I _ 1, I _ 2 , I _ 3 From equation (1.8), the current at the measurement points is expressed by
1 Introduction
10
∞ ⎡ ⎤ I _ X = ⎢ Ac + As ∑ bn sin( nω s t )⎥ sin(ω c t ) n =1 ⎣ ⎦
(1.11)
where
Ac
=
amplitude of carrier signal
Ac = 250 A
As
=
amplitude of modulating signal
As = 80 A
ωc
=
angular frequency of carrier signal
ω c = 2πf c
fc
=
frequency of carrier signal in Hertz
f c = [40Hz…60Hz]
n
=
order n of the harmonic of ω s
ωs
=
angular frequency of modulating signal
ω s = 2πf s
fs
=
frequency of modulating signal in Hertz
f s ≤ 25 kHz
t
=
time in second
bn =
⎧(−1) ( n −1) / 2 , n = odd 8 × ⎨ , n = even π 2n2 ⎩ 0
The required bandwidth is 825 kHz.
2 Currently Used Measurement System
11
2 Currently Used Measurement System Currently, Piller Power Systems GmbH is using the currently used measurement system in its own UPS systems. The block diagram of the currently used measurement system is shown in Figure 2.1.
Figure 2.1: Block Diagram of the Currently Used Measurement System
The Figure 2.1 shows that the currently used measurement system senses the three-phase voltages and three-phase currents at the measurement points in BOARD_1 and transmits the analog sensed signals over a transmission medium to BOARD_2, which consists of signal conditioning circuits, analog-to-digital converters (ADC), a digital signal processing unit (DSP) and a random access memory (RAM). The BOARD_2 is a part of the currently used measurement system which is in the controller unit of the UPS system. It receives the analog sensed signals from BOARD_1, converts the received signals to digital data, processes the digital data and interfaces them to the signal processing unit in the controller unit. The currently used measurement system can be divided in 2 main paths: the voltage measurement path, which measures the three-phase voltages, and the current measurement path, which measures the three-phase currents.
2 Currently Used Measurement System
12
2.1 Voltage Measurement Path The block diagram of the voltage measurement path in the currently used measurement system is shown in Figure 2.2.
Figure 2.2: Block diagram of the Voltage Measurement Path in the Currently Used Measurement System
As shown in Figure 2.2, BOARD_1 consists of a resistor network, which acts like resistive voltage sensors sensing the three-phase voltages at the measurement point. Then, the analog sensed voltage signals are transmitted through the transmission medium, which is a flexible flat cable, from BOARD_1 to BOARD_2. BOARD_2 consists of a signal conditioning circuit, ADC, DSP and RAM. The signal conditioning circuit receives the analog sensed signals from BOARD_1. The objective of the signal conditioning circuit is to adjust the magnitude of signals to the required characteristics preparing to convert analog to digital. The ADC receives the analog conditioned signals and converts them to the digital serial data stream. Then the converted serial data stream is transmitted to the DSP and RAM which convert the serial data stream to the parallel data and interface the
2 Currently Used Measurement System
13
converted parallel data to the signal processing unit in the controller unit of the UPS system.
2.2 Current Measurement Path The current measurement path measures the three-phase currents at the measurement point. In the currently used measurement system, the current sensors in BOARD_1 are transformers. The block diagram of the current measurement path in the currently used measurement system is shown in Figure 2.3.
Figure 2.3: Block diagram of the Current Measurement Path in the Currently Used Measurement System
As shown in Figure 2.3, the current measurement path is used in the similar way as the voltage measurement path except that the sensors in BOARD_1 are transformers and the analog current mode transmission between BOARD_1 and BOARD_2.
2 Currently Used Measurement System
14
2.3 Disadvantages of the Currently Used Measurement System The currently used measurement system, which is used in the UPS system, can measure the three-phase voltages and the three-phase currents with acceptable accuracy. However, the currently used measurement system has disadvantages which may cause a damage of the measurement system and a measurement error.
•
The voltage measurement in the currently used measurement system is not galvanically isolated. The lack of isolation can cause a damage of the measurement system.
•
The transmitted signals in the measurement system may be influenced external sources because the measurement system operates in the UPS system, which is a noisy environment. The influence of noise on the signal transmission can be a source of measurement error. The signal transmission in the currently used measurement system can be divided structurally into two sections:
o Transmission Medium
The currently used measurement system uses an unshielded flat cable as transmission medium, which carries the analog signals from BOARD_1 to BOARD_2. The signals being transmitted over the unshielded flat cable may be easily influenced by crosstalk and the external noise produced by electromagnetic fields.
o Transmission Type
In the currently used measurement system, the signals are transmitted in analog form. This is an analog transmission method. The disadvantage of analog transmission is shown in Figure 2.4.
2 Currently Used Measurement System
R’
15
L’ C’
R’
dx
Figure 2.4: The Disadvantages of Analog Transmission
The Figure 2.4 shows the disadvantages of analog transmission. The analog signal is being transmitted through the transmission medium. The analog transmitted signal may be influenced by external sources. And the transmission medium is a typical circuit with distributed parameters. The parasitic parameters in the transmission medium can cause signal attenuation and crosstalk on the analog transmitted signal. These effects can result in the received signals. They can cause a measurement error. In the next chapter, we will discuss the developed concept of the measurement system which can improve the safety of the data transmission and can overcome the disadvantages of the currently used measurement system.
3 My Concept of Measurement System
16
3 My Concept of Measurement System From the requirements of this work and the discussed disadvantages of the currently used measurement system, this chapter presents the developed concept of the measurement system which can improve the safety of data transmission and can overcome the disadvantages of the currently used measurement system. For improving the safety and reliability of the transmission system through a noisy environment in a UPS system, my developed concept of the measurement system uses a digital transmission method to transmit the sensed signals to the controller unit. The main disadvantage of the currently used measurement system is the low level of safety of data transmission due to analog transmission. The analog transmission method introduces sources of measurement error, as discussed above. The digital transmission method has several advantages comparing with the analog transmission method. It can improve the level of safety of data transmission through a noisy environment in a UPS system.
Advantages of Digital transmission
•
Digital transmission is less susceptible to noise problems than analog transmission
In analog transmission the objective is to transmit a waveform, which is a function that varies continuously with time. The function of time must be reproduced exactly at the output of the analog transmission. In practice, a transmission medium does not satisfy this condition, so degree of distortion is unavoidable. The digital transmission is a transmission system, which transmits digital information that is a given symbol in finite set. Binary digital transmission, for example, the objective is to transmit either a ‘0’ or a ‘1’ from transmitter to receiver. This can be done by transmitting positive voltage to convey a ‘1’ and ground voltage to convey a ‘0’. The positive and ground pluses that were transmitted can undergo a great degree of distortion. The system will operate correctly as long as the receiver can determine whether the original voltage was positive or ground.
3 My Concept of Measurement System
•
17
Control of quality
Another difference between analog and digital transmission deals with the hardware’s ability to recover the transmitted signal. Digital transmission, it uses only 1’s and 0’s to encode the signal, can incorporate error detecting and error correcting information to the signal being transmitted. Error Control codes can be encoded with transmitted data in transmitter. The results of encoding are called codewords, which are contained data and redundant checking bits. The receiver can detect and correct the transmitted data by using the redundant checking bits. The objective of Error Control codes is to reduce the chances of errors in transmission.
Transmitter
Receiver
Transmission Medium 1
0
0
1
0
Error Control Coding 1
0
0
0
0
ERROR Received Signal
Transmitted Signal
1
0
0
1
0
CORRECTED Decoded Signal
Figure 3.1: The Advantages of Digital Transmission
The Figure 3.1 shows the advantages of digital transmission. The transmitter transmits the digital information through the transmission medium by transmitting ground voltage, when a digital data is ‘0’ and positive voltage, when a digital data is ‘1’. The receiver receives the transmitted digital data, which may be distorted by the characteristic of transmission medium and/or external noises. However, the receiver will only determine whether the original voltage was positive or ground, and reproduces to the symbol ‘1’ or ‘0’. Sometimes in practice, the power of noises is greater the power of transmitted signals. The receiver may be receiving the error data. But, the digital transmission can incorporate Error Control Codes to detect and correct the error in received digital data. Because of the discussed advantages of the digital transmission method, the digital transmission can improve the level of safety of data transmission and overcome the disadvantages of the currently used measurement system. Consequently, my concept of the measurement system uses the digital transmission method to transmit the signal
3 My Concept of Measurement System
18
between BOARD_1 and BOARD_2. The overview of my concept of the measurement
Interface To Controller Unit
Receiver
Driver
system is shown in Figure 3.2.
Figure 3.2: Block diagram of my concept of measurement system
As shown in Figure 3.2, BOARD_1 is a circuit board at the measurement point in the UPS system, which senses the three-phase voltages and three-phase currents at the measurement point and drives the sensed signals into the transmission medium. BOARD_2 is a part of the measurement system in the controller unit of the UPS system, which acts like a receiver. It receives the measured signals from the transmission medium, processes the received signals and interfaces the processed signals to the signal processing unit in the controller unit. The data transmission in my concept of the measurement system transmits digital data in serial transmission from BOARD_1 to BOARD_2. Serial transmission is the process of transmitting a single stream of data over a transmission medium, which can reduce the cost of the transmission medium, the driver and the receiver components. As seen in Figure 3.2, my concept of the measurement system can be divided into two parts: the analog part and the digital part.
3 My Concept of Measurement System
19
Analog Part
The analog part of my concept of the measurement system is a part that carries the analog signals before they convert to digital signals. The analog part consists of two sections: the sensing section and signal conditioning section.
•
Sensing Section: Sensor is a device that monitors the signal and/or transduces a
signal from a physical form to a corresponding signal.
•
Signal Conditioning Section: Signal conditioning circuit is a circuit which
manipulates an analog signal waveform into a more useful or required size to prepare of analog-to-digital converting.
Digital Part
The digital part is a part which carries the digital signals after the sensed analog signals converted to the digital signals, including the analog to digital converters. The digital part consists of two sections: the analog to digital conversion section and the digital transmission section.
•
Analog to Digital Conversion Section: Analog to digital conversion section is
a section, which is between analog and digital signals. The objective of it is to convert input analog signals to output digital data.
•
Digital Transmission Section: Digital transmission section is a section which
transmits the converted digital data from the ADC to the signal processing unit in the controller unit of UPS systems. Digital transmission section consists of: o Signal Processing Unit_1: Signal Processing Unit_1 is a processing
unit, for my concept it is a FPGA, in BOARD_1 which controls and receives the digital output signals from the ADC, then processes the digital signals. In the Signal Processing Unit_1 the processes are to encode error control codes increasing safety level in data transmission, to serialize the encoded data and to modulate the series data with a digital
3 My Concept of Measurement System
20
line code. Then it provides the processed signals to the Data Transmission Unit. o Data Transmission Unit: Data Transmission Unit is a unit which
consists of a driver, a transmission medium and a receiver. The driver in BOARD_1 transmits the processed signals with serial transmission over the transmission medium to the receiver in BOARD_2. o Signal Processing Unit_2: Signal Processing Unit_2 is a processing
unit, FPGA, in BOARD_2, which receives the digital signals from the Data Transmission Unit, then processes the received digital signals. The processes in Signal Processing Unit_2 are to demodulate the received signals, to deserialize the received data, to decode error control codes (detecting and/or correcting error) and to interface the decoded signals to the signal processing unit in the controller unit of UPS systems. In practice, the Signal Processing Unit_2 is a part of the function of the signal processing unit in the controller unit of UPS systems.
3.1 Analog Part The analog part in my concept of the measurement system is shown in Figure 3.3. BOARD_1 Analog Part
Voltage, Current
Galvanic Isolation
Measurement Point
Sensor
Input of Rectifier Output of Inverter
Signal Conditionting
Op-Amp Circuits
Filter
To Input of ADC
Voltage offset
V_1, V_2, V_3 (t)
VSEN_1, VSEN_2, VSEN_3 (t)
VADC_1, VADC_2, VADC_3 (t)
I_1, I_2, I_3 (t)
ISEN_1, ISEN_2, ISEN_3 (t)
IADC_1, IADC_2, IADC_3 (t)
Figure 3.3: Analog Part
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The analog part consists of sensors, which sense the voltage and current signals at the measurement point, and signal conditioning circuits, which manipulate the sensed signals from sensors into the required size signals of the inputs of ADC.
3.1.1 Sensor For voltage and current measurement, sensors are devices that monitor the signal at the measurement point and/or transduce the signal from a physical form to a corresponding signal. The considered sensors in this work are the sensors with galvanic isolation [6], [7]. The galvanic isolation is a complete physical separation between the high power circuit and the electronic circuit. It is needed to protect the measurement system from potentially damaging high power signals and to eliminate ground loops between the high power circuit and the electronic circuit. Sensors with galvanic isolation are the sensors that provide isolator between power stage at the measurement point and sensing devices of the measurement system. For measuring current and voltage signals, there are three technologies that are typically used:
•
Resistive sensing
•
Transformer sensing
•
Hall Effect sensing
3.1.1.1 Resistive sensing
Figure 3.4: Resistive sensing
Current Resistive Sensing
Vmea = I M × R
Voltage Resistive Sensing
Vmea = VM × (
R1 ) R1 + Rs
(3.1) (3.2)
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Resistive sensor can sense current and voltage in both AC and DC form by using Ohm’s Law as shown in equations (3.1) and (3.2). Resistive sensor is a sensor which is high accuracy, low cost, easily understood and used, and can use in high frequency range. However, the shortcomings are its insertion loss (heating) and lack of isolation.
3.1.1.2 Transformer Sensing
Figure 3.5: Transformer sensing
Current Transformer Sensing
Np IM = I mea N s
(3.3)
Voltage Transformer Sensing
VM Vmea = Ns Np
(3.4)
Transformers can be used to sense current and voltage in only AC form. Transformers are relatively simple to implement and are passive devices that do not require external power. The primary current will generate a magnetic field that is coupled into a secondary coil by Faraday’s Law. Their construction is simple but they do not allow the measurement of DC signals. Isolation between primary and secondary side is implicitly given.
3.1.1.3 Hall Effect Sensing The Hall Effect sensors are based on the Hall Effect that is generated by Lorentz force, which act on charges moving through a magnetic filed and produces a proportional voltage output when the magnetic flux jumps through the gap. Because Hall Effect sensors measure the magnetic field strength in close proximity to the current conductor, they can be separated by a few millimeters from the current signal, providing several kilovolts of isolation.
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A Hall Effect sensor has many advantages. It can be measured in large frequency range with high accuracy. However, it has also shortcoming. It is an active device that requires external power and its cost is relatively expensive. Hall Effect sensors have 2 types, Open-Loop and Closed-Loop Hall Effect sensors [5].
•
Open-Loop Hall Effect sensors: Open-Loop transducers use the simplest
implementation of the Hall Effect. The magnetic flux created by the primary current is concentrated in a magnetic circuit and measured in the air gap using a Hall device. The output from the Hall device is then signal conditioned to provide an exact representation of the primary current at the output.
•
Closed-Loop Hall Effect sensors: The magnetic flux created by the primary
current is balanced by a complementary flux produced by driving a current through the secondary windings. A Hall device and associated electronic circuit are used to generate the secondary (compensating) current that is an exact representation of the primary current. Open-Loop Hall Effect sensors have a more limited range of linearity and cannot compensate for offset and residual field errors. But, the cost of Open-Loop type is cheaper when compared with Closed-Loop type. Closed-Loop Hall Effect sensors can provide excellent accuracy. Open-Loop and Closed-Loop Hall Effect sensors are current sensors. They can sense in both AC and DC form. However, Closed-Loop Hall Effect sensors can also sense AC and DC voltage when combined with a resistor.
Figure 3.6: Hall Effect sensors
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For this information, a summary of the different types of sensors has been compiled in the Table 3.1.
Table 3.1: Comparison table of sensors
Sensors
Insertion Loss
Circuit Isolation
External Power
Frequency Range
DC Sensing
Estimated Accuracy
Cost
Resistive
Yes
None
None
>500 kHz
Yes
>99%
Low
Transformer
Yes
Yes
None
>400Hz
No
>95%
High
Hall Effect Open-loop Closed-loop
None None
Yes Yes
Yes Yes
>20 kHz >150 kHz
Yes Yes
90-95% >95%
Med High
For sensing three-phase voltages and three-phase currents at the measurement point, the sensors require galvanic isolation to protect the measurement system. Although the Close-Loop Hall Effect sensors can sense current and voltage in both AC and DC form with galvanic isolation in very good accuracy, the cost of Closed-Loop Hall Effect sensor is extremely expensive comparing with others. For sensing the AC voltages, the combination of the resistive divider and the transformer sensor is used in my concept. The resistive divider provides a good accuracy but its problem is lack of isolation. The transformer can be used to solve the problem of lack of isolation. The disadvantage of this sensor is that it can not sense DC Voltage because of using transformer. Therefore, the Close-Loop Hall Effect Sensors are used, if DC voltage measurement with galvanic isolation at the battery in the UPS system is required. For sensing the current in my concept, the Open-Loop Hall Effect sensor can be used to sense both AC and DC current.
3.1.2 Signal Conditioning The signal conditioning circuit in my concept is a circuit which manipulates the sensed signals from the sensors into the required size of the inputs of ADC. The design of signal conditioning circuits is depended on the sensed signals and the required signals of the inputs of the ADC. In practice, the signal conditioning circuits are created by
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operational amplifier (Op-amp) circuits. The design of signal conditioning can be seen in [8]. In my concept of measurement system, the focus of our discussion is on the safety of data transmission which is in the digital part. In the analog part, we have already discussed the sensors and the signal conditioning circuits. Therefore, the analog part will not be further discussed in this work.
3.2 Digital Part The block diagram of the digital part in my concept of measurement system is shown in Figure 3.7. The digital part is a part which carries digital signals. The digital part consists of two sections: the analog to digital conversion section, which converts the analog conditioned signals to the digital signals, and the digital transmission section, which transmits the digital converted data from BOARD_1, through a noisy environment in the UPS system, to BOARD_2. VDATA_1, VDATA_1, VDATA_1 [11:0] IDATA_1, IDATA_1, IDATA_1 [11:0]
TX
Parallel Digital Data
Serial Digital Data
BOARD_1 Digtial Part
Signal Processing Unit_1
ADC
VADC_1, VADC_1, VADC_1 (t) IADC_1, IADC_1, IADC_1 (t)
Driver
Transmission Medium BOARD_2
Signal Processing Unit_2
Interface To Controller Unit
Receiver
Parallel Digital Data
Serial Digital Data
VINF_1, VINF_1, VINF_1 [11:0] IINF_1, IINF_1, IINF_1 [11:0]
RX
Figure 3.7: Digital Part
Data Transmission Unit
AnalogSignals from Signal Conditioning
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3.2.1 Analog to Digital Conversion Section The analog to digital conversion section is a section which is between analog and digital signals. This section consists of six analog to digital converters (ADC). One ADC converts one data channel. ADC is a device that converts input analog signal to output digital data. The architecture of ADC can be seen in [9]. From the sampling theory, for anti-aliasing effect, the sampling rate of ADC must be higher than twice of the maximum frequency of the analog input ( f sampling = 2 f max ). Because the required
bandwidth of the approximated measuring signals in equation (1.10) and (1.11) is 825 kHz, therefore the sampling rate of the selected ADC must be higher than 1.65 MHz. The block diagram of analog to digital conversion section is shown in Figure 3.8.
Figure 3.8: Analog to Digital Converter (ADC)
The digital output signals of ADCs ( VDATA _ 1[11 : 0] , VDATA _ 2[11 : 0] , V DATA _ 3[11 : 0] , I DATA _ 1[11 : 0] , I DATA _ 2[11 : 0] , I DATA _ 3[11 : 0] ) are the parallel converted data of
72 bits, 12 bits per one data channel. These digital signals are sent to the digital transmission section.
3.2.2 Digital Transmission Section As discussed above, the digital transmission method has many advantages than analog transmission method, especially higher level of the safety of data transmission. The
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digital transmission section is a section which transmits the converted digital signals from ADC in BOARD_1 to the signal processing unit in the controller unit of the UPS system in BOARD_2. In Figure 3.7, after the analog to digital section converted the conditioned signals to the digital signals, the Signal Processing Unit_1 in BOARD_1 receives the converted data, processes them and transmits the processed signals to the Data Transmission Unit. Then the Signal Processing Unit_2 in BOARD_2 receives the transmitted signals from the Data Transmission unit, reprocesses the received signals and interfaces the reprocessed signals to the controller unit of the USP system. The Signal Processing Unit_1 acts like a transmitter of the digital transmission section and, consequently, the Signal Processing Unit_2 acts like a receiver of the digital transmission section. Therefore, the digital transmission section can express in the block diagram, as shown in Figure 3.9.
Source
Error Protection
Transmission Waveform Gerneration
Error Control Encoder
Driver (Modulator)
(Error Control Codes)
(Digital Line Codes)
RECEIVER
Sink
Error Control Decoder
Data Transmission
TRANSMITTER
Receiver (Demodulator)
Figure 3.9: Digital Transmission System
As shown in Figure 3.9, the processes in digital transmission consist of 2 processes: the error control coding process and the digital line coding process. These processes are explained in the next sub-chapters.
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3.3 Error Control Codes The digital transmission method can reduce errors generated during data transmission, yet the probability of errors was not eliminated. Error control coding is in digital transmission aiming to reduce the chances of error, which are caused by the effects of transmission channel noise and external sources. There are 2 methods of error control coding in digital transmission: •
Error detection or Automatic Repeat Request (ARQ): Error detection employs
only error detection and no attempt to correct any received data in error is made. It detects error in receiver by adding redundancy to data before they transmitted in transmitter and it is requested that the received data in error by retransmitted.
Figure 3.10: ARQ System
•
Error correction or Forward Error Correction (FEC): Error correction is a
one-way communication system. It employs error correcting code. It detects and automatically corrects bit errors in the receiver by adding redundancy to data before they transmitted.
Figure 3.11: FEC System
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The advantage of ARQ over FEC is that error detection requires much simpler decoding-system than error correction because the ARQ is only error a detection system which does not need correct the errors. But, when the channel error rate is high, retransmissions must be sent too frequently and the system throughput rate is lowered by the ARQ. Due to the requirement of no more than 1 µs latency, the retransmissions of ARQ system result in wastage of bandwidth and make a large latency in the transmission system. By this reason, the ARQ system is not useful for my concept. The ARQ will not be discussed any further in this work. The focus of our discussion is on the Error correction coding.
3.3.1 Error correction Error correcting codes are broadly classified in two categories, Block Codes and Convolutional Codes [10]. The encoder for block codes takes a message block of k information symbols represented by a k-tuple X = ( X 0 , X 1 ,..., X k −1 ) and transforms each message E independently into an n-tuple E = ( E 0 , E1 ,..., E n −1 ) of discrete symbols called a codeword, where (k
X and generates an n-tuple codeword E , however the generated codeword E at the time of encoding depends not only on the current k symbol message, but also on m previous message blocks. The fundamental difference between block codes and convolutional codes is that in block coding a finite length of output codeword is generated for all input message words of finite length whereas input and output symbol sequences are infinite in convolutional coding. Another important aspect is the introduction of memory element in convolutional codes.
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Figure 3.12: Classification of Error Correcting Codes
It is difficult to implement convolutional code which operates at the high data rate applications, including this measurement system. Block codes are capable of correction multiple bit-errors with the low overhead constraint. The focus of this work is on the block codes.
3.3.2 Linear Block Codes
E = X ⋅G
S = D⋅HT
Figure 3.13: Linear Block Codec Process Diagram
In block coding, this binary information sequence is segmented into message blocks of fixed length; each message block, X , consists of k information digits. There are a total of 2 k distinct messages. The encoder transforms each input message, X , into a binary n-digits, E , with n>k, using a particular algebraic algorithm (generator matrix G ). The binary n-digits, E , is referred to as the codeword of the message
3 My Concept of Measurement System During the transmitter transmits the transmitted codeword
31
E
over a
transmission medium to the receiver, the receiver receives the received codeword D from a transmission medium. On the receiving end, the decoder applies an inverse of the algebraic algorithm (parity check matrix H ) to identify and correct any errors caused by channel corruption.
3.3.2.1 The Generator Matrix Because an ( n, k ) linear code C is a k-dimensional subspace of the vector space En of all the binary n-digits, it is possible to find k linearly independent codewords, g0, g1, …, gk-1, in C such that every codeword E in C is a linear combination of these k
codewords; that is, E
E
E
=
X ⋅G
⎡ g0 ⎤ ⎢ g ⎥ = ( x0 , x1 ,K, x k −1 ) ⋅ ⎢ 1 ⎥ ⎢ M ⎥ ⎢ ⎥ ⎣ g k −1 ⎦ = x0 g 0 + x1 g1 + L + x k −1 g k −1
(3.5)
where X = ( x 0 , x1 , K, x k −1 ) is the message to be encoded, xi = 0 or 1 for 0 ≤ i < k , and G is the generator matrix of linear block codes. A property for a linear block code to
possess is the systematic structure of the codeword, as shown in Figure 3.13, in which a codeword is divided into two parts, the message part and the redundant checking part. The message part consists of k unaltered information digits, and the redundant checking part consists of n-k parity-check digits, which are linear sums of the information digits. A linear systematic ( n, k ) code is completely specified by a k × n matrix G of the following form:
⎡ g0 ⎤ ⎡ g00 g01 ⎢g ⎥ ⎢g g11 10 G=⎢ 1 ⎥ =⎢ ⎢ M ⎥ ⎢ M M ⎢ ⎥ ⎢ ⎣gk−1⎦ ⎣gk −1,0 gk −1,1
⎡ ⎤ L g0,n−1 ⎤ p01 L p0,n−k −1 1 0 L 0⎥ ⎢ p00 ⎢ p L g1.n−1 ⎥⎥ p11 L p1.n−k −1 0 1 L 0⎥ 10 ⎥ = [P Ik ] = ⎢ O M ⎥ M O M M M O M ⎥ (3.6) ⎢ M ⎥ ⎢p L gk −1,n−1⎦ L p p 0 0 L 1⎥ ⎢ k −1,0 k−1p,1 matrix k −1,n−k −1 identiy matrix k×k⎥ ⎣ ⎦
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where I k is the k × k identity matrix and P is a k × (n − k ) matrix which generates parity symbols. The P matrix is generated by generator polynomial whose coefficients are elements of Galois Field [11] [12],denoted by GF (2 m ) . The generator polynomial and GF (2 m ) are presented in Appendix A. The encoding operation is E = X ⋅ G = X [P
I k ] = [X ⋅ P
X]
(3.7)
The codeword is divided into two parts: the part X consists of the message symbols, and the part X ⋅ P consists of the parity check symbols.
3.3.2.2 The Parity Check Matrix For any k × n matrix G , there exists an (n − k ) × n matrix H with n − k linearly independent rows such that any vector in the row space of G is orthogonal to the rows of H , and any vector that is orthogonal to the rows of H is in the row space of G .
G ⋅ H T = 0.
(3.8)
Hence, we can describe the (n, k ) linear code C generated by G in an alternative way as follows: An n-digit E is a codeword in the code C generated by G only if E ⋅ H T = 0 . The matrix H is called a parity-check matrix of the code. If the generator matrix is in the systematic form of (3.6), the parity-check matrix is the following form: ⎡ ⎡ h0 ⎤ ⎢1 0 ⎢ h ⎥ ⎢0 1 H = ⎢ 1 ⎥ = I n-k P T = ⎢ ⎢ M ⎥ ⎢M M ⎢ ⎥ ⎢0 1 ⎣hn − k −1 ⎦ ⎢⎣ identity
[
]
L L O L
matrix
where P T is the transpose of the matrix P .
0 0 M 0
p 00 p 01 M p 0,n − k −1
⎤ p k −1, 0 ⎥ p k −1,1 ⎥ ⎥ M O M ⎥ p1, n − k −1 L p k −1,n − k −1 ⎥ ⎥⎦ p matrix p10 p11
L L
(3.9)
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3.3.2.3 The Minimum Distance of Block Codes The minimum distance of a code is the minimum Hamming distance between any two different codewords. Any two distinct codewords of C ( n, k ) differ in at least d min locations. Let E and W be two different codewords n-digits. The Hamming distance between E and W , denoted d ( E ,W ) , is defined as the number of places where they differ. Given a block code C, one can compute the Hamming distance between any distinct codewords. The minimum distance of C, denoted by d min , is defined as d min = min{d ( E , W ) : E , W ∈ C , E ≠ W }
(3.10)
The minimum Hamming distance d min is a very important parameter when comparing the theoretical performance of different codes because it determines the random error detecting and random error correcting capabilities of code.
3.3.2.4 Syndrome and Error Detection Given the parity-check matrix H , it is possible to check whether the received word D is a valid codeword or not. Let E = (E 0 , E1 , K , E n −1 ) be a codeword that was transmitted over a noisy channel. Let D = (D0 , D1 , K , Dn −1 ) be the received vector at the output of the channel. Because of the channel noise, a codeword D may be different from a received vector E . The vector sum of the received is defined as D =E +e
(3.11)
The vector e = (e0 , e1 ,K, en −1 ) is the error vector caused by the channel noise. Of course, the receiver does not know either E or e . On receiving D , the decoder must first determine whether D contains transmission errors. S = D⋅HT S = (E + e ) ⋅ H T
(3.12)
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The vector S = ( S 0 , S1 ,K, S n − k −1 ) is called the syndrome of D . Then, S = 0 if and only if D is a codeword, and S ≠ 0 if and only if D is not a codeword. Therefore, when S ≠ 0 , we know that D is not a codeword and the presence of errors has been detected. When S = 0 , D is a codeword, and the receiver accepts D at the transmitted codeword. It is possible that the errors in certain error vectors are not detectable, D contains errors but S = D ⋅ H T = 0 . This happens when the error vector e is identical to a nonzero codewords. In this event, D is the sum of two codewords, which is a codeword, and consequently D ⋅ H T = 0 . Error vectors of this kind are called undetectable error vector.
3.3.2.5 Error Detecting Capability of a Block Code When a codeword E is transmitted over a noisy channel, an error pattern of l errors will result in a received vector D that differs from the transmitted codeword E in l places i.e. [ d ( E,D) = l ]. The detector observes the received word D and declares an error event if S ≠ 0 . This process is called error detection. If the minimum distance of a block code C ( n, k ) is d min , any two distinct codewords of C differ in at least d min places. For this code C, no error pattern of d min − 1 or fewer errors can change one codeword into another. Therefore, an error pattern of ( l ≤ d min − 1 ) errors will for sure result in a received word D that is not a codeword. Hence, a block code with minimum distance d min is capable of detecting all the error patterns of d min − 1 or fewer errors. An error pattern of d min errors is undetectable because there exits at least one pair of codewords that differ in d min places, and there is an error pattern of d min errors that will carry one into another. The same argument applies to error patterns of more than d min errors. For this reason we say that the random-error-detecting capability of a block code with minimum distance d min is d min − 1 . There are 2 k − 1 error patterns, which alters the transmitted codeword E into another codeword W . These 2 k − 1 error patterns are undetectable and the decoder accepts W as the transmitted codeword. The decoder is then said to have committed a decoder error. However, there are 2 n − 2 k error-patterns are detectable error patterns.
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For large n , 2 k − 1 is much smaller and only a small fraction of error patterns pass through the decoder being undetected.
3.3.2.6 Error Correcting Capability of a Block Code For a C ( n, k ) block code with minimum distance d min the random error correcting capability can be determined as follows 2t + 1 ≤ d min ≤ 2t + 2
(3.13)
Next, we show that the code C is capable of correcting all the error patterns of t or fewer errors. Let E and D be the transmitted codeword and the received vector, respectively. Let W be any other codeword in C. the Hamming distances among E , D and W satisfy the triangle inequality:
d ( E , D) + d (W , D) ≥ d ( E ,W )
(3.14)
Suppose that an error pattern of t´ errors occurs during the transmission of E . Then, the received vector D differs from E in t´ places, and therefore d ( E , D) = t´ . Because E and W are codewords in C, we have d ( E , W ) ≥ d min ≥ 2t + 1
(3.15)
Combining (3.14) and (3.15) and using the fact that d ( E , D) = t´ , we obtain the following inequality:
d (W , D) ≥ 2t + 1 − t´ , where t´≤ t d (W , D) ≥ t Consider the C(7,4) code with d min = 3 From (3.15), we have t =( d min − 1 )/2 = 1 since d min is odd and let
E D
= =
[ 1 1 0 1 0 0 0 ] [ 0 1 0 1 0 0 0 ]
(3.16)
3 My Concept of Measurement System
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=
36
[ 1 1 1 0 0 1 0 ]
d ( E , D) = 1 and d (W , D) = 4 and 4 > 1. From (3.16) we conclude that if an error pattern of t or fewer errors occur, the received word D is closer to the transmitted codeword E than to any other codeword W in C in the Hamming distance sense. For all error patterns with l errors such that l > t , there exists at least one case where the received word D is closer to an incorrect codeword W than the transmitted codeword E . To show this, let E and W be two codewords in C such that d ( E , W ) = d min .
Let e 1 and e 2 be two errors patterns that satisfy the following condition: e1 + e 2 = E + W where e1 and e 2 do not have non zero components in common places. Consider the C(7,4) code with d min = 3 E e1 e2 D = E + e1 W
= = = =
[ [ [ [
1 0 0 1
1 0 0 1
0 1 0 1
1 1 0 0
0 0 0 0
0 0 1 0
0 0 0 0
] ] ] ]
= [ 1 1 1 0 0 1 0 ]
d ( E , D) = 2 and d (W , D) = 1. In this case the decoder will select W as the transmitted codeword instead of E . We conclude stating that, a block code with minimum distance
d min guarantees correcting all the error patterns of t = ⎣(d min − 1) / 2⎦ or fewer errors, where ⎣(d min − 1) / 2⎦ denotes the largest integer no grater than (d min − 1) / 2 . The parameter t is called the random-error-correcting capability of the code. A t -error correcting linear block code C ( n, k ) is capable of correcting a total of 2 ( n− k ) error patterns, including those with t or fewer errors.
3.3.3 Hamming Code Error correcting coding increases reliability of a transmission system but it also decreases system efficiency. A number of redundant bits and a number of encoding and decoding clock cycles sacrifices transmission system bandwidth. There are many codes of block codes, e.g., Hamming codes, cyclic codes, BCH, and Reed Solomon. A
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Hamming code [10] can correct the presence of single bit errors in a transmitted codeword. The advantages of Hamming code are that it easily implements in FPGA by using a look up table or XOR calculators and it uses a few clock cycles to encode and decode. By these reasons, this work will focus on Hamming codes. Hamming codes have the following parameters: Code length:
n = 2m − 1
Number of information symbols:
k = 2m − m − 1
Number of parity-check symbols:
n−k = m, m ≥ 3
Error-correcting capability:
t = 1 , ( d min = 3).
The parity-check matrix H of this code consists of all the nonzero m-tuples as its columns. In systematic form, the columns of H are arranged in the following form:
H = [I m
Q ] , where I m is an m × m identity matrix, and the sub matrix Q consists of
2 m − m − 1 columns that are the m -tuples. The columns of Q may be arranged in any order without affecting the distance property and weight distribution of the code.
[
In systematic form, the generator matrix of the code is G = Q T
]
I 2 m - m -1 ,
where Q T is the transpose of Q , and I 2 m - m - 1 is a (2 m − m − 1) × (2 m − m − 1) identity matrix. The parity-check matrix can be used to generate parity-check bits during the process of encoding and to generate bits indicating the presence and location of errors, syndrome bits, during the decoding process.
3.3.3.1 Shortened Hamming Codes Hamming codes have only a limited range of values of length n and dimension k, and the available value may not suit the system. Shortening a code means reducing the number of information bits, keeping the number of parity checks the same. The length n and the dimension k are thus reduced by the same amount. The way in which this is done is to set one of the information bits permanently to zero and then remove that bit from the code.
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We may delete any l columns from the parity-check matrix H of a Hamming code. The deletion results in a m × (2 m − l − 1) matrix H´. Using H´ as a parity-check matrix, we obtain a shortened Hamming code with the following parameter: Code length:
n = 2m − l − 1
Number of information symbols:
k = 2m − m − l − 1
Number of parity-check symbols:
n−k = m
Error-correcting capability:
t = 1 for d min ≥ 3
A Hamming code is shortened it by deleting columns from H, we would then have created a code with even d min . If we delete columns from H properly, we may obtain a
d min = 4. For example, if we delete from the submatrix Q all the columns of even weight, we obtain a m × (2 m − l − 1) matrix. The distance-4 shortened Hamming codes, also called single-error correction and double-error detection (SEC-DED) codes [13], can be used for correcting all error patterns of single error and simultaneously detecting all error patterns of double errors. When a single error occurs during the transmission of a code vector, the resultant syndrome is nonzero, and it contains an odd number of 1’s. However, when double errors occur, the syndrome is also nonzero, but it contains an even number of 1’s. Based on these facts, decoding can be accomplished as follows: •
If the syndrome S is zero, we assume that no error occurred.
•
If S is nonzero and contains an odd number of 1’s, we assume that a single error occurred. The error pattern of a single error that corresponds to S is added to the received vector for error correction.
•
If S is nonzero and it contains an even number of 1’s, an uncorrectable error pattern has been detected.
3.3.4 Performance of Error Correction Codes Suppose we are using a t-error correcting code and subjecting the decoder to a probability of random bit error rate p . As shown in Figure 3.14, the data transmission system, i.e., modulation, channel, and detector can be described in additive white
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Gaussian noise channel (AWGN) and binary symmetric channel (BSC) [11]. The probability of random bit error rate p , also called crossover probability, can be computed based on the system parameters,
⎛ 2 Eb p = Q⎜ ⎜ N 0 ⎝
⎞ ⎟ ⎟ ⎠
(3.17)
where Q(x) is the Q function (Gaussian distribution), the quantity Eb / N 0 is the ratio of energy per bit to noise power spectral density or frequently called the bit signal to noise ratio (SNR)
Figure 3.14: Codeword transmission and Binary Symmetric Channel
Probability of the symbol error rate Puncoded for the symbol which consist of l bits is given by Puncoded = 1 − (1 − p ) l
(3.18)
Probability of a block decoding error Pcoded for the block code which consist of n bits is given by
Pcoded =
n
⎛ n⎞
∑ ⎜⎜ i ⎟⎟ p (1 − p) ⎝ ⎠
i =t +1
i
n −i
(3.19)
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n ⎛ n⎞ from ∑ ⎜⎜ ⎟⎟ p i (1 − p) n −i = 1 i =0 ⎝ i ⎠
t ⎛ n⎞ Pcoded = 1 − ∑ ⎜⎜ ⎟⎟ p i (1 − p) n −i i =0 ⎝ i ⎠
(3.20)
⎛ n⎞ n! and t is error correcting capability of the block code. Where ⎜⎜ ⎟⎟ = ⎝ i ⎠ i!(n − i )!
3.4 Digital Line Codes As shown in Figure 3.9, the digital line coding or digital modulation is used in digital communication between the transmitter and the receiver. When binary data is transmitted over a channel, it must be sent via some analog format that can encode the individual 0’s and 1’s of which it is comprised. This algorithm is called a line code. There are many different types of line codes, which differ of their complexity, efficiency and reliability. This part will present some line codes that frequently use in many digital transmissions. The following are some of the desirable properties of a line code [3]: •
Self–Synchronization: There is enough timing information built into the code
so that bit synchronizers can extract the timing or clock signal. A long series of binary 1’s or 0’s should not cause a problem in time recovery •
Low Probability of Bit Error: Receivers can be designed that will recover the
binary data with a low probability of bit error when the input data is corrupted by noise. •
A Spectrum that is Suitable for the Channel: In some cases DC component
should be avoided, e.g. of the channel has a DC blocking capacitance. In addition, the signal bandwidth needs to be sufficiently small compared to the channel bandwidth. •
Transmission Bandwidth: This should be as small as possible
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3.4.1 The Popular Line Codes
Figure 3.15: Line Codes
•
Non Return to Zero (NRZ): As shown in Figure 3.15, the rule of NRZ is to
send a positive voltage, when a digital data is ‘1’ and to send a ground voltage, when a digital data is ‘0’. The NRZ line code has the advantage of require the minimum bandwidth and simplest to implement but it has the disadvantage of lacking clocking information for receiver synchronization that make it cannot transit if there is a long string of identical ‘0’ or ‘1’. •
Return to Zero (RZ): The RZ code, as shown in Figure 3.15, transits from a
ground voltage to a positive voltage at start of interval and then transit from a positive or negative voltage to a ground voltage at middle of interval, when a digital data is ‘1’ and sends a ground voltage, when a digital data is ‘0’. For the problem of transmitting a long string of ‘0’ or ‘1’ in NRZ. The RZ can be fixed the problem with long string of ‘1’ but if there is a long string of ‘0’, it still is a problem. The RZ still has disadvantages of a long string of ‘0’ and lacking clocking information for receiver synchronization. •
Manchester: The rule of Manchester code is to transit from a ground voltage to
a positive voltage in middle of interval, when a digital data is ‘1’ and to transit from a positive voltage to a ground voltage in middle of interval, when a digital data is ‘0’.
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For the problems of NRZ, the Manchester line code has the advantage of having the property that they contain clocking information which may be extracted by the receiver and solving the problem of transmitting a long string of ‘0’ or ‘1’. However, it has the disadvantage of requiring twice the bandwidth of the NRZ code because the pulses are half the width. In the context of digital line coding, it is clear that the Manchester digital line code will be the safest for data transmission. However, Manchester code requires a painfully high bandwidth. Because of the signal processing unit performance, data transmission bandwidth, cable bandwidth limitation and the latency of 1 µs in the requirement of this work, the digital transmission system cannot be implemented Manchester code. My concept of the measurement system will use the NRZ code in the digital line coding process.
3.5 Data Transmission Technologies Nowadays, there are several methods and technologies to transmit digital data over a transmission channel. The Figure 3.16 shows the speed and distance coverage of some familiar data transmission choices.
Figure 3.16: Approximate Signaling Rates vs. Transmission Distance for Various Interfaces
As seen in Figure 3.16, signaling rate eventually decreases as transmission distance increases. This section shows single-ended data transmission systems (as employed in BTL, GTL, GTLP, TIA/EIA–232, etc.) and differential transmission systems (as used
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with TIA/EIA-422, TIA/EIA-485, TIA/EIA–644 (LVDS), etc.). Each method of transmission has benefits and disadvantages.
3.5.1 Single-Ended vs. Differential The Figure 3.17 shows the circuit schematic diagram of a single-ended transmission system and a differential transmission system.
(a) Single-Ended
(b) Differential
Figure 3.17: Circuit Schematic Diagram (a) Single-Ended Interface, (b)Differential Interface
Single-Ended Transmission: Single-ended transmission is performed by using one
signal line for each information channel and a common ground return path shared among numerous information channels. The Figure 3.17 (a) shows the electrical schematic diagram of a single-ended transmission system. Single-ended receivers interpret the logical state at their inputs based upon the voltage at the single input line with respect to ground. The advantages of single-ended transmission are simplicity and low cost of implementation. A single-ended system requires only one line per signal. It is therefore ideal when cabling and connector costs are more important than the signaling rate or transmission distance. The main disadvantage of the single-ended solution is its relatively poor noise performance at high signaling rates or long distances. Because the noise coupled to the circuit adds to the signal voltage, it is susceptible to data errors.
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Differential Transmission: Differential transmission addresses many of the
shortcomings of single-ended solutions by using a pair of signal lines for each information channel. The Figure 3.17 (b) shows an electrical schematic diagram of a differential transmission system. The differential driver uses a pair of complementary outputs to indicate the state transmitted. The differential receiver detects the voltage difference between the signal pair, rather than relative to ground, to determine its output state. This mode of transmission has several important advantages over single ended. We can see the fundamental advantage in the derivation of the differential input voltage, V ID , in Figure 3.17(b). The noise sources V N and VG add to the input signals VIA and VIB , just as with the single-ended circuit, but by taking the difference between the two
input voltages at the receiver, the common noise terms are cancelled from the desired signal. The differential receiver accomplishes this and, with small differential input voltage thresholds, maintains high signal-to-noise ratios.
Table 3.2: Comparison between Single-Ended and Differential Signaling
Criterion Speed Susceptibility to radiated EMI Radiation of EMI Cost Common-mode voltage range Power consumption
Single Ended Low to moderate High High Low Low Moderate to high
Differential Moderate to high Low Low to moderate Moderate Low to high Low to moderate
In this context, it is clear that the differential transmission has many advantages, including help to reduce noise during data transmission and eliminate the EMI problems.
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3.5.2 LVDS Transmission A popular type of differential transmission technologies is Low-Voltage Differential Signaling (LVDS) [14], [15]. LVDS is a differential transmission technology which delivers high data rate while consuming significantly less power than another transmission technology. LVDS works by switching current from a current source through a differential line pair. The current loop is completed by placing a 100Ω termination resistor across the differential line pair. The resistor creates a voltage swing across the input ports of LVDS receiver.
Figure 3.18: Simplified diagram of LVDS Driver and receiver
As discussed in the section above, the differential transmission can improve the safety of transmitting data through noisy environment. LVDS is a differential signaling technology which has many advantages, such as high speed, low power, low cost, and enhanced noise immunity. However, LVDS also has some disadvantage of Transmission distance and Transmission option. Because of its high speed and low voltage, LVDS is not suitable for long distance transmission (< 10 meters), and LVDS is suitable for point to point transmission because it is a current switching standard. The disadvantages of LVDS are not likely to be important for the measurement system because the transmission distance between BOARD_1 and BOARD_2 of measurement system is in a range of 3 to 10 meters and they are point to point transmission. For these reasons, LVDS is used in the data transmission part in my concept of the measurement system.
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3.6 Transmission Mediums For transmitting digital information along mediums (or channels), the digital signals can be transmitted in electrical cables, e.g. flat cables, twisted pair cables, coaxial cable, and in optical cables, e.g. optical fiber. The optical cables can transmit the digital signals in the higher data rate and longer distance than electrical cables, but the important drawback of optical fiber is the cost. The optical transmission system is substantially more expensive than electrical transmission system. Because of the reasons of cost-effectiveness of the transmission system, this work will focus to discuss on transmission of digital information through electrical cables. The fiber optic will not be discussed any further in this work. An electrical cable is a typical circuit with distributed parameters [16]. It can be explained by the classical equivalent circuit in Figure 3.19.
R’
L’ C’
R’
dx
Figure 3.19: Classical equivalent circuit of electrical cable
The electromagnetic properties of them are completely determined by parasitic parameters that include the resistance R and the inductive L of the conductors, and the capacitance C and the conductivities G of the insulator. The parameters R and G characterize the energy loss; the resistance R characterizes the heat loss in the wire and the conductivity G characterizes the loss in the insulator. The parameters L and C determine the reactivity of the transmission medium regarded as its frequency properties. The parasitic parameters of an electrical cable, as shown in Figure 3.19, may affect cable signal integrity. The effects of an electrical cable happening more frequently are Attenuation, Crosstalk, Delay skew and Interference from external sources of electromagnetic radiation.
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Figure 3.20: The effects of electrical cables
•
Attenuation: Attenuation is defined as the difference between the levels of the
signal at the transmitter outlet and the receiver inlet, due to loss energy in cable. •
Crosstalk: Since part of the energy of a signal being transmitted through one
transmission medium is converted into electromagnetic radiation that induces currents in neighboring transmission medium. This effect is called crosstalk. Crosstalk superimposed on a signal plays the role of noise. •
Delay skew: In data transmission, frequently, consisting of several transmission
mediums, each of the transmission mediums is characterized by its own time of signal transition from the transmitter to the receiver. •
Interference from external sources of electromagnetic radiation: The signals
being transmitted over the transmission medium can cause interference induced by external sources of electromagnetic radiation. Electromagnetic Interference (EMI) is caused by undesirable radiated electromagnetic. Low frequencies and high amplitudes are characteristic of interferences of this kind.
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For data transmission, the trace of using electrical transmission medium has 2 types, coaxial cables and twisted pair. The transmission systems based on coaxial cables have higher cost, in comparison with the transmission system based on twisted pairs. Twisted pair cabling is a common form of wiring in which two conductors is wound around each other for the purposes of canceling out electromagnetic which can cause crosstalk.
Figure 3.21: Twisted pair cabling
And in LVDS transmission, the quality and type of cable used for LVDS signals is crucial for reducing noise on the LVDS transmission line. For balanced data transmission in LVDS, twisted-pair cable is recommended since it provides two identical conductors to transmit the signal and its complement. Any distortion affects both conductors equally. Therefore, the differential signal does not change. The twisted pair cables come as shielded and unshielded types depending on whether the individual twisted pairs or core have an auxiliary shielding cover or not. Such classification makes it possible to define four main cable product types, i.e., along with unshielded cables (UTP), cables with an overall outer shield (S/UTP), with shields for each pair (STP), and with simultaneous shielding of both the pairs and core (S/STP). Shielding is basically used to increase the parameters crosstalk attenuation, reduce the electromagnetic emission level, and increase the noise immunity.
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Figure 3.22: The types of twisted pair
Table 3.3: Comparison the types of shielded twisted pair
a b
c d
Shield Unshielded Twisted pair (UTP) Shielding of each pair (STP)
Shielding results • Decreased EMI factor • Increased protection from external noises • Increased Crosstalk attenuation Common shield for all pair (S/UTP) • Decreased EMI factor • Increased protection from external noises Shielding of each pair + • Decreased EMI factor outer shield around all pairs (S/STP) • Increased protection from external noises • Increased Crosstalk attenuation • Increased mechanical reliability
Based on the above information, a twisted pair cable is a suitable transmission medium for my concept. And it is clear that a shielded twisted pair can increase the parameters crosstalk attenuation and reduce the electromagnetic emission level. However, the shielding cost is relatively expensive.
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3.7 My Concept The above sections showed the information of sensors, signal conditioning circuits, ADCs, the digital transmission method, error control codes, digital line codes, data transmission technologies and transmission mediums. Based on this information, the block diagram of my concept of the measurement system is shown in Figure 3.23.
DIGITAL PART
ANALOG PART Analog voltage signals
RESISTIVE DIVIDER AND ISOLATED
VSEN_1 VSEN_2 VSEN_3
VADC_1 VADC_2 VADC_3
DATA TRANSMISSION
VDATA_1[11:0] VDATA_2[11:0] VDATA_3[11:0]
THE SERIALIZED DATA STREAM OF 1 CHANNEL TRANSMITS IN ONE TRANSMISSION CHANNEL (6 TRANSMISSION CHANNELS)
SIGNAL PROCESSING UNIT_1
BOARD_1
3 channels
Digital parallel signals 12 bits per channel
SIGNALS CONDITIONING
TRNSFORMER
6X ADCs
OPEN-LOOP SIGNALS HALL EFFECT 3 channels CONDITIONING SENSORS
ERROR CORRECTING HAMMING ENCODER
SIGNAL PROCESSING UNIT_2
TWISTED PAIR
ERROR CORRECTING HAMMING DECODER
TWISTED PAIR TWISTED PAIR TWISTED PAIR TWISTED PAIR
SERIALIZER AND NRZ ENCODER
BOARD_2
72 bits
DESERIALIZER AND NRZ DETECTOR
TWISTED PAIR
CONTROLLER UNIT
3 PHASES VOLTAGE
Analog Voltage Conditioned Signals
INTERFACE TO
V_1 V_2 V_3
Analog Voltage Sensed Signals
6 X LVDS Receivers
Required BW 825 kHz
6 X LVDS Line Drivers
Amplitude range [-375V ... +375V]
3 PHASES CURRENT I_1 I_2 I_3
ISEN_1 ISEN_2 ISEN_3
Analog current signals Amplitude range [-330A ... +330A]
Analog Voltage Sensed Signals
IADC_1 IADC_2 IADC_3 Analog Voltage Conditioned Signals
IDATA_1[11:0] IDATA_2[11:0] IDATA_3[11:0]
TX 1 ... 6
Differential Signaling
RX 1 ... 6
Digital parallel signals 12 bits per channel
INF_DATA Digital parallel signals 72 bits 12 bits per channel
Required BW 825 kHz
Figure 3.23: Block Diagram of my concept
As shown in Figure 3.23, my concept of the measurement system consists of six measurement channels for measuring the three-phase voltages and the three-phase currents. In BOARD_1, the three-phase voltages are sensed by the three voltage sensors (the combination of the resistive divider and the transformer sensors) and the three-phase currents are sensed by the three current sensors (Open-loop Hall Effect sensors). Then the six sensed signals are conditioned and converted to the six 12-bit parallel digital data words by the signal conditioning circuits and the ADCs. The six converted digital data words are processed in the Signal Processing Unit_1, which is a
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FPGA. The processes of the Signal Processing Unit_1 are the Hamming encoding process and the serializing in NRZ code process. The output codewords of Signal Processing Unit_1 are the six serial bit streams. At this point, the six serial bit streams are driven into the twisted pair cables by the six LVDS drivers. In BOARD_2, the six LVDS receivers receive the six transmitted bit streams from the twisted pair cables. Then the six received bit streams are processed in the Signal Processing Unit_2, which also is a FPGA. The processes of Signal Processing Unit_2 are the deserializing process and the Hamming decoding process. The serial transmission of my concept of the measurement system transmits the serialized data stream in the six channels. The six channels carry the measured data of the three-phase voltages and the three-phase current, as shown in Figure 3.24.
TX 1 ... 6
RX 1 ... 6 Received Signals
Transmitted Signals Signal Processing Unit_1
CH1 = VDATA_1[11:0] CH2 = VDATA_2[11:0] CH3 = VDATA_3[11:0] CH4 = IDATA_1[11:0] CH5 = IDATA_2[11:0] CH6 = IDATA_3[11:0]
12 bits
Signal Processing Unit_2
Hamming Encoder
Hamming Decoder
12 bits
12 bits
Data Transmission Unit
12 bits 12 bits 12 bits 12 bits
12 bits
Serializer And NRZ Encoder
12 bits 12 bits
Deserializer And NRZ Detector
12 bits 12 bits
CH1 = INF_DATA[11:0] CH2 = INF_DATA[23:12] CH3 = INF_DATA[35:24] CH4 = INF_DATA[47:36] CH5 = INF_DATA[59:48] CH6 = INF_DATA[71:60]
Digital Parallel signals 6 Channels 72 bits
Digital Parallel signals 6 Channels 72 bits
TX 1 ... 6 RX 1 ... 6
Data 12 bits
Serialized Data Stream
Each channel
Redundant bits
1 Codeword
Figure 3.24: Data Transmission in my concept
As discussed in the above section, the focus of this work is on the safety of data transmission though a noisy environment. The data transmission is a section in the digital part of my concept. Therefore the analog part which senses and conditions signals will not be further discussed and implemented in the test system. For testing the digital part of my concept of the measurement system, the digital part will be physically implemented in a test system in the next chapter.
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4 Physical Implementation From my concept of measurement system in the previous chapter, this chapter shows the test system which is able to test the digital part of my concept. The test system represents only one measurement channel of the digital part in Figure 3.23.
4.1 Test System The block diagram and the picture of the test system are shown in Figure 4.1. The test system represents only one measurement channel of the six measurement channels. Because the behavior of the measurement channel being tested is similar to the others, therefore the results of one measurement channel can represent all the others.
DISPLAY-ERROR BOARD Error Correcting err_c[13:0]
Error Dectecting err_d[13:0]
FPGA BOARD ADC BOARD
din_adc[9:0]
dout_dac[11:0]
FPGA_1 (TX)
DAC BOARD
FPGA_2 (RX)
+2V
+5V neo
e_syn
d_syn
ndi
0V
0V
LVDS DRIVER
LVDS RECEIVER LVDS BOARD
Twisted Pair Cables
Figure 4.1: The Test System of My Concept
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The test system consists of ADC BOARD, FPGA BOARD, LVDS BOARD, DISPLAY-ERROR BOARD and DAC BOARD. In FPGA BOARD, the Signal Processing Unit_1 and Signal Processing Unit_2 in my concept are programmed by VHDL in the same FPGA chip. In the test system the Signal Processing Unit_1 and Signal Processing Unit_2 are called FPGA_1 and FPGA_2, respectively. In Figure 4.1, ADC BOARD converts the analog input signal to digital signals and sends the converted digital signals to FPGA BOARD. FPGA_1 in FPGA BOARD receives the converted digital signals, processes them by Hamming encoding, serializes the encoded signals and sends the serialized stream to LVDS BOARD. LVDS BOARD uses the LVDS data transmission technology to transmit and receive the serialized stream over a twisted pair cable. FPGA_2 in FPGA BOARD receives the serialized stream from LVDS BOARD and reprocesses it by Hamming decoding and deserializing (serial to parallel converting). The Hamming decoding process in FPGA_2 detects and corrects errors in the received data and sends the number of corrected errors and detected errors to DISPLAY-ERROR BOARD. The reprocessed digital signals are sent to DAC BOARD. DAC BOARD reconverts the digital signals to the analog signal to compare with the analog input signal of ADC BOARD checking the functionality of the test system. The analog input signal of ADC BOARD is generated by a function generator. And all boards of the test system are supplied by a laboratory power supply.
4.1.1 ADC BOARD The ADC BOARD in test system is the evaluation board of AD9200 from Analog Devices, as shown in Figure 4.2. The AD9200 is a pipeline architecture ADC which has 3 clock cycles pipeline latency [17]. Maximum conversion rate of AD9200 is 20 MHz, but in the test system it is run at 10 MHz. Therefore the maximum delay in ADC BOARD is expressed by Pipeline latency + Data Valid Delay =
1 × 3 cycles+ 25 ns = 325 ns 10 MHz
(4.1)
The analog input signal range of the test system is the same input voltage range of the currently used measurement system, 0V to +2V. The digital converted data of it is the 10-bit digital parallel data which is identified by din_adc[9:0].
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Figure 4.2: ADC BOARD (Evaluation Board of AD9200)
4.1.2 FPGA BOARD An important section of the digital part in my concept is the signal processing section. The test system uses a FPGA which is programmed by VHDL to process signals in the FPGA_1 and FPGA_2 section, as shown in Figure 4.1. The test system uses the evaluation board of FPGA APA075 from Actel, APA-EVAL-BRD075 [19] as FPGA BOARD. The design and source codes of FPGA_1 and FPGA_2 will be shown in chapter 4.2. The list of connecting pins of FPGA BOARD can be seen in Appendix B.
Figure 4.3: FPGA BOARD (Evaluation Board of APA075)
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4.1.3 LVDS BOARD My concept uses the LVDS technology for data transmission. LVDS BOARD is a board which consists of LVDS drivers and receivers, SN65LVDS1 and SN65LVDT2 of Texas instruments, respectively. Their data sheet can be seen in [18]. The drivers and receivers in LVDS BOARD transmit data in serial stream over a transmission medium. The transmission medium is a twisted pair cable. The twisted pair cables, which are used in this test, are the category 5 26AWG 4 pairs with common shield for all pair (S/UTP) commonly used on network application (also called network cable). In this test, the following four different cable lengths: 1, 3, 7.5 and 10 meters, are tested. The schematic circuit and the picture of LVDS BOARD are shown in Figure 4.4.
+3.3 V
+3.3 V
Differential Signaling
SN65LVDS1 +Dout
+Din
neo
SN65LVDT2
ndo
100 ohm
-Dout
-Din
SN65LVDS1 +Dout
+Din
+3.3 V
+3.3 V
e_syn
100 ohm
-Dout
SN65LVDT2
d_syn
-Din
Twisted Pair Cables
Figure 4.4: LVDS BOARD
4.1.4 DAC BOARD DAC BOARD is used to observe the processed digital signals, dout_dac[11:0], from FPGA_2. DAC BOARD is a board which consists of a digital to analog converter (DAC), AD767 from Analog Devices [20]. The picture of DAC BOARD is shown in Figure 4.5.
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Figure 4.5: DAC BOARD
4.1.5 DISPLAY-ERROR BOARD DISPLAY-ERROR BOARD is a board which is used to observe the number of corrected errors and the number of detected errors from the Hamming decoding process in FPGA_2. DISPLAY-ERROR BOARD consists of signal drivers, UDN2981A [21], and seven-segment LED which can display numbers from 0 to 99. The schematic circuit and the picture of DISPLAY-ERROR BOARD are shown in Figure 4.6.
Figure 4.6: DISPLAY-ERROR BOARD
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4.2 FPGA Design The most important part in my concept is to process the signals in the digital transmission system. The test system uses a FPGA, which is programmed by VHDL, to process the signals. The FPGA consists of 2 parts: FPGA_1, which acts like the transmitter and FPGA_2, which acts like the receiver. The process in FPGA is shown in the functional block diagram in Figure 4.7. For the FPGA design, the process is divided into 4 processes: Clock Control Generating process, Data Loading process, Hamming Coding process, and NRZ Coding and Serializing process. They will be discussed in the next sections. The VHDL codes of all blocks in the FPGA are shown in Appendix C.
Figure 4.7: Inside of FPGA design
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4.2.1 Clock Control Generating The clock control generating process is a process to generate clock signals to control the other blocks in the FPGA. This process consists of 3 blocks: CLK_DIVIDER, PLL_1 and PLL_2. •
CLK_DIVIDER: The process of CLK_DIVIDER block is to generate the clock
signal clk_2 that controls signals receiving from ADC BOARD. Consequently, the clock control is a signal which controls the sampling rate of ADC BOARD to FPGA BOARD. The FPGA BOARD has a 40 MHz oscillator which generates the signal clk on the board [19] and the required sampling rate (refer from chapter 3.2.1) is higher than 1.65 MHz. Due to the limited performance of FPGA, the test system can not process the signal at the sampling rate 1.65 MHz. Therefore, for testing, the test system uses the sampling rate at 1.0526 MHz. This sampling rate is the maximum possible rate of this FPGA. For generating the clock control 1.0526 MHz clk_2, in general, it can generate by dividing the 40 MHz clk by 38. The conceptual diagram of clock generating is shown in the Figure 4.8.
Figure 4.8: Conceptual diagram of the CLK_DIVIDER block
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PLL_1 and PLL_2: These blocks are phase lock loop (PLL) blocks in the
FPGA which are created by SmartGen in the Libero IDE program [22]. The PLL_1 generates the clock control clk5x_1 to control the blocks in FPGA_1: ECC_EN block and NRZ_EN block. And the PLL_2 generates the clock control clk5x_2 to control the blocks in FPGA_2: NRZ_DE block, ECC_DE block and BIN_TO_SSEG block. The minimum frequency of clock control signals, clk5x_1 and clk5x_2, can be expressed by: Conversion rate of ADC (frequency of clk_2)
= 1.0526 MHz
The number of bits of codeword (chapter 4.2.3)
= 18 bits
Over-sampling factor (chapter 4.2.4)
= 5 times
The minimum frequency of clk5x_1 and clk5x_2 is ADC conversion rate × Codeword bits × Over-sampling factor
(4.2)
1.0526MHz × 18bits × 5 = 94.73MHz
In this test system I use the clock control clk5x_1 and clk5x_2 signals at 110 MHz. The frequency of clk5x_1 and clk5x_2 signals is higher the minimum frequency to prevent the system from having some delays in the processes in FPGA and in the devices, e.g. ADC, and LVDS driver and receiver.
4.2.2 Data Loading After the clock control generating process generated the clock control signal clk_2, the data loading process, which is represented by LOADER_DATA block in Figure 4.7, uses this signal to control signals receiving from ADC BOARD. The converted digital signal from ADC BOARD is a digital parallel 10-bit din_adc[9:0]. Because the test system is required to test the 12-bit data dout_load[11:0] processing (from the requirements of this work, chapter 1.1), the data loading process will add digital ‘0’ signals into two least significant bits that can be seen in Figure 4.9.
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Figure 4.9: Conceptual diagram of the LOADER_DATA block
4.2.3 Hamming Coding As discussed in chapter 3.3, error control codes can improve reliability and reduce probability of error in digital transmission. My concept of measurement system uses Hamming codes as error control codes. Hamming codes are error correcting codes which are one-way transmission codes (FEC) and can correct the presence of single bit errors in a codeword. The advantages of Hamming codes are that it easily implements in FPGA by using a look up table or XOR operators and it uses a few clock cycles to encode and decode. The data dout_load[11:0] is a 12-bit digital parallel data. The general classes of Hamming codes are not suitable for 12-bit data. Therefore this work uses the shortened Hamming codes (refer from chapter 3.3.3.1). The general class of Hamming code, which is chosen, is Hamming code (63,57). The generator polynomial and GF (2 6 ) of Hamming code (63,57) are shown in Appendix A. The shortened Hamming code, which is used, is the shortened Hamming Code (18,12) which is modified from Hamming code (63,57) by the method of Hsiao [13].
4.2.3.1 Hamming Encoding The encoding algorithm is a mathematical method as shown in the equation (3.5), where the message X is the received data from LOADER_DATA block and the generator matrix G of shortened Hamming code (18,12) is shown in the following matrix.
4 Physical Implementation ⎡1 ⎢0 ⎢ ⎢1 ⎢ ⎢0 ⎢1 ⎢ 0 G = ⎢⎢ 1 ⎢ ⎢0 ⎢1 ⎢ ⎢0 ⎢ ⎢1 ⎢⎣0
1 0 1 0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 1 1 0 1 0
0 1 1 0 0 1 0 1 1 0 0 1
61
0 1 0 1 1 0 0 1 0 1 1 0
0 1 0 1 0 1 1 0 0 1 0 1
1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 0 1 0
0⎤ 0⎥⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ ⎥ 0⎥ 1⎥⎦
The Hamming encoding process is the ECC_EN block in Figure 4.7. The algorithm of Hamming encoding process, which is programmed by VHDL, is presented in the flowchart in Figure 4.10.
4.2.3.2 Hamming Decoding The Hamming decoding process uses the equation (3.12) where the parity check matrix H of the shortened Hamming code (18,12) is shown in the following matrix and the
received codeword D is the received codeword from NRZ_DE block. ⎡1 ⎢0 ⎢ ⎢0 H =⎢ ⎢0 ⎢0 ⎢ ⎢⎣0
0 1 0 0 0 0
0 0 1 0 0 0
0 0 0 1 0 0
0 0 0 0 1 0
0 0 0 0 0 1
1 1 1 0 0 0
0 0 0 1 1 1
1 1 0 1 0 0
0 0 1 0 1 1
1 1 0 0 1 0
0 0 1 1 0 1
1 1 0 0 0 1
0 0 1 1 1 0
1 0 1 1 0 0
0 1 0 0 1 1
1 0 1 0 1 0
0⎤ 1⎥⎥ 0⎥ ⎥ 1⎥ 0⎥ ⎥ 1⎥⎦
The outcome of Hamming decoding is syndrome S. The syndrome can be accomplished as follows: if the syndrome is zero assuming that no error occurred, if the syndrome is nonzero and contains an odd number of 1’s assuming that a single error occurred and it can be corrected by the following Table 4.1, and if the syndrome is nonzero and it contains an even number of 1’s that an uncorrectable error pattern has been detected.
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Furthermore, the Hamming decoding process counts the number of errors which were corrected and detected and sends the number of corrected errors and the number of detected errors in seven-segment codes to DISPLAY-ERROR BOARD for displaying numbers in the seven-segment LED. The Hamming decoding process is the ECC_DE block in Figure 4.7. The algorithm of the Hamming decoding process is shown in Figure 4.11 and the VHDL code of it is shown in Appendix C.
Table 4.1: Syndrome Bits and Look Up table
Syndrome Bits LSB MSB 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1
Look Up Table Error Free bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 bit 17
LSB 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
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False
Chip Enable (din_ecc_v = ’1’)
Ture
Store Input din_ecc in Register din_reg
Clock-Synchronized Combinational Circuit (XOR) C=MxG C = codeword registers (cout_reg) (18 bits) M = input registers (din_reg) (12 bits) G = gernerator matrix
Provide output codeword and valid signal Data: cout_ecc[17:0] Valid: cout_ecc_v
Figure 4.10: Flowchart of the ECC_EN block
Figure 4.11: Flowchart of the ECC_DE block
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4.2.3.3 Performance of Error correcting code For the performance of error correcting code calculation, I use probability of error (also called Bit Error Rate) to calculate and compare the transmission system which is installed Hamming code (18,12) and the transmission system which is not installed error correcting code. From the equation (3.18), the probability of error for the uncoded transmission system which transmits 12-bit data is given by Puncoded = 1 − (1 − p )
12
(4.3)
And from the equation (3.20), the probability of error for the Hamming encoded (18,12) transmission system is given by 1 ⎛ n⎞ n −i PHam (18,12 ) = 1 − ∑ ⎜⎜ ⎟⎟ p i (1 − p ) i =0 ⎝ i ⎠
or
(
(4.4)
PHam (18,12 ) = 1 − (1 − p ) + 18 p(1 − p ) 18
17
)
The transmission channel is approximated by Additive White Gaussian Noise (AWGN) Channel and Binary Symmetric Channel (BSC). The p , probability of random bit error, is given in the term of Gaussian distribution which is shown in the equation (3.17). ⎛ 2 Eb p = Q⎜ ⎜ N 0 ⎝
⎞ ⎟ ⎟ ⎠
The comparison of probability of error for the uncoded system, equation (4.3), and for the Hamming coded (18,12) system, equation (4.4), is shown in Figure 4.12. The m-files for illustrating this comparison are shown in Appendix D.
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Figure 4.12: Comparison of probability of error for the Hamming (18,12) coded system and the uncoded system
As seen in Figure 4.12, it illustrates the relationship between the ratio of energy per bit to noise power spectral density Eb / N 0 and the probability of error for the uncoded transmission system and the Hamming coded (18,12) transmission system. At the same quantity of Eb / N 0 , the probability of error for the uncoded transmission system is more than the probability of error for the Hamming coded (18,12) transmission system. And in the other hand, it is apparent that the Hamming coded (18,12) transmission system has a 3 dB advantage over the uncoded transmission system since the uncoded transmission system requires a Eb / N 0 that is 3 dB larger than that for the Hamming coded (18,12) transmission system for the same probability of error.
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4.2.4 NRZ Coding and Serializing The NRZ coding and serializing process is a process to transmit and receive data in a serialized stream data with NRZ line code form (refer from chapter 3.4). This process consists of 2 processes: the NRZ encoding process and the NRZ decoding process which are represented as NRZ_EN block and NRZ_DE block in Figure 4.7, respectively.
4.2.4.1 NRZ Encoding The NRZ encoding is a process to transmit the codeword signals from the Hamming encoding process to LVDS BOARD in a NRZ serialized stream data neo. The codeword of the Hamming code (18,12) is a 18-bit parallel data. Therefore, the NRZ encoding process serializes the 18-bit parallel codeword to a serialized stream data.
4.2.4.2 NRZ Decoding The NRZ decoding is a receiving process which receives the serialized stream data ndi from the transmission medium. And then it reconverts the received serialized data to the 18-bit parallel data sending the converted parallel data to the Hamming decoding process.
1 codeword Codeword 18-bits neo, ndi
bit17
bit16
bit15
bit14
bit13
bit12
bit11
bit10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Sample signal 5x Oversampling Synchronized signal e_syn, d_syn
Figure 4.13: Serialized communication in the Test System
The serialized stream data transmits and receives at the over-sampling factor of 5. The over-sampling in the digital transmission can improve the SNR of the transmitted signal. The sample signal, as shown in Figure 4.13, is a signal at receiving-side. The receiver detects the bit-symbol at the middle of a 5-times over-sampling. And this work uses the synchronized signal to synchronize the transmitter and receiver at the first bit (most significant bit, MSB) of codeword as shown in Figure 4.13. The processes of the
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NRZ encoding process and the NRZ decoding process are shown in the flowcharts in Figure 4.14 and Figure 4.15, respectively.
Figure 4.14: Flowchart of the NRZ_EN block
Figure 4.15: Flowchart of the NRZ_DE block
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4.2.5 Simulation Results In above sections, we discussed the processes in FPGA_1 and FPGA_2 of the digital transmission in my concept. For the FPGA implementation, this work uses Libero IDE version 7.1 [22], a program that Actel supports for use with their FPGA. It provides primarily methods of creating designs to a user: code design, synthesis, place and route, layout and program into a FPGA. All VHDL source codes, which are used in this work, are shown in Appendix C. The VHDL source codes of the processes, which were implemented into FPGA BOARD, can be simulated using a simulator program. This work uses ModelSim Actel 6.1b [23] program for simulation. The Figure 4.16 and Figure 4.17 show the simulated waveforms.
Figure 4.16: Simulated Waveforms of All Processes in FPGA BOARD
The Figure 4.16 shows the simulated waveforms of all processes in FPGA BOARD which the input stimuli were generated by the testbench TB_TOP_LEVEL (shown in Appendix C). The simulated waveforms show that the processes in FPGA BOARD are working correctly. CLK_DIVIDER block generates the clock signal 1.0526 MHz clk_2. LOADER_DATA block loads data from ADC BOARD. ECC_EN block encodes the data with Hamming code (18,12). NRZ_EN block serializes a codeword and transmits a serialized stream data with a synchronized signal. NRZ_DE block receives a serialized stream data and converts to an 18-bit parallel codeword. ECC_DE block decodes a
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codeword, corrects it and counts errors. SEVEN_SEGMENT block converts a binary code of the number of errors to a seven segment code for displaying numbers in the seven-segment LED. The all processes in FPGA use 102 clock cycles of clk5x_1 and clk5x_2 altogether. The clk5x_1 and clk5x_2 are a 110 MHz clock signal. Therefore the latency of all processes in the FPGA is 927.273 ns. It can achieve the requirement of this work that the latency is in the range of 1 µs. The Figure 4.17 shows the simulated waveforms of the Hamming decoding process which the input stimuli were generated by the testbench TB_ECC_DE (shown in Appendix C). In this figure, it shows that a codeword was decoded and if the syndrome of the Hamming decoding process was nonzero, the decoded data was corrected by using look up table.
Figure 4.17: Simulated Waveforms of Hamming Decoding Process
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4.3 Experimental Results One measurement channel of the digital part of my concept of the measurement system in chapter 3 was physically implemented in the test system, as shown in Figure 4.1. In this chapter, the test system was tested in the laboratory environment and in the operational environment.
4.3.1 Laboratory Environment Testing The test system was tested in the laboratory environment as shown in Figure 4.18. The test system was tested to transmit and receive over different twisted pair cable lengths: 1m, 3m 7.5m and 10m. All twisted pair cables in this test are the category 5 26AWG 4 pairs with common shield for all pair (S/UTP).
Figure 4.18: Test in the Laboratory Environment
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4.3.1.1 Functionality Testing Firstly, the test system was tested for the functionality of the test system by connecting the function generator to the ADC BOARD input, and the resulting analog output signal of DAC BOARD was observed on the oscilloscope.
Figure 4.19: Experimental Waveforms of ADC BORAD Input and DAC BOARD Output in the Laboratory Environment
As seen in Figure 4.19, the function generator generated the input signals sine and triangle waveforms which are a 2 Volt peak-to-peak (0 V to 2 V) 100 kHz signal. The output signals of DAC BOARD were also sine and triangle waveforms. They were similar to the input waveforms. Therefore, it is clear that the functionality of the test system is working correctly.
4.3.1.2 Bit Error Rate Testing Bit error rate (BER) testing is a method to determine the signal quality and the performance of a transmission system. The standard equation of a bit error rate measurement is: ⎛ number of bit error ⎞ ⎟⎟ BER = ⎜⎜ ⎝ total number of bit ⎠
(4.5)
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For BER test, the ADC BOARD was connected with a function generator which provides an input sine waveform 2 Volt peak-to-peak (0 V to 2 V) 100 kHz signal. This test method was tested with different cable lengths: 1m, 3m, 7.5m and 10m. Every cable was tested for 1 hour. The number of bit error was observed on DISPLAY-ERROR BOARD. Testing Conditions
Data rate
= 22 Mbps
Testing time = 3600 seconds (1 hour)
Codeword
= 18 bits (NRZ)
Total bits
= 7.92 × 1010 bits
Cable lengths = 1m, 3m, 7.5m and 10m The results of this test are shown in Table 4.2. In practical application, the required BER might be less than 10 −9 or less than one bit error in 1 billion bits sent.
Table 4.2: Errors Testing in the Laboratory Environment
Cable Length (m) 1 3 7.5 10
Laboratory Environment Corrected Detected BER Errors Errors 0 0 < 7.92 × 10 −10 0 0 < 7.92 × 10 −10 0 0 < 7.92 × 10 −10 0 0 < 7.92 × 10 −10
Table 4.2 shows that no errors were detected and corrected during this test. The BER test in the laboratory environment concludes that in the range of the twisted pair cable length from 1 m to 10 m the test system of my concept run error free, or at least the BER of the test system is less than 7.92 × 10 −10 . It is clear that the BER of the test system in the laboratory environment less than the required BER of 10 −9 . The results from this test show that the FPGA_1, which acts like transmitter, and the FPGA_2, which acts like receiver, in FPGA BOARD are running correctly and the LVDS data transmission technology, which is used in my concept, can transmit data with very low bit error rate in the range of 10 meters.
4.3.1.3 Data Transmission Testing The test system of my concept of measurement system uses the LVDS technology in a point-to-point configuration for data transmission. This test observes the transmitted
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signals at receiving-side in the laboratory environment as shown in Figure 4.20. This figure is a part of the driver and the receiver in LVDS BOARD in the test system.
Figure 4.20: LVDS Signals Quality test in the Laboratory Environment
The Figure 4.21 shows the measured signals of the LVDS signals at receiving-side, i.e. the single-ended LVDS signals at the LVDS receiver inputs, the differential signal which the LVDS receiver detects and the output of the LVDS receiver signal which is identified as ndi signal.
Figure 4.21: Experimental Waveforms of LVDS Receiver Input and Output in the Laboratory Environment
As shown in Figure 4.21, the LVDS signals, +Din and –Din, transmitted over the twisted pair cable that were influenced by noise. The twisted pair cable is a balanced cable. Therefore, noise appeared equally on each pair and this common-mode noise was rejected by the LVDS receiver because of detecting the differential signal, (+Din) – (–Din), across inputs. For this reason, the output of LVDS receiver, ndi, was low-noise and good quality.
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4.3.1.4 Eye Pattern Measurement The effect of all transmission impairments, i.e. high-to-low transition, low-to-high transition, overshoot, undershoot and noises, can be seen by observing the received signals on an oscilloscope from a diagram called an eye pattern. Eye pattern measurement is a very accurate way to measure the expected signal quality in the data transmission. The effect of impairments is to partially close the eye. As long as the eye is open at least a little in the middle at the sampling time, it is clear that the receiver will detect correctly. If all the space is filled with signal transitions, then detection can be erroneous. In this test, eye pattern measurement measures the LVDS differential signal at receiving-side, which is shown at the test point in Figure 4.20. The measured eye patterns are shown in Figure 4.22.
Figure 4.22: Eye Patterns of the Differential Signals at Receiving-Side in the Laboratory Environment
As seen in Figure 4.22, the measured eye patterns of the differential signals were clearly open in the laboratory environment.
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From the measured eye patterns, jitter measurement is used to measure the amount of sample timing error versus the unit interval as shown in Figure 4.23. The unit interval, t ui , of my concept is 45.45 ns ( 5 × 1 / 110 MHz ). Due to the factor of 5 over-sampling of the transmitter and the receiver of my concept, therefore the maximum jitter allotment is 20 %.
Figure 4.23: Jitter Measurement in a Measured Eye Pattern
Table 4.3: Jitter measurement in the laboratory environment
Cable Length (m) 1 3 7.5 10
Laboratory Environment Crossing jitter Jitter (ps) (%) 960 2.1 400 0.9 580 1.3 1040 2.3
In Figure 4.22 the measured eye patterns of different cable lengths showed that the eyes were effectively open and Table 4.3 showed that the jitter results were relatively low compared with the maximum jitter allotment of 20%. It is clear that in the laboratory environment and in the range of the twisted pair cable length from 1 m to 10 m, the LVDS technology transmits and receives a low-noise and good quality signal and the receiver will detect correctly.
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4.3.2 Operational Environment Testing The experimental results of the test system of my concept in the laboratory environment clearly showed a very good qualitative agreement. The test system was tested again in the operational environment as shown in Figure 4.24.
Figure 4.24: Test in the Operational Environment
The operational environment testing is a test which transmits signals inside of a running UPS system, which is a noisy environment with high levels of EMI. From laboratory environment testing it showed that in the cable length of 10m the test system of my concept was working well and error free. Thus, the different-cable-lengths-test is not required. The operational environment testing uses only the 7.5m-length twisted pair cable. The test system was tested while the UPS is operating under the no-load (0%) condition, the half-load (50%) condition and the full-load (100%) condition.
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4.3.2.1 Functionality Testing The test system of my concept was tested in the operational environment using the same method as described in section 4.3.1.1. The test system was tested while the UPS was operating under the full-load (100%) condition.
Figure 4.25: Experimental Waveforms of ADC BOARD Input and DAC BOARD Output in the Operational Environment at 100% Load Condition
Figure 4.25 shows that the output signals of DAC BOARD were also sine and triangle waveforms. They were similar to the input waveforms. It shows clear that the functionality of the test system is also working correctly in the operational environment.
4.3.2.2 Bit Error Ratio Testing The test system was tested in the operational environment, while the UPS was operating under the no-load condition, the half-load condition and the full-load condition using the same method as described in section 4.3.1.2. The results are shown in Table 4.4. Table 4.4: Error Testing in the Operational Environment
Load Testing (%)
Testing Time (s)
0 50 100
3600 600 20
Operational Environment Corrected Detected BER Errors Errors 0 0 < 7.92 × 10 −10 29 23 3.94 × 10 −9 99 99 4.50 × 10 −7
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It can be noticed from Table 4.4 that the test system ran error free while the UPS was operating under the no-load condition. But while the UPS was operating under the half-load condition and the full-load condition, there were few errors, which were observed by DISPLAY-ERROR BOARD, in the test system. The test system can achieve the required BER of 10 −9 while the UPS was operating under the no-load condition and the half-load condition. But while the UPS was operating under the full-load, it can not satisfy the required BER.
4.3.2.3 Data Transmission Testing This test observes the transmitted signals at receiving-side as shown in Figure 4.26. In the operational environment testing, the test system was tested to transmit over the 7.5 m twisted pair cable while the UPS was operating under a full-load.
Figure 4.26: LVDS Signals Quality test in the Operational Environment
The Figure 4.27 shows the measured signals of the LVDS signals at receiving-side, i.e. the single-ended LVDS signals at LVDS receiver inputs, the differential signal and the output of LVDS receiver signal.
Figure 4.27: Experimental Waveforms of LVDS Receiver Input and Output in the Operational Environment at 100% Load Condition
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The Figure 4.27 shows the measured LVDS signals at receiving-side. The LVDS signals, +Din and –Din, transmitted over the twisted pair cable that were influenced by the very high levels of noise, crosstalk and EMI while the UPS was operating under the full-load condition. This noise were rejected because the LVDS receiver detected the differential signal, (+Din) – (–Din), across inputs. But it did not perform very well in the very high noisy environment under the full-load condition. By this reason, the LVDS receiver could not produce good quality output.
4.3.2.4 Eye Pattern Measurement In this test, eye pattern measurement measures the LVDS differential signal at receiving-side as shown at the test point in Figure 4.26. The measured eye patterns are shown in Figure 4.28.
Figure 4.28: Eye Patterns of the Differential Signals at Receiving-Side in the Operational Environment
As seen in Figure 4.28, while the test system was testing in the operational environment, there was noise in the LVDS differential signals. The noise present in the full-load condition was greater than in the half-load condition and the no-load condition.
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The experimental results of the test system showed that the functionality of the test system was working correctly in both the laboratory environment and the operational environment. In laboratory environment, the test system worked perfectly and ran error free over a twisted pair cable in the range of 10 m. The LVDS signals showed very good quality and the measured eye patterns were clearly open. In operational environment, the test system worked perfectly and ran error free under the no-load condition. Under the half-load condition, the test system had the BER of 3.94 × 10 −9 , which can achieve the required BER of 10 −9 , but under the full-load condition it can not achieve the required BER performance. The measured eye patterns of the LVDS differential signals at receiving-side showed that there was noise which influenced in the signals and the noise present in the full-load condition was greater than in the half-load condition and the no-load condition. The experimental results show that the test system work well and can achieve the requirement of the safety of data transmission in a low to medium noisy environment, such as the laboratory environment condition, the no-load condition and the half-load condition of the UPS system. But in a very high noisy environment, such as the full-load condition of the UPS system, it does not perform well. This problem may be caused by creating the test system on breadboards. The circuits on breadboards are susceptible to noise. The test system can be effectively improved by making out of a printed circuit board (PCB) with a ground plane layer. The results show that in the range of 10 m in a low to medium noisy environment my concept can transmit the measured signals with a high-level of safety.
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5 Conclusion and Future Considerations This chapter contains the conclusion section, which summarizes the results of this work, and the future considerations section, which shows the information to provide for potential improvement of this work.
5.1 Conclusion The purpose of this project is to develop a concept of a measurement system that can improve the safety and reliability of the transmission system through a noisy environment in a UPS system. My concept has six measurement channels for measuring three-phase voltages and three-phase currents. It transmits data by using the digital transmission method as shown in Figure 3.23. The digital transmission in my concept was designed to use the LVDS technology with an error correcting code. The LVDS is a differential transmission technology which results in great noise immunity. The error correcting code, which was used in my concept, is the Hamming code (18,12). The Hamming code (18,12) can correct the presence of single bit errors in a transmitted codeword. Hence, my concept has a 3 dB advantage over the uncoded transmission system. Consequently, the measurement channel in the digital part of my concept of the measurement system was physically implemented in the test system by all signal processing processes programmed in a FPGA. The latency of all processes in the FPGA is 927.273 ns. The experimental results of the test system show that in a low to medium noisy environment, the test system work perfectly and run error free over a twisted pair cable in the range of 10 m. However, in a very high noisy environment, such as the full-load condition of a UPS system, it does not perform well. This problem may be caused by creating the test system on breadboards. The circuits on breadboards are susceptible to noise. The test system can be effectively improved by making out of a PCB with a ground plane layer. The results show that in the range of 10 m in a low to medium noisy environment my concept can transmit the measured signals with a high-level of safety. If DC voltage measurement with galvanic isolation at the battery in the UPS system is required, my concept can also be used by using Close-Loop Hall Effect sensors.
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82
5.2 Future Considerations •
FPGA: The problem of my signal processing design, which is implemented on
FPGA, is the limited performance of FPGA. The APA075 FPGA from Actel, which used in this work, can provide only a 5-times over-sampling in my design. The probability of error in my concept may reduce, if the system operates under a higher over-sampling factor by using a higher-performance FPGA or a FPGA which provides an attractive single-chip solution to serial transceiver (SER/DES) design, e.g. the Virtex-II Pro Platform FPGA from Xilinx. •
Transmission Medium: The EMI problems will be eliminated by using a fiber
optic transmission system. •
Error Correcting Codes: The chances of error will be more reduced by using a
code which has a higher error-correcting capability, such as the Bose, Chaudhuri, and Hocquenghem (BCH) code, the Reed-solomon (RS) code and the convolutional code.
6 Appendix
83
6 Appendix 6.1 Appendix A Galois Field m-tuple representation for GF( q = 2 m ) for 3 ≤ m ≤ 6
GF (2 3 = 8) p(x ) = x 3 + x + 1 1 0 0 0 0 1 0 1 0 0 1 2 1 1 0 3 0 1 1 4 1 1 1 5 1 0 1 6
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
GF (2 4 = 16) p(x ) = x 4 + x + 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 0 0
0 0 0 1 0 0 1 1 0 1 0 1 1 1 1
6 Appendix
84 GF (2 5 = 32) p ( x) = x 5 + x 2 + 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1
0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1
0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1
0 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1
0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 1
1 1 1 0 0 0 1 1 0 1 1 1 0 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 1 1 1 0 0 0 1 1 0 1 1 1 0 1
0 0 0 1 1 0 1 1 1 0 1 0 1 0 0
1 0 0 0 1 1 0 1 1 1 0 1 0 1 0
1 1 0 0 0 1 1 0 1 1 1 0 1 0 1
GF (2 6 = 64) p ( x) = 1 + x + x 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1
0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0
0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1
0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0
0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0
0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1
0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0
1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0
0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1
6 Appendix
85
6.2 Appendix B This Appendix lists a table for ProASIC plus Evaluation Board connection FPGA Board Pin No. 24 128 3 5 7 9 11 4 6 8 10 12 55 56 99 100 143 145 147 149 151 153 144 146 148 150 152 154 127 207 205 203 201 199 197 193 191 189 185 183 181
Description
Connected with
clk rst din_adc(9) din_adc(8) din_adc(7) din_adc(6) din_adc(5) din_adc(4) din_adc(3) din_adc(2) din_adc(1) din_adc(0) neo e_syn ndi d_syn dout_dac(11) dout_dac(10) dout_dac(9) dout_dac(8) dout_dac(7) dout_dac(6) dout_dac(5) dout_dac(4) dout_dac(3) dout_dac(2) dout_dac(1) dout_dac(0) dout_dac_v sseg_c(13) sseg_c(12) sseg_c(11) sseg_c(10) sseg_c(9) sseg_c(8) sseg_c(7) sseg_c(6) sseg_c(5) sseg_c(4) sseg_c(3) sseg_c(2)
Global signals in FPGA
ADC Board
LVDS Board
DAC Board
DISPLAYERROR BOARD
Input / Output Input Input Input Input Input Input Input Input Input Input Input Input Output Output Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
6 Appendix
FPGA Board Pin No. 179 177 206 204 202 200 198 196 194 192 190 188 184 182 180 176
86
Description
Connected with
sseg_c(1) sseg_c(0) sseg_d(13) sseg_d(12) sseg_d(11) sseg_d(10) sseg_d(9) sseg_d(8) sseg_d(7) sseg_d(6) sseg_d(5) sseg_d(4) sseg_d(3) sseg_d(2) sseg_d(1) sseg_d(0)
DISPLAYERROR BOARD
Input / Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
6 Appendix
87
6.3 Appendix C This Appendix presents the VHDL codes which programmed in FPGA as shown in Figure 4.7.
6.3.1 TOP_LEVEL.vhd -------------------------------------------------------------------------------- Title : Top level of Transmission System with NRZ coding -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : TOP_LEVEL.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 01.08.2006 -- Last update : 01.08.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY TOP_LEVEL IS PORT ( -- global signal rst : IN std_logic; clk : IN std_logic;
--
-- ADC clock control -clk_1 : OUT std_logic; -- CANCELED -- input -din_adc : IN std_logic_vector(9 downto 0); -- TX NRZ -neo : OUT std_logic; e_syn : OUT std_logic; -- RX NRZ -ndi : IN std_logic; d_syn : IN std_logic; -- output -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic;
-- output counter -sseg_d : OUT std_logic_vector(13 downto 0); sseg_c : OUT std_logic_vector(13 downto 0) ); END TOP_LEVEL; ARCHITECTURE RTL OF TOP_LEVEL IS
--
COMPONENT CLK_DIVIDER IS PORT ( rst : IN std_logic; clk : IN std_logic; -- input clk 40MHz -- output -clk_1 : OUT std_logic; -- output clk_1 20MHz -- CANCELED clk_2 : OUT std_logic -- output clk_2 1MHz ); END COMPONENT; COMPONENT PLL_1 PORT (
6 Appendix
CLK GLB LOCK ); END COMPONENT; COMPONENT PLL_2 PORT ( CLK GLB LOCK ); END COMPONENT;
88
: in std_logic; : out std_logic; : out std_logic
: in std_logic; : out std_logic; : out std_logic
COMPONENT LOADER_DATA PORT ( -- global input -clk_2 : IN std_logic; -- sampling rate of ADC -- input 10 bit -din_adc : IN std_logic_vector(9 downto 0); -- output 12 bit -dout_load : OUT std_logic_vector(11 downto 0); dout_load_v : OUT std_logic ); END COMPONENT; COMPONENT ECC_EN PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- input -din_ecc : IN std_logic_vector(11 downto 0); din_ecc_v : IN std_logic; -- output -cout_ecc : OUT std_logic_vector(17 downto 0); cout_ecc_v : OUT std_logic ); END COMPONENT;
COMPONENT NRZ_EN PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- from PLL_1 -- input -cin_nrz : IN std_logic_vector(17 downto 0); cin_nrz_v : IN std_logic; -- output -neo e_syn ); END COMPONENT;
: OUT std_logic; -- output NRZ encoding : OUT std_logic -- synchronized signal
COMPONENT NRZ_DE PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- from PLL_2 -- input -ndi : IN std_logic; -- input NRZ encoding d_syn : IN std_logic; -- synchronized signal -- output -cout_nrz cout_nrz_v );
: OUT std_logic_vector(17 downto 0); : OUT std_logic
6 Appendix
89
END COMPONENT; COMPONENT ECC_DE PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- input -cin_ecc : IN std_logic_vector(17 downto 0); cin_ecc_v : IN std_logic; -- output error counter -err_d : OUT std_logic_vector(6 downto 0); err_c : OUT std_logic_vector(6 downto 0); -- output data -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic ); END COMPONENT; COMPONENT BIN_TO_SSEG PORT ( -- global input -rst : in std_logic; clk5x_2 : in std_logic; -- input -bin : in std_logic_vector(6 downto 0); -- output -sseg : out std_logic_vector(13 downto 0) ); END COMPONENT; ----- signal ----SIGNAL clk_2
: std_logic;
SIGNAL clk5x_1 SIGNAL clk5x_2
: std_logic; : std_logic;
SIGNAL d_load_ecc SIGNAL v_load_ecc
: std_logic_vector(11 downto 0); : std_logic;
SIGNAL c_ecc_nrz SIGNAL v_ecc_nrz
: std_logic_vector(17 downto 0); : std_logic;
SIGNAL c_nrz_ecc SIGNAL v_nrz_ecc
: std_logic_vector(17 downto 0); : std_logic;
SIGNAL err_d SIGNAL err_c ----- end signal ----BEGIN U1:CLK_DIVIDER port map ( rst clk --
clk_1 clk_2 ); U2:PLL_1 port map ( clk glb ); U3:PLL_2 port map ( clk glb
: std_logic_vector(6 downto 0); : std_logic_vector(6 downto 0);
=> rst, => clk, => clk_1, -- CANCELED => clk_2
=> clk, => clk5x_1
=> clk, => clk5x_2
6 Appendix
90
); U4:LOADER_DATA port map ( clk_2 din_adc
=> clk_2, => din_adc,
dout_load => d_load_ecc, dout_load_v => v_load_ecc ); U5:ECC_EN port map ( rst clk5x_1 din_ecc din_ecc_v
=> rst, => clk5x_1, => d_load_ecc, => v_load_ecc,
cout_ecc => c_ecc_nrz, cout_ecc_v => v_ecc_nrz ); U6:NRZ_EN port map ( rst clk5x_1
=> rst, => clk5x_1,
cin_nrz cin_nrz_v
=> c_ecc_nrz, => v_ecc_nrz,
neo e_syn );
=> neo, => e_syn
U7:NRZ_DE port map ( rst clk5x_2 ndi d_syn cout_nrz cout_nrz_v ); U8:ECC_DE port map ( rst clk5x_2 cin_ecc cin_ecc_v err_d err_c dout_dac dout_dac_v );
=> rst, => clk5x_2, => ndi, => d_syn, => c_nrz_ecc, => v_nrz_ecc
=> rst, => clk5x_2, => c_nrz_ecc, => v_nrz_ecc, => err_d, => err_c, => dout_dac, => dout_dac_v
U9:BIN_TO_SSEG -- display counter error correcting port map ( rst => rst, clk5x_2 => clk5x_2, bin
=> err_c,
sseg );
=> sseg_c
U10:BIN_TO_SSEG -- display counter error detecting port map (
6 Appendix
91
rst clk5x_2
=> rst, => clk5x_2,
bin
=> err_d,
sseg );
=> sseg_d
END RTL;
6.3.2 CLK_DIVIDER.vhd -------------------------------------------------------------------------------- Title : Dividing Clock Signal at FPGA1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : CLK_DIVIDER.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY CLK_DIVIDER IS PORT ( rst : IN std_logic; clk : IN std_logic; -- input clk 40 MHz -- output --clk_1 : OUT std_logic; -- output clk_1 20MHz -- CANCELED clk_2 : OUT std_logic -- output clk_2 1.0526 MHz ); END CLK_DIVIDER; ARCHITECTURE RTL OF CLK_DIVIDER IS --
SIGNAL clk_1_reg : std_logic; -- CANCELED SIGNAL clk_2_reg : std_logic; SIGNAL count_2 : std_logic_vector(4 downto 0);
BEGIN ---- CANCELED BECAUSE WE USE FUNCTION GENERATOR FOR ADC -----divider_2:PROCESS (rst,clk) -- divide by 2 --output 20MHz --BEGIN -if rst ='1' then --clk_1_reg <= '0'; --elsif (clk'event and clk = '1') then --clk_1_reg <= not clk_1_reg; --end if; --END PROCESS; --clk_1 <= clk_1_reg; ---- CANCELED BECAUSE WE USE FUNCTION GENERATOR FOR ADC ---divider_38:PROCESS (rst,clk,count_2) -- 40MHz divide by 38 --output 1.0526 MHz BEGIN if rst = '1' then clk_2_reg <= '0'; elsif clk'event and clk = '1' then if std_logic_vector(count_2) = "10010" then -- 18 clk_2_reg <= not clk_2_reg;
6 Appendix
else clk_2_reg <= clk_2_reg; end if; end if; END PROCESS; clk_2 <= clk_2_reg; counting_for_clk_2:PROCESS (rst,clk,count_2) BEGIN if rst = '1' then count_2 <= (others=>'0'); elsif clk'event and clk = '1' then if std_logic_vector(count_2) <= "10001" then -- 0 - 17 count_2 <= count_2 + "00001"; else count_2 <= (others=>'0'); end if; end if; END PROCESS; END RTL;
6.3.3 LOADER_DATA.vhd -------------------------------------------------------------------------------- Title : Loading data from ADC at FPGA_1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : LOADER_DATA.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; USE ieee.std_logic_unsigned.all ; ENTITY LOADER_DATA IS PORT ( -- global input -clk_2 : IN std_logic; -- sampling rate of ADC -- input 10 bit -din_adc : IN std_logic_vector(9 downto 0); -- output 12 bit -dout_load : OUT std_logic_vector(11 downto 0); dout_load_v : OUT std_logic ); END LOADER_DATA; ARCHITECTURE RTL OF LOADER_DATA IS BEGIN loading:PROCESS (clk_2) BEGIN if (clk_2'event and clk_2 = '1') then dout_load <= din_adc & "00";
92
6 Appendix
93
end if; END PROCESS; dout_load_v <= clk_2; END RTL;
6.3.4 ECC_EN.vhd -------------------------------------------------------------------------------- Title : Error Control Correcting Encoding at FPGA1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : ECC_EN.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 25.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- Shortened Hamming Encoder (n,k) = (18,12) -- C = M*G -- C = codeword -- M is the message 12 bit -- M = [m0, m1, m2, m3, m4, m5, m6, m7, m8, m9, m10, m11] -- G is the gemerator matrix -1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 -1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 --0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 -1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 -0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 -- G = -1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 -0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 -1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 --0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 -1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 -0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY ECC_EN IS PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- input -din_ecc : IN std_logic_vector(11 downto 0); din_ecc_v : IN std_logic; -- output -cout_ecc : OUT std_logic_vector(17 downto 0); cout_ecc_v : OUT std_logic ); END ECC_EN; ARCHITECTURE BEHAVIOR OF ECC_EN IS SIGNAL SIGNAL SIGNAL SIGNAL
din_reg din_v_reg cout_reg cout_ecc_v_reg
: : : :
std_logic_vector(11 downto 0); std_logic; std_logic_vector(17 downto 0); std_logic;
6 Appendix
94
BEGIN -- register din_ecc_v receive_data_input_enable:PROCESS (rst,clk5x_1) BEGIN if rst ='1' then din_v_reg <= '0'; elsif (clk5x_1'event and clk5x_1 = '1') then din_v_reg <= din_ecc_v; end if; END PROCESS; -- register din receive_data_in:PROCESS (rst,clk5x_1,din_ecc_v) BEGIN if rst ='1' then din_reg <= (others=>'0'); elsif (clk5x_1'event and clk5x_1 = '1') then if din_ecc_v = '1' then din_reg <= din_ecc; end if; end if; END PROCESS;
-- matrix codec multiplication encoding:PROCESS (rst,clk5x_1) BEGIN if rst ='1' then cout_reg <= (others=>'0'); elsif (clk5x_1'event and clk5x_1 = '1') then cout_reg(0)
<= din_reg(0) xor din_reg(2) xor din_reg(4) xor din_reg(6) xor din_reg(8) xor din_reg(10);
cout_reg(1)
<= din_reg(0) xor din_reg(2) xor din_reg(4) xor din_reg(6) xor din_reg(9) xor din_reg(11);
cout_reg(2)
<= din_reg(0) xor din_reg(3) xor din_reg(5) xor din_reg(7) xor din_reg(8) xor din_reg(10);
cout_reg(3)
<= din_reg(1) xor din_reg(2) xor din_reg(5) xor din_reg(7) xor din_reg(8) xor din_reg(11);
cout_reg(4)
<= din_reg(1) xor din_reg(3) xor din_reg(4) xor din_reg(7) xor din_reg(9) xor din_reg(10);
cout_reg(5)
<= din_reg(1) xor din_reg(3) xor din_reg(5) xor din_reg(6) xor din_reg(9) xor din_reg(11);
cout_reg(6) cout_reg(7) cout_reg(8)
<= din_reg(0); <= din_reg(1); <= din_reg(2);
cout_reg(9) <= din_reg(3); cout_reg(10) <= din_reg(4); cout_reg(11) <= din_reg(5); cout_reg(12) <= din_reg(6); cout_reg(13) <= din_reg(7); cout_reg(14) <= din_reg(8); cout_reg(15) <= din_reg(9);
6 Appendix
95
cout_reg(16) <= din_reg(10); cout_reg(17) <= din_reg(11); end if; END PROCESS; --provide code output cout_ecc <= cout_reg;
-- provide cout out valid enable_cout_valid:PROCESS (rst,clk5x_1) BEGIN if rst = '1' then cout_ecc_v_reg <= '0'; cout_ecc_v
<= '0';
elsif (clk5x_1'event and clk5x_1 = '1') then cout_ecc_v_reg
<= din_v_reg;
cout_ecc_v
<= cout_ecc_v_reg;
end if; END PROCESS; END BEHAVIOR;
6.3.5 NRZ_EN.vhd -------------------------------------------------------------------------------- Title : Never Return to Zero Encoding at FPGA_1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : NRZ_EN.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 31.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- 5X oversampling LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY NRZ_EN is PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- from PLL_1 -- input -cin_nrz : IN std_logic_vector(17 downto 0); cin_nrz_v : IN std_logic; -- output -neo e_syn ); END NRZ_EN;
: OUT std_logic; -- output NRZ encoding : OUT std_logic -- synchronized signal
ARCHITECTURE RTL OF NRZ_EN IS SIGNAL count_loop
: std_logic_vector(4 downto 0);
SIGNAL count_clk
: std_logic_vector(2 downto 0);
SIGNAL s_reg
: std_logic_vector(17 downto 0);
6 Appendix
96
SIGNAL cin_nrz_reg
: std_logic_vector(17 downto 0);
SIGNAL enable
: std_logic;
SIGNAL clk1x_1
: std_logic;
SIGNAL e_syn_reg
: std_logic;
BEGIN -- enable process -enable_counting:PROCESS(rst,cin_nrz_v,count_loop,clk5x_1) BEGIN if rst = '1' or count_loop = "10010" then -- =18(19th loop will be disenabled) enable <= '0'; elsif clk5x_1'event and clk5x_1 = '1' then if cin_nrz_v = '1' then enable <= '1'; end if; end if; END PROCESS;
-- receive data from FEC, depended on clk5x_1 din_register:PROCESS (rst,clk5x_1,cin_nrz_v) BEGIN if rst = '1' then cin_nrz_reg <= (others=>'0'); elsif clk5x_1'event and clk5x_1 = '1' then if cin_nrz_v = '1' then cin_nrz_reg <= cin_nrz; end if; end if; END PROCESS;
-- count word 18 bits -count_loop_18:PROCESS(rst,enable,clk5x_1,count_clk) BEGIN if rst = '1' then count_loop <= (others=>'0'); elsif clk5x_1'event and clk5x_1 = '1' then if enable = '1' then if count_clk = "100" then count_loop <= count_loop + "00001"; end if; else count_loop <= (others=>'0'); end if; end if; END PROCESS;
6 Appendix
97
-- oversampling 5X counting 0 - 4 -oversampling:PROCESS(rst,enable,clk5x_1,count_clk) BEGIN if rst = '1' then count_clk <= (others=>'0'); elsif clk5x_1'event and clk5x_1 = '1' then if enable = '1' then if count_clk < "100" then count_clk <= count_clk + "001"; else count_clk <= (others=>'0'); end if; else count_clk <= (others=>'0'); end if; end if; END PROCESS; -- clock 1/5X of clk5x_1 -divided_5:PROCESS(rst,clk5x_1) BEGIN if rst = '1' then clk1x_1 <= '0'; elsif clk5x_1'event and clk5x_1 = '1' then clk1x_1 <=
((not count_clk(2)) and (not count_clk(1)) and (count_clk(0)));
end if; END PROCESS; -- shift data (parallel to serial) data_shifted_register:PROCESS (rst,clk1x_1,count_loop) BEGIN if rst ='1' then s_reg
<= (others=>'0');
e_syn_reg
<= '0';
elsif (clk1x_1'event and clk1x_1 = '1') then if enable = '1' then if count_loop = "00000" then s_reg <= cin_nrz_reg; e_syn_reg
<= '1';
else s_reg <= s_reg(16 downto 0) & '0'; e_syn_reg
<= '0';
end if; else s_reg <= (others=>'0');
6 Appendix
98
e_syn_reg
<= '0';
end if; end if; END PROCESS; -- NRZ encoding output -neo <= s_reg(17); -- Synchorized signals -e_syn <= e_syn_reg; END RTL;
6.3.6 NRZ_DE.vhd -------------------------------------------------------------------------------- Title : Never Return to Zero Decoding at FPGA_2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : NRZ_DE.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 31.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- 5X oversampling LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY NRZ_DE IS PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- from PLL_2 -- input -ndi : IN std_logic; -- input NRZ encoding d_syn : IN std_logic; -- synchronized signal -- output -cout_nrz cout_nrz_v ); END NRZ_DE;
: OUT std_logic_vector(17 downto 0); : OUT std_logic
ARCHITECTURE RTL OF NRZ_DE IS SIGNAL cout_nrz_reg : std_logic_vector(17 downto 0); SIGNAL rsr
: std_logic_vector(17 downto 0);
SIGNAL enable
: std_logic;
SIGNAL count_loop
: std_logic_vector(4 downto 0);
SIGNAL count_clk
: std_logic_vector(2 downto 0);
SIGNAL sample_2
: std_logic;
SIGNAL cout_nrz_v_reg : std_logic; BEGIN -- enable process -enable_counting:PROCESS(rst,d_syn,count_loop) BEGIN if rst = '1' or count_loop = "10010" then -- =18(19th loop will be disenabled)
6 Appendix
99
enable <= '0'; elsif d_syn'event and d_syn = '1' then enable <= '1'; end if; END PROCESS;
-- count word 18 bits -count_loop_18:PROCESS(rst,enable,clk5x_2,count_clk) BEGIN if rst = '1' then count_loop <= (others=>'0'); elsif clk5x_2'event and clk5x_2 = '1' then if enable = '1' then if count_clk = "100" then count_loop <= count_loop + "00001"; end if; else count_loop <= (others=>'0'); end if; end if; END PROCESS;
-- oversampling 5X counting 0 - 4 -oversampling:PROCESS(rst,enable,clk5x_2,count_clk) BEGIN if rst = '1' then count_clk <= (others=>'0'); elsif clk5x_2'event and clk5x_2 = '1' then if enable = '1' then if count_clk < "100" then count_clk <= count_clk + "001"; else count_clk <= (others=>'0'); end if; else count_clk <= (others=>'0'); end if; end if; END PROCESS;
-- synchronized sample signals with clk5x_2 sampling:PROCESS(rst,clk5x_2) BEGIN if rst = '1' then sample_2 <= '0';
6 Appendix
100
elsif clk5x_2'event and clk5x_2 = '1' then -- sample at center of 5X -sample_2 <= (not count_clk(2)) and (not count_clk(1)) and (count_clk(0)); end if; END PROCESS;
-- received signal register and shift it-shift_reg:PROCESS(rst,sample_2) BEGIN if rst = '1' then rsr <= (others=>'0'); elsif sample_2'event and sample_2 = '1' then rsr <= rsr(16 downto 0) & ndi; end if; END PROCESS;
-- sending output value -provide_output:PROCESS(rst,count_loop,clk5x_2) BEGIN if rst = '1' then cout_nrz_reg
<= (others=>'0');
cout_nrz_v_reg
<= '0';
elsif clk5x_2'event and clk5x_2 = '1' then if count_loop = "10010" then cout_nrz_reg
<= rsr;
cout_nrz_v_reg
<= '1';
elsif count_loop = "01000" then cout_nrz_v_reg
<= '0';
end if; end if; END PROCESS; cout_nrz
<= cout_nrz_reg;
cout_nrz_v
<= cout_nrz_v_reg;
END RTL;
6.3.7 ECC_DE.vhd -------------------------------------------------------------------------------- Title : Error Control Correcting Decoding at FPGA_2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : ECC_DE.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- Shortened Hamming Decoder (n,k) = (18,12) -- S = C*Ht -- S = syndrome
6 Appendix
-- C is the codeword 18 bit -- C = [c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, -c10, c11, c12, c13, c14, c15, c16, c17] -- H is the parity check matrix -- Ht is the transpose matrix of parity check matrix -1 0 0 0 0 0 -0 1 0 0 0 0 -0 0 1 0 0 0 --0 0 0 1 0 0 -0 0 0 0 1 0 -0 0 0 0 0 1 --1 1 1 0 0 0 -0 0 0 1 1 1 -1 1 0 1 0 0 -- Ht = -0 0 1 0 1 1 -1 1 0 0 1 0 -0 0 1 1 0 1 --1 1 0 0 0 1 -0 0 1 1 1 0 -1 0 1 1 0 0 --0 1 0 0 1 1 -1 0 1 0 1 0 -0 1 0 1 0 1 -- S = 0 0 0 0 0 0 = error free -- S = 1 0 0 0 0 0 = error bit 1 -- S = 0 1 0 0 0 0 = error bit 2 -- S = 0 0 1 0 0 0 = error bit 3 -- S = 0 0 0 1 0 0 = error bit 4 -- S = 0 0 0 0 1 0 = error bit 5 -- S = 0 0 0 0 0 1 = error bit 6 -- S = 1 1 1 0 0 0 = error bit 7 -- S = 0 0 0 1 1 1 = error bit 8 -- S = 1 1 0 1 0 0 = error bit 9 -- S = 0 0 1 0 1 1 = error bit 10 -- S = 1 1 0 0 1 0 = error bit 11 -- S = 0 0 1 1 0 1 = error bit 12 -- S = 1 1 0 0 0 1 = error bit 13 -- S = 0 0 1 1 1 0 = error bit 14 -- S = 1 0 1 1 0 0 = error bit 15 -- S = 0 1 0 0 1 1 = error bit 16 -- S = 1 0 1 0 1 0 = error bit 17 -- S = 0 1 0 1 0 1 = error bit 18 -------------------------------------------------------------------------------- dout_dac_v is inverted because -- dout_dac_v connects to (/CS) of DAC ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY ECC_DE IS PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- input -cin_ecc : IN std_logic_vector(17 downto 0); cin_ecc_v : IN std_logic; -- output error counter -err_d : OUT std_logic_vector(6 downto 0); err_c : OUT std_logic_vector(6 downto 0); -- output data --
101
6 Appendix
dout_dac dout_dac_v
102
: OUT std_logic_vector(11 downto 0); : OUT std_logic
); END ECC_DE; ARCHITECTURE BEHAVIOR OF ECC_DE IS SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL
cin_reg cin_v_reg delay_v_1 delay_v_2 delay_v_3 delay_v_4 err_d_reg err_c_reg dout_reg syd
: : : : : : : : : :
std_logic_vector(17 downto 0); std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(6 downto 0); std_logic_vector(6 downto 0); std_logic_vector(11 downto 0); std_logic_vector(0 to 5);
BEGIN
-- register cin_v receive_code_input_valid:PROCESS (rst,clk5x_2) BEGIN if rst ='1' then cin_v_reg <= '0'; elsif (clk5x_2'event and clk5x_2 = '1') then cin_v_reg <= cin_ecc_v; end if; END PROCESS; -- register cin, use positive egde of cin_v_reg receive_code_in:PROCESS (rst,cin_v_reg) BEGIN if rst ='1' then cin_reg <= (others=>'0'); elsif cin_v_reg'event and cin_v_reg = '1'
then
cin_reg <= cin_ecc; end if; END PROCESS;
-- parity check matrix -syndrome:PROCESS(rst,delay_v_2) BEGIN if rst = '1' then syd <= (others=>'0'); elsif delay_v_2'event and delay_v_2='1' then -- matrix codec multiplication syd(0) <= cin_reg(0) xor cin_reg(6) xor cin_reg(8) xor cin_reg(10) xor cin_reg(12) xor cin_reg(14) xor cin_reg(16); syd(1) <= cin_reg(1) xor cin_reg(6) xor cin_reg(8) xor cin_reg(10) xor cin_reg(12) xor cin_reg(15) xor cin_reg(17); syd(2) <= cin_reg(2) xor cin_reg(6) xor cin_reg(9) xor cin_reg(11) xor cin_reg(13) xor cin_reg(14) xor cin_reg(16); syd(3) <= cin_reg(3) xor cin_reg(7) xor cin_reg(8) xor cin_reg(11) xor cin_reg(13) xor cin_reg(14) xor cin_reg(17); syd(4) <= cin_reg(4) xor cin_reg(7) xor cin_reg(9) xor cin_reg(10) xor cin_reg(13) xor cin_reg(15) xor cin_reg(16);
6 Appendix
103
syd(5) <= cin_reg(5) xor cin_reg(7) xor cin_reg(9) xor cin_reg(11) xor cin_reg(12) xor cin_reg(15) xor cin_reg(17); end if; END PROCESS;
-- correcting data -correcting:PROCESS (rst,delay_v_3,syd) BEGIN if rst = '1' then dout_reg <= (others => '0'); elsif delay_v_3'event and case syd is
delay_v_3='1' then
when "111000" => dout_reg(0) dout_reg(11 downto 1)
<= (not cin_reg(6)); <= cin_reg(17 downto 7);
when "000111" => dout_reg(0) dout_reg(1) dout_reg(11 downto 2)
<= cin_reg(6); <= (not cin_reg(7)); <= cin_reg(17 downto 8);
when "110100" => dout_reg(1 downto 0) dout_reg(2) dout_reg(11 downto 3)
<= cin_reg(7 downto 6); <= (not cin_reg(8)); <= cin_reg(17 downto 9);
when "001011" => dout_reg(2 downto 0) dout_reg(3) dout_reg(11 downto 4)
<= cin_reg(8 downto 6); <= (not cin_reg(9)); <= cin_reg(17 downto 10);
when "110010" => dout_reg(3 downto 0) dout_reg(4) dout_reg(11 downto 5)
<= cin_reg(9 downto 6); <= (not cin_reg(10)); <= cin_reg(17 downto 11);
when "001101" => dout_reg(4 downto 0) dout_reg(5) dout_reg(11 downto 6)
<= cin_reg(10 downto 6); <= (not cin_reg(11)); <= cin_reg(17 downto 12);
when "110001" => dout_reg(5 downto 0) <= cin_reg(11 downto 6); dout_reg(6) <= (not cin_reg(12)); dout_reg(11 downto 7) <= cin_reg(17 downto 13); when "001110" => dout_reg(6 downto 0) dout_reg(7) dout_reg(11 downto 8)
<= cin_reg(12 downto 6); <= (not cin_reg(13)); <= cin_reg(17 downto 14);
when "101100" => dout_reg(7 downto 0) dout_reg(8) dout_reg(11 downto 9)
<= cin_reg(13 downto 6); <= (not cin_reg(14)); <= cin_reg(17 downto 15);
when "010011" => dout_reg(8 downto 0) dout_reg(9) dout_reg(11 downto 10)
<= cin_reg(14 downto 6); <= (not cin_reg(15)); <= cin_reg(17 downto 16);
6 Appendix
104
when "101010" => dout_reg(9 downto 0) dout_reg(10) dout_reg(11)
<= cin_reg(15 downto 6); <= (not cin_reg(16)); <= cin_reg(17);
when "010101" => dout_reg(10 downto 0) dout_reg(11)
<= cin_reg(16 downto 6); <= (not cin_reg(17));
when others => dout_reg(11 downto 0) <= cin_reg(17 downto 6); end case; end if; END PROCESS; -- provide output -dout_dac <= dout_reg;
-- provide cout out valid -enable_cout_valid:PROCESS (rst,clk5x_2) BEGIN if rst = '1' then dout_dac_v delay_v_1 delay_v_2 delay_v_3 delay_v_4
<= <= <= <= <=
'0'; '0'; '0'; '0'; '0';
elsif (clk5x_2'event and clk5x_2 = '1') then delay_v_1 delay_v_2 delay_v_3 delay_v_4 dout_dac_v
<= <= <= <= <=
cin_v_reg; delay_v_1; delay_v_2; delay_v_3; not delay_v_4; -- because dout_dac_v connects with /CS
end if; END PROCESS;
-- counter for error correcting (single error correcting) -error_correcting:PROCESS(rst,delay_v_4,syd) BEGIN if rst = '1' then err_c_reg err_c
<= (others=>'0'); <= (others=>'0');
elsif delay_v_4'event and delay_v_4='1' then if
(
then
syd = "100000" or syd = "010000" or syd = "001000" or syd = "000100" or syd = "000010" or syd = "000001" or syd = "111000" or syd = "000111" or syd = "110100" or syd = "001011" or syd = "110010" or syd = "001101" or syd = "110001" or syd = "001110" or syd = "101100" or syd = "010011" or syd = "101010" or syd = "010101")
6 Appendix
105
err_c_reg <= err_c_reg + "0000001"; else err_c_reg <= err_c_reg; end if; err_c <= err_c_reg; end if; END PROCESS;
-- counter for error that can only detecting (double errors detecting) -error_detecting:PROCESS(rst,delay_v_4,syd) BEGIN if rst = '1' then err_d_reg err_d
<= (others=>'0'); <= (others=>'0');
elsif delay_v_4'event and delay_v_4='1' then if
(
syd and and and and and and and and and and and and and and and and and and
/= "000000" syd /= "100000" syd /= "010000" syd /= "001000" syd /= "000100" syd /= "000010" syd /= "000001" syd /= "111000" syd /= "000111" syd /= "110100" syd /= "001011" syd /= "110010" syd /= "001101" syd /= "110001" syd /= "001110" syd /= "101100" syd /= "010011" syd /= "101010" syd /= "010101")
then err_d_reg <= err_d_reg + "0000001"; else err_d_reg <= err_d_reg; end if; err_d <= err_d_reg; end if; END PROCESS; END BEHAVIOR;
6.3.8 BIN_TO_SSEG.vhd -- BIN_TO_SSEG.vhd -------------------------------------------------------------------------------- Title : Convert Binary to Seven Segments LED at FPGA2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : BIN_TO_SSEG.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 02.08.2006 -- Last update : 02.08.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro
6 Appendix
-------------------------------------------------------------------------------- Creates driver bits for each of seven segments on display from binary input -- Inputs: Binary value to show on seven segment display (7 bit) (0 to 99) -- Outputs: On/Off values for each of seven segments on display (7 bit) -- LED active HIGH ------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BIN_TO_SSEG IS PORT ( -- global input -rst : in std_logic; clk5x_2 : in std_logic; -- input -bin : in std_logic_vector(6 downto 0); -- output -sseg : out std_logic_vector(13 downto 0) ); END BIN_TO_SSEG; ARCHITECTURE BEHAVIORAL OF BIN_TO_SSEG IS SIGNAL bin2_reg : std_logic_vector(3 downto 0); SIGNAL bin1_reg : std_logic_vector(6 downto 0); BEGIN manage_bin:PROCESS(rst,clk5x_2,bin) BEGIN if rst = '1' then bin1_reg <= (others=>'0'); bin2_reg <= (others=>'0'); elsif clk5x_2'event and clk5x_2='1' then if bin > "1100011" then -- >99 bin2_reg <= (others=>'1'); bin1_reg <= (others=>'1'); elsif bin > "1011001" then -- >89 bin2_reg <= "1001"; bin1_reg <= (bin - "1011010"); elsif bin > "1001111" then -- >79 bin2_reg <= "1000"; bin1_reg <= (bin - "1010000"); elsif bin > "1000101" then -- >69 bin2_reg <= "0111"; bin1_reg <= (bin - "1000110"); elsif bin > "0111011" then -- >59 bin2_reg <= "0110"; bin1_reg <= (bin - "0111100"); elsif bin > "0110001" then -- >49 bin2_reg <= "0101"; bin1_reg <= (bin - "0110010"); elsif bin > "0100111" then -- >39 bin2_reg <= "0100";
106
6 Appendix
107
bin1_reg <= (bin - "0101000"); elsif bin > "0011101" then -- >29 bin2_reg <= "0011"; bin1_reg <= (bin - "0011110"); elsif bin > "0010011" then -- >19 bin2_reg <= "0010"; bin1_reg <= (bin - "0010100"); elsif bin > "0001001" then -- >9 bin2_reg <= "0001"; bin1_reg <= (bin - "0001010"); elsif bin < "0001001" then -- <9 bin2_reg <= (others=>'0'); bin1_reg <= bin; end if; end if; END PROCESS; encode_to_sseg:PROCESS(rst,clk5x_2,bin2_reg,bin1_reg) BEGIN if rst = '1' then sseg(6 downto 0) sseg(13 downto 7)
<= "0111111"; -- one unit <= "0111111"; -- ten unit
elsif clk5x_2'event and clk5x_2='1' then case bin2_reg is -- ten unit when "0000" => sseg(13 when "0001" => sseg(13 when "0010" => sseg(13 when "0011" => sseg(13 when "0100" => sseg(13 when "0101" => sseg(13 when "0110" => sseg(13 when "0111" => sseg(13 when "1000" => sseg(13 when "1001" => sseg(13 when others => sseg(13 end case; case bin1_reg(3 downto 0) is when "0000" => sseg(6 when "0001" => sseg(6 when "0010" => sseg(6 when "0011" => sseg(6 when "0100" => sseg(6 when "0101" => sseg(6 when "0110" => sseg(6 when "0111" => sseg(6 when "1000" => sseg(6 when "1001" => sseg(6 when others => sseg(6 end case;
downto downto downto downto downto downto downto downto downto downto downto
-- one downto downto downto downto downto downto downto downto downto downto downto
7) 7) 7) 7) 7) 7) 7) 7) 7) 7) 7)
<= <= <= <= <= <= <= <= <= <= <=
unit 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <=
"0111111"; "0000110"; "1011011"; "1001111"; "1100110"; "1101101"; "1111101"; "0000111"; "1111111"; "1101111"; "0000000";
"0111111"; "0000110"; "1011011"; "1001111"; "1100110"; "1101101"; "1111101"; "0000111"; "1111111"; "1101111"; "0000000";
--0 --1 --2 --3 --4 --5 --6 --7 --8 --9 --Off
--0 --1 --2 --3 --4 --5 --6 --7 --8 --9 --Off
end if; END PROCESS; END BEHAVIORAL;
6.3.9 TB_TOP_LEVEL.vhd -------------------------------------------------------------------------------- Title : Test bench of Top level of Transmission System -- Project : The concept of measurement system
6 Appendix
108
-------------------------------------------------------------------------------- File : TB_TOP_LEVEL.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 01.08.2006 -- Last update : 01.08.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY TB_TOP_LEVEL IS END; ARCHITECTURE TB OF TB_TOP_LEVEL IS COMPONENT TOP_LEVEL PORT ( -- global signal rst : IN std_logic; clk : IN std_logic; -- ADC clock control -clk_1 : OUT std_logic; -- CANCELED
--
-- input -din_adc : IN std_logic_vector(9 downto 0); -- TX NRZ -neo : OUT std_logic; e_syn : OUT std_logic; -- RX NRZ -ndi : IN std_logic; d_syn : IN std_logic; -- output -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic; -- output counter -sseg_d : OUT std_logic_vector(13 downto 0); sseg_c : OUT std_logic_vector(13 downto 0) ); END COMPONENT; ------ signal -----SIGNAL rst SIGNAL clk --
SIGNAL clk_1
: std_logic; : std_logic; : std_logic; -- CANCELED
SIGNAL din_adc
: std_logic_vector(9 downto 0);
SIGNAL neo SIGNAL e_syn
: std_logic; : std_logic;
SIGNAL ndi SIGNAL d_syn
: std_logic; : std_logic;
SIGNAL dout_dac SIGNAL dout_dac_v
: std_logic_vector(11 downto 0); : std_logic;
SIGNAL sseg_d SIGNAL sseg_c
: std_logic_vector(13 downto 0); : std_logic_vector(13 downto 0);
signal a : std_logic; signal b : std_logic; ------ end signal -----BEGIN UUT:TOP_LEVEL port map (
6 Appendix
rst clk --
clk_1
109
=> rst, => clk, => clk_1, -- CANCELED
din_adc
=> din_adc,
neo e_syn
=> a, => b,
ndi d_syn
=> a, => b,
dout_dac dout_dac_v
=> dout_dac, => dout_dac_v,
sseg_d sseg_c );
=> sseg_d, => sseg_c
-- generate clk, 40 MHz gen_clk:PROCESS BEGIN clk <= '0'; wait for 12.5 ns; clk <= '1'; wait for 12.5 ns; END PROCESS; -- generate reset, in the first 200 ns gen_rst:PROCESS BEGIN rst <= '0'; wait for 10 ns; -- 30ns rst <= '1'; wait for 300 ns; -- 200ns reset actived rst <= '0'; wait; END PROCESS;
-- gen din_adc gen_stimulus:PROCESS BEGIN din_adc <= (others => '0'); wait for 100 ns; din_adc <= (others => '1'); wait for 100 ns; din_adc <= (others => '0'); wait for 100 ns; din_adc <= "1010101010"; wait for 100 ns; din_adc <= (others => '1'); wait for 300 ns; din_adc <= "1010101010"; wait for 100 ns; din_adc <= (others => '0'); wait for 3000 ns; din_adc <= "0101010101"; wait for 200 ns; din_adc <= (others => '1'); wait for 1 us; din_adc <= "0101010101"; wait for 100 ns; din_adc <= (others => '0');
6 Appendix
110
wait for 100 ns; din_adc <= "1010101010"; wait for 200 ns; END PROCESS; END;
6.3.10
TB_ECC_DE.vhd
-------------------------------------------------------------------------------- Title : Test Bench of Error Control Correcting Decoding at FPGA_2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : TB_ECC_DE.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 30.09.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY TB_ECC_DE IS END; ARCHITECTURE TB OF TB_ECC_DE IS COMPONENT ECC_DE PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- input -cin_ecc : IN std_logic_vector(17 downto 0); cin_ecc_v : IN std_logic; -- output error counter -err_d : OUT std_logic_vector(6 downto 0); err_c : OUT std_logic_vector(6 downto 0); -- output data -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic ); END COMPONENT; SIGNAL rst : SIGNAL clk5x_2 : SIGNAL cin_ecc SIGNAL cin_ecc_v : SIGNAL err_d : SIGNAL err_c : SIGNAL dout_dac SIGNAL dout_dac_v
std_logic; std_logic; : std_logic_vector(17 downto 0); std_logic; std_logic_vector(6 downto 0); std_logic_vector(6 downto 0); : std_logic_vector(11 downto 0); : std_logic;
BEGIN UUT:ECC_DE port map ( rst clk5x_2 cin_ecc cin_ecc_v err_d err_c dout_dac dout_dac_v );
=> => => => => => => =>
rst, clk5x_2, cin_ecc, cin_ecc_v, err_d, err_c, dout_dac, dout_dac_v
-- generate clk, 110 MHz
6 Appendix
gen_clk:PROCESS BEGIN clk5x_2 <= '0'; wait for 4.55 ns; clk5x_2 <= '1'; wait for 4.55 ns; END PROCESS; -- generate reset, in the first 200 ns gen_rst:PROCESS BEGIN rst <= '0'; wait for 10 ns; rst <= '1'; -- 200ns reset actived wait for 300 ns; rst <= '0'; wait; END PROCESS; -- generate stimulus input -- gen cin_v -- 1 MHz gen_data_enable:PROCESS -- input valid when cin_v = '1' BEGIN -- enable cin_ecc_v <= '1'; wait for 501 ns; -- disable cin_ecc_v <= '0'; wait for 501 ns; END PROCESS; -- gen cin_ecc gen_stimulus:PROCESS BEGIN cin_ecc <= (others => '0'); wait for 1 us; cin_ecc <= (others => '0'); wait for 1 us; cin_ecc <= "101000000000011000"; wait for 1 us; cin_ecc <= "111110100000110000"; wait for 1 us; cin_ecc <= "101000011111001011"; wait for 1 us; cin_ecc <= "000000010101011111"; wait for 1 us; cin_ecc <= "000000001011001011"; wait for 1 us; cin_ecc <= "101010010111100011"; wait for 1 us; cin_ecc <= "010000100011000110"; wait for 1 us; cin_ecc <= "001000000000110010"; wait for 1 us; cin_ecc <= "101000000100011000"; -- error bit 8th wait for 1 us; cin_ecc <= "011110100000110000"; -- error bit 17th wait for 1 us; cin_ecc <= "100000011111001011"; -- error bit 15th
111
6 Appendix
wait for 1 us;
cin_ecc <= "101000000100011001"; -- error bit 8th and 0th wait for 1 us; cin_ecc <= "011110100000010000"; -- error bit 17th and 5th wait for 1 us; cin_ecc <= "100000011111001001"; -- error bit 15th and 1st wait for 1 us;
cin_ecc <= "101000000100111001"; -- error bit 8th and 0th and 5th wait for 1 us; cin_ecc <= "011110100000010001"; -- error bit 17th and 5th and 0th wait for 1 us; cin_ecc <= "000000011111001001"; -- error bit 15th and 1st and 17th wait for 1 us;
END PROCESS; END;
112
6 Appendix
113
6.4 Appendix D This Appendix shows the m-files codes of Matlab program which illustrated in Figure 4.12 prob_ham_uncoded.m SNR = 0:10; PH = zeros(size(0:10)); Pu = zeros(size(0:10)); snrc = 0; for snr = SNR snrc = snrc+1; EbN0 = 10^(snr/10); p = qf(sqrt(2*EbN0)); Pu(snrc) = 1-((1-p)^12); % Ps Uncoded PH(snrc) = 1-((1-p)^18 + 18*p*(1-p)^17); % Ps Hamming 18 12 end clf; semilogy(SNR,Pu,'ro-'); hold on; semilogy(SNR,PH,'sg-'); lh = legend('P uncoded(E)','P Hamming 18,12(E)'); xh = xlabel('E_b/N_0(dB)'); yh = ylabel('Probability of Error');
qf.m function p = qf(xlist) % % Compute the Q function: % % function p = qf(x) % p = 1/sqrt(2pi)int_x^infty exp(-t^2/2)dt
p = zeros(size(xlist)); i = 0; for x = xlist i = i+1; if(x < 0) p(i) = 1- 0.5*erfc(-x/sqrt(2)); else p(i) = 0.5*erfc(x/sqrt(2)); end end
7 References
114
7 References UPS System
[1]
Ali Emadi, Abdolhosein Nasiri, Stoyan B. Bekiarov. Uninterruptible Power
Supplies and Active Filters. CRC Press. Florida. 2005. [2]
Giovanni Bucci and Carmine Landi. On-Line Digital Measurement for the
Quality Analysis of Power Systems under Non-Sinusoidal Conditions. IEEE Press. p.934-938. 1996. Digital Transmission
[3]
Leon W. Couch II Digital and analog communication systems. 6th ed. Prentice
hall, Inc. USA. 2001. [4]
John B. Anderson. Digital Transmission Engineering. IEEE Press. New York.
1999. Sensor
[5]
LEM. Isolated current and voltage transducers Characteristics – Applications -
Calculations. 3rd ed. [6]
Paul Emerald. Allegro MicroSystems, Inc. Non-intrusive Hall-Effect Current-
Sensing Techniques Provide safe, Reliable Detection and Protection for Power Electronics. Technical Paper STP 98-1 [7]
Richard Dickinson, Shaun Milano. Allegro MicroSystems, Inc. Isolated Open
Loop Current Sensing Using Hall Effect Technology in an Optimized Magnetic Circuit. 2002. Signal Conditioning
[8]
Bruce Newby. Electronic signal conditioning. Butterworth-Heinemann. Oxford.
1994. ADC
[9]
Walt Kester. Analog Devices. Which ADC Architecture is Right for Your
Application. Error Control Codes
[10]
Shu Lin, Daniel J. Costello. Error Control Coding Fundamentals and
Applications. 2nd ed. Pearson Prentice Hall, Inc. USA. 2004. [11]
Todd K. Moon. Error Correcting Coding Mathematical Methods Algorithms.
John Wiley & Sons, Inc. New jersey. 2005.
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Peter Sweeney Error Correcting Coding from Theory to Practice. John Wiley
& Sons, Inc. England. 2002. [13]
M.Y. Hsiao. A Class of Optimal Minimum Odd-Weight-Column SEC-DED
codes. IBM J. Res. Dev. 1970. Data Transmission Technologies
[14]
National Semiconductor. LVDS Owner’s Manual. 3rd ed. 2004.
[15]
Texas Instruments. LVDS Application and Data Handbook. Literature Number:
SLLD009. 2002. Transmission Mediums
[16]
A.B. Semenov, S.K. Strizhakov, I.R. Suncheley. Structured Cable Systems.
Springer-Verlag Berlin Heidelberg. 2002. Data Sheets
[17]
Analog Devices, Inc. Complete 10-Bit, 20MSPS, 80mW, CMOS A/D Converter
AD9200. 1999. [18]
Texas Instruments. High-Speed Differential Line Drivers/Receiver SN65LVDS1,
SN65LVDS2, SN65LVDT2. 2004. [19]
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[20]
Analog Devices, Inc. Microprocessor-Compatible 12-bit D/A Converter AD767.
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[22]
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MASTERARBEIT
PIPAT EUMTHURAPOT 2219560 ERSTPRÜFER:
PROF. DR.-ING AXEL MERTENS
ZWEITPRÜFER:
PROF. DR-ING. HABIL. BERND R. OSWALD
BETREUER:
DR.-ING MATTHIAS RICHTER, PILLER POWER SYSTEMS GMBH
BETREUER:
DIPL.-ING GUNTER WAKAN, PILLER POWER SYSTEMS GMBH
BETREUER:
DIPL.-ING NIKLAS RÜGER
Abstract
I
Abstract The main focus of power electronic applications in this work is on a UPS application. The power converters in a UPS system need to be controlled by a controller unit. For controlling the power converters, a measurement system is used to mention the signals and transmit the measured signals to a controller unit. The purpose of this work is to develop a concept of measurement system of three-phase voltages and three-phase currents that can improve the safety and reliability of data transmission in a UPS system. For improving the safety and reliability of data transmission through a noisy environment in a UPS system, the developed concept of measurement system transmits the measured data by a digital transmission method including an error control code. The digital part of the developed concept is physically implemented on a FPGA which is programmed by VHDL and uses the LVDS technology for data transmission. Keywords: measurement system, digital transmission, error control code
Contents
II
Contents Abstract..............................................................................................................................I Contents........................................................................................................................... II Abbreviations..................................................................................................................IV 1
Introduction ............................................................................................................. 1 1.1
2
3
Objectives and Requirements of this Work ............................................................ 3
1.1.1
Objectives ............................................................................................................................ 3
1.1.2
Requirements ....................................................................................................................... 3
1.2
Thesis Description...................................................................................................... 4
1.3
Characteristic of Voltages and Currents in the Measurement Points .................. 5
1.3.1
Approximated Voltages and Currents at the Measurement Points....................................... 6
1.3.2
Required Bandwidth ............................................................................................................ 8
1.3.3
The Result of Approximated Voltages and Currents at the Measurement Points ................ 9
Currently Used Measurement System ................................................................... 11 2.1
Voltage Measurement Path..................................................................................... 12
2.2
Current Measurement Path.................................................................................... 13
2.3
Disadvantages of the Currently Used Measurement System............................... 14
My Concept of Measurement System .................................................................... 16 3.1
Analog Part .............................................................................................................. 20
3.1.1
Sensor................................................................................................................................. 21
3.1.2
Signal Conditioning ........................................................................................................... 24
3.2
Digital Part ............................................................................................................... 25
3.2.1
Analog to Digital Conversion Section ............................................................................... 26
3.2.2
Digital Transmission Section ............................................................................................. 26
3.3
Error Control Codes................................................................................................ 28
3.3.1
Error correction.................................................................................................................. 29
3.3.2
Linear Block Codes............................................................................................................ 30
3.3.3
Hamming Code .................................................................................................................. 36
3.3.4
Performance of Error Correction Codes............................................................................. 38
3.4 3.4.1
3.5
Digital Line Codes ................................................................................................... 40 The Popular Line Codes..................................................................................................... 41
Data Transmission Technologies............................................................................ 42
3.5.1
Single-Ended vs. Differential............................................................................................. 43
3.5.2
LVDS Transmission........................................................................................................... 45
3.6
Transmission Mediums ........................................................................................... 46
3.7
My Concept .............................................................................................................. 50
Contents
4
Physical Implementation ....................................................................................... 52 4.1
ADC BOARD .................................................................................................................... 53
4.1.2
FPGA BOARD .................................................................................................................. 54
4.1.3
LVDS BOARD .................................................................................................................. 55
4.1.4
DAC BOARD .................................................................................................................... 55
4.1.5
DISPLAY-ERROR BOARD ............................................................................................. 56 Clock Control Generating .................................................................................................. 58
4.2.2
Data Loading...................................................................................................................... 59
4.2.3
Hamming Coding............................................................................................................... 60
4.2.4
NRZ Coding and Serializing.............................................................................................. 66
4.2.5
Simulation Results ............................................................................................................. 68
Experimental Results............................................................................................... 70
4.3.1
Laboratory Environment Testing ....................................................................................... 70
4.3.2
Operational Environment Testing ...................................................................................... 76
Conclusion and Future Considerations................................................................ 81 5.1
Conclusion ................................................................................................................ 81
5.2
Future Considerations............................................................................................. 82
Appendix................................................................................................................. 83 6.1
Appendix A............................................................................................................... 83
6.2
Appendix B............................................................................................................... 85
6.3
Appendix C............................................................................................................... 87
6.3.1
TOP_LEVEL.vhd .............................................................................................................. 87
6.3.2
CLK_DIVIDER.vhd .......................................................................................................... 91
6.3.3
LOADER_DATA.vhd ....................................................................................................... 92
6.3.4
ECC_EN.vhd ..................................................................................................................... 93
6.3.5
NRZ_EN.vhd ..................................................................................................................... 95
6.3.6
NRZ_DE.vhd ..................................................................................................................... 98
6.3.7
ECC_DE.vhd ................................................................................................................... 100
6.3.8
BIN_TO_SSEG.vhd......................................................................................................... 105
6.3.9
TB_TOP_LEVEL.vhd ..................................................................................................... 107
6.3.10
TB_ECC_DE.vhd ............................................................................................................ 110
6.4
7
FPGA Design............................................................................................................ 57
4.2.1
4.3
6
Test System............................................................................................................... 52
4.1.1
4.2
5
III
Appendix D............................................................................................................. 113
References ............................................................................................................ 114
Abbreviations
IV
Abbreviations AC
Alternating Current
ADC
Analog-to-Digital Converter
AM
Amplitude Modulation
ARQ
Automatic Retransmission Request
AWGN
Additive White Gaussian Noise
BER
Bit Error Rate
DC
Direct Current
DES
Deserializer
ECC
Error Control Code
EMI
Electromagnetic Interference
FEC
Forward Error Correcting
FPGA
Field Programmable Gate Array
GF
Galois Fields
IC
Integrated Circuit
ISI
Intersymbol Interference
LED
Light Emitting Diode
LSB
Least Significant Bit
LVDS
Low Voltage Differential Signaling
MSB
Most Significant Bit
NRZ
Never Return to Zero
PCB
Printed Circuit Board
PLL
Phase Locked Loop
PWM
Pulse-Width Modulation
RZ
Return to Zero
SEC-DED
Single-error correction and double-error detection
SER
Serializer
THD
Total Harmonic Distortion
UPS
Uninterruptible Power Supply
VHDL
Very-high-speed-integrated-circuit Hardware Description Language
XOR
Exclusive-OR
1 Introduction
1
1 Introduction An Uninterruptible Power Supply (UPS) is a system which provides uninterrupted, reliable and high-quality power for vital loads such as airline computer, life-support systems in hospitals and communication systems, among others. It, in fact, protects sensitive loads against power outages as well as over-voltage and under-voltage conditions.
Figure 1.1: Measurement systems in the UPS system
In UPS system as shown in Figure 1.1, the power is converted twice [1]. First it is converted from alternating current (AC) to direct current (DC) at the rectifier, and then it is converted back from DC to AC at the inverter. In power conversion, the purpose of an AC/DC rectifier in the UPS system is to produce DC voltage with quality sufficient for proper operation of the DC/AC inverter at the back end of the UPS system. The inverter is put in parallel to the mains delivered to the load. The inverter must then compensate for defects of the mains when present, and generate the sinusoidal output from the battery when AC-mains are absent.
1 Introduction
2
The power converters in the UPS system need to be controlled by a controller unit because the performance of UPS can be considerably improved if the current and voltage is effectively controlled. This is clear from the fact that to deliver a good AC power during emergency, the UPS systems that include the feedback controlled pulse-width modulation (PWM) inverter and L-C output filter have to convert a DC voltage source (battery) to a sinusoidal AC voltage with low steady state voltage error, low voltage total harmonic distortion (THD) and fast transient response under load disturbances. Furthermore, the good performance mention of the controller unit should be guaranteed under power pollution which leads to voltage distortion due to increasing applications of power converters or nonlinear loads in industry. As shown in Figure 1.1, the system between the measurement point and the controller unit is the measurement system, which is the objective of this work. The measurement system is a system which measures three-phase voltages and three-phase currents at the measurement points (the input of the rectifier and the output of the inverter) and transmits the measured signals to the controller unit. Voltage and current sensing in digitally controlled power converters in general requires sensing devices with galvanic isolation between the sensing point and the control electronics, transmission of measured signals through a noisy environment with high levels of Electromagnetic Interference (EMI) in UPS systems and appropriate analog-to-digital conversion for the controller unit.
1 Introduction
3
1.1 Objectives and Requirements of this Work 1.1.1 Objectives The measurement system of three-phase voltages and three-phase currents for a UPS system has to be developed. It has to provide a safe and reliable solution for data transmission and can be developed in a subsequent step. For a suitable concept, it should be defined and specified in functional units. The individual functional units should be developed in a Field Programmable Gate Array (FPGA) which is programmed in Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
1.1.2 Requirements •
Safe solution of data transmission through a noisy environment in a UPS system has to be created.
•
Six measurement channels for three-phase voltages and three-phase currents are considered as in one unit.
•
Voltage measurement with and without galvanic isolation.
•
Current measurement with galvanic isolation.
•
Digital information with 12-bit or 10-bit word length has to be presented in the range of 500 ns to 10 µs in a signal processing unit (microcontroller or FPGA).
•
Latency of the developed concept of the measurement system should be in the range of 1 µs.
•
Recurrent Interfaces should be defined.
The developed concept of the measurement system has to be considered in cost-effectiveness, data rate, noise immunity and reusability for different applications.
1 Introduction
4
1.2 Thesis Description A UPS system is an application that requires controlling the power converters. For controlling the power converters, i.e. rectifier and inverter, the measurement system is used to mention the signals and transmit the measured signals to the controller unit. The developed concept of measurement system in this work is a measurement system with galvanic isolation. The galvanic isolation is a complete physical separation between the high power circuit and the electronic circuit. It is needed to protect the measurement system from potentially damaging high power signals and to eliminate ground loops between the high power circuit and the electronic circuit. In the developed concept of the measurement system, the accuracy measured value, the latency of system, the safety and reliability of data transmission and the cost effectiveness of the system are the important parameters that need to be considered. This thesis report is organized as follows. Chapter 1 will show the introduction of this work, including the characteristic of voltages and currents in the measurement point. Chapter 2 will roughly explain the currently used measurement system and show some disadvantages of it. Chapter 3 will present my concept of the measurement system, which can solve the disadvantages of the currently used measurement system and also achieve the requirements of this work, including explanation of electronics devices and digital processing methods which are used in my concept, i.e. voltage and current sensors, signal conditioning circuits, digital transmission system, digital line codes, error control codes, data transmission technologies and transmission mediums. Next, Chapter 4 will implement the digital part of my concept of measurement system to the test system and show the simulation results and the experimental results of it. Finally, Chapter 5 concludes and discusses this work.
1 Introduction
5
1.3 Characteristic of Voltages and Currents in the Measurement Points For the three-phase voltages and currents measurement, the voltage and current must be approximated in a general mathematical model. An example of the worst case of the voltages and currents at the measurement point is shown in Figure 1.2. They are the voltage and current at the output of inverter with L-C filter. The signals are not the pure sinusoidal waveform [2]. The signals contain several harmonic components caused by the switching of the inverter.
(a)
(b) Figure 1.2: Examples of the input signals (a) voltage (b) current
As seen in Figure 1.2, the shapes of the voltage and current waveforms are a combination of a high-frequency triangular waveform and a low-frequency sine waveform. The voltages and currents at the measurement points can be closely approximated by amplitude modulation (AM) where the carrier signal of AM is a low-frequency sine wave and the modulating signal is a high-frequency triangular wave. The approximated voltages and currents at the measurement points are shown in Figure 1.3.
1 Introduction
6
Figure 1.3: Approximated input signals
1.3.1 Approximated Voltages and Currents at the Measurement Points As shown in Figure 1.3, the voltages and currents at the measurement points can be closely approximated by AM where the carrier signal of AM is a low-frequency sine wave and the modulating signal is a high-frequency triangular wave. Carrier signal is a sine wave vc (t) = Ac sin (ωc t) where Ac
=
amplitude of carrier signal For Voltage
Ac = 325 V
For Current
Ac = 250 A
(1.1)
1 Introduction
7
ωc
=
angular frequency of carrier signal, ωc = 2πf c
fc
=
frequency of carrier signal in Hertz, f c = [40 Hz … 60 Hz]
t
=
time in second.
Modulating signal is a triangular wave Description in Fourier series ∞
v s (t ) = ∑ (a n cos(nωt ) + bn sin(nωt ))
(1.2)
n =1
an = bn =
1
π 1
π
2π
∫ v(t ) cos(n ω t ) d(ω t )
(1.3)
0
2π
∫ v(t ) sin(n ω t ) d(ω t )
(1.4)
0
The triangular wave is a waveform with quarter-cycle symmetry, only the odd harmonics with sine components will appear. ∞
v s (t ) = As ∑ bn sin(nω s t )
(1.5)
n =1
bn = bn =
4
π
2π
∫ v(t ) sin(nω t ) d(ω t ) s
s
⎧(−1) ( n −1) / 2 , n = odd 8 × ⎨ , n = even π 2n2 ⎩ 0
where As
=
(1.6)
0
amplitude of modulating signal For Voltage
As = 50 V
For Current
As = 80 A
n
=
order n of the harmonic of ω s
ωs
=
angular frequency of modulating signal, ω s = 2πf s
fs
=
frequency of modulating signal in Hertz, f s ≤ 25 kHz
t
=
time in second
(1.7)
1 Introduction
8
Amplitude Modulated signal
The mathematical model of the approximated signal is given by = [ Ac + v s (t )]sin(ω c t )
vam (t )
∞ ⎡ ⎤ = ⎢ Ac + As ∑ bn sin(nω s t )⎥ sin(ω c t ) n =1 ⎣ ⎦
(1.8)
1.3.2 Required Bandwidth For signal measurement, the specified frequency range or the required bandwidth of the input signal is an important parameter. In practice, it is impossible to measure the signals with all harmonic components because the bandwidth of measurement system will be infinity. For resolving the question of how much bandwidth is required for acceptable measurement quality, it can be determined by calculating the magnitude of harmonics. The approximated signal, as shown in Figure 1.3, is the amplitude modulated signal combined by the carrier signal, which is a low-frequency sine wave, and the modulating signal, which is a high-frequency triangular wave. The fundamental frequency of the modulating signal is 25 kHz. From equation (1.5), the acceptable harmonics of the modulating signal are the harmonics which have a magnitude more than 0.1 % of the fundamental frequency magnitude.
bn =
8 π n2 2
b b33 = 12 = 0.00092 × b1 33
(1.9)
The equation (1.9) shows the magnitude of the 33rd harmonic of the modulating signal is below than 0.1 % of the fundamental frequency magnitude. Therefore, the required bandwidth is up to the 33rd harmonic of the modulating signal. The frequency of the 33rd harmonic of the modulating signal is 33 × 25 kHz = 825 kHz. Therefore, the required bandwidth of the approximated signal is 825 kHz
1 Introduction
9
1.3.3 The Result of Approximated Voltages and Currents at the Measurement Points As discussed above, the three-phase voltages and currents at the measurement points can be approximated by amplitude modulation. This section shows the mathematical models of the approximated three-phase voltages and currents which are identified at V _ X , I _ X by X is the order of phase {1, 2, 3}.
Three-Phase Voltages
V _ 1 ,V _ 2 ,V _ 3 From equation (1.8), the voltage at the measurement points is expressed by ∞ ⎡ ⎤ V _ X = ⎢ Ac + As ∑ bn sin(nω s t )⎥ sin(ω c t ) n =1 ⎣ ⎦
(1.10)
where
Ac
=
amplitude of carrier signal
Ac = 325 V
As
=
amplitude of modulating signal
As = 50 V
ωc
=
angular frequency of carrier signal
ω c = 2πf c
fc
=
frequency of carrier signal in Hertz
f c = [40Hz…60Hz]
n
=
order n of the harmonic of ω s
ωs
=
angular frequency of modulating signal
ω s = 2πf s
fs
=
frequency of modulating signal in Hertz
f s ≤ 25 kHz
t
=
time in second
bn =
⎧(−1) ( n −1) / 2 , n = odd 8 × ⎨ , n = even π 2n2 ⎩ 0
The required bandwidth is 825 kHz.
Three-Phase Currents
I _ 1, I _ 2 , I _ 3 From equation (1.8), the current at the measurement points is expressed by
1 Introduction
10
∞ ⎡ ⎤ I _ X = ⎢ Ac + As ∑ bn sin( nω s t )⎥ sin(ω c t ) n =1 ⎣ ⎦
(1.11)
where
Ac
=
amplitude of carrier signal
Ac = 250 A
As
=
amplitude of modulating signal
As = 80 A
ωc
=
angular frequency of carrier signal
ω c = 2πf c
fc
=
frequency of carrier signal in Hertz
f c = [40Hz…60Hz]
n
=
order n of the harmonic of ω s
ωs
=
angular frequency of modulating signal
ω s = 2πf s
fs
=
frequency of modulating signal in Hertz
f s ≤ 25 kHz
t
=
time in second
bn =
⎧(−1) ( n −1) / 2 , n = odd 8 × ⎨ , n = even π 2n2 ⎩ 0
The required bandwidth is 825 kHz.
2 Currently Used Measurement System
11
2 Currently Used Measurement System Currently, Piller Power Systems GmbH is using the currently used measurement system in its own UPS systems. The block diagram of the currently used measurement system is shown in Figure 2.1.
Figure 2.1: Block Diagram of the Currently Used Measurement System
The Figure 2.1 shows that the currently used measurement system senses the three-phase voltages and three-phase currents at the measurement points in BOARD_1 and transmits the analog sensed signals over a transmission medium to BOARD_2, which consists of signal conditioning circuits, analog-to-digital converters (ADC), a digital signal processing unit (DSP) and a random access memory (RAM). The BOARD_2 is a part of the currently used measurement system which is in the controller unit of the UPS system. It receives the analog sensed signals from BOARD_1, converts the received signals to digital data, processes the digital data and interfaces them to the signal processing unit in the controller unit. The currently used measurement system can be divided in 2 main paths: the voltage measurement path, which measures the three-phase voltages, and the current measurement path, which measures the three-phase currents.
2 Currently Used Measurement System
12
2.1 Voltage Measurement Path The block diagram of the voltage measurement path in the currently used measurement system is shown in Figure 2.2.
Figure 2.2: Block diagram of the Voltage Measurement Path in the Currently Used Measurement System
As shown in Figure 2.2, BOARD_1 consists of a resistor network, which acts like resistive voltage sensors sensing the three-phase voltages at the measurement point. Then, the analog sensed voltage signals are transmitted through the transmission medium, which is a flexible flat cable, from BOARD_1 to BOARD_2. BOARD_2 consists of a signal conditioning circuit, ADC, DSP and RAM. The signal conditioning circuit receives the analog sensed signals from BOARD_1. The objective of the signal conditioning circuit is to adjust the magnitude of signals to the required characteristics preparing to convert analog to digital. The ADC receives the analog conditioned signals and converts them to the digital serial data stream. Then the converted serial data stream is transmitted to the DSP and RAM which convert the serial data stream to the parallel data and interface the
2 Currently Used Measurement System
13
converted parallel data to the signal processing unit in the controller unit of the UPS system.
2.2 Current Measurement Path The current measurement path measures the three-phase currents at the measurement point. In the currently used measurement system, the current sensors in BOARD_1 are transformers. The block diagram of the current measurement path in the currently used measurement system is shown in Figure 2.3.
Figure 2.3: Block diagram of the Current Measurement Path in the Currently Used Measurement System
As shown in Figure 2.3, the current measurement path is used in the similar way as the voltage measurement path except that the sensors in BOARD_1 are transformers and the analog current mode transmission between BOARD_1 and BOARD_2.
2 Currently Used Measurement System
14
2.3 Disadvantages of the Currently Used Measurement System The currently used measurement system, which is used in the UPS system, can measure the three-phase voltages and the three-phase currents with acceptable accuracy. However, the currently used measurement system has disadvantages which may cause a damage of the measurement system and a measurement error.
•
The voltage measurement in the currently used measurement system is not galvanically isolated. The lack of isolation can cause a damage of the measurement system.
•
The transmitted signals in the measurement system may be influenced external sources because the measurement system operates in the UPS system, which is a noisy environment. The influence of noise on the signal transmission can be a source of measurement error. The signal transmission in the currently used measurement system can be divided structurally into two sections:
o Transmission Medium
The currently used measurement system uses an unshielded flat cable as transmission medium, which carries the analog signals from BOARD_1 to BOARD_2. The signals being transmitted over the unshielded flat cable may be easily influenced by crosstalk and the external noise produced by electromagnetic fields.
o Transmission Type
In the currently used measurement system, the signals are transmitted in analog form. This is an analog transmission method. The disadvantage of analog transmission is shown in Figure 2.4.
2 Currently Used Measurement System
R’
15
L’ C’
R’
dx
Figure 2.4: The Disadvantages of Analog Transmission
The Figure 2.4 shows the disadvantages of analog transmission. The analog signal is being transmitted through the transmission medium. The analog transmitted signal may be influenced by external sources. And the transmission medium is a typical circuit with distributed parameters. The parasitic parameters in the transmission medium can cause signal attenuation and crosstalk on the analog transmitted signal. These effects can result in the received signals. They can cause a measurement error. In the next chapter, we will discuss the developed concept of the measurement system which can improve the safety of the data transmission and can overcome the disadvantages of the currently used measurement system.
3 My Concept of Measurement System
16
3 My Concept of Measurement System From the requirements of this work and the discussed disadvantages of the currently used measurement system, this chapter presents the developed concept of the measurement system which can improve the safety of data transmission and can overcome the disadvantages of the currently used measurement system. For improving the safety and reliability of the transmission system through a noisy environment in a UPS system, my developed concept of the measurement system uses a digital transmission method to transmit the sensed signals to the controller unit. The main disadvantage of the currently used measurement system is the low level of safety of data transmission due to analog transmission. The analog transmission method introduces sources of measurement error, as discussed above. The digital transmission method has several advantages comparing with the analog transmission method. It can improve the level of safety of data transmission through a noisy environment in a UPS system.
Advantages of Digital transmission
•
Digital transmission is less susceptible to noise problems than analog transmission
In analog transmission the objective is to transmit a waveform, which is a function that varies continuously with time. The function of time must be reproduced exactly at the output of the analog transmission. In practice, a transmission medium does not satisfy this condition, so degree of distortion is unavoidable. The digital transmission is a transmission system, which transmits digital information that is a given symbol in finite set. Binary digital transmission, for example, the objective is to transmit either a ‘0’ or a ‘1’ from transmitter to receiver. This can be done by transmitting positive voltage to convey a ‘1’ and ground voltage to convey a ‘0’. The positive and ground pluses that were transmitted can undergo a great degree of distortion. The system will operate correctly as long as the receiver can determine whether the original voltage was positive or ground.
3 My Concept of Measurement System
•
17
Control of quality
Another difference between analog and digital transmission deals with the hardware’s ability to recover the transmitted signal. Digital transmission, it uses only 1’s and 0’s to encode the signal, can incorporate error detecting and error correcting information to the signal being transmitted. Error Control codes can be encoded with transmitted data in transmitter. The results of encoding are called codewords, which are contained data and redundant checking bits. The receiver can detect and correct the transmitted data by using the redundant checking bits. The objective of Error Control codes is to reduce the chances of errors in transmission.
Transmitter
Receiver
Transmission Medium 1
0
0
1
0
Error Control Coding 1
0
0
0
0
ERROR Received Signal
Transmitted Signal
1
0
0
1
0
CORRECTED Decoded Signal
Figure 3.1: The Advantages of Digital Transmission
The Figure 3.1 shows the advantages of digital transmission. The transmitter transmits the digital information through the transmission medium by transmitting ground voltage, when a digital data is ‘0’ and positive voltage, when a digital data is ‘1’. The receiver receives the transmitted digital data, which may be distorted by the characteristic of transmission medium and/or external noises. However, the receiver will only determine whether the original voltage was positive or ground, and reproduces to the symbol ‘1’ or ‘0’. Sometimes in practice, the power of noises is greater the power of transmitted signals. The receiver may be receiving the error data. But, the digital transmission can incorporate Error Control Codes to detect and correct the error in received digital data. Because of the discussed advantages of the digital transmission method, the digital transmission can improve the level of safety of data transmission and overcome the disadvantages of the currently used measurement system. Consequently, my concept of the measurement system uses the digital transmission method to transmit the signal
3 My Concept of Measurement System
18
between BOARD_1 and BOARD_2. The overview of my concept of the measurement
Interface To Controller Unit
Receiver
Driver
system is shown in Figure 3.2.
Figure 3.2: Block diagram of my concept of measurement system
As shown in Figure 3.2, BOARD_1 is a circuit board at the measurement point in the UPS system, which senses the three-phase voltages and three-phase currents at the measurement point and drives the sensed signals into the transmission medium. BOARD_2 is a part of the measurement system in the controller unit of the UPS system, which acts like a receiver. It receives the measured signals from the transmission medium, processes the received signals and interfaces the processed signals to the signal processing unit in the controller unit. The data transmission in my concept of the measurement system transmits digital data in serial transmission from BOARD_1 to BOARD_2. Serial transmission is the process of transmitting a single stream of data over a transmission medium, which can reduce the cost of the transmission medium, the driver and the receiver components. As seen in Figure 3.2, my concept of the measurement system can be divided into two parts: the analog part and the digital part.
3 My Concept of Measurement System
19
Analog Part
The analog part of my concept of the measurement system is a part that carries the analog signals before they convert to digital signals. The analog part consists of two sections: the sensing section and signal conditioning section.
•
Sensing Section: Sensor is a device that monitors the signal and/or transduces a
signal from a physical form to a corresponding signal.
•
Signal Conditioning Section: Signal conditioning circuit is a circuit which
manipulates an analog signal waveform into a more useful or required size to prepare of analog-to-digital converting.
Digital Part
The digital part is a part which carries the digital signals after the sensed analog signals converted to the digital signals, including the analog to digital converters. The digital part consists of two sections: the analog to digital conversion section and the digital transmission section.
•
Analog to Digital Conversion Section: Analog to digital conversion section is
a section, which is between analog and digital signals. The objective of it is to convert input analog signals to output digital data.
•
Digital Transmission Section: Digital transmission section is a section which
transmits the converted digital data from the ADC to the signal processing unit in the controller unit of UPS systems. Digital transmission section consists of: o Signal Processing Unit_1: Signal Processing Unit_1 is a processing
unit, for my concept it is a FPGA, in BOARD_1 which controls and receives the digital output signals from the ADC, then processes the digital signals. In the Signal Processing Unit_1 the processes are to encode error control codes increasing safety level in data transmission, to serialize the encoded data and to modulate the series data with a digital
3 My Concept of Measurement System
20
line code. Then it provides the processed signals to the Data Transmission Unit. o Data Transmission Unit: Data Transmission Unit is a unit which
consists of a driver, a transmission medium and a receiver. The driver in BOARD_1 transmits the processed signals with serial transmission over the transmission medium to the receiver in BOARD_2. o Signal Processing Unit_2: Signal Processing Unit_2 is a processing
unit, FPGA, in BOARD_2, which receives the digital signals from the Data Transmission Unit, then processes the received digital signals. The processes in Signal Processing Unit_2 are to demodulate the received signals, to deserialize the received data, to decode error control codes (detecting and/or correcting error) and to interface the decoded signals to the signal processing unit in the controller unit of UPS systems. In practice, the Signal Processing Unit_2 is a part of the function of the signal processing unit in the controller unit of UPS systems.
3.1 Analog Part The analog part in my concept of the measurement system is shown in Figure 3.3. BOARD_1 Analog Part
Voltage, Current
Galvanic Isolation
Measurement Point
Sensor
Input of Rectifier Output of Inverter
Signal Conditionting
Op-Amp Circuits
Filter
To Input of ADC
Voltage offset
V_1, V_2, V_3 (t)
VSEN_1, VSEN_2, VSEN_3 (t)
VADC_1, VADC_2, VADC_3 (t)
I_1, I_2, I_3 (t)
ISEN_1, ISEN_2, ISEN_3 (t)
IADC_1, IADC_2, IADC_3 (t)
Figure 3.3: Analog Part
3 My Concept of Measurement System
21
The analog part consists of sensors, which sense the voltage and current signals at the measurement point, and signal conditioning circuits, which manipulate the sensed signals from sensors into the required size signals of the inputs of ADC.
3.1.1 Sensor For voltage and current measurement, sensors are devices that monitor the signal at the measurement point and/or transduce the signal from a physical form to a corresponding signal. The considered sensors in this work are the sensors with galvanic isolation [6], [7]. The galvanic isolation is a complete physical separation between the high power circuit and the electronic circuit. It is needed to protect the measurement system from potentially damaging high power signals and to eliminate ground loops between the high power circuit and the electronic circuit. Sensors with galvanic isolation are the sensors that provide isolator between power stage at the measurement point and sensing devices of the measurement system. For measuring current and voltage signals, there are three technologies that are typically used:
•
Resistive sensing
•
Transformer sensing
•
Hall Effect sensing
3.1.1.1 Resistive sensing
Figure 3.4: Resistive sensing
Current Resistive Sensing
Vmea = I M × R
Voltage Resistive Sensing
Vmea = VM × (
R1 ) R1 + Rs
(3.1) (3.2)
3 My Concept of Measurement System
22
Resistive sensor can sense current and voltage in both AC and DC form by using Ohm’s Law as shown in equations (3.1) and (3.2). Resistive sensor is a sensor which is high accuracy, low cost, easily understood and used, and can use in high frequency range. However, the shortcomings are its insertion loss (heating) and lack of isolation.
3.1.1.2 Transformer Sensing
Figure 3.5: Transformer sensing
Current Transformer Sensing
Np IM = I mea N s
(3.3)
Voltage Transformer Sensing
VM Vmea = Ns Np
(3.4)
Transformers can be used to sense current and voltage in only AC form. Transformers are relatively simple to implement and are passive devices that do not require external power. The primary current will generate a magnetic field that is coupled into a secondary coil by Faraday’s Law. Their construction is simple but they do not allow the measurement of DC signals. Isolation between primary and secondary side is implicitly given.
3.1.1.3 Hall Effect Sensing The Hall Effect sensors are based on the Hall Effect that is generated by Lorentz force, which act on charges moving through a magnetic filed and produces a proportional voltage output when the magnetic flux jumps through the gap. Because Hall Effect sensors measure the magnetic field strength in close proximity to the current conductor, they can be separated by a few millimeters from the current signal, providing several kilovolts of isolation.
3 My Concept of Measurement System
23
A Hall Effect sensor has many advantages. It can be measured in large frequency range with high accuracy. However, it has also shortcoming. It is an active device that requires external power and its cost is relatively expensive. Hall Effect sensors have 2 types, Open-Loop and Closed-Loop Hall Effect sensors [5].
•
Open-Loop Hall Effect sensors: Open-Loop transducers use the simplest
implementation of the Hall Effect. The magnetic flux created by the primary current is concentrated in a magnetic circuit and measured in the air gap using a Hall device. The output from the Hall device is then signal conditioned to provide an exact representation of the primary current at the output.
•
Closed-Loop Hall Effect sensors: The magnetic flux created by the primary
current is balanced by a complementary flux produced by driving a current through the secondary windings. A Hall device and associated electronic circuit are used to generate the secondary (compensating) current that is an exact representation of the primary current. Open-Loop Hall Effect sensors have a more limited range of linearity and cannot compensate for offset and residual field errors. But, the cost of Open-Loop type is cheaper when compared with Closed-Loop type. Closed-Loop Hall Effect sensors can provide excellent accuracy. Open-Loop and Closed-Loop Hall Effect sensors are current sensors. They can sense in both AC and DC form. However, Closed-Loop Hall Effect sensors can also sense AC and DC voltage when combined with a resistor.
Figure 3.6: Hall Effect sensors
3 My Concept of Measurement System
24
For this information, a summary of the different types of sensors has been compiled in the Table 3.1.
Table 3.1: Comparison table of sensors
Sensors
Insertion Loss
Circuit Isolation
External Power
Frequency Range
DC Sensing
Estimated Accuracy
Cost
Resistive
Yes
None
None
>500 kHz
Yes
>99%
Low
Transformer
Yes
Yes
None
>400Hz
No
>95%
High
Hall Effect Open-loop Closed-loop
None None
Yes Yes
Yes Yes
>20 kHz >150 kHz
Yes Yes
90-95% >95%
Med High
For sensing three-phase voltages and three-phase currents at the measurement point, the sensors require galvanic isolation to protect the measurement system. Although the Close-Loop Hall Effect sensors can sense current and voltage in both AC and DC form with galvanic isolation in very good accuracy, the cost of Closed-Loop Hall Effect sensor is extremely expensive comparing with others. For sensing the AC voltages, the combination of the resistive divider and the transformer sensor is used in my concept. The resistive divider provides a good accuracy but its problem is lack of isolation. The transformer can be used to solve the problem of lack of isolation. The disadvantage of this sensor is that it can not sense DC Voltage because of using transformer. Therefore, the Close-Loop Hall Effect Sensors are used, if DC voltage measurement with galvanic isolation at the battery in the UPS system is required. For sensing the current in my concept, the Open-Loop Hall Effect sensor can be used to sense both AC and DC current.
3.1.2 Signal Conditioning The signal conditioning circuit in my concept is a circuit which manipulates the sensed signals from the sensors into the required size of the inputs of ADC. The design of signal conditioning circuits is depended on the sensed signals and the required signals of the inputs of the ADC. In practice, the signal conditioning circuits are created by
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operational amplifier (Op-amp) circuits. The design of signal conditioning can be seen in [8]. In my concept of measurement system, the focus of our discussion is on the safety of data transmission which is in the digital part. In the analog part, we have already discussed the sensors and the signal conditioning circuits. Therefore, the analog part will not be further discussed in this work.
3.2 Digital Part The block diagram of the digital part in my concept of measurement system is shown in Figure 3.7. The digital part is a part which carries digital signals. The digital part consists of two sections: the analog to digital conversion section, which converts the analog conditioned signals to the digital signals, and the digital transmission section, which transmits the digital converted data from BOARD_1, through a noisy environment in the UPS system, to BOARD_2. VDATA_1, VDATA_1, VDATA_1 [11:0] IDATA_1, IDATA_1, IDATA_1 [11:0]
TX
Parallel Digital Data
Serial Digital Data
BOARD_1 Digtial Part
Signal Processing Unit_1
ADC
VADC_1, VADC_1, VADC_1 (t) IADC_1, IADC_1, IADC_1 (t)
Driver
Transmission Medium BOARD_2
Signal Processing Unit_2
Interface To Controller Unit
Receiver
Parallel Digital Data
Serial Digital Data
VINF_1, VINF_1, VINF_1 [11:0] IINF_1, IINF_1, IINF_1 [11:0]
RX
Figure 3.7: Digital Part
Data Transmission Unit
AnalogSignals from Signal Conditioning
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3.2.1 Analog to Digital Conversion Section The analog to digital conversion section is a section which is between analog and digital signals. This section consists of six analog to digital converters (ADC). One ADC converts one data channel. ADC is a device that converts input analog signal to output digital data. The architecture of ADC can be seen in [9]. From the sampling theory, for anti-aliasing effect, the sampling rate of ADC must be higher than twice of the maximum frequency of the analog input ( f sampling = 2 f max ). Because the required
bandwidth of the approximated measuring signals in equation (1.10) and (1.11) is 825 kHz, therefore the sampling rate of the selected ADC must be higher than 1.65 MHz. The block diagram of analog to digital conversion section is shown in Figure 3.8.
Figure 3.8: Analog to Digital Converter (ADC)
The digital output signals of ADCs ( VDATA _ 1[11 : 0] , VDATA _ 2[11 : 0] , V DATA _ 3[11 : 0] , I DATA _ 1[11 : 0] , I DATA _ 2[11 : 0] , I DATA _ 3[11 : 0] ) are the parallel converted data of
72 bits, 12 bits per one data channel. These digital signals are sent to the digital transmission section.
3.2.2 Digital Transmission Section As discussed above, the digital transmission method has many advantages than analog transmission method, especially higher level of the safety of data transmission. The
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digital transmission section is a section which transmits the converted digital signals from ADC in BOARD_1 to the signal processing unit in the controller unit of the UPS system in BOARD_2. In Figure 3.7, after the analog to digital section converted the conditioned signals to the digital signals, the Signal Processing Unit_1 in BOARD_1 receives the converted data, processes them and transmits the processed signals to the Data Transmission Unit. Then the Signal Processing Unit_2 in BOARD_2 receives the transmitted signals from the Data Transmission unit, reprocesses the received signals and interfaces the reprocessed signals to the controller unit of the USP system. The Signal Processing Unit_1 acts like a transmitter of the digital transmission section and, consequently, the Signal Processing Unit_2 acts like a receiver of the digital transmission section. Therefore, the digital transmission section can express in the block diagram, as shown in Figure 3.9.
Source
Error Protection
Transmission Waveform Gerneration
Error Control Encoder
Driver (Modulator)
(Error Control Codes)
(Digital Line Codes)
RECEIVER
Sink
Error Control Decoder
Data Transmission
TRANSMITTER
Receiver (Demodulator)
Figure 3.9: Digital Transmission System
As shown in Figure 3.9, the processes in digital transmission consist of 2 processes: the error control coding process and the digital line coding process. These processes are explained in the next sub-chapters.
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3.3 Error Control Codes The digital transmission method can reduce errors generated during data transmission, yet the probability of errors was not eliminated. Error control coding is in digital transmission aiming to reduce the chances of error, which are caused by the effects of transmission channel noise and external sources. There are 2 methods of error control coding in digital transmission: •
Error detection or Automatic Repeat Request (ARQ): Error detection employs
only error detection and no attempt to correct any received data in error is made. It detects error in receiver by adding redundancy to data before they transmitted in transmitter and it is requested that the received data in error by retransmitted.
Figure 3.10: ARQ System
•
Error correction or Forward Error Correction (FEC): Error correction is a
one-way communication system. It employs error correcting code. It detects and automatically corrects bit errors in the receiver by adding redundancy to data before they transmitted.
Figure 3.11: FEC System
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The advantage of ARQ over FEC is that error detection requires much simpler decoding-system than error correction because the ARQ is only error a detection system which does not need correct the errors. But, when the channel error rate is high, retransmissions must be sent too frequently and the system throughput rate is lowered by the ARQ. Due to the requirement of no more than 1 µs latency, the retransmissions of ARQ system result in wastage of bandwidth and make a large latency in the transmission system. By this reason, the ARQ system is not useful for my concept. The ARQ will not be discussed any further in this work. The focus of our discussion is on the Error correction coding.
3.3.1 Error correction Error correcting codes are broadly classified in two categories, Block Codes and Convolutional Codes [10]. The encoder for block codes takes a message block of k information symbols represented by a k-tuple X = ( X 0 , X 1 ,..., X k −1 ) and transforms each message E independently into an n-tuple E = ( E 0 , E1 ,..., E n −1 ) of discrete symbols called a codeword, where (k
X and generates an n-tuple codeword E , however the generated codeword E at the time of encoding depends not only on the current k symbol message, but also on m previous message blocks. The fundamental difference between block codes and convolutional codes is that in block coding a finite length of output codeword is generated for all input message words of finite length whereas input and output symbol sequences are infinite in convolutional coding. Another important aspect is the introduction of memory element in convolutional codes.
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Figure 3.12: Classification of Error Correcting Codes
It is difficult to implement convolutional code which operates at the high data rate applications, including this measurement system. Block codes are capable of correction multiple bit-errors with the low overhead constraint. The focus of this work is on the block codes.
3.3.2 Linear Block Codes
E = X ⋅G
S = D⋅HT
Figure 3.13: Linear Block Codec Process Diagram
In block coding, this binary information sequence is segmented into message blocks of fixed length; each message block, X , consists of k information digits. There are a total of 2 k distinct messages. The encoder transforms each input message, X , into a binary n-digits, E , with n>k, using a particular algebraic algorithm (generator matrix G ). The binary n-digits, E , is referred to as the codeword of the message
3 My Concept of Measurement System During the transmitter transmits the transmitted codeword
31
E
over a
transmission medium to the receiver, the receiver receives the received codeword D from a transmission medium. On the receiving end, the decoder applies an inverse of the algebraic algorithm (parity check matrix H ) to identify and correct any errors caused by channel corruption.
3.3.2.1 The Generator Matrix Because an ( n, k ) linear code C is a k-dimensional subspace of the vector space En of all the binary n-digits, it is possible to find k linearly independent codewords, g0, g1, …, gk-1, in C such that every codeword E in C is a linear combination of these k
codewords; that is, E
E
E
=
X ⋅G
⎡ g0 ⎤ ⎢ g ⎥ = ( x0 , x1 ,K, x k −1 ) ⋅ ⎢ 1 ⎥ ⎢ M ⎥ ⎢ ⎥ ⎣ g k −1 ⎦ = x0 g 0 + x1 g1 + L + x k −1 g k −1
(3.5)
where X = ( x 0 , x1 , K, x k −1 ) is the message to be encoded, xi = 0 or 1 for 0 ≤ i < k , and G is the generator matrix of linear block codes. A property for a linear block code to
possess is the systematic structure of the codeword, as shown in Figure 3.13, in which a codeword is divided into two parts, the message part and the redundant checking part. The message part consists of k unaltered information digits, and the redundant checking part consists of n-k parity-check digits, which are linear sums of the information digits. A linear systematic ( n, k ) code is completely specified by a k × n matrix G of the following form:
⎡ g0 ⎤ ⎡ g00 g01 ⎢g ⎥ ⎢g g11 10 G=⎢ 1 ⎥ =⎢ ⎢ M ⎥ ⎢ M M ⎢ ⎥ ⎢ ⎣gk−1⎦ ⎣gk −1,0 gk −1,1
⎡ ⎤ L g0,n−1 ⎤ p01 L p0,n−k −1 1 0 L 0⎥ ⎢ p00 ⎢ p L g1.n−1 ⎥⎥ p11 L p1.n−k −1 0 1 L 0⎥ 10 ⎥ = [P Ik ] = ⎢ O M ⎥ M O M M M O M ⎥ (3.6) ⎢ M ⎥ ⎢p L gk −1,n−1⎦ L p p 0 0 L 1⎥ ⎢ k −1,0 k−1p,1 matrix k −1,n−k −1 identiy matrix k×k⎥ ⎣ ⎦
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where I k is the k × k identity matrix and P is a k × (n − k ) matrix which generates parity symbols. The P matrix is generated by generator polynomial whose coefficients are elements of Galois Field [11] [12],denoted by GF (2 m ) . The generator polynomial and GF (2 m ) are presented in Appendix A. The encoding operation is E = X ⋅ G = X [P
I k ] = [X ⋅ P
X]
(3.7)
The codeword is divided into two parts: the part X consists of the message symbols, and the part X ⋅ P consists of the parity check symbols.
3.3.2.2 The Parity Check Matrix For any k × n matrix G , there exists an (n − k ) × n matrix H with n − k linearly independent rows such that any vector in the row space of G is orthogonal to the rows of H , and any vector that is orthogonal to the rows of H is in the row space of G .
G ⋅ H T = 0.
(3.8)
Hence, we can describe the (n, k ) linear code C generated by G in an alternative way as follows: An n-digit E is a codeword in the code C generated by G only if E ⋅ H T = 0 . The matrix H is called a parity-check matrix of the code. If the generator matrix is in the systematic form of (3.6), the parity-check matrix is the following form: ⎡ ⎡ h0 ⎤ ⎢1 0 ⎢ h ⎥ ⎢0 1 H = ⎢ 1 ⎥ = I n-k P T = ⎢ ⎢ M ⎥ ⎢M M ⎢ ⎥ ⎢0 1 ⎣hn − k −1 ⎦ ⎢⎣ identity
[
]
L L O L
matrix
where P T is the transpose of the matrix P .
0 0 M 0
p 00 p 01 M p 0,n − k −1
⎤ p k −1, 0 ⎥ p k −1,1 ⎥ ⎥ M O M ⎥ p1, n − k −1 L p k −1,n − k −1 ⎥ ⎥⎦ p matrix p10 p11
L L
(3.9)
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3.3.2.3 The Minimum Distance of Block Codes The minimum distance of a code is the minimum Hamming distance between any two different codewords. Any two distinct codewords of C ( n, k ) differ in at least d min locations. Let E and W be two different codewords n-digits. The Hamming distance between E and W , denoted d ( E ,W ) , is defined as the number of places where they differ. Given a block code C, one can compute the Hamming distance between any distinct codewords. The minimum distance of C, denoted by d min , is defined as d min = min{d ( E , W ) : E , W ∈ C , E ≠ W }
(3.10)
The minimum Hamming distance d min is a very important parameter when comparing the theoretical performance of different codes because it determines the random error detecting and random error correcting capabilities of code.
3.3.2.4 Syndrome and Error Detection Given the parity-check matrix H , it is possible to check whether the received word D is a valid codeword or not. Let E = (E 0 , E1 , K , E n −1 ) be a codeword that was transmitted over a noisy channel. Let D = (D0 , D1 , K , Dn −1 ) be the received vector at the output of the channel. Because of the channel noise, a codeword D may be different from a received vector E . The vector sum of the received is defined as D =E +e
(3.11)
The vector e = (e0 , e1 ,K, en −1 ) is the error vector caused by the channel noise. Of course, the receiver does not know either E or e . On receiving D , the decoder must first determine whether D contains transmission errors. S = D⋅HT S = (E + e ) ⋅ H T
(3.12)
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The vector S = ( S 0 , S1 ,K, S n − k −1 ) is called the syndrome of D . Then, S = 0 if and only if D is a codeword, and S ≠ 0 if and only if D is not a codeword. Therefore, when S ≠ 0 , we know that D is not a codeword and the presence of errors has been detected. When S = 0 , D is a codeword, and the receiver accepts D at the transmitted codeword. It is possible that the errors in certain error vectors are not detectable, D contains errors but S = D ⋅ H T = 0 . This happens when the error vector e is identical to a nonzero codewords. In this event, D is the sum of two codewords, which is a codeword, and consequently D ⋅ H T = 0 . Error vectors of this kind are called undetectable error vector.
3.3.2.5 Error Detecting Capability of a Block Code When a codeword E is transmitted over a noisy channel, an error pattern of l errors will result in a received vector D that differs from the transmitted codeword E in l places i.e. [ d ( E,D) = l ]. The detector observes the received word D and declares an error event if S ≠ 0 . This process is called error detection. If the minimum distance of a block code C ( n, k ) is d min , any two distinct codewords of C differ in at least d min places. For this code C, no error pattern of d min − 1 or fewer errors can change one codeword into another. Therefore, an error pattern of ( l ≤ d min − 1 ) errors will for sure result in a received word D that is not a codeword. Hence, a block code with minimum distance d min is capable of detecting all the error patterns of d min − 1 or fewer errors. An error pattern of d min errors is undetectable because there exits at least one pair of codewords that differ in d min places, and there is an error pattern of d min errors that will carry one into another. The same argument applies to error patterns of more than d min errors. For this reason we say that the random-error-detecting capability of a block code with minimum distance d min is d min − 1 . There are 2 k − 1 error patterns, which alters the transmitted codeword E into another codeword W . These 2 k − 1 error patterns are undetectable and the decoder accepts W as the transmitted codeword. The decoder is then said to have committed a decoder error. However, there are 2 n − 2 k error-patterns are detectable error patterns.
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For large n , 2 k − 1 is much smaller and only a small fraction of error patterns pass through the decoder being undetected.
3.3.2.6 Error Correcting Capability of a Block Code For a C ( n, k ) block code with minimum distance d min the random error correcting capability can be determined as follows 2t + 1 ≤ d min ≤ 2t + 2
(3.13)
Next, we show that the code C is capable of correcting all the error patterns of t or fewer errors. Let E and D be the transmitted codeword and the received vector, respectively. Let W be any other codeword in C. the Hamming distances among E , D and W satisfy the triangle inequality:
d ( E , D) + d (W , D) ≥ d ( E ,W )
(3.14)
Suppose that an error pattern of t´ errors occurs during the transmission of E . Then, the received vector D differs from E in t´ places, and therefore d ( E , D) = t´ . Because E and W are codewords in C, we have d ( E , W ) ≥ d min ≥ 2t + 1
(3.15)
Combining (3.14) and (3.15) and using the fact that d ( E , D) = t´ , we obtain the following inequality:
d (W , D) ≥ 2t + 1 − t´ , where t´≤ t d (W , D) ≥ t Consider the C(7,4) code with d min = 3 From (3.15), we have t =( d min − 1 )/2 = 1 since d min is odd and let
E D
= =
[ 1 1 0 1 0 0 0 ] [ 0 1 0 1 0 0 0 ]
(3.16)
3 My Concept of Measurement System
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=
36
[ 1 1 1 0 0 1 0 ]
d ( E , D) = 1 and d (W , D) = 4 and 4 > 1. From (3.16) we conclude that if an error pattern of t or fewer errors occur, the received word D is closer to the transmitted codeword E than to any other codeword W in C in the Hamming distance sense. For all error patterns with l errors such that l > t , there exists at least one case where the received word D is closer to an incorrect codeword W than the transmitted codeword E . To show this, let E and W be two codewords in C such that d ( E , W ) = d min .
Let e 1 and e 2 be two errors patterns that satisfy the following condition: e1 + e 2 = E + W where e1 and e 2 do not have non zero components in common places. Consider the C(7,4) code with d min = 3 E e1 e2 D = E + e1 W
= = = =
[ [ [ [
1 0 0 1
1 0 0 1
0 1 0 1
1 1 0 0
0 0 0 0
0 0 1 0
0 0 0 0
] ] ] ]
= [ 1 1 1 0 0 1 0 ]
d ( E , D) = 2 and d (W , D) = 1. In this case the decoder will select W as the transmitted codeword instead of E . We conclude stating that, a block code with minimum distance
d min guarantees correcting all the error patterns of t = ⎣(d min − 1) / 2⎦ or fewer errors, where ⎣(d min − 1) / 2⎦ denotes the largest integer no grater than (d min − 1) / 2 . The parameter t is called the random-error-correcting capability of the code. A t -error correcting linear block code C ( n, k ) is capable of correcting a total of 2 ( n− k ) error patterns, including those with t or fewer errors.
3.3.3 Hamming Code Error correcting coding increases reliability of a transmission system but it also decreases system efficiency. A number of redundant bits and a number of encoding and decoding clock cycles sacrifices transmission system bandwidth. There are many codes of block codes, e.g., Hamming codes, cyclic codes, BCH, and Reed Solomon. A
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Hamming code [10] can correct the presence of single bit errors in a transmitted codeword. The advantages of Hamming code are that it easily implements in FPGA by using a look up table or XOR calculators and it uses a few clock cycles to encode and decode. By these reasons, this work will focus on Hamming codes. Hamming codes have the following parameters: Code length:
n = 2m − 1
Number of information symbols:
k = 2m − m − 1
Number of parity-check symbols:
n−k = m, m ≥ 3
Error-correcting capability:
t = 1 , ( d min = 3).
The parity-check matrix H of this code consists of all the nonzero m-tuples as its columns. In systematic form, the columns of H are arranged in the following form:
H = [I m
Q ] , where I m is an m × m identity matrix, and the sub matrix Q consists of
2 m − m − 1 columns that are the m -tuples. The columns of Q may be arranged in any order without affecting the distance property and weight distribution of the code.
[
In systematic form, the generator matrix of the code is G = Q T
]
I 2 m - m -1 ,
where Q T is the transpose of Q , and I 2 m - m - 1 is a (2 m − m − 1) × (2 m − m − 1) identity matrix. The parity-check matrix can be used to generate parity-check bits during the process of encoding and to generate bits indicating the presence and location of errors, syndrome bits, during the decoding process.
3.3.3.1 Shortened Hamming Codes Hamming codes have only a limited range of values of length n and dimension k, and the available value may not suit the system. Shortening a code means reducing the number of information bits, keeping the number of parity checks the same. The length n and the dimension k are thus reduced by the same amount. The way in which this is done is to set one of the information bits permanently to zero and then remove that bit from the code.
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We may delete any l columns from the parity-check matrix H of a Hamming code. The deletion results in a m × (2 m − l − 1) matrix H´. Using H´ as a parity-check matrix, we obtain a shortened Hamming code with the following parameter: Code length:
n = 2m − l − 1
Number of information symbols:
k = 2m − m − l − 1
Number of parity-check symbols:
n−k = m
Error-correcting capability:
t = 1 for d min ≥ 3
A Hamming code is shortened it by deleting columns from H, we would then have created a code with even d min . If we delete columns from H properly, we may obtain a
d min = 4. For example, if we delete from the submatrix Q all the columns of even weight, we obtain a m × (2 m − l − 1) matrix. The distance-4 shortened Hamming codes, also called single-error correction and double-error detection (SEC-DED) codes [13], can be used for correcting all error patterns of single error and simultaneously detecting all error patterns of double errors. When a single error occurs during the transmission of a code vector, the resultant syndrome is nonzero, and it contains an odd number of 1’s. However, when double errors occur, the syndrome is also nonzero, but it contains an even number of 1’s. Based on these facts, decoding can be accomplished as follows: •
If the syndrome S is zero, we assume that no error occurred.
•
If S is nonzero and contains an odd number of 1’s, we assume that a single error occurred. The error pattern of a single error that corresponds to S is added to the received vector for error correction.
•
If S is nonzero and it contains an even number of 1’s, an uncorrectable error pattern has been detected.
3.3.4 Performance of Error Correction Codes Suppose we are using a t-error correcting code and subjecting the decoder to a probability of random bit error rate p . As shown in Figure 3.14, the data transmission system, i.e., modulation, channel, and detector can be described in additive white
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Gaussian noise channel (AWGN) and binary symmetric channel (BSC) [11]. The probability of random bit error rate p , also called crossover probability, can be computed based on the system parameters,
⎛ 2 Eb p = Q⎜ ⎜ N 0 ⎝
⎞ ⎟ ⎟ ⎠
(3.17)
where Q(x) is the Q function (Gaussian distribution), the quantity Eb / N 0 is the ratio of energy per bit to noise power spectral density or frequently called the bit signal to noise ratio (SNR)
Figure 3.14: Codeword transmission and Binary Symmetric Channel
Probability of the symbol error rate Puncoded for the symbol which consist of l bits is given by Puncoded = 1 − (1 − p ) l
(3.18)
Probability of a block decoding error Pcoded for the block code which consist of n bits is given by
Pcoded =
n
⎛ n⎞
∑ ⎜⎜ i ⎟⎟ p (1 − p) ⎝ ⎠
i =t +1
i
n −i
(3.19)
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n ⎛ n⎞ from ∑ ⎜⎜ ⎟⎟ p i (1 − p) n −i = 1 i =0 ⎝ i ⎠
t ⎛ n⎞ Pcoded = 1 − ∑ ⎜⎜ ⎟⎟ p i (1 − p) n −i i =0 ⎝ i ⎠
(3.20)
⎛ n⎞ n! and t is error correcting capability of the block code. Where ⎜⎜ ⎟⎟ = ⎝ i ⎠ i!(n − i )!
3.4 Digital Line Codes As shown in Figure 3.9, the digital line coding or digital modulation is used in digital communication between the transmitter and the receiver. When binary data is transmitted over a channel, it must be sent via some analog format that can encode the individual 0’s and 1’s of which it is comprised. This algorithm is called a line code. There are many different types of line codes, which differ of their complexity, efficiency and reliability. This part will present some line codes that frequently use in many digital transmissions. The following are some of the desirable properties of a line code [3]: •
Self–Synchronization: There is enough timing information built into the code
so that bit synchronizers can extract the timing or clock signal. A long series of binary 1’s or 0’s should not cause a problem in time recovery •
Low Probability of Bit Error: Receivers can be designed that will recover the
binary data with a low probability of bit error when the input data is corrupted by noise. •
A Spectrum that is Suitable for the Channel: In some cases DC component
should be avoided, e.g. of the channel has a DC blocking capacitance. In addition, the signal bandwidth needs to be sufficiently small compared to the channel bandwidth. •
Transmission Bandwidth: This should be as small as possible
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3.4.1 The Popular Line Codes
Figure 3.15: Line Codes
•
Non Return to Zero (NRZ): As shown in Figure 3.15, the rule of NRZ is to
send a positive voltage, when a digital data is ‘1’ and to send a ground voltage, when a digital data is ‘0’. The NRZ line code has the advantage of require the minimum bandwidth and simplest to implement but it has the disadvantage of lacking clocking information for receiver synchronization that make it cannot transit if there is a long string of identical ‘0’ or ‘1’. •
Return to Zero (RZ): The RZ code, as shown in Figure 3.15, transits from a
ground voltage to a positive voltage at start of interval and then transit from a positive or negative voltage to a ground voltage at middle of interval, when a digital data is ‘1’ and sends a ground voltage, when a digital data is ‘0’. For the problem of transmitting a long string of ‘0’ or ‘1’ in NRZ. The RZ can be fixed the problem with long string of ‘1’ but if there is a long string of ‘0’, it still is a problem. The RZ still has disadvantages of a long string of ‘0’ and lacking clocking information for receiver synchronization. •
Manchester: The rule of Manchester code is to transit from a ground voltage to
a positive voltage in middle of interval, when a digital data is ‘1’ and to transit from a positive voltage to a ground voltage in middle of interval, when a digital data is ‘0’.
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For the problems of NRZ, the Manchester line code has the advantage of having the property that they contain clocking information which may be extracted by the receiver and solving the problem of transmitting a long string of ‘0’ or ‘1’. However, it has the disadvantage of requiring twice the bandwidth of the NRZ code because the pulses are half the width. In the context of digital line coding, it is clear that the Manchester digital line code will be the safest for data transmission. However, Manchester code requires a painfully high bandwidth. Because of the signal processing unit performance, data transmission bandwidth, cable bandwidth limitation and the latency of 1 µs in the requirement of this work, the digital transmission system cannot be implemented Manchester code. My concept of the measurement system will use the NRZ code in the digital line coding process.
3.5 Data Transmission Technologies Nowadays, there are several methods and technologies to transmit digital data over a transmission channel. The Figure 3.16 shows the speed and distance coverage of some familiar data transmission choices.
Figure 3.16: Approximate Signaling Rates vs. Transmission Distance for Various Interfaces
As seen in Figure 3.16, signaling rate eventually decreases as transmission distance increases. This section shows single-ended data transmission systems (as employed in BTL, GTL, GTLP, TIA/EIA–232, etc.) and differential transmission systems (as used
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with TIA/EIA-422, TIA/EIA-485, TIA/EIA–644 (LVDS), etc.). Each method of transmission has benefits and disadvantages.
3.5.1 Single-Ended vs. Differential The Figure 3.17 shows the circuit schematic diagram of a single-ended transmission system and a differential transmission system.
(a) Single-Ended
(b) Differential
Figure 3.17: Circuit Schematic Diagram (a) Single-Ended Interface, (b)Differential Interface
Single-Ended Transmission: Single-ended transmission is performed by using one
signal line for each information channel and a common ground return path shared among numerous information channels. The Figure 3.17 (a) shows the electrical schematic diagram of a single-ended transmission system. Single-ended receivers interpret the logical state at their inputs based upon the voltage at the single input line with respect to ground. The advantages of single-ended transmission are simplicity and low cost of implementation. A single-ended system requires only one line per signal. It is therefore ideal when cabling and connector costs are more important than the signaling rate or transmission distance. The main disadvantage of the single-ended solution is its relatively poor noise performance at high signaling rates or long distances. Because the noise coupled to the circuit adds to the signal voltage, it is susceptible to data errors.
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Differential Transmission: Differential transmission addresses many of the
shortcomings of single-ended solutions by using a pair of signal lines for each information channel. The Figure 3.17 (b) shows an electrical schematic diagram of a differential transmission system. The differential driver uses a pair of complementary outputs to indicate the state transmitted. The differential receiver detects the voltage difference between the signal pair, rather than relative to ground, to determine its output state. This mode of transmission has several important advantages over single ended. We can see the fundamental advantage in the derivation of the differential input voltage, V ID , in Figure 3.17(b). The noise sources V N and VG add to the input signals VIA and VIB , just as with the single-ended circuit, but by taking the difference between the two
input voltages at the receiver, the common noise terms are cancelled from the desired signal. The differential receiver accomplishes this and, with small differential input voltage thresholds, maintains high signal-to-noise ratios.
Table 3.2: Comparison between Single-Ended and Differential Signaling
Criterion Speed Susceptibility to radiated EMI Radiation of EMI Cost Common-mode voltage range Power consumption
Single Ended Low to moderate High High Low Low Moderate to high
Differential Moderate to high Low Low to moderate Moderate Low to high Low to moderate
In this context, it is clear that the differential transmission has many advantages, including help to reduce noise during data transmission and eliminate the EMI problems.
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3.5.2 LVDS Transmission A popular type of differential transmission technologies is Low-Voltage Differential Signaling (LVDS) [14], [15]. LVDS is a differential transmission technology which delivers high data rate while consuming significantly less power than another transmission technology. LVDS works by switching current from a current source through a differential line pair. The current loop is completed by placing a 100Ω termination resistor across the differential line pair. The resistor creates a voltage swing across the input ports of LVDS receiver.
Figure 3.18: Simplified diagram of LVDS Driver and receiver
As discussed in the section above, the differential transmission can improve the safety of transmitting data through noisy environment. LVDS is a differential signaling technology which has many advantages, such as high speed, low power, low cost, and enhanced noise immunity. However, LVDS also has some disadvantage of Transmission distance and Transmission option. Because of its high speed and low voltage, LVDS is not suitable for long distance transmission (< 10 meters), and LVDS is suitable for point to point transmission because it is a current switching standard. The disadvantages of LVDS are not likely to be important for the measurement system because the transmission distance between BOARD_1 and BOARD_2 of measurement system is in a range of 3 to 10 meters and they are point to point transmission. For these reasons, LVDS is used in the data transmission part in my concept of the measurement system.
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3.6 Transmission Mediums For transmitting digital information along mediums (or channels), the digital signals can be transmitted in electrical cables, e.g. flat cables, twisted pair cables, coaxial cable, and in optical cables, e.g. optical fiber. The optical cables can transmit the digital signals in the higher data rate and longer distance than electrical cables, but the important drawback of optical fiber is the cost. The optical transmission system is substantially more expensive than electrical transmission system. Because of the reasons of cost-effectiveness of the transmission system, this work will focus to discuss on transmission of digital information through electrical cables. The fiber optic will not be discussed any further in this work. An electrical cable is a typical circuit with distributed parameters [16]. It can be explained by the classical equivalent circuit in Figure 3.19.
R’
L’ C’
R’
dx
Figure 3.19: Classical equivalent circuit of electrical cable
The electromagnetic properties of them are completely determined by parasitic parameters that include the resistance R and the inductive L of the conductors, and the capacitance C and the conductivities G of the insulator. The parameters R and G characterize the energy loss; the resistance R characterizes the heat loss in the wire and the conductivity G characterizes the loss in the insulator. The parameters L and C determine the reactivity of the transmission medium regarded as its frequency properties. The parasitic parameters of an electrical cable, as shown in Figure 3.19, may affect cable signal integrity. The effects of an electrical cable happening more frequently are Attenuation, Crosstalk, Delay skew and Interference from external sources of electromagnetic radiation.
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Figure 3.20: The effects of electrical cables
•
Attenuation: Attenuation is defined as the difference between the levels of the
signal at the transmitter outlet and the receiver inlet, due to loss energy in cable. •
Crosstalk: Since part of the energy of a signal being transmitted through one
transmission medium is converted into electromagnetic radiation that induces currents in neighboring transmission medium. This effect is called crosstalk. Crosstalk superimposed on a signal plays the role of noise. •
Delay skew: In data transmission, frequently, consisting of several transmission
mediums, each of the transmission mediums is characterized by its own time of signal transition from the transmitter to the receiver. •
Interference from external sources of electromagnetic radiation: The signals
being transmitted over the transmission medium can cause interference induced by external sources of electromagnetic radiation. Electromagnetic Interference (EMI) is caused by undesirable radiated electromagnetic. Low frequencies and high amplitudes are characteristic of interferences of this kind.
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For data transmission, the trace of using electrical transmission medium has 2 types, coaxial cables and twisted pair. The transmission systems based on coaxial cables have higher cost, in comparison with the transmission system based on twisted pairs. Twisted pair cabling is a common form of wiring in which two conductors is wound around each other for the purposes of canceling out electromagnetic which can cause crosstalk.
Figure 3.21: Twisted pair cabling
And in LVDS transmission, the quality and type of cable used for LVDS signals is crucial for reducing noise on the LVDS transmission line. For balanced data transmission in LVDS, twisted-pair cable is recommended since it provides two identical conductors to transmit the signal and its complement. Any distortion affects both conductors equally. Therefore, the differential signal does not change. The twisted pair cables come as shielded and unshielded types depending on whether the individual twisted pairs or core have an auxiliary shielding cover or not. Such classification makes it possible to define four main cable product types, i.e., along with unshielded cables (UTP), cables with an overall outer shield (S/UTP), with shields for each pair (STP), and with simultaneous shielding of both the pairs and core (S/STP). Shielding is basically used to increase the parameters crosstalk attenuation, reduce the electromagnetic emission level, and increase the noise immunity.
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Figure 3.22: The types of twisted pair
Table 3.3: Comparison the types of shielded twisted pair
a b
c d
Shield Unshielded Twisted pair (UTP) Shielding of each pair (STP)
Shielding results • Decreased EMI factor • Increased protection from external noises • Increased Crosstalk attenuation Common shield for all pair (S/UTP) • Decreased EMI factor • Increased protection from external noises Shielding of each pair + • Decreased EMI factor outer shield around all pairs (S/STP) • Increased protection from external noises • Increased Crosstalk attenuation • Increased mechanical reliability
Based on the above information, a twisted pair cable is a suitable transmission medium for my concept. And it is clear that a shielded twisted pair can increase the parameters crosstalk attenuation and reduce the electromagnetic emission level. However, the shielding cost is relatively expensive.
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3.7 My Concept The above sections showed the information of sensors, signal conditioning circuits, ADCs, the digital transmission method, error control codes, digital line codes, data transmission technologies and transmission mediums. Based on this information, the block diagram of my concept of the measurement system is shown in Figure 3.23.
DIGITAL PART
ANALOG PART Analog voltage signals
RESISTIVE DIVIDER AND ISOLATED
VSEN_1 VSEN_2 VSEN_3
VADC_1 VADC_2 VADC_3
DATA TRANSMISSION
VDATA_1[11:0] VDATA_2[11:0] VDATA_3[11:0]
THE SERIALIZED DATA STREAM OF 1 CHANNEL TRANSMITS IN ONE TRANSMISSION CHANNEL (6 TRANSMISSION CHANNELS)
SIGNAL PROCESSING UNIT_1
BOARD_1
3 channels
Digital parallel signals 12 bits per channel
SIGNALS CONDITIONING
TRNSFORMER
6X ADCs
OPEN-LOOP SIGNALS HALL EFFECT 3 channels CONDITIONING SENSORS
ERROR CORRECTING HAMMING ENCODER
SIGNAL PROCESSING UNIT_2
TWISTED PAIR
ERROR CORRECTING HAMMING DECODER
TWISTED PAIR TWISTED PAIR TWISTED PAIR TWISTED PAIR
SERIALIZER AND NRZ ENCODER
BOARD_2
72 bits
DESERIALIZER AND NRZ DETECTOR
TWISTED PAIR
CONTROLLER UNIT
3 PHASES VOLTAGE
Analog Voltage Conditioned Signals
INTERFACE TO
V_1 V_2 V_3
Analog Voltage Sensed Signals
6 X LVDS Receivers
Required BW 825 kHz
6 X LVDS Line Drivers
Amplitude range [-375V ... +375V]
3 PHASES CURRENT I_1 I_2 I_3
ISEN_1 ISEN_2 ISEN_3
Analog current signals Amplitude range [-330A ... +330A]
Analog Voltage Sensed Signals
IADC_1 IADC_2 IADC_3 Analog Voltage Conditioned Signals
IDATA_1[11:0] IDATA_2[11:0] IDATA_3[11:0]
TX 1 ... 6
Differential Signaling
RX 1 ... 6
Digital parallel signals 12 bits per channel
INF_DATA Digital parallel signals 72 bits 12 bits per channel
Required BW 825 kHz
Figure 3.23: Block Diagram of my concept
As shown in Figure 3.23, my concept of the measurement system consists of six measurement channels for measuring the three-phase voltages and the three-phase currents. In BOARD_1, the three-phase voltages are sensed by the three voltage sensors (the combination of the resistive divider and the transformer sensors) and the three-phase currents are sensed by the three current sensors (Open-loop Hall Effect sensors). Then the six sensed signals are conditioned and converted to the six 12-bit parallel digital data words by the signal conditioning circuits and the ADCs. The six converted digital data words are processed in the Signal Processing Unit_1, which is a
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FPGA. The processes of the Signal Processing Unit_1 are the Hamming encoding process and the serializing in NRZ code process. The output codewords of Signal Processing Unit_1 are the six serial bit streams. At this point, the six serial bit streams are driven into the twisted pair cables by the six LVDS drivers. In BOARD_2, the six LVDS receivers receive the six transmitted bit streams from the twisted pair cables. Then the six received bit streams are processed in the Signal Processing Unit_2, which also is a FPGA. The processes of Signal Processing Unit_2 are the deserializing process and the Hamming decoding process. The serial transmission of my concept of the measurement system transmits the serialized data stream in the six channels. The six channels carry the measured data of the three-phase voltages and the three-phase current, as shown in Figure 3.24.
TX 1 ... 6
RX 1 ... 6 Received Signals
Transmitted Signals Signal Processing Unit_1
CH1 = VDATA_1[11:0] CH2 = VDATA_2[11:0] CH3 = VDATA_3[11:0] CH4 = IDATA_1[11:0] CH5 = IDATA_2[11:0] CH6 = IDATA_3[11:0]
12 bits
Signal Processing Unit_2
Hamming Encoder
Hamming Decoder
12 bits
12 bits
Data Transmission Unit
12 bits 12 bits 12 bits 12 bits
12 bits
Serializer And NRZ Encoder
12 bits 12 bits
Deserializer And NRZ Detector
12 bits 12 bits
CH1 = INF_DATA[11:0] CH2 = INF_DATA[23:12] CH3 = INF_DATA[35:24] CH4 = INF_DATA[47:36] CH5 = INF_DATA[59:48] CH6 = INF_DATA[71:60]
Digital Parallel signals 6 Channels 72 bits
Digital Parallel signals 6 Channels 72 bits
TX 1 ... 6 RX 1 ... 6
Data 12 bits
Serialized Data Stream
Each channel
Redundant bits
1 Codeword
Figure 3.24: Data Transmission in my concept
As discussed in the above section, the focus of this work is on the safety of data transmission though a noisy environment. The data transmission is a section in the digital part of my concept. Therefore the analog part which senses and conditions signals will not be further discussed and implemented in the test system. For testing the digital part of my concept of the measurement system, the digital part will be physically implemented in a test system in the next chapter.
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4 Physical Implementation From my concept of measurement system in the previous chapter, this chapter shows the test system which is able to test the digital part of my concept. The test system represents only one measurement channel of the digital part in Figure 3.23.
4.1 Test System The block diagram and the picture of the test system are shown in Figure 4.1. The test system represents only one measurement channel of the six measurement channels. Because the behavior of the measurement channel being tested is similar to the others, therefore the results of one measurement channel can represent all the others.
DISPLAY-ERROR BOARD Error Correcting err_c[13:0]
Error Dectecting err_d[13:0]
FPGA BOARD ADC BOARD
din_adc[9:0]
dout_dac[11:0]
FPGA_1 (TX)
DAC BOARD
FPGA_2 (RX)
+2V
+5V neo
e_syn
d_syn
ndi
0V
0V
LVDS DRIVER
LVDS RECEIVER LVDS BOARD
Twisted Pair Cables
Figure 4.1: The Test System of My Concept
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The test system consists of ADC BOARD, FPGA BOARD, LVDS BOARD, DISPLAY-ERROR BOARD and DAC BOARD. In FPGA BOARD, the Signal Processing Unit_1 and Signal Processing Unit_2 in my concept are programmed by VHDL in the same FPGA chip. In the test system the Signal Processing Unit_1 and Signal Processing Unit_2 are called FPGA_1 and FPGA_2, respectively. In Figure 4.1, ADC BOARD converts the analog input signal to digital signals and sends the converted digital signals to FPGA BOARD. FPGA_1 in FPGA BOARD receives the converted digital signals, processes them by Hamming encoding, serializes the encoded signals and sends the serialized stream to LVDS BOARD. LVDS BOARD uses the LVDS data transmission technology to transmit and receive the serialized stream over a twisted pair cable. FPGA_2 in FPGA BOARD receives the serialized stream from LVDS BOARD and reprocesses it by Hamming decoding and deserializing (serial to parallel converting). The Hamming decoding process in FPGA_2 detects and corrects errors in the received data and sends the number of corrected errors and detected errors to DISPLAY-ERROR BOARD. The reprocessed digital signals are sent to DAC BOARD. DAC BOARD reconverts the digital signals to the analog signal to compare with the analog input signal of ADC BOARD checking the functionality of the test system. The analog input signal of ADC BOARD is generated by a function generator. And all boards of the test system are supplied by a laboratory power supply.
4.1.1 ADC BOARD The ADC BOARD in test system is the evaluation board of AD9200 from Analog Devices, as shown in Figure 4.2. The AD9200 is a pipeline architecture ADC which has 3 clock cycles pipeline latency [17]. Maximum conversion rate of AD9200 is 20 MHz, but in the test system it is run at 10 MHz. Therefore the maximum delay in ADC BOARD is expressed by Pipeline latency + Data Valid Delay =
1 × 3 cycles+ 25 ns = 325 ns 10 MHz
(4.1)
The analog input signal range of the test system is the same input voltage range of the currently used measurement system, 0V to +2V. The digital converted data of it is the 10-bit digital parallel data which is identified by din_adc[9:0].
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Figure 4.2: ADC BOARD (Evaluation Board of AD9200)
4.1.2 FPGA BOARD An important section of the digital part in my concept is the signal processing section. The test system uses a FPGA which is programmed by VHDL to process signals in the FPGA_1 and FPGA_2 section, as shown in Figure 4.1. The test system uses the evaluation board of FPGA APA075 from Actel, APA-EVAL-BRD075 [19] as FPGA BOARD. The design and source codes of FPGA_1 and FPGA_2 will be shown in chapter 4.2. The list of connecting pins of FPGA BOARD can be seen in Appendix B.
Figure 4.3: FPGA BOARD (Evaluation Board of APA075)
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4.1.3 LVDS BOARD My concept uses the LVDS technology for data transmission. LVDS BOARD is a board which consists of LVDS drivers and receivers, SN65LVDS1 and SN65LVDT2 of Texas instruments, respectively. Their data sheet can be seen in [18]. The drivers and receivers in LVDS BOARD transmit data in serial stream over a transmission medium. The transmission medium is a twisted pair cable. The twisted pair cables, which are used in this test, are the category 5 26AWG 4 pairs with common shield for all pair (S/UTP) commonly used on network application (also called network cable). In this test, the following four different cable lengths: 1, 3, 7.5 and 10 meters, are tested. The schematic circuit and the picture of LVDS BOARD are shown in Figure 4.4.
+3.3 V
+3.3 V
Differential Signaling
SN65LVDS1 +Dout
+Din
neo
SN65LVDT2
ndo
100 ohm
-Dout
-Din
SN65LVDS1 +Dout
+Din
+3.3 V
+3.3 V
e_syn
100 ohm
-Dout
SN65LVDT2
d_syn
-Din
Twisted Pair Cables
Figure 4.4: LVDS BOARD
4.1.4 DAC BOARD DAC BOARD is used to observe the processed digital signals, dout_dac[11:0], from FPGA_2. DAC BOARD is a board which consists of a digital to analog converter (DAC), AD767 from Analog Devices [20]. The picture of DAC BOARD is shown in Figure 4.5.
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Figure 4.5: DAC BOARD
4.1.5 DISPLAY-ERROR BOARD DISPLAY-ERROR BOARD is a board which is used to observe the number of corrected errors and the number of detected errors from the Hamming decoding process in FPGA_2. DISPLAY-ERROR BOARD consists of signal drivers, UDN2981A [21], and seven-segment LED which can display numbers from 0 to 99. The schematic circuit and the picture of DISPLAY-ERROR BOARD are shown in Figure 4.6.
Figure 4.6: DISPLAY-ERROR BOARD
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4.2 FPGA Design The most important part in my concept is to process the signals in the digital transmission system. The test system uses a FPGA, which is programmed by VHDL, to process the signals. The FPGA consists of 2 parts: FPGA_1, which acts like the transmitter and FPGA_2, which acts like the receiver. The process in FPGA is shown in the functional block diagram in Figure 4.7. For the FPGA design, the process is divided into 4 processes: Clock Control Generating process, Data Loading process, Hamming Coding process, and NRZ Coding and Serializing process. They will be discussed in the next sections. The VHDL codes of all blocks in the FPGA are shown in Appendix C.
Figure 4.7: Inside of FPGA design
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4.2.1 Clock Control Generating The clock control generating process is a process to generate clock signals to control the other blocks in the FPGA. This process consists of 3 blocks: CLK_DIVIDER, PLL_1 and PLL_2. •
CLK_DIVIDER: The process of CLK_DIVIDER block is to generate the clock
signal clk_2 that controls signals receiving from ADC BOARD. Consequently, the clock control is a signal which controls the sampling rate of ADC BOARD to FPGA BOARD. The FPGA BOARD has a 40 MHz oscillator which generates the signal clk on the board [19] and the required sampling rate (refer from chapter 3.2.1) is higher than 1.65 MHz. Due to the limited performance of FPGA, the test system can not process the signal at the sampling rate 1.65 MHz. Therefore, for testing, the test system uses the sampling rate at 1.0526 MHz. This sampling rate is the maximum possible rate of this FPGA. For generating the clock control 1.0526 MHz clk_2, in general, it can generate by dividing the 40 MHz clk by 38. The conceptual diagram of clock generating is shown in the Figure 4.8.
Figure 4.8: Conceptual diagram of the CLK_DIVIDER block
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PLL_1 and PLL_2: These blocks are phase lock loop (PLL) blocks in the
FPGA which are created by SmartGen in the Libero IDE program [22]. The PLL_1 generates the clock control clk5x_1 to control the blocks in FPGA_1: ECC_EN block and NRZ_EN block. And the PLL_2 generates the clock control clk5x_2 to control the blocks in FPGA_2: NRZ_DE block, ECC_DE block and BIN_TO_SSEG block. The minimum frequency of clock control signals, clk5x_1 and clk5x_2, can be expressed by: Conversion rate of ADC (frequency of clk_2)
= 1.0526 MHz
The number of bits of codeword (chapter 4.2.3)
= 18 bits
Over-sampling factor (chapter 4.2.4)
= 5 times
The minimum frequency of clk5x_1 and clk5x_2 is ADC conversion rate × Codeword bits × Over-sampling factor
(4.2)
1.0526MHz × 18bits × 5 = 94.73MHz
In this test system I use the clock control clk5x_1 and clk5x_2 signals at 110 MHz. The frequency of clk5x_1 and clk5x_2 signals is higher the minimum frequency to prevent the system from having some delays in the processes in FPGA and in the devices, e.g. ADC, and LVDS driver and receiver.
4.2.2 Data Loading After the clock control generating process generated the clock control signal clk_2, the data loading process, which is represented by LOADER_DATA block in Figure 4.7, uses this signal to control signals receiving from ADC BOARD. The converted digital signal from ADC BOARD is a digital parallel 10-bit din_adc[9:0]. Because the test system is required to test the 12-bit data dout_load[11:0] processing (from the requirements of this work, chapter 1.1), the data loading process will add digital ‘0’ signals into two least significant bits that can be seen in Figure 4.9.
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Figure 4.9: Conceptual diagram of the LOADER_DATA block
4.2.3 Hamming Coding As discussed in chapter 3.3, error control codes can improve reliability and reduce probability of error in digital transmission. My concept of measurement system uses Hamming codes as error control codes. Hamming codes are error correcting codes which are one-way transmission codes (FEC) and can correct the presence of single bit errors in a codeword. The advantages of Hamming codes are that it easily implements in FPGA by using a look up table or XOR operators and it uses a few clock cycles to encode and decode. The data dout_load[11:0] is a 12-bit digital parallel data. The general classes of Hamming codes are not suitable for 12-bit data. Therefore this work uses the shortened Hamming codes (refer from chapter 3.3.3.1). The general class of Hamming code, which is chosen, is Hamming code (63,57). The generator polynomial and GF (2 6 ) of Hamming code (63,57) are shown in Appendix A. The shortened Hamming code, which is used, is the shortened Hamming Code (18,12) which is modified from Hamming code (63,57) by the method of Hsiao [13].
4.2.3.1 Hamming Encoding The encoding algorithm is a mathematical method as shown in the equation (3.5), where the message X is the received data from LOADER_DATA block and the generator matrix G of shortened Hamming code (18,12) is shown in the following matrix.
4 Physical Implementation ⎡1 ⎢0 ⎢ ⎢1 ⎢ ⎢0 ⎢1 ⎢ 0 G = ⎢⎢ 1 ⎢ ⎢0 ⎢1 ⎢ ⎢0 ⎢ ⎢1 ⎢⎣0
1 0 1 0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 1 1 0 1 0
0 1 1 0 0 1 0 1 1 0 0 1
61
0 1 0 1 1 0 0 1 0 1 1 0
0 1 0 1 0 1 1 0 0 1 0 1
1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 0 1 0
0⎤ 0⎥⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ 0⎥ ⎥ 0⎥ ⎥ 0⎥ 1⎥⎦
The Hamming encoding process is the ECC_EN block in Figure 4.7. The algorithm of Hamming encoding process, which is programmed by VHDL, is presented in the flowchart in Figure 4.10.
4.2.3.2 Hamming Decoding The Hamming decoding process uses the equation (3.12) where the parity check matrix H of the shortened Hamming code (18,12) is shown in the following matrix and the
received codeword D is the received codeword from NRZ_DE block. ⎡1 ⎢0 ⎢ ⎢0 H =⎢ ⎢0 ⎢0 ⎢ ⎢⎣0
0 1 0 0 0 0
0 0 1 0 0 0
0 0 0 1 0 0
0 0 0 0 1 0
0 0 0 0 0 1
1 1 1 0 0 0
0 0 0 1 1 1
1 1 0 1 0 0
0 0 1 0 1 1
1 1 0 0 1 0
0 0 1 1 0 1
1 1 0 0 0 1
0 0 1 1 1 0
1 0 1 1 0 0
0 1 0 0 1 1
1 0 1 0 1 0
0⎤ 1⎥⎥ 0⎥ ⎥ 1⎥ 0⎥ ⎥ 1⎥⎦
The outcome of Hamming decoding is syndrome S. The syndrome can be accomplished as follows: if the syndrome is zero assuming that no error occurred, if the syndrome is nonzero and contains an odd number of 1’s assuming that a single error occurred and it can be corrected by the following Table 4.1, and if the syndrome is nonzero and it contains an even number of 1’s that an uncorrectable error pattern has been detected.
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Furthermore, the Hamming decoding process counts the number of errors which were corrected and detected and sends the number of corrected errors and the number of detected errors in seven-segment codes to DISPLAY-ERROR BOARD for displaying numbers in the seven-segment LED. The Hamming decoding process is the ECC_DE block in Figure 4.7. The algorithm of the Hamming decoding process is shown in Figure 4.11 and the VHDL code of it is shown in Appendix C.
Table 4.1: Syndrome Bits and Look Up table
Syndrome Bits LSB MSB 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1
Look Up Table Error Free bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 bit 17
LSB 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
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False
Chip Enable (din_ecc_v = ’1’)
Ture
Store Input din_ecc in Register din_reg
Clock-Synchronized Combinational Circuit (XOR) C=MxG C = codeword registers (cout_reg) (18 bits) M = input registers (din_reg) (12 bits) G = gernerator matrix
Provide output codeword and valid signal Data: cout_ecc[17:0] Valid: cout_ecc_v
Figure 4.10: Flowchart of the ECC_EN block
Figure 4.11: Flowchart of the ECC_DE block
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4.2.3.3 Performance of Error correcting code For the performance of error correcting code calculation, I use probability of error (also called Bit Error Rate) to calculate and compare the transmission system which is installed Hamming code (18,12) and the transmission system which is not installed error correcting code. From the equation (3.18), the probability of error for the uncoded transmission system which transmits 12-bit data is given by Puncoded = 1 − (1 − p )
12
(4.3)
And from the equation (3.20), the probability of error for the Hamming encoded (18,12) transmission system is given by 1 ⎛ n⎞ n −i PHam (18,12 ) = 1 − ∑ ⎜⎜ ⎟⎟ p i (1 − p ) i =0 ⎝ i ⎠
or
(
(4.4)
PHam (18,12 ) = 1 − (1 − p ) + 18 p(1 − p ) 18
17
)
The transmission channel is approximated by Additive White Gaussian Noise (AWGN) Channel and Binary Symmetric Channel (BSC). The p , probability of random bit error, is given in the term of Gaussian distribution which is shown in the equation (3.17). ⎛ 2 Eb p = Q⎜ ⎜ N 0 ⎝
⎞ ⎟ ⎟ ⎠
The comparison of probability of error for the uncoded system, equation (4.3), and for the Hamming coded (18,12) system, equation (4.4), is shown in Figure 4.12. The m-files for illustrating this comparison are shown in Appendix D.
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Figure 4.12: Comparison of probability of error for the Hamming (18,12) coded system and the uncoded system
As seen in Figure 4.12, it illustrates the relationship between the ratio of energy per bit to noise power spectral density Eb / N 0 and the probability of error for the uncoded transmission system and the Hamming coded (18,12) transmission system. At the same quantity of Eb / N 0 , the probability of error for the uncoded transmission system is more than the probability of error for the Hamming coded (18,12) transmission system. And in the other hand, it is apparent that the Hamming coded (18,12) transmission system has a 3 dB advantage over the uncoded transmission system since the uncoded transmission system requires a Eb / N 0 that is 3 dB larger than that for the Hamming coded (18,12) transmission system for the same probability of error.
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4.2.4 NRZ Coding and Serializing The NRZ coding and serializing process is a process to transmit and receive data in a serialized stream data with NRZ line code form (refer from chapter 3.4). This process consists of 2 processes: the NRZ encoding process and the NRZ decoding process which are represented as NRZ_EN block and NRZ_DE block in Figure 4.7, respectively.
4.2.4.1 NRZ Encoding The NRZ encoding is a process to transmit the codeword signals from the Hamming encoding process to LVDS BOARD in a NRZ serialized stream data neo. The codeword of the Hamming code (18,12) is a 18-bit parallel data. Therefore, the NRZ encoding process serializes the 18-bit parallel codeword to a serialized stream data.
4.2.4.2 NRZ Decoding The NRZ decoding is a receiving process which receives the serialized stream data ndi from the transmission medium. And then it reconverts the received serialized data to the 18-bit parallel data sending the converted parallel data to the Hamming decoding process.
1 codeword Codeword 18-bits neo, ndi
bit17
bit16
bit15
bit14
bit13
bit12
bit11
bit10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Sample signal 5x Oversampling Synchronized signal e_syn, d_syn
Figure 4.13: Serialized communication in the Test System
The serialized stream data transmits and receives at the over-sampling factor of 5. The over-sampling in the digital transmission can improve the SNR of the transmitted signal. The sample signal, as shown in Figure 4.13, is a signal at receiving-side. The receiver detects the bit-symbol at the middle of a 5-times over-sampling. And this work uses the synchronized signal to synchronize the transmitter and receiver at the first bit (most significant bit, MSB) of codeword as shown in Figure 4.13. The processes of the
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NRZ encoding process and the NRZ decoding process are shown in the flowcharts in Figure 4.14 and Figure 4.15, respectively.
Figure 4.14: Flowchart of the NRZ_EN block
Figure 4.15: Flowchart of the NRZ_DE block
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4.2.5 Simulation Results In above sections, we discussed the processes in FPGA_1 and FPGA_2 of the digital transmission in my concept. For the FPGA implementation, this work uses Libero IDE version 7.1 [22], a program that Actel supports for use with their FPGA. It provides primarily methods of creating designs to a user: code design, synthesis, place and route, layout and program into a FPGA. All VHDL source codes, which are used in this work, are shown in Appendix C. The VHDL source codes of the processes, which were implemented into FPGA BOARD, can be simulated using a simulator program. This work uses ModelSim Actel 6.1b [23] program for simulation. The Figure 4.16 and Figure 4.17 show the simulated waveforms.
Figure 4.16: Simulated Waveforms of All Processes in FPGA BOARD
The Figure 4.16 shows the simulated waveforms of all processes in FPGA BOARD which the input stimuli were generated by the testbench TB_TOP_LEVEL (shown in Appendix C). The simulated waveforms show that the processes in FPGA BOARD are working correctly. CLK_DIVIDER block generates the clock signal 1.0526 MHz clk_2. LOADER_DATA block loads data from ADC BOARD. ECC_EN block encodes the data with Hamming code (18,12). NRZ_EN block serializes a codeword and transmits a serialized stream data with a synchronized signal. NRZ_DE block receives a serialized stream data and converts to an 18-bit parallel codeword. ECC_DE block decodes a
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codeword, corrects it and counts errors. SEVEN_SEGMENT block converts a binary code of the number of errors to a seven segment code for displaying numbers in the seven-segment LED. The all processes in FPGA use 102 clock cycles of clk5x_1 and clk5x_2 altogether. The clk5x_1 and clk5x_2 are a 110 MHz clock signal. Therefore the latency of all processes in the FPGA is 927.273 ns. It can achieve the requirement of this work that the latency is in the range of 1 µs. The Figure 4.17 shows the simulated waveforms of the Hamming decoding process which the input stimuli were generated by the testbench TB_ECC_DE (shown in Appendix C). In this figure, it shows that a codeword was decoded and if the syndrome of the Hamming decoding process was nonzero, the decoded data was corrected by using look up table.
Figure 4.17: Simulated Waveforms of Hamming Decoding Process
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4.3 Experimental Results One measurement channel of the digital part of my concept of the measurement system in chapter 3 was physically implemented in the test system, as shown in Figure 4.1. In this chapter, the test system was tested in the laboratory environment and in the operational environment.
4.3.1 Laboratory Environment Testing The test system was tested in the laboratory environment as shown in Figure 4.18. The test system was tested to transmit and receive over different twisted pair cable lengths: 1m, 3m 7.5m and 10m. All twisted pair cables in this test are the category 5 26AWG 4 pairs with common shield for all pair (S/UTP).
Figure 4.18: Test in the Laboratory Environment
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4.3.1.1 Functionality Testing Firstly, the test system was tested for the functionality of the test system by connecting the function generator to the ADC BOARD input, and the resulting analog output signal of DAC BOARD was observed on the oscilloscope.
Figure 4.19: Experimental Waveforms of ADC BORAD Input and DAC BOARD Output in the Laboratory Environment
As seen in Figure 4.19, the function generator generated the input signals sine and triangle waveforms which are a 2 Volt peak-to-peak (0 V to 2 V) 100 kHz signal. The output signals of DAC BOARD were also sine and triangle waveforms. They were similar to the input waveforms. Therefore, it is clear that the functionality of the test system is working correctly.
4.3.1.2 Bit Error Rate Testing Bit error rate (BER) testing is a method to determine the signal quality and the performance of a transmission system. The standard equation of a bit error rate measurement is: ⎛ number of bit error ⎞ ⎟⎟ BER = ⎜⎜ ⎝ total number of bit ⎠
(4.5)
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For BER test, the ADC BOARD was connected with a function generator which provides an input sine waveform 2 Volt peak-to-peak (0 V to 2 V) 100 kHz signal. This test method was tested with different cable lengths: 1m, 3m, 7.5m and 10m. Every cable was tested for 1 hour. The number of bit error was observed on DISPLAY-ERROR BOARD. Testing Conditions
Data rate
= 22 Mbps
Testing time = 3600 seconds (1 hour)
Codeword
= 18 bits (NRZ)
Total bits
= 7.92 × 1010 bits
Cable lengths = 1m, 3m, 7.5m and 10m The results of this test are shown in Table 4.2. In practical application, the required BER might be less than 10 −9 or less than one bit error in 1 billion bits sent.
Table 4.2: Errors Testing in the Laboratory Environment
Cable Length (m) 1 3 7.5 10
Laboratory Environment Corrected Detected BER Errors Errors 0 0 < 7.92 × 10 −10 0 0 < 7.92 × 10 −10 0 0 < 7.92 × 10 −10 0 0 < 7.92 × 10 −10
Table 4.2 shows that no errors were detected and corrected during this test. The BER test in the laboratory environment concludes that in the range of the twisted pair cable length from 1 m to 10 m the test system of my concept run error free, or at least the BER of the test system is less than 7.92 × 10 −10 . It is clear that the BER of the test system in the laboratory environment less than the required BER of 10 −9 . The results from this test show that the FPGA_1, which acts like transmitter, and the FPGA_2, which acts like receiver, in FPGA BOARD are running correctly and the LVDS data transmission technology, which is used in my concept, can transmit data with very low bit error rate in the range of 10 meters.
4.3.1.3 Data Transmission Testing The test system of my concept of measurement system uses the LVDS technology in a point-to-point configuration for data transmission. This test observes the transmitted
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signals at receiving-side in the laboratory environment as shown in Figure 4.20. This figure is a part of the driver and the receiver in LVDS BOARD in the test system.
Figure 4.20: LVDS Signals Quality test in the Laboratory Environment
The Figure 4.21 shows the measured signals of the LVDS signals at receiving-side, i.e. the single-ended LVDS signals at the LVDS receiver inputs, the differential signal which the LVDS receiver detects and the output of the LVDS receiver signal which is identified as ndi signal.
Figure 4.21: Experimental Waveforms of LVDS Receiver Input and Output in the Laboratory Environment
As shown in Figure 4.21, the LVDS signals, +Din and –Din, transmitted over the twisted pair cable that were influenced by noise. The twisted pair cable is a balanced cable. Therefore, noise appeared equally on each pair and this common-mode noise was rejected by the LVDS receiver because of detecting the differential signal, (+Din) – (–Din), across inputs. For this reason, the output of LVDS receiver, ndi, was low-noise and good quality.
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4.3.1.4 Eye Pattern Measurement The effect of all transmission impairments, i.e. high-to-low transition, low-to-high transition, overshoot, undershoot and noises, can be seen by observing the received signals on an oscilloscope from a diagram called an eye pattern. Eye pattern measurement is a very accurate way to measure the expected signal quality in the data transmission. The effect of impairments is to partially close the eye. As long as the eye is open at least a little in the middle at the sampling time, it is clear that the receiver will detect correctly. If all the space is filled with signal transitions, then detection can be erroneous. In this test, eye pattern measurement measures the LVDS differential signal at receiving-side, which is shown at the test point in Figure 4.20. The measured eye patterns are shown in Figure 4.22.
Figure 4.22: Eye Patterns of the Differential Signals at Receiving-Side in the Laboratory Environment
As seen in Figure 4.22, the measured eye patterns of the differential signals were clearly open in the laboratory environment.
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From the measured eye patterns, jitter measurement is used to measure the amount of sample timing error versus the unit interval as shown in Figure 4.23. The unit interval, t ui , of my concept is 45.45 ns ( 5 × 1 / 110 MHz ). Due to the factor of 5 over-sampling of the transmitter and the receiver of my concept, therefore the maximum jitter allotment is 20 %.
Figure 4.23: Jitter Measurement in a Measured Eye Pattern
Table 4.3: Jitter measurement in the laboratory environment
Cable Length (m) 1 3 7.5 10
Laboratory Environment Crossing jitter Jitter (ps) (%) 960 2.1 400 0.9 580 1.3 1040 2.3
In Figure 4.22 the measured eye patterns of different cable lengths showed that the eyes were effectively open and Table 4.3 showed that the jitter results were relatively low compared with the maximum jitter allotment of 20%. It is clear that in the laboratory environment and in the range of the twisted pair cable length from 1 m to 10 m, the LVDS technology transmits and receives a low-noise and good quality signal and the receiver will detect correctly.
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4.3.2 Operational Environment Testing The experimental results of the test system of my concept in the laboratory environment clearly showed a very good qualitative agreement. The test system was tested again in the operational environment as shown in Figure 4.24.
Figure 4.24: Test in the Operational Environment
The operational environment testing is a test which transmits signals inside of a running UPS system, which is a noisy environment with high levels of EMI. From laboratory environment testing it showed that in the cable length of 10m the test system of my concept was working well and error free. Thus, the different-cable-lengths-test is not required. The operational environment testing uses only the 7.5m-length twisted pair cable. The test system was tested while the UPS is operating under the no-load (0%) condition, the half-load (50%) condition and the full-load (100%) condition.
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4.3.2.1 Functionality Testing The test system of my concept was tested in the operational environment using the same method as described in section 4.3.1.1. The test system was tested while the UPS was operating under the full-load (100%) condition.
Figure 4.25: Experimental Waveforms of ADC BOARD Input and DAC BOARD Output in the Operational Environment at 100% Load Condition
Figure 4.25 shows that the output signals of DAC BOARD were also sine and triangle waveforms. They were similar to the input waveforms. It shows clear that the functionality of the test system is also working correctly in the operational environment.
4.3.2.2 Bit Error Ratio Testing The test system was tested in the operational environment, while the UPS was operating under the no-load condition, the half-load condition and the full-load condition using the same method as described in section 4.3.1.2. The results are shown in Table 4.4. Table 4.4: Error Testing in the Operational Environment
Load Testing (%)
Testing Time (s)
0 50 100
3600 600 20
Operational Environment Corrected Detected BER Errors Errors 0 0 < 7.92 × 10 −10 29 23 3.94 × 10 −9 99 99 4.50 × 10 −7
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It can be noticed from Table 4.4 that the test system ran error free while the UPS was operating under the no-load condition. But while the UPS was operating under the half-load condition and the full-load condition, there were few errors, which were observed by DISPLAY-ERROR BOARD, in the test system. The test system can achieve the required BER of 10 −9 while the UPS was operating under the no-load condition and the half-load condition. But while the UPS was operating under the full-load, it can not satisfy the required BER.
4.3.2.3 Data Transmission Testing This test observes the transmitted signals at receiving-side as shown in Figure 4.26. In the operational environment testing, the test system was tested to transmit over the 7.5 m twisted pair cable while the UPS was operating under a full-load.
Figure 4.26: LVDS Signals Quality test in the Operational Environment
The Figure 4.27 shows the measured signals of the LVDS signals at receiving-side, i.e. the single-ended LVDS signals at LVDS receiver inputs, the differential signal and the output of LVDS receiver signal.
Figure 4.27: Experimental Waveforms of LVDS Receiver Input and Output in the Operational Environment at 100% Load Condition
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The Figure 4.27 shows the measured LVDS signals at receiving-side. The LVDS signals, +Din and –Din, transmitted over the twisted pair cable that were influenced by the very high levels of noise, crosstalk and EMI while the UPS was operating under the full-load condition. This noise were rejected because the LVDS receiver detected the differential signal, (+Din) – (–Din), across inputs. But it did not perform very well in the very high noisy environment under the full-load condition. By this reason, the LVDS receiver could not produce good quality output.
4.3.2.4 Eye Pattern Measurement In this test, eye pattern measurement measures the LVDS differential signal at receiving-side as shown at the test point in Figure 4.26. The measured eye patterns are shown in Figure 4.28.
Figure 4.28: Eye Patterns of the Differential Signals at Receiving-Side in the Operational Environment
As seen in Figure 4.28, while the test system was testing in the operational environment, there was noise in the LVDS differential signals. The noise present in the full-load condition was greater than in the half-load condition and the no-load condition.
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The experimental results of the test system showed that the functionality of the test system was working correctly in both the laboratory environment and the operational environment. In laboratory environment, the test system worked perfectly and ran error free over a twisted pair cable in the range of 10 m. The LVDS signals showed very good quality and the measured eye patterns were clearly open. In operational environment, the test system worked perfectly and ran error free under the no-load condition. Under the half-load condition, the test system had the BER of 3.94 × 10 −9 , which can achieve the required BER of 10 −9 , but under the full-load condition it can not achieve the required BER performance. The measured eye patterns of the LVDS differential signals at receiving-side showed that there was noise which influenced in the signals and the noise present in the full-load condition was greater than in the half-load condition and the no-load condition. The experimental results show that the test system work well and can achieve the requirement of the safety of data transmission in a low to medium noisy environment, such as the laboratory environment condition, the no-load condition and the half-load condition of the UPS system. But in a very high noisy environment, such as the full-load condition of the UPS system, it does not perform well. This problem may be caused by creating the test system on breadboards. The circuits on breadboards are susceptible to noise. The test system can be effectively improved by making out of a printed circuit board (PCB) with a ground plane layer. The results show that in the range of 10 m in a low to medium noisy environment my concept can transmit the measured signals with a high-level of safety.
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5 Conclusion and Future Considerations This chapter contains the conclusion section, which summarizes the results of this work, and the future considerations section, which shows the information to provide for potential improvement of this work.
5.1 Conclusion The purpose of this project is to develop a concept of a measurement system that can improve the safety and reliability of the transmission system through a noisy environment in a UPS system. My concept has six measurement channels for measuring three-phase voltages and three-phase currents. It transmits data by using the digital transmission method as shown in Figure 3.23. The digital transmission in my concept was designed to use the LVDS technology with an error correcting code. The LVDS is a differential transmission technology which results in great noise immunity. The error correcting code, which was used in my concept, is the Hamming code (18,12). The Hamming code (18,12) can correct the presence of single bit errors in a transmitted codeword. Hence, my concept has a 3 dB advantage over the uncoded transmission system. Consequently, the measurement channel in the digital part of my concept of the measurement system was physically implemented in the test system by all signal processing processes programmed in a FPGA. The latency of all processes in the FPGA is 927.273 ns. The experimental results of the test system show that in a low to medium noisy environment, the test system work perfectly and run error free over a twisted pair cable in the range of 10 m. However, in a very high noisy environment, such as the full-load condition of a UPS system, it does not perform well. This problem may be caused by creating the test system on breadboards. The circuits on breadboards are susceptible to noise. The test system can be effectively improved by making out of a PCB with a ground plane layer. The results show that in the range of 10 m in a low to medium noisy environment my concept can transmit the measured signals with a high-level of safety. If DC voltage measurement with galvanic isolation at the battery in the UPS system is required, my concept can also be used by using Close-Loop Hall Effect sensors.
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82
5.2 Future Considerations •
FPGA: The problem of my signal processing design, which is implemented on
FPGA, is the limited performance of FPGA. The APA075 FPGA from Actel, which used in this work, can provide only a 5-times over-sampling in my design. The probability of error in my concept may reduce, if the system operates under a higher over-sampling factor by using a higher-performance FPGA or a FPGA which provides an attractive single-chip solution to serial transceiver (SER/DES) design, e.g. the Virtex-II Pro Platform FPGA from Xilinx. •
Transmission Medium: The EMI problems will be eliminated by using a fiber
optic transmission system. •
Error Correcting Codes: The chances of error will be more reduced by using a
code which has a higher error-correcting capability, such as the Bose, Chaudhuri, and Hocquenghem (BCH) code, the Reed-solomon (RS) code and the convolutional code.
6 Appendix
83
6 Appendix 6.1 Appendix A Galois Field m-tuple representation for GF( q = 2 m ) for 3 ≤ m ≤ 6
GF (2 3 = 8) p(x ) = x 3 + x + 1 1 0 0 0 0 1 0 1 0 0 1 2 1 1 0 3 0 1 1 4 1 1 1 5 1 0 1 6
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
GF (2 4 = 16) p(x ) = x 4 + x + 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 0 0
0 0 0 1 0 0 1 1 0 1 0 1 1 1 1
6 Appendix
84 GF (2 5 = 32) p ( x) = x 5 + x 2 + 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1
0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1
0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1
0 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1
0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 1
1 1 1 0 0 0 1 1 0 1 1 1 0 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 1 1 1 0 0 0 1 1 0 1 1 1 0 1
0 0 0 1 1 0 1 1 1 0 1 0 1 0 0
1 0 0 0 1 1 0 1 1 1 0 1 0 1 0
1 1 0 0 0 1 1 0 1 1 1 0 1 0 1
GF (2 6 = 64) p ( x) = 1 + x + x 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1
0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0
0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1
0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0
0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0
0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1
0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0
1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0
0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1
6 Appendix
85
6.2 Appendix B This Appendix lists a table for ProASIC plus Evaluation Board connection FPGA Board Pin No. 24 128 3 5 7 9 11 4 6 8 10 12 55 56 99 100 143 145 147 149 151 153 144 146 148 150 152 154 127 207 205 203 201 199 197 193 191 189 185 183 181
Description
Connected with
clk rst din_adc(9) din_adc(8) din_adc(7) din_adc(6) din_adc(5) din_adc(4) din_adc(3) din_adc(2) din_adc(1) din_adc(0) neo e_syn ndi d_syn dout_dac(11) dout_dac(10) dout_dac(9) dout_dac(8) dout_dac(7) dout_dac(6) dout_dac(5) dout_dac(4) dout_dac(3) dout_dac(2) dout_dac(1) dout_dac(0) dout_dac_v sseg_c(13) sseg_c(12) sseg_c(11) sseg_c(10) sseg_c(9) sseg_c(8) sseg_c(7) sseg_c(6) sseg_c(5) sseg_c(4) sseg_c(3) sseg_c(2)
Global signals in FPGA
ADC Board
LVDS Board
DAC Board
DISPLAYERROR BOARD
Input / Output Input Input Input Input Input Input Input Input Input Input Input Input Output Output Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
6 Appendix
FPGA Board Pin No. 179 177 206 204 202 200 198 196 194 192 190 188 184 182 180 176
86
Description
Connected with
sseg_c(1) sseg_c(0) sseg_d(13) sseg_d(12) sseg_d(11) sseg_d(10) sseg_d(9) sseg_d(8) sseg_d(7) sseg_d(6) sseg_d(5) sseg_d(4) sseg_d(3) sseg_d(2) sseg_d(1) sseg_d(0)
DISPLAYERROR BOARD
Input / Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
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87
6.3 Appendix C This Appendix presents the VHDL codes which programmed in FPGA as shown in Figure 4.7.
6.3.1 TOP_LEVEL.vhd -------------------------------------------------------------------------------- Title : Top level of Transmission System with NRZ coding -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : TOP_LEVEL.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 01.08.2006 -- Last update : 01.08.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY TOP_LEVEL IS PORT ( -- global signal rst : IN std_logic; clk : IN std_logic;
--
-- ADC clock control -clk_1 : OUT std_logic; -- CANCELED -- input -din_adc : IN std_logic_vector(9 downto 0); -- TX NRZ -neo : OUT std_logic; e_syn : OUT std_logic; -- RX NRZ -ndi : IN std_logic; d_syn : IN std_logic; -- output -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic;
-- output counter -sseg_d : OUT std_logic_vector(13 downto 0); sseg_c : OUT std_logic_vector(13 downto 0) ); END TOP_LEVEL; ARCHITECTURE RTL OF TOP_LEVEL IS
--
COMPONENT CLK_DIVIDER IS PORT ( rst : IN std_logic; clk : IN std_logic; -- input clk 40MHz -- output -clk_1 : OUT std_logic; -- output clk_1 20MHz -- CANCELED clk_2 : OUT std_logic -- output clk_2 1MHz ); END COMPONENT; COMPONENT PLL_1 PORT (
6 Appendix
CLK GLB LOCK ); END COMPONENT; COMPONENT PLL_2 PORT ( CLK GLB LOCK ); END COMPONENT;
88
: in std_logic; : out std_logic; : out std_logic
: in std_logic; : out std_logic; : out std_logic
COMPONENT LOADER_DATA PORT ( -- global input -clk_2 : IN std_logic; -- sampling rate of ADC -- input 10 bit -din_adc : IN std_logic_vector(9 downto 0); -- output 12 bit -dout_load : OUT std_logic_vector(11 downto 0); dout_load_v : OUT std_logic ); END COMPONENT; COMPONENT ECC_EN PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- input -din_ecc : IN std_logic_vector(11 downto 0); din_ecc_v : IN std_logic; -- output -cout_ecc : OUT std_logic_vector(17 downto 0); cout_ecc_v : OUT std_logic ); END COMPONENT;
COMPONENT NRZ_EN PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- from PLL_1 -- input -cin_nrz : IN std_logic_vector(17 downto 0); cin_nrz_v : IN std_logic; -- output -neo e_syn ); END COMPONENT;
: OUT std_logic; -- output NRZ encoding : OUT std_logic -- synchronized signal
COMPONENT NRZ_DE PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- from PLL_2 -- input -ndi : IN std_logic; -- input NRZ encoding d_syn : IN std_logic; -- synchronized signal -- output -cout_nrz cout_nrz_v );
: OUT std_logic_vector(17 downto 0); : OUT std_logic
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89
END COMPONENT; COMPONENT ECC_DE PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- input -cin_ecc : IN std_logic_vector(17 downto 0); cin_ecc_v : IN std_logic; -- output error counter -err_d : OUT std_logic_vector(6 downto 0); err_c : OUT std_logic_vector(6 downto 0); -- output data -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic ); END COMPONENT; COMPONENT BIN_TO_SSEG PORT ( -- global input -rst : in std_logic; clk5x_2 : in std_logic; -- input -bin : in std_logic_vector(6 downto 0); -- output -sseg : out std_logic_vector(13 downto 0) ); END COMPONENT; ----- signal ----SIGNAL clk_2
: std_logic;
SIGNAL clk5x_1 SIGNAL clk5x_2
: std_logic; : std_logic;
SIGNAL d_load_ecc SIGNAL v_load_ecc
: std_logic_vector(11 downto 0); : std_logic;
SIGNAL c_ecc_nrz SIGNAL v_ecc_nrz
: std_logic_vector(17 downto 0); : std_logic;
SIGNAL c_nrz_ecc SIGNAL v_nrz_ecc
: std_logic_vector(17 downto 0); : std_logic;
SIGNAL err_d SIGNAL err_c ----- end signal ----BEGIN U1:CLK_DIVIDER port map ( rst clk --
clk_1 clk_2 ); U2:PLL_1 port map ( clk glb ); U3:PLL_2 port map ( clk glb
: std_logic_vector(6 downto 0); : std_logic_vector(6 downto 0);
=> rst, => clk, => clk_1, -- CANCELED => clk_2
=> clk, => clk5x_1
=> clk, => clk5x_2
6 Appendix
90
); U4:LOADER_DATA port map ( clk_2 din_adc
=> clk_2, => din_adc,
dout_load => d_load_ecc, dout_load_v => v_load_ecc ); U5:ECC_EN port map ( rst clk5x_1 din_ecc din_ecc_v
=> rst, => clk5x_1, => d_load_ecc, => v_load_ecc,
cout_ecc => c_ecc_nrz, cout_ecc_v => v_ecc_nrz ); U6:NRZ_EN port map ( rst clk5x_1
=> rst, => clk5x_1,
cin_nrz cin_nrz_v
=> c_ecc_nrz, => v_ecc_nrz,
neo e_syn );
=> neo, => e_syn
U7:NRZ_DE port map ( rst clk5x_2 ndi d_syn cout_nrz cout_nrz_v ); U8:ECC_DE port map ( rst clk5x_2 cin_ecc cin_ecc_v err_d err_c dout_dac dout_dac_v );
=> rst, => clk5x_2, => ndi, => d_syn, => c_nrz_ecc, => v_nrz_ecc
=> rst, => clk5x_2, => c_nrz_ecc, => v_nrz_ecc, => err_d, => err_c, => dout_dac, => dout_dac_v
U9:BIN_TO_SSEG -- display counter error correcting port map ( rst => rst, clk5x_2 => clk5x_2, bin
=> err_c,
sseg );
=> sseg_c
U10:BIN_TO_SSEG -- display counter error detecting port map (
6 Appendix
91
rst clk5x_2
=> rst, => clk5x_2,
bin
=> err_d,
sseg );
=> sseg_d
END RTL;
6.3.2 CLK_DIVIDER.vhd -------------------------------------------------------------------------------- Title : Dividing Clock Signal at FPGA1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : CLK_DIVIDER.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY CLK_DIVIDER IS PORT ( rst : IN std_logic; clk : IN std_logic; -- input clk 40 MHz -- output --clk_1 : OUT std_logic; -- output clk_1 20MHz -- CANCELED clk_2 : OUT std_logic -- output clk_2 1.0526 MHz ); END CLK_DIVIDER; ARCHITECTURE RTL OF CLK_DIVIDER IS --
SIGNAL clk_1_reg : std_logic; -- CANCELED SIGNAL clk_2_reg : std_logic; SIGNAL count_2 : std_logic_vector(4 downto 0);
BEGIN ---- CANCELED BECAUSE WE USE FUNCTION GENERATOR FOR ADC -----divider_2:PROCESS (rst,clk) -- divide by 2 --output 20MHz --BEGIN -if rst ='1' then --clk_1_reg <= '0'; --elsif (clk'event and clk = '1') then --clk_1_reg <= not clk_1_reg; --end if; --END PROCESS; --clk_1 <= clk_1_reg; ---- CANCELED BECAUSE WE USE FUNCTION GENERATOR FOR ADC ---divider_38:PROCESS (rst,clk,count_2) -- 40MHz divide by 38 --output 1.0526 MHz BEGIN if rst = '1' then clk_2_reg <= '0'; elsif clk'event and clk = '1' then if std_logic_vector(count_2) = "10010" then -- 18 clk_2_reg <= not clk_2_reg;
6 Appendix
else clk_2_reg <= clk_2_reg; end if; end if; END PROCESS; clk_2 <= clk_2_reg; counting_for_clk_2:PROCESS (rst,clk,count_2) BEGIN if rst = '1' then count_2 <= (others=>'0'); elsif clk'event and clk = '1' then if std_logic_vector(count_2) <= "10001" then -- 0 - 17 count_2 <= count_2 + "00001"; else count_2 <= (others=>'0'); end if; end if; END PROCESS; END RTL;
6.3.3 LOADER_DATA.vhd -------------------------------------------------------------------------------- Title : Loading data from ADC at FPGA_1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : LOADER_DATA.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; USE ieee.std_logic_unsigned.all ; ENTITY LOADER_DATA IS PORT ( -- global input -clk_2 : IN std_logic; -- sampling rate of ADC -- input 10 bit -din_adc : IN std_logic_vector(9 downto 0); -- output 12 bit -dout_load : OUT std_logic_vector(11 downto 0); dout_load_v : OUT std_logic ); END LOADER_DATA; ARCHITECTURE RTL OF LOADER_DATA IS BEGIN loading:PROCESS (clk_2) BEGIN if (clk_2'event and clk_2 = '1') then dout_load <= din_adc & "00";
92
6 Appendix
93
end if; END PROCESS; dout_load_v <= clk_2; END RTL;
6.3.4 ECC_EN.vhd -------------------------------------------------------------------------------- Title : Error Control Correcting Encoding at FPGA1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : ECC_EN.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 25.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- Shortened Hamming Encoder (n,k) = (18,12) -- C = M*G -- C = codeword -- M is the message 12 bit -- M = [m0, m1, m2, m3, m4, m5, m6, m7, m8, m9, m10, m11] -- G is the gemerator matrix -1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 -1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 --0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 -1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 -0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 -- G = -1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 -0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 -1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 --0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 -1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 -0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY ECC_EN IS PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- input -din_ecc : IN std_logic_vector(11 downto 0); din_ecc_v : IN std_logic; -- output -cout_ecc : OUT std_logic_vector(17 downto 0); cout_ecc_v : OUT std_logic ); END ECC_EN; ARCHITECTURE BEHAVIOR OF ECC_EN IS SIGNAL SIGNAL SIGNAL SIGNAL
din_reg din_v_reg cout_reg cout_ecc_v_reg
: : : :
std_logic_vector(11 downto 0); std_logic; std_logic_vector(17 downto 0); std_logic;
6 Appendix
94
BEGIN -- register din_ecc_v receive_data_input_enable:PROCESS (rst,clk5x_1) BEGIN if rst ='1' then din_v_reg <= '0'; elsif (clk5x_1'event and clk5x_1 = '1') then din_v_reg <= din_ecc_v; end if; END PROCESS; -- register din receive_data_in:PROCESS (rst,clk5x_1,din_ecc_v) BEGIN if rst ='1' then din_reg <= (others=>'0'); elsif (clk5x_1'event and clk5x_1 = '1') then if din_ecc_v = '1' then din_reg <= din_ecc; end if; end if; END PROCESS;
-- matrix codec multiplication encoding:PROCESS (rst,clk5x_1) BEGIN if rst ='1' then cout_reg <= (others=>'0'); elsif (clk5x_1'event and clk5x_1 = '1') then cout_reg(0)
<= din_reg(0) xor din_reg(2) xor din_reg(4) xor din_reg(6) xor din_reg(8) xor din_reg(10);
cout_reg(1)
<= din_reg(0) xor din_reg(2) xor din_reg(4) xor din_reg(6) xor din_reg(9) xor din_reg(11);
cout_reg(2)
<= din_reg(0) xor din_reg(3) xor din_reg(5) xor din_reg(7) xor din_reg(8) xor din_reg(10);
cout_reg(3)
<= din_reg(1) xor din_reg(2) xor din_reg(5) xor din_reg(7) xor din_reg(8) xor din_reg(11);
cout_reg(4)
<= din_reg(1) xor din_reg(3) xor din_reg(4) xor din_reg(7) xor din_reg(9) xor din_reg(10);
cout_reg(5)
<= din_reg(1) xor din_reg(3) xor din_reg(5) xor din_reg(6) xor din_reg(9) xor din_reg(11);
cout_reg(6) cout_reg(7) cout_reg(8)
<= din_reg(0); <= din_reg(1); <= din_reg(2);
cout_reg(9) <= din_reg(3); cout_reg(10) <= din_reg(4); cout_reg(11) <= din_reg(5); cout_reg(12) <= din_reg(6); cout_reg(13) <= din_reg(7); cout_reg(14) <= din_reg(8); cout_reg(15) <= din_reg(9);
6 Appendix
95
cout_reg(16) <= din_reg(10); cout_reg(17) <= din_reg(11); end if; END PROCESS; --provide code output cout_ecc <= cout_reg;
-- provide cout out valid enable_cout_valid:PROCESS (rst,clk5x_1) BEGIN if rst = '1' then cout_ecc_v_reg <= '0'; cout_ecc_v
<= '0';
elsif (clk5x_1'event and clk5x_1 = '1') then cout_ecc_v_reg
<= din_v_reg;
cout_ecc_v
<= cout_ecc_v_reg;
end if; END PROCESS; END BEHAVIOR;
6.3.5 NRZ_EN.vhd -------------------------------------------------------------------------------- Title : Never Return to Zero Encoding at FPGA_1/TX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : NRZ_EN.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 31.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- 5X oversampling LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY NRZ_EN is PORT ( -- global input -rst : IN std_logic; clk5x_1 : IN std_logic; -- from PLL_1 -- input -cin_nrz : IN std_logic_vector(17 downto 0); cin_nrz_v : IN std_logic; -- output -neo e_syn ); END NRZ_EN;
: OUT std_logic; -- output NRZ encoding : OUT std_logic -- synchronized signal
ARCHITECTURE RTL OF NRZ_EN IS SIGNAL count_loop
: std_logic_vector(4 downto 0);
SIGNAL count_clk
: std_logic_vector(2 downto 0);
SIGNAL s_reg
: std_logic_vector(17 downto 0);
6 Appendix
96
SIGNAL cin_nrz_reg
: std_logic_vector(17 downto 0);
SIGNAL enable
: std_logic;
SIGNAL clk1x_1
: std_logic;
SIGNAL e_syn_reg
: std_logic;
BEGIN -- enable process -enable_counting:PROCESS(rst,cin_nrz_v,count_loop,clk5x_1) BEGIN if rst = '1' or count_loop = "10010" then -- =18(19th loop will be disenabled) enable <= '0'; elsif clk5x_1'event and clk5x_1 = '1' then if cin_nrz_v = '1' then enable <= '1'; end if; end if; END PROCESS;
-- receive data from FEC, depended on clk5x_1 din_register:PROCESS (rst,clk5x_1,cin_nrz_v) BEGIN if rst = '1' then cin_nrz_reg <= (others=>'0'); elsif clk5x_1'event and clk5x_1 = '1' then if cin_nrz_v = '1' then cin_nrz_reg <= cin_nrz; end if; end if; END PROCESS;
-- count word 18 bits -count_loop_18:PROCESS(rst,enable,clk5x_1,count_clk) BEGIN if rst = '1' then count_loop <= (others=>'0'); elsif clk5x_1'event and clk5x_1 = '1' then if enable = '1' then if count_clk = "100" then count_loop <= count_loop + "00001"; end if; else count_loop <= (others=>'0'); end if; end if; END PROCESS;
6 Appendix
97
-- oversampling 5X counting 0 - 4 -oversampling:PROCESS(rst,enable,clk5x_1,count_clk) BEGIN if rst = '1' then count_clk <= (others=>'0'); elsif clk5x_1'event and clk5x_1 = '1' then if enable = '1' then if count_clk < "100" then count_clk <= count_clk + "001"; else count_clk <= (others=>'0'); end if; else count_clk <= (others=>'0'); end if; end if; END PROCESS; -- clock 1/5X of clk5x_1 -divided_5:PROCESS(rst,clk5x_1) BEGIN if rst = '1' then clk1x_1 <= '0'; elsif clk5x_1'event and clk5x_1 = '1' then clk1x_1 <=
((not count_clk(2)) and (not count_clk(1)) and (count_clk(0)));
end if; END PROCESS; -- shift data (parallel to serial) data_shifted_register:PROCESS (rst,clk1x_1,count_loop) BEGIN if rst ='1' then s_reg
<= (others=>'0');
e_syn_reg
<= '0';
elsif (clk1x_1'event and clk1x_1 = '1') then if enable = '1' then if count_loop = "00000" then s_reg <= cin_nrz_reg; e_syn_reg
<= '1';
else s_reg <= s_reg(16 downto 0) & '0'; e_syn_reg
<= '0';
end if; else s_reg <= (others=>'0');
6 Appendix
98
e_syn_reg
<= '0';
end if; end if; END PROCESS; -- NRZ encoding output -neo <= s_reg(17); -- Synchorized signals -e_syn <= e_syn_reg; END RTL;
6.3.6 NRZ_DE.vhd -------------------------------------------------------------------------------- Title : Never Return to Zero Decoding at FPGA_2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : NRZ_DE.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 31.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- 5X oversampling LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY NRZ_DE IS PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- from PLL_2 -- input -ndi : IN std_logic; -- input NRZ encoding d_syn : IN std_logic; -- synchronized signal -- output -cout_nrz cout_nrz_v ); END NRZ_DE;
: OUT std_logic_vector(17 downto 0); : OUT std_logic
ARCHITECTURE RTL OF NRZ_DE IS SIGNAL cout_nrz_reg : std_logic_vector(17 downto 0); SIGNAL rsr
: std_logic_vector(17 downto 0);
SIGNAL enable
: std_logic;
SIGNAL count_loop
: std_logic_vector(4 downto 0);
SIGNAL count_clk
: std_logic_vector(2 downto 0);
SIGNAL sample_2
: std_logic;
SIGNAL cout_nrz_v_reg : std_logic; BEGIN -- enable process -enable_counting:PROCESS(rst,d_syn,count_loop) BEGIN if rst = '1' or count_loop = "10010" then -- =18(19th loop will be disenabled)
6 Appendix
99
enable <= '0'; elsif d_syn'event and d_syn = '1' then enable <= '1'; end if; END PROCESS;
-- count word 18 bits -count_loop_18:PROCESS(rst,enable,clk5x_2,count_clk) BEGIN if rst = '1' then count_loop <= (others=>'0'); elsif clk5x_2'event and clk5x_2 = '1' then if enable = '1' then if count_clk = "100" then count_loop <= count_loop + "00001"; end if; else count_loop <= (others=>'0'); end if; end if; END PROCESS;
-- oversampling 5X counting 0 - 4 -oversampling:PROCESS(rst,enable,clk5x_2,count_clk) BEGIN if rst = '1' then count_clk <= (others=>'0'); elsif clk5x_2'event and clk5x_2 = '1' then if enable = '1' then if count_clk < "100" then count_clk <= count_clk + "001"; else count_clk <= (others=>'0'); end if; else count_clk <= (others=>'0'); end if; end if; END PROCESS;
-- synchronized sample signals with clk5x_2 sampling:PROCESS(rst,clk5x_2) BEGIN if rst = '1' then sample_2 <= '0';
6 Appendix
100
elsif clk5x_2'event and clk5x_2 = '1' then -- sample at center of 5X -sample_2 <= (not count_clk(2)) and (not count_clk(1)) and (count_clk(0)); end if; END PROCESS;
-- received signal register and shift it-shift_reg:PROCESS(rst,sample_2) BEGIN if rst = '1' then rsr <= (others=>'0'); elsif sample_2'event and sample_2 = '1' then rsr <= rsr(16 downto 0) & ndi; end if; END PROCESS;
-- sending output value -provide_output:PROCESS(rst,count_loop,clk5x_2) BEGIN if rst = '1' then cout_nrz_reg
<= (others=>'0');
cout_nrz_v_reg
<= '0';
elsif clk5x_2'event and clk5x_2 = '1' then if count_loop = "10010" then cout_nrz_reg
<= rsr;
cout_nrz_v_reg
<= '1';
elsif count_loop = "01000" then cout_nrz_v_reg
<= '0';
end if; end if; END PROCESS; cout_nrz
<= cout_nrz_reg;
cout_nrz_v
<= cout_nrz_v_reg;
END RTL;
6.3.7 ECC_DE.vhd -------------------------------------------------------------------------------- Title : Error Control Correcting Decoding at FPGA_2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : ECC_DE.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 31.07.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro -------------------------------------------------------------------------------- Shortened Hamming Decoder (n,k) = (18,12) -- S = C*Ht -- S = syndrome
6 Appendix
-- C is the codeword 18 bit -- C = [c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, -c10, c11, c12, c13, c14, c15, c16, c17] -- H is the parity check matrix -- Ht is the transpose matrix of parity check matrix -1 0 0 0 0 0 -0 1 0 0 0 0 -0 0 1 0 0 0 --0 0 0 1 0 0 -0 0 0 0 1 0 -0 0 0 0 0 1 --1 1 1 0 0 0 -0 0 0 1 1 1 -1 1 0 1 0 0 -- Ht = -0 0 1 0 1 1 -1 1 0 0 1 0 -0 0 1 1 0 1 --1 1 0 0 0 1 -0 0 1 1 1 0 -1 0 1 1 0 0 --0 1 0 0 1 1 -1 0 1 0 1 0 -0 1 0 1 0 1 -- S = 0 0 0 0 0 0 = error free -- S = 1 0 0 0 0 0 = error bit 1 -- S = 0 1 0 0 0 0 = error bit 2 -- S = 0 0 1 0 0 0 = error bit 3 -- S = 0 0 0 1 0 0 = error bit 4 -- S = 0 0 0 0 1 0 = error bit 5 -- S = 0 0 0 0 0 1 = error bit 6 -- S = 1 1 1 0 0 0 = error bit 7 -- S = 0 0 0 1 1 1 = error bit 8 -- S = 1 1 0 1 0 0 = error bit 9 -- S = 0 0 1 0 1 1 = error bit 10 -- S = 1 1 0 0 1 0 = error bit 11 -- S = 0 0 1 1 0 1 = error bit 12 -- S = 1 1 0 0 0 1 = error bit 13 -- S = 0 0 1 1 1 0 = error bit 14 -- S = 1 0 1 1 0 0 = error bit 15 -- S = 0 1 0 0 1 1 = error bit 16 -- S = 1 0 1 0 1 0 = error bit 17 -- S = 0 1 0 1 0 1 = error bit 18 -------------------------------------------------------------------------------- dout_dac_v is inverted because -- dout_dac_v connects to (/CS) of DAC ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY ECC_DE IS PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- input -cin_ecc : IN std_logic_vector(17 downto 0); cin_ecc_v : IN std_logic; -- output error counter -err_d : OUT std_logic_vector(6 downto 0); err_c : OUT std_logic_vector(6 downto 0); -- output data --
101
6 Appendix
dout_dac dout_dac_v
102
: OUT std_logic_vector(11 downto 0); : OUT std_logic
); END ECC_DE; ARCHITECTURE BEHAVIOR OF ECC_DE IS SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL
cin_reg cin_v_reg delay_v_1 delay_v_2 delay_v_3 delay_v_4 err_d_reg err_c_reg dout_reg syd
: : : : : : : : : :
std_logic_vector(17 downto 0); std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(6 downto 0); std_logic_vector(6 downto 0); std_logic_vector(11 downto 0); std_logic_vector(0 to 5);
BEGIN
-- register cin_v receive_code_input_valid:PROCESS (rst,clk5x_2) BEGIN if rst ='1' then cin_v_reg <= '0'; elsif (clk5x_2'event and clk5x_2 = '1') then cin_v_reg <= cin_ecc_v; end if; END PROCESS; -- register cin, use positive egde of cin_v_reg receive_code_in:PROCESS (rst,cin_v_reg) BEGIN if rst ='1' then cin_reg <= (others=>'0'); elsif cin_v_reg'event and cin_v_reg = '1'
then
cin_reg <= cin_ecc; end if; END PROCESS;
-- parity check matrix -syndrome:PROCESS(rst,delay_v_2) BEGIN if rst = '1' then syd <= (others=>'0'); elsif delay_v_2'event and delay_v_2='1' then -- matrix codec multiplication syd(0) <= cin_reg(0) xor cin_reg(6) xor cin_reg(8) xor cin_reg(10) xor cin_reg(12) xor cin_reg(14) xor cin_reg(16); syd(1) <= cin_reg(1) xor cin_reg(6) xor cin_reg(8) xor cin_reg(10) xor cin_reg(12) xor cin_reg(15) xor cin_reg(17); syd(2) <= cin_reg(2) xor cin_reg(6) xor cin_reg(9) xor cin_reg(11) xor cin_reg(13) xor cin_reg(14) xor cin_reg(16); syd(3) <= cin_reg(3) xor cin_reg(7) xor cin_reg(8) xor cin_reg(11) xor cin_reg(13) xor cin_reg(14) xor cin_reg(17); syd(4) <= cin_reg(4) xor cin_reg(7) xor cin_reg(9) xor cin_reg(10) xor cin_reg(13) xor cin_reg(15) xor cin_reg(16);
6 Appendix
103
syd(5) <= cin_reg(5) xor cin_reg(7) xor cin_reg(9) xor cin_reg(11) xor cin_reg(12) xor cin_reg(15) xor cin_reg(17); end if; END PROCESS;
-- correcting data -correcting:PROCESS (rst,delay_v_3,syd) BEGIN if rst = '1' then dout_reg <= (others => '0'); elsif delay_v_3'event and case syd is
delay_v_3='1' then
when "111000" => dout_reg(0) dout_reg(11 downto 1)
<= (not cin_reg(6)); <= cin_reg(17 downto 7);
when "000111" => dout_reg(0) dout_reg(1) dout_reg(11 downto 2)
<= cin_reg(6); <= (not cin_reg(7)); <= cin_reg(17 downto 8);
when "110100" => dout_reg(1 downto 0) dout_reg(2) dout_reg(11 downto 3)
<= cin_reg(7 downto 6); <= (not cin_reg(8)); <= cin_reg(17 downto 9);
when "001011" => dout_reg(2 downto 0) dout_reg(3) dout_reg(11 downto 4)
<= cin_reg(8 downto 6); <= (not cin_reg(9)); <= cin_reg(17 downto 10);
when "110010" => dout_reg(3 downto 0) dout_reg(4) dout_reg(11 downto 5)
<= cin_reg(9 downto 6); <= (not cin_reg(10)); <= cin_reg(17 downto 11);
when "001101" => dout_reg(4 downto 0) dout_reg(5) dout_reg(11 downto 6)
<= cin_reg(10 downto 6); <= (not cin_reg(11)); <= cin_reg(17 downto 12);
when "110001" => dout_reg(5 downto 0) <= cin_reg(11 downto 6); dout_reg(6) <= (not cin_reg(12)); dout_reg(11 downto 7) <= cin_reg(17 downto 13); when "001110" => dout_reg(6 downto 0) dout_reg(7) dout_reg(11 downto 8)
<= cin_reg(12 downto 6); <= (not cin_reg(13)); <= cin_reg(17 downto 14);
when "101100" => dout_reg(7 downto 0) dout_reg(8) dout_reg(11 downto 9)
<= cin_reg(13 downto 6); <= (not cin_reg(14)); <= cin_reg(17 downto 15);
when "010011" => dout_reg(8 downto 0) dout_reg(9) dout_reg(11 downto 10)
<= cin_reg(14 downto 6); <= (not cin_reg(15)); <= cin_reg(17 downto 16);
6 Appendix
104
when "101010" => dout_reg(9 downto 0) dout_reg(10) dout_reg(11)
<= cin_reg(15 downto 6); <= (not cin_reg(16)); <= cin_reg(17);
when "010101" => dout_reg(10 downto 0) dout_reg(11)
<= cin_reg(16 downto 6); <= (not cin_reg(17));
when others => dout_reg(11 downto 0) <= cin_reg(17 downto 6); end case; end if; END PROCESS; -- provide output -dout_dac <= dout_reg;
-- provide cout out valid -enable_cout_valid:PROCESS (rst,clk5x_2) BEGIN if rst = '1' then dout_dac_v delay_v_1 delay_v_2 delay_v_3 delay_v_4
<= <= <= <= <=
'0'; '0'; '0'; '0'; '0';
elsif (clk5x_2'event and clk5x_2 = '1') then delay_v_1 delay_v_2 delay_v_3 delay_v_4 dout_dac_v
<= <= <= <= <=
cin_v_reg; delay_v_1; delay_v_2; delay_v_3; not delay_v_4; -- because dout_dac_v connects with /CS
end if; END PROCESS;
-- counter for error correcting (single error correcting) -error_correcting:PROCESS(rst,delay_v_4,syd) BEGIN if rst = '1' then err_c_reg err_c
<= (others=>'0'); <= (others=>'0');
elsif delay_v_4'event and delay_v_4='1' then if
(
then
syd = "100000" or syd = "010000" or syd = "001000" or syd = "000100" or syd = "000010" or syd = "000001" or syd = "111000" or syd = "000111" or syd = "110100" or syd = "001011" or syd = "110010" or syd = "001101" or syd = "110001" or syd = "001110" or syd = "101100" or syd = "010011" or syd = "101010" or syd = "010101")
6 Appendix
105
err_c_reg <= err_c_reg + "0000001"; else err_c_reg <= err_c_reg; end if; err_c <= err_c_reg; end if; END PROCESS;
-- counter for error that can only detecting (double errors detecting) -error_detecting:PROCESS(rst,delay_v_4,syd) BEGIN if rst = '1' then err_d_reg err_d
<= (others=>'0'); <= (others=>'0');
elsif delay_v_4'event and delay_v_4='1' then if
(
syd and and and and and and and and and and and and and and and and and and
/= "000000" syd /= "100000" syd /= "010000" syd /= "001000" syd /= "000100" syd /= "000010" syd /= "000001" syd /= "111000" syd /= "000111" syd /= "110100" syd /= "001011" syd /= "110010" syd /= "001101" syd /= "110001" syd /= "001110" syd /= "101100" syd /= "010011" syd /= "101010" syd /= "010101")
then err_d_reg <= err_d_reg + "0000001"; else err_d_reg <= err_d_reg; end if; err_d <= err_d_reg; end if; END PROCESS; END BEHAVIOR;
6.3.8 BIN_TO_SSEG.vhd -- BIN_TO_SSEG.vhd -------------------------------------------------------------------------------- Title : Convert Binary to Seven Segments LED at FPGA2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : BIN_TO_SSEG.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 02.08.2006 -- Last update : 02.08.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro
6 Appendix
-------------------------------------------------------------------------------- Creates driver bits for each of seven segments on display from binary input -- Inputs: Binary value to show on seven segment display (7 bit) (0 to 99) -- Outputs: On/Off values for each of seven segments on display (7 bit) -- LED active HIGH ------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BIN_TO_SSEG IS PORT ( -- global input -rst : in std_logic; clk5x_2 : in std_logic; -- input -bin : in std_logic_vector(6 downto 0); -- output -sseg : out std_logic_vector(13 downto 0) ); END BIN_TO_SSEG; ARCHITECTURE BEHAVIORAL OF BIN_TO_SSEG IS SIGNAL bin2_reg : std_logic_vector(3 downto 0); SIGNAL bin1_reg : std_logic_vector(6 downto 0); BEGIN manage_bin:PROCESS(rst,clk5x_2,bin) BEGIN if rst = '1' then bin1_reg <= (others=>'0'); bin2_reg <= (others=>'0'); elsif clk5x_2'event and clk5x_2='1' then if bin > "1100011" then -- >99 bin2_reg <= (others=>'1'); bin1_reg <= (others=>'1'); elsif bin > "1011001" then -- >89 bin2_reg <= "1001"; bin1_reg <= (bin - "1011010"); elsif bin > "1001111" then -- >79 bin2_reg <= "1000"; bin1_reg <= (bin - "1010000"); elsif bin > "1000101" then -- >69 bin2_reg <= "0111"; bin1_reg <= (bin - "1000110"); elsif bin > "0111011" then -- >59 bin2_reg <= "0110"; bin1_reg <= (bin - "0111100"); elsif bin > "0110001" then -- >49 bin2_reg <= "0101"; bin1_reg <= (bin - "0110010"); elsif bin > "0100111" then -- >39 bin2_reg <= "0100";
106
6 Appendix
107
bin1_reg <= (bin - "0101000"); elsif bin > "0011101" then -- >29 bin2_reg <= "0011"; bin1_reg <= (bin - "0011110"); elsif bin > "0010011" then -- >19 bin2_reg <= "0010"; bin1_reg <= (bin - "0010100"); elsif bin > "0001001" then -- >9 bin2_reg <= "0001"; bin1_reg <= (bin - "0001010"); elsif bin < "0001001" then -- <9 bin2_reg <= (others=>'0'); bin1_reg <= bin; end if; end if; END PROCESS; encode_to_sseg:PROCESS(rst,clk5x_2,bin2_reg,bin1_reg) BEGIN if rst = '1' then sseg(6 downto 0) sseg(13 downto 7)
<= "0111111"; -- one unit <= "0111111"; -- ten unit
elsif clk5x_2'event and clk5x_2='1' then case bin2_reg is -- ten unit when "0000" => sseg(13 when "0001" => sseg(13 when "0010" => sseg(13 when "0011" => sseg(13 when "0100" => sseg(13 when "0101" => sseg(13 when "0110" => sseg(13 when "0111" => sseg(13 when "1000" => sseg(13 when "1001" => sseg(13 when others => sseg(13 end case; case bin1_reg(3 downto 0) is when "0000" => sseg(6 when "0001" => sseg(6 when "0010" => sseg(6 when "0011" => sseg(6 when "0100" => sseg(6 when "0101" => sseg(6 when "0110" => sseg(6 when "0111" => sseg(6 when "1000" => sseg(6 when "1001" => sseg(6 when others => sseg(6 end case;
downto downto downto downto downto downto downto downto downto downto downto
-- one downto downto downto downto downto downto downto downto downto downto downto
7) 7) 7) 7) 7) 7) 7) 7) 7) 7) 7)
<= <= <= <= <= <= <= <= <= <= <=
unit 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <= 0) <=
"0111111"; "0000110"; "1011011"; "1001111"; "1100110"; "1101101"; "1111101"; "0000111"; "1111111"; "1101111"; "0000000";
"0111111"; "0000110"; "1011011"; "1001111"; "1100110"; "1101101"; "1111101"; "0000111"; "1111111"; "1101111"; "0000000";
--0 --1 --2 --3 --4 --5 --6 --7 --8 --9 --Off
--0 --1 --2 --3 --4 --5 --6 --7 --8 --9 --Off
end if; END PROCESS; END BEHAVIORAL;
6.3.9 TB_TOP_LEVEL.vhd -------------------------------------------------------------------------------- Title : Test bench of Top level of Transmission System -- Project : The concept of measurement system
6 Appendix
108
-------------------------------------------------------------------------------- File : TB_TOP_LEVEL.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 01.08.2006 -- Last update : 01.08.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY TB_TOP_LEVEL IS END; ARCHITECTURE TB OF TB_TOP_LEVEL IS COMPONENT TOP_LEVEL PORT ( -- global signal rst : IN std_logic; clk : IN std_logic; -- ADC clock control -clk_1 : OUT std_logic; -- CANCELED
--
-- input -din_adc : IN std_logic_vector(9 downto 0); -- TX NRZ -neo : OUT std_logic; e_syn : OUT std_logic; -- RX NRZ -ndi : IN std_logic; d_syn : IN std_logic; -- output -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic; -- output counter -sseg_d : OUT std_logic_vector(13 downto 0); sseg_c : OUT std_logic_vector(13 downto 0) ); END COMPONENT; ------ signal -----SIGNAL rst SIGNAL clk --
SIGNAL clk_1
: std_logic; : std_logic; : std_logic; -- CANCELED
SIGNAL din_adc
: std_logic_vector(9 downto 0);
SIGNAL neo SIGNAL e_syn
: std_logic; : std_logic;
SIGNAL ndi SIGNAL d_syn
: std_logic; : std_logic;
SIGNAL dout_dac SIGNAL dout_dac_v
: std_logic_vector(11 downto 0); : std_logic;
SIGNAL sseg_d SIGNAL sseg_c
: std_logic_vector(13 downto 0); : std_logic_vector(13 downto 0);
signal a : std_logic; signal b : std_logic; ------ end signal -----BEGIN UUT:TOP_LEVEL port map (
6 Appendix
rst clk --
clk_1
109
=> rst, => clk, => clk_1, -- CANCELED
din_adc
=> din_adc,
neo e_syn
=> a, => b,
ndi d_syn
=> a, => b,
dout_dac dout_dac_v
=> dout_dac, => dout_dac_v,
sseg_d sseg_c );
=> sseg_d, => sseg_c
-- generate clk, 40 MHz gen_clk:PROCESS BEGIN clk <= '0'; wait for 12.5 ns; clk <= '1'; wait for 12.5 ns; END PROCESS; -- generate reset, in the first 200 ns gen_rst:PROCESS BEGIN rst <= '0'; wait for 10 ns; -- 30ns rst <= '1'; wait for 300 ns; -- 200ns reset actived rst <= '0'; wait; END PROCESS;
-- gen din_adc gen_stimulus:PROCESS BEGIN din_adc <= (others => '0'); wait for 100 ns; din_adc <= (others => '1'); wait for 100 ns; din_adc <= (others => '0'); wait for 100 ns; din_adc <= "1010101010"; wait for 100 ns; din_adc <= (others => '1'); wait for 300 ns; din_adc <= "1010101010"; wait for 100 ns; din_adc <= (others => '0'); wait for 3000 ns; din_adc <= "0101010101"; wait for 200 ns; din_adc <= (others => '1'); wait for 1 us; din_adc <= "0101010101"; wait for 100 ns; din_adc <= (others => '0');
6 Appendix
110
wait for 100 ns; din_adc <= "1010101010"; wait for 200 ns; END PROCESS; END;
6.3.10
TB_ECC_DE.vhd
-------------------------------------------------------------------------------- Title : Test Bench of Error Control Correcting Decoding at FPGA_2/RX -- Project : The concept of measurement system -------------------------------------------------------------------------------- File : TB_ECC_DE.vhd -- Author : Pipat Eumthurapot -- Organization : Piller Power Systems -- Created : 07.07.2006 -- Last update : 30.09.2006 -- Simulators : ModelsimActel 6.1b/WindowsXP Pro ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY TB_ECC_DE IS END; ARCHITECTURE TB OF TB_ECC_DE IS COMPONENT ECC_DE PORT ( -- global input -rst : IN std_logic; clk5x_2 : IN std_logic; -- input -cin_ecc : IN std_logic_vector(17 downto 0); cin_ecc_v : IN std_logic; -- output error counter -err_d : OUT std_logic_vector(6 downto 0); err_c : OUT std_logic_vector(6 downto 0); -- output data -dout_dac : OUT std_logic_vector(11 downto 0); dout_dac_v : OUT std_logic ); END COMPONENT; SIGNAL rst : SIGNAL clk5x_2 : SIGNAL cin_ecc SIGNAL cin_ecc_v : SIGNAL err_d : SIGNAL err_c : SIGNAL dout_dac SIGNAL dout_dac_v
std_logic; std_logic; : std_logic_vector(17 downto 0); std_logic; std_logic_vector(6 downto 0); std_logic_vector(6 downto 0); : std_logic_vector(11 downto 0); : std_logic;
BEGIN UUT:ECC_DE port map ( rst clk5x_2 cin_ecc cin_ecc_v err_d err_c dout_dac dout_dac_v );
=> => => => => => => =>
rst, clk5x_2, cin_ecc, cin_ecc_v, err_d, err_c, dout_dac, dout_dac_v
-- generate clk, 110 MHz
6 Appendix
gen_clk:PROCESS BEGIN clk5x_2 <= '0'; wait for 4.55 ns; clk5x_2 <= '1'; wait for 4.55 ns; END PROCESS; -- generate reset, in the first 200 ns gen_rst:PROCESS BEGIN rst <= '0'; wait for 10 ns; rst <= '1'; -- 200ns reset actived wait for 300 ns; rst <= '0'; wait; END PROCESS; -- generate stimulus input -- gen cin_v -- 1 MHz gen_data_enable:PROCESS -- input valid when cin_v = '1' BEGIN -- enable cin_ecc_v <= '1'; wait for 501 ns; -- disable cin_ecc_v <= '0'; wait for 501 ns; END PROCESS; -- gen cin_ecc gen_stimulus:PROCESS BEGIN cin_ecc <= (others => '0'); wait for 1 us; cin_ecc <= (others => '0'); wait for 1 us; cin_ecc <= "101000000000011000"; wait for 1 us; cin_ecc <= "111110100000110000"; wait for 1 us; cin_ecc <= "101000011111001011"; wait for 1 us; cin_ecc <= "000000010101011111"; wait for 1 us; cin_ecc <= "000000001011001011"; wait for 1 us; cin_ecc <= "101010010111100011"; wait for 1 us; cin_ecc <= "010000100011000110"; wait for 1 us; cin_ecc <= "001000000000110010"; wait for 1 us; cin_ecc <= "101000000100011000"; -- error bit 8th wait for 1 us; cin_ecc <= "011110100000110000"; -- error bit 17th wait for 1 us; cin_ecc <= "100000011111001011"; -- error bit 15th
111
6 Appendix
wait for 1 us;
cin_ecc <= "101000000100011001"; -- error bit 8th and 0th wait for 1 us; cin_ecc <= "011110100000010000"; -- error bit 17th and 5th wait for 1 us; cin_ecc <= "100000011111001001"; -- error bit 15th and 1st wait for 1 us;
cin_ecc <= "101000000100111001"; -- error bit 8th and 0th and 5th wait for 1 us; cin_ecc <= "011110100000010001"; -- error bit 17th and 5th and 0th wait for 1 us; cin_ecc <= "000000011111001001"; -- error bit 15th and 1st and 17th wait for 1 us;
END PROCESS; END;
112
6 Appendix
113
6.4 Appendix D This Appendix shows the m-files codes of Matlab program which illustrated in Figure 4.12 prob_ham_uncoded.m SNR = 0:10; PH = zeros(size(0:10)); Pu = zeros(size(0:10)); snrc = 0; for snr = SNR snrc = snrc+1; EbN0 = 10^(snr/10); p = qf(sqrt(2*EbN0)); Pu(snrc) = 1-((1-p)^12); % Ps Uncoded PH(snrc) = 1-((1-p)^18 + 18*p*(1-p)^17); % Ps Hamming 18 12 end clf; semilogy(SNR,Pu,'ro-'); hold on; semilogy(SNR,PH,'sg-'); lh = legend('P uncoded(E)','P Hamming 18,12(E)'); xh = xlabel('E_b/N_0(dB)'); yh = ylabel('Probability of Error');
qf.m function p = qf(xlist) % % Compute the Q function: % % function p = qf(x) % p = 1/sqrt(2pi)int_x^infty exp(-t^2/2)dt
p = zeros(size(xlist)); i = 0; for x = xlist i = i+1; if(x < 0) p(i) = 1- 0.5*erfc(-x/sqrt(2)); else p(i) = 0.5*erfc(x/sqrt(2)); end end
7 References
114
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