Multipl I Cador

Tarea  Multiplicación de dos números de 8 bits que se active con una señal de START.  Código  Ruta de datos library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ruta_datos is port( dato_A,dato_B: in std_logic_vector(7 downto 0); clk,c1,c2,c3,fin: in std_logic; s,z: out std_logic; salida: out std_logic_vector(15 downto 0)); end ruta_datos; architecture solucion of ruta_datos is signal veces: std_logic_vector(3 downto 0); signal p,q_A,q_B: std_logic_vector( 15 downto 0); begin process(clk) begin if rising_edge(clk) then if c1='1' then p<=(others=>'0'); veces<="0000"; q_A<="00000000" & dato_A; q_B<="00000000" & dato_B; elsif c2='1' then p<=p+q_A; elsif c3='1' then veces<=veces+1; q_A<= q_A(14 downto 0) & '0'; q_B<= '0' & q_B(15 downto 1) ; end if; end if; end process; z<='1' when veces=8 else '0'; s<=q_B(0); salida<=p when fin='1' else (others=>'Z');

end solucion;



Unidad de control

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity control_mef is port(

clk,s,z,start: in std_logic; c1,c2,c3,fin: out std_logic);

end control_mef;

architecture solucion of control_mef is type Estados is (S0,S1,S2,S3,S4,S5); signal EP,ES: estados;

begin

process(clk) begin if rising_edge (clk) then EP<=ES; end if; end process;

process(EP) begin ES<=EP;

case EP is when S0=> c1<='0';c2<='0';c3<='0';fin<='0'; if start='1' then ES<=S1; else ES<=S0; end if;

when S1=> c1<='1';c2<='0';c3<='0';fin<='0'; ES<=S2;

when S2=> c1<='0';c2<='0';c3<='0';fin<='0'; if s='1'then ES<=S3; else ES<=s4; end if;

when S3=> c1<='0';c2<='1';c3<='0';fin<='0'; ES<=S4;

when S4=> c1<='0';c2<='0';c3<='1';fin<='0'; if z='1' then ES<=S5; else ES<=S2; end if;

when S5=> c1<='0';c2<='0';c3<='0';fin<='1';

ES<=S5; end case; end process;

end solucion;

 Implementación del circuito final library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity multiplicador is port( A,B: in std_logic_vector(7 downto 0); clk,start: in std_logic; fin: buffer std_logic; salida: out std_logic_vector(15 downto 0)); end multiplicador; architecture solucion of multiplicador is component ruta_datos port( dato_A,dato_B: in std_logic_vector(7 downto 0); clk,c1,c2,c3,fin: in std_logic; s,z: out std_logic; salida: out std_logic_vector(15 downto 0)); end component; component control_mef port( clk,s,z,start: in std_logic; c1,c2,c3,fin: out std_logic); end component; signal c1,c2,c3,s,z: std_logic; begin U0: ruta_datos port map(A,B,clk,c1,c2,c3,fin,s,z,salida); U1: control_mef port map(clk,s,z,start,c1,c2,c3,fin); end solucion;

 Simulacion en Max Plus II