Modeling And Simulation Of Strained Silicon Mosfets For Nanoscale Applications

Modeling and Simulation of Strained Silicon MOSFETs for Nanoscale Applications

A dissertation submitted in partial fulfillment of the requirement for the degree of Bachelor of Technology by Vivek Venkataraman (2002193) Susheel Nawal (2002185)

Under the Supervision of Prof. M. Jagadesh Kumar

to the Department of Electrical Engineering Indian Institute of Technology Delhi May 2006

What we have learnt from this endeavour....

“Stress IS proportional to strain !!!”

2

CERTIFICATE This is to certify that the thesis entitled “Modeling and Simulation of Strained Silicon MOSFETs for Nanoscale Applications” being submitted by Vivek Venkataraman and Susheel Nawal to the Indian Institute of Technology, Delhi, in the Electrical Engineering Department is a bona fide work carried out by them under my supervision and guidance. The research reports and the results presented in this thesis have not been submitted in parts or in full to any other University or Institute.

Date : 1 May 2006 Dr. M. Jagadesh Kumar Professor Department of Electrical Engineering Indian Institute of Technology New Delhi - 110016

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Publications from this thesis M. Jagadesh Kumar, Vivek Venkataraman and Susheel Nawal,"Comprehensive Approach to Modeling Threshold Voltage of Nanoscale Strained Silicon SOI MOSFETs," Journal of Computational Electronics, Vol.6, No.4, pp.439-444, December 2007. Vivek Venkataraman, Susheel Nawal and M. Jagadesh Kumar, "Compact Analytical Threshold Voltage Model of Nanoscale Fully-depleted Strained-silicon on Silicongermanium-on-insulator (SGOI) MOSFETs," IEEE Trans. on Electron Devices, Vol.54, pp.554-562, March 2007. M. Jagadesh Kumar, Vivek Venkataraman and Susheel Nawal, "Impact of Strain or Ge content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs," IEEE Trans. on Device and Materials Reliability, Vol.7, pp.181-187, March 2007. M. Jagadesh Kumar, Vivek Venkataraman and Susheel Nawal, "A Simple Analytical Threshold Voltage Model of Nanoscale Fully Depleted Single-Layer Strained-Silicon-onInsulator (SSOI) MOSFETs," IEEE Trans. on Electron Devices, Vol.53, pp.2500-2506, October 2006. Susheel Nawal, Vivek Venkataraman and M. Jagadesh Kumar, "Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs," Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3, pp. 854-857, May 7-11,2006, Boston, Massachusetts, U.S.A.

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ACKNOWLEDGEMENT We wish to express our sincere gratitude to our supervisor Dr. M. Jagadesh Kumar for his invaluable guidance and advice during every stage of this project. We are greatly indebted to him for his constant encouragement and support, without which it would not have been possible for us to pursue this research. Special thanks are due to Prof. G. S. Visweswaran for his insightful comments and valuable suggestions during our project presentations. We also thank Prof.

B.

Bhaumik for her comments and questions related to our work, which have helped us immensely to improve our understanding. We are grateful to Mr. Chandrashekhar for allowing us to use the laboratory facilities at all points of time. We would also like to express our sincere thanks to Mr. Ali A. Orouji and Mr. B. Subrahmaniam for helpful discussions.

Vivek Venkataraman Susheel Nawal

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Abstract For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. However, no compact models are available in the literature modeling their threshold voltage or current characteristics, taking into account short channel effects. The aim of our project is to study various strained silicon devices and develop analytical models for the same. In this work, novel analytical models for the threshold voltage of nanoscale bulk strained-Si/SiGe MOSFETs, Fully Depleted Strained Silicon on Insulator (FD-SSOI) MOSFETs, and Fully Depleted strained-Si on Silicon-Germanium-on-Insulator (SGOI) MOSFETs are developed by solving the 2-D Poisson equation. Our models include the effects of the strain (in terms of equivalent Ge mole fraction), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin film thickness, gate work function and other device parameters. Our models correctly predict a decrease in threshold voltage with decreasing channel length and increasing strain in the silicon thin film i.e. with increasing Ge concentration. An analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs is also developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. The accuracy of the results obtained using our analytical models, is verified using two-dimensional device simulations.

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TABLE OF CONTENTS Figure Captions...................................................................................................8 Chapter I............................................................................................................11 Introduction.......................................................................................................11 Chapter II ..........................................................................................................14 Effect of Strain ..................................................................................................14 2.1 Introduction...........................................................................................................................................14 2.2 Effect on Silicon Band Structure...........................................................................................................14 2.3 Effect on MOSFET parameters.............................................................................................................15

Chapter III.........................................................................................................17 Strained-Si / SiGe MOSFET............................................................................17 3.1 Introduction...........................................................................................................................................17 3.2 Threshold Voltage Model .....................................................................................................................18 3.3 Calculation of Equivalent Depletion Region Depth (xd) .......................................................................23 3.4 Results and Discussion..........................................................................................................................25 3.5 Concluding Remarks.............................................................................................................................29

Chapter IV.........................................................................................................30 Fully Depleted Strained Silicon On Insulator MOSFET..............................30 4.1 Introduction...........................................................................................................................................30 4.2 Threshold Voltage Model .....................................................................................................................30 4.3 Results and Discussion..........................................................................................................................34 4.4 Concluding Remarks.............................................................................................................................36

Chapter V ..........................................................................................................38 Fully Depleted Strained Silicon On SiGe-on-Insulator MOSFET...............38 5.1 Introduction...........................................................................................................................................38 5.2 Threshold Voltage Model .....................................................................................................................38 5.3 Results and Discussion..........................................................................................................................44 5.4 Concluding Remarks.............................................................................................................................50

Chapter VI.........................................................................................................51 Analytical Drain Current Model for Strained-Si/SiGe MOSFETs .............51 6.1 Introduction...........................................................................................................................................51 6.2 Model for output characteristics of Strained-Si/SiGe nMOSFET.........................................................51 6.3 Results and Discussion..........................................................................................................................56 6.4 Concluding Remarks.............................................................................................................................61

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Chapter VII .......................................................................................................62 Conclusions........................................................................................................62 Future Work:...............................................................................................................................................63

References..........................................................................................................64

Figure Captions Figure 1

Effect of strain on Si and SiGe band structure (Ref. [15]).

Figure 2

Cross-sectional view of the strained-Si/SiGe MOSFET showing the depletion regions.

Figure 3

Box approximation of the depletion region for solving 2-D Poisson equation.

Figure 4

Depletion region of the strained-Si/SiGe MOSFET for L ≥ 2 x d l

Figure 5

Depletion region of the strained-Si/SiGe MOSFET for L ≤ 2 x d l

Figure 6

Threshold voltage versus strain x (Ge content in SiGe substrate) for channel lengths (L) of 50 nm and 30 nm. The parameters used are: VDS = 50 mV, Vsub = 0 V, 18

-3

NA = 1 x 10 cm , ts-Si = 15 nm, rj = 50 nm, tf = 2 nm, φM = 4.35 eV. Figure 7

Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV, 18

-3

Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 15 nm, rj = 50 nm, tf = 2 nm, φM = 4.35 eV. Figure 8

18

-3

Threshold voltage versus strain x (Ge content) for body dopings NA = 1 x 10 cm 17

and NA = 1 x 10

-3

cm , and corresponding gate work functions φM = 4.35 eV (n+

poly) and φM = 4.71 eV (Mid-gap metal) respectively. The parameters used are: VDS = 50 mV, Vsub = 0 V, L = 50 nm, ts-Si = 15 nm, rj = 50 nm, tf = 2 nm. Figure 9

Threshold voltage versus strain x (Ge content in SiGe substrate) for S/D junction depths rj = 50 nm and rj = 80 nm. The parameters used are: VDS = 50 mV, Vsub = 0 V, 18

-3

L = 50 nm, NA = 1 x 10 cm , ts-Si = 15 nm, tf = 2 nm, φM = 4.35 eV. Figure 10

Threshold voltage versus strained-Si film thickness ts-Si. The parameters used are: VDS = 50 mV, Vsub = 0 V, NA = 1 x 10

18

-3

cm , L = 50 nm, rj = 50 nm, tf = 2 nm,

φM = 4.35 eV. Figure 11

Cross-sectional view of the FD-SSOI MOSFET.

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Figure 12

Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV, 18

-3

Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 25 nm, tf = 2 nm, tb = 100 nm, φM = 4.35 eV. Figure 13

Threshold voltage versus strain x (equivalent Ge content) for strained-Si film thicknesses ts-Si = 15 nm and ts-Si = 10 nm. The parameters used are: VDS = 50 mV, 18

-3

Vsub = 0 V, L = 50 nm, NA = 1 x 10 cm , tf = 2 nm, tb = 100 nm, φM = 4.35 eV. Figure 14

Threshold voltage versus strained-Si film thickness ts-Si. The parameters used are: 18

-3

VDS = 50 mV, Vsub = 0 V, NA = 1 x 10 cm , L = 50 nm, tf = 2 nm, tb = 100 nm,

φM = 4.35 eV. Figure 15

Cross-sectional view of the FD-strained-Si on SGOI MOSFET.

Figure 16

Comparison between the actual surface potential (solving the fourth order differential equation) and approximate solution (neglecting the fourth order term). The parameters used are: x = 0.1, VGS = 0.15 V, VDS = 50 mV, Vsub = 0 V, L = 50 nm, 18

-3

NA = 1 x 10 cm , tf = 2 nm, tb = 100 nm, φM = 4.35 eV, ts-Si = 5 nm, tSiGe = 10 nm. Figure 17

Threshold voltage versus strain x (Ge content in the SiGe film) for different strained-Si and SiGe film thicknesses. The parameters used are: VDS = 50 mV, 18

-3

Vsub = 0 V, L = 50 nm, NA = 1 x 10 cm , tf = 2 nm, tb = 100 nm, φM = 4.35 eV. Figure 18

Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV, 18

-3

Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb = 100 nm,

φM = 4.35 eV (Maximum Transconductance Method) Figure 19

Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV, 18

-3

Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb = 100 nm,

φM = 4.35 eV ( Ninv = NA Method) Figure 20

Threshold voltage versus strain x (Ge content in the SiGe film) for gate work functions φM = 4.35 eV (n+ poly) and φM = 4.71 eV (Mid-gap metal) and 18

-3

17

-3

corresponding body dopings NA = 1 x 10 cm and NA = 1 x 10 cm respectively. The parameters used are: VDS = 50 mV, Vsub = 0 V, L = 50 nm, ts-Si = 5 nm, tSiGe = 5 nm, tf = 2 nm, tb = 100 nm.

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Figure 21

Threshold voltage versus SiGe film thickness tSiGe. 18

The parameters used are:

-3

VDS = 50 mV, Vsub = 0 V, NA = 1 x 10 cm , L = 50 nm, ts-Si = 10 nm, tf = 2 nm, tb = 100 nm, φM = 4.35 eV. Figure 22

Saturation threshold voltage versus channel length L. The parameters used are: 18

-3

VDS = 0.5 V, Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb = 100 nm, φM = 4.35 eV. Figure 23

Drain Induced Barrier Lowering (DIBL) versus channel length L. The parameters 18

-3

used are: x = 0.2, Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb = 100 nm, φM = 4.35 eV. Figure 24

Output Current versus drain voltage for different values of strain x (Ge content in the 18

-3

SiGe film). The parameters used are: VGS = 0.75 V, Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 15 nm, tox = 2 nm, φM = 4.35 eV, L = 50 nm Figure 25

Normalized current characteristics for different values of strain x (Ge content in the 18

-3

SiGe film). The parameters used are: VGS = 0.75 V, Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 15 nm, tox = 2 nm, φM = 4.35 eV, L = 50 nm Figure 26

Output Characteristics for unstrained MOSFET (x = 0). The parameters used are: 18

-3

Vsub = 0 V, NA = 1 x 10 cm , ts-Si = 15 nm, tox = 2 nm, φM = 4.35 eV, τ w = 0.1 ps, L = 50 nm. Figure 27

Output Characteristics for strain x = 0.1. The parameters used are: Vsub = 0 V, 18

-3

NA = 1 x 10 cm , ts-Si =15 nm, tox = 4 nm, φM = 4.35 eV, τ w = 0.15 ps, L = 50 nm. Figure 28

Output Characteristics for strain x = 0.2. The parameters used are: Vsub = 0 V, 18

-3

NA = 1 x 10 cm , ts-Si = 15 nm, tox =5 nm, φM = 4.35 eV, τ w = 0.2 ps, L = 50 nm. Figure 29

Output Characteristics for strain x = 0.2. The parameters used are: Vsub = 0 V, 18

-3

NA = 1 x 10 cm , ts-Si = 15 nm, tox =2 nm, φM = 4.71 eV, τ w = 0.2 ps, L = 50 nm.

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Chapter I Introduction Silicon-based MOSFETs have reached remarkable levels of performance through device scaling. However, it is becoming increasingly hard to improve device performance through traditional scaling methods. Device dimensions are approaching their scaling limit giving rise to undesirable effects like gate leakage current, short channel effects etc. Consequently, innovative device structures and materials are actively being investigated to boost performance. Strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance due to improved carrier-transport properties, i.e., mobility and high-field velocity [1], and compatibility with conventional silicon processing [2]-[4]. The conventional method of producing strained Si is pseudomorphic Si epitaxial growth on relaxed SiGe alloys. By increasing the Ge content of the relaxed SiGe alloy, the amount of biaxial strain and therefore the magnitude of the mobility enhancement can be enhanced. However, as the Ge content is increased, the critical thickness (the thickness to which the strained silicon can be grown without inducing misfit dislocations to alleviate the strain) is reduced. Strained silicon-on-insulator (SOI) MOSFETs have been proposed for applications in high-speed CMOS devices as they combine the carrier transport advantages of strained-Si with the reduced parasitic capacitance and improved MOSFET scalability of thinfilm SOI [15,23]. Thin body SOI with a fully depleted layer has additional advantages, such as steep sub-threshold slope, low junction leakage current, maximized channel mobility and reduced threshold-voltage fluctuation due to low impurity concentration. A number of different structures have been suggested for strained SOI devices employing various fabrication techniques [24-26]. Among these, the strained-Si on SGOI substrate is expected to have a high strain in the Si layer because of the underlying SiGe layer with high Ge content, resulting in better performance [27]. Consequently, these devices have been receiving considerable attention. Strained silicon-on-insulator (SSOI) is a new SiGe-free material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. The strained silicon-on-insulator (SSOI) structure is less susceptible to misfit dislocation-induced

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leakage current, while maintaining increased carrier mobility [21]. Tremendous improvement in static and dynamic CMOS circuit performance has been demonstrated using strained SOI as well as strained-Si/SiGe MOSFETs [5]. Accurate modeling of nanoscale strained-Si devices along the lines of conventional nanoscale Si MOSFETs [6-9] thus becomes necessary for future device and circuit design. There is no comprehensive analytical model available for the threshold voltage of SSOI or strained-Si on SGOI MOSFETs, while earlier works on the threshold voltage of strainedSi/SiGe MOSFETs [10]-[11] have concentrated on the band offsets due to strain and modified the long channel threshold voltage model. One-dimensional Poisson equation solution has also been considered [12]-[13], however for short channel devices, twodimensional effects such as the influence of source/drain depletion widths becomes important. The aim of this work is, therefore, to develop, for the first time, models for the threshold voltage of short channel (sub 100 nm) nanoscale strained-Si/SiGe, SSOI and strained-Si on SGOI MOSFETs by solving the 2-D Poisson equation in the strained-Si thin film and analyzing the dependence of threshold voltage on various device parameters. Also, an analytical model for the output current characteristics (Ids – Vds) is developed for nanoscale strained-Si/SiGe MOSFETs to examine the effect of strain on current drive enhancement. Our models thus provide an efficient tool for design and characterization of high performance SSOI, strained-Si on SGOI and strained-Si/SiGe nanoscale MOSFETs including the short channel effects. The effect of varying device parameters can easily be investigated using the analytical models presented in this work. The model results are verified by comparing them with the 2-D simulation results obtained using MEDICI [14]. The dissertation is divided into seven chapters and its outline is described as given below: ¾ Chapter I: Introduction. Concepts and previous works related to Strained Silicon devices, its advantages & disadvantages, objectives of the project and outline of the thesis.

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¾ Chapter II: Effect of Strain This chapter analyzes the effect of strain due to lattice mismatch between Si and SiGe on various properties of silicon. The impact on various MOSFET parameters like flat band voltage, built in voltage etc. has also been discussed. ¾ Chapter III: Strained-Si / SiGe MOSFET In this chapter we have derived the threshold voltage model of Strained-Si / SiGe MOSFET. The model has been compared with 2D simulations and the results with varying device parameters have been discussed. ¾ Chapter IV: Fully Depleted Strained Silicon On Insulator MOSFET In this chapter we have derived the threshold voltage model of FD-SSOI MOSFET. The model has been compared with 2D simulations and the results with varying device parameters have been discussed. ¾ Chapter V: Fully Depleted Strained Silicon On Silicon-Germanium-on-Insulator MOSFET In this chapter we have derived the threshold voltage model of FD-strained-Si on SGOI MOSFET. The model has been compared with 2D simulations and the results with varying device parameters have been discussed. ¾ Chapter VI: Analytical Drain Current Model for Strained-Si/SiGe MOSFETs In this chapter we have developed the model for output current characteristics of Strained-Si / SiGe MOSFETs. The model has been compared with 2D simulations and the enhancement in current due to strain is discussed. ¾ Chapter VII: Conclusions and Future Work.

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Chapter II Effect of Strain 2.1 Introduction Silicon under biaxial tension, caused due to lattice mismatch with SiGe leads to enhanced carrier mobility, providing improved MOSFET performance compared to standard bulk and silicon-on-insulator (SOI) substrates [10,11]. In strained Si, the silicon 6-fold degenerate valley in the conduction band is split into 2-fold and 4-fold degenerate valleys. Similar splitting is observed between the light and heavy hole bands in the valence band. The band with lower energy is preferentially occupied resulting in the reduction of the carrier effective mass and intervalley scattering rates [22].

2.2 Effect on Silicon Band Structure Vacuum level Work-function

EC 0.57x (eV)

Gate Eg,Si - 0.4x (eV) 0.467x (eV)

EV Si

Strained-Si

Unstrained Si1-xGex x : Ge content

Figure 1- Cross-sectional view of the strained-Si/SiGe MOSFET [15]

Due to strain, the electron affinity of silicon increases and the bandgap decreases (Fig. 1). Also the effective mass of carriers decreases. The effect of strain on Si band structure can be modeled as [10,11,15]: (ΔEC ) s − Si = 0.57 x , (ΔEg ) s − Si

⎛ NV , Si ⎞ ⎛ mh*, Si ⎞ ⎜ ⎟ ⎜ ⎟ = 0.4 x , VT ln⎜ ⎟ = VT ln⎜ m* ⎟ N ⎝ V , s − Si ⎠ ⎝ h, s − Si ⎠

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3/ 2

≈ 0.075 x

(1)

where x is the Ge mole fraction in Si1-xGex substrate, (ΔEC ) s − Si is the decrease in electron affinity of silicon due to strain, (ΔEg ) s − Si is the decrease in bandgap of silicon due to strain, VT is the thermal voltage, NV , Si and NV , s − Si are the density of states in the valence band in

normal and strained silicon respectively, mh*, Si and mh*, s − Si are the hole density of states (DOS) effective masses in normal and strained silicon, respectively. The band structure parameters for relaxed Si1-xGex substrate can also be estimated as [14]-[16]: (ΔEg ) SiGe = 0.467 x , NV , SiGe = ( 0.6 x + 1.04(1 − x) ) × 1019 cm −3 , ε SiGe = 11.8 + 4.2 x

(2)

where (ΔEg ) SiGe is the decrease in bandgap of Si1-xGex from that of Si, NV , SiGe is the density of states in the valence band in relaxed Si1-xGex, and ε SiGe is the permittivity of Si1-xGex.

2.3 Effect on MOSFET parameters

The flat-band voltage of a MOSFET is thus modified due to strain as [11] (VFB , f ) s − Si = (VFB , f ) Si + ΔVFB , f

(3)

where (VFB , f ) Si = φM − φSi ,

φSi =

χ Si q

ΔVFB , f =

+

Eg , Si 2q

⎛ N ⎞ − (ΔEC ) s − Si (ΔEg ) s − Si + − VT ln⎜⎜ V , Si ⎟⎟ , q q ⎝ NV , s − Si ⎠

+ φF , Si ,

⎛ NA ⎞ ⎟ . ⎟ n ⎝ i , Si ⎠

φF , Si = VT ln⎜⎜

In the above relations, φM is the gate work function, φSi is the unstrained Si work function,

φF , Si is the Fermi potential in unstrained Si, χ Si is the electron affinity in unstrained Si, Eg , Si is the bandgap in unstrained Si, q is the electronic charge, NA is the body doping concentration and ni , Si is the intrinsic carrier concentration in unstrained Si. The built-in voltage across the source-body and drain-body junctions in the strainedSi thin film is also affected by strain as

Vbi , s − Si = Vbi , Si + ( ΔVbi ) s − Si where

Vbi , Si =

Eg , Si 2q

+ φF , Si ,

(ΔVbi ) s − Si =

− (ΔEg ) s − Si q

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(4) ⎛ N ⎞ + VT ln⎜⎜ V , Si ⎟⎟ . ⎝ NV , s − Si ⎠

The built-in voltage across the source-body and drain-body junctions in the relaxed Si1-xGex substrate can be written as

Vbi , SiGe = Vbi , Si + ( ΔVbi ) SiGe where

Vbi , Si =

Eg , Si 2q

+ φF , Si ,

(ΔVbi ) SiGe =

−(ΔEg ) SiGe q

(5) ⎛ N ⎞ + VT ln ⎜ V , Si ⎟ . ⎜N ⎟ ⎝ V , SiGe ⎠

In the next three chapters, the above effects have been incorporated to derive an analytical threshold voltage model for Strained Si/SiGe, FD-SSOI and FD-strained-Si on SGOI MOSFETs.

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Chapter III Strained-Si / SiGe MOSFET 3.1 Introduction

Epitaxial growth of Si on relaxed SiGe alloys creates strained-Si layers due to the larger atomic spacing of Ge. However the film thickness cannot exceed few tens of nanometers, otherwise misfit dislocations will creep in. Fig. 2 shows the cross-section of a short channel strained-Si/SiGe n-MOSFET with depletion regions also indicated. The depletion region under the gate for short channel MOSFETs is not uniform and is affected by the lateral source-body and drain-body depletion widths (xdl ) and their respective charges, as shown in Fig.2. The exact solution of the 2-D Poisson equation for such a case is too complicated and would most probably require numerical methods and iterations. To obtain a meaningful analytical solution, Fig. 2 is transformed to a box type approximation of the depletion region as shown in Fig. 3 with a uniform charge density NA,eff and a uniform depth of depletion thickness xd.

VG

Gate

VS =0

tf

rj

VD

Gate oxide s-Si

n+

ts-si

xdv

NA xdl

n+ xdl

L Si1-x Gex VSub =0

Figure 2- Cross-sectional view of the strained-Si/SiGe MOSFET

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The gate-S/D charge sharing [17] and source-body/drain-body built-in potential barrier lowering [18] due to overlap of the lateral source-body and drain-body depletion regions (xdl in Fig. 2) become important as the channel length reduces.

3.2 Threshold Voltage Model

To incorporate the short channel effects, the effective doping NA,eff is defined taking into account only the effective charge under the influence of the gate [17] as

⎡ ⎛ N A , eff = N A ⎢1 − ⎜ ⎢ ⎜ ⎣ ⎝ where xdv =

⎛ 2 x dv ⎜⎜ 1 + rj ⎝

⎞r ⎤ ⎞ ⎟ j⎥ − 1 ⎟⎟ ⎟ L⎥ ⎠ ⎠ ⎦

(6)

2ε SiGe (φth − Vsub ) ⎛ N ⎞ − (ΔEg ) s − Si , φth = 2φF , Si + Δφs − Si , Δφs − Si = + VT ln⎜⎜ V , Si ⎟⎟ , qN A q ⎝ NV , s − Si ⎠

xdv is the vertical depletion region depth due to gate bias only, φth is the minimum surface potential required for inversion [11], rj is the source/drain junction depth, L is the channel or gate length, and Vsub is the substrate bias. φth is that value of surface potential at which the inversion electron charge density in the strained-Si device is the same as that in unstrained-Si at threshold [11] (i.e. Δφs − Si = 0 for unstrained-Si). The above approach is analogous to the one used in [13], where a voltage-doping transformation [19] is used to define an effective doping to extend the long channel threshold voltage model to the short channel case. To complete the box approximation, an average vertical depletion region depth (xd in Fig. 3) is calculated using simple geometry (see section III b.) from Fig. 2 as

xd ≅

2 xdl ( rj + π4 xdl ) + ( L − 2 xdl ) xdv L

xdl2 1 2 L2 xd ≅ r j + xdl − +θ L 2 4 where

⎛ L ⎞ ⎟, ⎝ 2 xdl ⎠

θ = sin −1 ⎜

for

for

and

L ≥ 2 x dl L ≤ 2 x dl x dl =

(7)

(8)

2ε SiGeVbi , SiGe qN A

is the lateral source-body and drain-body depletion region width. It can be seen that in the case of large channel length, i.e. L >> 2xdl, equation (7) reduces to xd ≈ xdv. Also, for 18

extremely short channel lengths i.e. L << 2xdl, equation (8) reduces to xd ≈ rj+ xdl. These results are along expected lines. For L = 2xdl, equations (7) and (8) yield the same value for xd. VG

Gate

VS=0

rj

tf xd

n+

VD

Gate oxide s-Si

y=0 ts-si φ 1 ( x,y)

tSiGe

NA,eff

n+

φ 2( x,y') y' = 0

x=0

x=L

L Si1-x Gex VSub=0

Figure 3- Box approximation of the depletion region

For the simplified structure in Fig. 3, the 2-D Poisson equation in the strained silicon thin-film, before the onset of strong inversion can be written as [20]:

d 2φ1 ( x, y ) d 2φ1 ( x, y ) qN A,eff + = ε Si dx 2 dy 2

for 0 ≤ x ≤ L , 0 ≤ y ≤ ts − Si

(9)

where ε Si is the dielectric constant of silicon, and t s − Si is the strained-Si thin film thickness. The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 3) and the depletion region in the SiGe substrate below (y’-direction in Fig. 3) can be approximated by a parabolic function, as done in [20] as:

φ1 ( x, y ) = φs ( x) + c11 ( x) y + c12 ( x) y 2

for 0 ≤ x ≤ L , 0 ≤ y ≤ ts − Si

φ2 ( x, y ') = Vsub + c21 ( x) y '+ c22 ( x) y '2 for 0 ≤ x ≤ L , 0 ≤ y ' ≤ tSiGe

(10) (11)

where t SiGe = xd − t s − Si , φS ( x ) is the surface potential and the coefficients c11 ( x ) , c12 ( x ) , c21 ( x ) and c22 ( x )

are functions of x only.

The Poisson equation is solved using the following boundary conditions: 19

1. Electric flux (displacement) at the gate-oxide/strained-Si film interface is continuous.

⎡ d φ1 ( x , y ) ⎤ ε ox ⎛ φ s ( x ) − VGS ⎢ dy ⎥ = ε ⎜⎜ tf ⎣ ⎦ y =0 Si ⎝

'⎞ ⎟⎟ ⎠

(12)

where ε ox is the dielectric constant of the gate oxide, t f is the gate oxide thickness, VGS ' = VGS − (VFB , f ) s − Si , and VGS is the gate-to-source bias voltage. 2. Electric flux/field at the end of the depletion region (y’=0 in Fig. 3) in the SiGe substrate is zero. ⎡ dφ2 ( x, y ') ⎤ =0 ⎢ dy ' ⎥ ⎣ ⎦ y '= 0

(13)

3. Potential at the interface of strained-Si thin film and SiGe substrate is continuous.

φ1 ( x , t s − Si ) = φ2 ( x, t SiGe )

(14)

4. Electric flux (displacement) at the interface of strained-Si thin film and SiGe substrate is continuous.

⎡ d φ1 ( x, y ) ⎤ ⎡ d φ ( x, y ') ⎤ ε = − SiGe ⎢ 2 ⎢ dy ⎥ ε Si ⎣ dy ' ⎥⎦ y '=tSiGe ⎣ ⎦ y =ts−Si

(15)

5. The surface potential at the source end is

φ1 (0, 0) = φs (0) = Vsub + Vbi , s − Si

(16)

6. The surface potential at the drain end is

φ1 ( L, 0) = φs ( L ) = Vsub + Vbi , s − Si + VDS

(17)

where VDS is the drain-to-source bias voltage. The coefficients c11 ( x ) , c12 ( x ) , c21 ( x ) and c22 ( x ) in equations (10) and (11) can be deduced from the boundary conditions (12) – (15). Substituting the values of c11 ( x ) and c12 ( x ) in (10), we obtain the expression for φ1 ( x, y ) . Then, substituting φ1 ( x, y ) in (9) and

putting y=0, we obtain

d 2φs ( x) − αφs ( x) = β dx 2 where

20

(18)

α= where

(

2 1+

Cf 2 C SiGe

(

t s2− Si 1 +

Cf =

ε ox tf

+

Cf C Si

C Si C SiGe

)

, C Si =

)

,

ε Si t s − Si

β=

qN A

ε Si

, C SiG e =

−

2VGS '

ε SiG e t SiG e

(

Cf 2 CSiGe

(

C

+ CSif

Si ts2− Si 1 + CCSiGe

)

)−

2Vsub

(

Si ts2− Si 1 + CCSiGe

)

.

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form

φs ( x) = A exp(λx) + B exp(−λx) − σ

(19)

where λ = α and σ = β α . Now using boundary conditions (16) – (17) to solve for A and B, we obtain ⎧⎪ (Vsub + Vbi , s − Si + σ + VDS ) − (Vsub + Vbi , s − Si + σ ) exp ( −λ L ) ⎫⎪ A=⎨ ⎬ exp ( −λ L ) 1 − exp ( −2λ L ) ⎩⎪ ⎭⎪ ⎧⎪ (Vsub + Vbi , s − Si + σ ) − (Vsub + Vbi , s − Si + σ + VDS ) exp ( −λ L ) ⎫⎪ B=⎨ ⎬. 1 − exp ( −2λ L ) ⎪⎩ ⎪⎭

The minimum surface potential can be calculated from (19) by putting d φs ( x ) =0. dx

(20)

The minimum surface potential is

φs , min = 2 AB − σ

(21)

The threshold voltage Vth is that value of the gate voltage VGS at which a conducting channel is induced under the gate oxide at the surface of a MOSFET. In a conventional unstrained silicon MOSFET, the threshold voltage is taken to be that value of gate-source voltage for which φS ,min = 2φF , Si , where φF , Si is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level [20]. At this potential the inversion electron concentration becomes equal to the body doping. For the strained-Si MOSFETs, the condition for threshold is modified as [11]:

φs , min = 2φF , Si + Δφs − Si = φth where Δφs − Si =

− (ΔEg ) s − Si q

⎛ N ⎞ + VT ln⎜⎜ V , Si ⎟⎟ . ⎝ NV , s − Si ⎠

21

(22)

and φth is that value of surface potential at which the inversion electron charge density in the strained-Si device is the same as that in unstrained-Si at threshold [11]. So the threshold voltage is defined as the value of VGS at which the minimum surface potential φS ,min equals

φth . Hence we can determine the value of threshold voltage by substituting (21) into (22) and solving for VGS , as

⎛ − V + V 2 − 4ξV φ1 φ1 φ2 Vth = k ⎜⎜ 2ξ ⎜ ⎝

⎞ ⎟ ⎟⎟ ⎠

where, ξ = 2 cosh ( λ L ) − 2 − sinh 2 ( λ L ) Vφ 1 = Vbi1 (1 − exp ( λ L ) ) + ( 2φth − 2u ) sinh 2 ( λ L ) − Vbi 2 (1 − exp ( −λ L ) )

Vφ 2 = Vbi1Vbi 2 − (φth − u ) sinh 2 ( λ L ) 2

Vbi1 = (Vsub + Vbi,s−Si − u ) (1 − exp ( −λ L) ) + VDS Vbi 2 = (Vsub + Vbi , s − Si − u ) ( exp ( λ L ) − 1) − VDS

u=

Vsub

(

C

C

f 1 + 2CSiGe + CSif

1+ ( k = (

Cf C Si

Cf C Si

+

+

)

−

Cf 2 C SiG e

Cf 2 C SiG e

)

qN A

ε Siα

−

(

(

Cf 2 CSiGe

C

+ CSif

C

)

C

f 1 + 2CSiGe + CSif

).

22

)

(VFB , f ) s − Si

(23)

3.3 Calculation of Equivalent Depletion Region Depth (xd) VG

Gate

VS =0

tf

rj

n+

VD

Gate oxide s-Si

22

1

ts-si

xdv

xdl

3

n+

xdl

L Si1-x Gex VSub =0

Figure 4- Depletion region of the strained-Si/SiGe MOSFET for L ≥ 2 x d l

The average vertical depletion region depth (xd in Fig. 3) in equations (7) and (8) is calculated using the constraint that the total depletion region area under the gate should remain the same as before after transformation to the box approximation. For L ≥ 2 x dl , the total depletion region area (DA) under the gate is calculated from Fig. 4 as DA = (Area of Region 1) + (Area of Region 2) + (Area of Region 3). Thus,

DA ≅ ( rj xdl + π4 xdl2 ) + ( L − 2 xdl ) xdv + ( rj xdl + π4 xdl2 )

(A1)

In the box approximation of Fig. 3, the total depletion region area (DA) under the gate is

DA = xd L

(A2)

Equating (A1) and (A2), we get the expression for average vertical depletion region depth xd as

xd ≅

2 xdl ( rj + π4 xdl ) + ( L − 2 xdl ) xdv L

Equation (A3) is the same as equation (7).

23

for L ≥ 2 x d l

(A3)

VG

Gate

VS =0

tf

n+

VD

Gate oxide s-Si

ts-si

L/2

rj θ

n+

1

2

xdl

xdl

L Si1-x Gex VSub =0

Figure 5- Depletion region of the strained-Si/SiGe MOSFET for L ≤ 2 x d l

Similarly, for L ≤ 2 x dl , the total depletion region area (DA) under the gate is calculated from Fig. 5 as DA = (Area of Region 1) + (Area of Region 2) = 2*(Area of Region 1 or 2). Thus DA can be approximated as,

⎡L⎛ 1 2 L2 ⎞ θ 2 ⎤ DA ≅ 2 ⎢ ⎜ rj + xdl − ⎟ + xdl ⎥ 2 4 ⎟⎠ 2 ⎥ ⎢⎣ 2 ⎜⎝ ⎦

(A4)

⎛ L ⎞ where θ = sin −1 ⎜ ⎟. ⎝ 2 xdl ⎠

Again, in the box approximation of Fig. 3, the total depletion region area (DA) under the gate is given by equation (A2). Comparing equating (A4) and (A2), we get the expression for average vertical depletion region depth xd as

xdl2 1 2 L2 xd ≅ r j + xdl − +θ L 2 4 Equation (A5) is the same as equation (8).

24

for L ≤ 2 x d l

(A5)

3.4 Results and Discussion

To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was used to simulate the threshold voltage of strained-Si/SiGe MOSFETs for various device parameters and the results were compared with the values predicted by the model. The threshold voltage is extracted from 2-D simulation using the commonly used maximum transconductance method. The parameters used in our simulation are given in Table 1.

Threshold Voltage (volts)

0.5 Model Medici

0.4 0.3 0.2 0.1

L = 50 nm

0 -0.1 -0.2

L = 30 nm 0

0.1

0.2

0.3

0.4

Equivalent Ge Content Strain , x Figure 6- Threshold voltage versus strain x

Fig. 6 shows the variation of threshold voltage with change in strain i.e. Ge mole fraction of SiGe substrate, for gate lengths of 50 nm and 30 nm. The threshold voltage obtained from the model tracks the simulation values very well. It is evident that there is a significant fall in threshold voltage with increasing strain, and the decrease in Vth is almost linear. Vth rolls off drastically with strain x, even going negative for Ge content of 30-40 %. The threshold voltage decreases with increasing Ge content x because of decrease in flatband voltage (equation (3)), decrease in source-body/drain-body built-in potential barrier (equation (4)), and earlier onset of inversion due to decrease in φth (equation (22)). Also, it

25

can be seen from the figure that Vth for L=50 nm is noticeably greater than that for L=30 nm, indicating the on-set of the short-channel effects.

Threshold Voltage (volts)

0.7 0.6

Model Medici

0.5 0.4 x=0 0.3 0.2

x=0.2

0.1

x=0.4

0 -0.1 -0.2

50

100

150

200

Gate Length , Lg (nm) Figure 7- Threshold voltage versus channel length L

Fig. 7 shows the variation of threshold voltage with gate length for different values of Ge mole fraction x in the SiGe substrate. It is observed that short channel effects become prevalent below 70-80 nm gate length, as predicted above, and is marked by the sharp decrease in Vth value. The gate-S/D charge sharing and source-body/drain-body built-in potential barrier lowering due to overlap of the lateral source-body and drain-body depletion regions (xdl in Fig. 2) become significant for such short channel lengths. Also, the threshold voltage is lower for higher strain for the same channel length, thus confirming the results from Fig. 6. The Vth values from the analytical model are in close proximity with the simulation results, with a maximum error of approximately 20-30 mV.

26

Threshold Voltage (volts)

Model Medici

0.5 0.4

17

NA = 1X 10 cm - 3 Mid-gap metal gate

0.3 0.2 18

0.1

NA = 1X 10 cm - 3 n+ poly gate

0 -0.1

0

0.1

0.2

0.3

0.4

Equivalent Ge Content Strain , x Figure 8- Threshold voltage versus strain x for different body dopings

In Fig. 8, the variation of threshold voltage with change in strain (Ge mole fraction x in SiGe substrate) for a gate length of 50 nm is plotted for two different body doping concentrations and corresponding gate work functions. It is evident from the figure that the threshold voltage of the strained-Si/SiGe MOSFETs can be controlled by using an appropriate gate material with a suitable work function φM . A higher work function (eg. Midgap metal with φM =4.71 eV) increases the flat-band voltage (equation (3)) thereby affording a lower doping concentration and higher strain levels for the same Vth , as compared to a normal n+ polysilicon gate ( φM =4.35 eV). Thus, by using a suitable gate material, we can achieve higher mobility of charge carriers due to larger strain and consequently higher transconductance without affecting Vth . There is again a close match between the analytical results and the 2-D simulation results [14]. In Fig. 9, the variation of threshold voltage with change in strain (Ge mole fraction x in SiGe substrate) for a gate length of 50 nm is plotted for two different source/drain junction depths. It is observed that Vth also reduces slightly with increase in source/drain junction depth, for the same gate length. This is because of the lower effective doping ( equation (6) )

27

Threshold Voltage (volts)

0.4 Model Medici

0.3

0.2

0.1

S/D junction depth, r j = 50 nm

S/D junction depth, rj = 80 nm

0

-0.1

0

0.1

0.2

0.3

0.4

Equivalent Ge Content Strain , x Figure 9- Threshold voltage versus strain x for various S/D junction depths

due to increased gate-S/D sharing and overlap of the lateral source-body and drain-body

Threshold Voltage (volts)

depletion regions. Thus, a lower S/D junction depth is desirable for better performance.

0.5

Model Medici

0.4 0.3

x=0 0.2 x=0.2

0.1 0

x=0.4

-0.1 8

10

12

14

16

Strained-Si thin film thickness, t s-Si (nm) Figure 10-Threshold voltage versus strained-Si film thickness ts-Si

28

The variation of threshold with the thickness of the strained-Si thin film is plotted in Fig. 10. As can be seen from the figure, there is no discernible change in threshold voltage with change in strained-Si film thickness from 10 nm -15 nm. This suggests that one can allow small variations and tolerances in the fabrication process without affecting the Vth too much. The table below gives various device parameters used in the simulation. Table 1: Device parameters used in the simulation (s-Si/SiGe) Parameter Value Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%) Source/Drain doping 2x1020 cm-3

Body doping, NA

1018 cm-3, 1017 cm-3

Gate Oxide Thickness, tf Work function of gate material, φM

2.0 nm 4.35 eV (n+ poly Si), 4.71 eV (Mid-Gap metal)

Strained-Silicon film thickness, ts-Si

10 nm - 15 nm

Source/drain junction depth, rj Substrate bias, Vsub Drain bias, VDS

50 nm, 80 nm 0 Volts (Gnd) 0.05 Volts (50 mV)

3.5 Concluding Remarks

Strained Si/SiGe MOSFETs offer better performance than conventional MOSFETs due to its higher electron and hole mobility. By increasing the Ge content of the relaxed SiGe alloy, the amount of biaxial strain and therefore the magnitude of the mobility can be enhanced. However, as the Ge content is increased the threshold voltage rolls off as seen from the model developed, and also the critical thickness (the thickness to which the strained silicon can be grown without inducing misfit dislocations to alleviate the strain) is reduced [21]. Therefore an alternate device structure has been proposed which combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI i.e. Fully Depleted Strained silicon MOSFET. This has been studied in the next chapter.

29

Chapter IV Fully Depleted Strained Silicon On Insulator MOSFET 4.1 Introduction

FD-SSOI is a Germanium free device hence it is less susceptible to misfit dislocationinduced leakage current compared to conventional strained Si/SiGe, while maintaining increased carrier mobility. Thus, strained Si thickness constraints for MOSFET fabrication are eased, allowing the successful fabrication of devices on strained Si films above the critical thickness. At the same time, SSOI provides the advantages of the SOI structure including reduced parasitic capacitance and improved electrostatics. Fig. 11 shows the crosssection of a FD-SSOI MOSFET. This chapter deals with the derivation of an analytical threshold voltage model for the same. 4.2 Threshold Voltage Model

The 2-D Poisson equation in the strained silicon thin-film, before the onset of strong inversion can be written as [20]: d 2φ ( x, y ) d 2φ ( x, y ) qN A + = ε Si dx 2 dy 2

for 0 ≤ x ≤ L , 0 ≤ y ≤ ts − Si

(24)

where ε Si is the dielectric constant of silicon, and t s − Si is the strained-Si thin film thickness. The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 11) can be approximated by a parabolic function, as done in [20] as:

φ ( x, y ) = φs ( x) + c1 ( x) y + c2 ( x) y 2

for 0 ≤ x ≤ L , 0 ≤ y ≤ ts − Si

(25)

where φS ( x ) is the surface potential and the coefficients c1 ( x ) and c2 ( x ) are functions of x only. The Poisson equation is solved using the following boundary conditions: 1. Electric flux (displacement) at the gate-oxide/strained-Si film interface is continuous.

⎡ dφ ( x, y ) ⎤ ε ox ⎛ φs ( x ) − VGS ⎢ dy ⎥ = ε ⎜⎜ tf ⎣ ⎦ y =0 Si ⎝

'⎞ ⎟⎟ ⎠

where ε ox is the dielectric constant of the gate oxide, t f is the gate oxide thickness,

30

(26)

VGS ' = VGS − (VFB , f ) s − Si , and VGS is the gate-to-source bias voltage. VG

VS=0

n+

Gate

tf

VD

Gate oxide

ts-si

s-Si

NA

φ ( x,y)

x=0

y=0

n+

y

x=L

L tb

Buried oxide

Substrate VSub=0

Figure 11- Cross-sectional view of the FD-SSOI MOSFET.

2. Electric flux at the interface of buried oxide and the back-channel is continuous. ⎡ d φ ( x, y ) ⎤ ε ⎛ V '− φ ( x, ts − Si ) ⎞ = ox ⎜ sub ⎟ ⎢ dy ⎥ tb ⎣ ⎦ y =ts−Si ε Si ⎝ ⎠

(27)

where tb is the buried oxide thickness, Vsub ' = Vsub − (VFB ,b ) s − Si , Vsub is the substrate bias, (VFB,b ) s − Si = (VFB,b ) Si + ΔVFB,b is the back-channel flat-band voltage, (VFB ,b ) Si = φsub − φSi ,

φsub is the substrate work function and ΔVFB ,b =

⎞ ⎛ N − (ΔEC ) s − Si (ΔEg ) s − Si + − VT ln⎜⎜ V , Si ⎟⎟ . q q ⎝ NV , s − Si ⎠

3. The surface potential at the source end is

φ (0, 0) = φs (0) = Vbi , s − Si

(28)

4. The surface potential at the drain end is

φ ( L, 0) = φs ( L ) = Vbi , s − Si + VDS where VDS is the drain-to-source bias voltage.

31

(29)

The coefficients c1 ( x ) and c2 ( x ) in equation (25) can be deduced from the boundary conditions (26) – (27). Substituting the values of c1 ( x ) and c2 ( x ) in (25), we obtain the expression for φ ( x, y ) . Then, substituting φ ( x, y ) in (24) and putting y=0, we obtain

d 2φs ( x) − αφs ( x) = β dx 2

(30)

where

α= where

(

2 1+

(

Cf Cb

t s2− Si 1 +

Cf =

ε ox tf

+

Cf C Si

2 C Si Cb

)

)

, C Si =

β=

,

ε Si t s − Si

qN A

ε Si

, Cb =

−

ε ox tb

2VGS '

(

(

Cf Cb

C

+ CSif

ts2− Si 1 + 2CCbSi

)

)−

2Vsub '

(

ts2− Si 1 + 2CCbSi

)

.

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form

φs ( x) = A exp(λx) + B exp(−λx) − σ

(31)

where λ = α and σ = β α . Now using boundary conditions (28) – (29) to solve for A and B, we obtain ⎧⎪ (Vbi , s − Si + σ + VDS ) − (Vbi , s − Si + σ ) exp ( −λ L ) ⎫⎪ A=⎨ ⎬ exp ( −λ L ) 1 − exp ( −2λ L ) ⎩⎪ ⎭⎪ ⎧⎪ (Vbi , s − Si + σ ) − (Vbi , s − Si + σ + VDS ) exp ( −λ L ) ⎫⎪ B=⎨ ⎬. 1 − exp ( −2λ L ) ⎪⎩ ⎪⎭

The minimum surface potential can be calculated from (31) by putting d φs ( x ) =0. dx

(32)

The minimum surface potential is

φs , min = 2 AB − σ

(33)

The threshold voltage Vth is that value of the gate voltage VGS at which a conducting channel is induced under the gate oxide at the surface of SOI MOSFET. In a fully depleted thin-film SOI, it is desirable that the front channel turns on before the back channel. Therefore, in a conventional unstrained silicon MOSFET, the threshold voltage is taken to be

32

that value of gate-source voltage for which φS ,min = 2φF , Si , where φF , Si is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level [20]. For the strained-Si MOSFETs, the condition for threshold is modified as [11]:

φs , min = 2φF , Si + Δφs − Si = φth where Δφs − Si =

− (ΔEg ) s − Si

q

(34)

⎞ ⎛ N + VT ln⎜⎜ V , Si ⎟⎟ . ⎝ NV , s − Si ⎠

and φth is that value of surface potential at which the inversion electron charge density in the strained-Si device is the same as that in unstrained-Si at threshold [11]. So the threshold voltage is defined as the value of VGS at which the minimum surface potential φS ,min equals φth . Hence we can determine the value of threshold voltage by substituting (33) into (34) and solving for VGS , as

⎛ − V + V 2 − 4ξV φ1 φ1 φ2 Vth = k ⎜⎜ 2ξ ⎜ ⎝

⎞ ⎟ ⎟⎟ ⎠

where ξ = 2 cosh ( λ L ) − 2 − sinh 2 ( λ L )

Vφ 1 = Vbi1 (1 − exp ( λ L ) ) + ( 2φth − 2u ) sinh 2 ( λ L ) − Vbi 2 (1 − exp ( −λ L ) )

Vφ 2 = Vbi1Vbi 2 − (φth − u ) sinh 2 ( λ L ) 2

Vbi1 = (Vbi,s−Si − u ) (1 − exp ( −λ L ) ) + VDS Vbi 2 = (Vbi , s − Si − u ) ( exp ( λ L ) − 1) − VDS

u=

(1+

Vsub ' Cf Cb

(1 + k = (

Cf Cb

+ Cf Cb

+

−

Cf CSi

)

+

Cf C Si

Cf C Si

)

qN A

ε Siα

−

(

Cf Cb

(1+

C

)

+

Cf CSi

+ CSif

Cf Cb

)

(VFB, f )s −Si

).

33

(35)

4.3 Results and Discussion

To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was used to simulate the threshold voltage of FD-SSOI MOSFETs for various device parameters and compared with the values predicted by the model. The threshold voltage is extracted from 2-D simulation using the commonly used maximum transconductance method. The

Threshold Voltage (volts)

parameters used in our simulation are given in Table 2.

0.5

Model Medici

0.4 0.3

x=0

0.2

x=0.2

0.1

x=0.4

0

-0.1 50

100

150

200

Gate Length , Lg (nm) Figure 12- Threshold voltage versus channel length L

Fig. 12 shows the variation of threshold voltage with gate length for different values of effective Ge mole fraction, and strained silicon thickness of 25 nm. It is observed that short channel effects become prevalent below 70-80 nm gate length and is marked by the sharp decrease in Vth value. The gate-S/D charge sharing and source-body/drain-body built-in potential barrier lowering [18] due to overlap of the lateral source-body and drain-body depletion regions become significant for such short channel lengths. Also, threshold voltage is lower for higher strain at the same gate length. This result can be confirmed from Fig. 13, which shows the variation of threshold voltage with change in strain for a gate length of 50 nm. It is evident that there is a significant fall in threshold voltage with increasing strain, and the decrease in Vth is almost linear. Vth rolls off drastically

34

with strain x, even going negative for Ge content of 0.3-0.4. The threshold voltage decreases with increasing Ge content x because of decrease in flat-band voltage (equation (3)), decrease in source-body/drain-body built-in potential barrier (equation (4)), and earlier onset of

Threshold Voltage (volts)

inversion due to decrease in φth (equation (34)).

Model Medici

0.25 0.2 0.15 0.1 0.05

tsi=15 nm

0 -0.05

tsi=10 nm

-0.1 0

0.1

0.2

0.3

0.4

Equivalent Ge Content Strain , x Figure 13- Threshold voltage versus strain x for different strained-Si film thicknesses ts-Si

Fig. 14 shows the variation of threshold voltage with thickness of strained Si thin film. It can be seen that Vth also reduces with decreasing thickness of strained Si thin film. This is because of the decrease in total depletion charge under the gate in the strained-Si thin film and increased gate-S/D sharing leading to early onset of inversion. Thus, a higher strained-Si film thickness is desirable for better performance; however it should not be much larger than the critical thickness to avoid misfit dislocations. The threshold voltage obtained from the model tracks the simulation values very well.

35

Threshold Voltage (volts)

0.4

Model Medici

0.3

x=0

0.2

x=0.2

0.1

x=0.4

0

-0.1

10

15

20

25

Strained Silicon Thin Film Thickness, tsi (nm) Figure 14- Threshold voltage versus strained-Si film thickness ts-Si.

Table 2: Device parameters used in the simulation (FD-SSOI) Parameter Value Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%) Source/Drain doping 2x1020 cm-3 1018 cm-3 Body doping, NA Gate Oxide Thickness, tf 2.0 nm 4.35 eV (n+ poly Si) Work function of gate material, φM

Strained-Silicon film thickness, ts-Si Buried Oxide Thickness, tb Substrate bias, Vsub Drain bias, VDS

10 nm – 25 nm 100 nm 0 Volts (Gnd) 0.05 Volts (50 mV)

4.4 Concluding Remarks

SSOI devices are free of the high off-state leakage current which can plague bulk strained Si/SiGe devices beyond the critical thickness. SSOI devices possess immunity to this misfit dislocation related leakage mechanism because the dislocation cores at the strained Si/SiGe interface are eliminated during the SSOI wafer fabrication process, opening a path to higher strain and associated performance levels. However, as the strain is increased the

36

threshold voltage rolls off, as seen from the model developed above. Therefore, the threshold voltage needs to be controlled through methods like varying gate work function. Another type of strained SOI device, the strained-Si on SGOI substrate is expected to have a high strain in Si layers using SiGe layers (with high Ge content) directly on Insulator, resulting in better performance. This has been studied in the next chapter.

37

Chapter V Fully Depleted Strained Silicon On SiGe-on-Insulator MOSFET 5.1 Introduction

The strained-Si on SGOI MOSFET also provides the advantages of the SOI structure including reduced parasitic capacitance and improved electrostatics. Fig. 15 shows the crosssection of a FD-strained-Si on SGOI MOSFET. This chapter deals with the derivation of an analytical threshold voltage model for the same. SGOI substrates can be fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques [28-30]. For a Fully Depleted structure, a strained-Si thin film is directly grown on this thin SGOI substrate. By varying the Ge mole fraction in SGOI layer, the amount of strain in the thin silicon layer on top can be controlled. 5.2 Threshold Voltage Model

Before the onset of strong inversion, the two-dimensional Poisson equation in the strained silicon thin-film of a FD-strained-Si on SGOI MOSFET can be written as [20]: d 2φ1 ( x, y ) d 2φ1 ( x, y ) qN A + = ε Si dx 2 dy 2

for 0 ≤ x ≤ L , 0 ≤ y ≤ ts − Si

(36)

where ε Si is the dielectric constant of silicon, and t s − Si is the strained-Si thin film thickness. Similarly, the Poisson equation in the Si1-xGex layer on insulator below, for full depletion, can be written as d 2φ2 ( x, y ') d 2φ2 ( x, y ') qN A + = dx 2 dy '2 ε SiGe

for 0 ≤ x ≤ L , 0 ≤ y ' ≤ tSiGe

where ε SiGe is the dielectric constant of Si1-xGex, and t SiGe is the its layer thickness.

38

(37)

VG

VS=0

Gate

tf

VD

Gate oxide

ts-si φ 1 ( x,y)

s-Si

NA tSiGe Si1-x Gex

n+ x=0

n+

y=0

φ 2( x,y') y' = 0

x=L

L tb

Buried oxide

Substrate VSub=0

Figure 15- Cross-sectional view of the FD-strained-Si on SGOI MOSFET.

The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 15) and the Si1-xGex layer below (y’-direction in Fig. 15) can be approximated by a parabolic function, as done in [20] as:

φ1 ( x, y ) = φs ( x ) + c11 ( x ) y + c12 ( x ) y 2

for 0 ≤ x ≤ L , 0 ≤ y ≤ ts − Si

φ2 ( x, y ') = φb ( x ) + c21 ( x ) y '+ c22 ( x) y '2 for 0 ≤ x ≤ L , 0 ≤ y ' ≤ tSiGe

(38) (39)

where φS ( x ) is the front channel surface potential at the gate-oxide/strained-Si interface, φb ( x ) is the back channel potential at the SiGe/Buried-Oxide interface, and the coefficients c11 ( x ) , c12 ( x ) , c21 ( x ) and c22 ( x )

are functions of x only. The Poisson equations (36) and (37)

can be solved using the following boundary conditions: 1. Electric flux (displacement) at the gate-oxide/strained-Si film interface is continuous.

⎡ d φ1 ( x , y ) ⎤ ε ox ⎛ φ s ( x ) − VGS = ⎜ ⎢ dy ⎥ tf ⎣ ⎦ y = 0 ε Si ⎜⎝

'⎞ ⎟⎟ ⎠

where ε ox is the dielectric constant of the gate oxide, t f is the gate oxide thickness, VGS ' = VGS − (VFB , f ) s − Si , and VGS is the gate-to-source bias voltage.

39

(40)

2. Electric flux at the interface of buried oxide and the SiGe back-channel is continuous. ⎡ dφ2 ( x, y ') ⎤ ε ⎛ φ ( x) − Vsub ' ⎞ = ox ⎜ b ⎟ ⎢ dy ' ⎥ tb ⎣ ⎦ y '=0 ε SiGe ⎝ ⎠

(41)

where tb is the buried oxide thickness, Vsub ' = Vsub − (VFB ,b ) SiGe , Vsub is the substrate bias, (VFB ,b ) SiGe = (VFB ,b ) Si + ΔVFB ,b,SiGe is the back-channel flat-band voltage, (VFB ,b ) Si = φsub − φSi ,

φsub is the substrate work function and ΔVFB ,b , SiGe =

(ΔEg ) SiGe q

⎛ N ⎞ − VT ln ⎜ V , Si ⎟ . ⎜N ⎟ ⎝ V , SiGe ⎠

3. Potential at the interface of strained-Si thin film and SiGe layer is continuous.

φ1 ( x , t s − Si ) = φ2 ( x , t SiGe )

(42)

4. Electric flux (displacement) at the interface of strained-Si thin film and SiGe layer is continuous.

⎡ d φ1 ( x, y ) ⎤ ⎡ d φ ( x, y ') ⎤ ε = − SiGe ⎢ 2 ⎢ dy ⎥ ε Si ⎣ dy ' ⎥⎦ y '=tSiGe ⎣ ⎦ y =ts−Si

(43)

5. The surface potential at the source end is

φ1 (0, 0) = φs (0) = Vbi , s − Si

(44)

6. The surface potential at the drain end is

φ1 ( L, 0) = φs ( L) = Vbi , s − Si + VDS

(45)

where VDS is the drain-to-source bias voltage. The coefficients c11 ( x ) , c12 ( x ) , c21 ( x ) and c22 ( x ) in equations (38) and (39) can be deduced from the boundary conditions (40) – (43). Thus, we obtain the expressions for

φ1 ( x, y ) and φ2 ( x, y ') . Substituting φ1 ( x, y ) in (36) and putting y=0, we obtain d 2φs ( x) − 2b1φs ( x) + 2a1φb ( x) = c1 dx 2

(46)

where

a1 =

Cb + 2CSiGe , 2t ( CSi + CSiGe ) 2 s − Si

b1 =

40

CSiGe + C f ( CSiGe CSi ) + ( C f 2 ) ts2− Si ( CSi + CSiGe )

,

qN A

c1 = and

Cf =

ε ox tf

, C Si =

ε Si

ε Si t s − Si

⎛ C f ( 2 ( CSiGe CSi ) + 1) VGS '− CbVsub ' ⎞ −⎜ ⎟ ⎜ ⎟ ts2− Si ( CSi + CSiGe ) ⎝ ⎠

, CSiGe =

ε SiGe t SiGe

,

Cb =

ε ox tb

.

Similarly, substituting φ2 ( x, y ') in (37) and putting y’=0, we obtain

d 2φb ( x) − 2a2φb ( x) + 2b2φs ( x) = c2 dx 2

(47)

where

a2 =

CSi + Cb ( CSi CSiGe ) + ( Cb 2 ) , 2 tSiGe ( CSi + CSiGe ) c2 =

qN A

ε SiGe

b2 =

C f + 2CSi 2t

2 SiGe

( CSi + CSiGe )

,

⎛ Cb ( 2 ( CSi CSiGe ) + 1) Vsub '− C f VGS ' ⎞ −⎜ ⎟ 2 ⎜ ⎟ tSiGe ( CSi + CSiGe ) ⎝ ⎠

Eliminating φb ( x) from equations (46) and (47), we obtain d 4φs ( x) d 2φs ( x) − ( 2a2 + 2b1 ) + 4 ( a2b1 − a1b2 ) φs ( x) = −2 ( a2 c1 + a1c2 ) dx 4 dx 2

(48)

The exact solution to the above fourth-order differential equation would be too complicated for a simple compact model that we are striving to obtain, and thus to gain any physical insight. Noting that the surface potential variation φs ( x) , across the front channel from the source to the drain, is quite smooth and does not vary rapidly (especially for gate voltage close to the threshold voltage of MOSFET), we neglect its fourth derivative with respect to the other terms. This approximation is quite valid as we can see from Fig.16. Thus equation (48) reduces to

d 2φs ( x) − αφs ( x) = β dx 2 where

⎛ a2 c1 + a1c2 ⎞ ⎟ ⎝ a2 + b1 ⎠

⎛ a2b1 − a1b2 ⎞ ⎟, ⎝ a2 + b1 ⎠

β =⎜

α = 2⎜

41

(49)

Distance from source (nm)

10

20

30

40

50

Potential ,Volts

0.98 0.96 0.94 0.92

0.90 0.88

Vgs = 0.15V actual surface potential approximate surface potential Figure 16 – Surface potential variation along the channel

Thus equation (48) reduces to

d 2φs ( x) − αφs ( x) = β dx 2

(49)

where

⎛ a2 c1 + a1c2 ⎞ ⎟ ⎝ a2 + b1 ⎠

⎛ a2b1 − a1b2 ⎞ ⎟, ⎝ a2 + b1 ⎠

β =⎜

α = 2⎜

The solution for equation (49), which is a simple second-order non-homogenous differential equation with constant coefficients, can be written as:

φs ( x) = A exp(λx) + B exp(−λx) − σ

(50)

where λ = α and σ = β α . Now using boundary conditions (44) – (45) to solve for A and B, we obtain ⎧⎪ (Vbi , s − Si + σ + VDS ) − (Vbi , s − Si + σ ) exp ( −λ L ) ⎫⎪ A=⎨ ⎬ exp ( −λ L ) 1 − exp ( −2λ L ) ⎩⎪ ⎭⎪ ⎧⎪ (Vbi , s − Si + σ ) − (Vbi , s − Si + σ + VDS ) exp ( −λ L ) ⎫⎪ B=⎨ ⎬. 1 exp 2 λ L − − ( ) ⎩⎪ ⎭⎪

42

In order to obtain a model for the threshold voltage, we need to find the minimum surface potential from (50) by putting d φs ( x ) =0 dx

(51)

This will give us the minimum surface potential as:

φs , min = 2 AB − σ

(52)

The threshold voltage Vth is that value of the gate voltage VGS at which a conducting channel is induced under the gate oxide at the surface of SOI MOSFET. In a fully depleted thin-film SOI, it is desirable that the front channel turns on before the back channel. Therefore, in a conventional unstrained silicon MOSFET, the threshold voltage is taken to be that value of gate-source voltage for which φS ,min = 2φF , Si , where φF , Si is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level [20]. For the strained silicon on SGOI MOSFET, the condition for threshold is modified as [11]:

φs , min = 2φF , Si + Δφs − Si = φth where Δφs − Si =

− (ΔEg ) s − Si q

(53)

⎛ N ⎞ + VT ln⎜⎜ V , Si ⎟⎟ , ⎝ NV , s − Si ⎠

and φth is that value of surface potential at which the inversion electron charge density in the strained-Si device is the same as that in unstrained-Si at threshold. Therefore, the threshold voltage is defined as the value of VGS at which the minimum surface potential φS ,min equals φth . Hence we can determine the value of threshold voltage by substituting (52) into (53) and solving for VGS as: 2 1 ⎛⎜ −Vφ 1 + Vφ 1 − 4ξVφ 2 Vth = k⎜ 2ξ ⎝

⎞ ⎟ ⎟ ⎠

where ξ = 2 cosh ( λ L ) − 2 − sinh 2 ( λ L )

Vφ 1 = Vbi1 (1 − exp ( λ L ) ) + ( 2φth − 2u ) sinh 2 ( λ L ) − Vbi 2 (1 − exp ( −λ L ) )

Vφ 2 = Vbi1Vbi 2 − (φth − u ) sinh 2 ( λ L ) 2

43

(54)

Vbi1 = (Vbi,s−Si − u ) (1 − exp ( −λ L ) ) + VDS Vbi 2 = (Vbi , s − Si − u ) ( exp ( λ L ) − 1) − VDS

u=

⎡ a1Cb ( 2 ( CSi CSiGe ) + 1) ⎤ ⎛ a2 Vsub ' a2Cb qN A a1 ⎞ − 2 − k (VFB, f )s−Si ⎢ ⎥− ⎜ + 2 ( a2b1 − a1b2 ) ⎢⎣ 2tSiGe ( CSi + CSiGe ) 2ts−Si ( CSi + CSiGe ) ⎥⎦ 2 ( a2b1 − a1b2 ) ⎝ ε Si ε SiGe ⎠⎟

k=

⎡ a2C f ( 2 ( C SiGe C Si ) + 1) ⎤ a1C f 1 − ⎢ ⎥ 2 2t SiGe ( a2b1 − a1b2 ) ⎢⎣ 2ts2− Si ( CSi + CSiGe ) ( CSi + CSiGe ) ⎥⎦

5.3 Results and Discussion

To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was used to simulate the threshold voltage of FD-strained-Si on SGOI MOSFETs for various device parameters and compared with the values predicted by the model. The threshold voltage is extracted from 2-D simulation using the commonly used maximum transconductance method. The parameters used in our simulation are given in Table 3. Fig. 17 shows the variation of threshold voltage with change in strain (Ge content in SiGe) for a gate length of 50 nm (effective channel length of 45 nm). We can observe that the threshold voltage decreases almost linearly with increasing strain (even becoming negative for a Ge content of 0.3-0.4), and the decrease in Vth is quite significant. This reduction in the threshold voltage with increasing Ge content x can be attributed to a decrease in the flat-band voltage (equation (3)), decrease in the source-body/drain-body built-in potential barrier (equation (4)), and an earlier onset of inversion due to a decrease in φth (equation (53)). It can also be noticed that the threshold voltage is slightly higher for a thicker strained-silicon film, which may be due to an increase in the depletion charge. The threshold voltage obtained from the model tracks the simulation values well. Fig. 18 shows the variation of threshold voltage with gate length for different values of Ge mole fraction in the SGOI layer, for a strained-silicon thickness of 5 nm and SiGe thickness of 10 nm. It is observed that Vth falls sharply below ~75nm gate length, due to short channel effects like Drain Induced Barrier Lowering (DIBL), the gate-S/D charge sharing etc. The Vth values from the analytical model are in close proximity with the simulation results.

44

Figure 17- Threshold voltage versus strain x for different strained-Si and SiGe film thicknesses

Figure 18- Threshold voltage versus channel length L

45

Fig. 19 also shows the variation of threshold voltage with gate length – however, here Vth is extracted from MEDICI as the gate voltage at which surface inversion electron concentration becomes equal to background doping. It is evident that there is an excellent match between model and simulation, thus confirming the model calculations. Therefore, the small difference between model and simulations in various plots can be attributed to the difference in the method of Vth calculation (Model: Ninv = NA; MEDICI: Maximum Transconductance).

Figure 19- Threshold voltage versus channel length L

Fig. 20 shows the effect of variation in body doping concentrations and gate work functions on the threshold voltage for a gate length of 50 nm. It is evident that by using a higher work function (eg. Mid-gap metal with φM =4.71 eV) material, we can afford a lower doping and higher Ge concentration for the same Vth, thus achieving higher carrier mobility due to lower impurity scattering and higher strain. This is because a higher workfunction gate increases the flat-band voltage (equation (3)) as compared to a normal n+ poly-Si gate ( φM =4.35 eV).

46

Figure 20- Threshold voltage versus strain x for different body dopings

Fig. 21 shows the variation of threshold voltage versus the SiGe layer thickness, for a fixed strained-Si film thickness. It can be seen that Vth is almost constant with change in thickness of SiGe. The possible increase in Vth due to increase in the total depletion charge under the gate (with increase in SiGe thickness), is mitigated by the enhanced SCEs due to higher permittivity of SiGe. The higher permittivity of SiGe enhances the SCEs, leading to worse roll-off in thicker SiGe. This is probably because the number of lines of electric force, which increase in SiGe with the high permittivity, can lower the source-to-channel potential barrier, leading to increase drain-induced barrier lowering (DIBL) [15]. As a result, thinner SiGe layers are preferable.

47

Figure 21- Threshold voltage versus SiGe film thickness tSiGe.

In order to examine the Drain Induced Barrier Lowering (DIBL) effect for shortchannel strained-Si on SGOI MOSFETs, the saturation threshold voltage was extracted from MEDICI simulations using the modified constant-current method at VDS = 0.5 V, where the critical current is defined as the drain current when the gate voltage is equal to the linear threshold voltage [31]. Fig. 22 shows the variation of saturation threshold voltage with gate length for different values of Ge mole fraction in the SGOI layer, for a strained-silicon thickness of 5 nm and SiGe thickness of 10 nm. Again, it is evident that Vth falls drastically below ~75nm gate length, due to short channel effects. The Vth values from the analytical model are in close proximity with the simulation results. The DIBL is computed as the difference between the linear (VDS = 0.05 V) and saturation (VDS = 0.5 V) threshold voltages. Fig. 23 shows the DIBL variation with gate length for 20% Ge mole fraction. It is observed that the DIBL is significant for small channel lengths (below 60-70 nm), while it is negligible for longer channel lengths (above 100 nm).

48

Figure 22- Saturation Threshold voltage versus channel length L

Figure 23- Drain Induced Barrier Lowering (DIBL) versus channel length L

49

Table 3: Device parameters used in simulation (FD-strained-Si on SGOI MOSFET) Parameter Value Ge mole fraction in SiGe layer 0 – 0.4 (0 – 40%) Source/Drain doping 2x1020 cm-3 1017 cm-3 , 1018 cm-3 Body doping, NA Gate Oxide Thickness, tf 2.0 nm 4.35 eV (n+ poly Si), Work function of gate material, φM 4.71 eV (Mid-Gap metal gate) 2 nm – 10 nm Strained-Silicon film thickness, ts-Si Silicon-Germanium film thickness, tSiGe 2 nm – 10 nm Buried Oxide Thickness, tb 100 nm Substrate bias, Vsub 0 Volts (Gnd) Drain bias, VDS 0.05 V, 0.5 V 5.4 Concluding Remarks

Strained Silicon-on-Insulator technology offers significant performance enhancement over conventional bulk silicon and Silicon-on-Insulator technology [32]. The increase in strain, i.e. Ge content in SiGe, enhances the performance of strained-Si on SGOI MOSFETs in terms of improved transconductance and speed because of an increase in the carrier mobility and velocity overshoot effects. However, as we have demonstrated, deleterious effects of Vth roll-off with increasing strain, can affect the device characteristics and performance significantly. In the next chapter, we investigate into the current drive enhancement promised by strained-Si devices and whether the same can be achieved for extremely short channel devices. An analytical model for the output characteristics of nanoscale strained-Si/SiGe bulk MOSFETs is developed for this purpose. .

50

Chapter VI Analytical Drain Current Model for Strained-Si/SiGe MOSFETs 6.1 Introduction

The low field mobility of carriers (μeff) is enhanced due to strain in Si thin films grown pseudomorphically over a relaxed SiGe substrate [33]. However, for short channel devices, high-field effects like velocity saturation work against this enhancement, and hence the benefits of strained-Si for sub-100 nm CMOS are not obvious. In spite of this, enhanced current drive and transconductance has been experimentally observed in deep submicron strained-Si devices as well [49]. Non-local effects like velocity overshoot become prominent as MOSFET dimensions shrink to the nanoscale regime, and this is directly related with the aforementioned improvement in current drive observed in short-channel MOSFETs [34]. It has been shown that an electric field step can result in the electron velocity exceeding the saturation velocity for a period shorter than the energy relaxation time τw (which is an average time constant associated with the energy scattering process, or the time needed by the electron to once again reach equilibrium with the lattice), thus causing the electron to approach ballistic transport conditions. Strain in the silicon thin film also leads to an increase in the energy relaxation time (τw) of carriers, thus increasing the velocity overshoot [48]. Hence, to account for current enhancement in short channel strained-Si devices, the velocity overshoot effect has to be considered [35]. 6.2 Model for output characteristics of Strained-Si/SiGe nMOSFET

The low-field mobility of carriers is enhanced in strained-Si channels on SiGe substrates due to reduced phonon scattering [22] and carrier redistribution in the modified energy-subband structure [36]. The mobility enhancement factor ‘en’ for electrons, for different values of Ge mole fraction ‘x’ of the relaxed SiGe substrate, is calculated based on theoretical models [22,37] as en = 1 for x = 0, en = 1.46 for x = 0.1, en = 1.68 for x = 0.2

(55)

The above values are found to agree well with experimental data [38]. The electron mobility enhancement is found to be sustained at high values of the transverse electric field ‘ Eeff ’ as well ( ~ 70% enhancement (en = 1.7) for x = 0.2, even for Eeff as high as 1.5 MV/cm) [3].

51

Using the Watt mobility model, the effective mobility of inversion layer electrons in the channel at the gate-oxide / strained-Si film interface can be written as [14,39,40]: −1 μeff = ( μ ph + μ sr−1 + μc−1 )

where μ ph

⎛E ⎞ = en ( 481) ⎜ eff6 ⎟ ⎝ 10 ⎠

−0.16

⎛E ⎞ , μ sr = en ( 591) ⎜ eff6 ⎟ ⎝ 10 ⎠

−1

−2.17

(56) 1.07

⎛N ⎞ , μc = en (1270 ) ⎜ inv 12 ⎟ ⎝ 10 ⎠

⎛ 1018 ⎞ ⎜ ⎟. ⎝ NA ⎠

Here μ ph is the mobility associated with phonon scattering, μ sr is the mobility associated with surface roughness scattering and μc is the mobility associated with coulomb/ionic impurity scattering, all in units of cm2/V.s. The transverse electric field Eeff is given by [41]: Eeff =

where N inv ≅

N inv ⎞ q ⎛ ⎜ Nd + ⎟ ε Si ⎝ 2 ⎠

(57)

Cox (VGS − Vth ) and N d ≅ N A xd . q

In equation (57), N inv is the inversion electron sheet density (per unit area), N d is the bulk depletion charge density per unit area under the gate, and xd is the average depletion depth under the gate (see equation (7) and (8)). To account for velocity saturation in nanoscale devices at high longitudinal electric fields, the following two-region piecewise empirical model for velocity vDD ( x ) versus longitudinal electric field Ex (for electrons in the inversion layer) has been used [42,43]: vDD ( x ) =

1+

μeff E μeff Ex x

vDD ( x ) = vsat

where

Esat =

2vsat

μeff

for E ( x ) ≤ Esat

(58)

for E ( x ) > Esat

(59)

2vsat

is the saturation electric field, vsat ; 1× 107 cm / s is the saturation

velocity [14], and x is the distance from the source along the channel. The above is the simple drift-diffusion model for carrier transport. However, for nanoscale devices, non-local effects like velocity overshoot play a significant role. This overshoot occurs in scaled devices because of the large gradient in the longitudinal electric field in the channel, and the average carrier transit time from source to drain being 52

comparable to, or less than, the average energy relaxation time, τ w [47]. The carrier kinetic energy, or equivalently the carrier temperature, lags the local field due to this finite energy relaxation time τ w , or relaxation length δ ( Ex ) . When carriers are injected into the high-field region of a scaled MOSFET channel, their random thermal kinetic energy is smaller than that implied by the local field. Since the carrier mobility is inversely proportional to the carrier energy, these carriers have mobilities that are high, and therefore move with velocities higher than those implied by a local velocity-field model, i.e., they experience, on the average, quasi-ballistic flow. The average velocity of the carriers can hence be higher than the saturation velocity. Thus, including the velocity overshoot effect, the expression for carrier velocity along the channel is modified as [44-46]: ⎛ δ ( Ex ) dEx v ( x ) = vDD ( x ) ⎜ 1 + Ex dx ⎝

⎞ ⎛ 2vsatτ w dEx ⎞ ⎟ ≅ vDD ( x ) ⎜1 + ⎟ 3Ex dx ⎠ ⎝ ⎠

(60)

Due to strain, the high field transport properties of carriers in the inversion layer are also modified. Although the change in the saturation velocity with strain is expected to be small, transient transport calculations at high lateral (longitudinal) fields show a significant enhancement of the transient velocity overshoot with increasing energy splitting between the conduction subbands i.e. with increasing strain [48]. This effect can be attributed to an increase in the energy relaxation time with increasing strain [49]:

τ w = 0.1 ps for x=0, τ w = 0.15 ps for x=0.1, τ w = 0.2 ps for x=0.2

(61)

where x is the Ge mole fraction in Si1-xGex substrate. From equations (58) and (60), we get v ( x) = 1+

μeff ⎛ 2v τ dEx ⎞ Ex ⎜1 + sat w ⎟ μeff Ex ⎝ 3Ex dx ⎠

(62)

2vsat

To estimate the gradient of the longitudinal electric field along the channel, we assume a quadratic variation of the electrostatic potential along the channel as

a VDS 2 ⎛ a ⎞V V ( x) ≅ ⎜1 − ⎟ DS x + x 2 L2 ⎝ 2⎠ L where a is a constant that could be dependent on device parameters and technological features of the MOSFET. Comparing model with simulation, we get a ≈ 0.2 . Thus,

53

(63)

2 dEx d V ( x ) V = = a DS2 2 dx dx L

(64)

This approximation is quite valid in strong inversion conditions and similar expressions can also be found in [50,51]. It helps us in finally obtaining a closed form analytical expression for the output drain current. Substituting (64) into (62) we get, v ( x) = 1+ where k =

μeff μeff Ex

VDS ⎞ ⎛ ⎜ Ex + k L2 ⎟ ⎝ ⎠

(65)

2vsat

2avsatτ w . 3

To derive the current expression, we first write the current at any point x along the channel as I D = WQinv ( x ) v ( x ) = WCox (VGS − Vth − V ( x ) ) v ( x )

(66)

where W is the device width. Therefore, v ( x) =

ID WCox (VGS − Vth − V ( x ) )

Putting (65) in (67) and using Ex =

(67)

dV ( x ) we get: dx

μeff dV ( x ) ⎞ ⎛ ⎛ dV ( x ) V ⎞ I D ⎜1 + + k DS2 ⎟ ⎟ = μeff WCox (VGS − Vth − V ( x ) ) ⎜ L ⎠ ⎝ 2vsat dx ⎠ ⎝ dx

(68)

By integrating the above equation from x= 0 to x= L and V(0) = 0 to V(L) =VDS, we arrive at ID =

μeff WCox ⎛ μeff VDS

2 2 ⎡⎛ ⎤ ⎞ ⎛ k ⎞ ka VDS VDS V V V − − + + 1 ( ) ⎢⎜ GS ⎥ ⎟⎜ th DS ⎟ 2 ⎠ ⎝ L ⎠ 12 L ⎦ ⎞ ⎣⎝ L ⎜1 + ⎟ 2vsat L ⎠ ⎝

where

VDS , sat =

for VDS ≤ VDS , sat

(69)

VGS − Vth is the drain voltage at which the carriers at the drain become VGS − Vth 1+ Esat L

velocity saturated [43]. When VDS is greater than VDS,sat, the velocity saturation or pinch-off point moves towards the source, away from the drain, by a distance ld. The voltage difference VDS - VDS,sat is dropped across this distance ld, where ld is the channel length modulation, given by [51]:

54

⎛ V − VDS , sat ld = lc sinh −1 ⎜⎜ DS ⎝ lc Esat where lc =

ε av xdv

2 ( Cox + Cd )

, ε av ;

ε Si + ε SiGe 2

, Cd =

⎞ ⎟⎟ ⎠

(70)

ε av xdv

and xdv is the vertical depletion region

depth under the gate (as defined in equation (6)). Hence, to obtain the current expression in the saturation region, we integrate equation (68) from x = 0 to x = L - ld, and get

IDsat =

⎡ ⎛ k VDS ⎛ ld ⎞ ⎞ VDS2 ,sat k VDS2 ⎛ ld ⎞2 ⎛ a a ld ⎞⎤ μeff WCox − ⎢(VGS −Vth )VDS,sat ⎜⎜1+ ⎜1− ⎟ ⎟⎟ − ⎜1− ⎟ ⎜1− − ⎟⎥ 2 2 L ⎝ L ⎠ ⎝ 6 3 L ⎠⎦⎥ ld μeff VDS,sat ⎞ ⎣⎢ ⎝ L VDS ,sat ⎝ L ⎠ ⎠

⎛ L⎜1− + ⎟ ⎝ L 2vsat L ⎠

for VDS > VDS , sat

(71)

Equations (69) and (71) reduce to the familiar velocity saturation limited drift-diffusion current model given in [43] - and used in many previous works - for k = 0 i.e. no velocity overshoot. To complete the analysis, we consider the impact ionization and avalanche multiplication of carriers in the high-field region near the drain in the saturation regime. The generation current (due to holes flowing into the substrate and electrons flowing out of the drain), can be written as [52]: I G = (M − 1)I D , sat

(72)

where the multiplication factor ( M − 1) is given by [53] ⎛

(M − 1) = α (VDS − VDS ,sat )exp⎜⎜

⎝ VDS

−β − VDS , sat

⎞ ⎟ ⎟ ⎠

(73)

where α and β are fitting parameters [54]. We have used α = 0.15 and β = 15.7 (from [7, 53]) in our model. For strained Si devices, the ionization rate increases with increasing strain, because of the reduction in the bandgap of Si - (ΔEg ) s − Si (see eqn. (1)) - induced by the strain at the Si/SiGe heterointerface [48]. Hence the multiplication factor is modified as: ⎛

( M − 1) = α (VDS − VDS ,sat ) exp ⎜⎜

⎝ VDS

−β − VDS , sat

⎞ ⎛ (ΔEg ) s − Si ⎞ ⎟⎟ exp ⎜ ⎟ ⎝ qVT ⎠ ⎠

(74)

Hence the total drain current in the saturation region can be written as: for VDS > VDS , sat

I D = I D , sat + I G

55

(75)

6.3 Results and Discussion

The low-field mobility enhancement in strained-Si n-MOSFETs can be explained by suppressed intervalley scattering and reduced effective mass, due to the strain-induced conduction band energy splitting [1]. However, high-field and transient transport properties are expected to dominate the characteristics of deep submicron MOSFETs. Hence, hydrodynamic (HD) (energy balance) device simulations were carried out using MEDICI [14] to analyze the impact of low field mobility and high field transport on device characteristics. In hydrodynamic modeling of current transport, the strength of transient transport behavior is represented by the energy relaxation time τ w . With increasing strain, τ w increases and almost doubles for x = 0.2, indicating that the transient electron velocity overshoot is significantly enhanced. The Watt surface mobility model is used to model the transverse-field dependent low field mobility, whereas, the high lateral-field transport is modeled with “carrier temperature based mobility” (TMPMOB) [14]. In this approach, the energy balance equation is locally solved concurrently with the drift-diffusion equation, to calculate the local mobility as a function of the local carrier temperature. The simulation parameters used are given in Table 4. Fig. 24 shows the drain current enhancement with change in strain (Ge content in SiGe) for a gate length of 50 nm and VGS = 0.75 V. We can observe that there is a significant increase in the drain current with increasing strain. This can be attributed to three main factors: 1) the increase in electron velocity overshoot due to increase in the energy relaxation time τ w , 2) increase in low field mobility and 3) decrease in threshold voltage Vth . Thus it is evident that strained Si provides current enhancement even for nanoscale devices. However, for a particular technology, it is desirable to have approximately the same Vth for various devices. Therefore, to exclude the contribution of decrease in Vth to current enhancement, we plot the normalized current ( I DS (VGS − Vth ) ) versus drain voltage in Fig. 25. Clearly, we can see that strained Si offers tremendous improvement in current drive. The model predictions are in close proximity with simulation data.

56

-3

2

x 10

MEDICI Model

x = 0.2

Ids (A/um)

1.5 x = 0.1 1 x=0

0.5 Vgs = 0.75 V tox = 2 nm 0 0

0.2

0.4

0.6

0.8

1

Vds (Volts) Figure 24- Comparison of drain current for different Ge concentrations.

-3

Ids/(Vgs-Vth) (A/um/V)

3

x 10

2.5

MEDICI Model

x = 0.2

x = 0.1

2 1.5

x=0

1 Vgs = 0.75 V

0.5

tox = 2 nm 0 0

0.2

0.4

0.6

0.8

1

Vds (Volts) Figure 25- Comparison of normalized drain current for different Ge concentrations.

57

Figs. 26, 27 and 28 show the output characteristics for different Ge mole fractions ‘x’ in the SiGe substrate (0, 0.1 and 0.2 respectively), and corresponding gate oxide thicknesses tox, in order to keep roughly the same value of Vth ~ 0.25 V. It is observed that strained-Si

MOSFETs are able to achieve the same current drive as conventional unstrained MOSFETs, even with a drastic increase in oxide thickness. There is a good agreement between model and simulation throughout the range of device parameters and bias conditions. Our model deviates slightly from the simulation results for VGS very close to Vth and VGS ? Vth , because for these voltages our approximation for the inversion charge, N inv ≅

Cox (VGS − Vth ) , is not valid. However, as can be seen from the figures, an excellent q

agreement is obtained for gate voltages ( VGS ) upto 1.0 volt, which is expected to be the supply voltage for this technology (50 nm gate length).

2

x 10

-3

x=0 t ox= 2 nm

MEDICI Model

Ids (A/um)

1.5 Vgs = 1 V

1

Vgs = 0.8 V

Vgs = 0.6 V

0.5 Vgs = 0.4 V

0 0

0.2

0.4

0.6

0.8

1

Vds (Volts) Figure 26- Output characteristics for conventional unstrained MOSFET (x = 0)

58

-3

2

x 10

x = 0.1 t ox= 4 nm

MEDICI Model

Ids (A/um)

1.5

Vgs = 1 V

1

Vgs = 0.8 V

0.5

Vgs = 0.6 V Vgs = 0.4 V

0 0

0.2

0.4

0.6

0.8

1

Vds (Volts) Figure 27- Output characteristics for x = 0.1 and tox = 4 nm

2

x 10

-3

x = 0.2 t ox= 5 nm

MEDICI Model

Ids (A/um)

1.5

1

Vgs = 1 V Vgs = 0.8 V Vgs = 0.6 V

0.5

Vgs = 0.4 V

0 0

0.2

0.4

0.6

0.8

Vds (Volts) Figure 28- Output characteristics for x = 0.2 and tox = 5 nm

59

1

Fig. 29 shows the output characteristics for 20% Ge fraction in the SiGe substrate, with a mid-gap metal gate. We can again see that the model values track the simulation data well, thus confirming the validity of the model over different gate workfunctions as well. 2

x 10

-3

x = 0.2 t ox= 2 nm

MEDICI Model

Ids (A/um)

1.5 Mid-gap metal gate 4.71 eV

Vgs = 1 V

1 Vgs = 0.75 V

0.5 Vgs = 0.5 V

0 0

0.2

0.4

0.6

0.8

1

Vds (Volts) Figure 29- Output characteristics for x = 0.2, tox = 2nm and

φM = 4.71 eV

Table 4: Device parameters used in the simulation (output characteristics of s-Si/SiGe MOSFET) Parameter Value Ge mole fraction of SiGe substrate, x 0 – 0.2 (0 – 20%) Source/Drain doping 2x1020 cm-3

Body doping, NA

1018 cm-3

Gate Length, L

50 nm

Gate Oxide Thickness, tf

2.0 nm – 6.0 nm 4.35 eV (n+ poly Si)

Work function of gate material, φM Strained-Silicon film thickness, ts-Si

15 nm

Source/drain junction depth, rj Substrate bias, Vsub Drain bias, VDS

50 nm 0 Volts (Gnd) 0.0 – 1.0 Volts

Gate bias, VGS

0.4 – 1.0 Volts (Vth ~ 0.25 V)

60

6.4 Concluding Remarks

Strain in the Si channel is emerging as a powerful technique of increasing MOSFET performance. As we have demonstrated above, strain-induced enhancements will persist even for extremely short channel length devices. Non-equilibrium high-field effects like velocity overshoot contribute highly to the increase in current drive of these nanoscale devices. Improvements in n-MOSFET performance can be obtained in a wide range of operating conditions with moderate strain. Experimental evidence corroborating the same is also widely reported [49,55].

61

Chapter VII Conclusions For the first time, we have examined the effect of various device parameters like strain (Ge mole fraction), gate length, source/drain junction depths, substrate (body) doping, strained silicon thin film thickness, and gate work function on the threshold voltage of nanoscale Strained-Si/SiGe, Fully Depleted-Strained Silicon On Insulator (FD-SSOI), and Fully Depleted-Strained Silicon On SiGe-on-Insulator (SGOI) MOSFETs by developing analytical models for the same. The 2-D Poisson equation is solved in the strained-Si thin film using appropriate boundary conditions. The model results are compared with accurate two-dimensional simulations [14]. The calculated values of the threshold voltage obtained from the proposed model agree well with the simulated results. There is a significant drop in threshold voltage with increasing equivalent Ge content and decreasing channel length. The increase in strain, i.e. Ge content, enhances the performance of MOSFETs in terms of transconductance and speed because of an increase in the carrier transport properties [1]-[5]. However, as demonstrated by our results, there are undesirable side effects with increasing Ge content such as a roll-off in Vth, which may affect the device characteristics and performance significantly. Our compact model accurately predicts the threshold voltage over a large range of device parameters and can be effectively used to design and characterize nanoscale Strained Si/SiGe, FD-SSOI, and FD-strained-Si on SGOI MOSFETs with the desired performance. We have also developed an analytical model for the output drain current characteristics of short channel Strained-Si/SiGe MOSFETs by taking into account various high field effects like velocity overshoot, velocity saturation, DIBL, Impact Ionization etc. We demonstrate a significant current enhancement due to strain even in the nanoscale regime, thus corroborating the advantages of strained-Si devices over a wide range of device parameters. Our model gives a simple method for predicting the performance of strainedSi/SiGe MOSFETs given the device parameters and bias conditions.

62

Future Work:

To extend our I-V model to the entire range of MOSFET operation (subthreshold current etc.) and different strained Si device structures like SSOI and SGOI MOSFETs thus completing the current modeling of strained Si devices. Also, methods for controlling Vth roll-off with increasing strain and decreasing channel length need to be investigated.

63

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