Microelectronics - Today And Tomorrow

Dr.D.N. Singh Professor, Bharti Chair in Telecommunication and Information Technology UIET, Panjab University, Chandigarh. E-mail: [email protected]

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♦INFORMATION

TECHNOLOGY, THE COMBINATION OF COMMUNICATIONS AND COMPUTER TECHNOLOGY RIDING ON THE TIDAL WAVE OF SEMICONDUCTOR TECHNOLOGY, IS ACKNOWLEDGED TO BECOME THE MAJOR DRIVER OF WORLD ECONOMY IN THE 21ST CENTURY. ♦IN

THIS NEW SO CALLED KNOWLEDGE ERA, VLSIs/SOCs (INCLUDING EMBEDDED SYSTEMS’) ARE GOING TO CONTINUE TO PLAY A KEY ROLE EVEN WHILE MICROELECTRONICS IS ON THE THRESHOLD OF MOVING TO NANOELECTRONICS BASED PERHAPS ON ALTOGETHER NEW APPROACH. ♦ECONOMIC

WELL-BEING OF THE NATIONS IN FUTURE WILL INDEED BE CLOSELY TIED TO THEIR ABILITY TO COMPETE IN THIS HIGH TECH AREA. ♦SEMICONDUCTOR

INDUSTRY IS ONE OF THE FEW INDUSTRIES THAT HAS GROWN AT A COMPOUND AVERAGE RATE OF MORE THAN 15 PERCENT FOR THE LAST 40 YEARS AND IS PRESENTLY OSCILLATING AROUND US$ 200 BILLION.

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IT PRACTICALLY CONTROLS THE OEM MARKET OF ABOUT US$1 TRILLION.

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SEMICONDUCTOR INDUSTRY TODAY MANUFACTURES APPROXIMATELY 60 MILLION TRANSISTORS AND BY 2008 WILL MANUFACTURE APPROXIMATELY ONE BILLION TRANSISTORS FOR EVERY INDIVIDUAL ON THIS EARTH.

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SEMICONDUCTOR MARKET GROWTH

Automobile

IT IS EXPECTED THAT SEMICONDUCTOR INDUSTRY WILL OVERTAKE STEEL BY 2010 AS A CONTRIBUTOR TO THE GNP.

GIVEN THIS SCENARIO, CAN INDIA, ASPIRING TO BE A DEVELOPED NATION, AFFORD NOT TO PLAY A SIGNIFICANT ROLE IN THIS KEY SECTOR OF ECONOMY? IN FACT IT MUST CHANNELISE A MAJOR FRACTION OF ITS ACKNOWLEDGED LARGE POOL OF SCIENTIFIC AND TECHNICAL MANPOWER TO PARTICIPATE IN THIS MAJOR AREA IN A MORE SIGNIFICANT WAY.

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BY THE YEAR 2010, ALL PREDICTIONS INDICATE A TECHNICAL CAPABILITY TO FABRICATE MORE THAN 1 BILLION LOGIC GATES OR 64 GBITS OF MEMORY PER CHIP IN 0.07 MICRON TECHNOLOGY AT 0.6 V OPERATING VOLTAGE.

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OVERALL PERFORMANCE, POWER DISSIPATION AND RELIABILITY OF SINGLE CHIP SYSTEMS WILL BE LIMITED BY INTERCONNECTIONS AMONG DEVICS AND THE IMPLICATIONS OF INTERCONNECT (COMMUNICATION) WILL DOMINATE ALL ASPECTS OF THE DESIGN PROCESS, FROM FUNDAMENTAL PROCESS TECHNOLOGY TO SYSTEM LEVEL ARCHITECTURE.

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MINIMIZATION OF POWER CONSUMPTION IS CRITICAL FOR BOTH PORTABLE AND STATIONARY SYSTEMS. TODAY 8% OF THE WORLD’S ELECTRIC POWER IS CONSUMED BY THE COMPUTERS AND INTERNET AND THIS COULD RISE TO 50% BY 2010.

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IN 2010, A SINGLE CHIP COULD CONTAIN 4 GBITS OF DRAM AND A PROCESSOR CONTAINING 25 TIMES THE TRANSISTORS USED BY THE STATE-OF-THE-ART PROCESSORS IN USE TODAY AND RUN AT 2GHz. THE SAME CHIP COULD ALSO CONTAIN A MILLION GATE OF FIELD PROGRAMMABLE LOGIC AND ASSOCIATED ON-BOARD 400 GBIT MEMORY, RUNNING AT 200 MHz

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BECAUSE OF THE COMPLEXITY OF SUCH DESIGNS, ACCEPTABLE DESIGN PRODUCTIVITY IS ONLY POSSIBLE THROUGH RE-USE OF EXISTING COMPONENTS AND STRUCTURES ON NEW DESIGNS (EMERGING CONCEPT OF SYSTEM-ON-CHIP – SOCs ).

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SOC ARCHITECTURE WOULD INCLUDE A MIXED HARDWARESOFTWARE PROGRAMMABLE STYLE WHERE STANDARD SOFTWAREPROGRAMMABLE AREAS ARE AUGMENTED BY FPGA AND MEMORY.

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THE PARADIGM SHIFT FROM INTEGRATED DEVICE MAKER (IDM) TO “DE-VERTICALIZATION” WILL BESIDES FOUNDRIES INCLUDE SEMICONDUCTOR INTELLECTUAL PROPERTY (SIP) SUPPLIERS AND EMBEDDED SOLUTION PROVIDERS IN THE SUPPLY CHAIN OF FINAL SOCs.

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INTERESTING TIME BECAUSE WE ARE GOING TO WITNESS:       

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GATE DIELECTRIC MOVING TO EOT <1 nm i.e. ~5 ATOMS THICK SILICON DIOXIDE – POLYSILICON GETTING REPLACED BY HIGH K DIELECTRIC – METAL GATE STACK STRAINED SILICON/MIXED CRYSTAL ORIENTATION REPLACING SINGLE CRYSTAL SILICON NEW DEVICE STRUCTURES SUCH AS FINFET REPLACING CONVENTIONAL MOSFET 3-D INTEGRATION i.e. THIN DIES CONNECTED THORUGH SILICON VIAS IMPROVED SOC & SIP DESIGN 450/675 mm WAFERS USE OR 2X PRODUCTIVITY WITH 300mm WAFER WITH ADVANCED PRECISION MANUFACTURING END OF ERA OF SCALING

INTERESTING TIMES AHEAD INDEED  WHO WANTS IT ANY OTHER WAY

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LOGIC DESIGN

CIRCUIT DESIGN

LAYOUT DESIGN

MASK FABRICATION

TRANSISTOR DEVELOPMENT

DEVICE DEVELOPMENT

TEST & ASSY.

RELIABILITY

DEVELOPMENT OF ONSTITUENT PROCESS TECH.

EQIPMENT & PROCESS SIMULATORS DEVICE SIMULATOR CIRCUIT SIMULATOR, LAYOUT & VERIFICATION TOOLS LOGIC SIMULATOR PHYSICO-CHEMICAL MODEL NUMERICAL CALCULATION AND CALCULATION ALGORITHMS 7

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The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. For an enhancement mode, nchannel MOSFET the modes are: •

Cut-off or sub-threshold mode: When VGS < Vth where Vth is the threshold voltage of the device. The transistor is turned off, and there is no conduction between drain and source. While the current between drain and source should ideally be zero since the switch is turned off, there is a weak-inversion current, or subthreshold leakage.

•

Triode or linear region: When VGS > Vth and VDS < VGS − Vth The transistor is turned on, and a channel has been created which allows current to flow between the drain and source. The MOSFET operates like a resistor, controlled by the gate voltage.

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The current from drain to source is,

3.

where μn is the charge-carrier mobility, W is the gate width, L is the gate length and Cox is the capacitance per unit at the gate. Saturation: When VGS > Vth and VDS > VGS − Vth The switch is turned on, and a channel has been created which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, a portion of the channel is turned off. The onset of this region is also known as pinch-off. The drain current is now relatively independent of the drain voltage (in a first-order approximation) and the current is only controlled by the gate voltage such that,

this equation can be multiplied by (1 + λVDS) to take into account the channel length modulation (λ). In digital circuits MOSFETs are operated in cut-off and saturation mode. The triode mode is mainly used in analog circuit applications 11

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DEVELOPMENT OF CMOS LOGIC IS THE REASON FOR GREAT SUCCESS OF MOSFET

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IN CMOS LOGIC NO CURRENT IS ALLOWED TO FLOW (IDEALLY) AND THUS NO POWER TO BE CONSUMED EXCEPT WHEN THE INPUTS TO THE LOGIC GATES ARE BEING SWITCHED

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IN MOSFETs THE OXIDE LAYER BETWEEN THE GATE AND THE CHANNEL PREVENTS DC CURRENT FROM FLOWING THROUGH THE GATE, FURTHER REDUCING POWER CONSUMPTION AND GIVING A VERY LARGE INPUT IMPEDENCE. THIS ALSO ALLOWS HIGH FAN OUT CAPACITY.

VDD

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THRESHOLD VOLTAGE IS THE GATE VOLTAGE REQUIRED TO PRODUCE STRONG INVERSION LAYER BELOW THE GATE.

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THE THRESHOLD VOLTAGE CONSISTS OF SEVERAL COMPONENTS QB • A VOLTAGE (-2 ΦF- ------ ) COX TO CHANGE THE SURFACE POTENTIAL AND OFFSET THE IMMOBILE DEPLETION LAYER CHARGE QB. Cox IS THE CAPACITANCE PER UNIT AREA OF THE GATE OXIDE. • A VOLTAGE REPRESENTING THE DIFFERENCE IN THE WORK FUNCTION BETWEEN THE GATE MATERIALS AND THE CHANNEL MATERIAL: ΦGC = ΦF substrate – Φgate • ADDITIONAL CHARGE AT THE OXIDE – SEMICONDUCTOR INTERFACE DUE TO IMPURITIES ETC. – QOX/COX

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THEREFORE, THE THRESHOLD VOLTAGE IS GIVEN BY QB QOX VTH = ΦGC - 2 ΦF - ------- - ------COX COX 13

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THE THRESHOLD VOLTAGE AND CONSEQUENTLY THE DRAIN TO SOURCE ON-CURRENT IS DETERMINED BY THE WORK FUNCTION DIFFERENCE BETWEEN THE GATE MATERIAL AND CHANNEL MATERIAL.

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WHEN METAL WAS USED AS GATE MATERIAL, GATE VOLTAGES WERE LARGE (IN THE ORDER OF 3V TO 5V), THE HIGH THRESHOLD VOLTAGE COULD STILL BE OVERCOME BY THE APPLIED GATE VOLTAGE i.e. Vg- Vt > 0

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AS TRANSISTOR SIZES WERE SCALED DOWN, THE APPLIED SIGNAL VOLTAGES WERE ALSO BROUGHT DOWN – TO AVOID GATE OXIDE BREAKDOWN, HOT ELECTRON REDUCTION, POWER CONSUMPTION REDUCTION ETC. – A TRANSISTOR WITH A HIGH THRESHOLD VOLTAGE WOULD BECOME NON-OPERATIONAL UNDER THESE NEW CONDITIONS. THE POLYSILICON BECAME THE MODERN GATE MATERIAL BECAUSE THE WORK FUNCTION DIFFERENCE WITH SINGLE CRYSTAL SILICON IS CLOSE TO ZERO, MAKING THE THRESHOLD VOLTAGE LOWER AND ENSURING THE TRANSISTOR CAN BE TURNED ON.

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HOWEVER, POLYSILICON IS HIGHLY RESISTIVE MATERIAL (APPROXIMATELY 1000 TIME MORE REISTIVE THAN METALS) WHICH REDUCED THE SIGNAL PROPAGATION SPEED THROUGH THE MATERIAL.

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POLYSILICON IS ALSO SUITABLE FOR MODERN FABRICATION PROCESS WHEREIN GATE MATERIAL IS DEPOSITED PRIOR TO CERTAIN HIGH TEMPERATURE STEPS IN ORDER TO BETTER PERFORMING TRANSISTORS (SELF ALIGNED PROCESS)

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WHEN THE TRANSISTORS ARE EXTREMELY SCALED DOWN, IT IS NECESSARY TO MAKE THE GATE DIELECTRIC LAYER VERY THIN, AROUND 1NM IN STATE-OF-THE-ART TECHNOLOGIES. A PHENOMENON OBSERVED HERE IS THE SO-CALLED POLY DEPLETION, WHERE A DEPLETION LAYER IS FORMED IN THE GATE POLYSILICON LAYER NEXT TO THE GATE DIELECTRIC WHEN THE TRANSISTOR IS IN THE INVERSION. TO AVOID THIS PROBLEM A METAL GATE IS DESIRED. A VARIETY OF METAL GATES SUCH AS TANTALUM, TUNGSTEN, TANTALUM NITRIDE, AND TITANIUM NITRIDE, USUALLY IN CONJUNCTION WITH HIGH-K DIELECTRICS ARE BEING TRIED OUT. AN ALTERNATIVE IS TO USE FULLY-SILICIDED POLYSILICON GATES, AND THE PROSESS IS REFERED TO AS FUSI. FUSI 15

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SIMULATION PROGRAMME WITH INTEGRATED CIRCUIT EMPHASIS (SPICE) IS A NEUMERICAL PROGRAMME CONSTRUCTED TO SOLVE THE VOLTAGES AND CURRENTS OF A GIVEN CIRCUIT.

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CONSIDER THE SIMPLE 3 NODE CIRCUIT 1

2 RA

In

RB 3 RC

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ACCORDING TO KIRCHOFF’S CURRENT LAW (KCL) FOR NODE 2 V1-V2 V2-V3 W µn COX --------- - --------- - ---- --------------- (V3-VT)2 = 0 RA RB L 2

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HERE THE DRAIN CURRENT OF THE MOSFET IS MODELLED WITH THE WELL KNOWN SATURATION CURRENT: W µn COX IDS = --------------- (VGS – VT)2 L 2

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WHERE, W, L, un, COX AND VT ARE PAREMETERS WHICH ARE CALCULATED FROM SPICE MODELS – LEVEL 1,2,3 BSIM1, 2, 3,4, MODEL 9, EKV ETC.

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KCL STATEMENTS AT NODE 1,2 & 3 CAN BE WRITTEN AS • f1 (V1, V2, V3) = 0 • f2 (V1, V2, V3) = 0 • f3 (V1, V2, V3) = 0

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SPICE SIMULATOR SOLVES THESE THREE EQUAITONS OF THREE UNKNOWN BY THE NEWTON – RAPHSON ALGORITHM, 17

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ALLOWS MORE CURRENT TO PASS

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SMALLER GATE GIVES LOWER GATE CAPACITANCE WHICH LEADS TO LOWER SWITCHING TIME CONSEQUENTLY HIGHER PROCESSING SPEED.

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SMALLER MOSFETS CAN BE PACKED MORE DENSLY RESULTING IN EITHERE SMALLER CHIPS OR CHIPS WITH MORE COMPUTING POWER IN THE SAME AREA.

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SMALLER CHIPS – MORE ON A WAFER – LESS COST AS COST OF PROCESSING A WAFER IS RELATIVELY FIXED.

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GEOMETRIC PARAMETERS OF THE MOSFET ARE SCALED DOWN BY A DIMENSIONLESS FACTOR 1/K OTHER PARAMETERS ARE GENERALLY SCALED FOR CONSTANT ELECTRIC FIELD AS FOLLOWS.

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DEVICE FABRICATION IS ALWAYS A LIMITING FACTOR IN ADVANCING INTEGRTED CIRCUIT TECHNOLOGY

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SUBTHRESHOLD LEAKAGE – GATE VOLTAGE IS REDUCED TO MAINTAIN RELIABILITY – LEADS TO REDUCTION OF THRESHOLD VOLTAGE TO MAINTAIN PERFORMACNE – LEADS TO HIGHER LEAKAGE CURRENT - 50% OF

POWER

CONSUMPTION

IS

NOW-A-DAYS

ACCOUNTED

FOR

SUBSHTRESHOLD LEAKAGE.

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

THE EVER INCREASING DENSITY OF MOSFETS IN AN IC IS CREATING PROBLEMS OF SUBSTANTIAL LOCALIZED HEATING THAT CAN IMPAIR CIRCUIT OPERATION MAKING THOSE SLOW AND LESS RELIABILE. HEAT SINKS AND OTHER COOLING METHODS ARE NOW REQUIRED FOR MANY ICs INCLUDING MICROPROCESSORS.

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THE GATE OXIDE, WHICH SERVES AS INSULATOR BETWEEN THE GATE AND CHANNEL, SHOULD BE MADE AS THIN AS POSSIBLE TO INCREASE THE CHANNEL CONDUCTIVITY AND PERFORMANCE WHEN THE TRANSISTOR IS ON AND TO REDUCE SUBTHRESHOLD LEAKAGE WHEN THE TRANSISTOR IS OFF. HOWEVER, WITH CURRENT GATE OXIDES WITH A THICKNESS OF AROUND 1.2 NM (WHICH IS ~5 ATOMS THICK) THE PHENOMENON OF TUNNELING LEAKAGE OCCURS BETWEEN THE GATE AND CHANNEL, LEADING TO INCREASED POWER CONSUMPTION.

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INSULATORS (REFERRED TO AS HIGH-K DIELECTRICS) THAT HAVE A LARGER DIELECTRIC CONSTANT THAN SILICON DIOXIDE, SUCH AS GROUP IVB METAL SILICATES E.G. HAFNIUM AND ZIRCONIUM SILICATES AND OXIDES, ARE NOW BEING RESEARCHED TO REDUCE THE GATE LEAKAGE. INCREASING THE DIELECTRIC CONSTANT OF THE GATE OXIDE MATERIAL ALLOWS A THICKER LAYER WHILE MAINTAINING A HIGH CAPACITANCE. THE HIGHER THICKNESS REDUCES THE TUNNELING CURRENT BETWEEN THE GATE AND THE CHANNEL.

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PROCESS VARIATIONS: WITH MOSFET BECOMING SMALLER THE NUMBER OF ATOMS IN THE SILICON THAT PRODUCE MANY OF THE TRANSISTOR’S PROPERTIES IS BECOMING FEWER.

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DURING CHIP MANUFACTURING, RANDOM PROCESS VARIATION CAN AFFECT THE SIZE OF THE TRANSISTOR, WHICH BECOMES A GREATER PERCENTAGE OF THE OVERALL TRANSISTOR SIZE AS THE TRANSISTOR SHRINKS

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• • •

NO MORE TECHNOLOGY NODES 4X TRANSISTORS, 0.7X M1 HALFPITCH, CYCLE-3 YEARS TRADITIONAL FOR DRAM NEW PRODUCT WISE ROADMAP IN ITRS 2005

Year of Production

2005

2006

2007

2008

2009

2010

2011

2012

2013

DRAM half-pitch (nm) (contacted)

80

70

65

57

50

45

40

36

32

MPU/ASIC Metal 1 (M1) half-pitch (nm)

90

78

68

59

52

45

40

36

32

MPU printed gate length (nm)

54

48

42

38

34

30

27

24

21

MPU physical gate length (nm)

32

28

25

23

20

18

16

14

13

ASIC/low operating power printed gate length (nm)

76

64

54

48

42

38

34

30

27

ASIC/low operating poer physical gate length (nm)

45

38

32

28

25

23

20

18

16

Flash half-pitch (nm) (uncontacted poly)

76

64

57

51

45

40

36

32

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SOURCE: SEMICONDUCTOR INTERNATIONAL

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APPROACHING A “RED BRICK WALL” (Challenges/Opportunities for Semiconductor R&D)

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DESIGN TECHNOLOGY

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WITH PROCESS TECHNOLOGY LED PUSH IN MICROELECTRONICS, DESIGNER PRODUCTIVITY HAS AND CONTINUES TO BE BELOW THE SILICON OPPORTUNITY GROWTH.

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A NEW GENERATION OF EDA TOOLS ESSENTIAL FOR A NEW LEVEL OF ACCELERATION IN PRODUCTIVITY. 25

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DESIGN INNOVATION SUCH AS FUNCTION SPECIFIC DESIGN REQUIRED TO BRING FURTHER BREAKTHROUGH IN CHIP INDUSTRY

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DESIGN PRODUCTIVITY REQUIRES HIGHER LEVELS OF DESIGN • DESIGN RE-USE • HIGH-LEVEL SYNTHESIS • SYSTEM-LEVEL VERIFICATION • SPECIALIZED TOOLS OPERATING AT STRUCTURED LEVELS

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PRODUCT FUNCTIONALITY AND PERFORMANCE REQUIRE INTERACTING TOOLS REACHING FROM HIGH TO CIRCUIT LEVEL: • SYNTHESIS/VERIFICATION / TOGETHER • DYNAMIC LOGIC FAMILIES • CRITICAL TIMING BEHAVIOUR • INTERCONNECT-AWARE DESIGN • SOC WITH DIGITAL/ANALOG/MEMORY/SOFTWARE 26

VERTICAL REPLACEMENT GATE MOSFET COMBINES THE ADVANTAGES OF PREVIOUS VERTICAL MOSFETS WITH THE ESSENTIAL FEATURES OF PLANAR MOSFETS

LG LG

PLANAR MOSFET

VRG MOSFET 27

FINFET (BODY IS A THIN SILICON FIN) • •

Double gate structure + thin body Raised Source/Drain

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STRAINED SILICON ♦

STRAIN ENGINEERING INVOLVES STRAINING OF THE SILICON CRYSTAL TO INCREASE THE MOBILITY OF CHARGE CARRIERS IN THE CHANNEL

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IT ALSO REDUCES THE SOURCE/DRAIN SERIES RESISTANCE

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COMPRESSIVE STRAIN IS INDUCED IN PMOS TRANSISTORS TYPICALLY USING EPITAXIALLY GROWN SiGe SOURCE/DRAIN AND/OR COMPRESSIVELY STRAINED NITRIDE LAYER OVER THE GATE

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THE GREATEST EMPHSIS IS GIVEN TO THE PMOSFET, SINCE HOLE MOBILITY IS TYPICALLY THREE TIMES LESS THAN ELECTRON MOBILITY.

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IN NMOS TRANSISTOR, A TENSILE STRAINED NITRIDE LAYER IS USED.

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STRAINED SILICON ♦

SINCE ELECTRON MOVE FASTER THROUGH SILICON WITH A (100) ORIENTATION AND HOLES MOVE FSTER THROUGH SILICON WITH (110) ORIENTATION (THE ORIENTATION OF MOST SUBSTRATES), HYBRIDE ORIENTATION TECHNOLOGY (HOT) HAS DEVELOPED TO DRIVE CURRENT AND TO REDUCE THE GATE DELAYS IN SILICON BY 20%.

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BIAXIAL STRAIN OR GLOBAL STRAIN CAN ALSO BE USED WHERE ENTIRE WAFER IS STRAINED BY VARIOUS METHODS BUT IT HAS PROBLEM OF DEFECTIVITY AND INTEGRATION ISSUE SO IT CAN BE DELAYED UNTIL 32nm NODE OR LATER.

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UPCOMING NANOELECTRONICS NANOELECTRONICS

BIO-MOLECULAR ELECTRONICS

QUANTUM DOTS

QUANTUM EFFECT SOLID STATE ELECTRONICS

CARBON NANO-TUBE BASED ELECTRONICS

RESONANT TUNNELING DEVICES

RESONANT TUNNELING DIODES

SINGLE ELECTRON TRANSISTOR

RESONANT TUNNELING TRANSISTORS 31

SINGLE ELECTRON TRANSISTORS (SET)

THE SET TRANSISTOR CAN BE VIEWED AS AN ELECTRON BOX THAT HAS TWO SEPARATE JUNCTIONS FOR THE ENTRANCE AND EXIT OF SINGLE ELECTRONS. IT CAN ALSO BE VIEWED AS A FIELD-EFFECT TRANSISTOR IN WHICH THE CHANNEL IS REPLACED BY TWO TUNNEL JUNCTIONS FORMING A METALLIC ISLAND. THE VOLTAGE APPLIED TO THE GATE ELECTRODE AFFECTS THE AMOUNT OF ENERGY NEEDED TO CHANGE THE NUMBER OF ELECTRONS ON THE ISLAND.

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SINGLE ELECTRON TRANSISTORS (SET)

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QUANTUM DOT AN OBJECT WITH NANOMETER SCALE EXTENSION IN ALL THREE SPATIAL DIRECTIONS IS CALLED A QUANTUM DOT

 QUANTUM DOTS POSSESS ATOM-LIKE ENERGY STATES AND NO ELECTRONICS BAND STRUCTURE LIKE BULK SEMICONDUCTORS  EACH QD HAS ITS OWN CHARACTERISTICS, HENCE REFERRED AS ARTIFICIAL ATOM.  CHARACTERISTICS FROM QD CAN BE DEFINED DURING FABRICATION PROCESS

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CARBON NANOTUBE • CARBON NANOTUBES (CNT) ARE STRUCTURES OF CARBON, CONFIGURATIONALLY EQUIVALENT TO 2-D GRAPHITE SHEET ROLLED INTO A TUBE. • DIMENSIONALLY CNT ARE A FEW NANOMETERS IN DIAMETER BUT MAY BE SEVERAL MICRONS LONG. • CNT CAN BE METALLIC, SEMICONDUCTING OR INSULATOR THUS OFFERS AMAZING POSSIBILITIES TO CREATE FUTURE NANOELECTRONICS DEVICES • FIRST NOTICED BY SUMIO IJIMA OF NEC, JAPAN IN EARLY NINTIES. • THE ABILITY OF CNT TO ACT AS WIRES WAS FIRST SHOWN EXPERIMENTALLY IN 1997 BY CEES DEKKER, DELFT UNIV. OF TECHN. NETHERLAND. • IN 1998 DEKKER SHOWED A TRANSISTOR THAT USED A NANOTUBE AS ONE OF THE COMPONENTS. 35

CARBON NANOTUBE

•

IN A CNT TRANSISTOR, CHANNEL IS FORMED BY A CNT PLACED BETWEEN TWO CLOSELY SPACED GOLD/PLATINUM ELECTRODES PATTERNED ON A INSULATING LAYER GROWN ON SILICON SUBSTRATE.

•

APPLYING AN ELECTRIC FIELD TO THE SILICON TURNS ON AND OFF THE FLOW OF CURRENT THROUGH THE NANOTUBE. 36

MOLECULAR NANOELECTRONICS •

MOLECULAR NANOELECTRONICS IS ELECTRONICS BASED ON INDIVIDUAL MOLECULES, AT A SCALE OF NANOMETER

•

MOLECULES ARE IN NATURAL NANOMETER SCALE. INDIVIDUAL COVALENTLY BONDED MOLECULES ACT AS WIRES AND SWITCHING DEVICES.

Molecular electronics resonant tunneling Diode

•

METHYLENE GROUPS CREATE “BARRIERS” ALONG A MOLECULAR WIRE TO CONTROL TRANSMISSION OF ELECTRONS THROUGH A QUANTUM WELL. 37

NANOFABRICATION OF FUTURE INTEGRATED CIRCUITS •

IN THE FUTURE, HOW DO WE COST EFFECTIVELY MANUFACTURE “ALMOST ATOMICALLY-PERFECT” NANOELECTRONIC ICS? (BASED ON SILICON, NANOTUBES, OR WHATEVER).

•

NANO-TOOL ARRAYS? AFM LITHOGRAPHY?

•

DNA + ENZYMES? PROCESSING IN A LARGE BEAKER? DEFECT IMMUNITY AND/OR SELF REPAIR

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USE OF FinFET, HIGH K AND METAL GATES, SOI, 3D STRUCTURES WILL BE DELAYED, USE OF STRAINED SILICON WILL BE EMPHASISED IN COMING FEW YEARS.

•

EMPHASIS WILL SHIFT TO DESIGN INNOVATIONS AND DESIGN PRODUCTIVITY.

•

NEVER BEFORE HAVE WE FACED SUCH A COMBINATION OF TECHNICAL CHALLENGES AND OPPORTUNITIES.  KEEP MOS SCALING GOING TO ITS ULTIMATE LIMIT  TRANSITION FROM CONTINUUM TO ATOMIC UNDERSTANDING  INVENT NEW TECHNOLOGIES AT THE GRANULARITY OF MATTER TO SUSTAIN MOORE’S LAW BENEFITS TO SOCIETY.

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